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path: root/drivers/pci/hotplug/shpchp.h
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Diffstat (limited to 'drivers/pci/hotplug/shpchp.h')
-rw-r--r--drivers/pci/hotplug/shpchp.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h
index 37ed0884b972..f66e8d6315ab 100644
--- a/drivers/pci/hotplug/shpchp.h
+++ b/drivers/pci/hotplug/shpchp.h
@@ -234,7 +234,7 @@ static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
234 return slot; 234 return slot;
235 } 235 }
236 236
237 err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device); 237 err("%s: slot (device=0x%x) not found\n", __func__, device);
238 return NULL; 238 return NULL;
239} 239}
240 240
@@ -268,7 +268,7 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
268 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); 268 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
269 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; 269 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
270 if (perr_set) { 270 if (perr_set) {
271 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set); 271 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__func__ , perr_set);
272 272
273 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); 273 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
274 } 274 }
@@ -277,7 +277,7 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
277 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); 277 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
278 rse_set = pcix_mem_base_reg & RSE_MASK; 278 rse_set = pcix_mem_base_reg & RSE_MASK;
279 if (rse_set) { 279 if (rse_set) {
280 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ ); 280 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__func__ );
281 281
282 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); 282 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
283 } 283 }