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path: root/drivers/pci/hotplug/shpchp.h
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Diffstat (limited to 'drivers/pci/hotplug/shpchp.h')
-rw-r--r--drivers/pci/hotplug/shpchp.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h
index 0d48d38cbf41..6aba0b6cf2e0 100644
--- a/drivers/pci/hotplug/shpchp.h
+++ b/drivers/pci/hotplug/shpchp.h
@@ -253,7 +253,7 @@ static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
253 return slot; 253 return slot;
254 } 254 }
255 255
256 ctrl_err(ctrl, "%s: slot (device=0x%x) not found\n", __func__, device); 256 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
257 return NULL; 257 return NULL;
258} 258}
259 259
@@ -288,8 +288,8 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
288 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; 288 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
289 if (perr_set) { 289 if (perr_set) {
290 ctrl_dbg(p_slot->ctrl, 290 ctrl_dbg(p_slot->ctrl,
291 "%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n", 291 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
292 __func__ , perr_set); 292 perr_set);
293 293
294 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); 294 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
295 } 295 }
@@ -298,8 +298,7 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
298 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); 298 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
299 rse_set = pcix_mem_base_reg & RSE_MASK; 299 rse_set = pcix_mem_base_reg & RSE_MASK;
300 if (rse_set) { 300 if (rse_set) {
301 ctrl_dbg(p_slot->ctrl, "%s W1C: Memory_Base_Limit[ RSE ]\n", 301 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
302 __func__);
303 302
304 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); 303 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
305 } 304 }