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path: root/drivers/pci/hotplug/shpchp.h
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Diffstat (limited to 'drivers/pci/hotplug/shpchp.h')
-rw-r--r--drivers/pci/hotplug/shpchp.h22
1 files changed, 19 insertions, 3 deletions
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h
index 4d9fed00e1d0..6aba0b6cf2e0 100644
--- a/drivers/pci/hotplug/shpchp.h
+++ b/drivers/pci/hotplug/shpchp.h
@@ -59,6 +59,20 @@ extern struct workqueue_struct *shpchp_wq;
59#define warn(format, arg...) \ 59#define warn(format, arg...) \
60 printk(KERN_WARNING "%s: " format, MY_NAME , ## arg) 60 printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
61 61
62#define ctrl_dbg(ctrl, format, arg...) \
63 do { \
64 if (shpchp_debug) \
65 dev_printk(, &ctrl->pci_dev->dev, \
66 format, ## arg); \
67 } while (0)
68#define ctrl_err(ctrl, format, arg...) \
69 dev_err(&ctrl->pci_dev->dev, format, ## arg)
70#define ctrl_info(ctrl, format, arg...) \
71 dev_info(&ctrl->pci_dev->dev, format, ## arg)
72#define ctrl_warn(ctrl, format, arg...) \
73 dev_warn(&ctrl->pci_dev->dev, format, ## arg)
74
75
62#define SLOT_NAME_SIZE 10 76#define SLOT_NAME_SIZE 10
63struct slot { 77struct slot {
64 u8 bus; 78 u8 bus;
@@ -239,7 +253,7 @@ static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
239 return slot; 253 return slot;
240 } 254 }
241 255
242 err("%s: slot (device=0x%x) not found\n", __func__, device); 256 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
243 return NULL; 257 return NULL;
244} 258}
245 259
@@ -273,7 +287,9 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
273 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); 287 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
274 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; 288 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
275 if (perr_set) { 289 if (perr_set) {
276 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__func__ , perr_set); 290 ctrl_dbg(p_slot->ctrl,
291 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
292 perr_set);
277 293
278 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); 294 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
279 } 295 }
@@ -282,7 +298,7 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
282 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); 298 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
283 rse_set = pcix_mem_base_reg & RSE_MASK; 299 rse_set = pcix_mem_base_reg & RSE_MASK;
284 if (rse_set) { 300 if (rse_set) {
285 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__func__ ); 301 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
286 302
287 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); 303 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
288 } 304 }