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path: root/drivers/pci/hotplug/pciehprm_nonacpi.c
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Diffstat (limited to 'drivers/pci/hotplug/pciehprm_nonacpi.c')
-rw-r--r--drivers/pci/hotplug/pciehprm_nonacpi.c107
1 files changed, 4 insertions, 103 deletions
diff --git a/drivers/pci/hotplug/pciehprm_nonacpi.c b/drivers/pci/hotplug/pciehprm_nonacpi.c
index ed68c3dd0f08..32371cd19e34 100644
--- a/drivers/pci/hotplug/pciehprm_nonacpi.c
+++ b/drivers/pci/hotplug/pciehprm_nonacpi.c
@@ -37,15 +37,9 @@
37#include <linux/slab.h> 37#include <linux/slab.h>
38#include <asm/uaccess.h> 38#include <asm/uaccess.h>
39#include "pciehp.h" 39#include "pciehp.h"
40#include "pciehprm.h"
41#include "pciehprm_nonacpi.h" 40#include "pciehprm_nonacpi.h"
42 41
43 42
44void pciehprm_cleanup(void)
45{
46 return;
47}
48
49int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum) 43int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
50{ 44{
51 45
@@ -53,106 +47,13 @@ int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busn
53 return 0; 47 return 0;
54} 48}
55 49
56int pciehprm_set_hpp( 50void get_hp_params_from_firmware(struct pci_dev *dev,
57 struct controller *ctrl, 51 struct hotplug_params *hpp)
58 struct pci_func *func,
59 u8 card_type)
60{
61 u32 rc;
62 u8 temp_byte;
63 struct pci_bus lpci_bus, *pci_bus;
64 unsigned int devfn;
65 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
66 pci_bus = &lpci_bus;
67 pci_bus->number = func->bus;
68 devfn = PCI_DEVFN(func->device, func->function);
69
70 temp_byte = 0x40; /* hard coded value for LT */
71 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
72 /* set subordinate Latency Timer */
73 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
74
75 if (rc) {
76 dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__,
77 func->bus, func->device, func->function);
78 return rc;
79 }
80 }
81
82 /* set base Latency Timer */
83 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
84
85 if (rc) {
86 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
87 return rc;
88 }
89
90 /* set Cache Line size */
91 temp_byte = 0x08; /* hard coded value for CLS */
92
93 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
94
95 if (rc) {
96 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
97 }
98
99 /* set enable_perr */
100 /* set enable_serr */
101
102 return rc;
103}
104
105void pciehprm_enable_card(
106 struct controller *ctrl,
107 struct pci_func *func,
108 u8 card_type)
109{ 52{
110 u16 command, bcommand; 53 return;
111 struct pci_bus lpci_bus, *pci_bus;
112 unsigned int devfn;
113 int rc;
114
115 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
116 pci_bus = &lpci_bus;
117 pci_bus->number = func->bus;
118 devfn = PCI_DEVFN(func->device, func->function);
119
120 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
121
122 command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
123 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
124 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
125
126 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
127
128 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
129
130 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
131
132 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
133 | PCI_BRIDGE_CTL_NO_ISA;
134
135 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
136 }
137} 54}
138 55
139static int legacy_pciehprm_init_pci(void) 56int get_hp_hw_control_from_firmware(struct pci_dev *dev)
140{ 57{
141 return 0; 58 return 0;
142} 59}
143
144int pciehprm_init(enum php_ctlr_type ctrl_type)
145{
146 int retval;
147
148 switch (ctrl_type) {
149 case PCI:
150 retval = legacy_pciehprm_init_pci();
151 break;
152 default:
153 retval = -ENODEV;
154 break;
155 }
156
157 return retval;
158}