diff options
Diffstat (limited to 'drivers/pci/hotplug/pciehp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/pciehp_hpc.c | 43 |
1 files changed, 17 insertions, 26 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 58c72d2cc217..b643ca13e4f1 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c | |||
@@ -316,22 +316,19 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
316 | * proceed forward to issue the next command according | 316 | * proceed forward to issue the next command according |
317 | * to spec. Just print out the error message. | 317 | * to spec. Just print out the error message. |
318 | */ | 318 | */ |
319 | ctrl_dbg(ctrl, | 319 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
320 | "%s: CMD_COMPLETED not clear after 1 sec.\n", | ||
321 | __func__); | ||
322 | } else if (!NO_CMD_CMPL(ctrl)) { | 320 | } else if (!NO_CMD_CMPL(ctrl)) { |
323 | /* | 321 | /* |
324 | * This controller semms to notify of command completed | 322 | * This controller semms to notify of command completed |
325 | * event even though it supports none of power | 323 | * event even though it supports none of power |
326 | * controller, attention led, power led and EMI. | 324 | * controller, attention led, power led and EMI. |
327 | */ | 325 | */ |
328 | ctrl_dbg(ctrl, "%s: Unexpected CMD_COMPLETED. Need to " | 326 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
329 | "wait for command completed event.\n", | 327 | "wait for command completed event.\n"); |
330 | __func__); | ||
331 | ctrl->no_cmd_complete = 0; | 328 | ctrl->no_cmd_complete = 0; |
332 | } else { | 329 | } else { |
333 | ctrl_dbg(ctrl, "%s: Unexpected CMD_COMPLETED. Maybe " | 330 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
334 | "the controller is broken.\n", __func__); | 331 | "the controller is broken.\n"); |
335 | } | 332 | } |
336 | } | 333 | } |
337 | 334 | ||
@@ -347,8 +344,7 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
347 | smp_mb(); | 344 | smp_mb(); |
348 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); | 345 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); |
349 | if (retval) | 346 | if (retval) |
350 | ctrl_err(ctrl, "%s: Cannot write to SLOTCTRL register\n", | 347 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
351 | __func__); | ||
352 | 348 | ||
353 | /* | 349 | /* |
354 | * Wait for command completion. | 350 | * Wait for command completion. |
@@ -418,15 +414,14 @@ static int hpc_check_lnk_status(struct controller *ctrl) | |||
418 | 414 | ||
419 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); | 415 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
420 | if (retval) { | 416 | if (retval) { |
421 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", | 417 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
422 | __func__); | ||
423 | return retval; | 418 | return retval; |
424 | } | 419 | } |
425 | 420 | ||
426 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | 421 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
427 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || | 422 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
428 | !(lnk_status & NEG_LINK_WD)) { | 423 | !(lnk_status & NEG_LINK_WD)) { |
429 | ctrl_err(ctrl, "%s : Link Training Error occurs \n", __func__); | 424 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
430 | retval = -1; | 425 | retval = -1; |
431 | return retval; | 426 | return retval; |
432 | } | 427 | } |
@@ -551,7 +546,7 @@ static int hpc_query_power_fault(struct slot *slot) | |||
551 | 546 | ||
552 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 547 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
553 | if (retval) { | 548 | if (retval) { |
554 | ctrl_err(ctrl, "%s: Cannot check for power fault\n", __func__); | 549 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
555 | return retval; | 550 | return retval; |
556 | } | 551 | } |
557 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | 552 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); |
@@ -567,7 +562,7 @@ static int hpc_get_emi_status(struct slot *slot, u8 *status) | |||
567 | 562 | ||
568 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 563 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
569 | if (retval) { | 564 | if (retval) { |
570 | ctrl_err(ctrl, "%s : Cannot check EMI status\n", __func__); | 565 | ctrl_err(ctrl, "Cannot check EMI status\n"); |
571 | return retval; | 566 | return retval; |
572 | } | 567 | } |
573 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | 568 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; |
@@ -697,8 +692,7 @@ static int hpc_power_on_slot(struct slot * slot) | |||
697 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 692 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
698 | 693 | ||
699 | if (retval) { | 694 | if (retval) { |
700 | ctrl_err(ctrl, "%s: Write %x command failed!\n", | 695 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
701 | __func__, slot_cmd); | ||
702 | return -1; | 696 | return -1; |
703 | } | 697 | } |
704 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", | 698 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
@@ -776,7 +770,7 @@ static int hpc_power_off_slot(struct slot * slot) | |||
776 | 770 | ||
777 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 771 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
778 | if (retval) { | 772 | if (retval) { |
779 | ctrl_err(ctrl, "%s: Write command failed!\n", __func__); | 773 | ctrl_err(ctrl, "Write command failed!\n"); |
780 | retval = -1; | 774 | retval = -1; |
781 | goto out; | 775 | goto out; |
782 | } | 776 | } |
@@ -1056,8 +1050,7 @@ int pcie_enable_notification(struct controller *ctrl) | |||
1056 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; | 1050 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; |
1057 | 1051 | ||
1058 | if (pcie_write_cmd(ctrl, cmd, mask)) { | 1052 | if (pcie_write_cmd(ctrl, cmd, mask)) { |
1059 | ctrl_err(ctrl, "%s: Cannot enable software notification\n", | 1053 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
1060 | __func__); | ||
1061 | return -1; | 1054 | return -1; |
1062 | } | 1055 | } |
1063 | return 0; | 1056 | return 0; |
@@ -1069,8 +1062,7 @@ static void pcie_disable_notification(struct controller *ctrl) | |||
1069 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | | 1062 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | |
1070 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; | 1063 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; |
1071 | if (pcie_write_cmd(ctrl, 0, mask)) | 1064 | if (pcie_write_cmd(ctrl, 0, mask)) |
1072 | ctrl_warn(ctrl, "%s: Cannot disable software notification\n", | 1065 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
1073 | __func__); | ||
1074 | } | 1066 | } |
1075 | 1067 | ||
1076 | static int pcie_init_notification(struct controller *ctrl) | 1068 | static int pcie_init_notification(struct controller *ctrl) |
@@ -1179,7 +1171,7 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
1179 | 1171 | ||
1180 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); | 1172 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
1181 | if (!ctrl) { | 1173 | if (!ctrl) { |
1182 | dev_err(&dev->device, "%s : out of memory\n", __func__); | 1174 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
1183 | goto abort; | 1175 | goto abort; |
1184 | } | 1176 | } |
1185 | INIT_LIST_HEAD(&ctrl->slot_list); | 1177 | INIT_LIST_HEAD(&ctrl->slot_list); |
@@ -1188,12 +1180,11 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
1188 | ctrl->pci_dev = pdev; | 1180 | ctrl->pci_dev = pdev; |
1189 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | 1181 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
1190 | if (!ctrl->cap_base) { | 1182 | if (!ctrl->cap_base) { |
1191 | ctrl_err(ctrl, "%s: Cannot find PCI Express capability\n", | 1183 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
1192 | __func__); | ||
1193 | goto abort_ctrl; | 1184 | goto abort_ctrl; |
1194 | } | 1185 | } |
1195 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { | 1186 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { |
1196 | ctrl_err(ctrl, "%s: Cannot read SLOTCAP register\n", __func__); | 1187 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
1197 | goto abort_ctrl; | 1188 | goto abort_ctrl; |
1198 | } | 1189 | } |
1199 | 1190 | ||