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path: root/drivers/pci/hotplug/pciehp_hpc.c
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Diffstat (limited to 'drivers/pci/hotplug/pciehp_hpc.c')
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 6692832c9c81..81a177a5f032 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -280,6 +280,14 @@ int pciehp_check_link_status(struct controller *ctrl)
280 else 280 else
281 msleep(1000); 281 msleep(1000);
282 282
283 /*
284 * Need to wait for 1000 ms after Data Link Layer Link Active
285 * (DLLLA) bit reads 1b before sending configuration request.
286 * We need it before checking Link Training (LT) bit becuase
287 * LT is still set even after DLLLA bit is set on some platform.
288 */
289 msleep(1000);
290
283 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
284 if (retval) { 292 if (retval) {
285 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); 293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");