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path: root/drivers/pci/dmar.c
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-rw-r--r--drivers/pci/dmar.c56
1 files changed, 56 insertions, 0 deletions
diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c
index b64cec190542..0f409e23631e 100644
--- a/drivers/pci/dmar.c
+++ b/drivers/pci/dmar.c
@@ -645,6 +645,62 @@ void qi_global_iec(struct intel_iommu *iommu)
645 qi_submit_sync(&desc, iommu); 645 qi_submit_sync(&desc, iommu);
646} 646}
647 647
648int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
649 u64 type, int non_present_entry_flush)
650{
651
652 struct qi_desc desc;
653
654 if (non_present_entry_flush) {
655 if (!cap_caching_mode(iommu->cap))
656 return 1;
657 else
658 did = 0;
659 }
660
661 desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
662 | QI_CC_GRAN(type) | QI_CC_TYPE;
663 desc.high = 0;
664
665 qi_submit_sync(&desc, iommu);
666
667 return 0;
668
669}
670
671int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
672 unsigned int size_order, u64 type,
673 int non_present_entry_flush)
674{
675 u8 dw = 0, dr = 0;
676
677 struct qi_desc desc;
678 int ih = 0;
679
680 if (non_present_entry_flush) {
681 if (!cap_caching_mode(iommu->cap))
682 return 1;
683 else
684 did = 0;
685 }
686
687 if (cap_write_drain(iommu->cap))
688 dw = 1;
689
690 if (cap_read_drain(iommu->cap))
691 dr = 1;
692
693 desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
694 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
695 desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
696 | QI_IOTLB_AM(size_order);
697
698 qi_submit_sync(&desc, iommu);
699
700 return 0;
701
702}
703
648/* 704/*
649 * Enable Queued Invalidation interface. This is a must to support 705 * Enable Queued Invalidation interface. This is a must to support
650 * interrupt-remapping. Also used by DMA-remapping, which replaces 706 * interrupt-remapping. Also used by DMA-remapping, which replaces