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path: root/drivers/ntb/ntb_regs.h
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Diffstat (limited to 'drivers/ntb/ntb_regs.h')
-rw-r--r--drivers/ntb/ntb_regs.h31
1 files changed, 23 insertions, 8 deletions
diff --git a/drivers/ntb/ntb_regs.h b/drivers/ntb/ntb_regs.h
index 07872057c76e..f028ff81fd77 100644
--- a/drivers/ntb/ntb_regs.h
+++ b/drivers/ntb/ntb_regs.h
@@ -57,6 +57,7 @@
57#define SNB_MAX_DB_BITS 15 57#define SNB_MAX_DB_BITS 15
58#define SNB_LINK_DB 15 58#define SNB_LINK_DB 15
59#define SNB_DB_BITS_PER_VEC 5 59#define SNB_DB_BITS_PER_VEC 5
60#define HSX_SPLITBAR_MAX_MW 3
60#define SNB_MAX_MW 2 61#define SNB_MAX_MW 2
61#define SNB_ERRATA_MAX_MW 1 62#define SNB_ERRATA_MAX_MW 1
62 63
@@ -72,15 +73,20 @@
72 73
73#define SNB_PBAR2LMT_OFFSET 0x0000 74#define SNB_PBAR2LMT_OFFSET 0x0000
74#define SNB_PBAR4LMT_OFFSET 0x0008 75#define SNB_PBAR4LMT_OFFSET 0x0008
76#define SNB_PBAR5LMT_OFFSET 0x000C
75#define SNB_PBAR2XLAT_OFFSET 0x0010 77#define SNB_PBAR2XLAT_OFFSET 0x0010
76#define SNB_PBAR4XLAT_OFFSET 0x0018 78#define SNB_PBAR4XLAT_OFFSET 0x0018
79#define SNB_PBAR5XLAT_OFFSET 0x001C
77#define SNB_SBAR2LMT_OFFSET 0x0020 80#define SNB_SBAR2LMT_OFFSET 0x0020
78#define SNB_SBAR4LMT_OFFSET 0x0028 81#define SNB_SBAR4LMT_OFFSET 0x0028
82#define SNB_SBAR5LMT_OFFSET 0x002C
79#define SNB_SBAR2XLAT_OFFSET 0x0030 83#define SNB_SBAR2XLAT_OFFSET 0x0030
80#define SNB_SBAR4XLAT_OFFSET 0x0038 84#define SNB_SBAR4XLAT_OFFSET 0x0038
85#define SNB_SBAR5XLAT_OFFSET 0x003C
81#define SNB_SBAR0BASE_OFFSET 0x0040 86#define SNB_SBAR0BASE_OFFSET 0x0040
82#define SNB_SBAR2BASE_OFFSET 0x0048 87#define SNB_SBAR2BASE_OFFSET 0x0048
83#define SNB_SBAR4BASE_OFFSET 0x0050 88#define SNB_SBAR4BASE_OFFSET 0x0050
89#define SNB_SBAR5BASE_OFFSET 0x0054
84#define SNB_NTBCNTL_OFFSET 0x0058 90#define SNB_NTBCNTL_OFFSET 0x0058
85#define SNB_SBDF_OFFSET 0x005C 91#define SNB_SBDF_OFFSET 0x005C
86#define SNB_PDOORBELL_OFFSET 0x0060 92#define SNB_PDOORBELL_OFFSET 0x0060
@@ -96,12 +102,18 @@
96#define SNB_B2B_XLAT_OFFSETL 0x0144 102#define SNB_B2B_XLAT_OFFSETL 0x0144
97#define SNB_B2B_XLAT_OFFSETU 0x0148 103#define SNB_B2B_XLAT_OFFSETU 0x0148
98 104
99#define SNB_MBAR01_USD_ADDR 0x000000210000000CULL 105/*
100#define SNB_MBAR23_USD_ADDR 0x000000410000000CULL 106 * The addresses are setup so the 32bit BARs can function. Thus
101#define SNB_MBAR45_USD_ADDR 0x000000810000000CULL 107 * the addresses are all in 32bit space
102#define SNB_MBAR01_DSD_ADDR 0x000000200000000CULL 108 */
103#define SNB_MBAR23_DSD_ADDR 0x000000400000000CULL 109#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL
104#define SNB_MBAR45_DSD_ADDR 0x000000800000000CULL 110#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL
111#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL
112#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL
113#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL
114#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL
115#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL
116#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL
105 117
106#define BWD_MSIX_CNT 34 118#define BWD_MSIX_CNT 34
107#define BWD_MAX_SPADS 16 119#define BWD_MAX_SPADS 16
@@ -150,13 +162,16 @@
150#define NTB_CNTL_LINK_DISABLE (1 << 1) 162#define NTB_CNTL_LINK_DISABLE (1 << 1)
151#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) 163#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
152#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) 164#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
153#define NTB_CNTL_S2P_BAR45_SNOOP (1 << 6) 165#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
154#define NTB_CNTL_P2S_BAR45_SNOOP (1 << 8) 166#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
167#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
168#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
155#define BWD_CNTL_LINK_DOWN (1 << 16) 169#define BWD_CNTL_LINK_DOWN (1 << 16)
156 170
157#define NTB_PPD_OFFSET 0x00D4 171#define NTB_PPD_OFFSET 0x00D4
158#define SNB_PPD_CONN_TYPE 0x0003 172#define SNB_PPD_CONN_TYPE 0x0003
159#define SNB_PPD_DEV_TYPE 0x0010 173#define SNB_PPD_DEV_TYPE 0x0010
174#define SNB_PPD_SPLIT_BAR (1 << 6)
160#define BWD_PPD_INIT_LINK 0x0008 175#define BWD_PPD_INIT_LINK 0x0008
161#define BWD_PPD_CONN_TYPE 0x0300 176#define BWD_PPD_CONN_TYPE 0x0300
162#define BWD_PPD_DEV_TYPE 0x1000 177#define BWD_PPD_DEV_TYPE 0x1000