165 files changed, 10711 insertions, 2874 deletions

diff --git a/drivers/net/3c501.c b/drivers/net/3c501.c
index 11d170afa9c3..06e33786078d 100644
--- a/drivers/net/3c501.c
+++ b/drivers/net/3c501.c
@@ -922,7 +922,7 @@ int __init init_module(void)
  * and then free up the resources we took when the card was found.
  */
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         struct net_device *dev = dev_3c501;
         unregister_netdev(dev);
diff --git a/drivers/net/3c503.c b/drivers/net/3c503.c
index a34b2206132d..7e34c4f07b70 100644
--- a/drivers/net/3c503.c
+++ b/drivers/net/3c503.c
@@ -726,7 +726,7 @@ static void cleanup_card(struct net_device *dev)
                 iounmap(ei_status.mem);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/3c505.c b/drivers/net/3c505.c
index 458cb9cbe915..702bfb2a5e99 100644
--- a/drivers/net/3c505.c
+++ b/drivers/net/3c505.c
@@ -1670,7 +1670,7 @@ int __init init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/3c507.c b/drivers/net/3c507.c
index aa43563610ae..54e1d5aebed3 100644
--- a/drivers/net/3c507.c
+++ b/drivers/net/3c507.c
@@ -940,7 +940,7 @@ int __init init_module(void)
         return IS_ERR(dev_3c507) ? PTR_ERR(dev_3c507) : 0;
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         struct net_device *dev = dev_3c507;
diff --git a/drivers/net/3c523.c b/drivers/net/3c523.c
index 91849469b4f4..17d61eb0a7e5 100644
--- a/drivers/net/3c523.c
+++ b/drivers/net/3c523.c
@@ -1302,7 +1302,7 @@ int __init init_module(void)
         } else return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
         for (this_dev=0; this_dev<MAX_3C523_CARDS; this_dev++) {
diff --git a/drivers/net/3c527.c b/drivers/net/3c527.c
index f4aca5386add..6c7437e60bd2 100644
--- a/drivers/net/3c527.c
+++ b/drivers/net/3c527.c
@@ -1659,7 +1659,7 @@ int __init init_module(void)
  *      transmit operations are allowed to start scribbling into memory.
  */
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(this_device);
         cleanup_card(this_device);
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index d02ed51abfcc..931028f672de 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -594,7 +594,7 @@ struct rtl8139_private {
         u32 rx_config;
         struct rtl_extra_stats xstats;
 
-        struct work_struct thread;
+        struct delayed_work thread;
 
         struct mii_if_info mii;
         unsigned int regs_len;
@@ -636,8 +636,8 @@ static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
 static void rtl8139_set_rx_mode (struct net_device *dev);
 static void __set_rx_mode (struct net_device *dev);
 static void rtl8139_hw_start (struct net_device *dev);
-static void rtl8139_thread (void *_data);
-static void rtl8139_tx_timeout_task(void *_data);
+static void rtl8139_thread (struct work_struct *work);
+static void rtl8139_tx_timeout_task(struct work_struct *work);
 static const struct ethtool_ops rtl8139_ethtool_ops;
 
 /* write MMIO register, with flush */
@@ -1010,7 +1010,7 @@ static int __devinit rtl8139_init_one (struct pci_dev *pdev,
                 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
         spin_lock_init (&tp->lock);
         spin_lock_init (&tp->rx_lock);
-        INIT_WORK(&tp->thread, rtl8139_thread, dev);
+        INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
         tp->mii.dev = dev;
         tp->mii.mdio_read = mdio_read;
         tp->mii.mdio_write = mdio_write;
@@ -1596,15 +1596,16 @@ static inline void rtl8139_thread_iter (struct net_device *dev,
                  RTL_R8 (Config1));
 }
 
-static void rtl8139_thread (void *_data)
+static void rtl8139_thread (struct work_struct *work)
 {
-        struct net_device *dev = _data;
-        struct rtl8139_private *tp = netdev_priv(dev);
+        struct rtl8139_private *tp =
+                container_of(work, struct rtl8139_private, thread.work);
+        struct net_device *dev = tp->mii.dev;
         unsigned long thr_delay = next_tick;
 
         if (tp->watchdog_fired) {
                 tp->watchdog_fired = 0;
-                rtl8139_tx_timeout_task(_data);
+                rtl8139_tx_timeout_task(work);
         } else if (rtnl_trylock()) {
                 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
                 rtnl_unlock ();
@@ -1646,10 +1647,11 @@ static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
         /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
 }
 
-static void rtl8139_tx_timeout_task (void *_data)
+static void rtl8139_tx_timeout_task (struct work_struct *work)
 {
-        struct net_device *dev = _data;
-        struct rtl8139_private *tp = netdev_priv(dev);
+        struct rtl8139_private *tp =
+                container_of(work, struct rtl8139_private, thread.work);
+        struct net_device *dev = tp->mii.dev;
         void __iomem *ioaddr = tp->mmio_addr;
         int i;
         u8 tmp8;
@@ -1695,7 +1697,7 @@ static void rtl8139_tx_timeout (struct net_device *dev)
         struct rtl8139_private *tp = netdev_priv(dev);
 
         if (!tp->have_thread) {
-                INIT_WORK(&tp->thread, rtl8139_tx_timeout_task, dev);
+                INIT_DELAYED_WORK(&tp->thread, rtl8139_tx_timeout_task);
                 schedule_delayed_work(&tp->thread, next_tick);
         } else
                 tp->watchdog_fired = 1;
diff --git a/drivers/net/Space.c b/drivers/net/Space.c
index a67f5efc983f..602ed31a5dd9 100644
--- a/drivers/net/Space.c
+++ b/drivers/net/Space.c
@@ -33,7 +33,6 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/netlink.h>
-#include <linux/divert.h>
 
 /* A unified ethernet device probe.  This is the easiest way to have every
    ethernet adaptor have the name "eth[0123...]".
diff --git a/drivers/net/ac3200.c b/drivers/net/ac3200.c
index 0dca8bb9d2c7..c01f87f5bed7 100644
--- a/drivers/net/ac3200.c
+++ b/drivers/net/ac3200.c
@@ -405,7 +405,7 @@ static void cleanup_card(struct net_device *dev)
         iounmap(ei_status.mem);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/apne.c b/drivers/net/apne.c
index 9164d8cd670e..d4e408169073 100644
--- a/drivers/net/apne.c
+++ b/drivers/net/apne.c
@@ -568,7 +568,7 @@ static irqreturn_t apne_interrupt(int irq, void *dev_id)
 #ifdef MODULE
 static struct net_device *apne_dev;
 
-int init_module(void)
+int __init init_module(void)
 {
         apne_dev = apne_probe(-1);
         if (IS_ERR(apne_dev))
@@ -576,7 +576,7 @@ int init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(apne_dev);
 
diff --git a/drivers/net/appletalk/cops.c b/drivers/net/appletalk/cops.c
index cc1a27ed197f..dba5e5165452 100644
--- a/drivers/net/appletalk/cops.c
+++ b/drivers/net/appletalk/cops.c
@@ -1041,7 +1041,7 @@ int __init init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(cops_dev);
         cleanup_card(cops_dev);
diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c
index b54b857e357e..fada15d959de 100644
--- a/drivers/net/arm/at91_ether.c
+++ b/drivers/net/arm/at91_ether.c
@@ -41,9 +41,6 @@
 #define DRV_NAME        "at91_ether"
 #define DRV_VERSION     "1.0"
 
-static struct net_device *at91_dev;
-
-static struct timer_list check_timer;
 #define LINK_POLL_INTERVAL      (HZ)
 
 /* ..................................................................... */
@@ -146,7 +143,7 @@ static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int
  */
 static void update_linkspeed(struct net_device *dev, int silent)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned int bmsr, bmcr, lpa, mac_cfg;
         unsigned int speed, duplex;
 
@@ -199,7 +196,7 @@ static void update_linkspeed(struct net_device *dev, int silent)
 static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
 {
         struct net_device *dev = (struct net_device *) dev_id;
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned int phy;
 
         /*
@@ -242,7 +239,7 @@ done:
  */
 static void enable_phyirq(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned int dsintr, irq_number;
         int status;
 
@@ -252,8 +249,7 @@ static void enable_phyirq(struct net_device *dev)
                  * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
                  * or board does not have it connected.
                  */
-                check_timer.expires = jiffies + LINK_POLL_INTERVAL;
-                add_timer(&check_timer);
+                mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
                 return;
         }
 
@@ -294,13 +290,13 @@ static void enable_phyirq(struct net_device *dev)
  */
 static void disable_phyirq(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned int dsintr;
         unsigned int irq_number;
 
         irq_number = lp->board_data.phy_irq_pin;
         if (!irq_number) {
-                del_timer_sync(&check_timer);
+                del_timer_sync(&lp->check_timer);
                 return;
         }
 
@@ -340,7 +336,7 @@ static void disable_phyirq(struct net_device *dev)
 #if 0
 static void reset_phy(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned int bmcr;
 
         spin_lock_irq(&lp->lock);
@@ -362,13 +358,13 @@ static void reset_phy(struct net_device *dev)
 static void at91ether_check_link(unsigned long dev_id)
 {
         struct net_device *dev = (struct net_device *) dev_id;
+        struct at91_private *lp = netdev_priv(dev);
 
         enable_mdi();
         update_linkspeed(dev, 1);
         disable_mdi();
 
-        check_timer.expires = jiffies + LINK_POLL_INTERVAL;
-        add_timer(&check_timer);
+        mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
 }
 
 /* ......................... ADDRESS MANAGEMENT ........................ */
@@ -590,7 +586,7 @@ static void mdio_write(struct net_device *dev, int phy_id, int location, int val
 
 static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         int ret;
 
         spin_lock_irq(&lp->lock);
@@ -611,7 +607,7 @@ static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cm
 
 static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         int ret;
 
         spin_lock_irq(&lp->lock);
@@ -627,7 +623,7 @@ static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cm
 
 static int at91ether_nwayreset(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         int ret;
 
         spin_lock_irq(&lp->lock);
@@ -658,7 +654,7 @@ static const struct ethtool_ops at91ether_ethtool_ops = {
 
 static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         int res;
 
         if (!netif_running(dev))
@@ -680,7 +676,7 @@ static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  */
 static void at91ether_start(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         struct recv_desc_bufs *dlist, *dlist_phys;
         int i;
         unsigned long ctl;
@@ -712,7 +708,7 @@ static void at91ether_start(struct net_device *dev)
  */
 static int at91ether_open(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned long ctl;
 
         if (!is_valid_ether_addr(dev->dev_addr))
@@ -752,7 +748,7 @@ static int at91ether_open(struct net_device *dev)
  */
 static int at91ether_close(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned long ctl;
 
         /* Disable Receiver and Transmitter */
@@ -779,7 +775,7 @@ static int at91ether_close(struct net_device *dev)
  */
 static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
 
         if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
                 netif_stop_queue(dev);
@@ -811,7 +807,7 @@ static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
  */
 static struct net_device_stats *at91ether_stats(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         int ale, lenerr, seqe, lcol, ecol;
 
         if (netif_running(dev)) {
@@ -847,7 +843,7 @@ static struct net_device_stats *at91ether_stats(struct net_device *dev)
  */
 static void at91ether_rx(struct net_device *dev)
 {
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         struct recv_desc_bufs *dlist;
         unsigned char *p_recv;
         struct sk_buff *skb;
@@ -857,14 +853,13 @@ static void at91ether_rx(struct net_device *dev)
         while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
                 p_recv = dlist->recv_buf[lp->rxBuffIndex];
                 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff;      /* Length of frame including FCS */
-                skb = alloc_skb(pktlen + 2, GFP_ATOMIC);
+                skb = dev_alloc_skb(pktlen + 2);
                 if (skb != NULL) {
                         skb_reserve(skb, 2);
                         memcpy(skb_put(skb, pktlen), p_recv, pktlen);
 
                         skb->dev = dev;
                         skb->protocol = eth_type_trans(skb, dev);
-                        skb->len = pktlen;
                         dev->last_rx = jiffies;
                         lp->stats.rx_bytes += pktlen;
                         netif_rx(skb);
@@ -891,7 +886,7 @@ static void at91ether_rx(struct net_device *dev)
 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
 {
         struct net_device *dev = (struct net_device *) dev_id;
-        struct at91_private *lp = (struct at91_private *) dev->priv;
+        struct at91_private *lp = netdev_priv(dev);
         unsigned long intstatus, ctl;
 
         /* MAC Interrupt Status register indicates what interrupts are pending.
@@ -927,6 +922,17 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void at91ether_poll_controller(struct net_device *dev)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        at91ether_interrupt(dev->irq, dev);
+        local_irq_restore(flags);
+}
+#endif
+
 /*
  * Initialize the ethernet interface
  */
@@ -939,9 +945,6 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
         unsigned int val;
         int res;
 
-        if (at91_dev)                   /* already initialized */
-                return 0;
-
         dev = alloc_etherdev(sizeof(struct at91_private));
         if (!dev)
                 return -ENOMEM;
@@ -957,7 +960,7 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
         }
 
         /* Allocate memory for DMA Receive descriptors */
-        lp = (struct at91_private *)dev->priv;
+        lp = netdev_priv(dev);
         lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
         if (lp->dlist == NULL) {
                 free_irq(dev->irq, dev);
@@ -979,6 +982,9 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
         dev->set_mac_address = set_mac_address;
         dev->ethtool_ops = &at91ether_ethtool_ops;
         dev->do_ioctl = at91ether_ioctl;
+#ifdef CONFIG_NET_POLL_CONTROLLER
+        dev->poll_controller = at91ether_poll_controller;
+#endif
 
         SET_NETDEV_DEV(dev, &pdev->dev);
 
@@ -1024,7 +1030,6 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
                 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
                 return res;
         }
-        at91_dev = dev;
 
         /* Determine current link speed */
         spin_lock_irq(&lp->lock);
@@ -1036,9 +1041,9 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
 
         /* If board has no PHY IRQ, use a timer to poll the PHY */
         if (!lp->board_data.phy_irq_pin) {
-                init_timer(&check_timer);
-                check_timer.data = (unsigned long)dev;
-                check_timer.function = at91ether_check_link;
+                init_timer(&lp->check_timer);
+                lp->check_timer.data = (unsigned long)dev;
+                lp->check_timer.function = at91ether_check_link;
         }
 
         /* Display ethernet banner */
@@ -1115,15 +1120,16 @@ static int __init at91ether_probe(struct platform_device *pdev)
 
 static int __devexit at91ether_remove(struct platform_device *pdev)
 {
-        struct at91_private *lp = (struct at91_private *) at91_dev->priv;
+        struct net_device *dev = platform_get_drvdata(pdev);
+        struct at91_private *lp = netdev_priv(dev);
 
-        unregister_netdev(at91_dev);
-        free_irq(at91_dev->irq, at91_dev);
+        unregister_netdev(dev);
+        free_irq(dev->irq, dev);
         dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
         clk_put(lp->ether_clk);
 
-        free_netdev(at91_dev);
-        at91_dev = NULL;
+        platform_set_drvdata(pdev, NULL);
+        free_netdev(dev);
         return 0;
 }
 
@@ -1131,8 +1137,8 @@ static int __devexit at91ether_remove(struct platform_device *pdev)
 
 static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
 {
-        struct at91_private *lp = (struct at91_private *) at91_dev->priv;
         struct net_device *net_dev = platform_get_drvdata(pdev);
+        struct at91_private *lp = netdev_priv(net_dev);
         int phy_irq = lp->board_data.phy_irq_pin;
 
         if (netif_running(net_dev)) {
@@ -1149,8 +1155,8 @@ static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
 
 static int at91ether_resume(struct platform_device *pdev)
 {
-        struct at91_private *lp = (struct at91_private *) at91_dev->priv;
         struct net_device *net_dev = platform_get_drvdata(pdev);
+        struct at91_private *lp = netdev_priv(net_dev);
         int phy_irq = lp->board_data.phy_irq_pin;
 
         if (netif_running(net_dev)) {
diff --git a/drivers/net/arm/at91_ether.h b/drivers/net/arm/at91_ether.h
index d1e72e02be3a..b6b665de2ea0 100644
--- a/drivers/net/arm/at91_ether.h
+++ b/drivers/net/arm/at91_ether.h
@@ -87,6 +87,7 @@ struct at91_private
         spinlock_t lock;                        /* lock for MDI interface */
         short phy_media;                        /* media interface type */
         unsigned short phy_address;             /* 5-bit MDI address of PHY (0..31) */
+        struct timer_list check_timer;          /* Poll link status */
 
         /* Transmit */
         struct sk_buff *skb;                    /* holds skb until xmit interrupt completes */
diff --git a/drivers/net/arm/ether1.c b/drivers/net/arm/ether1.c
index f3478a30e778..d6da3ce9ad79 100644
--- a/drivers/net/arm/ether1.c
+++ b/drivers/net/arm/ether1.c
@@ -254,7 +254,7 @@ ether1_readbuffer (struct net_device *dev, void *data, unsigned int start, unsig
         } while (thislen);
 }
 
-static int __init
+static int __devinit
 ether1_ramtest(struct net_device *dev, unsigned char byte)
 {
         unsigned char *buffer = kmalloc (BUFFER_SIZE, GFP_KERNEL);
@@ -308,7 +308,7 @@ ether1_reset (struct net_device *dev)
         return BUS_16;
 }
 
-static int __init
+static int __devinit
 ether1_init_2(struct net_device *dev)
 {
         int i;
@@ -986,7 +986,7 @@ ether1_setmulticastlist (struct net_device *dev)
 
 /* ------------------------------------------------------------------------- */
 
-static void __init ether1_banner(void)
+static void __devinit ether1_banner(void)
 {
         static unsigned int version_printed = 0;
 
diff --git a/drivers/net/arm/ether3.c b/drivers/net/arm/ether3.c
index 84686c8a5bc2..4fc234785d56 100644
--- a/drivers/net/arm/ether3.c
+++ b/drivers/net/arm/ether3.c
@@ -198,7 +198,7 @@ static inline void ether3_ledon(struct net_device *dev)
  * Read the ethernet address string from the on board rom.
  * This is an ascii string!!!
  */
-static int __init
+static int __devinit
 ether3_addr(char *addr, struct expansion_card *ec)
 {
         struct in_chunk_dir cd;
@@ -223,7 +223,7 @@ ether3_addr(char *addr, struct expansion_card *ec)
 
 /* --------------------------------------------------------------------------- */
 
-static int __init
+static int __devinit
 ether3_ramtest(struct net_device *dev, unsigned char byte)
 {
         unsigned char *buffer = kmalloc(RX_END, GFP_KERNEL);
@@ -272,7 +272,7 @@ ether3_ramtest(struct net_device *dev, unsigned char byte)
 
 /* ------------------------------------------------------------------------------- */
 
-static int __init ether3_init_2(struct net_device *dev)
+static int __devinit ether3_init_2(struct net_device *dev)
 {
         int i;
 
@@ -765,7 +765,7 @@ static void ether3_tx(struct net_device *dev)
         }
 }
 
-static void __init ether3_banner(void)
+static void __devinit ether3_banner(void)
 {
         static unsigned version_printed = 0;
 
diff --git a/drivers/net/at1700.c b/drivers/net/at1700.c
index 8620a5b470f5..56ae8babd919 100644
--- a/drivers/net/at1700.c
+++ b/drivers/net/at1700.c
@@ -908,7 +908,7 @@ int __init init_module(void)
         return 0;
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         unregister_netdev(dev_at1700);
diff --git a/drivers/net/atarilance.c b/drivers/net/atarilance.c
index d79489e46249..7e37ac86a69a 100644
--- a/drivers/net/atarilance.c
+++ b/drivers/net/atarilance.c
@@ -1179,7 +1179,7 @@ static int lance_set_mac_address( struct net_device *dev, void *addr )
 #ifdef MODULE
 static struct net_device *atarilance_dev;
 
-int init_module(void)
+int __init init_module(void)
 {
         atarilance_dev = atarilance_probe(-1);
         if (IS_ERR(atarilance_dev))
@@ -1187,7 +1187,7 @@ int init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(atarilance_dev);
         free_irq(atarilance_dev->irq, atarilance_dev);
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 01b76d3aa42f..5bacb7587df4 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -53,11 +53,12 @@
 
 #include "bnx2.h"
 #include "bnx2_fw.h"
+#include "bnx2_fw2.h"
 
 #define DRV_MODULE_NAME         "bnx2"
 #define PFX DRV_MODULE_NAME     ": "
-#define DRV_MODULE_VERSION      "1.4.45"
-#define DRV_MODULE_RELDATE      "September 29, 2006"
+#define DRV_MODULE_VERSION      "1.5.1"
+#define DRV_MODULE_RELDATE      "November 15, 2006"
 
 #define RUN_AT(x) (jiffies + (x))
 
@@ -85,6 +86,7 @@ typedef enum {
         NC370F,
         BCM5708,
         BCM5708S,
+        BCM5709,
 } board_t;
 
 /* indexed by board_t, above */
@@ -98,6 +100,7 @@ static const struct {
         { "HP NC370F Multifunction Gigabit Server Adapter" },
         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
+        { "Broadcom NetXtreme II BCM5709 1000Base-T" },
         };
 
 static struct pci_device_id bnx2_pci_tbl[] = {
@@ -115,6 +118,8 @@ static struct pci_device_id bnx2_pci_tbl[] = {
           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
+        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
+          PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
         { 0, }
 };
 
@@ -236,8 +241,23 @@ static void
 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 {
         offset += cid_addr;
-        REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
-        REG_WR(bp, BNX2_CTX_DATA, val);
+        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+                int i;
+
+                REG_WR(bp, BNX2_CTX_CTX_DATA, val);
+                REG_WR(bp, BNX2_CTX_CTX_CTRL,
+                       offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
+                for (i = 0; i < 5; i++) {
+                        u32 val;
+                        val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
+                        if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
+                                break;
+                        udelay(5);
+                }
+        } else {
+                REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
+                REG_WR(bp, BNX2_CTX_DATA, val);
+        }
 }
 
 static int
@@ -403,6 +423,14 @@ bnx2_free_mem(struct bnx2 *bp)
 {
         int i;
 
+        for (i = 0; i < bp->ctx_pages; i++) {
+                if (bp->ctx_blk[i]) {
+                        pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
+                                            bp->ctx_blk[i],
+                                            bp->ctx_blk_mapping[i]);
+                        bp->ctx_blk[i] = NULL;
+                }
+        }
         if (bp->status_blk) {
                 pci_free_consistent(bp->pdev, bp->status_stats_size,
                                     bp->status_blk, bp->status_blk_mapping);
@@ -481,6 +509,18 @@ bnx2_alloc_mem(struct bnx2 *bp)
 
         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 
+        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+                bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
+                if (bp->ctx_pages == 0)
+                        bp->ctx_pages = 1;
+                for (i = 0; i < bp->ctx_pages; i++) {
+                        bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
+                                                BCM_PAGE_SIZE,
+                                                &bp->ctx_blk_mapping[i]);
+                        if (bp->ctx_blk[i] == NULL)
+                                goto alloc_mem_err;
+                }
+        }
         return 0;
 
 alloc_mem_err:
@@ -803,13 +843,13 @@ bnx2_set_mac_link(struct bnx2 *bp)
 
         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
-                BNX2_EMAC_MODE_25G);
+                BNX2_EMAC_MODE_25G_MODE);
 
         if (bp->link_up) {
                 switch (bp->line_speed) {
                         case SPEED_10:
-                                if (CHIP_NUM(bp) == CHIP_NUM_5708) {
-                                        val |= BNX2_EMAC_MODE_PORT_MII_10;
+                                if (CHIP_NUM(bp) != CHIP_NUM_5706) {
+                                        val |= BNX2_EMAC_MODE_PORT_MII_10M;
                                         break;
                                 }
                                 /* fall through */
@@ -817,7 +857,7 @@ bnx2_set_mac_link(struct bnx2 *bp)
                                 val |= BNX2_EMAC_MODE_PORT_MII;
                                 break;
                         case SPEED_2500:
-                                val |= BNX2_EMAC_MODE_25G;
+                                val |= BNX2_EMAC_MODE_25G_MODE;
                                 /* fall through */
                         case SPEED_1000:
                                 val |= BNX2_EMAC_MODE_PORT_GMII;
@@ -860,7 +900,7 @@ bnx2_set_link(struct bnx2 *bp)
         u32 bmsr;
         u8 link_up;
 
-        if (bp->loopback == MAC_LOOPBACK) {
+        if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
                 bp->link_up = 1;
                 return 0;
         }
@@ -902,6 +942,7 @@ bnx2_set_link(struct bnx2 *bp)
                         u32 bmcr;
 
                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
+                        bmcr &= ~BCM5708S_BMCR_FORCE_2500;
                         if (!(bmcr & BMCR_ANENABLE)) {
                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
                                         BMCR_ANENABLE);
@@ -988,7 +1029,21 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
                 u32 new_bmcr;
                 int force_link_down = 0;
 
-                if (CHIP_NUM(bp) == CHIP_NUM_5708) {
+                bnx2_read_phy(bp, MII_ADVERTISE, &adv);
+                adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
+
+                bnx2_read_phy(bp, MII_BMCR, &bmcr);
+                new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500);
+                new_bmcr |= BMCR_SPEED1000;
+                if (bp->req_line_speed == SPEED_2500) {
+                        new_bmcr |= BCM5708S_BMCR_FORCE_2500;
+                        bnx2_read_phy(bp, BCM5708S_UP1, &up1);
+                        if (!(up1 & BCM5708S_UP1_2G5)) {
+                                up1 |= BCM5708S_UP1_2G5;
+                                bnx2_write_phy(bp, BCM5708S_UP1, up1);
+                                force_link_down = 1;
+                        }
+                } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
                         if (up1 & BCM5708S_UP1_2G5) {
                                 up1 &= ~BCM5708S_UP1_2G5;
@@ -997,12 +1052,6 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
                         }
                 }
 
-                bnx2_read_phy(bp, MII_ADVERTISE, &adv);
-                adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
-
-                bnx2_read_phy(bp, MII_BMCR, &bmcr);
-                new_bmcr = bmcr & ~BMCR_ANENABLE;
-                new_bmcr |= BMCR_SPEED1000;
                 if (bp->req_duplex == DUPLEX_FULL) {
                         adv |= ADVERTISE_1000XFULL;
                         new_bmcr |= BMCR_FULLDPLX;
@@ -1023,6 +1072,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
                                 bp->link_up = 0;
                                 netif_carrier_off(bp->dev);
                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
+                                bnx2_report_link(bp);
                         }
                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
@@ -1048,30 +1098,26 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
                 /* Force a link down visible on the other side */
                 if (bp->link_up) {
-                        int i;
-
                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
-                        for (i = 0; i < 110; i++) {
-                                udelay(100);
-                        }
+                        spin_unlock_bh(&bp->phy_lock);
+                        msleep(20);
+                        spin_lock_bh(&bp->phy_lock);
                 }
 
                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
                         BMCR_ANENABLE);
-                if (CHIP_NUM(bp) == CHIP_NUM_5706) {
-                        /* Speed up link-up time when the link partner
-                         * does not autonegotiate which is very common
-                         * in blade servers. Some blade servers use
-                         * IPMI for kerboard input and it's important
-                         * to minimize link disruptions. Autoneg. involves
-                         * exchanging base pages plus 3 next pages and
-                         * normally completes in about 120 msec.
-                         */
-                        bp->current_interval = SERDES_AN_TIMEOUT;
-                        bp->serdes_an_pending = 1;
-                        mod_timer(&bp->timer, jiffies + bp->current_interval);
-                }
+                /* Speed up link-up time when the link partner
+                 * does not autonegotiate which is very common
+                 * in blade servers. Some blade servers use
+                 * IPMI for kerboard input and it's important
+                 * to minimize link disruptions. Autoneg. involves
+                 * exchanging base pages plus 3 next pages and
+                 * normally completes in about 120 msec.
+                 */
+                bp->current_interval = SERDES_AN_TIMEOUT;
+                bp->serdes_an_pending = 1;
+                mod_timer(&bp->timer, jiffies + bp->current_interval);
         }
 
         return 0;
@@ -1153,7 +1199,6 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
         }
         if (new_bmcr != bmcr) {
                 u32 bmsr;
-                int i = 0;
 
                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
@@ -1161,12 +1206,12 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
                 if (bmsr & BMSR_LSTATUS) {
                         /* Force link down */
                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
-                        do {
-                                udelay(100);
-                                bnx2_read_phy(bp, MII_BMSR, &bmsr);
-                                bnx2_read_phy(bp, MII_BMSR, &bmsr);
-                                i++;
-                        } while ((bmsr & BMSR_LSTATUS) && (i < 620));
+                        spin_unlock_bh(&bp->phy_lock);
+                        msleep(50);
+                        spin_lock_bh(&bp->phy_lock);
+
+                        bnx2_read_phy(bp, MII_BMSR, &bmsr);
+                        bnx2_read_phy(bp, MII_BMSR, &bmsr);
                 }
 
                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
@@ -1258,9 +1303,8 @@ bnx2_init_5706s_phy(struct bnx2 *bp)
 {
         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 
-        if (CHIP_NUM(bp) == CHIP_NUM_5706) {
-                REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
-        }
+        if (CHIP_NUM(bp) == CHIP_NUM_5706)
+                REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
 
         if (bp->dev->mtu > 1500) {
                 u32 val;
@@ -1397,13 +1441,13 @@ bnx2_set_phy_loopback(struct bnx2 *bp)
         for (i = 0; i < 10; i++) {
                 if (bnx2_test_link(bp) == 0)
                         break;
-                udelay(10);
+                msleep(100);
         }
 
         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
-                      BNX2_EMAC_MODE_25G);
+                      BNX2_EMAC_MODE_25G_MODE);
 
         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
@@ -1454,6 +1498,40 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
         return 0;
 }
 
+static int
+bnx2_init_5709_context(struct bnx2 *bp)
+{
+        int i, ret = 0;
+        u32 val;
+
+        val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
+        val |= (BCM_PAGE_BITS - 8) << 16;
+        REG_WR(bp, BNX2_CTX_COMMAND, val);
+        for (i = 0; i < bp->ctx_pages; i++) {
+                int j;
+
+                REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
+                       (bp->ctx_blk_mapping[i] & 0xffffffff) |
+                       BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
+                REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
+                       (u64) bp->ctx_blk_mapping[i] >> 32);
+                REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
+                       BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
+                for (j = 0; j < 10; j++) {
+
+                        val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
+                        if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
+                                break;
+                        udelay(5);
+                }
+                if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
+                        ret = -EBUSY;
+                        break;
+                }
+        }
+        return ret;
+}
+
 static void
 bnx2_init_context(struct bnx2 *bp)
 {
@@ -1576,9 +1654,8 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
                 return -ENOMEM;
         }
 
-        if (unlikely((align = (unsigned long) skb->data & 0x7))) {
-                skb_reserve(skb, 8 - align);
-        }
+        if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
+                skb_reserve(skb, BNX2_RX_ALIGN - align);
 
         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
                 PCI_DMA_FROMDEVICE);
@@ -2040,7 +2117,8 @@ bnx2_set_rx_mode(struct net_device *dev)
         if (dev->flags & IFF_PROMISC) {
                 /* Promiscuous mode. */
                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
-                sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
+                sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
+                             BNX2_RPM_SORT_USER0_PROM_VLAN;
         }
         else if (dev->flags & IFF_ALLMULTI) {
                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
@@ -2208,11 +2286,12 @@ load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
         }
 }
 
-static void
+static int
 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
 {
         u32 offset;
         u32 val;
+        int rc;
 
         /* Halt the CPU. */
         val = REG_RD_IND(bp, cpu_reg->mode);
@@ -2222,7 +2301,18 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
 
         /* Load the Text area. */
         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
-        if (fw->text) {
+        if (fw->gz_text) {
+                u32 text_len;
+                void *text;
+
+                rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text,
+                                 &text_len);
+                if (rc)
+                        return rc;
+
+                fw->text = text;
+        }
+        if (fw->gz_text) {
                 int j;
 
                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
@@ -2280,13 +2370,15 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
         val &= ~cpu_reg->mode_value_halt;
         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
         REG_WR_IND(bp, cpu_reg->mode, val);
+
+        return 0;
 }
 
 static int
 bnx2_init_cpus(struct bnx2 *bp)
 {
         struct cpu_reg cpu_reg;
-        struct fw_info fw;
+        struct fw_info *fw;
         int rc = 0;
         void *text;
         u32 text_len;
@@ -2323,44 +2415,15 @@ bnx2_init_cpus(struct bnx2 *bp)
         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
         cpu_reg.mips_view_base = 0x8000000;
 
-        fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
-        fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
-        fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
-        fw.start_addr = bnx2_RXP_b06FwStartAddr;
-
-        fw.text_addr = bnx2_RXP_b06FwTextAddr;
-        fw.text_len = bnx2_RXP_b06FwTextLen;
-        fw.text_index = 0;
+        if (CHIP_NUM(bp) == CHIP_NUM_5709)
+                fw = &bnx2_rxp_fw_09;
+        else
+                fw = &bnx2_rxp_fw_06;
 
-        rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText),
-                         &text, &text_len);
+        rc = load_cpu_fw(bp, &cpu_reg, fw);
         if (rc)
                 goto init_cpu_err;
 
-        fw.text = text;
-
-        fw.data_addr = bnx2_RXP_b06FwDataAddr;
-        fw.data_len = bnx2_RXP_b06FwDataLen;
-        fw.data_index = 0;
-        fw.data = bnx2_RXP_b06FwData;
-
-        fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
-        fw.sbss_len = bnx2_RXP_b06FwSbssLen;
-        fw.sbss_index = 0;
-        fw.sbss = bnx2_RXP_b06FwSbss;
-
-        fw.bss_addr = bnx2_RXP_b06FwBssAddr;
-        fw.bss_len = bnx2_RXP_b06FwBssLen;
-        fw.bss_index = 0;
-        fw.bss = bnx2_RXP_b06FwBss;
-
-        fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
-        fw.rodata_len = bnx2_RXP_b06FwRodataLen;
-        fw.rodata_index = 0;
-        fw.rodata = bnx2_RXP_b06FwRodata;
-
-        load_cpu_fw(bp, &cpu_reg, &fw);
-
         /* Initialize the TX Processor. */
         cpu_reg.mode = BNX2_TXP_CPU_MODE;
         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
@@ -2375,44 +2438,15 @@ bnx2_init_cpus(struct bnx2 *bp)
         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
         cpu_reg.mips_view_base = 0x8000000;
 
-        fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
-        fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
-        fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
-        fw.start_addr = bnx2_TXP_b06FwStartAddr;
-
-        fw.text_addr = bnx2_TXP_b06FwTextAddr;
-        fw.text_len = bnx2_TXP_b06FwTextLen;
-        fw.text_index = 0;
+        if (CHIP_NUM(bp) == CHIP_NUM_5709)
+                fw = &bnx2_txp_fw_09;
+        else
+                fw = &bnx2_txp_fw_06;
 
-        rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText),
-                         &text, &text_len);
+        rc = load_cpu_fw(bp, &cpu_reg, fw);
         if (rc)
                 goto init_cpu_err;
 
-        fw.text = text;
-
-        fw.data_addr = bnx2_TXP_b06FwDataAddr;
-        fw.data_len = bnx2_TXP_b06FwDataLen;
-        fw.data_index = 0;
-        fw.data = bnx2_TXP_b06FwData;
-
-        fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
-        fw.sbss_len = bnx2_TXP_b06FwSbssLen;
-        fw.sbss_index = 0;
-        fw.sbss = bnx2_TXP_b06FwSbss;
-
-        fw.bss_addr = bnx2_TXP_b06FwBssAddr;
-        fw.bss_len = bnx2_TXP_b06FwBssLen;
-        fw.bss_index = 0;
-        fw.bss = bnx2_TXP_b06FwBss;
-
-        fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
-        fw.rodata_len = bnx2_TXP_b06FwRodataLen;
-        fw.rodata_index = 0;
-        fw.rodata = bnx2_TXP_b06FwRodata;
-
-        load_cpu_fw(bp, &cpu_reg, &fw);
-
         /* Initialize the TX Patch-up Processor. */
         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
@@ -2427,44 +2461,15 @@ bnx2_init_cpus(struct bnx2 *bp)
         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
         cpu_reg.mips_view_base = 0x8000000;
 
-        fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
-        fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
-        fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
-        fw.start_addr = bnx2_TPAT_b06FwStartAddr;
-
-        fw.text_addr = bnx2_TPAT_b06FwTextAddr;
-        fw.text_len = bnx2_TPAT_b06FwTextLen;
-        fw.text_index = 0;
+        if (CHIP_NUM(bp) == CHIP_NUM_5709)
+                fw = &bnx2_tpat_fw_09;
+        else
+                fw = &bnx2_tpat_fw_06;
 
-        rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText),
-                         &text, &text_len);
+        rc = load_cpu_fw(bp, &cpu_reg, fw);
         if (rc)
                 goto init_cpu_err;
 
-        fw.text = text;
-
-        fw.data_addr = bnx2_TPAT_b06FwDataAddr;
-        fw.data_len = bnx2_TPAT_b06FwDataLen;
-        fw.data_index = 0;
-        fw.data = bnx2_TPAT_b06FwData;
-
-        fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
-        fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
-        fw.sbss_index = 0;
-        fw.sbss = bnx2_TPAT_b06FwSbss;
-
-        fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
-        fw.bss_len = bnx2_TPAT_b06FwBssLen;
-        fw.bss_index = 0;
-        fw.bss = bnx2_TPAT_b06FwBss;
-
-        fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
-        fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
-        fw.rodata_index = 0;
-        fw.rodata = bnx2_TPAT_b06FwRodata;
-
-        load_cpu_fw(bp, &cpu_reg, &fw);
-
         /* Initialize the Completion Processor. */
         cpu_reg.mode = BNX2_COM_CPU_MODE;
         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
@@ -2479,44 +2484,36 @@ bnx2_init_cpus(struct bnx2 *bp)
         cpu_reg.spad_base = BNX2_COM_SCRATCH;
         cpu_reg.mips_view_base = 0x8000000;
 
-        fw.ver_major = bnx2_COM_b06FwReleaseMajor;
-        fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
-        fw.ver_fix = bnx2_COM_b06FwReleaseFix;
-        fw.start_addr = bnx2_COM_b06FwStartAddr;
-
-        fw.text_addr = bnx2_COM_b06FwTextAddr;
-        fw.text_len = bnx2_COM_b06FwTextLen;
-        fw.text_index = 0;
+        if (CHIP_NUM(bp) == CHIP_NUM_5709)
+                fw = &bnx2_com_fw_09;
+        else
+                fw = &bnx2_com_fw_06;
 
-        rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText),
-                         &text, &text_len);
+        rc = load_cpu_fw(bp, &cpu_reg, fw);
         if (rc)
                 goto init_cpu_err;
 
-        fw.text = text;
-
-        fw.data_addr = bnx2_COM_b06FwDataAddr;
-        fw.data_len = bnx2_COM_b06FwDataLen;
-        fw.data_index = 0;
-        fw.data = bnx2_COM_b06FwData;
-
-        fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
-        fw.sbss_len = bnx2_COM_b06FwSbssLen;
-        fw.sbss_index = 0;
-        fw.sbss = bnx2_COM_b06FwSbss;
-
-        fw.bss_addr = bnx2_COM_b06FwBssAddr;
-        fw.bss_len = bnx2_COM_b06FwBssLen;
-        fw.bss_index = 0;
-        fw.bss = bnx2_COM_b06FwBss;
-
-        fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
-        fw.rodata_len = bnx2_COM_b06FwRodataLen;
-        fw.rodata_index = 0;
-        fw.rodata = bnx2_COM_b06FwRodata;
+        /* Initialize the Command Processor. */
+        cpu_reg.mode = BNX2_CP_CPU_MODE;
+        cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
+        cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
+        cpu_reg.state = BNX2_CP_CPU_STATE;
+        cpu_reg.state_value_clear = 0xffffff;
+        cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
+        cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
+        cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
+        cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
+        cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
+        cpu_reg.spad_base = BNX2_CP_SCRATCH;
+        cpu_reg.mips_view_base = 0x8000000;
 
-        load_cpu_fw(bp, &cpu_reg, &fw);
+        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+                fw = &bnx2_cp_fw_09;
 
+                load_cpu_fw(bp, &cpu_reg, fw);
+                if (rc)
+                        goto init_cpu_err;
+        }
 init_cpu_err:
         bnx2_gunzip_end(bp);
         return rc;
@@ -3288,31 +3285,44 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
          * before we issue a reset. */
         val = REG_RD(bp, BNX2_MISC_ID);
 
-        val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
-              BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
-              BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
+        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+                REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
+                REG_RD(bp, BNX2_MISC_COMMAND);
+                udelay(5);
 
-        /* Chip reset. */
-        REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
+                val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
+                      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
 
-        if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
-            (CHIP_ID(bp) == CHIP_ID_5706_A1))
-                msleep(15);
+                pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
 
-        /* Reset takes approximate 30 usec */
-        for (i = 0; i < 10; i++) {
-                val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
-                if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
-                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
-                        break;
+        } else {
+                val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
+                      BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
+                      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
+
+                /* Chip reset. */
+                REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
+
+                if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
+                    (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
+                        current->state = TASK_UNINTERRUPTIBLE;
+                        schedule_timeout(HZ / 50);
                 }
-                udelay(10);
-        }
 
-        if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
-                   BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
-                printk(KERN_ERR PFX "Chip reset did not complete\n");
-                return -EBUSY;
+                /* Reset takes approximate 30 usec */
+                for (i = 0; i < 10; i++) {
+                        val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
+                        if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
+                                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
+                                break;
+                        udelay(10);
+                }
+
+                if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
+                           BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
+                        printk(KERN_ERR PFX "Chip reset did not complete\n");
+                        return -EBUSY;
+                }
         }
 
         /* Make sure byte swapping is properly configured. */
@@ -3390,7 +3400,10 @@ bnx2_init_chip(struct bnx2 *bp)
 
         /* Initialize context mapping and zero out the quick contexts.  The
          * context block must have already been enabled. */
-        bnx2_init_context(bp);
+        if (CHIP_NUM(bp) == CHIP_NUM_5709)
+                bnx2_init_5709_context(bp);
+        else
+                bnx2_init_context(bp);
 
         if ((rc = bnx2_init_cpus(bp)) != 0)
                 return rc;
@@ -3501,12 +3514,40 @@ bnx2_init_chip(struct bnx2 *bp)
         return rc;
 }
 
+static void
+bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
+{
+        u32 val, offset0, offset1, offset2, offset3;
+
+        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+                offset0 = BNX2_L2CTX_TYPE_XI;
+                offset1 = BNX2_L2CTX_CMD_TYPE_XI;
+                offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
+                offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
+        } else {
+                offset0 = BNX2_L2CTX_TYPE;
+                offset1 = BNX2_L2CTX_CMD_TYPE;
+                offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
+                offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
+        }
+        val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
+        CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
+
+        val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
+        CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
+
+        val = (u64) bp->tx_desc_mapping >> 32;
+        CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
+
+        val = (u64) bp->tx_desc_mapping & 0xffffffff;
+        CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
+}
 
 static void
 bnx2_init_tx_ring(struct bnx2 *bp)
 {
         struct tx_bd *txbd;
-        u32 val;
+        u32 cid;
 
         bp->tx_wake_thresh = bp->tx_ring_size / 2;
 
@@ -3520,19 +3561,11 @@ bnx2_init_tx_ring(struct bnx2 *bp)
         bp->hw_tx_cons = 0;
         bp->tx_prod_bseq = 0;
 
-        val = BNX2_L2CTX_TYPE_TYPE_L2;
-        val |= BNX2_L2CTX_TYPE_SIZE_L2;
-        CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
+        cid = TX_CID;
+        bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
+        bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
 
-        val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
-        val |= 8 << 16;
-        CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
-
-        val = (u64) bp->tx_desc_mapping >> 32;
-        CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
-
-        val = (u64) bp->tx_desc_mapping & 0xffffffff;
-        CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
+        bnx2_init_tx_context(bp, cid);
 }
 
 static void
@@ -3545,8 +3578,8 @@ bnx2_init_rx_ring(struct bnx2 *bp)
 
         /* 8 for CRC and VLAN */
         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
-        /* 8 for alignment */
-        bp->rx_buf_size = bp->rx_buf_use_size + 8;
+        /* hw alignment */
+        bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
 
         ring_prod = prod = bp->rx_prod = 0;
         bp->rx_cons = 0;
@@ -3712,7 +3745,9 @@ bnx2_init_nic(struct bnx2 *bp)
         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
                 return rc;
 
+        spin_lock_bh(&bp->phy_lock);
         bnx2_init_phy(bp);
+        spin_unlock_bh(&bp->phy_lock);
         bnx2_set_link(bp);
         return 0;
 }
@@ -3952,7 +3987,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
                 bnx2_set_mac_loopback(bp);
         }
         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
-                bp->loopback = 0;
+                bp->loopback = PHY_LOOPBACK;
                 bnx2_set_phy_loopback(bp);
         }
         else
@@ -3992,8 +4027,8 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
         bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
         bp->tx_prod_bseq += pkt_size;
 
-        REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
-        REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
+        REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
+        REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
 
         udelay(100);
 
@@ -4162,80 +4197,117 @@ bnx2_test_intr(struct bnx2 *bp)
 }
 
 static void
-bnx2_timer(unsigned long data)
+bnx2_5706_serdes_timer(struct bnx2 *bp)
 {
-        struct bnx2 *bp = (struct bnx2 *) data;
-        u32 msg;
+        spin_lock(&bp->phy_lock);
+        if (bp->serdes_an_pending)
+                bp->serdes_an_pending--;
+        else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
+                u32 bmcr;
 
-        if (!netif_running(bp->dev))
-                return;
+                bp->current_interval = bp->timer_interval;
 
-        if (atomic_read(&bp->intr_sem) != 0)
-                goto bnx2_restart_timer;
+                bnx2_read_phy(bp, MII_BMCR, &bmcr);
 
-        msg = (u32) ++bp->fw_drv_pulse_wr_seq;
-        REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
+                if (bmcr & BMCR_ANENABLE) {
+                        u32 phy1, phy2;
 
-        bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
+                        bnx2_write_phy(bp, 0x1c, 0x7c00);
+                        bnx2_read_phy(bp, 0x1c, &phy1);
 
-        if ((bp->phy_flags & PHY_SERDES_FLAG) &&
-            (CHIP_NUM(bp) == CHIP_NUM_5706)) {
+                        bnx2_write_phy(bp, 0x17, 0x0f01);
+                        bnx2_read_phy(bp, 0x15, &phy2);
+                        bnx2_write_phy(bp, 0x17, 0x0f01);
+                        bnx2_read_phy(bp, 0x15, &phy2);
 
-                spin_lock(&bp->phy_lock);
-                if (bp->serdes_an_pending) {
-                        bp->serdes_an_pending--;
+                        if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
+                                !(phy2 & 0x20)) {       /* no CONFIG */
+
+                                bmcr &= ~BMCR_ANENABLE;
+                                bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
+                                bnx2_write_phy(bp, MII_BMCR, bmcr);
+                                bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
+                        }
                 }
-                else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
-                        u32 bmcr;
+        }
+        else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
+                 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
+                u32 phy2;
 
-                        bp->current_interval = bp->timer_interval;
+                bnx2_write_phy(bp, 0x17, 0x0f01);
+                bnx2_read_phy(bp, 0x15, &phy2);
+                if (phy2 & 0x20) {
+                        u32 bmcr;
 
                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
+                        bmcr |= BMCR_ANENABLE;
+                        bnx2_write_phy(bp, MII_BMCR, bmcr);
 
-                        if (bmcr & BMCR_ANENABLE) {
-                                u32 phy1, phy2;
+                        bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+                }
+        } else
+                bp->current_interval = bp->timer_interval;
 
-                                bnx2_write_phy(bp, 0x1c, 0x7c00);
-                                bnx2_read_phy(bp, 0x1c, &phy1);
+        spin_unlock(&bp->phy_lock);
+}
 
-                                bnx2_write_phy(bp, 0x17, 0x0f01);
-                                bnx2_read_phy(bp, 0x15, &phy2);
-                                bnx2_write_phy(bp, 0x17, 0x0f01);
-                                bnx2_read_phy(bp, 0x15, &phy2);
+static void
+bnx2_5708_serdes_timer(struct bnx2 *bp)
+{
+        if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
+                bp->serdes_an_pending = 0;
+                return;
+        }
 
-                                if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
-                                        !(phy2 & 0x20)) {       /* no CONFIG */
+        spin_lock(&bp->phy_lock);
+        if (bp->serdes_an_pending)
+                bp->serdes_an_pending--;
+        else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
+                u32 bmcr;
 
-                                        bmcr &= ~BMCR_ANENABLE;
-                                        bmcr |= BMCR_SPEED1000 |
-                                                BMCR_FULLDPLX;
-                                        bnx2_write_phy(bp, MII_BMCR, bmcr);
-                                        bp->phy_flags |=
-                                                PHY_PARALLEL_DETECT_FLAG;
-                                }
-                        }
+                bnx2_read_phy(bp, MII_BMCR, &bmcr);
+
+                if (bmcr & BMCR_ANENABLE) {
+                        bmcr &= ~BMCR_ANENABLE;
+                        bmcr |= BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500;
+                        bnx2_write_phy(bp, MII_BMCR, bmcr);
+                        bp->current_interval = SERDES_FORCED_TIMEOUT;
+                } else {
+                        bmcr &= ~(BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500);
+                        bmcr |= BMCR_ANENABLE;
+                        bnx2_write_phy(bp, MII_BMCR, bmcr);
+                        bp->serdes_an_pending = 2;
+                        bp->current_interval = bp->timer_interval;
                 }
-                else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
-                        (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
-                        u32 phy2;
 
-                        bnx2_write_phy(bp, 0x17, 0x0f01);
-                        bnx2_read_phy(bp, 0x15, &phy2);
-                        if (phy2 & 0x20) {
-                                u32 bmcr;
+        } else
+                bp->current_interval = bp->timer_interval;
 
-                                bnx2_read_phy(bp, MII_BMCR, &bmcr);
-                                bmcr |= BMCR_ANENABLE;
-                                bnx2_write_phy(bp, MII_BMCR, bmcr);
+        spin_unlock(&bp->phy_lock);
+}
+
+static void
+bnx2_timer(unsigned long data)
+{
+        struct bnx2 *bp = (struct bnx2 *) data;
+        u32 msg;
 
-                                bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+        if (!netif_running(bp->dev))
+                return;
 
-                        }
-                }
-                else
-                        bp->current_interval = bp->timer_interval;
+        if (atomic_read(&bp->intr_sem) != 0)
+                goto bnx2_restart_timer;
 
-                spin_unlock(&bp->phy_lock);
+        msg = (u32) ++bp->fw_drv_pulse_wr_seq;
+        REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
+
+        bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
+
+        if (bp->phy_flags & PHY_SERDES_FLAG) {
+                if (CHIP_NUM(bp) == CHIP_NUM_5706)
+                        bnx2_5706_serdes_timer(bp);
+                else if (CHIP_NUM(bp) == CHIP_NUM_5708)
+                        bnx2_5708_serdes_timer(bp);
         }
 
 bnx2_restart_timer:
@@ -4339,9 +4411,9 @@ bnx2_open(struct net_device *dev)
 }
 
 static void
-bnx2_reset_task(void *data)
+bnx2_reset_task(struct work_struct *work)
 {
-        struct bnx2 *bp = data;
+        struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
 
         if (!netif_running(bp->dev))
                 return;
@@ -4508,8 +4580,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
         prod = NEXT_TX_BD(prod);
         bp->tx_prod_bseq += skb->len;
 
-        REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
-        REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
+        REG_WR16(bp, bp->tx_bidx_addr, prod);
+        REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
 
         mmiowb();
 
@@ -4743,10 +4815,14 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
         }
         else {
                 if (bp->phy_flags & PHY_SERDES_FLAG) {
-                        if ((cmd->speed != SPEED_1000) ||
-                                (cmd->duplex != DUPLEX_FULL)) {
+                        if ((cmd->speed != SPEED_1000 &&
+                             cmd->speed != SPEED_2500) ||
+                            (cmd->duplex != DUPLEX_FULL))
+                                return -EINVAL;
+
+                        if (cmd->speed == SPEED_2500 &&
+                            !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
                                 return -EINVAL;
-                        }
                 }
                 else if (cmd->speed == SPEED_1000) {
                         return -EINVAL;
@@ -4903,11 +4979,10 @@ bnx2_nway_reset(struct net_device *dev)
                 msleep(20);
 
                 spin_lock_bh(&bp->phy_lock);
-                if (CHIP_NUM(bp) == CHIP_NUM_5706) {
-                        bp->current_interval = SERDES_AN_TIMEOUT;
-                        bp->serdes_an_pending = 1;
-                        mod_timer(&bp->timer, jiffies + bp->current_interval);
-                }
+
+                bp->current_interval = SERDES_AN_TIMEOUT;
+                bp->serdes_an_pending = 1;
+                mod_timer(&bp->timer, jiffies + bp->current_interval);
         }
 
         bnx2_read_phy(bp, MII_BMCR, &bmcr);
@@ -5288,6 +5363,8 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
 
         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
         if (etest->flags & ETH_TEST_FL_OFFLINE) {
+                int i;
+
                 bnx2_netif_stop(bp);
                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
                 bnx2_free_skbs(bp);
@@ -5312,9 +5389,11 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
                 }
 
                 /* wait for link up */
-                msleep_interruptible(3000);
-                if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
-                        msleep_interruptible(4000);
+                for (i = 0; i < 7; i++) {
+                        if (bp->link_up)
+                                break;
+                        msleep_interruptible(1000);
+                }
         }
 
         if (bnx2_test_nvram(bp) != 0) {
@@ -5604,13 +5683,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                 goto err_out_release;
         }
 
-        bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
-        if (bp->pcix_cap == 0) {
-                dev_err(&pdev->dev, "Cannot find PCIX capability, aborting.\n");
-                rc = -EIO;
-                goto err_out_release;
-        }
-
         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
                 bp->flags |= USING_DAC_FLAG;
                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
@@ -5630,10 +5702,10 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
         bp->pdev = pdev;
 
         spin_lock_init(&bp->phy_lock);
-        INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
+        INIT_WORK(&bp->reset_task, bnx2_reset_task);
 
         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
-        mem_len = MB_GET_CID_ADDR(17);
+        mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
         dev->mem_end = dev->mem_start + mem_len;
         dev->irq = pdev->irq;
 
@@ -5657,6 +5729,16 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
 
         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
 
+        if (CHIP_NUM(bp) != CHIP_NUM_5709) {
+                bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
+                if (bp->pcix_cap == 0) {
+                        dev_err(&pdev->dev,
+                                "Cannot find PCIX capability, aborting.\n");
+                        rc = -EIO;
+                        goto err_out_unmap;
+                }
+        }
+
         /* Get bus information. */
         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
@@ -5776,10 +5858,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
         bp->phy_addr = 1;
 
         /* Disable WOL support if we are running on a SERDES chip. */
-        if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
+        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+                if (CHIP_BOND_ID(bp) != BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
+                        bp->phy_flags |= PHY_SERDES_FLAG;
+        } else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
                 bp->phy_flags |= PHY_SERDES_FLAG;
+
+        if (bp->phy_flags & PHY_SERDES_FLAG) {
                 bp->flags |= NO_WOL_FLAG;
-                if (CHIP_NUM(bp) == CHIP_NUM_5708) {
+                if (CHIP_NUM(bp) != CHIP_NUM_5706) {
                         bp->phy_addr = 2;
                         reg = REG_RD_IND(bp, bp->shmem_base +
                                          BNX2_SHARED_HW_CFG_CONFIG);
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index ca31904893ea..13b6f9b11e01 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -56,6 +56,7 @@ struct rx_bd {
 
 };
 
+#define BNX2_RX_ALIGN                   16
 
 /*
  *  status_block definition
@@ -90,6 +91,7 @@ struct status_block {
                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
+                #define STATUS_ATTN_BITS_EPB_ERROR              (1L<<30)
                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
 
         u32 status_attn_bits_ack;
@@ -117,7 +119,8 @@ struct status_block {
         u16 status_completion_producer_index;
         u16 status_cmd_consumer_index;
         u16 status_idx;
-        u16 status_unused;
+        u8 status_unused;
+        u8 status_blk_num;
 #elif defined(__LITTLE_ENDIAN)
         u16 status_tx_quick_consumer_index1;
         u16 status_tx_quick_consumer_index0;
@@ -141,7 +144,8 @@ struct status_block {
         u16 status_rx_quick_consumer_index14;
         u16 status_cmd_consumer_index;
         u16 status_completion_producer_index;
-        u16 status_unused;
+        u8 status_blk_num;
+        u8 status_unused;
         u16 status_idx;
 #endif
 };
@@ -301,6 +305,10 @@ struct l2_fhdr {
 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
 
+#define BNX2_L2CTX_TYPE_XI                              0x00000080
+#define BNX2_L2CTX_CMD_TYPE_XI                          0x00000240
+#define BNX2_L2CTX_TBDR_BHADDR_HI_XI                    0x00000258
+#define BNX2_L2CTX_TBDR_BHADDR_LO_XI                    0x0000025c
 
 /*
  *  l2_bd_chain_context definition
@@ -328,11 +336,15 @@ struct l2_fhdr {
 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
+#define BNX2_PCICFG_MISC_CONFIG_RESERVED1                (1L<<4)
 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1L<<10)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1L<<11)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1L<<12)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
@@ -347,6 +359,7 @@ struct l2_fhdr {
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
+#define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1L<<8)
 
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
@@ -366,7 +379,7 @@ struct l2_fhdr {
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD     (1L<<11)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1L<<11)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
@@ -374,18 +387,21 @@ struct l2_fhdr {
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP  (1L<<17)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1L<<17)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET   (1L<<19)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1L<<19)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
 
 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
+#define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffL<<2)
+
 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
+#define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfL<<24)
 
 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
@@ -398,9 +414,11 @@ struct l2_fhdr {
  *  offset: 0x400
  */
 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
-#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE       (0x3ffffL<<8)
+#define BNX2_PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffL<<13)
+#define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1L<<31)
 
 #define BNX2_PCI_CONFIG_1                               0x00000404
+#define BNX2_PCI_CONFIG_1_RESERVED0                      (0xffL<<0)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
@@ -419,6 +437,7 @@ struct l2_fhdr {
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
+#define BNX2_PCI_CONFIG_1_RESERVED1                      (0x3ffffL<<14)
 
 #define BNX2_PCI_CONFIG_2                               0x00000408
 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
@@ -468,9 +487,13 @@ struct l2_fhdr {
 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
+#define BNX2_PCI_CONFIG_2_RESERVED0                      (0x3fL<<26)
+#define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI                (1L<<16)
+#define BNX2_PCI_CONFIG_2_RESERVED0_XI                   (0x7fffL<<17)
 
 #define BNX2_PCI_CONFIG_3                               0x0000040c
 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
+#define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE                (0xffL<<8)
 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
@@ -501,8 +524,10 @@ struct l2_fhdr {
 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
 
 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
-#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fff<<2)
-#define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1<<15)
+#define BNX2_PCI_VPD_ADDR_FLAG_MSK                      0x0000ffff
+#define BNX2_PCI_VPD_ADDR_FLAG_SL                       0L
+#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fffL<<2)
+#define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1L<<15)
 
 #define BNX2_PCI_VPD_DATA                               0x00000430
 #define BNX2_PCI_ID_VAL1                                0x00000434
@@ -535,19 +560,26 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
+#define BNX2_PCI_ID_VAL4_RESERVED0                       (0x3L<<4)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
+#define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1L<<8)
 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
-#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE                   (0x7L<<12)
+#define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7L<<12)
 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
-#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE               (0x3L<<21)
-#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE                  (0x7L<<23)
-#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE             (0x7L<<26)
+#define BNX2_PCI_ID_VAL4_RESERVED2                       (0x7L<<18)
+#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21         (0x3L<<21)
+#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21              (0x3L<<23)
+#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0          (1L<<25)
+#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10           (0x3L<<26)
+#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0               (1L<<28)
+#define BNX2_PCI_ID_VAL4_RESERVED3                       (0x7L<<29)
+#define BNX2_PCI_ID_VAL4_RESERVED3_XI                    (0xffffL<<16)
 
 #define BNX2_PCI_ID_VAL5                                0x00000444
 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
@@ -556,6 +588,10 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
+#define BNX2_PCI_ID_VAL5_RESERVED0_TE                    (0x3ffffffL<<6)
+#define BNX2_PCI_ID_VAL5_PM_VERSION_XI                   (0x7L<<6)
+#define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI                (1L<<9)
+#define BNX2_PCI_ID_VAL5_RESERVED0_XI                    (0x3fffffL<<10)
 
 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
@@ -567,12 +603,91 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
+#define BNX2_PCI_ID_VAL6_RESERVED0                       (0xffL<<24)
 
 #define BNX2_PCI_MSI_DATA                               0x00000450
-#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA                   (0xffffL<<0)
+#define BNX2_PCI_MSI_DATA_MSI_DATA                       (0xffffL<<0)
 
 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
+#define BNX2_PCI_MSI_ADDR_L_VAL                          (0x3fffffffL<<2)
+
+#define BNX2_PCI_CFG_ACCESS_CMD                         0x0000045c
+#define BNX2_PCI_CFG_ACCESS_CMD_ADR                      (0x3fL<<2)
+#define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ                   (1L<<27)
+#define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfL<<28)
+
+#define BNX2_PCI_CFG_ACCESS_DATA                        0x00000460
+#define BNX2_PCI_MSI_MASK                               0x00000464
+#define BNX2_PCI_MSI_MASK_MSI_MASK                       (0xffffffffL<<0)
+
+#define BNX2_PCI_MSI_PEND                               0x00000468
+#define BNX2_PCI_MSI_PEND_MSI_PEND                       (0xffffffffL<<0)
+
+#define BNX2_PCI_PM_DATA_C                              0x0000046c
+#define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffL<<0)
+#define BNX2_PCI_PM_DATA_C_RESERVED0                     (0xffffffL<<8)
+
+#define BNX2_PCI_MSIX_CONTROL                           0x000004c0
+#define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffL<<0)
+#define BNX2_PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffL<<11)
+
+#define BNX2_PCI_MSIX_TBL_OFF_BIR                       0x000004c4
+#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7L<<0)
+#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffL<<3)
+
+#define BNX2_PCI_MSIX_PBA_OFF_BIT                       0x000004c8
+#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7L<<0)
+#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffL<<3)
+
+#define BNX2_PCI_PCIE_CAPABILITY                        0x000004d0
+#define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fL<<0)
+#define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1L<<5)
+
+#define BNX2_PCI_DEVICE_CAPABILITY                      0x000004d4
+#define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7L<<0)
+#define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1L<<5)
+#define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY        (0x7L<<6)
+#define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY         (0x7L<<9)
+#define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1L<<15)
+
+#define BNX2_PCI_LINK_CAPABILITY                        0x000004dc
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfL<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001     (1L<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010     (1L<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fL<<4)
+#define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1L<<9)
+#define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3L<<10)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101        (5L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110        (6L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001         (1L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010         (2L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101   (5L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110   (6L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001    (1L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010    (2L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_PORT_NUM                (0xffL<<24)
+
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2               0x000004e4
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP     (0xfL<<0)
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP    (1L<<4)
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffL<<5)
+
+#define BNX2_PCI_PCIE_LINK_CAPABILITY_2                 0x000004e8
+#define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffL<<0)
+
+#define BNX2_PCI_GRC_WINDOW1_ADDR                       0x00000610
+#define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffL<<13)
+
+#define BNX2_PCI_GRC_WINDOW2_ADDR                       0x00000614
+#define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffL<<13)
+
+#define BNX2_PCI_GRC_WINDOW3_ADDR                       0x00000618
+#define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffL<<13)
 
 
 /*
@@ -582,13 +697,23 @@ struct l2_fhdr {
 #define BNX2_MISC_COMMAND                               0x00000800
 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
-#define BNX2_MISC_COMMAND_CORE_RESET                     (1L<<4)
-#define BNX2_MISC_COMMAND_HARD_RESET                     (1L<<5)
+#define BNX2_MISC_COMMAND_SW_RESET                       (1L<<4)
+#define BNX2_MISC_COMMAND_POR_RESET                      (1L<<5)
+#define BNX2_MISC_COMMAND_HD_RESET                       (1L<<6)
+#define BNX2_MISC_COMMAND_CMN_SW_RESET                   (1L<<7)
 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
+#define BNX2_MISC_COMMAND_CS16_ERR                       (1L<<9)
+#define BNX2_MISC_COMMAND_CS16_ERR_LOC                   (0xfL<<12)
 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
+#define BNX2_MISC_COMMAND_POWERDOWN_EVENT                (1L<<23)
+#define BNX2_MISC_COMMAND_SW_SHUTDOWN                    (1L<<24)
+#define BNX2_MISC_COMMAND_SHUTDOWN_EN                    (1L<<25)
+#define BNX2_MISC_COMMAND_DINTEG_ATTN_EN                 (1L<<26)
+#define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23               (1L<<27)
+#define BNX2_MISC_COMMAND_PCIE_DIS                       (1L<<28)
 
 #define BNX2_MISC_CFG                                   0x00000804
-#define BNX2_MISC_CFG_PCI_GRC_TMOUT                      (1L<<0)
+#define BNX2_MISC_CFG_GRC_TMOUT                          (1L<<0)
 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
@@ -596,16 +721,45 @@ struct l2_fhdr {
 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
-#define BNX2_MISC_CFG_BYPASS_BSCAN                       (1L<<5)
-#define BNX2_MISC_CFG_BYPASS_EJTAG                       (1L<<6)
+#define BNX2_MISC_CFG_RESERVED5_TE                       (1L<<5)
+#define BNX2_MISC_CFG_RESERVED6_TE                       (1L<<6)
 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
-#define BNX2_MISC_CFG_LEDMODE                            (0x3L<<8)
+#define BNX2_MISC_CFG_LEDMODE                            (0x7L<<8)
 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
-#define BNX2_MISC_CFG_LEDMODE_GPHY1                      (1L<<8)
-#define BNX2_MISC_CFG_LEDMODE_GPHY2                      (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY1_TE                    (1L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY2_TE                    (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY3_TE                    (3L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY4_TE                    (4L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY5_TE                    (5L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY6_TE                    (6L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY7_TE                    (7L<<8)
+#define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE                   (1L<<11)
+#define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE                   (1L<<12)
+#define BNX2_MISC_CFG_LEDMODE_XI                         (0xfL<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC_XI                     (0L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY1_XI                    (1L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY2_XI                    (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY3_XI                    (3L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC2_XI                    (4L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY4_XI                    (5L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY5_XI                    (6L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY6_XI                    (7L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC3_XI                    (8L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY7_XI                    (9L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY8_XI                    (10L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY9_XI                    (11L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC4_XI                    (12L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY10_XI                   (13L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY11_XI                   (14L<<8)
+#define BNX2_MISC_CFG_LEDMODE_UNUSED_XI                  (15L<<8)
+#define BNX2_MISC_CFG_PORT_SELECT_XI                     (1L<<13)
+#define BNX2_MISC_CFG_PARITY_MODE_XI                     (1L<<14)
 
 #define BNX2_MISC_ID                                    0x00000808
 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
+#define BNX2_MISC_ID_BOND_ID_X                           (0L<<0)
+#define BNX2_MISC_ID_BOND_ID_C                           (3L<<0)
+#define BNX2_MISC_ID_BOND_ID_S                           (12L<<0)
 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
@@ -639,6 +793,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE   (1L<<28)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE  (0x7L<<29)
 
 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
@@ -669,6 +825,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
+#define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
+#define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 
 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
@@ -699,6 +857,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
+#define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
+#define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 
 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
@@ -718,30 +878,41 @@ struct l2_fhdr {
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD           (1L<<11)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI        (0x7L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER           (1L<<11)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI        (0xfL<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP        (1L<<17)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18         (1L<<18)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET         (1L<<19)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED            (0xfffL<<20)
-
-#define BNX2_MISC_GPIO                                  0x0000081c
-#define BNX2_MISC_GPIO_VALUE                             (0xffL<<0)
-#define BNX2_MISC_GPIO_SET                               (0xffL<<8)
-#define BNX2_MISC_GPIO_CLR                               (0xffL<<16)
-#define BNX2_MISC_GPIO_FLOAT                             (0xffL<<24)
-
-#define BNX2_MISC_GPIO_INT                              0x00000820
-#define BNX2_MISC_GPIO_INT_INT_STATE                     (0xfL<<0)
-#define BNX2_MISC_GPIO_INT_OLD_VALUE                     (0xfL<<8)
-#define BNX2_MISC_GPIO_INT_OLD_SET                       (0xfL<<16)
-#define BNX2_MISC_GPIO_INT_OLD_CLR                       (0xfL<<24)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE      (1L<<17)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE      (1L<<18)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE      (1L<<19)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE         (0xfffL<<20)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI        (1L<<17)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI        (0x3fL<<18)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI         (0x7L<<24)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI        (1L<<27)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI       (0xfL<<28)
+
+#define BNX2_MISC_SPIO                                  0x0000081c
+#define BNX2_MISC_SPIO_VALUE                             (0xffL<<0)
+#define BNX2_MISC_SPIO_SET                               (0xffL<<8)
+#define BNX2_MISC_SPIO_CLR                               (0xffL<<16)
+#define BNX2_MISC_SPIO_FLOAT                             (0xffL<<24)
+
+#define BNX2_MISC_SPIO_INT                              0x00000820
+#define BNX2_MISC_SPIO_INT_INT_STATE_TE                  (0xfL<<0)
+#define BNX2_MISC_SPIO_INT_OLD_VALUE_TE                  (0xfL<<8)
+#define BNX2_MISC_SPIO_INT_OLD_SET_TE                    (0xfL<<16)
+#define BNX2_MISC_SPIO_INT_OLD_CLR_TE                    (0xfL<<24)
+#define BNX2_MISC_SPIO_INT_INT_STATE_XI                  (0xffL<<0)
+#define BNX2_MISC_SPIO_INT_OLD_VALUE_XI                  (0xffL<<8)
+#define BNX2_MISC_SPIO_INT_OLD_SET_XI                    (0xffL<<16)
+#define BNX2_MISC_SPIO_INT_OLD_CLR_XI                    (0xffL<<24)
 
 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
@@ -775,6 +946,8 @@ struct l2_fhdr {
 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
+#define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE       (1L<<28)
+#define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE      (0x7L<<29)
 
 #define BNX2_MISC_ARB_REQ0                              0x0000082c
 #define BNX2_MISC_ARB_REQ1                              0x00000830
@@ -831,22 +1004,12 @@ struct l2_fhdr {
 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
 
-#define BNX2_MISC_PRBS_CONTROL                          0x00000878
-#define BNX2_MISC_PRBS_CONTROL_EN                        (1L<<0)
-#define BNX2_MISC_PRBS_CONTROL_RSTB                      (1L<<1)
-#define BNX2_MISC_PRBS_CONTROL_INV                       (1L<<2)
-#define BNX2_MISC_PRBS_CONTROL_ERR_CLR                   (1L<<3)
-#define BNX2_MISC_PRBS_CONTROL_ORDER                     (0x3L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH                 (0L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH                (1L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD                (2L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST                (3L<<4)
-
-#define BNX2_MISC_PRBS_STATUS                           0x0000087c
-#define BNX2_MISC_PRBS_STATUS_LOCK                       (1L<<0)
-#define BNX2_MISC_PRBS_STATUS_STKY                       (1L<<1)
-#define BNX2_MISC_PRBS_STATUS_ERRORS                     (0x3fffL<<2)
-#define BNX2_MISC_PRBS_STATUS_STATE                      (0xfL<<16)
+#define BNX2_MISC_RESERVED1                             0x00000878
+#define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE         (0x3fL<<0)
+
+#define BNX2_MISC_RESERVED2                             0x0000087c
+#define BNX2_MISC_RESERVED2_PCIE_DIS                     (1L<<0)
+#define BNX2_MISC_RESERVED2_LINK_IN_L23                  (1L<<1)
 
 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
@@ -857,13 +1020,15 @@ struct l2_fhdr {
 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
-#define BNX2_MISC_SM_ASF_CONTROL_RES                     (0xfL<<8)
+#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN              (1L<<8)
+#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE           (1L<<9)
+#define BNX2_MISC_SM_ASF_CONTROL_RES                     (0x3L<<10)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
-#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x3fL<<16)
-#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x3fL<<24)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x7fL<<16)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x7fL<<23)
 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
 
@@ -891,13 +1056,13 @@ struct l2_fhdr {
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
-#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (6L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
-#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (0x6L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
@@ -955,6 +1120,38 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
+#define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI          (1L<<0)
+#define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI           (1L<<1)
+#define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI     (1L<<2)
+#define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI     (1L<<3)
+#define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI         (1L<<4)
+#define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI         (1L<<5)
+#define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI        (1L<<6)
+#define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI          (1L<<7)
+#define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI         (1L<<8)
+#define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI           (1L<<9)
+#define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI          (1L<<10)
+#define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI         (1L<<11)
+#define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI          (1L<<12)
+#define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI         (1L<<13)
+#define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI        (1L<<14)
+#define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI          (1L<<15)
+#define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI         (1L<<16)
+#define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI           (1L<<17)
+#define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI            (1L<<18)
+#define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI      (1L<<19)
+#define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI      (1L<<20)
+#define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI       (1L<<21)
+#define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI      (1L<<22)
+#define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI       (1L<<23)
+#define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI       (1L<<24)
+#define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI      (1L<<25)
+#define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI      (1L<<26)
+#define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI             (1L<<27)
+#define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI             (1L<<28)
+#define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI              (1L<<29)
+#define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI              (1L<<30)
+#define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI           (1L<<31)
 
 #define BNX2_MISC_PERR_ENA1                             0x000008a8
 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
@@ -989,6 +1186,35 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
+#define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI              (1L<<0)
+#define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI        (1L<<2)
+#define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI          (1L<<3)
+#define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI           (1L<<4)
+#define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI      (1L<<5)
+#define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI      (1L<<6)
+#define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI             (1L<<7)
+#define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI              (1L<<8)
+#define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI             (1L<<9)
+#define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI              (1L<<10)
+#define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI             (1L<<11)
+#define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI              (1L<<12)
+#define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI             (1L<<13)
+#define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI              (1L<<14)
+#define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI            (1L<<15)
+#define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI             (1L<<16)
+#define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI              (1L<<17)
+#define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI             (1L<<18)
+#define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI             (1L<<19)
+#define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI             (1L<<20)
+#define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI             (1L<<21)
+#define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI            (1L<<22)
+#define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI            (1L<<23)
+#define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI               (1L<<24)
+#define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI               (1L<<25)
+#define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI          (1L<<26)
+#define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI       (1L<<27)
+#define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI           (1L<<28)
+#define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI            (1L<<29)
 
 #define BNX2_MISC_PERR_ENA2                             0x000008ac
 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
@@ -1000,19 +1226,498 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
+#define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI          (1L<<0)
+#define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI            (1L<<1)
+#define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI            (1L<<2)
+#define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI           (1L<<3)
+#define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI         (1L<<4)
+#define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI            (1L<<5)
+#define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI       (1L<<6)
 
 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
+#define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI                  (0xfffL<<15)
 
 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI               (0xfL<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI        (0L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI        (1L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI        (2L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI         (3L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI         (4L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI         (5L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI         (6L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI           (7L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI        (8L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI        (9L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI        (10L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI        (11L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI       (12L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI       (13L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI       (14L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI       (15L<<0)
 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS14                (0L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS12                (1L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS10                (2L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS8                 (3L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS6                 (4L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS4                 (5L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS2                 (6L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_NOM                   (7L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS2                (8L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS4                (9L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS6                (10L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS8                (11L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS10               (12L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS12               (13L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS14               (14L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS16               (15L<<4)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT                  (0xfL<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14           (0L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12           (1L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10           (2L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8            (3L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6            (4L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4            (5L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2            (6L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM              (7L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2           (8L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4           (9L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6           (10L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8           (11L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10          (12L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12          (13L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14          (14L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16          (15L<<8)
 
 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
 
-#define BNX2_MISC_UNUSED0                               0x000008bc
+#define BNX2_MISC_GP_HW_CTL0                            0x000008bc
+#define BNX2_MISC_GP_HW_CTL0_TX_DRIVE                    (1L<<0)
+#define BNX2_MISC_GP_HW_CTL0_RMII_MODE                   (1L<<1)
+#define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL              (1L<<2)
+#define BNX2_MISC_GP_HW_CTL0_RVMII_MODE                  (1L<<3)
+#define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE  (1L<<4)
+#define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE       (1L<<5)
+#define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE    (1L<<6)
+#define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI                (0x7L<<4)
+#define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY         (1L<<7)
+#define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE     (1L<<8)
+#define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE         (1L<<9)
+#define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE              (1L<<10)
+#define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI                (0x7L<<8)
+#define BNX2_MISC_GP_HW_CTL0_UP1_DEF0                    (1L<<11)
+#define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF          (1L<<12)
+#define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF               (1L<<13)
+#define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF          (1L<<14)
+#define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF         (1L<<15)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI                 (0xfL<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA             (0L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA           (1L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA           (3L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA           (5L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA           (7L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN           (15L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS             (1L<<20)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS             (1L<<21)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT                (0x3L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P            (0L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P            (1L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P            (2L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P            (3L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT                (0x3L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P            (0L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P            (1L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P            (2L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P            (3L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ            (0x3L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA      (0L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA      (1L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA      (2L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA      (3L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ           (0x3L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA     (0L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA     (1L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA     (2L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA     (3L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ            (0x3L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57       (0L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45       (1L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62       (2L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66       (3L<<30)
+
+#define BNX2_MISC_GP_HW_CTL1                            0x000008c0
+#define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE         (1L<<0)
+#define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE         (1L<<1)
+#define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE          (1L<<2)
+#define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE          (1L<<3)
+#define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI            (0xffffL<<0)
+#define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI            (0xffffL<<16)
+
+#define BNX2_MISC_NEW_HW_CTL                            0x000008c4
+#define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS             (1L<<0)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE              (1L<<1)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0                (1L<<2)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1                (1L<<3)
+#define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED             (0xfffL<<4)
+#define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT              (0xffffL<<16)
+
+#define BNX2_MISC_NEW_CORE_CTL                          0x000008c8
+#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS      (1L<<0)
+#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ          (1L<<1)
+#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN              (0x3fffL<<2)
+#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC               (0xffffL<<16)
+
+#define BNX2_MISC_ECO_HW_CTL                            0x000008cc
+#define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN          (1L<<0)
+#define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT               (0x7fffL<<1)
+#define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD               (0xffffL<<16)
+
+#define BNX2_MISC_ECO_CORE_CTL                          0x000008d0
+#define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT             (0xffffL<<0)
+#define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD             (0xffffL<<16)
+
+#define BNX2_MISC_PPIO                                  0x000008d4
+#define BNX2_MISC_PPIO_VALUE                             (0xfL<<0)
+#define BNX2_MISC_PPIO_SET                               (0xfL<<8)
+#define BNX2_MISC_PPIO_CLR                               (0xfL<<16)
+#define BNX2_MISC_PPIO_FLOAT                             (0xfL<<24)
+
+#define BNX2_MISC_PPIO_INT                              0x000008d8
+#define BNX2_MISC_PPIO_INT_INT_STATE                     (0xfL<<0)
+#define BNX2_MISC_PPIO_INT_OLD_VALUE                     (0xfL<<8)
+#define BNX2_MISC_PPIO_INT_OLD_SET                       (0xfL<<16)
+#define BNX2_MISC_PPIO_INT_OLD_CLR                       (0xfL<<24)
+
+#define BNX2_MISC_RESET_NUMS                            0x000008dc
+#define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS             (0x7L<<0)
+#define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS             (0x7L<<4)
+#define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS           (0x7L<<8)
+#define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS              (0x7L<<12)
+#define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS             (0x7L<<16)
+
+#define BNX2_MISC_CS16_ERR                              0x000008e0
+#define BNX2_MISC_CS16_ERR_ENA_PCI                       (1L<<0)
+#define BNX2_MISC_CS16_ERR_ENA_RDMA                      (1L<<1)
+#define BNX2_MISC_CS16_ERR_ENA_TDMA                      (1L<<2)
+#define BNX2_MISC_CS16_ERR_ENA_EMAC                      (1L<<3)
+#define BNX2_MISC_CS16_ERR_ENA_CTX                       (1L<<4)
+#define BNX2_MISC_CS16_ERR_ENA_TBDR                      (1L<<5)
+#define BNX2_MISC_CS16_ERR_ENA_RBDC                      (1L<<6)
+#define BNX2_MISC_CS16_ERR_ENA_COM                       (1L<<7)
+#define BNX2_MISC_CS16_ERR_ENA_CP                        (1L<<8)
+#define BNX2_MISC_CS16_ERR_STA_PCI                       (1L<<16)
+#define BNX2_MISC_CS16_ERR_STA_RDMA                      (1L<<17)
+#define BNX2_MISC_CS16_ERR_STA_TDMA                      (1L<<18)
+#define BNX2_MISC_CS16_ERR_STA_EMAC                      (1L<<19)
+#define BNX2_MISC_CS16_ERR_STA_CTX                       (1L<<20)
+#define BNX2_MISC_CS16_ERR_STA_TBDR                      (1L<<21)
+#define BNX2_MISC_CS16_ERR_STA_RBDC                      (1L<<22)
+#define BNX2_MISC_CS16_ERR_STA_COM                       (1L<<23)
+#define BNX2_MISC_CS16_ERR_STA_CP                        (1L<<24)
+
+#define BNX2_MISC_SPIO_EVENT                            0x000008e4
+#define BNX2_MISC_SPIO_EVENT_ENABLE                      (0xffL<<0)
+
+#define BNX2_MISC_PPIO_EVENT                            0x000008e8
+#define BNX2_MISC_PPIO_EVENT_ENABLE                      (0xfL<<0)
+
+#define BNX2_MISC_DUAL_MEDIA_CTRL                       0x000008ec
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID                (0xffL<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X              (0L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C              (3L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S              (12L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP         (0x7L<<8)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN          (1L<<11)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET         (1L<<12)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET         (1L<<13)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET            (1L<<14)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET            (1L<<15)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST              (1L<<16)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST            (1L<<17)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST            (1L<<18)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST               (1L<<19)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST               (1L<<20)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL               (0x7L<<21)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP              (1L<<24)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE         (1L<<25)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ        (0xfL<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ      (1L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ      (2L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ      (4L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ      (8L<<26)
+
+#define BNX2_MISC_OTP_CMD1                              0x000008f0
+#define BNX2_MISC_OTP_CMD1_FMODE                         (0x7L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_IDLE                    (0L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_WRITE                   (1L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_INIT                    (2L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_SET                     (3L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RST                     (4L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_VERIFY                  (5L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0               (6L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1               (7L<<0)
+#define BNX2_MISC_OTP_CMD1_USEPINS                       (1L<<8)
+#define BNX2_MISC_OTP_CMD1_PROGSEL                       (1L<<9)
+#define BNX2_MISC_OTP_CMD1_PROGSTART                     (1L<<10)
+#define BNX2_MISC_OTP_CMD1_PCOUNT                        (0x7L<<16)
+#define BNX2_MISC_OTP_CMD1_PBYP                          (1L<<19)
+#define BNX2_MISC_OTP_CMD1_VSEL                          (0xfL<<20)
+#define BNX2_MISC_OTP_CMD1_TM                            (0x7L<<27)
+#define BNX2_MISC_OTP_CMD1_SADBYP                        (1L<<30)
+#define BNX2_MISC_OTP_CMD1_DEBUG                         (1L<<31)
+
+#define BNX2_MISC_OTP_CMD2                              0x000008f4
+#define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR                  (0x3ffL<<0)
+#define BNX2_MISC_OTP_CMD2_DOSEL                         (0x7fL<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_0                       (0L<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_1                       (1L<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_127                     (127L<<16)
+
+#define BNX2_MISC_OTP_STATUS                            0x000008f8
+#define BNX2_MISC_OTP_STATUS_DATA                        (0xffL<<0)
+#define BNX2_MISC_OTP_STATUS_VALID                       (1L<<8)
+#define BNX2_MISC_OTP_STATUS_BUSY                        (1L<<9)
+#define BNX2_MISC_OTP_STATUS_BUSYSM                      (1L<<10)
+#define BNX2_MISC_OTP_STATUS_DONE                        (1L<<11)
+
+#define BNX2_MISC_OTP_SHIFT1_CMD                        0x000008fc
+#define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N            (1L<<0)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START             (1L<<2)
+#define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA               (1L<<3)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT            (0x1fL<<8)
+
+#define BNX2_MISC_OTP_SHIFT1_DATA                       0x00000900
+#define BNX2_MISC_OTP_SHIFT2_CMD                        0x00000904
+#define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N            (1L<<0)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START             (1L<<2)
+#define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA               (1L<<3)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT            (0x1fL<<8)
+
+#define BNX2_MISC_OTP_SHIFT2_DATA                       0x00000908
+#define BNX2_MISC_BIST_CS0                              0x0000090c
+#define BNX2_MISC_BIST_CS0_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS0_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS0_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS0_MBIST_GO                      (1L<<9)
+#define BNX2_MISC_BIST_CS0_BIST_OVERRIDE                 (1L<<31)
+
+#define BNX2_MISC_BIST_MEMSTATUS0                       0x00000910
+#define BNX2_MISC_BIST_CS1                              0x00000914
+#define BNX2_MISC_BIST_CS1_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS1_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS1_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS1_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS1                       0x00000918
+#define BNX2_MISC_BIST_CS2                              0x0000091c
+#define BNX2_MISC_BIST_CS2_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS2_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS2_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS2_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS2                       0x00000920
+#define BNX2_MISC_BIST_CS3                              0x00000924
+#define BNX2_MISC_BIST_CS3_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS3_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS3_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS3_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS3                       0x00000928
+#define BNX2_MISC_BIST_CS4                              0x0000092c
+#define BNX2_MISC_BIST_CS4_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS4_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS4_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS4_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS4                       0x00000930
+#define BNX2_MISC_BIST_CS5                              0x00000934
+#define BNX2_MISC_BIST_CS5_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS5_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS5_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS5_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS5                       0x00000938
+#define BNX2_MISC_MEM_TM0                               0x0000093c
+#define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM                 (0xfL<<0)
+#define BNX2_MISC_MEM_TM0_MCP_SCPAD                      (0xfL<<8)
+#define BNX2_MISC_MEM_TM0_UMP_TM                         (0xffL<<16)
+#define BNX2_MISC_MEM_TM0_HB_MEM_TM                      (0xfL<<24)
+
+#define BNX2_MISC_USPLL_CTRL                            0x00000940
+#define BNX2_MISC_USPLL_CTRL_PH_DET_DIS                  (1L<<0)
+#define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS                (1L<<1)
+#define BNX2_MISC_USPLL_CTRL_LCPX                        (0x3fL<<2)
+#define BNX2_MISC_USPLL_CTRL_RX                          (0x3L<<8)
+#define BNX2_MISC_USPLL_CTRL_VC_EN                       (1L<<10)
+#define BNX2_MISC_USPLL_CTRL_VCO_MG                      (0x3L<<11)
+#define BNX2_MISC_USPLL_CTRL_KVCO_XF                     (0x7L<<13)
+#define BNX2_MISC_USPLL_CTRL_KVCO_XS                     (0x7L<<16)
+#define BNX2_MISC_USPLL_CTRL_TESTD_EN                    (1L<<19)
+#define BNX2_MISC_USPLL_CTRL_TESTD_SEL                   (0x7L<<20)
+#define BNX2_MISC_USPLL_CTRL_TESTA_EN                    (1L<<23)
+#define BNX2_MISC_USPLL_CTRL_TESTA_SEL                   (0x3L<<24)
+#define BNX2_MISC_USPLL_CTRL_ATTEN_FREF                  (1L<<26)
+#define BNX2_MISC_USPLL_CTRL_DIGITAL_RST                 (1L<<27)
+#define BNX2_MISC_USPLL_CTRL_ANALOG_RST                  (1L<<28)
+#define BNX2_MISC_USPLL_CTRL_LOCK                        (1L<<29)
+
+#define BNX2_MISC_PERR_STATUS0                          0x00000944
+#define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR             (1L<<0)
+#define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR              (1L<<1)
+#define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR        (1L<<2)
+#define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR        (1L<<3)
+#define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR            (1L<<4)
+#define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR            (1L<<5)
+#define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR           (1L<<6)
+#define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR             (1L<<7)
+#define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR            (1L<<8)
+#define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR              (1L<<9)
+#define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR             (1L<<10)
+#define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR            (1L<<11)
+#define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR             (1L<<12)
+#define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR            (1L<<13)
+#define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR           (1L<<14)
+#define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR             (1L<<15)
+#define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR            (1L<<16)
+#define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR              (1L<<17)
+#define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR               (1L<<18)
+#define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR         (1L<<19)
+#define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR         (1L<<20)
+#define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR          (1L<<21)
+#define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR         (1L<<22)
+#define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR          (1L<<23)
+#define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR          (1L<<24)
+#define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR         (1L<<25)
+#define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR         (1L<<26)
+#define BNX2_MISC_PERR_STATUS0_TPBUF_PERR                (1L<<27)
+#define BNX2_MISC_PERR_STATUS0_THBUF_PERR                (1L<<28)
+#define BNX2_MISC_PERR_STATUS0_TDMA_PERR                 (1L<<29)
+#define BNX2_MISC_PERR_STATUS0_TBDC_PERR                 (1L<<30)
+#define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR              (1L<<31)
+
+#define BNX2_MISC_PERR_STATUS1                          0x00000948
+#define BNX2_MISC_PERR_STATUS1_RBDC_PERR                 (1L<<0)
+#define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR           (1L<<2)
+#define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR             (1L<<3)
+#define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR              (1L<<4)
+#define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR         (1L<<5)
+#define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR         (1L<<6)
+#define BNX2_MISC_PERR_STATUS1_TPATQ_PERR                (1L<<7)
+#define BNX2_MISC_PERR_STATUS1_MCPQ_PERR                 (1L<<8)
+#define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR                (1L<<9)
+#define BNX2_MISC_PERR_STATUS1_TXPQ_PERR                 (1L<<10)
+#define BNX2_MISC_PERR_STATUS1_COMTQ_PERR                (1L<<11)
+#define BNX2_MISC_PERR_STATUS1_COMQ_PERR                 (1L<<12)
+#define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR                (1L<<13)
+#define BNX2_MISC_PERR_STATUS1_RXPQ_PERR                 (1L<<14)
+#define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR               (1L<<15)
+#define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR                (1L<<16)
+#define BNX2_MISC_PERR_STATUS1_TASQ_PERR                 (1L<<17)
+#define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR                (1L<<18)
+#define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR                (1L<<19)
+#define BNX2_MISC_PERR_STATUS1_COMXQ_PERR                (1L<<20)
+#define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR                (1L<<21)
+#define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR               (1L<<22)
+#define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR               (1L<<23)
+#define BNX2_MISC_PERR_STATUS1_CPQ_PERR                  (1L<<24)
+#define BNX2_MISC_PERR_STATUS1_CSQ_PERR                  (1L<<25)
+#define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR             (1L<<26)
+#define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR          (1L<<27)
+#define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR              (1L<<28)
+#define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR               (1L<<29)
+
+#define BNX2_MISC_PERR_STATUS2                          0x0000094c
+#define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR             (1L<<0)
+#define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR               (1L<<1)
+#define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR               (1L<<2)
+#define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR              (1L<<3)
+#define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR            (1L<<4)
+#define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR               (1L<<5)
+#define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR          (1L<<6)
+
+#define BNX2_MISC_LCPLL_CTRL0                           0x00000950
+#define BNX2_MISC_LCPLL_CTRL0_OAC                        (0x7L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY              (0L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO                   (1L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY                 (3L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY                  (7L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL                   (0x7L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360               (0L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480               (1L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600               (3L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720               (7L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL                  (0x3L<<6)
+#define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE                (0x7L<<8)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL                   (0x3L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0                 (0L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1                 (1L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2                 (2L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART                (1L<<13)
+#define BNX2_MISC_LCPLL_CTRL0_RESERVED                   (1L<<14)
+#define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN                (1L<<15)
+#define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN             (1L<<16)
+#define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN          (1L<<17)
+#define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN            (1L<<18)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN           (1L<<19)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE              (1L<<20)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS              (1L<<21)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN         (1L<<22)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE            (1L<<23)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN         (1L<<24)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS            (1L<<25)
+#define BNX2_MISC_LCPLL_CTRL0_CAPRESTART                 (1L<<26)
+#define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN              (1L<<27)
+
+#define BNX2_MISC_LCPLL_CTRL1                           0x00000954
+#define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM                 (0x1fL<<0)
+#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN        (1L<<5)
+#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN           (1L<<6)
+#define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR                 (1L<<7)
+
+#define BNX2_MISC_LCPLL_STATUS                          0x00000958
+#define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM               (1L<<0)
+#define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM               (1L<<1)
+#define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE                (1L<<2)
+#define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS                (1L<<3)
+#define BNX2_MISC_LCPLL_STATUS_PLLSTATE                  (0x7L<<4)
+#define BNX2_MISC_LCPLL_STATUS_CAPSTATE                  (0x7L<<7)
+#define BNX2_MISC_LCPLL_STATUS_CAPSELECT                 (0x1fL<<10)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR          (1L<<15)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0        (0L<<15)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1        (1L<<15)
+
+#define BNX2_MISC_OSCFUNDS_CTRL                         0x0000095c
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON                 (1L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF             (0L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON              (1L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM               (0x3L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0             (0L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1             (1L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2             (2L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3             (3L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ                (0x3L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0              (0L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1              (1L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2              (2L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3              (3L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ                 (0x3L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0               (0L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1               (1L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2               (2L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3               (3L<<10)
 
 
 /*
@@ -1031,11 +1736,35 @@ struct l2_fhdr {
 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
+#define BNX2_NVM_COMMAND_RD_ID                           (1L<<20)
+#define BNX2_NVM_COMMAND_RD_STATUS                       (1L<<21)
+#define BNX2_NVM_COMMAND_MODE_256                        (1L<<22)
 
 #define BNX2_NVM_STATUS                                 0x00006404
 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_XI                 (0x1fL<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI        (0L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI        (1L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI        (2L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI         (3L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI         (4L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI       (5L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI         (6L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI         (7L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI         (8L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI  (9L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI  (10L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI  (11L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI   (12L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI   (13L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI   (14L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI   (15L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI   (16L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI         (17L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI     (18L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI        (19L<<0)
 
 #define BNX2_NVM_WRITE                                  0x00006408
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
@@ -1046,6 +1775,10 @@ struct l2_fhdr {
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI             (1L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI             (2L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI           (4L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI           (8L<<0)
 
 #define BNX2_NVM_ADDR                                   0x0000640c
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
@@ -1056,6 +1789,10 @@ struct l2_fhdr {
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI               (1L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI               (2L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI             (4L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI             (8L<<0)
 
 #define BNX2_NVM_READ                                   0x00006410
 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
@@ -1066,6 +1803,10 @@ struct l2_fhdr {
 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI               (1L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI               (2L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI             (4L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI             (8L<<0)
 
 #define BNX2_NVM_CFG1                                   0x00006414
 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
@@ -1077,14 +1818,21 @@ struct l2_fhdr {
 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
+#define BNX2_NVM_CFG1_STRAP_CONTROL_0                    (1L<<23)
 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
+#define BNX2_NVM_CFG1_FW_USTRAP_1                        (1L<<26)
+#define BNX2_NVM_CFG1_FW_USTRAP_0                        (1L<<27)
+#define BNX2_NVM_CFG1_FW_USTRAP_2                        (1L<<28)
+#define BNX2_NVM_CFG1_FW_USTRAP_3                        (1L<<29)
+#define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN                   (1L<<30)
 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
 
 #define BNX2_NVM_CFG2                                   0x00006418
 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
+#define BNX2_NVM_CFG2_READ_ID                            (0xffL<<24)
 
 #define BNX2_NVM_CFG3                                   0x0000641c
 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
@@ -1119,6 +1867,35 @@ struct l2_fhdr {
 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
 
+#define BNX2_NVM_CFG4                                   0x0000642c
+#define BNX2_NVM_CFG4_FLASH_SIZE                         (0x7L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT                   (0L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT                   (1L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT                   (2L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT                   (3L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT                  (4L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT                  (5L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT                  (6L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT                 (7L<<0)
+#define BNX2_NVM_CFG4_FLASH_VENDOR                       (1L<<3)
+#define BNX2_NVM_CFG4_FLASH_VENDOR_ST                    (0L<<3)
+#define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL                 (1L<<3)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC             (0x3L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8        (0L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9        (1L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10       (2L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11       (3L<<4)
+#define BNX2_NVM_CFG4_STATUS_BIT_POLARITY                (1L<<6)
+#define BNX2_NVM_CFG4_RESERVED                           (0x1ffffffL<<7)
+
+#define BNX2_NVM_RECONFIG                               0x00006430
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE               (0xfL<<0)
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST            (0L<<0)
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL         (1L<<0)
+#define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE           (0xfL<<4)
+#define BNX2_NVM_RECONFIG_RESERVED                       (0x7fffffL<<8)
+#define BNX2_NVM_RECONFIG_RECONFIG_DONE                  (1L<<31)
+
 
 
 /*
@@ -1140,6 +1917,8 @@ struct l2_fhdr {
 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
+#define BNX2_DMA_STATUS_GLOBAL_ERR_XI                    (1L<<0)
+#define BNX2_DMA_STATUS_BME_XI                           (1L<<4)
 
 #define BNX2_DMA_CONFIG                                 0x00000c08
 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
@@ -1161,85 +1940,315 @@ struct l2_fhdr {
 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
+#define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI               (0x3L<<0)
+#define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI               (0x3L<<4)
+#define BNX2_DMA_CONFIG_MAX_PL_XI                        (0x7L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_128B_XI                   (0L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_256B_XI                   (1L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_512B_XI                   (2L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_EN_XI                     (1L<<15)
+#define BNX2_DMA_CONFIG_MAX_RRS_XI                       (0x7L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_128B_XI                  (0L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_256B_XI                  (1L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_512B_XI                  (2L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI                 (3L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI                 (4L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI                 (5L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_EN_XI                    (1L<<19)
+#define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI                  (1L<<31)
 
 #define BNX2_DMA_BLACKOUT                               0x00000c0c
 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
 
-#define BNX2_DMA_RCHAN_STAT                             0x00000c30
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0                    (1L<<3)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1                    (1L<<7)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2                    (1L<<11)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3                    (1L<<15)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4                    (1L<<19)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5                    (1L<<23)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6                    (1L<<27)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7                    (1L<<31)
-
-#define BNX2_DMA_WCHAN_STAT                             0x00000c34
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0                    (1L<<3)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1                    (1L<<7)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2                    (1L<<11)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3                    (1L<<15)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4                    (1L<<19)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5                    (1L<<23)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6                    (1L<<27)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7                    (1L<<31)
-
-#define BNX2_DMA_RCHAN_ASSIGNMENT                       0x00000c38
-#define BNX2_DMA_RCHAN_ASSIGNMENT_0                      (0xfL<<0)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_1                      (0xfL<<4)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_2                      (0xfL<<8)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_3                      (0xfL<<12)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_4                      (0xfL<<16)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_5                      (0xfL<<20)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_6                      (0xfL<<24)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_7                      (0xfL<<28)
-
-#define BNX2_DMA_WCHAN_ASSIGNMENT                       0x00000c3c
-#define BNX2_DMA_WCHAN_ASSIGNMENT_0                      (0xfL<<0)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_1                      (0xfL<<4)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_2                      (0xfL<<8)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_3                      (0xfL<<12)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_4                      (0xfL<<16)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_5                      (0xfL<<20)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_6                      (0xfL<<24)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_7                      (0xfL<<28)
-
-#define BNX2_DMA_RCHAN_STAT_00                          0x00000c40
-#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
-
-#define BNX2_DMA_RCHAN_STAT_01                          0x00000c44
-#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
-
-#define BNX2_DMA_RCHAN_STAT_02                          0x00000c48
-#define BNX2_DMA_RCHAN_STAT_02_LENGTH                    (0xffffL<<0)
-#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP                 (1L<<16)
-#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
-#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
-
-#define BNX2_DMA_RCHAN_STAT_10                          0x00000c4c
-#define BNX2_DMA_RCHAN_STAT_11                          0x00000c50
-#define BNX2_DMA_RCHAN_STAT_12                          0x00000c54
-#define BNX2_DMA_RCHAN_STAT_20                          0x00000c58
-#define BNX2_DMA_RCHAN_STAT_21                          0x00000c5c
+#define BNX2_DMA_READ_MASTER_SETTING_0                  0x00000c10
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP     (1L<<0)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER  (1L<<1)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY     (1L<<2)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS        (0x7L<<4)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN     (1L<<7)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP     (1L<<8)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER  (1L<<9)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY     (1L<<10)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS        (0x7L<<12)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN     (1L<<15)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP     (1L<<16)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER  (1L<<17)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY     (1L<<18)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS        (0x7L<<20)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN     (1L<<23)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP      (1L<<24)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER   (1L<<25)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY      (1L<<26)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS         (0x7L<<28)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN      (1L<<31)
+
+#define BNX2_DMA_READ_MASTER_SETTING_1                  0x00000c14
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP      (1L<<0)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER   (1L<<1)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY      (1L<<2)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS         (0x7L<<4)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN      (1L<<7)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP       (1L<<8)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER    (1L<<9)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY       (1L<<10)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS  (0x7L<<12)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN       (1L<<15)
+
+#define BNX2_DMA_WRITE_MASTER_SETTING_0                 0x00000c18
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP      (1L<<0)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER   (1L<<1)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY      (1L<<2)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD        (1L<<3)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS         (0x7L<<4)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN      (1L<<7)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP    (1L<<8)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER         (1L<<9)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY    (1L<<10)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD      (1L<<11)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS       (0x7L<<12)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN    (1L<<15)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP     (1L<<24)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER  (1L<<25)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY     (1L<<26)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD       (1L<<27)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS        (0x7L<<28)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN     (1L<<31)
+
+#define BNX2_DMA_WRITE_MASTER_SETTING_1                 0x00000c1c
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP     (1L<<0)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER  (1L<<1)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY     (1L<<2)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD       (1L<<3)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS        (0x7L<<4)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN     (1L<<7)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP      (1L<<8)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER   (1L<<9)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY      (1L<<10)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD        (1L<<11)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS         (0x7L<<12)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN      (1L<<15)
+
+#define BNX2_DMA_ARBITER                                0x00000c20
+#define BNX2_DMA_ARBITER_NUM_READS                       (0x7L<<0)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE                     (1L<<4)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT              (0L<<4)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN             (1L<<4)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE                     (0x3L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT              (0L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN             (1L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN         (2L<<5)
+#define BNX2_DMA_ARBITER_ALT_MODE_EN                     (1L<<8)
+#define BNX2_DMA_ARBITER_RR_MODE                         (1L<<9)
+#define BNX2_DMA_ARBITER_TIMER_MODE                      (1L<<10)
+#define BNX2_DMA_ARBITER_OUSTD_READ_REQ                  (0xfL<<12)
+
+#define BNX2_DMA_ARB_TIMERS                             0x00000c24
+#define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME             (0xffL<<0)
+#define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT               (0xffL<<12)
+#define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT               (0xfffL<<20)
+
+#define BNX2_DMA_DEBUG_VECT_PEEK                        0x00000c2c
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
+
+#define BNX2_DMA_TAG_RAM_00                             0x00000c30
+#define BNX2_DMA_TAG_RAM_00_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_00_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_00_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_00_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_00_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_01                             0x00000c34
+#define BNX2_DMA_TAG_RAM_01_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_01_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_01_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_01_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_01_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_02                             0x00000c38
+#define BNX2_DMA_TAG_RAM_02_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_02_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_02_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_02_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_02_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_03                             0x00000c3c
+#define BNX2_DMA_TAG_RAM_03_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_03_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_03_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_03_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_03_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_04                             0x00000c40
+#define BNX2_DMA_TAG_RAM_04_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_04_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_04_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_04_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_04_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_05                             0x00000c44
+#define BNX2_DMA_TAG_RAM_05_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_05_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_05_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_05_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_05_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_06                             0x00000c48
+#define BNX2_DMA_TAG_RAM_06_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_06_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_06_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_06_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_06_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_07                             0x00000c4c
+#define BNX2_DMA_TAG_RAM_07_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_07_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_07_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_07_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_07_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_08                             0x00000c50
+#define BNX2_DMA_TAG_RAM_08_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_08_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_08_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_08_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_08_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_09                             0x00000c54
+#define BNX2_DMA_TAG_RAM_09_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_09_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_09_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_09_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_09_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_10                             0x00000c58
+#define BNX2_DMA_TAG_RAM_10_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_10_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_10_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_10_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_10_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_11                             0x00000c5c
+#define BNX2_DMA_TAG_RAM_11_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_11_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_11_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_11_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_11_VALID                        (1L<<10)
+
 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
@@ -1336,6 +2345,25 @@ struct l2_fhdr {
  */
 #define BNX2_CTX_COMMAND                                0x00001000
 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
+#define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT               (1L<<1)
+#define BNX2_CTX_COMMAND_DISABLE_PLRU                    (1L<<2)
+#define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ            (1L<<3)
+#define BNX2_CTX_COMMAND_FLUSH_AHEAD                     (0x1fL<<8)
+#define BNX2_CTX_COMMAND_MEM_INIT                        (1L<<13)
+#define BNX2_CTX_COMMAND_PAGE_SIZE                       (0xfL<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_256                   (0L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_512                   (1L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_1K                    (2L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_2K                    (3L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_4K                    (4L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_8K                    (5L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_16K                   (6L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_32K                   (7L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_64K                   (8L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_128K                  (9L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_256K                  (10L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_512K                  (11L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_1M                    (12L<<16)
 
 #define BNX2_CTX_STATUS                                 0x00001004
 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
@@ -1343,6 +2371,13 @@ struct l2_fhdr {
 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
+#define BNX2_CTX_STATUS_EXT_READ_STAT                    (1L<<20)
+#define BNX2_CTX_STATUS_EXT_WRITE_STAT                   (1L<<21)
+#define BNX2_CTX_STATUS_MISS_STAT                        (1L<<22)
+#define BNX2_CTX_STATUS_HIT_STAT                         (1L<<23)
+#define BNX2_CTX_STATUS_DEAD_LOCK                        (1L<<24)
+#define BNX2_CTX_STATUS_USAGE_CNT_ERR                    (1L<<25)
+#define BNX2_CTX_STATUS_INVALID_PAGE                     (1L<<26)
 
 #define BNX2_CTX_VIRT_ADDR                              0x00001008
 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
@@ -1357,10 +2392,15 @@ struct l2_fhdr {
 #define BNX2_CTX_LOCK                                   0x00001018
 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
-#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
+#define BNX2_CTX_LOCK_TYPE_VOID_XI                       (0L<<0)
+#define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI                   (1L<<0)
+#define BNX2_CTX_LOCK_TYPE_TX_XI                         (2L<<0)
+#define BNX2_CTX_LOCK_TYPE_TIMER_XI                      (4L<<0)
+#define BNX2_CTX_LOCK_TYPE_COMPLETE_XI                   (7L<<0)
 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
@@ -1370,21 +2410,89 @@ struct l2_fhdr {
 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
 
+#define BNX2_CTX_CTX_CTRL                               0x0000101c
+#define BNX2_CTX_CTX_CTRL_CTX_ADDR                       (0x7ffffL<<2)
+#define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT                  (0x3L<<21)
+#define BNX2_CTX_CTX_CTRL_NO_RAM_ACC                     (1L<<23)
+#define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE                  (0x3L<<24)
+#define BNX2_CTX_CTX_CTRL_ATTR                           (1L<<26)
+#define BNX2_CTX_CTX_CTRL_WRITE_REQ                      (1L<<30)
+#define BNX2_CTX_CTX_CTRL_READ_REQ                       (1L<<31)
+
+#define BNX2_CTX_CTX_DATA                               0x00001020
 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
+#define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI       (0x1fL<<0)
+#define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI     (0x1fL<<5)
+#define BNX2_CTX_ACCESS_STATUS_REQUEST_XI                (0x3fffffL<<10)
 
 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
 
+#define BNX2_CTX_CACHE_CTRL_STATUS                      0x00001048
+#define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW        (1L<<0)
+#define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP     (1L<<1)
+#define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START           (1L<<6)
+#define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT        (0x3fL<<7)
+#define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED    (0x3fL<<13)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE       (1L<<19)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE       (1L<<20)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE       (1L<<21)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE       (1L<<22)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE       (1L<<23)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE       (1L<<24)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE       (1L<<25)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE       (1L<<26)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE       (1L<<27)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE       (1L<<28)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE      (1L<<29)
+
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS                   0x0000104c
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC             (0x7L<<0)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC          (0x7L<<3)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC           (0x7L<<6)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC          (0x7L<<9)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR   (0x7fffL<<16)
+
+#define BNX2_CTX_CACHE_STATUS                           0x00001050
+#define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES               (0x3ffL<<0)
+#define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES           (0x3ffL<<16)
+
+#define BNX2_CTX_DMA_STATUS                             0x00001054
+#define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS              (0x3L<<0)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS              (0x3L<<2)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS              (0x3L<<4)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS              (0x3L<<6)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS              (0x3L<<8)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS              (0x3L<<10)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS              (0x3L<<12)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS              (0x3L<<14)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS              (0x3L<<16)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS              (0x3L<<18)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS             (0x3L<<20)
+
+#define BNX2_CTX_REP_STATUS                             0x00001058
+#define BNX2_CTX_REP_STATUS_ERROR_ENTRY                  (0x3ffL<<0)
+#define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID              (0x1fL<<10)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR            (1L<<16)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR            (1L<<17)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR           (1L<<18)
+
+#define BNX2_CTX_CKSUM_ERROR_STATUS                     0x0000105c
+#define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
+#define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
+
 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI              (1L<<14)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI              (0x7L<<15)
 
 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
@@ -1394,6 +2502,26 @@ struct l2_fhdr {
 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
+#define BNX2_CTX_CHNL_LOCK_STATUS_9                     0x000010a4
+
+#define BNX2_CTX_CACHE_DATA                             0x000010c4
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL                     0x000010c8
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR        (0x1ffL<<0)
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ            (1L<<30)
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ             (1L<<31)
+
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0                    0x000010cc
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID               (1L<<0)
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE               (0xffffffL<<8)
+
+#define BNX2_CTX_HOST_PAGE_TBL_DATA1                    0x000010d0
+#define BNX2_CTX_CAM_CTRL                               0x000010d4
+#define BNX2_CTX_CAM_CTRL_CAM_ADDR                       (0x3ffL<<0)
+#define BNX2_CTX_CAM_CTRL_RESET                          (1L<<27)
+#define BNX2_CTX_CAM_CTRL_INVALIDATE                     (1L<<28)
+#define BNX2_CTX_CAM_CTRL_SEARCH                         (1L<<29)
+#define BNX2_CTX_CAM_CTRL_WRITE_REQ                      (1L<<30)
+#define BNX2_CTX_CAM_CTRL_READ_REQ                       (1L<<31)
 
 
 /*
@@ -1407,14 +2535,16 @@ struct l2_fhdr {
 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
-#define BNX2_EMAC_MODE_PORT_MII_10                       (3L<<2)
+#define BNX2_EMAC_MODE_PORT_MII_10M                      (3L<<2)
 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
-#define BNX2_EMAC_MODE_25G                               (1L<<5)
+#define BNX2_EMAC_MODE_25G_MODE                          (1L<<5)
 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
+#define BNX2_EMAC_MODE_SERDES_MODE                       (1L<<12)
+#define BNX2_EMAC_MODE_BOND_OVRD                         (1L<<13)
 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
@@ -1422,6 +2552,11 @@ struct l2_fhdr {
 #define BNX2_EMAC_STATUS                                0x00001404
 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
+#define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE         (1L<<13)
+#define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE           (1L<<14)
+#define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE            (1L<<16)
+#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0           (1L<<17)
+#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE    (1L<<18)
 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
@@ -1429,6 +2564,9 @@ struct l2_fhdr {
 
 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
+#define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE           (1L<<14)
+#define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE            (1L<<16)
+#define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE     (1L<<18)
 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
@@ -1445,6 +2583,13 @@ struct l2_fhdr {
 #define BNX2_EMAC_LED_100MB                              (1L<<8)
 #define BNX2_EMAC_LED_10MB                               (1L<<9)
 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
+#define BNX2_EMAC_LED_2500MB                             (1L<<11)
+#define BNX2_EMAC_LED_2500MB_OVERRIDE                    (1L<<12)
+#define BNX2_EMAC_LED_ACTIVITY_SEL                       (0x3L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_0                     (0L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_1                     (1L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_2                     (2L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_3                     (3L<<17)
 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
 
@@ -1515,9 +2660,15 @@ struct l2_fhdr {
 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS              (0L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI          (1L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI          (1L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI           (2L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI       (2L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45              (3L<<26)
 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
@@ -1534,13 +2685,17 @@ struct l2_fhdr {
 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
+#define BNX2_EMAC_MDIO_MODE_EXT_MDINT                    (1L<<13)
 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
+#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI                 (0x3fL<<16)
+#define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI                 (1L<<31)
 
 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
 
 #define BNX2_EMAC_TX_MODE                               0x000014bc
 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
+#define BNX2_EMAC_TX_MODE_CS16_TEST                      (1L<<2)
 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
@@ -1553,6 +2708,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
+#define BNX2_EMAC_TX_STATUS_CS16_ERROR                   (1L<<5)
 
 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
@@ -1586,6 +2742,10 @@ struct l2_fhdr {
 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
+#define BNX2_EMAC_CKSUM_ERROR_STATUS                    0x000014f0
+#define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
+#define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
+
 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
@@ -1608,7 +2768,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
-#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001558
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001558
 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
@@ -1661,9 +2821,9 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
-#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
@@ -1701,7 +2861,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
-#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND                 (1L<<26)
+#define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND                 (1L<<26)
 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
 
@@ -1733,6 +2893,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
 
+#define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS            0x00001574
 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
@@ -1757,6 +2918,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
+#define BNX2_EMAC_RX_STAT_AC_28                         0x000015f4
 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
@@ -1777,7 +2939,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
-#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001650
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001650
 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
@@ -1843,16 +3005,16 @@ struct l2_fhdr {
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
@@ -1887,8 +3049,11 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
-#define BNX2_EMAC_TX_STAT_AC21                          0x000016d4
 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL                    0x000016fc
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC     (0x7fL<<0)
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM     (0x7fL<<16)
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN     (1L<<31)
 
 
 /*
@@ -1909,8 +3074,15 @@ struct l2_fhdr {
 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
+#define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT               (1L<<30)
 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
 
+#define BNX2_RPM_MGMT_PKT_CTRL                          0x0000180c
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT                 (0xfL<<0)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE                 (0xfL<<4)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN           (1L<<30)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN                   (1L<<31)
+
 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
 
@@ -1931,6 +3103,7 @@ struct l2_fhdr {
 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
+#define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH                (1L<<25)
 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
 
 #define BNX2_RPM_SORT_USER1                             0x00001824
@@ -1968,11 +3141,187 @@ struct l2_fhdr {
 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0           0x00001854
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1           0x00001858
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2           0x0000185c
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3           0x00001860
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4           0x00001864
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5           0x00001868
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6           0x0000186c
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7           0x00001870
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN     (1L<<31)
+
 #define BNX2_RPM_STAT_AC0                               0x00001880
 #define BNX2_RPM_STAT_AC1                               0x00001884
 #define BNX2_RPM_STAT_AC2                               0x00001888
 #define BNX2_RPM_STAT_AC3                               0x0000188c
 #define BNX2_RPM_STAT_AC4                               0x00001890
+#define BNX2_RPM_RC_CNTL_16                             0x000018e0
+#define BNX2_RPM_RC_CNTL_16_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_16_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_16_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_16_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_16_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_16_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_16_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_16_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_16_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_16_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_16_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_16_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_16_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_16_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_16                       0x000018e4
+#define BNX2_RPM_RC_VALUE_MASK_16_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_16_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_17                             0x000018e8
+#define BNX2_RPM_RC_CNTL_17_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_17_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_17_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_17_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_17_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_17_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_17_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_17_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_17_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_17_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_17_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_17_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_17_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_17_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_17                       0x000018ec
+#define BNX2_RPM_RC_VALUE_MASK_17_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_17_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_18                             0x000018f0
+#define BNX2_RPM_RC_CNTL_18_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_18_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_18_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_18_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_18_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_18_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_18_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_18_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_18_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_18_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_18_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_18_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_18_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_18_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_18                       0x000018f4
+#define BNX2_RPM_RC_VALUE_MASK_18_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_18_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_19                             0x000018f8
+#define BNX2_RPM_RC_CNTL_19_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_19_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_19_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_19_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_19_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_19_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_19_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_19_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_19_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_19_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_19_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_19_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_19_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_19_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_19                       0x000018fc
+#define BNX2_RPM_RC_VALUE_MASK_19_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_19_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_0                              0x00001900
 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
@@ -1984,14 +3333,18 @@ struct l2_fhdr {
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP              (5L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6               (6L<<13)
 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
+#define BNX2_RPM_RC_CNTL_0_MAP_XI                        (1L<<18)
 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
+#define BNX2_RPM_RC_CNTL_0_CMDSEL_XI                     (0x1fL<<20)
 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
@@ -2006,81 +3359,518 @@ struct l2_fhdr {
 #define BNX2_RPM_RC_CNTL_1                              0x00001908
 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_1_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_1_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_1_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_1_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_1_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_1_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_1_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_1_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_1_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_1_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_1_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_1_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_1_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_1_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
+#define BNX2_RPM_RC_VALUE_MASK_1_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_1_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_2                              0x00001910
 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_2_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_2_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_2_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_2_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_2_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_2_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_2_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_2_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_2_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_2_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_2_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_2_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_2_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_2_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
+#define BNX2_RPM_RC_VALUE_MASK_2_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_2_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_3                              0x00001918
 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_3_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_3_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_3_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_3_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_3_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_3_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_3_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_3_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_3_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_3_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_3_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_3_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_3_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_3_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
+#define BNX2_RPM_RC_VALUE_MASK_3_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_3_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_4                              0x00001920
 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_4_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_4_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_4_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_4_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_4_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_4_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_4_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_4_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_4_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_4_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_4_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_4_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_4_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_4_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
+#define BNX2_RPM_RC_VALUE_MASK_4_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_4_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_5                              0x00001928
 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_5_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_5_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_5_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_5_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_5_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_5_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_5_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_5_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_5_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_5_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_5_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_5_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_5_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_5_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
+#define BNX2_RPM_RC_VALUE_MASK_5_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_5_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_6                              0x00001930
 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_6_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_6_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_6_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_6_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_6_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_6_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_6_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_6_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_6_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_6_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_6_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_6_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_6_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_6_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
+#define BNX2_RPM_RC_VALUE_MASK_6_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_6_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_7                              0x00001938
 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_7_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_7_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_7_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_7_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_7_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_7_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_7_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_7_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_7_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_7_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_7_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_7_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_7_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_7_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
+#define BNX2_RPM_RC_VALUE_MASK_7_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_7_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_8                              0x00001940
 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_8_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_8_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_8_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_8_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_8_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_8_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_8_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_8_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_8_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_8_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_8_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_8_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_8_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_8_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
+#define BNX2_RPM_RC_VALUE_MASK_8_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_8_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_9                              0x00001948
 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_9_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_9_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_9_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_9_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_9_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_9_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_9_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_9_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_9_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_9_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_9_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_9_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_9_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_9_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
+#define BNX2_RPM_RC_VALUE_MASK_9_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_9_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_10                             0x00001950
 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_10_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_10_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_10_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_10_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_10_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_10_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_10_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_10_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_10_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_10_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_10_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_10_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_10_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_10_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
+#define BNX2_RPM_RC_VALUE_MASK_10_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_10_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_11                             0x00001958
 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_11_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_11_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_11_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_11_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_11_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_11_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_11_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_11_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_11_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_11_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_11_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_11_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_11_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_11_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
+#define BNX2_RPM_RC_VALUE_MASK_11_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_11_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_12                             0x00001960
 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_12_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_12_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_12_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_12_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_12_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_12_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_12_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_12_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_12_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_12_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_12_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_12_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_12_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_12_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
+#define BNX2_RPM_RC_VALUE_MASK_12_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_12_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_13                             0x00001968
 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_13_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_13_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_13_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_13_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_13_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_13_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_13_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_13_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_13_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_13_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_13_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_13_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_13_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_13_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
+#define BNX2_RPM_RC_VALUE_MASK_13_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_13_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_14                             0x00001970
 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_14_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_14_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_14_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_14_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_14_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_14_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_14_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_14_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_14_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_14_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_14_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_14_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_14_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_14_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
+#define BNX2_RPM_RC_VALUE_MASK_14_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_14_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_15                             0x00001978
 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_15_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_15_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_15_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_15_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_15_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_15_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_15_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_15_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_15_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_15_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_15_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_15_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_15_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_15_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
+#define BNX2_RPM_RC_VALUE_MASK_15_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_15_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CONFIG                              0x00001980
 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
+#define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI                (0xfffffL<<0)
 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
+#define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE                (1L<<31)
 
 #define BNX2_RPM_DEBUG0                                 0x00001984
 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
@@ -2236,6 +4026,16 @@ struct l2_fhdr {
 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
+#define BNX2_RPM_DEBUG9_BEMEM_R_XI                       (0x1fL<<0)
+#define BNX2_RPM_DEBUG9_EO_XI                            (1L<<5)
+#define BNX2_RPM_DEBUG9_AEOF_DE_XI                       (1L<<6)
+#define BNX2_RPM_DEBUG9_SO_XI                            (1L<<7)
+#define BNX2_RPM_DEBUG9_WD64_CT_XI                       (0x1fL<<8)
+#define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI                   (0x7L<<13)
+#define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI               (0xfL<<16)
+#define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI                 (0x3ffL<<20)
+#define BNX2_RPM_DEBUG9_DATA_IN_VL_XI                    (1L<<30)
+#define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI             (1L<<31)
 
 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
@@ -2253,6 +4053,56 @@ struct l2_fhdr {
 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL                  0x00001a00
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS      (0xffffL<<0)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD           (1L<<28)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE              (1L<<29)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT              (1L<<30)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR                (1L<<31)
+
+#define BNX2_RPM_ACPI_PATTERN_CTRL                      0x00001a04
+#define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID            (0xfL<<0)
+#define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR            (1L<<30)
+#define BNX2_RPM_ACPI_PATTERN_CTRL_WR                    (1L<<31)
+
+#define BNX2_RPM_ACPI_DATA                              0x00001a08
+#define BNX2_RPM_ACPI_DATA_PATTERN_BE                    (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_LEN0                      0x00001a0c
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3          (0xffL<<0)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2          (0xffL<<8)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1          (0xffL<<16)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0          (0xffL<<24)
+
+#define BNX2_RPM_ACPI_PATTERN_LEN1                      0x00001a10
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7          (0xffL<<0)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6          (0xffL<<8)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5          (0xffL<<16)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4          (0xffL<<24)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC0                      0x00001a18
+#define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC1                      0x00001a1c
+#define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC2                      0x00001a20
+#define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC3                      0x00001a24
+#define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC4                      0x00001a28
+#define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC5                      0x00001a2c
+#define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC6                      0x00001a30
+#define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC7                      0x00001a34
+#define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7          (0xffffffffL<<0)
 
 
 /*
@@ -2263,15 +4113,20 @@ struct l2_fhdr {
 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
+#define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL                (1L<<3)
 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
+#define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE                (1L<<6)
+#define BNX2_RBUF_COMMAND_CU_ISOLATE_XI                  (1L<<5)
+#define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI               (1L<<6)
+#define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI         (1L<<7)
 
 #define BNX2_RBUF_STATUS1                               0x00200004
 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
 
 #define BNX2_RBUF_STATUS2                               0x00200008
-#define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x3ffL<<0)
-#define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x3ffL<<16)
+#define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x1ffL<<0)
+#define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x1ffL<<16)
 
 #define BNX2_RBUF_CONFIG                                0x0020000c
 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
@@ -2279,16 +4134,21 @@ struct l2_fhdr {
 
 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
+#define BNX2_RBUF_FW_BUF_ALLOC_TYPE                      (1L<<16)
+#define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ                 (1L<<31)
 
 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
+#define BNX2_RBUF_FW_BUF_FREE_TYPE                       (1L<<25)
+#define BNX2_RBUF_FW_BUF_FREE_FREE_REQ                   (1L<<31)
 
 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
+#define BNX2_RBUF_FW_BUF_SEL_SEL_REQ                     (1L<<31)
 
 #define BNX2_RBUF_CONFIG2                               0x0020001c
 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
@@ -2376,6 +4236,8 @@ struct l2_fhdr {
 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
 
 #define BNX2_RV2P_INSTR_LOW                             0x00002834
+#define BNX2_RV2P_INSTR_LOW_LOW                          (0xffffffffL<<0)
+
 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
@@ -2395,7 +4257,29 @@ struct l2_fhdr {
 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
 
-#define BNX2_RV2P_PFTQ_DATA                             0x00002b40
+#define BNX2_RV2P_MPFE_PFE_CTL                          0x00002afc
+#define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT             (1L<<0)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE                  (0xfL<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0                (0L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1                (1L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2                (2L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3                (3L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4                (4L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5                (5L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6                (6L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7                (7L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8                (8L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9                (9L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10               (10L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11               (11L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12               (12L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13               (13L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14               (14L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15               (15L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT                 (0xfL<<12)
+#define BNX2_RV2P_MPFE_PFE_CTL_OFFSET                    (0x1ffL<<16)
+
+#define BNX2_RV2P_RV2PPQ                                0x00002b40
 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
@@ -2416,7 +4300,7 @@ struct l2_fhdr {
 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
 
-#define BNX2_RV2P_TFTQ_DATA                             0x00002b80
+#define BNX2_RV2P_RV2PTQ                                0x00002b80
 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
@@ -2437,7 +4321,7 @@ struct l2_fhdr {
 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
 
-#define BNX2_RV2P_MFTQ_DATA                             0x00002bc0
+#define BNX2_RV2P_RV2PMQ                                0x00002bc0
 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
@@ -2466,18 +4350,26 @@ struct l2_fhdr {
  */
 #define BNX2_MQ_COMMAND                                 0x00003c00
 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
+#define BNX2_MQ_COMMAND_INIT                             (1L<<1)
 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
+#define BNX2_MQ_COMMAND_IDB_CFG_ERROR                    (1L<<7)
+#define BNX2_MQ_COMMAND_IDB_OVERFLOW                     (1L<<10)
+#define BNX2_MQ_COMMAND_NO_BIN_ERROR                     (1L<<11)
+#define BNX2_MQ_COMMAND_NO_MAP_ERROR                     (1L<<12)
 
 #define BNX2_MQ_STATUS                                  0x00003c04
 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
+#define BNX2_MQ_STATUS_IDB_OFLOW_STAT                    (1L<<19)
 
 #define BNX2_MQ_CONFIG                                  0x00003c08
 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
+#define BNX2_MQ_CONFIG_BIN_MQ_MODE                       (1L<<2)
+#define BNX2_MQ_CONFIG_DIS_IDB_DROP                      (1L<<3)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
@@ -2533,6 +4425,7 @@ struct l2_fhdr {
 
 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
+#define BNX2_MQ_MEM_WR_DATA2_VALUE_XI                    (0x7fffffffL<<0)
 
 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
@@ -2545,6 +4438,16 @@ struct l2_fhdr {
 
 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
+#define BNX2_MQ_MEM_RD_DATA2_VALUE_XI                    (0x7fffffffL<<0)
+
+
+/*
+ *  tsch_reg definition
+ *  offset: 0x4c00
+ */
+#define BNX2_TSCH_TSS_CFG                               0x00004c1c
+#define BNX2_TSCH_TSS_CFG_TSS_START_CID                  (0x7ffL<<8)
+#define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON                 (0xfL<<24)
 
 
 
@@ -2594,7 +4497,11 @@ struct l2_fhdr {
 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
 
-#define BNX2_TBDR_FTQ_DATA                              0x000053c0
+#define BNX2_TBDR_CKSUM_ERROR_STATUS                    0x00005010
+#define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
+#define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
+
+#define BNX2_TBDR_TBDRQ                                 0x000053c0
 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -2624,7 +4531,15 @@ struct l2_fhdr {
 #define BNX2_TDMA_COMMAND                               0x00005c00
 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
+#define BNX2_TDMA_COMMAND_CS16_ERR                       (1L<<5)
 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
+#define BNX2_TDMA_COMMAND_MASK_CS1                       (1L<<20)
+#define BNX2_TDMA_COMMAND_MASK_CS2                       (1L<<21)
+#define BNX2_TDMA_COMMAND_MASK_CS3                       (1L<<22)
+#define BNX2_TDMA_COMMAND_MASK_CS4                       (1L<<23)
+#define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR              (1L<<24)
+#define BNX2_TDMA_COMMAND_OFIFO_CLR                      (1L<<30)
+#define BNX2_TDMA_COMMAND_IFIFO_CLR                      (1L<<31)
 
 #define BNX2_TDMA_STATUS                                0x00005c04
 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
@@ -2633,10 +4548,18 @@ struct l2_fhdr {
 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
+#define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH                 (0x3fL<<20)
+#define BNX2_TDMA_STATUS_OFIFO_OVERFLOW                  (1L<<30)
+#define BNX2_TDMA_STATUS_IFIFO_OVERFLOW                  (1L<<31)
 
 #define BNX2_TDMA_CONFIG                                0x00005c08
 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN                    (0x3L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0                  (0L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1                  (1L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2                  (2L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3                  (3L<<2)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
@@ -2649,7 +4572,35 @@ struct l2_fhdr {
 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
+#define BNX2_TDMA_CONFIG_CMPL_ENTRY                      (1L<<17)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP                       (1L<<19)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP_3                     (0L<<19)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP_2                     (1L<<19)
 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI                  (0x7L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI                (0L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI                (1L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI                (2L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI               (3L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI               (4L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI               (5L<<20)
+#define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI                  (1L<<23)
+#define BNX2_TDMA_CONFIG_BYTES_OST_XI                    (0x7L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_512_XI                (0L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI               (1L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI               (2L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI               (3L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI               (4L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI              (5L<<24)
+#define BNX2_TDMA_CONFIG_HC_BYPASS_XI                    (1L<<27)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_XI                     (0x7L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI                 (0L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI                 (1L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI                 (2L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI                (3L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI                (4L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI                (5L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI                  (1L<<31)
 
 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
@@ -2685,7 +4636,22 @@ struct l2_fhdr {
 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
 
-#define BNX2_TDMA_FTQ_DATA                              0x00005fc0
+#define BNX2_TDMA_PUSH_FSM                              0x00005c90
+#define BNX2_TDMA_BD_IF_DEBUG                           0x00005c94
+#define BNX2_TDMA_DMAD_IF_DEBUG                         0x00005c98
+#define BNX2_TDMA_CTX_IF_DEBUG                          0x00005c9c
+#define BNX2_TDMA_TPBUF_IF_DEBUG                        0x00005ca0
+#define BNX2_TDMA_DR_IF_DEBUG                           0x00005ca4
+#define BNX2_TDMA_TPATQ_IF_DEBUG                        0x00005ca8
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM                      0x00005cac
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED            (0xffffL<<0)
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED              (0xffffL<<16)
+
+#define BNX2_TDMA_TDMA_PCIE_CKSUM                       0x00005cb0
+#define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED             (0xffffL<<0)
+#define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED               (0xffffL<<16)
+
+#define BNX2_TDMA_TDMAQ                                 0x00005fc0
 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -2724,6 +4690,8 @@ struct l2_fhdr {
 #define BNX2_HC_COMMAND_FORCE_INT_LOW                    (2L<<19)
 #define BNX2_HC_COMMAND_FORCE_INT_FREE                   (3L<<19)
 #define BNX2_HC_COMMAND_CLR_STAT_NOW                     (1L<<21)
+#define BNX2_HC_COMMAND_MAIN_PWR_INT                     (1L<<22)
+#define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT               (1L<<27)
 
 #define BNX2_HC_STATUS                                  0x00006804
 #define BNX2_HC_STATUS_MASTER_ABORT                      (1L<<0)
@@ -2746,6 +4714,23 @@ struct l2_fhdr {
 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY                (1L<<5)
 #define BNX2_HC_CONFIG_STATUS_PRIORITY                   (1L<<6)
 #define BNX2_HC_CONFIG_STAT_MEM_ADDR                     (0xffL<<8)
+#define BNX2_HC_CONFIG_PER_MODE                          (1L<<16)
+#define BNX2_HC_CONFIG_ONE_SHOT                          (1L<<17)
+#define BNX2_HC_CONFIG_USE_INT_PARAM                     (1L<<18)
+#define BNX2_HC_CONFIG_SET_MASK_AT_RD                    (1L<<19)
+#define BNX2_HC_CONFIG_PER_COLLECT_LIMIT                 (0xfL<<20)
+#define BNX2_HC_CONFIG_SB_ADDR_INC                       (0x7L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_64B                   (0L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_128B                  (1L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_256B                  (2L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_512B                  (3L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_1024B                 (4L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_2048B                 (5L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_4096B                 (6L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_8192B                 (7L<<24)
+#define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR                 (1L<<29)
+#define BNX2_HC_CONFIG_UNMASK_ALL                        (1L<<30)
+#define BNX2_HC_CONFIG_TX_SEL                            (1L<<31)
 
 #define BNX2_HC_ATTN_BITS_ENABLE                        0x0000680c
 #define BNX2_HC_STATUS_ADDR_L                           0x00006810
@@ -2782,6 +4767,7 @@ struct l2_fhdr {
 
 #define BNX2_HC_PERIODIC_TICKS                          0x0000683c
 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS         (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS     (0xffffL<<16)
 
 #define BNX2_HC_STAT_COLLECT_TICKS                      0x00006840
 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
@@ -2789,6 +4775,10 @@ struct l2_fhdr {
 #define BNX2_HC_STATS_TICKS                             0x00006844
 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS                (0xffffL<<8)
 
+#define BNX2_HC_STATS_INTERRUPT_STATUS                  0x00006848
+#define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS         (0x1ffL<<0)
+#define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS        (0x1ffL<<16)
+
 #define BNX2_HC_STAT_MEM_DATA                           0x0000684c
 #define BNX2_HC_STAT_GEN_SEL_0                          0x00006850
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                 (0x7fL<<0)
@@ -2917,24 +4907,108 @@ struct l2_fhdr {
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2                 (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3                 (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI    (52L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI    (57L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI    (58L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI    (85L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI    (86L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI    (87L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI    (88L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI    (89L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI    (90L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI    (91L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI    (92L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI   (93L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI         (94L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI       (123L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI       (124L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI     (125L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI   (126L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI    (128L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI  (129L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI      (130L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI       (131L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI       (132L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI   (133L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI    (134L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI  (135L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI      (136L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI       (137L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI       (138L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI   (139L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI    (140L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI  (141L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI      (142L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI       (143L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI       (144L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI   (145L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI    (146L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI  (147L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI      (148L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI       (149L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI       (150L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI   (151L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI    (152L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI  (153L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI      (154L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI       (155L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI       (156L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI   (157L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI    (158L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI  (159L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI      (160L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI       (161L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI       (162L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI   (163L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI    (164L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI  (165L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI      (166L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI       (167L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI       (168L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI   (169L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI    (170L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI  (171L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI      (172L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI       (173L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI       (174L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI   (175L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI       (176L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI      (177L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI    (178L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI              (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI              (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_1                          0x00006854
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4                 (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6                 (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7                 (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI              (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI              (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_2                          0x00006858
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8                 (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10                (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11                (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI             (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI             (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_3                          0x0000685c
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12                (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13                (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14                (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15                (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI             (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI             (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI             (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI             (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_STAT0                          0x00006888
 #define BNX2_HC_STAT_GEN_STAT1                          0x0000688c
@@ -2968,6 +5042,7 @@ struct l2_fhdr {
 #define BNX2_HC_STAT_GEN_STAT_AC13                      0x000068fc
 #define BNX2_HC_STAT_GEN_STAT_AC14                      0x00006900
 #define BNX2_HC_STAT_GEN_STAT_AC15                      0x00006904
+#define BNX2_HC_STAT_GEN_STAT_AC                        0x000068c8
 #define BNX2_HC_VIS                                     0x00006908
 #define BNX2_HC_VIS_STAT_BUILD_STATE                     (0xfL<<0)
 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE                (0L<<0)
@@ -3038,6 +5113,349 @@ struct l2_fhdr {
 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN                (1L<<27)
 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL                    (0xfL<<28)
 
+#define BNX2_HC_COALESCE_NOW                            0x00006914
+#define BNX2_HC_COALESCE_NOW_COAL_NOW                    (0x1ffL<<1)
+#define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT             (0x1ffL<<11)
+#define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT           (0x1ffL<<21)
+
+#define BNX2_HC_MSIX_BIT_VECTOR                         0x00006918
+#define BNX2_HC_MSIX_BIT_VECTOR_VAL                      (0x1ffL<<0)
+
+#define BNX2_HC_SB_CONFIG_1                             0x00006a00
+#define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_1_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_1_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1                    0x00006a04
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_1                        0x00006a08
+#define BNX2_HC_COMP_PROD_TRIP_1_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_1_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1                    0x00006a0c
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_1                              0x00006a10
+#define BNX2_HC_RX_TICKS_1_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_1_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_1                              0x00006a14
+#define BNX2_HC_TX_TICKS_1_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_1_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_1                             0x00006a18
+#define BNX2_HC_COM_TICKS_1_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_1_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_1                             0x00006a1c
+#define BNX2_HC_CMD_TICKS_1_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_1_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_1                        0x00006a20
+#define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_2                             0x00006a24
+#define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_2_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_2_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2                    0x00006a28
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_2                        0x00006a2c
+#define BNX2_HC_COMP_PROD_TRIP_2_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_2_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2                    0x00006a30
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_2                              0x00006a34
+#define BNX2_HC_RX_TICKS_2_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_2_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_2                              0x00006a38
+#define BNX2_HC_TX_TICKS_2_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_2_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_2                             0x00006a3c
+#define BNX2_HC_COM_TICKS_2_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_2_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_2                             0x00006a40
+#define BNX2_HC_CMD_TICKS_2_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_2_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_2                        0x00006a44
+#define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_3                             0x00006a48
+#define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_3_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_3_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3                    0x00006a4c
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_3                        0x00006a50
+#define BNX2_HC_COMP_PROD_TRIP_3_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_3_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3                    0x00006a54
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_3                              0x00006a58
+#define BNX2_HC_RX_TICKS_3_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_3_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_3                              0x00006a5c
+#define BNX2_HC_TX_TICKS_3_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_3_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_3                             0x00006a60
+#define BNX2_HC_COM_TICKS_3_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_3_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_3                             0x00006a64
+#define BNX2_HC_CMD_TICKS_3_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_3_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_3                        0x00006a68
+#define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_4                             0x00006a6c
+#define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_4_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_4_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4                    0x00006a70
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_4                        0x00006a74
+#define BNX2_HC_COMP_PROD_TRIP_4_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_4_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4                    0x00006a78
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_4                              0x00006a7c
+#define BNX2_HC_RX_TICKS_4_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_4_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_4                              0x00006a80
+#define BNX2_HC_TX_TICKS_4_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_4_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_4                             0x00006a84
+#define BNX2_HC_COM_TICKS_4_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_4_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_4                             0x00006a88
+#define BNX2_HC_CMD_TICKS_4_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_4_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_4                        0x00006a8c
+#define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_5                             0x00006a90
+#define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_5_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_5_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5                    0x00006a94
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_5                        0x00006a98
+#define BNX2_HC_COMP_PROD_TRIP_5_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_5_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5                    0x00006a9c
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_5                              0x00006aa0
+#define BNX2_HC_RX_TICKS_5_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_5_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_5                              0x00006aa4
+#define BNX2_HC_TX_TICKS_5_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_5_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_5                             0x00006aa8
+#define BNX2_HC_COM_TICKS_5_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_5_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_5                             0x00006aac
+#define BNX2_HC_CMD_TICKS_5_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_5_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_5                        0x00006ab0
+#define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_6                             0x00006ab4
+#define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_6_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_6_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6                    0x00006ab8
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_6                        0x00006abc
+#define BNX2_HC_COMP_PROD_TRIP_6_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_6_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6                    0x00006ac0
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_6                              0x00006ac4
+#define BNX2_HC_RX_TICKS_6_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_6_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_6                              0x00006ac8
+#define BNX2_HC_TX_TICKS_6_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_6_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_6                             0x00006acc
+#define BNX2_HC_COM_TICKS_6_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_6_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_6                             0x00006ad0
+#define BNX2_HC_CMD_TICKS_6_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_6_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_6                        0x00006ad4
+#define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_7                             0x00006ad8
+#define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_7_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_7_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7                    0x00006adc
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_7                        0x00006ae0
+#define BNX2_HC_COMP_PROD_TRIP_7_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_7_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7                    0x00006ae4
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_7                              0x00006ae8
+#define BNX2_HC_RX_TICKS_7_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_7_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_7                              0x00006aec
+#define BNX2_HC_TX_TICKS_7_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_7_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_7                             0x00006af0
+#define BNX2_HC_COM_TICKS_7_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_7_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_7                             0x00006af4
+#define BNX2_HC_CMD_TICKS_7_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_7_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_7                        0x00006af8
+#define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_8                             0x00006afc
+#define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_8_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_8_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8                    0x00006b00
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_8                        0x00006b04
+#define BNX2_HC_COMP_PROD_TRIP_8_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_8_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8                    0x00006b08
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_8                              0x00006b0c
+#define BNX2_HC_RX_TICKS_8_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_8_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_8                              0x00006b10
+#define BNX2_HC_TX_TICKS_8_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_8_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_8                             0x00006b14
+#define BNX2_HC_COM_TICKS_8_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_8_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_8                             0x00006b18
+#define BNX2_HC_CMD_TICKS_8_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_8_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_8                        0x00006b1c
+#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
 
 
 /*
@@ -3063,7 +5481,7 @@ struct l2_fhdr {
 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_TXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_TXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3111,7 +5529,7 @@ struct l2_fhdr {
 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_TXP_CPU_REG_FILE                           0x00045200
-#define BNX2_TXP_FTQ_DATA                               0x000453c0
+#define BNX2_TXP_TXPQ                                   0x000453c0
 #define BNX2_TXP_FTQ_CMD                                0x000453f8
 #define BNX2_TXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
 #define BNX2_TXP_FTQ_CMD_WR_TOP                          (1L<<10)
@@ -3158,7 +5576,7 @@ struct l2_fhdr {
 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED         (1L<<5)
-#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED                (1L<<6)
+#define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED                (1L<<6)
 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED                 (1L<<7)
 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED                  (1L<<10)
@@ -3206,7 +5624,7 @@ struct l2_fhdr {
 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
 
 #define BNX2_TPAT_CPU_REG_FILE                          0x00085200
-#define BNX2_TPAT_FTQ_DATA                              0x000853c0
+#define BNX2_TPAT_TPATQ                                 0x000853c0
 #define BNX2_TPAT_FTQ_CMD                               0x000853f8
 #define BNX2_TPAT_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TPAT_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -3253,7 +5671,7 @@ struct l2_fhdr {
 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_RXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_RXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3301,7 +5719,29 @@ struct l2_fhdr {
 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_RXP_CPU_REG_FILE                           0x000c5200
-#define BNX2_RXP_CFTQ_DATA                              0x000c5380
+#define BNX2_RXP_PFE_PFE_CTL                            0x000c537c
+#define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT               (1L<<0)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE                    (0xfL<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0                  (0L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1                  (1L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2                  (2L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3                  (3L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4                  (4L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5                  (5L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6                  (6L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7                  (7L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8                  (8L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9                  (9L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10                 (10L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11                 (11L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12                 (12L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13                 (13L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14                 (14L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15                 (15L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT                   (0xfL<<12)
+#define BNX2_RXP_PFE_PFE_CTL_OFFSET                      (0x1ffL<<16)
+
+#define BNX2_RXP_RXPCQ                                  0x000c5380
 #define BNX2_RXP_CFTQ_CMD                               0x000c53b8
 #define BNX2_RXP_CFTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_RXP_CFTQ_CMD_WR_TOP                         (1L<<10)
@@ -3322,7 +5762,7 @@ struct l2_fhdr {
 #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
 #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
 
-#define BNX2_RXP_FTQ_DATA                               0x000c53c0
+#define BNX2_RXP_RXPQ                                   0x000c53c0
 #define BNX2_RXP_FTQ_CMD                                0x000c53f8
 #define BNX2_RXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
 #define BNX2_RXP_FTQ_CMD_WR_TOP                          (1L<<10)
@@ -3350,6 +5790,10 @@ struct l2_fhdr {
  *  com_reg definition
  *  offset: 0x100000
  */
+#define BNX2_COM_CKSUM_ERROR_STATUS                     0x00100000
+#define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
+#define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
+
 #define BNX2_COM_CPU_MODE                               0x00105000
 #define BNX2_COM_CPU_MODE_LOCAL_RST                      (1L<<0)
 #define BNX2_COM_CPU_MODE_STEP_ENA                       (1L<<1)
@@ -3369,7 +5813,7 @@ struct l2_fhdr {
 #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_COM_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_COM_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_COM_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_COM_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3417,7 +5861,29 @@ struct l2_fhdr {
 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_COM_CPU_REG_FILE                           0x00105200
-#define BNX2_COM_COMXQ_FTQ_DATA                         0x00105340
+#define BNX2_COM_COMTQ_PFE_PFE_CTL                      0x001052bc
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT         (1L<<0)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE              (0xfL<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0            (0L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1            (1L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2            (2L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3            (3L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4            (4L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5            (5L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6            (6L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7            (7L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8            (8L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9            (9L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10           (10L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11           (11L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12           (12L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13           (13L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14           (14L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15           (15L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT             (0xfL<<12)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET                (0x1ffL<<16)
+
+#define BNX2_COM_COMXQ                                  0x00105340
 #define BNX2_COM_COMXQ_FTQ_CMD                          0x00105378
 #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP                    (1L<<10)
@@ -3438,7 +5904,7 @@ struct l2_fhdr {
 #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
 #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
 
-#define BNX2_COM_COMTQ_FTQ_DATA                         0x00105380
+#define BNX2_COM_COMTQ                                  0x00105380
 #define BNX2_COM_COMTQ_FTQ_CMD                          0x001053b8
 #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP                    (1L<<10)
@@ -3459,7 +5925,7 @@ struct l2_fhdr {
 #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
 #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
 
-#define BNX2_COM_COMQ_FTQ_DATA                          0x001053c0
+#define BNX2_COM_COMQ                                   0x001053c0
 #define BNX2_COM_COMQ_FTQ_CMD                           0x001053f8
 #define BNX2_COM_COMQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP                     (1L<<10)
@@ -3489,6 +5955,10 @@ struct l2_fhdr {
  *  cp_reg definition
  *  offset: 0x180000
  */
+#define BNX2_CP_CKSUM_ERROR_STATUS                      0x00180000
+#define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED            (0xffffL<<0)
+#define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED              (0xffffL<<16)
+
 #define BNX2_CP_CPU_MODE                                0x00185000
 #define BNX2_CP_CPU_MODE_LOCAL_RST                       (1L<<0)
 #define BNX2_CP_CPU_MODE_STEP_ENA                        (1L<<1)
@@ -3508,7 +5978,7 @@ struct l2_fhdr {
 #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
 #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
 #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
-#define BNX2_CP_CPU_STATE_BAD_pc_HALTED                  (1L<<6)
+#define BNX2_CP_CPU_STATE_BAD_PC_HALTED                  (1L<<6)
 #define BNX2_CP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
 #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
 #define BNX2_CP_CPU_STATE_SOFT_HALTED                    (1L<<10)
@@ -3556,7 +6026,29 @@ struct l2_fhdr {
 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
 
 #define BNX2_CP_CPU_REG_FILE                            0x00185200
-#define BNX2_CP_CPQ_FTQ_DATA                            0x001853c0
+#define BNX2_CP_CPQ_PFE_PFE_CTL                         0x001853bc
+#define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT            (1L<<0)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE                 (0xfL<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0               (0L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1               (1L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2               (2L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3               (3L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4               (4L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5               (5L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6               (6L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7               (7L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8               (8L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9               (9L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10              (10L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11              (11L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12              (12L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13              (13L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14              (14L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15              (15L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT                (0xfL<<12)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET                   (0x1ffL<<16)
+
+#define BNX2_CP_CPQ                                     0x001853c0
 #define BNX2_CP_CPQ_FTQ_CMD                             0x001853f8
 #define BNX2_CP_CPQ_FTQ_CMD_OFFSET                       (0x3ffL<<0)
 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP                       (1L<<10)
@@ -3584,6 +6076,59 @@ struct l2_fhdr {
  *  mcp_reg definition
  *  offset: 0x140000
  */
+#define BNX2_MCP_MCP_CONTROL                            0x00140080
+#define BNX2_MCP_MCP_CONTROL_SMBUS_SEL                   (1L<<30)
+#define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE                 (1L<<31)
+
+#define BNX2_MCP_MCP_ATTENTION_STATUS                   0x00140084
+#define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL       (1L<<29)
+#define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT   (1L<<30)
+#define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT          (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT_CONTROL                  0x00140088
+#define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE      (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS                   0x0014008c
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD       (0x7ffL<<0)
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID              (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT                          0x00140090
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT       (0x3fffffffL<<0)
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC         (1L<<30)
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET       (1L<<31)
+
+#define BNX2_MCP_WATCHDOG_RESET                         0x00140094
+#define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET           (1L<<31)
+
+#define BNX2_MCP_WATCHDOG_CONTROL                       0x00140098
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT       (0xfffffffL<<0)
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN          (1L<<29)
+#define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE         (1L<<30)
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE        (1L<<31)
+
+#define BNX2_MCP_ACCESS_LOCK                            0x0014009c
+#define BNX2_MCP_ACCESS_LOCK_LOCK                        (1L<<31)
+
+#define BNX2_MCP_TOE_ID                                 0x001400a0
+#define BNX2_MCP_TOE_ID_FUNCTION_ID                      (1L<<31)
+
+#define BNX2_MCP_MAILBOX_CFG                            0x001400a4
+#define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET              (0x3fffL<<0)
+#define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE                (0xfffL<<20)
+
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC                 0x001400a8
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET   (0x3fffL<<0)
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE     (0xfffL<<20)
+
+#define BNX2_MCP_MCP_DOORBELL                           0x001400ac
+#define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL               (1L<<31)
+
+#define BNX2_MCP_DRIVER_DOORBELL                        0x001400b0
+#define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL         (1L<<31)
+
+#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC             0x001400b4
+#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL      (1L<<31)
+
 #define BNX2_MCP_CPU_MODE                               0x00145000
 #define BNX2_MCP_CPU_MODE_LOCAL_RST                      (1L<<0)
 #define BNX2_MCP_CPU_MODE_STEP_ENA                       (1L<<1)
@@ -3603,7 +6148,7 @@ struct l2_fhdr {
 #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_MCP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_MCP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_MCP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -3651,7 +6196,7 @@ struct l2_fhdr {
 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_MCP_CPU_REG_FILE                           0x00145200
-#define BNX2_MCP_MCPQ_FTQ_DATA                          0x001453c0
+#define BNX2_MCP_MCPQ                                   0x001453c0
 #define BNX2_MCP_MCPQ_FTQ_CMD                           0x001453f8
 #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP                     (1L<<10)
@@ -3696,6 +6241,8 @@ struct l2_fhdr {
 
 /* 5708 Serdes PHY registers */
 
+#define BCM5708S_BMCR_FORCE_2500                0x20
+
 #define BCM5708S_UP1                            0xb
 
 #define BCM5708S_UP1_2G5                        0x1
@@ -3804,6 +6351,7 @@ struct l2_fhdr {
 #define INVALID_CID_ADDR            0xffffffff
 
 #define TX_CID          16
+#define TX_TSS_CID      32
 #define RX_CID          0
 
 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
@@ -3889,6 +6437,8 @@ struct bnx2 {
 
         u32             tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
         u16             tx_prod;
+        u32             tx_bidx_addr;
+        u32             tx_bseq_addr;
 
         u16             tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
         u16             hw_tx_cons;
@@ -3945,6 +6495,7 @@ struct bnx2 {
 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
 #define CHIP_NUM_5706                   0x57060000
 #define CHIP_NUM_5708                   0x57080000
+#define CHIP_NUM_5709                   0x57090000
 
 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
 #define CHIP_REV_Ax                     0x00000000
@@ -4007,6 +6558,10 @@ struct bnx2 {
         struct statistics_block *stats_blk;
         dma_addr_t              stats_blk_mapping;
 
+        int                     ctx_pages;
+        void                    *ctx_blk[4];
+        dma_addr_t              ctx_blk_mapping[4];
+
         u32                     hc_cmd;
         u32                     rx_mode;
 
@@ -4038,6 +6593,7 @@ struct bnx2 {
 
         u8                      serdes_an_pending;
 #define SERDES_AN_TIMEOUT       (HZ / 3)
+#define SERDES_FORCED_TIMEOUT   (HZ / 10)
 
         u8                      mac_addr[8];
 
@@ -4104,41 +6660,43 @@ struct cpu_reg {
 };
 
 struct fw_info {
-        u32 ver_major;
-        u32 ver_minor;
-        u32 ver_fix;
+        const u32 ver_major;
+        const u32 ver_minor;
+        const u32 ver_fix;
 
-        u32 start_addr;
+        const u32 start_addr;
 
         /* Text section. */
-        u32 text_addr;
-        u32 text_len;
-        u32 text_index;
+        const u32 text_addr;
+        const u32 text_len;
+        const u32 text_index;
         u32 *text;
+        u8 *gz_text;
+        const u32 gz_text_len;
 
         /* Data section. */
-        u32 data_addr;
-        u32 data_len;
-        u32 data_index;
-        u32 *data;
+        const u32 data_addr;
+        const u32 data_len;
+        const u32 data_index;
+        const u32 *data;
 
         /* SBSS section. */
-        u32 sbss_addr;
-        u32 sbss_len;
-        u32 sbss_index;
-        u32 *sbss;
+        const u32 sbss_addr;
+        const u32 sbss_len;
+        const u32 sbss_index;
+        const u32 *sbss;
 
         /* BSS section. */
-        u32 bss_addr;
-        u32 bss_len;
-        u32 bss_index;
-        u32 *bss;
+        const u32 bss_addr;
+        const u32 bss_len;
+        const u32 bss_index;
+        const u32 *bss;
 
         /* Read-only section. */
-        u32 rodata_addr;
-        u32 rodata_len;
-        u32 rodata_index;
-        u32 *rodata;
+        const u32 rodata_addr;
+        const u32 rodata_len;
+        const u32 rodata_index;
+        const u32 *rodata;
 };
 
 #define RV2P_PROC1                              0
diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h
index 2d753dca0d75..21d368ff424d 100644
--- a/drivers/net/bnx2_fw.h
+++ b/drivers/net/bnx2_fw.h
@@ -14,20 +14,6 @@
  * accompanying it.
  */
 
-static const int bnx2_COM_b06FwReleaseMajor = 0x1;
-static const int bnx2_COM_b06FwReleaseMinor = 0x0;
-static const int bnx2_COM_b06FwReleaseFix = 0x0;
-static const u32 bnx2_COM_b06FwStartAddr = 0x080008b4;
-static const u32 bnx2_COM_b06FwTextAddr = 0x08000000;
-static const int bnx2_COM_b06FwTextLen = 0x57bc;
-static const u32 bnx2_COM_b06FwDataAddr = 0x08005840;
-static const int bnx2_COM_b06FwDataLen = 0x0;
-static const u32 bnx2_COM_b06FwRodataAddr = 0x080057c0;
-static const int bnx2_COM_b06FwRodataLen = 0x58;
-static const u32 bnx2_COM_b06FwBssAddr = 0x08005860;
-static const int bnx2_COM_b06FwBssLen = 0x88;
-static const u32 bnx2_COM_b06FwSbssAddr = 0x08005840;
-static const int bnx2_COM_b06FwSbssLen = 0x1c;
 static u8 bnx2_COM_b06FwText[] = {
         0x1f, 0x8b, 0x08, 0x08, 0x09, 0x83, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
         0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5b, 0x7d, 0x6c,
@@ -673,389 +659,752 @@ static u32 bnx2_COM_b06FwRodata[(0x58/4) + 1] = {
 static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 };
 static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
 
-static int bnx2_RXP_b06FwReleaseMajor = 0x1;
-static int bnx2_RXP_b06FwReleaseMinor = 0x0;
-static int bnx2_RXP_b06FwReleaseFix = 0x0;
-static u32 bnx2_RXP_b06FwStartAddr = 0x08003184;
-static u32 bnx2_RXP_b06FwTextAddr = 0x08000000;
-static int bnx2_RXP_b06FwTextLen = 0x588c;
-static u32 bnx2_RXP_b06FwDataAddr = 0x080058e0;
-static int bnx2_RXP_b06FwDataLen = 0x0;
-static u32 bnx2_RXP_b06FwRodataAddr = 0x08005890;
-static int bnx2_RXP_b06FwRodataLen = 0x28;
-static u32 bnx2_RXP_b06FwBssAddr = 0x08005900;
-static int bnx2_RXP_b06FwBssLen = 0x13a4;
-static u32 bnx2_RXP_b06FwSbssAddr = 0x080058e0;
-static int bnx2_RXP_b06FwSbssLen = 0x1c;
+static struct fw_info bnx2_com_fw_06 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x080008b4,
+
+        .text_addr                      = 0x08000000,
+        .text_len                       = 0x57bc,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_COM_b06FwText,
+        .gz_text_len                    = sizeof(bnx2_COM_b06FwText),
+
+        .data_addr                      = 0x08005840,
+        .data_len                       = 0x0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_COM_b06FwData,
+
+        .sbss_addr                      = 0x08005840,
+        .sbss_len                       = 0x1c,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_COM_b06FwSbss,
+
+        .bss_addr                       = 0x08005860,
+        .bss_len                        = 0x88,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_COM_b06FwBss,
+
+        .rodata_addr                    = 0x080057c0,
+        .rodata_len                     = 0x58,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_COM_b06FwRodata,
+};
+
 static u8 bnx2_RXP_b06FwText[] = {
-        0x1f, 0x8b, 0x08, 0x08, 0x07, 0x87, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
-        0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x5d, 0x6c,
-        0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x43, 0x71, 0x49, 0x91, 0xd4, 0x70, 0xb9,
-        0x62, 0x57, 0x12, 0x65, 0xed, 0x8a, 0x43, 0x71, 0x6d, 0x31, 0xce, 0x50,
-        0x58, 0xdb, 0x82, 0xb1, 0x48, 0xc7, 0xb3, 0xa4, 0xc8, 0x24, 0x02, 0x42,
-        0x1b, 0x42, 0xab, 0xa4, 0xa9, 0xc1, 0x90, 0x72, 0x91, 0x22, 0x2c, 0xa0,
-        0x1a, 0x79, 0xf0, 0x43, 0x10, 0x2f, 0x56, 0x3f, 0xa6, 0xd1, 0x8d, 0x96,
-        0xb6, 0x1c, 0x53, 0x08, 0x82, 0x82, 0xe5, 0x52, 0x52, 0x0b, 0x2c, 0xb4,
-        0x96, 0xed, 0x36, 0x7e, 0xa8, 0x23, 0x9a, 0x92, 0x8d, 0xa6, 0x68, 0x81,
-        0x22, 0xad, 0xd1, 0xf4, 0x4d, 0x95, 0x9a, 0x4a, 0x75, 0x5f, 0xd4, 0xa2,
-        0x48, 0xda, 0x46, 0xcd, 0xf4, 0xfb, 0xee, 0xcc, 0x88, 0xd4, 0x9a, 0xb2,
-        0x2c, 0x3b, 0x0d, 0x62, 0x74, 0x0e, 0x30, 0xd8, 0xb9, 0x7f, 0xe7, 0xef,
-        0x9e, 0x73, 0xee, 0x39, 0x77, 0x28, 0x7d, 0xa5, 0x43, 0xda, 0x25, 0x84,
-        0x4e, 0x3c, 0x99, 0xc3, 0xcf, 0x3c, 0xfd, 0xe0, 0xc3, 0x0f, 0xee, 0xc1,
-        0xeb, 0xb0, 0xa1, 0x6d, 0xd0, 0xa3, 0xfe, 0x18, 0x62, 0x88, 0x21, 0x86,
-        0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62,
-        0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21,
-        0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18,
-        0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88,
-        0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0xff, 0xef, 0x60, 0x88, 0x58,
-        0xfc, 0xed, 0x0c, 0x1f, 0x49, 0xe8, 0x85, 0xcb, 0x07, 0x3d, 0x5b, 0x12,
-        0x46, 0x61, 0x69, 0x66, 0xda, 0x16, 0x71, 0xeb, 0xbb, 0x33, 0x45, 0xf9,
-        0x1f, 0xbf, 0x94, 0x32, 0x85, 0xfd, 0xdb, 0x0b, 0x37, 0x9f, 0x7d, 0xf3,
-        0x91, 0xec, 0x8d, 0x05, 0x43, 0x12, 0x56, 0xe1, 0xe8, 0xb0, 0xb5, 0x4b,
-        0x12, 0x7d, 0x58, 0xf3, 0xdd, 0xc1, 0xcf, 0x59, 0xd2, 0x15, 0xe1, 0xba,
-        0xee, 0xbf, 0x39, 0x68, 0xc9, 0x2b, 0x8d, 0x94, 0x5c, 0x68, 0x6c, 0xdf,
-        0x24, 0x5d, 0xd9, 0x52, 0x09, 0xfd, 0x6e, 0x8a, 0xe3, 0x96, 0x94, 0xab,
-        0x2d, 0xe2, 0x2a, 0xba, 0x7d, 0x5a, 0x71, 0xfe, 0x3e, 0xcd, 0x9b, 0x7f,
-        0x9e, 0xff, 0x1e, 0x24, 0xa5, 0xcb, 0x7d, 0x68, 0xf7, 0xa1, 0xcd, 0xf7,
-        0x81, 0xf4, 0x94, 0x98, 0x72, 0xa4, 0x91, 0x90, 0xa3, 0xd5, 0x8c, 0xe8,
-        0x05, 0x71, 0xbd, 0xbc, 0x9d, 0x2e, 0xa3, 0x6f, 0xea, 0x00, 0xdb, 0x29,
-        0xe0, 0xf9, 0x0e, 0xd7, 0x59, 0x5e, 0x5e, 0x4a, 0xb7, 0xc6, 0x14, 0x0d,
-        0x8e, 0xb1, 0x0f, 0xbf, 0x58, 0x5f, 0xae, 0x76, 0x00, 0x6f, 0xd6, 0x71,
-        0x41, 0xdc, 0x73, 0x2c, 0xd0, 0xf6, 0xfd, 0xdf, 0x75, 0x32, 0xb2, 0xe2,
-        0x74, 0x81, 0xa7, 0x16, 0x69, 0xb5, 0xc5, 0xd2, 0x0b, 0xb6, 0xb5, 0x22,
-        0x6d, 0x1c, 0xeb, 0x34, 0x0a, 0xbe, 0x3f, 0x9d, 0x97, 0xae, 0xa0, 0x6f,
-        0xb7, 0xe2, 0x63, 0x72, 0x42, 0xc3, 0xbc, 0x57, 0x49, 0x0f, 0x3a, 0xe2,
-        0x3b, 0x7f, 0xf3, 0x52, 0xac, 0x6c, 0x97, 0xc9, 0x54, 0xf6, 0xa0, 0x1b,
-        0xd0, 0x74, 0x3d, 0x67, 0x2b, 0x70, 0x6a, 0xe0, 0x4f, 0xdb, 0x81, 0xf5,
-        0xee, 0x0a, 0x68, 0x1a, 0x85, 0xcd, 0x62, 0x6c, 0x66, 0x9f, 0xe8, 0x3b,
-        0x87, 0x93, 0xe1, 0x78, 0x97, 0x36, 0x32, 0x6f, 0x88, 0x6e, 0xff, 0x81,
-        0xe6, 0xd5, 0x7a, 0xe5, 0xd8, 0xbc, 0x8e, 0x77, 0x5d, 0xae, 0xe6, 0x4b,
-        0x9a, 0xdb, 0xa8, 0x68, 0xde, 0xd9, 0x59, 0xad, 0x78, 0xd6, 0x94, 0xa3,
-        0xb6, 0x7f, 0xe1, 0xb4, 0x73, 0x42, 0x1b, 0x39, 0x7b, 0x46, 0x1b, 0x3d,
-        0xfb, 0x86, 0x36, 0xde, 0xd8, 0xb2, 0x49, 0xda, 0xb3, 0xd0, 0x1e, 0x71,
-        0x90, 0xbf, 0x4f, 0x87, 0xba, 0xec, 0xa2, 0xde, 0x4a, 0xe4, 0x7d, 0x9f,
-        0xf3, 0x86, 0xe6, 0x55, 0x6d, 0x8b, 0xfb, 0xe6, 0xa6, 0x22, 0x1a, 0xed,
-        0x72, 0x74, 0xde, 0x94, 0x63, 0xd5, 0x94, 0x3c, 0x57, 0x2d, 0x29, 0x5a,
-        0x86, 0x5d, 0xd2, 0xbc, 0x06, 0xc7, 0x2b, 0xa0, 0x75, 0x42, 0xdb, 0x07,
-        0x9a, 0xde, 0x59, 0x29, 0x5d, 0x71, 0xe6, 0x40, 0xaf, 0x03, 0x78, 0xff,
-        0x58, 0x1b, 0x6d, 0xf4, 0x6a, 0xde, 0xc9, 0x9b, 0xe2, 0x39, 0x59, 0xeb,
-        0x4b, 0x62, 0xba, 0xb0, 0x01, 0xc8, 0x0c, 0xfd, 0x38, 0xd0, 0x49, 0xca,
-        0xf7, 0xf5, 0x82, 0xff, 0x2c, 0x74, 0x6f, 0x5d, 0xa1, 0xfc, 0x8d, 0x5e,
-        0x29, 0xcf, 0x53, 0xd7, 0xa6, 0x36, 0x52, 0xf5, 0x2f, 0x78, 0x8e, 0xf4,
-        0x19, 0xe2, 0xfb, 0x47, 0x9d, 0x81, 0xf4, 0x21, 0x39, 0x03, 0xdc, 0x75,
-        0xad, 0xd8, 0xa0, 0xae, 0xc1, 0xdf, 0x2d, 0x39, 0x02, 0xbd, 0x15, 0x9d,
-        0x5e, 0x99, 0xb4, 0xb2, 0x2e, 0xf6, 0x68, 0x53, 0x20, 0x57, 0x32, 0xb4,
-        0x17, 0xd2, 0xe7, 0xde, 0x67, 0xd3, 0x9e, 0xa1, 0xcb, 0x53, 0x2f, 0x3d,
-        0xdf, 0xb3, 0x38, 0xb4, 0x91, 0x32, 0x43, 0xff, 0xf2, 0x45, 0xcf, 0xf6,
-        0xb6, 0xb4, 0x48, 0x29, 0x6d, 0x48, 0x16, 0xfb, 0xb4, 0x43, 0x4e, 0x3b,
-        0x22, 0x87, 0x2a, 0xd0, 0x8d, 0x6d, 0x5a, 0x8b, 0x62, 0x67, 0xca, 0x32,
-        0x50, 0x32, 0x75, 0x74, 0x26, 0x49, 0x97, 0x3a, 0xd2, 0xe5, 0x7a, 0x9e,
-        0x7a, 0xa2, 0x3d, 0x7f, 0x28, 0x5d, 0x69, 0xab, 0xba, 0x5a, 0xd5, 0xd3,
-        0xf8, 0x2f, 0x5d, 0x4f, 0xd4, 0xc9, 0x72, 0x28, 0xb7, 0x03, 0xdc, 0x8f,
-        0x40, 0x5f, 0xe2, 0xea, 0xc3, 0x0f, 0xb1, 0x6f, 0x93, 0x51, 0xb0, 0xd3,
-        0x17, 0x61, 0x14, 0x7a, 0x61, 0x37, 0x64, 0x19, 0xa6, 0xee, 0xe0, 0xc3,
-        0x1f, 0x49, 0x5e, 0xf9, 0xd5, 0x90, 0x97, 0xfc, 0xdb, 0x32, 0x55, 0x49,
-        0x80, 0x06, 0x65, 0xd4, 0xe5, 0xbd, 0x7c, 0x64, 0x1b, 0x7b, 0x20, 0x5f,
-        0x5e, 0xa6, 0xbe, 0x45, 0x7f, 0xa2, 0xfd, 0xf3, 0x9d, 0xb2, 0xfe, 0xcc,
-        0xbf, 0xee, 0x7c, 0x92, 0xf6, 0x96, 0x7c, 0x27, 0xe4, 0x78, 0x35, 0xc9,
-        0x3d, 0xd4, 0x56, 0x54, 0x6c, 0x8a, 0x64, 0x14, 0xdd, 0x28, 0x74, 0x48,
-        0x51, 0xed, 0xf7, 0x5e, 0xd0, 0x43, 0x2c, 0xa8, 0xf2, 0xbd, 0xa0, 0x64,
-        0x9b, 0xb6, 0xed, 0xcc, 0x11, 0xc9, 0xc2, 0xbe, 0x45, 0x8e, 0xcc, 0x99,
-        0x32, 0x6d, 0xff, 0x63, 0xa7, 0xb4, 0x2f, 0xdf, 0x6f, 0xa8, 0xb8, 0xae,
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+        0xa5, 0x0c, 0xdc, 0x7c, 0x60, 0x02, 0xef, 0xc8, 0xdb, 0x61, 0x8b, 0xaa,
+        0x5a, 0x7e, 0xd9, 0xce, 0xef, 0x5b, 0x6c, 0x24, 0xcd, 0x77, 0xc5, 0xef,
+        0x3b, 0x6f, 0xd3, 0xee, 0x74, 0x00, 0x5f, 0xe2, 0x9a, 0x57, 0xde, 0xb2,
+        0x0b, 0x40, 0x05, 0x2b, 0x3e, 0x05, 0x19, 0x6d, 0x17, 0xcb, 0xc9, 0xc9,
+        0xc3, 0xef, 0xce, 0xea, 0xbe, 0x6c, 0xdb, 0xea, 0xdb, 0xfa, 0x2e, 0xc7,
+        0xcf, 0xb9, 0x70, 0x0e, 0xf0, 0x6d, 0x4c, 0x53, 0xcb, 0xe8, 0x4e, 0xc3,
+        0x18, 0xf0, 0x65, 0xb4, 0x35, 0x8f, 0xe8, 0xff, 0x99, 0x07, 0xe5, 0x64,
+        0xc4, 0xf0, 0xcf, 0xdb, 0x71, 0x6d, 0x70, 0x3d, 0x3f, 0x06, 0xbf, 0xdf,
+        0x2b, 0x3f, 0xad, 0x38, 0xa3, 0x2f, 0x3f, 0x4f, 0xec, 0xca, 0x0f, 0x7d,
+        0xd4, 0x2e, 0xc9, 0xad, 0xd8, 0x32, 0x59, 0xd6, 0xfb, 0x0d, 0xae, 0xc9,
+        0xf8, 0xd1, 0x09, 0xc8, 0x0d, 0x65, 0x9d, 0xba, 0x65, 0x4a, 0x15, 0x72,
+        0x54, 0x05, 0x3e, 0x55, 0x21, 0x53, 0xe4, 0x40, 0x55, 0xe0, 0x5b, 0xb5,
+        0x69, 0x39, 0x75, 0xcc, 0x99, 0x36, 0x7b, 0x1d, 0x72, 0x74, 0xb5, 0xc9,
+        0xfd, 0xd7, 0x63, 0x36, 0x69, 0x07, 0x6f, 0xee, 0xee, 0xfd, 0xa7, 0xd8,
+        0xfb, 0x23, 0x72, 0x0d, 0x7e, 0xcb, 0xf5, 0xca, 0x08, 0x30, 0x49, 0x80,
+        0x51, 0x2e, 0x64, 0x23, 0x25, 0x1b, 0x95, 0x71, 0xd9, 0x84, 0x7d, 0xda,
+        0x5a, 0x4d, 0x80, 0x4f, 0x03, 0x47, 0xaf, 0x1c, 0x93, 0x37, 0x56, 0x95,
+        0xcc, 0xd8, 0xb0, 0x33, 0x6b, 0x8c, 0xc1, 0x43, 0x9e, 0xab, 0x5d, 0xfa,
+        0xbc, 0x7d, 0xa2, 0xee, 0xc7, 0xe2, 0x73, 0xf5, 0x1e, 0x99, 0xac, 0x9b,
+        0xf2, 0x54, 0xbd, 0x57, 0xbe, 0x5a, 0x8f, 0xca, 0xe9, 0x46, 0x4c, 0xbe,
+        0x56, 0x1f, 0x94, 0xa7, 0xeb, 0x47, 0xe4, 0x99, 0x46, 0x5c, 0xbe, 0x0e,
+        0xbf, 0x30, 0xdf, 0x70, 0x64, 0xaa, 0x31, 0x22, 0xa7, 0x1a, 0x8c, 0xb1,
+        0xe3, 0x7b, 0xf8, 0x65, 0x77, 0x63, 0x17, 0x1c, 0x57, 0x27, 0xc6, 0xe5,
+        0xa8, 0x9c, 0x3e, 0x6f, 0x94, 0xbc, 0x1f, 0xff, 0x10, 0x79, 0x01, 0x7d,
+        0x17, 0xae, 0x28, 0xa9, 0xe9, 0xef, 0xb7, 0xfe, 0x47, 0x24, 0xa2, 0x7d,
+        0xa3, 0x17, 0xaa, 0x83, 0x68, 0x63, 0xd3, 0x27, 0x09, 0xe2, 0x20, 0xad,
+        0xf8, 0x7f, 0xcb, 0xf7, 0x32, 0x74, 0x0c, 0xfb, 0x26, 0x7d, 0x2f, 0xbd,
+        0xf6, 0xc4, 0x0f, 0xfa, 0x39, 0xf4, 0xb5, 0xf6, 0x9e, 0x51, 0xb4, 0xbe,
+        0xbb, 0x90, 0x7f, 0xf4, 0x7f, 0x51, 0xfc, 0xb3, 0xa6, 0x73, 0x8d, 0x41,
+        0xfe, 0x4f, 0x0a, 0xc6, 0xf2, 0xf9, 0xf9, 0xdd, 0x93, 0x95, 0x09, 0xf5,
+        0x54, 0x85, 0x8c, 0xc6, 0x93, 0x85, 0xdd, 0x3c, 0xba, 0xaf, 0xc8, 0x9a,
+        0x1b, 0xd1, 0x63, 0xf0, 0xe3, 0xf6, 0x69, 0x9d, 0x53, 0x37, 0x31, 0x4c,
+        0xf9, 0xe3, 0x19, 0x5a, 0x4f, 0x70, 0xb6, 0x00, 0x6e, 0xeb, 0x9a, 0x72,
+        0xb1, 0xee, 0xc7, 0xaf, 0xe6, 0xb4, 0xbc, 0x5c, 0x87, 0xcc, 0xf1, 0xfc,
+        0xc1, 0xbf, 0x16, 0xaa, 0x7e, 0xdf, 0xec, 0xb0, 0x43, 0x7f, 0x1c, 0xf3,
+        0x35, 0x7a, 0xf9, 0x2d, 0xfe, 0x4f, 0x0e, 0xca, 0xc1, 0x78, 0x99, 0x0f,
+        0x6c, 0x6b, 0x59, 0xf4, 0xcf, 0x67, 0x1d, 0x79, 0x11, 0x7b, 0x51, 0x33,
+        0x39, 0xfe, 0x4e, 0xa9, 0x39, 0xf4, 0x6d, 0x89, 0xdf, 0xc3, 0x52, 0xc5,
+        0x77, 0x6a, 0x4e, 0x2b, 0x36, 0xe6, 0xe3, 0x6c, 0xcd, 0x7c, 0xf8, 0xdd,
+        0xe9, 0xea, 0x41, 0xdc, 0xa3, 0xce, 0x01, 0x67, 0x3a, 0xc3, 0xfb, 0x05,
+        0x94, 0x19, 0x1b, 0x99, 0xc3, 0x35, 0x16, 0xd4, 0xfd, 0x7c, 0x40, 0x73,
+        0xf5, 0xf1, 0x87, 0xfd, 0x66, 0xaa, 0x56, 0x21, 0x13, 0xba, 0xab, 0x8c,
+        0x9f, 0xad, 0x0f, 0x10, 0x73, 0x0f, 0xda, 0xfc, 0x45, 0xe4, 0x6f, 0xa6,
+        0x8e, 0x29, 0x04, 0xcf, 0xf6, 0xc9, 0xb3, 0x26, 0x73, 0xcd, 0xd3, 0x6a,
+        0xa2, 0xf2, 0x72, 0x90, 0x57, 0x7b, 0x57, 0x1d, 0xac, 0x35, 0x07, 0xfc,
+        0xbc, 0x74, 0xbe, 0x7b, 0x6f, 0x2e, 0xfa, 0x5e, 0x39, 0x61, 0x4e, 0x7a,
+        0x07, 0x78, 0xab, 0x36, 0x62, 0xd0, 0x41, 0xe0, 0x9d, 0xdd, 0xa6, 0xf5,
+        0xb1, 0xd8, 0xf8, 0x97, 0xb7, 0xad, 0xf5, 0xb9, 0x15, 0x63, 0xb8, 0x35,
+        0x40, 0xdf, 0x96, 0xb8, 0x71, 0xd1, 0x8f, 0x1b, 0x69, 0x1f, 0x1a, 0x58,
+        0x81, 0x3a, 0xea, 0x2a, 0xf4, 0x64, 0xb7, 0x2d, 0xff, 0xfe, 0x03, 0x7d,
+        0xe7, 0x95, 0xf0, 0x2c, 0x67, 0x00, 0x00, 0x00 };
 
 static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x0 };
-static u32 bnx2_RXP_b06FwRodata[(0x28/4) + 1] = {
-        0x0800468c, 0x0800458c, 0x08004630, 0x08004648, 0x08004660, 0x08004680,
-        0x0800468c, 0x0800468c, 0x08004594, 0x00000000, 0x00000000 };
-static u32 bnx2_RXP_b06FwBss[(0x13a4/4) + 1] = { 0x0 };
-static u32 bnx2_RXP_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
+static u32 bnx2_RXP_b06FwRodata[(0x278/4) + 1] = {
+        0x08003fdc, 0x08003edc, 0x08003f80, 0x08003f98, 0x08003fb0, 0x08003fd0,
+        0x08003fdc, 0x08003fdc, 0x08003ee4, 0x00000000, 0x08004a04, 0x08004a3c,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004a74, 0x08004c38,
+        0x08004b80, 0x08004bb8, 0x08004c38, 0x08004b08, 0x08004c38, 0x08004c38,
+        0x08004bb8, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004bf8,
+        0x08004c38, 0x08004bf8, 0x08004b80, 0x08004c38, 0x08004c38, 0x08004bf8,
+        0x08004bf8, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
+        0x08004ae4, 0x00000000, 0x08006018, 0x08006030, 0x08006030, 0x08006030,
+        0x08006018, 0x08006030, 0x08006030, 0x08006030, 0x08006018, 0x08006030,
+        0x08006030, 0x08006030, 0x08006018, 0x08006030, 0x08006030, 0x08006030,
+        0x08006024, 0x00000000, 0x00000000 };
+
+static u32 bnx2_RXP_b06FwBss[(0x13dc/4) + 1] = { 0x0 };
+static u32 bnx2_RXP_b06FwSbss[(0x2c/4) + 1] = { 0x0 };
+
+static struct fw_info bnx2_rxp_fw_06 = {
+        .ver_major                      = 0x2,
+        .ver_minor                      = 0x8,
+        .ver_fix                        = 0x17,
+
+        .start_addr                     = 0x08003184,
+
+        .text_addr                      = 0x08000000,
+        .text_len                       = 0x6728,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_RXP_b06FwText,
+        .gz_text_len                    = sizeof(bnx2_RXP_b06FwText),
+
+        .data_addr                      = 0x080069c0,
+        .data_len                       = 0x0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_RXP_b06FwData,
+
+        .sbss_addr                      = 0x080069c0,
+        .sbss_len                       = 0x2c,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_RXP_b06FwSbss,
+
+        .bss_addr                       = 0x080069f0,
+        .bss_len                        = 0x13dc,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_RXP_b06FwBss,
+
+        .rodata_addr                    = 0x08006728,
+        .rodata_len                     = 0x278,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_RXP_b06FwRodata,
+};
 
 static u8 bnx2_rv2p_proc1[] = {
         0x1f, 0x8b, 0x08, 0x08, 0x5e, 0xd0, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
@@ -1316,20 +1665,6 @@ static u8 bnx2_rv2p_proc2[] = {
         0x63, 0xd6, 0x11, 0x8f, 0x47, 0xd5, 0x5f, 0x3f, 0x97, 0x8f, 0x31, 0xd8,
         0x17, 0x00, 0x00, 0x00 };
 
-static const int bnx2_TPAT_b06FwReleaseMajor = 0x1;
-static const int bnx2_TPAT_b06FwReleaseMinor = 0x0;
-static const int bnx2_TPAT_b06FwReleaseFix = 0x0;
-static const u32 bnx2_TPAT_b06FwStartAddr = 0x08000860;
-static const u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
-static const int bnx2_TPAT_b06FwTextLen = 0x122c;
-static const u32 bnx2_TPAT_b06FwDataAddr = 0x08001a60;
-static const int bnx2_TPAT_b06FwDataLen = 0x0;
-static const u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
-static const int bnx2_TPAT_b06FwRodataLen = 0x0;
-static const u32 bnx2_TPAT_b06FwBssAddr = 0x08001aa0;
-static const int bnx2_TPAT_b06FwBssLen = 0x250;
-static const u32 bnx2_TPAT_b06FwSbssAddr = 0x08001a60;
-static const int bnx2_TPAT_b06FwSbssLen = 0x34;
 static u8 bnx2_TPAT_b06FwText[] = {
         0x1f, 0x8b, 0x08, 0x08, 0x47, 0xd2, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
         0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x57, 0x4d, 0x68,
@@ -1529,20 +1864,40 @@ static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };
 static u32 bnx2_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 };
 static u32 bnx2_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 };
 
-static const int bnx2_TXP_b06FwReleaseMajor = 0x1;
-static const int bnx2_TXP_b06FwReleaseMinor = 0x0;
-static const int bnx2_TXP_b06FwReleaseFix = 0x0;
-static const u32 bnx2_TXP_b06FwStartAddr = 0x080034b0;
-static const u32 bnx2_TXP_b06FwTextAddr = 0x08000000;
-static const int bnx2_TXP_b06FwTextLen = 0x5748;
-static const u32 bnx2_TXP_b06FwDataAddr = 0x08005760;
-static const int bnx2_TXP_b06FwDataLen = 0x0;
-static const u32 bnx2_TXP_b06FwRodataAddr = 0x00000000;
-static const int bnx2_TXP_b06FwRodataLen = 0x0;
-static const u32 bnx2_TXP_b06FwBssAddr = 0x080057a0;
-static const int bnx2_TXP_b06FwBssLen = 0x1c4;
-static const u32 bnx2_TXP_b06FwSbssAddr = 0x08005760;
-static const int bnx2_TXP_b06FwSbssLen = 0x38;
+static struct fw_info bnx2_tpat_fw_06 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x08000860,
+
+        .text_addr                      = 0x08000800,
+        .text_len                       = 0x122c,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_TPAT_b06FwText,
+        .gz_text_len                    = sizeof(bnx2_TPAT_b06FwText),
+
+        .data_addr                      = 0x08001a60,
+        .data_len                       = 0x0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_TPAT_b06FwData,
+
+        .sbss_addr                      = 0x08001a60,
+        .sbss_len                       = 0x34,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_TPAT_b06FwSbss,
+
+        .bss_addr                       = 0x08001aa0,
+        .bss_len                        = 0x250,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_TPAT_b06FwBss,
+
+        .rodata_addr                    = 0x00000000,
+        .rodata_len                     = 0x0,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_TPAT_b06FwRodata,
+};
+
 static u8 bnx2_TXP_b06FwText[] = {
         0x1f, 0x8b, 0x08, 0x08, 0x21, 0xd3, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
         0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x6d, 0x6c,
@@ -1964,3 +2319,38 @@ static u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x0 };
 static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 };
 static u32 bnx2_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 };
 static u32 bnx2_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 };
+
+static struct fw_info bnx2_txp_fw_06 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x080034b0,
+
+        .text_addr                      = 0x08000000,
+        .text_len                       = 0x5748,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_TXP_b06FwText,
+        .gz_text_len                    = sizeof(bnx2_TXP_b06FwText),
+
+        .data_addr                      = 0x08005760,
+        .data_len                       = 0x0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_TXP_b06FwData,
+
+        .sbss_addr                      = 0x08005760,
+        .sbss_len                       = 0x38,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_TXP_b06FwSbss,
+
+        .bss_addr                       = 0x080057a0,
+        .bss_len                        = 0x1c4,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_TXP_b06FwBss,
+
+        .rodata_addr                    = 0x00000000,
+        .rodata_len                     = 0x0,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_TXP_b06FwRodata,
+};
+
diff --git a/drivers/net/bnx2_fw2.h b/drivers/net/bnx2_fw2.h
new file mode 100644
index 000000000000..680c769a3fc0
--- /dev/null
+++ b/drivers/net/bnx2_fw2.h
@@ -0,0 +1,4086 @@
+/* bnx2_fw2.h: Broadcom NX2 network driver.
+ *
+ * Copyright (c) 2006 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, except as noted below.
+ *
+ * This file contains firmware data derived from proprietary unpublished
+ * source code, Copyright (c) 2006 Broadcom Corporation.
+ *
+ * Permission is hereby granted for the distribution of this firmware data
+ * in hexadecimal or equivalent format, provided this copyright notice is
+ * accompanying it.
+ */
+
+static u8 bnx2_COM_b09FwText[] = {
+        0x1f, 0x8b, 0x08, 0x08, 0xac, 0xfb, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
+        0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xdc, 0x5b, 0x6b, 0x70,
+        0x1b, 0xd7, 0x75, 0x3e, 0xfb, 0x00, 0x09, 0x91, 0x10, 0xb5, 0xa4, 0x60,
+        0x1a, 0x96, 0x68, 0x07, 0x20, 0x57, 0x22, 0x6a, 0xb1, 0x29, 0x4c, 0x33,
+        0x16, 0x9b, 0xc2, 0x12, 0x02, 0x50, 0xae, 0x26, 0xc3, 0x3a, 0x94, 0xcd,
+        0xd8, 0x4a, 0xaa, 0xc9, 0x30, 0x00, 0xa5, 0xf4, 0x61, 0xb7, 0x92, 0xab,
+        0xa9, 0x5d, 0xd7, 0xaa, 0x21, 0x92, 0x6a, 0xf5, 0x83, 0xe5, 0x2a, 0x16,
+        0x43, 0xa9, 0xd3, 0x74, 0xc2, 0x12, 0x56, 0xac, 0x4e, 0x31, 0x85, 0xfc,
+        0xd6, 0x38, 0xb1, 0xc9, 0x4a, 0x76, 0xeb, 0xf4, 0xe1, 0xa6, 0x33, 0xcd,
+        0xa3, 0x9d, 0x36, 0xf6, 0xa8, 0x3f, 0xea, 0xe9, 0xd3, 0x33, 0x6e, 0xa7,
+        0xea, 0xd8, 0x0e, 0xfa, 0x7d, 0x77, 0x77, 0x81, 0x25, 0x48, 0xbd, 0xfc,
+        0xc8, 0x8f, 0x70, 0x06, 0xb3, 0x7b, 0xef, 0xde, 0xbd, 0xf7, 0xdc, 0xf3,
+        0xf8, 0xce, 0x63, 0x2f, 0xfb, 0x44, 0x5a, 0xc4, 0xfb, 0x5b, 0x8b, 0x5f,
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+        0xc0, 0xe9, 0xe3, 0xa2, 0xc7, 0xad, 0x62, 0x10, 0xdb, 0xc9, 0x59, 0xc2,
+        0x3b, 0xb7, 0xd0, 0x77, 0xf3, 0x6e, 0xc0, 0x9e, 0xf7, 0xc8, 0x1d, 0xa3,
+        0xf8, 0x94, 0x7a, 0xff, 0xcf, 0x9d, 0xda, 0xb7, 0x5d, 0x1e, 0xfb, 0xf6,
+        0xbd, 0x41, 0x19, 0x03, 0xbb, 0x4b, 0x8d, 0xf1, 0xca, 0x53, 0xfd, 0xfb,
+        0xa7, 0xe1, 0x4f, 0xaa, 0xd4, 0x51, 0x5c, 0x13, 0x7c, 0xa5, 0xde, 0xa7,
+        0x1d, 0x62, 0x7e, 0x2a, 0xe9, 0xf8, 0xb8, 0x07, 0x1d, 0xf7, 0xce, 0x40,
+        0x2f, 0xb9, 0x7d, 0x3a, 0x3e, 0xd6, 0x90, 0x8e, 0xff, 0x75, 0x50, 0xfa,
+        0x54, 0xeb, 0xe9, 0x18, 0xb5, 0x3c, 0xc7, 0x8b, 0x8d, 0xfc, 0x57, 0xd8,
+        0x07, 0xd4, 0xa4, 0xc3, 0xe7, 0x01, 0x58, 0x69, 0xbf, 0x07, 0xe2, 0x7e,
+        0xc0, 0x47, 0xc4, 0x4e, 0xfe, 0x90, 0xe2, 0x8b, 0xb5, 0xb1, 0xd0, 0xcd,
+        0xae, 0xf9, 0x96, 0xc7, 0x35, 0xd0, 0xc5, 0x41, 0x0b, 0x76, 0x48, 0xda,
+        0xf4, 0x1a, 0x5e, 0xef, 0xf9, 0x0e, 0xe5, 0xec, 0x54, 0x9e, 0xe0, 0xa3,
+        0x0e, 0xd2, 0x53, 0x88, 0x2b, 0x2b, 0x1f, 0xf0, 0xd1, 0x8c, 0x5c, 0xb7,
+        0x79, 0x40, 0xe0, 0x03, 0xf4, 0xd5, 0x50, 0xc2, 0x9f, 0xe0, 0x3d, 0x95,
+        0xfe, 0xdf, 0xe4, 0x6a, 0x48, 0xed, 0x13, 0x8f, 0xc5, 0xfd, 0x3c, 0xeb,
+        0xfc, 0xb0, 0x3f, 0xf6, 0xd7, 0xd7, 0xcb, 0x79, 0xc5, 0x90, 0x05, 0x25,
+        0xfa, 0x0f, 0x96, 0x73, 0xfe, 0x03, 0xa6, 0xe8, 0xb9, 0x70, 0xb9, 0x78,
+        0x80, 0xf5, 0x47, 0xec, 0x21, 0x7c, 0x87, 0xda, 0xb7, 0xfb, 0xf6, 0x30,
+        0x75, 0xed, 0x67, 0xa9, 0x6f, 0x90, 0xc3, 0x7a, 0xa3, 0x71, 0x00, 0xf9,
+        0xe1, 0x16, 0x5f, 0x83, 0x5e, 0x51, 0x63, 0x56, 0x9c, 0x3a, 0xe0, 0x4f,
+        0x40, 0x0f, 0x68, 0x2b, 0x5d, 0x45, 0x53, 0xb3, 0x82, 0xa6, 0xe2, 0x6b,
+        0xb3, 0x8a, 0xa6, 0x66, 0x95, 0xff, 0x7c, 0x56, 0xd1, 0xd4, 0xac, 0xa2,
+        0xa9, 0x59, 0x45, 0x53, 0xb3, 0x8c, 0xd7, 0xa3, 0xac, 0xaf, 0x42, 0xf7,
+        0xd0, 0xfe, 0xcb, 0x2e, 0x4a, 0xe6, 0x70, 0x1e, 0xf2, 0xb8, 0x96, 0xae,
+        0x7e, 0x6d, 0x58, 0xfb, 0x47, 0x0b, 0x32, 0xcf, 0x8e, 0x9f, 0x85, 0x3d,
+        0x78, 0x98, 0xe1, 0x77, 0xcd, 0x37, 0xbf, 0x88, 0xb9, 0xfa, 0x28, 0x26,
+        0x7a, 0xc0, 0x36, 0x51, 0xd4, 0xad, 0xe3, 0x9a, 0xa8, 0xeb, 0x92, 0xb6,
+        0x5c, 0xaa, 0x61, 0x8d, 0x97, 0xc6, 0x8b, 0x69, 0xb5, 0x5f, 0xb5, 0x76,
+        0x4e, 0x0b, 0x25, 0xb2, 0x80, 0x2b, 0x72, 0x21, 0x2d, 0xde, 0x1b, 0x01,
+        0xa7, 0x94, 0xe9, 0x01, 0x83, 0xa3, 0x0a, 0x06, 0x4f, 0x8b, 0x35, 0x22,
+        0x97, 0x10, 0x3e, 0xc8, 0xc6, 0x70, 0x48, 0x67, 0x46, 0xf9, 0x3e, 0x8c,
+        0xfb, 0x07, 0x42, 0xcc, 0x83, 0xb6, 0x0b, 0x07, 0xf7, 0xda, 0x1b, 0xf1,
+        0x9a, 0xed, 0xd6, 0xd3, 0x5c, 0x77, 0xc9, 0x8e, 0x90, 0x92, 0x1b, 0x52,
+        0xef, 0xdd, 0xe5, 0xd8, 0x89, 0x14, 0xcf, 0xed, 0x2f, 0xc2, 0x7f, 0x39,
+        0x44, 0x6d, 0x25, 0x3a, 0x12, 0x06, 0x3e, 0x77, 0xb1, 0x5d, 0xc9, 0x73,
+        0x18, 0x2b, 0xd1, 0x85, 0xf0, 0x3e, 0xb6, 0x5d, 0xf6, 0xb3, 0x0e, 0x3a,
+        0xca, 0xff, 0x4e, 0xc4, 0xef, 0xc3, 0xbc, 0x3a, 0xf8, 0xda, 0x7e, 0x32,
+        0x7a, 0x52, 0x66, 0x2b, 0xeb, 0x07, 0x47, 0x2a, 0xf6, 0x88, 0x05, 0xff,
+        0x1c, 0xeb, 0xb6, 0xc6, 0x5c, 0xb8, 0x5b, 0xd5, 0x9c, 0xc1, 0x87, 0x8d,
+        0xf8, 0xd6, 0x3f, 0x97, 0x64, 0xaf, 0x80, 0x21, 0x75, 0xfc, 0xe3, 0x52,
+        0x64, 0x08, 0xc7, 0x78, 0xe7, 0x90, 0x3d, 0x11, 0xf1, 0xfd, 0x58, 0xea,
+        0xf2, 0x3e, 0xfb, 0x88, 0x7c, 0x3f, 0x80, 0x6d, 0x5a, 0x3e, 0x2f, 0xbc,
+        0x97, 0x3a, 0x4f, 0x25, 0x5f, 0x15, 0x74, 0x50, 0xa2, 0x7f, 0x67, 0x9a,
+        0x35, 0x09, 0xb1, 0x8c, 0x29, 0x51, 0x0b, 0x8d, 0x7c, 0xe5, 0xf9, 0x45,
+        0x3d, 0x2f, 0x47, 0xed, 0xf5, 0xfd, 0xc8, 0x37, 0xcb, 0x16, 0x68, 0x73,
+        0x99, 0x01, 0x3f, 0xda, 0xe8, 0xf2, 0x46, 0x4f, 0x50, 0xd4, 0x66, 0x77,
+        0xb3, 0x8e, 0xa3, 0xf3, 0x92, 0xc7, 0xf8, 0xfe, 0x01, 0xf1, 0xbe, 0xb9,
+        0xd8, 0x12, 0xc6, 0x35, 0xd3, 0xc8, 0x72, 0xe9, 0x21, 0xfe, 0x5d, 0xc4,
+        0x11, 0x93, 0xd4, 0xaa, 0x62, 0x04, 0x1d, 0x2a, 0xae, 0x14, 0x62, 0x5a,
+        0xaa, 0xd4, 0x1c, 0x8f, 0x94, 0x7d, 0x6d, 0xc0, 0xf1, 0x5a, 0x5f, 0xdb,
+        0x73, 0x5b, 0xc8, 0x9b, 0xad, 0xf0, 0x1a, 0x39, 0xa5, 0x2d, 0xa4, 0x7c,
+        0x88, 0xd6, 0x02, 0x6d, 0xb7, 0xb6, 0x6e, 0xc7, 0xd7, 0xb4, 0x36, 0xcf,
+        0xac, 0x9f, 0x79, 0xc7, 0x69, 0x53, 0xf8, 0xd4, 0x4c, 0xf3, 0xb9, 0x36,
+        0x96, 0xd9, 0xa8, 0x97, 0x02, 0xbc, 0xfc, 0x43, 0xa8, 0x37, 0x79, 0x32,
+        0xd0, 0x4c, 0xab, 0xab, 0xc8, 0x79, 0x78, 0xfc, 0x2e, 0x99, 0xe7, 0xfb,
+        0x08, 0xc3, 0x65, 0x3f, 0xcb, 0x37, 0x43, 0xc5, 0x70, 0x70, 0x0e, 0xbc,
+        0x41, 0xf4, 0xfd, 0x0c, 0x3c, 0x3c, 0xde, 0xc6, 0x7a, 0xbd, 0x8c, 0x01,
+        0x1c, 0xe4, 0x7b, 0x7f, 0x33, 0xf7, 0x08, 0xfc, 0x59, 0xe6, 0x61, 0xbe,
+        0x7f, 0x8c, 0xf5, 0x81, 0x08, 0x35, 0xd3, 0xca, 0x6a, 0x33, 0xeb, 0xf5,
+        0xcd, 0xac, 0x0f, 0x8c, 0x9a, 0x23, 0x3e, 0xf1, 0x2c, 0x51, 0xdb, 0xf2,
+        0xe9, 0xc0, 0x7e, 0xc6, 0x41, 0x3c, 0xeb, 0x8b, 0xea, 0x59, 0xb5, 0xcf,
+        0xb8, 0x55, 0xc2, 0xf1, 0x61, 0xff, 0xfa, 0x99, 0xab, 0x78, 0x2f, 0xd4,
+        0xe2, 0x34, 0xeb, 0xbe, 0x41, 0xf1, 0x6e, 0x46, 0x63, 0x66, 0x86, 0xed,
+        0x80, 0x30, 0x1f, 0x1f, 0xa1, 0x54, 0x31, 0x41, 0xbf, 0x57, 0x74, 0xfb,
+        0x6a, 0x8f, 0xf0, 0x9c, 0x65, 0x6d, 0x7d, 0x0b, 0xcf, 0xeb, 0x7d, 0xa7,
+        0x96, 0x67, 0xb4, 0x91, 0xff, 0x6b, 0x41, 0x6a, 0x7e, 0x11, 0xbe, 0x91,
+        0x12, 0x65, 0xc3, 0xf6, 0x85, 0xeb, 0xe2, 0xbd, 0x1b, 0x16, 0xbd, 0x22,
+        0xf2, 0x5b, 0xf9, 0x7a, 0xbe, 0xe7, 0x79, 0x8c, 0x7b, 0xc5, 0xa2, 0x2b,
+        0x8e, 0x84, 0xf7, 0x9f, 0x05, 0x82, 0xe4, 0x7f, 0x1d, 0x39, 0x48, 0xd0,
+        0xb5, 0xd6, 0xcf, 0x38, 0xfb, 0x98, 0x5f, 0xbf, 0x88, 0xeb, 0xf8, 0xf3,
+        0x75, 0x1c, 0xb7, 0xf1, 0x3a, 0x21, 0x6f, 0x91, 0x77, 0x02, 0x3e, 0xb7,
+        0x3f, 0x64, 0x0a, 0xfc, 0x3b, 0xc2, 0x38, 0xd5, 0x24, 0x7c, 0x81, 0xbd,
+        0x18, 0xeb, 0x0c, 0xb2, 0x6e, 0xb0, 0x7e, 0x66, 0x7c, 0x1f, 0x8e, 0x23,
+        0x3d, 0x7e, 0x86, 0x91, 0xc4, 0xa1, 0xb0, 0x78, 0xff, 0xa1, 0xeb, 0x2f,
+        0x70, 0x70, 0x9c, 0x78, 0x3f, 0xa1, 0x3f, 0xf0, 0x7e, 0x9a, 0xe8, 0xb3,
+        0xd4, 0x46, 0x71, 0x7e, 0x46, 0x2c, 0x27, 0xd7, 0x7d, 0xbe, 0xe8, 0x27,
+        0xe9, 0x47, 0x6a, 0x1e, 0xd6, 0xef, 0x29, 0xa4, 0x7e, 0xdc, 0x5b, 0xd3,
+        0x0a, 0xbe, 0x77, 0xd1, 0x8d, 0x5c, 0x07, 0xdd, 0x54, 0xb1, 0xa5, 0x1b,
+        0xc2, 0xae, 0x62, 0x9e, 0x9c, 0xe8, 0xa2, 0xeb, 0xab, 0x4d, 0x44, 0xbd,
+        0x6d, 0x22, 0xf6, 0x7b, 0x23, 0x97, 0xc7, 0xf3, 0x87, 0xa5, 0xdf, 0xa5,
+        0x82, 0x23, 0x37, 0x3c, 0x70, 0xe4, 0x3d, 0x81, 0x23, 0xef, 0x6d, 0x81,
+        0x23, 0x7b, 0x95, 0x2d, 0xd1, 0x46, 0xcd, 0x0a, 0x3f, 0x5e, 0x63, 0xfc,
+        0x78, 0x81, 0xf1, 0xe3, 0x50, 0x03, 0xfc, 0x30, 0x6a, 0xf0, 0xe3, 0xb0,
+        0xc0, 0x8f, 0x9f, 0x6d, 0x8a, 0x1f, 0x87, 0xfc, 0x9b, 0xf9, 0x82, 0x34,
+        0x6e, 0x0e, 0xd0, 0x4a, 0xce, 0xa1, 0xd5, 0x45, 0x9b, 0x2d, 0x7b, 0xd8,
+        0xe6, 0x88, 0x19, 0xce, 0x88, 0x7a, 0x97, 0x82, 0xc0, 0x2b, 0x96, 0xe3,
+        0x33, 0xa8, 0x69, 0xaa, 0xdb, 0x03, 0x12, 0xef, 0xa5, 0x14, 0xf0, 0x97,
+        0x7b, 0x12, 0xcb, 0xac, 0x9f, 0xf9, 0x73, 0xde, 0xc7, 0x2b, 0x6b, 0x81,
+        0x00, 0x7e, 0xf3, 0xcf, 0x04, 0x69, 0x63, 0x8d, 0xed, 0x54, 0xc6, 0xb1,
+        0xab, 0xb9, 0x21, 0xba, 0x92, 0x1b, 0xa0, 0x8d, 0xdc, 0x30, 0xbd, 0x93,
+        0xc3, 0x33, 0x00, 0x73, 0x3e, 0x16, 0x30, 0x37, 0xe8, 0x60, 0x90, 0xc7,
+        0xac, 0x0e, 0xd0, 0xfa, 0xaa, 0xc6, 0x57, 0xe0, 0x2a, 0xf6, 0x3f, 0xd2,
+        0x23, 0xeb, 0xd0, 0xea, 0x71, 0x20, 0x56, 0x85, 0x03, 0xf2, 0x1a, 0xec,
+        0xfd, 0x42, 0x7d, 0x0d, 0x6d, 0xab, 0x39, 0x83, 0x1c, 0xb8, 0x36, 0xb6,
+        0xc9, 0x6d, 0xe1, 0x73, 0x3d, 0xe8, 0x87, 0x4e, 0x6b, 0xdc, 0x4d, 0x5d,
+        0xbc, 0x07, 0x0e, 0xf2, 0x87, 0x86, 0x59, 0x3f, 0xed, 0x16, 0xfa, 0x68,
+        0xd4, 0x09, 0x84, 0x62, 0x54, 0x3a, 0x6b, 0x38, 0xe8, 0x93, 0xf8, 0x08,
+        0xdf, 0xcf, 0x50, 0x7e, 0x9e, 0x4e, 0x17, 0x3e, 0xd5, 0xea, 0x9e, 0x88,
+        0xd1, 0x9e, 0xe0, 0x39, 0x43, 0x4e, 0x56, 0xe2, 0x22, 0x54, 0x8e, 0x8b,
+        0xb4, 0xf2, 0xba, 0x25, 0x2d, 0xcd, 0x39, 0x3c, 0xae, 0xc8, 0xe3, 0x8a,
+        0x88, 0xa9, 0xf1, 0xf9, 0x55, 0xc4, 0x73, 0x87, 0x68, 0x63, 0x11, 0x34,
+        0x07, 0xff, 0x44, 0x25, 0x86, 0xba, 0xb1, 0x86, 0xf3, 0xf0, 0x51, 0x54,
+        0x62, 0xa8, 0x1b, 0x2a, 0x86, 0xba, 0xb1, 0x36, 0x2d, 0xf8, 0xf0, 0x42,
+        0x8e, 0x79, 0x40, 0xce, 0xaf, 0xf2, 0x07, 0xf7, 0xa9, 0x77, 0xf6, 0x9c,
+        0x10, 0x3e, 0xe4, 0x1e, 0x67, 0x73, 0x18, 0x1e, 0xac, 0x83, 0xe1, 0xb4,
+        0xd0, 0x83, 0xe2, 0x7c, 0xcf, 0x58, 0xee, 0x04, 0xc3, 0x73, 0x96, 0x69,
+        0x69, 0xb7, 0xa2, 0x25, 0x1d, 0x93, 0xed, 0x26, 0xf5, 0xfe, 0x1f, 0xa1,
+        0xeb, 0x4b, 0xfe, 0x33, 0x54, 0xc3, 0x7f, 0x28, 0x10, 0x1d, 0x97, 0xd7,
+        0xa7, 0x8b, 0xaf, 0x0c, 0x6b, 0xff, 0x5b, 0x9a, 0xef, 0xbb, 0x90, 0xdb,
+        0x49, 0x4c, 0x97, 0xe5, 0xa6, 0x67, 0xce, 0xe0, 0x76, 0x9f, 0xad, 0x71,
+        0xe1, 0xc4, 0x6d, 0xe0, 0x93, 0xbc, 0x47, 0x05, 0x9f, 0xfe, 0x77, 0x16,
+        0xc0, 0xb2, 0x93, 0x05, 0x98, 0x57, 0x84, 0x80, 0xf5, 0x03, 0x03, 0xb4,
+        0x8e, 0x39, 0x00, 0x1e, 0x53, 0x68, 0x02, 0xe6, 0x19, 0xa7, 0xf5, 0x40,
+        0xfb, 0xfb, 0x95, 0xc1, 0xeb, 0x5d, 0x1b, 0xa0, 0x67, 0x4f, 0x2d, 0xea,
+        0x79, 0x2c, 0x07, 0xca, 0xa3, 0x4e, 0x2a, 0x0c, 0x24, 0xe6, 0x27, 0x90,
+        0xff, 0x80, 0xfe, 0x00, 0xf9, 0x11, 0x98, 0x9f, 0x9c, 0x81, 0x72, 0xa0,
+        0x35, 0x53, 0xcd, 0x6b, 0x40, 0xfa, 0x40, 0x61, 0x08, 0x2a, 0x53, 0x41,
+        0x63, 0x1d, 0x40, 0xf6, 0x12, 0x21, 0x68, 0xd8, 0x01, 0x69, 0x20, 0xbb,
+        0x79, 0x8a, 0x08, 0x98, 0x9f, 0x14, 0x20, 0xc4, 0xd0, 0x00, 0xcf, 0x4f,
+        0xec, 0x40, 0x97, 0xc2, 0xdc, 0xf4, 0xff, 0xff, 0x31, 0x15, 0x16, 0x60,
+        0xda, 0x03, 0xad, 0xf9, 0xfc, 0xfd, 0xff, 0x80, 0x08, 0x0b, 0x43, 0x0b,
+        0x7c, 0xed, 0x9e, 0xb0, 0x3c, 0xa8, 0x9c, 0x5b, 0x00, 0x64, 0xb5, 0xc1,
+        0xeb, 0x6d, 0x16, 0xf0, 0x7d, 0xc4, 0x0b, 0x18, 0x7e, 0x01, 0xcb, 0x95,
+        0xff, 0xff, 0x97, 0xc2, 0xd5, 0x82, 0x00, 0x00, 0xd4, 0xc2, 0xcb, 0x42,
+        0x60, 0x7c, 0x00, 0x00, 0x00 };
+static u32 bnx2_COM_b09FwData[(0x0/4) + 1] = { 0x0 };
+static u32 bnx2_COM_b09FwRodata[(0x88/4) + 1] = {
+        0x08001ad8, 0x08001b14, 0x08001b14, 0x08001b14, 0x08001b14, 0x08001b14,
+        0x08001a24, 0x08001b14, 0x08001a98, 0x08001b14, 0x080019ac, 0x08001b14,
+        0x08001b14, 0x08001b14, 0x080019b8, 0x0, 0x08002a2c, 0x08002a7c,
+        0x08002aac, 0x08002adc, 0x08002b0c, 0x0, 0x08005fac, 0x08005fac,
+        0x08005fac, 0x08005fac, 0x08005fac, 0x08005fd8, 0x08005fd8, 0x08006018,
+        0x08006024, 0x08006024, 0x08005fac, 0x0, 0x0 };
+static u32 bnx2_COM_b09FwBss[(0x88/4) + 1] = { 0x0 };
+static u32 bnx2_COM_b09FwSbss[(0x5c/4) + 1] = { 0x0 };
+
+static struct fw_info bnx2_com_fw_09 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x080000b0,
+
+        .text_addr                      = 0x08000000,
+        .text_len                       = 0x7c5c,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_COM_b09FwText,
+        .gz_text_len                    = sizeof(bnx2_COM_b09FwText),
+
+        .data_addr                      = 0x08007d00,
+        .data_len                       = 0x0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_COM_b09FwData,
+
+        .sbss_addr                      = 0x08007d00,
+        .sbss_len                       = 0x5c,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_COM_b09FwSbss,
+
+        .bss_addr                       = 0x08007d60,
+        .bss_len                        = 0x88,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_COM_b09FwBss,
+
+        .rodata_addr                    = 0x08007c60,
+        .rodata_len                     = 0x88,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_COM_b09FwRodata,
+};
+
+static u8 bnx2_CP_b09FwText[] = {
+        0x1f, 0x8b, 0x08, 0x08, 0x8e, 0xfc, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
+        0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xbd, 0x7d, 0x0d, 0x74,
+        0x5c, 0x57, 0x7d, 0xe7, 0xff, 0xdd, 0x79, 0x92, 0xc6, 0xb2, 0x2c, 0x3f,
+        0xcb, 0x63, 0x65, 0x22, 0x0b, 0x7b, 0x46, 0x7a, 0xb2, 0x95, 0x58, 0x64,
+        0xc7, 0xae, 0x00, 0x6d, 0x3b, 0x85, 0xe9, 0x48, 0xb2, 0x9d, 0x0f, 0x8a,
+        0x4c, 0x44, 0x4f, 0x5a, 0xe8, 0x22, 0xc6, 0x76, 0x48, 0x80, 0xb2, 0x4e,
+        0x09, 0x69, 0x80, 0x04, 0x0f, 0x23, 0xf9, 0x83, 0x74, 0xec, 0x51, 0x12,
+        0xc5, 0x76, 0x4f, 0x73, 0x58, 0x55, 0x92, 0x1d, 0x43, 0xa7, 0x1e, 0x27,
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+        0x02, 0xbd, 0x45, 0xb9, 0x9d, 0x97, 0x6c, 0x0f, 0xd3, 0x4c, 0x9d, 0x3e,
+        0xed, 0x23, 0x1f, 0x77, 0x7a, 0xe7, 0xfa, 0x27, 0x7e, 0xc3, 0x35, 0x70,
+        0xfe, 0xa6, 0x9d, 0x93, 0x71, 0xb2, 0x15, 0xe6, 0x87, 0x6b, 0xe1, 0x77,
+        0xdb, 0xfb, 0x08, 0x99, 0x5f, 0x7d, 0xff, 0xb5, 0xe1, 0xd3, 0xac, 0xfe,
+        0x3b, 0x22, 0x23, 0x4e, 0x1f, 0xea, 0x4c, 0x7b, 0x0d, 0x03, 0x2a, 0x7d,
+        0xd3, 0x00, 0xcf, 0xca, 0x4d, 0x2c, 0xf9, 0xfb, 0x01, 0xf3, 0xba, 0xb0,
+        0xa0, 0xe7, 0x94, 0xfb, 0xb0, 0xa6, 0x41, 0x8b, 0x9a, 0xb6, 0x34, 0xfd,
+        0x1f, 0x98, 0xd3, 0x91, 0xd4, 0xad, 0xd4, 0x93, 0xa1, 0x8e, 0x4c, 0xc6,
+        0xfb, 0x78, 0x7f, 0x84, 0xa6, 0x71, 0x7b, 0x97, 0xc4, 0xd4, 0x39, 0xad,
+        0xdf, 0x47, 0x52, 0xbc, 0x5f, 0x66, 0x99, 0xb2, 0xa3, 0x55, 0x65, 0xf5,
+        0xb8, 0x3d, 0xf9, 0x43, 0xcc, 0xcd, 0x17, 0x61, 0x6f, 0xf6, 0x8e, 0xbd,
+        0x0a, 0x9f, 0x31, 0x2e, 0x5f, 0x2a, 0xbd, 0x04, 0x7a, 0xcd, 0xaf, 0xb5,
+        0x77, 0xe1, 0x65, 0x01, 0x37, 0xcf, 0x38, 0xeb, 0xfd, 0xc3, 0x91, 0x3f,
+        0x02, 0x5d, 0xfc, 0xc1, 0x4b, 0xec, 0x03, 0xb0, 0x44, 0x60, 0xcf, 0xc3,
+        0x36, 0x18, 0x7f, 0x49, 0xef, 0x95, 0xbb, 0xbe, 0xfc, 0x92, 0x8e, 0x53,
+        0xf4, 0x97, 0x5b, 0x65, 0x7b, 0xb9, 0x41, 0x76, 0x40, 0x2f, 0xec, 0x28,
+        0xfb, 0x78, 0xa2, 0x72, 0x63, 0xd9, 0xcc, 0xd3, 0x47, 0xca, 0x9c, 0xef,
+        0x6d, 0x32, 0x71, 0xbc, 0x9a, 0x66, 0xa7, 0xed, 0xde, 0x31, 0xd2, 0x0f,
+        0x9e, 0x52, 0x32, 0x3f, 0xad, 0xc7, 0xce, 0x5d, 0xac, 0xc9, 0xc3, 0xb3,
+        0xc2, 0xbd, 0xf8, 0xfc, 0x1b, 0x74, 0xdf, 0x68, 0xe5, 0x19, 0x77, 0xde,
+        0x8f, 0xd8, 0x5f, 0x09, 0xf7, 0x86, 0xbf, 0xfe, 0x19, 0x10, 0xfd, 0x77,
+        0x5d, 0xf4, 0xde, 0x70, 0x4d, 0x7b, 0xd2, 0x76, 0x26, 0xa6, 0x75, 0x84,
+        0xa1, 0xf1, 0xf9, 0xbf, 0xe7, 0x22, 0xf2, 0x7f, 0x01, 0x95, 0xf6, 0x2d,
+        0x58, 0xd0, 0x73, 0x00, 0x00, 0x00 };
+static u32 bnx2_CP_b09FwData[(0x50/4) + 1] = {
+        0x00010030, 0x00000030, 0x00000000, 0x00000001, 0x00010fd0, 0x00000fd0,
+        0x00001430, 0x0000007f, 0x00030400, 0x00001000, 0x00000030, 0x00000020,
+        0x00050200, 0x00001000, 0x00000030, 0x00000010, 0x00010400, 0x00000400,
+        0x00001030, 0x00000020, 0x00000000 };
+static u32 bnx2_CP_b09FwRodata[(0x118/4) + 1] = {
+        0x080005d8, 0x080007f8, 0x0800073c, 0x08000764, 0x0800078c, 0x080007b4,
+        0x08000610, 0x080005fc, 0x08000820, 0x08000820, 0x0800062c, 0x08000648,
+        0x08000648, 0x08000820, 0x08000660, 0x08000674, 0x08000820, 0x08000688,
+        0x08000820, 0x08000820, 0x0800069c, 0x08000820, 0x08000820, 0x08000820,
+        0x08000820, 0x08000820, 0x08000820, 0x08000820, 0x08000820, 0x08000820,
+        0x08000820, 0x080006b0, 0x08000820, 0x080006c4, 0x080006d8, 0x080006ec,
+        0x08000820, 0x08000700, 0x08000714, 0x08000728, 0x08003740, 0x08003758,
+        0x08003768, 0x08003778, 0x08003790, 0x080037a8, 0x080037b8, 0x080037c8,
+        0x080037e8, 0x080037f8, 0x08003808, 0x08003898, 0x080037d8, 0x08003818,
+        0x08003828, 0x08003840, 0x08003860, 0x08003898, 0x08003878, 0x08003878,
+        0x080055f0, 0x080055f0, 0x080055f0, 0x080055f0, 0x080055f0, 0x08005618,
+        0x08005618, 0x08005640, 0x08005690, 0x08005660, 0x00000000 };
+static u32 bnx2_CP_b09FwBss[(0x870/4) + 1] = { 0x0 };
+static u32 bnx2_CP_b09FwSbss[(0xe9/4) + 1] = { 0x0 };
+
+static struct fw_info bnx2_cp_fw_09 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x0800006c,
+
+        .text_addr                      = 0x08000000,
+        .text_len                       = 0x73cc,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_CP_b09FwText,
+        .gz_text_len                    = sizeof(bnx2_CP_b09FwText),
+
+        .data_addr                      = 0x08007500,
+        .data_len                       = 0x50,
+        .data_index                     = 0x0,
+        .data                           = bnx2_CP_b09FwData,
+
+        .sbss_addr                      = 0x08007554,
+        .sbss_len                       = 0xe9,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_CP_b09FwSbss,
+
+        .bss_addr                       = 0x08007640,
+        .bss_len                        = 0x870,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_CP_b09FwBss,
+
+        .rodata_addr                    = 0x080073d0,
+        .rodata_len                     = 0x118,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_CP_b09FwRodata,
+};
+
+static u8 bnx2_RXP_b09FwText[] = {
+        0x1f, 0x8b, 0x08, 0x08, 0x19, 0xfd, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
+        0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5c, 0x6b, 0x6c,
+        0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x20, 0xb5, 0xa2, 0xf8, 0x18, 0x2e, 0x57,
+        0xcc, 0x4a, 0x66, 0xec, 0x5d, 0x71, 0x24, 0xb2, 0x16, 0x6b, 0x8c, 0xd8,
+        0xad, 0x4d, 0x04, 0x6b, 0x7b, 0x33, 0xbb, 0x92, 0x98, 0x54, 0x85, 0x29,
+        0x87, 0x75, 0x0c, 0xc3, 0x75, 0xd9, 0xa5, 0x1a, 0xbb, 0xae, 0x51, 0xc8,
+        0x8f, 0xc4, 0x06, 0x6a, 0xd6, 0x9b, 0x25, 0xdd, 0xa8, 0xe9, 0x82, 0x43,
+        0x4b, 0xaa, 0xe9, 0x02, 0x69, 0xbb, 0x20, 0xa9, 0xc7, 0x8f, 0x85, 0x56,
+        0x76, 0x52, 0xc7, 0xf9, 0xe1, 0x48, 0x50, 0x95, 0x20, 0x28, 0x0c, 0x43,
+        0x48, 0x8d, 0xd6, 0x3f, 0xda, 0x40, 0x95, 0x9f, 0x68, 0x92, 0x42, 0x41,
+        0x0b, 0xc7, 0x68, 0x6c, 0x4f, 0xbf, 0xef, 0xce, 0x0c, 0xb9, 0xa4, 0x5f,
+        0x40, 0x7f, 0xf4, 0x4f, 0xe7, 0x02, 0x8b, 0xb9, 0xf7, 0xce, 0x3d, 0xe7,
+        0x9e, 0x7b, 0xde, 0xe7, 0x0e, 0xa5, 0xdf, 0xef, 0x94, 0x0e, 0x09, 0x5b,
+        0x17, 0x7e, 0x99, 0xc3, 0x8f, 0x3d, 0x74, 0xc3, 0xd8, 0x0d, 0xa3, 0x22,
+        0x7b, 0xf6, 0x18, 0x5b, 0x12, 0x7a, 0x34, 0x1f, 0xb7, 0xb8, 0xc5, 0x2d,
+        0x6e, 0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e,
+        0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71,
+        0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b,
+        0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b,
+        0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b, 0xdc,
+        0xe2, 0xf6, 0xff, 0xbd, 0x19, 0x22, 0x16, 0x9f, 0x5d, 0xe1, 0x4f, 0x12,
+        0x7a, 0xfe, 0xf2, 0x1f, 0xba, 0xb6, 0x24, 0x8c, 0xfc, 0xcf, 0x66, 0xa6,
+        0x6d, 0x91, 0x42, 0x63, 0x77, 0xa6, 0x28, 0xef, 0xfb, 0x95, 0x94, 0x29,
+        0x9c, 0xff, 0x6c, 0xfe, 0xbd, 0xbf, 0x7d, 0xf1, 0xa6, 0xec, 0xd5, 0xba,
+        0x21, 0x09, 0x2b, 0x3f, 0xb7, 0xc7, 0xda, 0x25, 0x89, 0x01, 0xc0, 0x7c,
+        0x6b, 0xe8, 0xc7, 0xdd, 0xd2, 0x2d, 0x6b, 0x78, 0xec, 0x84, 0x5c, 0x36,
+        0x5e, 0xd0, 0xdc, 0xa6, 0xef, 0x9f, 0x70, 0x7c, 0xff, 0x87, 0xf8, 0xbd,
+        0xe5, 0x60, 0xec, 0x7d, 0xe0, 0x17, 0x4c, 0x43, 0x74, 0xfb, 0x2f, 0x34,
+        0x77, 0xb9, 0x43, 0xaa, 0x8b, 0xa6, 0xcc, 0x7a, 0x29, 0x39, 0xe2, 0x55,
+        0xb4, 0x52, 0xb3, 0xa6, 0xed, 0x3d, 0x35, 0xaf, 0xed, 0x3b, 0x75, 0x44,
+        0xdb, 0x7f, 0x6a, 0x41, 0x73, 0x4f, 0x49, 0x45, 0xdf, 0xd3, 0x29, 0x05,
+        0xeb, 0xb4, 0x56, 0x6c, 0xf6, 0x6b, 0xee, 0xe2, 0x7b, 0xbe, 0xeb, 0x64,
+        0xad, 0xbb, 0xc4, 0x2c, 0x80, 0x16, 0x71, 0x6b, 0x3e, 0xc6, 0xa6, 0x14,
+        0x52, 0xbe, 0xaf, 0xe7, 0xfd, 0x27, 0xdc, 0x9c, 0x6d, 0xe9, 0x5a, 0x4a,
+        0xaa, 0xcd, 0x7e, 0xe0, 0xed, 0xd4, 0x8a, 0x8b, 0xa6, 0x56, 0xf2, 0xfc,
+        0x73, 0xae, 0x23, 0x03, 0x86, 0xf8, 0xfe, 0x9c, 0xb3, 0x33, 0x7d, 0x48,
+        0x4e, 0x02, 0x6f, 0x03, 0xf8, 0xc4, 0xd2, 0xf3, 0xa4, 0x8f, 0x74, 0x92,
+        0xe4, 0x8a, 0x56, 0x1c, 0x8a, 0xe8, 0x93, 0x0c, 0xe9, 0x2f, 0xaf, 0xe8,
+        0xa0, 0x73, 0x8b, 0x94, 0xeb, 0x96, 0x4c, 0xad, 0x6c, 0x5c, 0x7f, 0xd9,
+        0x7f, 0x71, 0x28, 0x25, 0xcf, 0x36, 0xb3, 0x47, 0x2a, 0x92, 0x90, 0x39,
+        0x2f, 0x23, 0x7a, 0x5e, 0x0a, 0x6e, 0x6e, 0x40, 0xce, 0x35, 0xd3, 0xf2,
+        0x5c, 0xd3, 0x4e, 0x57, 0x65, 0x93, 0x94, 0x53, 0x96, 0x9c, 0x6d, 0xa6,
+        0x70, 0x46, 0xff, 0x9c, 0x6e, 0xdb, 0x56, 0x15, 0x6b, 0xab, 0xcd, 0x97,
+        0xf8, 0xef, 0x5f, 0xac, 0xe9, 0x9c, 0x82, 0xa9, 0x80, 0xee, 0x70, 0x2d,
+        0xcf, 0xa1, 0xd6, 0xaa, 0xb3, 0x04, 0x6b, 0xa5, 0x32, 0x9d, 0xc3, 0x5c,
+        0x73, 0x34, 0xe4, 0xef, 0x16, 0x9c, 0x97, 0x4f, 0x4b, 0xaa, 0x9e, 0x01,
+        0xde, 0xb0, 0xff, 0xcf, 0xc0, 0x37, 0x80, 0xf3, 0x5e, 0xab, 0x7e, 0xee,
+        0xa2, 0xa4, 0x74, 0xd9, 0x99, 0x2e, 0x0b, 0x78, 0xdb, 0xec, 0xc4, 0x98,
+        0xf4, 0xf9, 0xfe, 0x7e, 0x47, 0xac, 0xaa, 0xd3, 0x03, 0x98, 0x8c, 0x54,
+        0x9d, 0x6e, 0xe0, 0x69, 0x13, 0xcb, 0xe6, 0xb9, 0xb8, 0xd7, 0x66, 0xcc,
+        0xfb, 0x5d, 0x46, 0xde, 0xf7, 0xa7, 0x73, 0xd2, 0x1d, 0xcc, 0xed, 0x56,
+        0x38, 0xa6, 0x26, 0x34, 0xac, 0xfb, 0x05, 0x69, 0x4e, 0x24, 0xf3, 0xec,
+        0xf3, 0x99, 0x13, 0x77, 0xfe, 0xda, 0x90, 0x96, 0x34, 0x68, 0xb9, 0x26,
+        0xec, 0x83, 0xff, 0x1e, 0xf8, 0xe0, 0x7c, 0x06, 0x63, 0xed, 0x3a, 0xe0,
+        0x19, 0xae, 0x0a, 0xf7, 0xe8, 0x93, 0xa5, 0x94, 0xe8, 0x57, 0x9c, 0xde,
+        0x70, 0x5d, 0x37, 0x68, 0x8d, 0xf4, 0xa0, 0x5f, 0xe6, 0x16, 0xc9, 0xeb,
+        0x1a, 0x64, 0x83, 0xe7, 0x8d, 0x15, 0xad, 0xd0, 0x3c, 0x82, 0xbe, 0x29,
+        0xd3, 0xb6, 0x7f, 0x6e, 0xce, 0x99, 0xd7, 0x8a, 0xa7, 0x4e, 0x6a, 0xa5,
+        0x53, 0x2f, 0x68, 0x7b, 0x9b, 0x2f, 0x74, 0x49, 0x47, 0x16, 0xa7, 0x4e,
+        0xc8, 0x93, 0x9e, 0x26, 0xa4, 0x73, 0x09, 0xbc, 0x2b, 0x58, 0x15, 0x31,
+        0xed, 0x6e, 0x6d, 0x1f, 0xf0, 0xb4, 0xd9, 0x7f, 0xd2, 0x29, 0xdd, 0x86,
+        0x6c, 0xb2, 0xa3, 0xb5, 0x29, 0xf9, 0x33, 0xd0, 0x74, 0xc1, 0x49, 0x91,
+        0x5f, 0x3d, 0x01, 0x4c, 0x44, 0x07, 0xf5, 0x8a, 0x3a, 0xa5, 0x17, 0x4a,
+        0xc7, 0xff, 0xbc, 0xaf, 0x3a, 0xb2, 0x85, 0x6b, 0xa0, 0xff, 0xd6, 0xfd,
+        0xd3, 0xb6, 0xdb, 0x6b, 0x4a, 0xc5, 0xd2, 0x25, 0x6b, 0x15, 0xe5, 0x3a,
+        0x99, 0x73, 0x44, 0x8a, 0x35, 0xec, 0x69, 0x9b, 0xe0, 0x8d, 0x0d, 0xde,
+        0xec, 0x3c, 0x32, 0xa8, 0xff, 0x96, 0x64, 0xfa, 0x2b, 0x9a, 0x19, 0xf2,
+        0x71, 0x49, 0x6e, 0x51, 0xf0, 0x7a, 0xde, 0x81, 0x7e, 0x76, 0xb0, 0x8f,
+        0x7d, 0x13, 0x6a, 0x5f, 0x23, 0x6f, 0xa7, 0x97, 0x45, 0x34, 0x3d, 0xbf,
+        0x1b, 0xf8, 0xa8, 0xb7, 0x5c, 0xf7, 0x04, 0x68, 0x24, 0xed, 0xec, 0xdb,
+        0x80, 0x49, 0x88, 0xeb, 0x74, 0xb5, 0xd0, 0x49, 0x79, 0x93, 0xd7, 0xe4,
+        0x9d, 0x3a, 0xa7, 0xb6, 0x76, 0xce, 0x5f, 0xf9, 0x9b, 0x46, 0x4d, 0xf9,
+        0xa1, 0x3a, 0x2f, 0x6d, 0x8c, 0xeb, 0x52, 0xa1, 0x4e, 0x24, 0xa0, 0x47,
+        0xa2, 0x95, 0x1d, 0x6b, 0x15, 0x57, 0x59, 0x44, 0x37, 0xf2, 0x9d, 0x52,
+        0x54, 0xf4, 0x8d, 0x61, 0x2f, 0xda, 0x1e, 0x6c, 0xc8, 0xe6, 0x59, 0x38,
+        0x97, 0x87, 0x8d, 0x67, 0xd9, 0x97, 0xf2, 0x02, 0xed, 0x9d, 0xb4, 0x9d,
+        0xcf, 0xaa, 0x7f, 0x8e, 0x45, 0x5d, 0x3c, 0xd6, 0x03, 0xda, 0x38, 0x86,
+        0x1d, 0xda, 0x78, 0x3f, 0xa2, 0x89, 0x3b, 0x36, 0x08, 0xfe, 0x70, 0x9d,
+        0x9d, 0x81, 0x9c, 0x0b, 0x2e, 0xf6, 0x74, 0x9d, 0xdf, 0x50, 0x3c, 0xe8,
+        0xc5, 0x79, 0x06, 0xe7, 0xc9, 0xaf, 0x0e, 0xe8, 0xb6, 0x26, 0x65, 0x27,
+        0x9b, 0xa1, 0xdc, 0x03, 0xda, 0x75, 0xd9, 0x74, 0x63, 0x2b, 0xed, 0x91,
+        0xac, 0xa8, 0x87, 0xa6, 0x24, 0x47, 0xb9, 0x96, 0xeb, 0xb8, 0x3e, 0x3b,
+        0x26, 0xfa, 0xaf, 0x7c, 0x6b, 0xdd, 0x59, 0x6d, 0xd9, 0x31, 0x0f, 0x1a,
+        0x02, 0xde, 0x82, 0x27, 0x9f, 0xb6, 0x96, 0x7c, 0xdd, 0xc8, 0x3f, 0xae,
+        0x6d, 0x5d, 0x07, 0x9d, 0xe8, 0x27, 0x0d, 0x27, 0x3a, 0x03, 0x5b, 0x8b,
+        0x68, 0x8a, 0x64, 0xa3, 0x85, 0x38, 0x3e, 0xe9, 0x1c, 0x5c, 0x0f, 0x1f,
+        0xe0, 0xc1, 0x07, 0xc0, 0xaf, 0x3d, 0xeb, 0xc1, 0xfe, 0x3d, 0xfa, 0x8c,
+        0x8c, 0xbc, 0x38, 0x04, 0x1f, 0xb7, 0xe6, 0x63, 0xd0, 0xc6, 0xd1, 0xd7,
+        0xc5, 0x80, 0x8f, 0x99, 0xad, 0xeb, 0xb0, 0x59, 0xf0, 0x78, 0x85, 0x73,
+        0xb0, 0xed, 0x95, 0x12, 0x9e, 0xb6, 0x54, 0x1b, 0xd4, 0xab, 0xc8, 0x97,
+        0xd2, 0xe7, 0xa4, 0xe1, 0x5f, 0xe8, 0x77, 0xe8, 0x57, 0xb8, 0xd6, 0xf7,
+        0x4b, 0x0e, 0x61, 0x7d, 0x99, 0x70, 0x68, 0x43, 0x9d, 0xa2, 0x27, 0x2b,
+        0xda, 0xc1, 0x21, 0xd8, 0xd6, 0xf5, 0x6d, 0xa0, 0x95, 0x36, 0x76, 0x8d,
+        0x48, 0x3b, 0xf7, 0xfb, 0x69, 0x57, 0xf0, 0xef, 0xee, 0x36, 0x61, 0x0d,
+        0x9f, 0xef, 0x86, 0x63, 0x2d, 0xf4, 0x2d, 0x7c, 0x9f, 0xcd, 0x14, 0xa4,
+        0x3f, 0x1c, 0xb3, 0xbf, 0x4a, 0xaf, 0xa3, 0xdf, 0x98, 0x90, 0x1d, 0x27,
+        0x03, 0x9f, 0xb8, 0x63, 0xc9, 0x12, 0xfb, 0x64, 0x40, 0xe3, 0x8e, 0x33,
+        0x91, 0x6f, 0x7c, 0x1f, 0xf0, 0xa0, 0xcf, 0x5b, 0x8d, 0x03, 0x68, 0x3f,
+        0xd3, 0x60, 0x2a, 0x98, 0xdb, 0xc8, 0x0b, 0xfa, 0x63, 0xda, 0x9b, 0xd5,
+        0x6a, 0x6f, 0x7b, 0x60, 0x6f, 0x4e, 0xbb, 0x64, 0x9d, 0xbf, 0x87, 0xbd,
+        0x7d, 0xc3, 0xd1, 0xc0, 0x1b, 0x91, 0x8b, 0xb5, 0x34, 0x6c, 0xdd, 0x4c,
+        0xbf, 0x26, 0x3b, 0x33, 0xb3, 0xa2, 0xc9, 0x09, 0xce, 0x35, 0x30, 0xa7,
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+        0x94, 0x97, 0x7f, 0x0a, 0xef, 0x5e, 0xe9, 0xdc, 0xba, 0x19, 0xb3, 0x1b,
+        0xed, 0x9a, 0xb2, 0x6b, 0x30, 0x88, 0xb9, 0xab, 0xdb, 0x68, 0x83, 0x39,
+        0x80, 0x19, 0xaf, 0x43, 0x87, 0x34, 0x9c, 0x6e, 0x8d, 0xfd, 0x1a, 0xce,
+        0x21, 0x9d, 0x77, 0xcb, 0x71, 0x0a, 0x45, 0x5b, 0xe6, 0x8a, 0x56, 0x32,
+        0x0f, 0xfa, 0xbb, 0x01, 0xbb, 0x6d, 0x15, 0x77, 0xb0, 0x86, 0x33, 0x58,
+        0xaf, 0x53, 0xcf, 0x6f, 0x6a, 0xd9, 0xbb, 0x5c, 0xff, 0x23, 0xc6, 0xb1,
+        0xce, 0xa4, 0xe5, 0x0f, 0x7d, 0x94, 0x81, 0xf4, 0x4d, 0x65, 0x75, 0xff,
+        0xa0, 0xdf, 0x2a, 0xda, 0xae, 0xd5, 0x29, 0x8f, 0x45, 0x2e, 0x79, 0x36,
+        0x74, 0xc9, 0xcb, 0x09, 0x62, 0x80, 0xb2, 0x6a, 0xf6, 0xf3, 0xc3, 0x35,
+        0xfb, 0xfe, 0x5e, 0x9b, 0xeb, 0x72, 0x42, 0xb9, 0x4d, 0xdd, 0xbf, 0xa1,
+        0xb1, 0x8d, 0x57, 0x7a, 0x56, 0xde, 0xc4, 0x7d, 0x07, 0x18, 0x27, 0x27,
+        0x6f, 0x00, 0xe3, 0xd5, 0x4b, 0xcd, 0xbc, 0xed, 0x93, 0x38, 0xa7, 0x92,
+        0x9a, 0xbb, 0xda, 0x29, 0x97, 0xaf, 0x15, 0xd4, 0x4b, 0xd7, 0x3c, 0xf5,
+        0xf3, 0xab, 0x45, 0x55, 0xb8, 0xea, 0xfb, 0xff, 0x70, 0x67, 0xe4, 0x9d,
+        0x25, 0x5f, 0x4e, 0xbb, 0x46, 0x7f, 0x44, 0x9a, 0xf9, 0x74, 0xbe, 0xdf,
+        0x01, 0xd9, 0xbc, 0x7e, 0xc0, 0xf7, 0x1f, 0x19, 0x19, 0x11, 0xe7, 0x00,
+        0x31, 0xca, 0x70, 0x82, 0x39, 0xae, 0x94, 0x39, 0x19, 0xdb, 0x3e, 0x5f,
+        0x51, 0x0a, 0xf2, 0xad, 0x3b, 0xc0, 0x2f, 0x8f, 0xee, 0x0b, 0xe3, 0x26,
+        0x3f, 0x7c, 0x9e, 0x7e, 0xe5, 0xc4, 0xe7, 0xfc, 0xca, 0xa6, 0x9c, 0x2d,
+        0xf6, 0xa2, 0x7f, 0x4c, 0x7e, 0x50, 0x8c, 0xee, 0x2a, 0x9b, 0x78, 0x3a,
+        0x46, 0xa1, 0x78, 0xcf, 0x1f, 0xd4, 0xf1, 0x03, 0x60, 0x12, 0xd3, 0xf7,
+        0x67, 0x5d, 0xce, 0xd7, 0x8d, 0xf9, 0x36, 0xcc, 0x7d, 0xd0, 0xff, 0xa7,
+        0xb5, 0x7e, 0x2e, 0x2b, 0xd8, 0xc1, 0xe0, 0xef, 0x98, 0x8c, 0x15, 0xa1,
+        0xe3, 0x15, 0xf3, 0x4c, 0x89, 0x15, 0xac, 0xc4, 0x2c, 0x64, 0xc7, 0x0c,
+        0xe4, 0xcd, 0x29, 0x1d, 0x67, 0xed, 0xd5, 0xb2, 0x67, 0x8e, 0xe5, 0x9c,
+        0xa4, 0x2b, 0x6e, 0x8f, 0x3e, 0xbf, 0xcd, 0x1b, 0x2f, 0x26, 0x82, 0x3b,
+        0x07, 0x1f, 0xe7, 0x94, 0xb4, 0xc1, 0x1e, 0xca, 0xae, 0x4c, 0x81, 0x27,
+        0x12, 0x38, 0xdb, 0x56, 0xcd, 0x0f, 0x0d, 0xe8, 0xef, 0x86, 0xf6, 0x29,
+        0x06, 0xb1, 0x8b, 0x86, 0xc9, 0x76, 0xa7, 0xd0, 0xaf, 0x5d, 0x32, 0x57,
+        0xdb, 0xb4, 0x5c, 0x7d, 0xb8, 0x2e, 0x0d, 0x1c, 0xf2, 0x04, 0xca, 0x11,
+        0xd4, 0x25, 0xc3, 0xb2, 0x81, 0xf2, 0x34, 0xca, 0x2d, 0x78, 0xb2, 0xcd,
+        0x61, 0xe0, 0x0a, 0x3c, 0x5f, 0xc3, 0x78, 0x23, 0x58, 0x73, 0xce, 0x94,
+        0x8f, 0x4e, 0x50, 0x97, 0x38, 0x06, 0x73, 0x91, 0x67, 0x6d, 0x3c, 0x6b,
+        0x45, 0x95, 0x5d, 0x60, 0x19, 0xcf, 0x72, 0xf0, 0xfd, 0x21, 0x99, 0x84,
+        0x3e, 0x99, 0x6b, 0x81, 0x4c, 0xfa, 0x68, 0x5b, 0x26, 0xb1, 0xae, 0x5d,
+        0xc6, 0xae, 0x92, 0xd7, 0x4d, 0xd0, 0x5b, 0xa7, 0x64, 0xaf, 0xc5, 0x34,
+        0x1e, 0xad, 0x80, 0x16, 0xaf, 0x83, 0xae, 0x96, 0x41, 0x53, 0x99, 0xa2,
+        0x35, 0x3a, 0xad, 0x92, 0xda, 0x2f, 0xf0, 0x38, 0xe8, 0xb5, 0xe3, 0x0a,
+        0xb1, 0x28, 0x79, 0xd9, 0x01, 0xed, 0x89, 0xdf, 0x61, 0xdb, 0x93, 0x8e,
+        0xb2, 0x41, 0x83, 0xa0, 0xcb, 0x62, 0xc0, 0xd3, 0xef, 0x29, 0x2d, 0x57,
+        0x47, 0xef, 0x48, 0x2a, 0x7d, 0x47, 0x2c, 0xc8, 0x02, 0xcb, 0xfd, 0x50,
+        0x5c, 0x8c, 0x79, 0x5c, 0x5e, 0xc7, 0x3c, 0x06, 0xf8, 0xfb, 0xc8, 0x90,
+        0xe6, 0xef, 0x51, 0x89, 0xec, 0xe6, 0x71, 0xd0, 0x1b, 0x64, 0x50, 0xc0,
+        0xd3, 0xe9, 0x90, 0x46, 0x9f, 0x06, 0xff, 0x5a, 0xb0, 0xca, 0x92, 0x32,
+        0x0f, 0xfe, 0xbf, 0x8e, 0xef, 0xb7, 0xea, 0x9f, 0xaa, 0xb9, 0x05, 0x15,
+        0xe6, 0xb2, 0x7c, 0x1b, 0x38, 0xf9, 0xf7, 0x38, 0xbb, 0x2e, 0x8d, 0xdd,
+        0x07, 0x46, 0x18, 0x4b, 0xfb, 0xb7, 0xba, 0x6c, 0x1f, 0x95, 0xcd, 0xe1,
+        0xe3, 0x28, 0xef, 0xc3, 0xd3, 0xc0, 0x39, 0x44, 0x75, 0x2c, 0x7c, 0xd9,
+        0x1b, 0x36, 0x0a, 0x3a, 0xef, 0xe0, 0x98, 0xce, 0xcf, 0x37, 0xec, 0x03,
+        0xf8, 0x4e, 0xbf, 0x0c, 0xf7, 0x06, 0xcc, 0xa4, 0x12, 0x3a, 0xc7, 0xb4,
+        0x02, 0x2c, 0xb1, 0x82, 0xf1, 0xde, 0xa7, 0x5f, 0xaf, 0x06, 0x1e, 0x1e,
+        0xfe, 0xa7, 0x9f, 0x8e, 0x31, 0x27, 0x7d, 0x33, 0x11, 0xe8, 0xbf, 0xcf,
+        0xfc, 0x4d, 0x7b, 0x6e, 0xd4, 0xc0, 0xcb, 0x6d, 0x33, 0x86, 0xb6, 0xd0,
+        0x65, 0xd0, 0x45, 0x65, 0x4d, 0xbf, 0x6c, 0x17, 0xf4, 0x2d, 0xd4, 0x52,
+        0xe6, 0x07, 0x12, 0xf4, 0x9d, 0xb7, 0xa9, 0x77, 0xda, 0x21, 0x5f, 0x92,
+        0x1a, 0x57, 0xbe, 0x6f, 0xe7, 0x21, 0x15, 0xac, 0xe4, 0x24, 0x68, 0xb4,
+        0x4d, 0x2c, 0x67, 0x5c, 0x1e, 0xcc, 0x3b, 0xab, 0xfb, 0xb2, 0x6d, 0xb3,
+        0x6f, 0x73, 0x5e, 0xae, 0x9f, 0x7b, 0xe1, 0x1e, 0xe8, 0xa7, 0x36, 0x35,
+        0x8d, 0x36, 0x6a, 0xed, 0xfd, 0x01, 0x8d, 0x36, 0xf7, 0x11, 0xfb, 0x3f,
+        0xfb, 0x20, 0x9d, 0x0c, 0x1b, 0x41, 0x0e, 0x06, 0x9e, 0x35, 0x9e, 0xe7,
+        0xa7, 0xc0, 0xf7, 0x3b, 0xe9, 0xa7, 0xe9, 0x67, 0x0c, 0xe8, 0xe7, 0x91,
+        0x6d, 0xfa, 0x21, 0xdd, 0x74, 0xca, 0xd8, 0x35, 0x5b, 0x26, 0x8a, 0xfa,
+        0xbe, 0x81, 0x35, 0xe9, 0x3f, 0x3a, 0x0e, 0xba, 0x21, 0xad, 0x93, 0xb7,
+        0x4c, 0x29, 0x83, 0x8e, 0xca, 0x90, 0x4f, 0x65, 0xd0, 0x14, 0x31, 0x50,
+        0x19, 0xf2, 0xad, 0x5c, 0xb7, 0x9c, 0x2a, 0xf6, 0x4c, 0x9d, 0xbd, 0x02,
+        0x3a, 0xba, 0x5e, 0xe7, 0xfd, 0xeb, 0x35, 0x9b, 0xd4, 0x83, 0xb7, 0xb6,
+        0xef, 0xfe, 0xef, 0xb8, 0xfb, 0x43, 0x72, 0x03, 0x76, 0xcb, 0x9b, 0xa5,
+        0x61, 0xc8, 0x24, 0x21, 0x5e, 0x04, 0x6d, 0x8c, 0xca, 0x6a, 0xe9, 0xa4,
+        0xac, 0x41, 0x3f, 0xad, 0x2f, 0x0d, 0x00, 0x4f, 0x43, 0x8e, 0xbe, 0x72,
+        0x44, 0xde, 0x58, 0x52, 0x32, 0x63, 0x43, 0xbf, 0x2c, 0xd3, 0x07, 0x0f,
+        0x7a, 0x2e, 0x77, 0xea, 0x98, 0xfd, 0x58, 0x35, 0xf0, 0xc5, 0x8f, 0x57,
+        0xbb, 0x64, 0xa2, 0x6a, 0xca, 0x63, 0xd5, 0x1e, 0x79, 0xa2, 0x1a, 0x93,
+        0xd3, 0xb5, 0x84, 0x7c, 0xa3, 0x7a, 0x50, 0x4e, 0x55, 0x0f, 0xc9, 0x93,
+        0xb5, 0xa4, 0x7c, 0x13, 0x76, 0x61, 0xae, 0xe6, 0xc8, 0x64, 0x6d, 0x58,
+        0x1e, 0xaf, 0xd1, 0xc7, 0x8e, 0xf9, 0xf0, 0xcb, 0x6e, 0xfb, 0x2e, 0xb8,
+        0xae, 0x0e, 0xac, 0xcb, 0x51, 0xe3, 0x3a, 0x66, 0x29, 0xb9, 0xc0, 0xff,
+        0x21, 0x72, 0x0e, 0x7d, 0x2f, 0xbe, 0xa2, 0xa4, 0xa2, 0xe7, 0x6f, 0xfe,
+        0xdf, 0x48, 0x54, 0xdb, 0x46, 0xe7, 0xca, 0x07, 0xd1, 0xc6, 0xa6, 0x4d,
+        0x12, 0xfa, 0x41, 0x9a, 0xfe, 0xff, 0xa6, 0xed, 0x65, 0x68, 0x1f, 0xf6,
+        0x2d, 0xda, 0x5e, 0xfa, 0xec, 0x29, 0x3f, 0x68, 0xe7, 0xd0, 0xd6, 0xda,
+        0x19, 0xe7, 0x68, 0xce, 0x7b, 0x31, 0xf7, 0xf0, 0xff, 0xa7, 0x04, 0xf1,
+        0xaa, 0xb3, 0xb5, 0x83, 0xfc, 0x3f, 0x15, 0xac, 0xe5, 0x8b, 0xf3, 0xc5,
+        0x27, 0x4a, 0x63, 0xea, 0xb1, 0x12, 0x11, 0x8d, 0x2f, 0x17, 0xb7, 0x73,
+        0xf2, 0xbe, 0x2e, 0xcb, 0x6e, 0x54, 0xaf, 0x21, 0xf0, 0xdb, 0xa7, 0x75,
+        0x7e, 0xde, 0xd8, 0x10, 0xe9, 0x8f, 0x71, 0xb8, 0xae, 0x30, 0xb6, 0x00,
+        0x6c, 0xeb, 0x9a, 0x72, 0xa9, 0x1a, 0xf8, 0xaf, 0xe6, 0x34, 0xbd, 0xbc,
+        0x05, 0x9a, 0x63, 0xfc, 0x21, 0x78, 0xe6, 0xcb, 0x41, 0xdf, 0xec, 0x90,
+        0x43, 0x7b, 0x1c, 0xfb, 0x35, 0x7a, 0x38, 0x17, 0xff, 0x4f, 0x07, 0xe5,
+        0x70, 0xbd, 0xcc, 0x2f, 0xb6, 0x35, 0x2d, 0x06, 0x31, 0x5e, 0x47, 0x9e,
+        0xc3, 0x5d, 0x54, 0x4c, 0xae, 0xbf, 0x43, 0x2a, 0x0e, 0x6d, 0x5b, 0xca,
+        0xef, 0x21, 0x29, 0x63, 0x9e, 0x8a, 0xd3, 0xf4, 0x8d, 0x05, 0x72, 0xb6,
+        0x62, 0x3e, 0x98, 0x77, 0xba, 0xbc, 0x1f, 0xef, 0xa8, 0x73, 0x80, 0x99,
+        0xa6, 0xf8, 0x7e, 0x11, 0x65, 0xfa, 0x46, 0xe6, 0xf0, 0x4c, 0x84, 0x75,
+        0xaf, 0xf5, 0x6b, 0xac, 0x7e, 0xf2, 0x41, 0xbf, 0x99, 0xb2, 0x95, 0xcf,
+        0x44, 0xb6, 0x94, 0xf1, 0x8b, 0xf5, 0x7e, 0xca, 0xdc, 0xfd, 0x36, 0x7f,
+        0x51, 0xf9, 0x8b, 0xa9, 0x7d, 0x0a, 0xe1, 0xb7, 0x3d, 0xf2, 0x94, 0xc9,
+        0xdc, 0xf5, 0xb4, 0x1a, 0x2b, 0xfd, 0x34, 0xcc, 0xd3, 0xdd, 0x52, 0xfb,
+        0x2b, 0x6f, 0xf7, 0x07, 0x79, 0xee, 0x1c, 0x7b, 0x67, 0x6e, 0xfb, 0x4e,
+        0x3a, 0x61, 0x8e, 0x7b, 0x3b, 0x70, 0xab, 0x56, 0x62, 0xe0, 0x41, 0xc8,
+        0x3b, 0xbb, 0x45, 0xf3, 0x63, 0xa1, 0xf6, 0x2f, 0x7f, 0x43, 0xf3, 0x73,
+        0xd3, 0xc7, 0xf0, 0xdb, 0x7e, 0xda, 0xb6, 0x94, 0x1b, 0x97, 0x02, 0xbf,
+        0x91, 0xb6, 0xa1, 0x21, 0x2b, 0x50, 0x47, 0x5e, 0x05, 0x9f, 0x6c, 0xb7,
+        0xe5, 0xdf, 0x7f, 0x01, 0x99, 0xe7, 0xd3, 0x46, 0x40, 0x67, 0x00, 0x00,
+        0x00 };
+static u32 bnx2_RXP_b09FwData[(0x0/4) + 1] = { 0x0 };
+static u32 bnx2_RXP_b09FwRodata[(0x278/4) + 1] = {
+        0x08003fa4, 0x08003ea4, 0x08003f48, 0x08003f60, 0x08003f78, 0x08003f98,
+        0x08003fa4, 0x08003fa4, 0x08003eac, 0x00000000, 0x080049d4, 0x08004a0c,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004a44, 0x08004c08,
+        0x08004b50, 0x08004b88, 0x08004c08, 0x08004ad8, 0x08004c08, 0x08004c08,
+        0x08004b88, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004bc8,
+        0x08004c08, 0x08004bc8, 0x08004b50, 0x08004c08, 0x08004c08, 0x08004bc8,
+        0x08004bc8, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
+        0x08004ab4, 0x00000000, 0x0800602c, 0x08006044, 0x08006044, 0x08006044,
+        0x0800602c, 0x08006044, 0x08006044, 0x08006044, 0x0800602c, 0x08006044,
+        0x08006044, 0x08006044, 0x0800602c, 0x08006044, 0x08006044, 0x08006044,
+        0x08006038, 0x00000000, 0x00000000 };
+static u32 bnx2_RXP_b09FwBss[(0x13dc/4) + 1] = { 0x0 };
+static u32 bnx2_RXP_b09FwSbss[(0x2c/4) + 1] = { 0x0 };
+
+static struct fw_info bnx2_rxp_fw_09 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x08003184,
+
+        .text_addr                      = 0x08000000,
+        .text_len                       = 0x673c,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_RXP_b09FwText,
+        .gz_text_len                    = sizeof(bnx2_RXP_b09FwText),
+
+        .data_addr                      = 0x080069e0,
+        .data_len                       = 0x0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_RXP_b09FwData,
+
+        .sbss_addr                      = 0x080069e0,
+        .sbss_len                       = 0x2c,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_RXP_b09FwSbss,
+
+        .bss_addr                       = 0x08006a10,
+        .bss_len                        = 0x13dc,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_RXP_b09FwBss,
+
+        .rodata_addr                    = 0x08006740,
+        .rodata_len                     = 0x278,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_RXP_b09FwRodata,
+};
+
+static u8 bnx2_TPAT_b09FwText[] = {
+        0x1f, 0x8b, 0x08, 0x08, 0xdb, 0xfd, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
+        0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x58, 0x5d, 0x6c,
+        0x1c, 0x57, 0x15, 0x3e, 0xf3, 0xbb, 0x13, 0x77, 0xed, 0xbd, 0x49, 0x97,
+        0x6a, 0x13, 0xb9, 0x74, 0xc6, 0x1e, 0x3b, 0x8b, 0x1c, 0x35, 0x93, 0xb0,
+        0x24, 0x16, 0x5a, 0xd1, 0xc9, 0xcc, 0xae, 0x6b, 0xe5, 0x29, 0x86, 0xbc,
+        0xf1, 0xb2, 0xac, 0xed, 0x46, 0x54, 0x48, 0x4d, 0x51, 0x84, 0x22, 0x81,
+        0x94, 0x65, 0x76, 0x53, 0x40, 0x5a, 0x65, 0xc1, 0xa0, 0x04, 0x21, 0x84,
+        0x22, 0x9b, 0x66, 0x91, 0x58, 0x3c, 0x4d, 0xe9, 0x6b, 0x94, 0xbc, 0x90,
+        0x96, 0x17, 0x9e, 0x4b, 0x9e, 0xac, 0x02, 0x12, 0x0f, 0xa8, 0x8a, 0x78,
+        0x40, 0x15, 0x0d, 0x1e, 0xbe, 0x33, 0x3f, 0x9b, 0x5d, 0xd7, 0x29, 0x79,
+        0xa8, 0x84, 0xa5, 0xf1, 0xcc, 0xfd, 0x39, 0xf7, 0xe7, 0x7c, 0xdf, 0x77,
+        0xee, 0xb9, 0x5b, 0x92, 0x69, 0x82, 0xd2, 0xbf, 0x49, 0x3c, 0x97, 0xbe,
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+        0xed, 0x39, 0x1c, 0x73, 0x3f, 0xaf, 0xd0, 0x43, 0x8a, 0x39, 0x29, 0x4e,
+        0x20, 0x16, 0x9f, 0x86, 0x8d, 0x1b, 0xeb, 0x31, 0xc9, 0xbd, 0x32, 0x9b,
+        0x0f, 0xf7, 0x8c, 0xf1, 0x17, 0x65, 0xbc, 0xec, 0x82, 0xd3, 0x95, 0x74,
+        0xbe, 0x51, 0x8e, 0x2c, 0x20, 0xe5, 0x79, 0xa0, 0x0d, 0xf3, 0xb7, 0xa2,
+        0x8e, 0x7e, 0xbc, 0x46, 0xd6, 0x25, 0xdb, 0x1c, 0xd1, 0xc6, 0xc7, 0x99,
+        0xdd, 0x67, 0x8c, 0xea, 0xc8, 0x18, 0x45, 0xde, 0x9b, 0x68, 0x3a, 0xcf,
+        0xa4, 0xf7, 0x0c, 0x8e, 0x2d, 0x02, 0x3a, 0x95, 0x9f, 0x93, 0xb1, 0x0f,
+        0x0f, 0x7b, 0xf6, 0xe3, 0xfa, 0x5f, 0xe9, 0xe3, 0xe3, 0xfe, 0x56, 0x4d,
+        0xca, 0xc7, 0x12, 0x6e, 0xda, 0x78, 0x87, 0x0f, 0x46, 0xd6, 0xae, 0xed,
+        0x33, 0xef, 0xd7, 0x38, 0x5d, 0x43, 0xbc, 0x21, 0x57, 0xc1, 0x1d, 0xcc,
+        0x27, 0x7c, 0x87, 0xaf, 0x67, 0x3e, 0x04, 0x6f, 0xe8, 0x5c, 0x3b, 0xe5,
+        0x8b, 0x9c, 0xf0, 0x85, 0xf3, 0xba, 0xc5, 0x55, 0xf0, 0xa5, 0x0d, 0xbe,
+        0xc0, 0xae, 0xa1, 0x55, 0xa7, 0xc1, 0x05, 0x8e, 0x4d, 0x28, 0x87, 0xcc,
+        0x1d, 0xe6, 0x0a, 0xf3, 0xe6, 0x31, 0x5f, 0x5e, 0xe9, 0x1a, 0xc6, 0xe6,
+        0xa7, 0x70, 0xe5, 0x8d, 0x98, 0x2b, 0xcc, 0xd9, 0x24, 0x7e, 0x74, 0x80,
+        0x55, 0x90, 0xc6, 0x8f, 0x00, 0xf1, 0xa3, 0xc6, 0xf9, 0x4f, 0x1c, 0x0b,
+        0x12, 0xfd, 0xac, 0x41, 0x3f, 0x35, 0x85, 0xf3, 0x23, 0xd6, 0x0e, 0xdb,
+        0xb1, 0x7e, 0xd8, 0xae, 0x90, 0xda, 0x8d, 0xc7, 0x91, 0x76, 0xcf, 0x32,
+        0xb3, 0x38, 0xd2, 0x86, 0x76, 0x3a, 0xa9, 0x8e, 0xda, 0xa9, 0x8e, 0xd0,
+        0xa7, 0xa5, 0x54, 0xf8, 0x4c, 0xb0, 0x4c, 0x1f, 0xf1, 0xa3, 0x13, 0x8f,
+        0xd9, 0xa2, 0xe4, 0x2e, 0xc3, 0xda, 0xe6, 0xb8, 0x3b, 0x12, 0x6f, 0xd3,
+        0x7b, 0x6e, 0x23, 0xbe, 0xe7, 0x7e, 0x45, 0x1f, 0x8f, 0xb7, 0x38, 0x6b,
+        0xe2, 0x7b, 0xee, 0x29, 0x9d, 0xef, 0xb9, 0x01, 0x7d, 0x49, 0x1f, 0xbd,
+        0xe7, 0x06, 0x63, 0xf7, 0xdc, 0xcc, 0x96, 0xeb, 0xf7, 0x8b, 0xbb, 0x99,
+        0x4f, 0x38, 0xf6, 0x32, 0x9f, 0xf6, 0xcb, 0x15, 0xb3, 0x3e, 0x1c, 0x93,
+        0x58, 0xef, 0x1c, 0xcb, 0x92, 0xdc, 0xec, 0x6e, 0x98, 0xe9, 0xe2, 0x55,
+        0xcc, 0x83, 0x72, 0x6f, 0x3f, 0x5d, 0x18, 0xa9, 0x2e, 0x26, 0x13, 0x9b,
+        0xde, 0xa8, 0x36, 0x5e, 0xd5, 0xc7, 0xb5, 0x91, 0x8d, 0x93, 0x69, 0x23,
+        0x19, 0x73, 0x47, 0x29, 0xe1, 0x0c, 0x2c, 0x23, 0x1e, 0x09, 0xbe, 0xa3,
+        0x21, 0x5e, 0x54, 0xf3, 0xb8, 0xa7, 0x14, 0x78, 0xec, 0x76, 0xf8, 0x2c,
+        0x35, 0x8a, 0x8c, 0x0b, 0xaf, 0xff, 0x61, 0x7c, 0x7f, 0xc0, 0xba, 0x0b,
+        0x01, 0xff, 0xfe, 0xf1, 0x09, 0x3e, 0xbe, 0x06, 0x3e, 0x66, 0xfb, 0x19,
+        0xad, 0xbf, 0x34, 0x52, 0x5f, 0x4e, 0x31, 0x4f, 0x7c, 0x7e, 0x2f, 0xd5,
+        0xc8, 0x26, 0x72, 0xb7, 0xfb, 0xc8, 0x8b, 0xde, 0x44, 0xfc, 0x0e, 0x06,
+        0x1f, 0x47, 0xf7, 0x8a, 0x2a, 0x75, 0x86, 0x36, 0xbf, 0xc0, 0xba, 0x2d,
+        0x71, 0x13, 0x5f, 0x6f, 0x0c, 0xb2, 0xb1, 0xb9, 0x9d, 0xeb, 0xfe, 0x8d,
+        0xf3, 0x19, 0x79, 0xdf, 0xb0, 0xef, 0xfb, 0x11, 0xe7, 0xbb, 0x77, 0x81,
+        0xc5, 0x3b, 0xe1, 0x34, 0xfd, 0x1e, 0x1c, 0x7b, 0x3b, 0xce, 0x79, 0x93,
+        0x5c, 0x17, 0xfe, 0xc3, 0x99, 0xc7, 0x67, 0xbd, 0xf7, 0x39, 0x99, 0x2e,
+        0xd3, 0x57, 0x1d, 0xae, 0x93, 0xa9, 0x7e, 0x2a, 0x8a, 0x2e, 0xe2, 0xdc,
+        0x5f, 0x19, 0x3b, 0xf7, 0x71, 0x07, 0x3c, 0xc9, 0xf9, 0x7f, 0x96, 0xf3,
+        0xef, 0x46, 0x33, 0xf3, 0xd6, 0x4d, 0x97, 0x5c, 0xa9, 0xde, 0xe7, 0x7c,
+        0x6c, 0x98, 0x8b, 0x11, 0x1d, 0x7a, 0x14, 0xc9, 0xf3, 0x7c, 0x36, 0xbd,
+        0x9b, 0xfa, 0x1c, 0x6d, 0x37, 0x1e, 0xe1, 0x1e, 0x53, 0x8b, 0x7f, 0x17,
+        0x72, 0xfb, 0x3c, 0x0f, 0x97, 0xf1, 0x0e, 0x39, 0x47, 0x78, 0xd2, 0x6f,
+        0x35, 0x2a, 0xf0, 0xb5, 0xcc, 0x75, 0x85, 0xe2, 0x7b, 0x21, 0xee, 0x6e,
+        0x3f, 0x6f, 0x53, 0x12, 0x3b, 0x6a, 0xce, 0x39, 0xac, 0x05, 0x98, 0x88,
+        0x06, 0x30, 0x9e, 0x47, 0xac, 0xb2, 0xcc, 0x93, 0x72, 0xf2, 0x5b, 0xd5,
+        0x1a, 0xc6, 0x56, 0x4e, 0x72, 0x2e, 0xf9, 0x51, 0xb4, 0x36, 0x88, 0xcf,
+        0x44, 0x87, 0xb9, 0xe6, 0x87, 0x07, 0x65, 0x7e, 0xbb, 0x21, 0x7f, 0xeb,
+        0x98, 0xc7, 0x7c, 0x02, 0x0f, 0x8b, 0xa2, 0x76, 0xc3, 0x14, 0xf5, 0x9e,
+        0x29, 0x96, 0x7a, 0x32, 0x54, 0x52, 0xc8, 0xd1, 0x14, 0xe7, 0x08, 0x3a,
+        0xd1, 0x73, 0x58, 0xcb, 0x2d, 0x53, 0xf8, 0xc8, 0xa3, 0xbe, 0xad, 0x58,
+        0x62, 0x85, 0x76, 0xb1, 0xc7, 0x47, 0x51, 0x72, 0xa7, 0x35, 0x45, 0x6d,
+        0x38, 0xf7, 0x23, 0xcc, 0xcd, 0x6b, 0x62, 0x2d, 0xf3, 0x79, 0xb6, 0x2c,
+        0x9d, 0x83, 0x8f, 0xce, 0xf7, 0x77, 0x11, 0x43, 0xf9, 0x3c, 0xcb, 0x23,
+        0xe6, 0x59, 0x26, 0x5f, 0xf6, 0xef, 0x62, 0xff, 0xef, 0xf4, 0x80, 0x0f,
+        0x72, 0xc7, 0xb7, 0x87, 0x79, 0x1a, 0x63, 0x58, 0x06, 0x17, 0xd9, 0x3e,
+        0x8a, 0x82, 0xc5, 0x38, 0x47, 0xc1, 0x5a, 0xe6, 0xca, 0xb7, 0x90, 0xa7,
+        0xd7, 0x69, 0xa1, 0x5c, 0x8f, 0xdf, 0x11, 0x72, 0x12, 0xfe, 0x5d, 0xc0,
+        0x12, 0x4d, 0x7c, 0xd7, 0xd2, 0xef, 0x80, 0x73, 0xf8, 0x45, 0x1e, 0x83,
+        0x73, 0x79, 0xd6, 0xe1, 0x7f, 0x01, 0x17, 0xc6, 0xf1, 0xb2, 0x84, 0x14,
+        0x00, 0x00, 0x00 };
+static u32 bnx2_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 };
+static u32 bnx2_TPAT_b09FwRodata[(0x0/4) + 1] = { 0x0 };
+static u32 bnx2_TPAT_b09FwBss[(0x250/4) + 1] = { 0x0 };
+static u32 bnx2_TPAT_b09FwSbss[(0x34/4) + 1] = { 0x0 };
+
+static struct fw_info bnx2_tpat_fw_09 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x08000860,
+
+        .text_addr                      = 0x08000800,
+        .text_len                       = 0x1480,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_TPAT_b09FwText,
+        .gz_text_len                    = sizeof(bnx2_TPAT_b09FwText),
+
+        .data_addr                      = 0x08001ca0,
+        .data_len                       = 0x0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_TPAT_b09FwData,
+
+        .sbss_addr                      = 0x08001ca0,
+        .sbss_len                       = 0x34,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_TPAT_b09FwSbss,
+
+        .bss_addr                       = 0x08001ce0,
+        .bss_len                        = 0x250,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_TPAT_b09FwBss,
+
+        .rodata_addr                    = 0x00000000,
+        .rodata_len                     = 0x0,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_TPAT_b09FwRodata,
+};
+
+static u8 bnx2_TXP_b09FwText[] = {
+        0x1f, 0x8b, 0x08, 0x08, 0x51, 0xfe, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
+        0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xcd, 0x7b, 0x7f, 0x70,
+        0x1b, 0xe7, 0x99, 0xde, 0xbb, 0x0b, 0x80, 0x04, 0x29, 0x8a, 0x5a, 0x31,
+        0x30, 0x83, 0x38, 0xb4, 0x8d, 0x15, 0x17, 0x34, 0x6d, 0xf2, 0x1c, 0x58,
+        0xe5, 0xf9, 0xd8, 0x06, 0xb5, 0xd7, 0xc0, 0x92, 0xa2, 0x63, 0x26, 0x47,
+        0xbb, 0xcc, 0x9d, 0x92, 0x51, 0x7d, 0x28, 0x48, 0x29, 0x6e, 0xe3, 0xb4,
+        0xaa, 0xe3, 0x3f, 0x34, 0x4d, 0x5b, 0xc3, 0x00, 0x25, 0xcb, 0x2e, 0x44,
+        0xd0, 0x16, 0x63, 0xa5, 0x33, 0x37, 0x53, 0x18, 0x80, 0x28, 0xe7, 0xba,
+        0x24, 0xdc, 0xe4, 0x2e, 0xe9, 0x1f, 0xc9, 0x99, 0xa5, 0x6c, 0xc5, 0x6d,
+        0xae, 0x33, 0xbe, 0x3f, 0xda, 0xa6, 0x37, 0xd7, 0x19, 0x8d, 0xfc, 0x23,
+        0xce, 0x8f, 0xb9, 0xb8, 0x69, 0x7a, 0x56, 0x5b, 0xd9, 0xe8, 0xf3, 0x7c,
+        0xbb, 0x4b, 0x82, 0x32, 0x15, 0x5b, 0xd7, 0x76, 0xa6, 0x9c, 0xc1, 0x10,
+        0xfb, 0xed, 0xb7, 0xdf, 0xf7, 0xfe, 0x7e, 0xdf, 0xe7, 0xfd, 0x16, 0x71,
+        0x91, 0x6e, 0xf1, 0xff, 0x76, 0xe3, 0x93, 0x38, 0x7a, 0xec, 0xb1, 0x3b,
+        0xc6, 0xef, 0xd8, 0x2f, 0x72, 0xe7, 0x9d, 0xb2, 0x2b, 0xaa, 0xf3, 0xe6,
+        0xdb, 0x21, 0x91, 0xdc, 0x4f, 0xe5, 0xaf, 0xfc, 0x87, 0xc7, 0x8d, 0x60,
+        0x7d, 0x7e, 0x24, 0xaa, 0xa7, 0x5f, 0xcc, 0x64, 0x2c, 0x89, 0x86, 0xd2,
+        0x33, 0x9f, 0x9d, 0xb3, 0x44, 0x6c, 0x77, 0x24, 0x91, 0x95, 0xf7, 0x5a,
+        0x85, 0x58, 0x58, 0x38, 0x7e, 0x53, 0xfa, 0xca, 0xe3, 0xdf, 0xff, 0x2d,
+        0xf3, 0x9d, 0x6a, 0x48, 0xa2, 0x46, 0x3a, 0x27, 0xc6, 0x90, 0x44, 0x07,
+        0xf0, 0xcc, 0xef, 0xdf, 0x3a, 0xa5, 0x4b, 0x6f, 0xb0, 0x56, 0x5c, 0x16,
+        0x2a, 0x6f, 0xb7, 0xbe, 0x7f, 0x6b, 0x4c, 0xfe, 0x55, 0xd3, 0x90, 0x17,
+        0x9b, 0x61, 0x6d, 0xb2, 0xd2, 0x23, 0xa5, 0x8a, 0x2b, 0xc7, 0xcb, 0x05,
+        0xc9, 0x36, 0x5f, 0x90, 0xe2, 0xb2, 0xd1, 0x9b, 0x39, 0xf7, 0x07, 0x52,
+        0x5a, 0xee, 0xeb, 0xcd, 0x9e, 0x73, 0xa5, 0x58, 0x8e, 0xf7, 0x66, 0x9a,
+        0x46, 0x6f, 0xf6, 0x4c, 0x0c, 0xd7, 0x7d, 0xbd, 0x99, 0x33, 0x66, 0x41,
+        0xa4, 0x1f, 0x73, 0xe2, 0xbd, 0xd9, 0x8a, 0x99, 0x13, 0x19, 0x4c, 0xbd,
+        0x22, 0x03, 0xbd, 0xd9, 0x66, 0x4d, 0x5b, 0x37, 0x34, 0x29, 0xfe, 0x86,
+        0x18, 0xbd, 0xe9, 0xcb, 0xad, 0x4f, 0x58, 0x86, 0xec, 0xb5, 0x64, 0xcf,
+        0x1e, 0x4b, 0x9e, 0x88, 0xa7, 0xa3, 0x92, 0x3f, 0xdd, 0x25, 0xb6, 0xe2,
+        0xc9, 0x90, 0xfc, 0x99, 0x11, 0x63, 0x43, 0x22, 0x62, 0xc7, 0x82, 0xeb,
+        0x56, 0x2b, 0x93, 0xfa, 0x02, 0xe5, 0x8a, 0xbd, 0xa4, 0x77, 0xb2, 0x29,
+        0x92, 0xa9, 0x44, 0x25, 0x93, 0x7a, 0xaf, 0xe5, 0x3d, 0x13, 0xc5, 0xbe,
+        0xe1, 0xde, 0x89, 0x4a, 0xab, 0xe5, 0xa4, 0xb0, 0x47, 0x2a, 0x78, 0x36,
+        0x22, 0xd5, 0x98, 0x5d, 0x2d, 0xa5, 0x4c, 0xdd, 0xd3, 0x09, 0x79, 0xe4,
+        0xb5, 0x2d, 0xba, 0xf5, 0xdb, 0x92, 0x8f, 0x49, 0xb5, 0x98, 0xba, 0x4b,
+        0x9e, 0x4e, 0x19, 0x72, 0x12, 0xeb, 0x3d, 0x95, 0x82, 0x1c, 0xad, 0x63,
+        0x5a, 0xa6, 0x69, 0xc6, 0x45, 0x7b, 0x5a, 0x32, 0x67, 0x06, 0x8d, 0xac,
+        0x60, 0x6f, 0xab, 0x75, 0x4b, 0x26, 0x85, 0xfd, 0x46, 0xff, 0x67, 0xcb,
+        0x8e, 0x99, 0xb9, 0xaa, 0x0c, 0x48, 0xb1, 0x32, 0x98, 0xfa, 0x13, 0xd1,
+        0xa4, 0xd3, 0xa2, 0x7c, 0x5a, 0x72, 0x3f, 0xf6, 0xcd, 0x58, 0x18, 0x6f,
+        0x8a, 0xad, 0x27, 0x23, 0xf2, 0x0f, 0x0c, 0x33, 0x91, 0x09, 0xf5, 0x4b,
+        0xf1, 0x74, 0x27, 0xe8, 0xb4, 0xfb, 0x74, 0xcc, 0x3d, 0x30, 0x26, 0xb1,
+        0x5d, 0x22, 0x5a, 0x28, 0x9d, 0xc4, 0xba, 0x22, 0x45, 0x77, 0x00, 0xcf,
+        0x26, 0xc7, 0x7f, 0x2a, 0x7b, 0x24, 0xb1, 0x37, 0x2c, 0x25, 0xb7, 0x1b,
+        0x72, 0x34, 0xa0, 0x83, 0xe4, 0xf8, 0x5f, 0x40, 0x29, 0xba, 0x95, 0x8c,
+        0x1f, 0x93, 0x9c, 0x96, 0x6d, 0x76, 0x48, 0x29, 0x19, 0x95, 0x05, 0xd0,
+        0xb1, 0x90, 0xfa, 0xa2, 0x96, 0x39, 0x77, 0x50, 0xcb, 0x9e, 0xc3, 0xbc,
+        0x66, 0xdd, 0xb7, 0x35, 0x03, 0xeb, 0xe8, 0x52, 0x4c, 0x1e, 0xc4, 0xbd,
+        0xa8, 0xcc, 0x61, 0xde, 0x1c, 0x78, 0x2a, 0x35, 0xf7, 0xc8, 0xfa, 0x6c,
+        0xac, 0x37, 0x03, 0x1d, 0x16, 0x71, 0xff, 0xb7, 0x67, 0x34, 0x31, 0x2c,
+        0x5b, 0x7e, 0x3c, 0x06, 0x1d, 0x9e, 0x81, 0xfe, 0xce, 0xc4, 0xe5, 0x78,
+        0x45, 0x62, 0xba, 0x24, 0xe3, 0x79, 0x79, 0x41, 0xea, 0x2e, 0xf5, 0x0f,
+        0x7d, 0x42, 0xdf, 0x45, 0x97, 0xcf, 0x41, 0x6f, 0x15, 0x07, 0xf2, 0x98,
+        0x02, 0x0d, 0x0f, 0x6a, 0xf7, 0xd7, 0x67, 0xb5, 0x03, 0xcd, 0x1f, 0x6b,
+        0xd2, 0x7d, 0x4c, 0xfb, 0x5c, 0xf3, 0x88, 0xe6, 0xcb, 0x1e, 0xba, 0x8b,
+        0x8a, 0x3d, 0x13, 0x95, 0x95, 0xa6, 0xa7, 0xbb, 0x1a, 0xec, 0xd3, 0x36,
+        0x6c, 0xe8, 0xe1, 0x6f, 0x6f, 0xce, 0x59, 0x69, 0xc6, 0x64, 0x01, 0xb4,
+        0x1d, 0x6f, 0x72, 0xfe, 0xef, 0x41, 0x3f, 0x51, 0x71, 0x6f, 0xed, 0x91,
+        0x1c, 0xc6, 0x8b, 0x67, 0xc4, 0xce, 0xa4, 0x74, 0x3c, 0xd3, 0x2b, 0x21,
+        0xab, 0x1f, 0x9f, 0x6e, 0x99, 0xab, 0x77, 0xda, 0x21, 0x2b, 0x26, 0x73,
+        0x4d, 0xca, 0x10, 0xff, 0x2b, 0x81, 0x1c, 0x49, 0x2b, 0xc7, 0xf9, 0x1c,
+        0xc7, 0x0d, 0x8c, 0xb7, 0x8f, 0xd1, 0x2e, 0x7a, 0x41, 0x8f, 0x39, 0x2c,
+        0x18, 0xcb, 0x57, 0x92, 0xc6, 0xe7, 0xf8, 0xbf, 0x49, 0xd9, 0x06, 0x32,
+        0x0d, 0x63, 0xae, 0x2e, 0xf9, 0x3a, 0xf6, 0x39, 0x7d, 0xa5, 0x15, 0x19,
+        0xc3, 0xb5, 0xf5, 0x4b, 0xc8, 0x92, 0xfb, 0x86, 0x41, 0x93, 0x2e, 0xb9,
+        0x3a, 0xd7, 0xe2, 0x7d, 0x81, 0xee, 0x8b, 0x7b, 0x75, 0x19, 0x86, 0x7e,
+        0x4d, 0xec, 0xd3, 0x85, 0x39, 0x3d, 0x90, 0x1f, 0x78, 0x3d, 0x87, 0xef,
+        0xe0, 0x5d, 0xb7, 0x74, 0x3c, 0xdf, 0x29, 0x73, 0x29, 0xda, 0x0b, 0xe9,
+        0xdc, 0x85, 0xb5, 0xbb, 0x64, 0xfe, 0x34, 0xe5, 0x01, 0xbb, 0xaa, 0xc4,
+        0xa4, 0x74, 0xc6, 0x34, 0x1c, 0x31, 0x21, 0x1b, 0x1b, 0xf3, 0x3a, 0x25,
+        0x67, 0xb4, 0x5a, 0x13, 0xa9, 0x11, 0xe3, 0x9b, 0xca, 0xce, 0x47, 0x8c,
+        0xa4, 0x26, 0x85, 0x8e, 0xf4, 0x10, 0x64, 0x6b, 0x1e, 0x14, 0xe1, 0xf5,
+        0x0f, 0xc4, 0x9e, 0xa5, 0xff, 0xc4, 0xb8, 0x17, 0xfc, 0xa9, 0x1f, 0xf4,
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+        0xb0, 0xf3, 0x5e, 0xe4, 0x87, 0x9f, 0xc0, 0x66, 0x8c, 0x4c, 0xbd, 0x91,
+        0x43, 0xbd, 0xc3, 0xf9, 0x77, 0x40, 0x8f, 0x85, 0x4c, 0xad, 0x51, 0xc8,
+        0x9c, 0xe5, 0x79, 0x0e, 0xe6, 0xd5, 0x1a, 0x3d, 0x90, 0x7b, 0x8f, 0xea,
+        0x8b, 0xbc, 0x5c, 0x8e, 0x31, 0x06, 0xc1, 0xd6, 0x63, 0x18, 0x8b, 0xab,
+        0xdf, 0x68, 0xd5, 0xdd, 0x65, 0xf8, 0x74, 0x02, 0xe3, 0xd5, 0xae, 0x49,
+        0x85, 0x47, 0x2d, 0x59, 0x71, 0x7f, 0xa5, 0x15, 0xcb, 0x97, 0xb5, 0x52,
+        0x79, 0x18, 0x73, 0x46, 0xf9, 0x5b, 0x9f, 0x3d, 0xc0, 0x49, 0x53, 0xd5,
+        0x1d, 0x69, 0x4a, 0x80, 0x26, 0xbd, 0x8d, 0xa6, 0x04, 0xe8, 0x41, 0xcc,
+        0x3c, 0xc5, 0xde, 0xf1, 0xa8, 0x9c, 0x28, 0xf3, 0x9d, 0x26, 0xfe, 0x46,
+        0xd5, 0x90, 0x30, 0xb0, 0x65, 0xe4, 0x94, 0x19, 0x5f, 0x57, 0xbd, 0x1a,
+        0x73, 0xb8, 0x2e, 0x23, 0xa9, 0xba, 0xa8, 0xfc, 0x92, 0x38, 0x81, 0x7c,
+        0xf5, 0x86, 0xdb, 0x23, 0x6f, 0xfa, 0x7b, 0x5d, 0x14, 0x9e, 0x33, 0x6e,
+        0xdf, 0xeb, 0xc9, 0x4a, 0x2a, 0xf3, 0x8a, 0x15, 0xf2, 0xf9, 0xea, 0xc3,
+        0x5e, 0x7b, 0x30, 0x37, 0x95, 0x39, 0xdf, 0xd8, 0x69, 0xae, 0x83, 0xb9,
+        0x91, 0xb6, 0xb9, 0x0e, 0xe6, 0xf5, 0x20, 0xef, 0xf5, 0x28, 0x9e, 0x4a,
+        0xa0, 0xeb, 0x52, 0x99, 0x3c, 0xf1, 0x0c, 0x82, 0x7b, 0x1a, 0xc4, 0xc6,
+        0x53, 0xe2, 0x9f, 0xd9, 0xf2, 0xf7, 0x7a, 0x57, 0xf5, 0x6b, 0x94, 0x0d,
+        0x4c, 0x58, 0x3c, 0x9b, 0x99, 0xd1, 0xb2, 0xf5, 0x3c, 0x72, 0xd5, 0x8d,
+        0xc4, 0x43, 0x29, 0x1b, 0xb9, 0x92, 0xe7, 0x3c, 0x8d, 0x72, 0x81, 0xef,
+        0x3d, 0xc3, 0x2e, 0xde, 0x21, 0x5e, 0xbe, 0x31, 0xa4, 0xde, 0x43, 0x70,
+        0xfc, 0x73, 0x20, 0x31, 0x32, 0x63, 0x7c, 0xf7, 0xe0, 0x6e, 0xa9, 0x2f,
+        0x7f, 0x11, 0x63, 0x19, 0xe4, 0xc5, 0x43, 0x5a, 0xe6, 0xdc, 0x24, 0xae,
+        0x1f, 0xc2, 0x35, 0xe2, 0xf0, 0x72, 0x0e, 0xf7, 0x1f, 0xc2, 0xf5, 0xbc,
+        0x96, 0x6d, 0xe6, 0x70, 0xfd, 0x30, 0xae, 0x27, 0x48, 0x9b, 0xf3, 0x8a,
+        0x35, 0xa5, 0xd9, 0x58, 0xcb, 0x3e, 0x37, 0x89, 0x4f, 0xfb, 0x7a, 0xbc,
+        0x07, 0x3d, 0x95, 0x79, 0x3e, 0x96, 0x04, 0x4d, 0x0f, 0x6a, 0x4e, 0xbd,
+        0x1b, 0x6b, 0x0c, 0xe1, 0x79, 0xda, 0x54, 0xfb, 0x39, 0xd4, 0x6d, 0xaa,
+        0x67, 0x14, 0x4a, 0xa7, 0x81, 0x77, 0x1f, 0x41, 0xde, 0xd7, 0xc4, 0xb1,
+        0x1e, 0x97, 0x62, 0x2a, 0x2d, 0x0b, 0xf5, 0x90, 0x64, 0x63, 0x05, 0x7c,
+        0x2f, 0x48, 0x66, 0x1c, 0xf7, 0xeb, 0xb4, 0x05, 0xce, 0x2b, 0x49, 0xb1,
+        0x4a, 0xfc, 0xce, 0x7e, 0xd1, 0x57, 0xc0, 0x37, 0xfb, 0x44, 0x79, 0xc8,
+        0x20, 0x46, 0xfb, 0xdd, 0xa1, 0xa7, 0xe5, 0xbd, 0xd3, 0x8c, 0x7c, 0xac,
+        0x65, 0xea, 0xfe, 0x59, 0x9d, 0xc5, 0xdf, 0x2b, 0xb1, 0x47, 0x25, 0xc5,
+        0x50, 0x9a, 0x7d, 0x0e, 0xd5, 0x17, 0x4f, 0x79, 0x67, 0x7a, 0xed, 0xef,
+        0x90, 0x04, 0xfe, 0xc2, 0x7d, 0xbf, 0x82, 0xe7, 0xbd, 0xbe, 0x54, 0xb6,
+        0xf9, 0x41, 0x5d, 0xf0, 0x5d, 0xfd, 0x15, 0xe8, 0xe2, 0xfc, 0x87, 0xf6,
+        0xb9, 0xd8, 0xe3, 0x9a, 0x47, 0x2c, 0x62, 0x7f, 0x2c, 0x90, 0xdf, 0xd5,
+        0x34, 0x92, 0xbe, 0xc3, 0x58, 0x4b, 0x52, 0x8c, 0xb3, 0xb9, 0x58, 0x42,
+        0xd5, 0xbe, 0x1b, 0x4b, 0xf2, 0xc4, 0x16, 0xbd, 0xa4, 0x95, 0x72, 0x78,
+        0x04, 0xf5, 0x1a, 0x7f, 0xff, 0xf0, 0xb8, 0xe4, 0x53, 0xec, 0xd1, 0x84,
+        0x90, 0x0b, 0x0b, 0xf8, 0xbe, 0x25, 0xb7, 0x92, 0x2f, 0xb7, 0x7c, 0xf5,
+        0x5b, 0x4a, 0x77, 0x35, 0x8b, 0xfb, 0x05, 0xbd, 0x8b, 0x69, 0xa5, 0xb3,
+        0x9a, 0x7a, 0xcf, 0x36, 0xe0, 0x3d, 0xe8, 0xbf, 0xed, 0x6c, 0x73, 0x93,
+        0x16, 0x69, 0xfb, 0x38, 0xdf, 0x5b, 0x18, 0xb6, 0x85, 0xf4, 0x93, 0x0f,
+        0xe6, 0xac, 0xe0, 0x5c, 0x34, 0xe0, 0x21, 0xe0, 0xf3, 0xa3, 0xca, 0x85,
+        0x74, 0xee, 0x31, 0xa4, 0x7b, 0xca, 0x08, 0x59, 0xcc, 0x01, 0x9f, 0xf6,
+        0xfb, 0xf8, 0xff, 0x37, 0xe5, 0xea, 0xf1, 0x1e, 0x86, 0xa8, 0xfc, 0xdf,
+        0x8b, 0xee, 0xa0, 0xf7, 0xab, 0xcf, 0x80, 0x0d, 0xe7, 0xac, 0xb5, 0xc5,
+        0x67, 0x6d, 0x07, 0x3e, 0x6b, 0x3e, 0x9f, 0x1f, 0x7e, 0x4e, 0xea, 0xd1,
+        0x59, 0x5b, 0xb2, 0xc1, 0x23, 0x6d, 0x6a, 0x27, 0x7b, 0xe3, 0x6f, 0x9c,
+        0xd4, 0xef, 0xad, 0xa2, 0xb6, 0x7b, 0xad, 0x5e, 0x27, 0xeb, 0x64, 0xcf,
+        0xee, 0xce, 0x22, 0xd7, 0x55, 0xab, 0x5e, 0xcd, 0x5c, 0x75, 0xd9, 0x6b,
+        0xde, 0x69, 0x6f, 0x0d, 0x34, 0xff, 0x8e, 0x7a, 0xef, 0xa4, 0xe4, 0x7a,
+        0x7d, 0xa9, 0x6a, 0xb5, 0x3d, 0x57, 0xde, 0xc0, 0x3c, 0x39, 0x5c, 0x90,
+        0x19, 0xe8, 0x31, 0x89, 0xeb, 0x9b, 0xe5, 0xe5, 0x65, 0x75, 0x86, 0xe4,
+        0x9f, 0xd5, 0xf0, 0x0c, 0x46, 0x9d, 0x43, 0x23, 0x5e, 0xcd, 0xaa, 0x78,
+        0xbd, 0xb1, 0xac, 0xee, 0xa9, 0xdf, 0x3c, 0xd4, 0xdd, 0x19, 0xc4, 0x73,
+        0xd4, 0x06, 0xd6, 0x6e, 0x29, 0xa2, 0x86, 0x3e, 0x6b, 0xcd, 0x18, 0xc4,
+        0x29, 0x5c, 0x6b, 0x03, 0x6b, 0x9d, 0x5f, 0x96, 0xbd, 0x7c, 0xa7, 0xa3,
+        0xaa, 0xce, 0xbd, 0xbc, 0x7e, 0xf5, 0xbc, 0x04, 0xbf, 0xd7, 0x8d, 0xfa,
+        0x39, 0x8e, 0xef, 0x95, 0xf0, 0xb7, 0xa7, 0x8c, 0x01, 0xa8, 0x6b, 0x66,
+        0x0a, 0x58, 0xaf, 0xd5, 0xf2, 0xfa, 0xd9, 0x2d, 0xd8, 0x7d, 0x84, 0xbf,
+        0x65, 0xc0, 0xdf, 0x23, 0xb0, 0x13, 0xf8, 0xc1, 0xe6, 0x38, 0xaf, 0x59,
+        0x4b, 0x04, 0xd7, 0x4c, 0x58, 0xff, 0x1b, 0xed, 0xcc, 0xfa, 0xa1, 0x98,
+        0x41, 0x00, 0x00, 0x00 };
+static u32 bnx2_TXP_b09FwData[(0xd0/4) + 1] = {
+        0x00000000, 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000010,
+        0x00000030, 0x00000030, 0x00000000, 0x00000000, 0x00000000, 0x00000010,
+        0x00008000, 0x00000000, 0x00000000, 0x00000000, 0x00008002, 0x00000000,
+        0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000006,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000,
+        0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
+static u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = {
+        0x08003be8, 0x08003c14, 0x08003c5c, 0x08003c5c, 0x08003ae8, 0x08003b14,
+        0x08003b14, 0x08003c5c, 0x08003c5c, 0x08003c5c, 0x08003b7c, 0x00000000,
+        0x00000000 };
+static u32 bnx2_TXP_b09FwBss[(0xa20/4) + 1] = { 0x0 };
+static u32 bnx2_TXP_b09FwSbss[(0x80/4) + 1] = { 0x0 };
+
+static struct fw_info bnx2_txp_fw_09 = {
+        .ver_major                      = 0x1,
+        .ver_minor                      = 0x0,
+        .ver_fix                        = 0x0,
+
+        .start_addr                     = 0x08000060,
+
+        .text_addr                      = 0x08000000,
+        .text_len                       = 0x4194,
+        .text_index                     = 0x0,
+        .gz_text                        = bnx2_TXP_b09FwText,
+        .gz_text_len                    = sizeof(bnx2_TXP_b09FwText),
+
+        .data_addr                      = 0x080041e0,
+        .data_len                       = 0xd0,
+        .data_index                     = 0x0,
+        .data                           = bnx2_TXP_b09FwData,
+
+        .sbss_addr                      = 0x080042b0,
+        .sbss_len                       = 0x80,
+        .sbss_index                     = 0x0,
+        .sbss                           = bnx2_TXP_b09FwSbss,
+
+        .bss_addr                       = 0x08004330,
+        .bss_len                        = 0xa20,
+        .bss_index                      = 0x0,
+        .bss                            = bnx2_TXP_b09FwBss,
+
+        .rodata_addr                    = 0x08004198,
+        .rodata_len                     = 0x30,
+        .rodata_index                   = 0x0,
+        .rodata                         = bnx2_TXP_b09FwRodata,
+};
+
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 488d8ed9e740..6482aed4bb7c 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -3684,7 +3684,7 @@ static int bond_do_ioctl(struct net_device *bond_dev, struct ifreq *ifr, int cmd
                         mii->val_out = 0;
                         read_lock_bh(&bond->lock);
                         read_lock(&bond->curr_slave_lock);
-                        if (bond->curr_active_slave) {
+                        if (netif_carrier_ok(bond->dev)) {
                                 mii->val_out = BMSR_LSTATUS;
                         }
                         read_unlock(&bond->curr_slave_lock);
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index 521c5b71023c..c8126484c2be 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -2825,7 +2825,7 @@ static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
                 u64 csum_start_off, csum_stuff_off;
 
                 csum_start_off = (u64) (skb->h.raw - skb->data);
-                csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
+                csum_stuff_off = csum_start_off + skb->csum_offset;
 
                 ctrl =  TX_DESC_CSUM_EN |
                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
@@ -4066,9 +4066,9 @@ static int cas_alloc_rxds(struct cas *cp)
         return 0;
 }
 
-static void cas_reset_task(void *data)
+static void cas_reset_task(struct work_struct *work)
 {
-        struct cas *cp = (struct cas *) data;
+        struct cas *cp = container_of(work, struct cas, reset_task);
 #if 0
         int pending = atomic_read(&cp->reset_task_pending);
 #else
@@ -5006,7 +5006,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
         atomic_set(&cp->reset_task_pending_spare, 0);
         atomic_set(&cp->reset_task_pending_mtu, 0);
 #endif
-        INIT_WORK(&cp->reset_task, cas_reset_task, cp);
+        INIT_WORK(&cp->reset_task, cas_reset_task);
 
         /* Default link parameters */
         if (link_mode >= 0 && link_mode <= 6)
diff --git a/drivers/net/chelsio/common.h b/drivers/net/chelsio/common.h
index b265941e1372..74758d2c7af8 100644
--- a/drivers/net/chelsio/common.h
+++ b/drivers/net/chelsio/common.h
@@ -279,7 +279,7 @@ struct adapter {
         struct petp   *tp;
 
         struct port_info port[MAX_NPORTS];
-        struct work_struct stats_update_task;
+        struct delayed_work stats_update_task;
         struct timer_list stats_update_timer;
 
         spinlock_t tpi_lock;
diff --git a/drivers/net/chelsio/cphy.h b/drivers/net/chelsio/cphy.h
index 60901f25014e..cf9143499882 100644
--- a/drivers/net/chelsio/cphy.h
+++ b/drivers/net/chelsio/cphy.h
@@ -91,7 +91,7 @@ struct cphy {
         int state;      /* Link status state machine */
         adapter_t *adapter;                  /* associated adapter */
 
-        struct work_struct phy_update;
+        struct delayed_work phy_update;
 
         u16 bmsr;
         int count;
diff --git a/drivers/net/chelsio/cxgb2.c b/drivers/net/chelsio/cxgb2.c
index 53bec6739812..de48eadddbc4 100644
--- a/drivers/net/chelsio/cxgb2.c
+++ b/drivers/net/chelsio/cxgb2.c
@@ -953,10 +953,11 @@ static void t1_netpoll(struct net_device *dev)
  * Periodic accumulation of MAC statistics.  This is used only if the MAC
  * does not have any other way to prevent stats counter overflow.
  */
-static void mac_stats_task(void *data)
+static void mac_stats_task(struct work_struct *work)
 {
         int i;
-        struct adapter *adapter = data;
+        struct adapter *adapter =
+                container_of(work, struct adapter, stats_update_task.work);
 
         for_each_port(adapter, i) {
                 struct port_info *p = &adapter->port[i];
@@ -977,9 +978,10 @@ static void mac_stats_task(void *data)
 /*
  * Processes elmer0 external interrupts in process context.
  */
-static void ext_intr_task(void *data)
+static void ext_intr_task(struct work_struct *work)
 {
-        struct adapter *adapter = data;
+        struct adapter *adapter =
+                container_of(work, struct adapter, ext_intr_handler_task);
 
         t1_elmer0_ext_intr_handler(adapter);
 
@@ -1113,9 +1115,9 @@ static int __devinit init_one(struct pci_dev *pdev,
                         spin_lock_init(&adapter->mac_lock);
 
                         INIT_WORK(&adapter->ext_intr_handler_task,
-                                  ext_intr_task, adapter);
-                        INIT_WORK(&adapter->stats_update_task, mac_stats_task,
-                                  adapter);
+                                  ext_intr_task);
+                        INIT_DELAYED_WORK(&adapter->stats_update_task,
+                                          mac_stats_task);
 
                         pci_set_drvdata(pdev, netdev);
                 }
diff --git a/drivers/net/chelsio/my3126.c b/drivers/net/chelsio/my3126.c
index 0b90014d5b3e..c7731b6f9de3 100644
--- a/drivers/net/chelsio/my3126.c
+++ b/drivers/net/chelsio/my3126.c
@@ -93,9 +93,11 @@ static int my3126_interrupt_handler(struct cphy *cphy)
         return cphy_cause_link_change;
 }
 
-static void my3216_poll(void *arg)
+static void my3216_poll(struct work_struct *work)
 {
-        my3126_interrupt_handler(arg);
+        struct cphy *cphy = container_of(work, struct cphy, phy_update.work);
+
+        my3126_interrupt_handler(cphy);
 }
 
 static int my3126_set_loopback(struct cphy *cphy, int on)
@@ -171,7 +173,7 @@ static struct cphy *my3126_phy_create(adapter_t *adapter,
         if (cphy)
                 cphy_init(cphy, adapter, phy_addr, &my3126_ops, mdio_ops);
 
-        INIT_WORK(&cphy->phy_update, my3216_poll, cphy);
+        INIT_DELAYED_WORK(&cphy->phy_update, my3216_poll);
         cphy->bmsr = 0;
 
         return (cphy);
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index dec70c2b374a..4612f71a7106 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -1974,7 +1974,7 @@ out:
         return ret;
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         unregister_netdev(dev_cs89x0);
diff --git a/drivers/net/declance.c b/drivers/net/declance.c
index 00e2a8a134d7..4ae0fed7122e 100644
--- a/drivers/net/declance.c
+++ b/drivers/net/declance.c
@@ -40,6 +40,10 @@
  *
  *      v0.009: Module support fixes, multiple interfaces support, various
  *              bits. macro
+ *
+ *      v0.010: Fixes for the PMAD mapping of the LANCE buffer and for the
+ *              PMAX requirement to only use halfword accesses to the
+ *              buffer. macro
  */
 
 #include <linux/crc32.h>
@@ -54,6 +58,7 @@
 #include <linux/spinlock.h>
 #include <linux/stddef.h>
 #include <linux/string.h>
+#include <linux/types.h>
 
 #include <asm/addrspace.h>
 #include <asm/system.h>
@@ -67,7 +72,7 @@
 #include <asm/dec/tc.h>
 
 static char version[] __devinitdata =
-"declance.c: v0.009 by Linux MIPS DECstation task force\n";
+"declance.c: v0.010 by Linux MIPS DECstation task force\n";
 
 MODULE_AUTHOR("Linux MIPS DECstation task force");
 MODULE_DESCRIPTION("DEC LANCE (DECstation onboard, PMAD-xx) driver");
@@ -110,24 +115,25 @@ MODULE_LICENSE("GPL");
 #define LE_C3_BCON      0x1     /* Byte control */
 
 /* Receive message descriptor 1 */
-#define LE_R1_OWN       0x80    /* Who owns the entry */
-#define LE_R1_ERR       0x40    /* Error: if FRA, OFL, CRC or BUF is set */
-#define LE_R1_FRA       0x20    /* FRA: Frame error */
-#define LE_R1_OFL       0x10    /* OFL: Frame overflow */
-#define LE_R1_CRC       0x08    /* CRC error */
-#define LE_R1_BUF       0x04    /* BUF: Buffer error */
-#define LE_R1_SOP       0x02    /* Start of packet */
-#define LE_R1_EOP       0x01    /* End of packet */
-#define LE_R1_POK       0x03    /* Packet is complete: SOP + EOP */
-
-#define LE_T1_OWN       0x80    /* Lance owns the packet */
-#define LE_T1_ERR       0x40    /* Error summary */
-#define LE_T1_EMORE     0x10    /* Error: more than one retry needed */
-#define LE_T1_EONE      0x08    /* Error: one retry needed */
-#define LE_T1_EDEF      0x04    /* Error: deferred */
-#define LE_T1_SOP       0x02    /* Start of packet */
-#define LE_T1_EOP       0x01    /* End of packet */
-#define LE_T1_POK       0x03    /* Packet is complete: SOP + EOP */
+#define LE_R1_OWN       0x8000  /* Who owns the entry */
+#define LE_R1_ERR       0x4000  /* Error: if FRA, OFL, CRC or BUF is set */
+#define LE_R1_FRA       0x2000  /* FRA: Frame error */
+#define LE_R1_OFL       0x1000  /* OFL: Frame overflow */
+#define LE_R1_CRC       0x0800  /* CRC error */
+#define LE_R1_BUF       0x0400  /* BUF: Buffer error */
+#define LE_R1_SOP       0x0200  /* Start of packet */
+#define LE_R1_EOP       0x0100  /* End of packet */
+#define LE_R1_POK       0x0300  /* Packet is complete: SOP + EOP */
+
+/* Transmit message descriptor 1 */
+#define LE_T1_OWN       0x8000  /* Lance owns the packet */
+#define LE_T1_ERR       0x4000  /* Error summary */
+#define LE_T1_EMORE     0x1000  /* Error: more than one retry needed */
+#define LE_T1_EONE      0x0800  /* Error: one retry needed */
+#define LE_T1_EDEF      0x0400  /* Error: deferred */
+#define LE_T1_SOP       0x0200  /* Start of packet */
+#define LE_T1_EOP       0x0100  /* End of packet */
+#define LE_T1_POK       0x0300  /* Packet is complete: SOP + EOP */
 
 #define LE_T3_BUF       0x8000  /* Buffer error */
 #define LE_T3_UFL       0x4000  /* Error underflow */
@@ -156,69 +162,57 @@ MODULE_LICENSE("GPL");
 #undef TEST_HITS
 #define ZERO 0
 
-/* The DS2000/3000 have a linear 64 KB buffer.
-
- * The PMAD-AA has 128 kb buffer on-board.
+/*
+ * The DS2100/3100 have a linear 64 kB buffer which supports halfword
+ * accesses only.  Each halfword of the buffer is word-aligned in the
+ * CPU address space.
  *
- * The IOASIC LANCE devices use a shared memory region. This region as seen
- * from the CPU is (max) 128 KB long and has to be on an 128 KB boundary.
- * The LANCE sees this as a 64 KB long continuous memory region.
+ * The PMAD-AA has a 128 kB buffer on-board.
  *
- * The LANCE's DMA address is used as an index in this buffer and DMA takes
- * place in bursts of eight 16-Bit words which are packed into four 32-Bit words
- * by the IOASIC. This leads to a strange padding: 16 bytes of valid data followed
- * by a 16 byte gap :-(.
+ * The IOASIC LANCE devices use a shared memory region.  This region
+ * as seen from the CPU is (max) 128 kB long and has to be on an 128 kB
+ * boundary.  The LANCE sees this as a 64 kB long continuous memory
+ * region.
+ *
+ * The LANCE's DMA address is used as an index in this buffer and DMA
+ * takes place in bursts of eight 16-bit words which are packed into
+ * four 32-bit words by the IOASIC.  This leads to a strange padding:
+ * 16 bytes of valid data followed by a 16 byte gap :-(.
  */
 
 struct lance_rx_desc {
         unsigned short rmd0;            /* low address of packet */
-        short gap0;
-        unsigned char rmd1_hadr;        /* high address of packet */
-        unsigned char rmd1_bits;        /* descriptor bits */
-        short gap1;
+        unsigned short rmd1;            /* high address of packet
+                                           and descriptor bits */
         short length;                   /* 2s complement (negative!)
                                            of buffer length */
-        short gap2;
         unsigned short mblength;        /* actual number of bytes received */
-        short gap3;
 };
 
 struct lance_tx_desc {
         unsigned short tmd0;            /* low address of packet */
-        short gap0;
-        unsigned char tmd1_hadr;        /* high address of packet */
-        unsigned char tmd1_bits;        /* descriptor bits */
-        short gap1;
+        unsigned short tmd1;            /* high address of packet
+                                           and descriptor bits */
         short length;                   /* 2s complement (negative!)
                                            of buffer length */
-        short gap2;
         unsigned short misc;
-        short gap3;
 };
 
 
 /* First part of the LANCE initialization block, described in databook. */
 struct lance_init_block {
         unsigned short mode;            /* pre-set mode (reg. 15) */
-        short gap0;
 
-        unsigned char phys_addr[12];    /* physical ethernet address
-                                           only 0, 1, 4, 5, 8, 9 are valid
-                                           2, 3, 6, 7, 10, 11 are gaps */
-        unsigned short filter[8];       /* multicast filter
-                                           only 0, 2, 4, 6 are valid
-                                           1, 3, 5, 7 are gaps */
+        unsigned short phys_addr[3];    /* physical ethernet address */
+        unsigned short filter[4];       /* multicast filter */
 
         /* Receive and transmit ring base, along with extra bits. */
         unsigned short rx_ptr;          /* receive descriptor addr */
-        short gap1;
         unsigned short rx_len;          /* receive len and high addr */
-        short gap2;
         unsigned short tx_ptr;          /* transmit descriptor addr */
-        short gap3;
         unsigned short tx_len;          /* transmit len and high addr */
-        short gap4;
-        short gap5[8];
+
+        short gap[4];
 
         /* The buffer descriptors */
         struct lance_rx_desc brx_ring[RX_RING_SIZE];
@@ -226,15 +220,28 @@ struct lance_init_block {
 };
 
 #define BUF_OFFSET_CPU sizeof(struct lance_init_block)
-#define BUF_OFFSET_LNC (sizeof(struct lance_init_block)>>1)
+#define BUF_OFFSET_LNC sizeof(struct lance_init_block)
 
-#define libdesc_offset(rt, elem) \
-((__u32)(((unsigned long)(&(((struct lance_init_block *)0)->rt[elem])))))
+#define shift_off(off, type)                                            \
+        (type == ASIC_LANCE || type == PMAX_LANCE ? off << 1 : off)
 
-/*
- * This works *only* for the ring descriptors
- */
-#define LANCE_ADDR(x) (CPHYSADDR(x) >> 1)
+#define lib_off(rt, type)                                               \
+        shift_off(offsetof(struct lance_init_block, rt), type)
+
+#define lib_ptr(ib, rt, type)                                           \
+        ((volatile u16 *)((u8 *)(ib) + lib_off(rt, type)))
+
+#define rds_off(rt, type)                                               \
+        shift_off(offsetof(struct lance_rx_desc, rt), type)
+
+#define rds_ptr(rd, rt, type)                                           \
+        ((volatile u16 *)((u8 *)(rd) + rds_off(rt, type)))
+
+#define tds_off(rt, type)                                               \
+        shift_off(offsetof(struct lance_tx_desc, rt), type)
+
+#define tds_ptr(td, rt, type)                                           \
+        ((volatile u16 *)((u8 *)(td) + tds_off(rt, type)))
 
 struct lance_private {
         struct net_device *next;
@@ -242,7 +249,6 @@ struct lance_private {
         int slot;
         int dma_irq;
         volatile struct lance_regs *ll;
-        volatile struct lance_init_block *init_block;
 
         spinlock_t      lock;
 
@@ -260,8 +266,8 @@ struct lance_private {
         char *tx_buf_ptr_cpu[TX_RING_SIZE];
 
         /* Pointers to the ring buffers as seen from the LANCE */
-        char *rx_buf_ptr_lnc[RX_RING_SIZE];
-        char *tx_buf_ptr_lnc[TX_RING_SIZE];
+        uint rx_buf_ptr_lnc[RX_RING_SIZE];
+        uint tx_buf_ptr_lnc[TX_RING_SIZE];
 };
 
 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
@@ -294,7 +300,7 @@ static inline void writereg(volatile unsigned short *regptr, short value)
 static void load_csrs(struct lance_private *lp)
 {
         volatile struct lance_regs *ll = lp->ll;
-        int leptr;
+        uint leptr;
 
         /* The address space as seen from the LANCE
          * begins at address 0. HK
@@ -316,12 +322,14 @@ static void load_csrs(struct lance_private *lp)
  * Our specialized copy routines
  *
  */
-void cp_to_buf(const int type, void *to, const void *from, int len)
+static void cp_to_buf(const int type, void *to, const void *from, int len)
 {
         unsigned short *tp, *fp, clen;
         unsigned char *rtp, *rfp;
 
-        if (type == PMAX_LANCE) {
+        if (type == PMAD_LANCE) {
+                memcpy(to, from, len);
+        } else if (type == PMAX_LANCE) {
                 clen = len >> 1;
                 tp = (unsigned short *) to;
                 fp = (unsigned short *) from;
@@ -370,12 +378,14 @@ void cp_to_buf(const int type, void *to, const void *from, int len)
         iob();
 }
 
-void cp_from_buf(const int type, void *to, const void *from, int len)
+static void cp_from_buf(const int type, void *to, const void *from, int len)
 {
         unsigned short *tp, *fp, clen;
         unsigned char *rtp, *rfp;
 
-        if (type == PMAX_LANCE) {
+        if (type == PMAD_LANCE) {
+                memcpy(to, from, len);
+        } else if (type == PMAX_LANCE) {
                 clen = len >> 1;
                 tp = (unsigned short *) to;
                 fp = (unsigned short *) from;
@@ -431,12 +441,10 @@ void cp_from_buf(const int type, void *to, const void *from, int len)
 static void lance_init_ring(struct net_device *dev)
 {
         struct lance_private *lp = netdev_priv(dev);
-        volatile struct lance_init_block *ib;
-        int leptr;
+        volatile u16 *ib = (volatile u16 *)dev->mem_start;
+        uint leptr;
         int i;
 
-        ib = (struct lance_init_block *) (dev->mem_start);
-
         /* Lock out other processes while setting up hardware */
         netif_stop_queue(dev);
         lp->rx_new = lp->tx_new = 0;
@@ -445,55 +453,64 @@ static void lance_init_ring(struct net_device *dev)
         /* Copy the ethernet address to the lance init block.
          * XXX bit 0 of the physical address registers has to be zero
          */
-        ib->phys_addr[0] = dev->dev_addr[0];
-        ib->phys_addr[1] = dev->dev_addr[1];
-        ib->phys_addr[4] = dev->dev_addr[2];
-        ib->phys_addr[5] = dev->dev_addr[3];
-        ib->phys_addr[8] = dev->dev_addr[4];
-        ib->phys_addr[9] = dev->dev_addr[5];
+        *lib_ptr(ib, phys_addr[0], lp->type) = (dev->dev_addr[1] << 8) |
+                                     dev->dev_addr[0];
+        *lib_ptr(ib, phys_addr[1], lp->type) = (dev->dev_addr[3] << 8) |
+                                     dev->dev_addr[2];
+        *lib_ptr(ib, phys_addr[2], lp->type) = (dev->dev_addr[5] << 8) |
+                                     dev->dev_addr[4];
         /* Setup the initialization block */
 
         /* Setup rx descriptor pointer */
-        leptr = LANCE_ADDR(libdesc_offset(brx_ring, 0));
-        ib->rx_len = (LANCE_LOG_RX_BUFFERS << 13) | (leptr >> 16);
-        ib->rx_ptr = leptr;
+        leptr = offsetof(struct lance_init_block, brx_ring);
+        *lib_ptr(ib, rx_len, lp->type) = (LANCE_LOG_RX_BUFFERS << 13) |
+                                         (leptr >> 16);
+        *lib_ptr(ib, rx_ptr, lp->type) = leptr;
         if (ZERO)
-                printk("RX ptr: %8.8x(%8.8x)\n", leptr, libdesc_offset(brx_ring, 0));
+                printk("RX ptr: %8.8x(%8.8x)\n",
+                       leptr, lib_off(brx_ring, lp->type));
 
         /* Setup tx descriptor pointer */
-        leptr = LANCE_ADDR(libdesc_offset(btx_ring, 0));
-        ib->tx_len = (LANCE_LOG_TX_BUFFERS << 13) | (leptr >> 16);
-        ib->tx_ptr = leptr;
+        leptr = offsetof(struct lance_init_block, btx_ring);
+        *lib_ptr(ib, tx_len, lp->type) = (LANCE_LOG_TX_BUFFERS << 13) |
+                                         (leptr >> 16);
+        *lib_ptr(ib, tx_ptr, lp->type) = leptr;
         if (ZERO)
-                printk("TX ptr: %8.8x(%8.8x)\n", leptr, libdesc_offset(btx_ring, 0));
+                printk("TX ptr: %8.8x(%8.8x)\n",
+                       leptr, lib_off(btx_ring, lp->type));
 
         if (ZERO)
                 printk("TX rings:\n");
 
         /* Setup the Tx ring entries */
         for (i = 0; i < TX_RING_SIZE; i++) {
-                leptr = (int) lp->tx_buf_ptr_lnc[i];
-                ib->btx_ring[i].tmd0 = leptr;
-                ib->btx_ring[i].tmd1_hadr = leptr >> 16;
-                ib->btx_ring[i].tmd1_bits = 0;
-                ib->btx_ring[i].length = 0xf000;        /* The ones required by tmd2 */
-                ib->btx_ring[i].misc = 0;
+                leptr = lp->tx_buf_ptr_lnc[i];
+                *lib_ptr(ib, btx_ring[i].tmd0, lp->type) = leptr;
+                *lib_ptr(ib, btx_ring[i].tmd1, lp->type) = (leptr >> 16) &
+                                                           0xff;
+                *lib_ptr(ib, btx_ring[i].length, lp->type) = 0xf000;
+                                                /* The ones required by tmd2 */
+                *lib_ptr(ib, btx_ring[i].misc, lp->type) = 0;
                 if (i < 3 && ZERO)
-                        printk("%d: 0x%8.8x(0x%8.8x)\n", i, leptr, (int) lp->tx_buf_ptr_cpu[i]);
+                        printk("%d: 0x%8.8x(0x%8.8x)\n",
+                               i, leptr, (uint)lp->tx_buf_ptr_cpu[i]);
         }
 
         /* Setup the Rx ring entries */
         if (ZERO)
                 printk("RX rings:\n");
         for (i = 0; i < RX_RING_SIZE; i++) {
-                leptr = (int) lp->rx_buf_ptr_lnc[i];
-                ib->brx_ring[i].rmd0 = leptr;
-                ib->brx_ring[i].rmd1_hadr = leptr >> 16;
-                ib->brx_ring[i].rmd1_bits = LE_R1_OWN;
-                ib->brx_ring[i].length = -RX_BUFF_SIZE | 0xf000;
-                ib->brx_ring[i].mblength = 0;
+                leptr = lp->rx_buf_ptr_lnc[i];
+                *lib_ptr(ib, brx_ring[i].rmd0, lp->type) = leptr;
+                *lib_ptr(ib, brx_ring[i].rmd1, lp->type) = ((leptr >> 16) &
+                                                            0xff) |
+                                                           LE_R1_OWN;
+                *lib_ptr(ib, brx_ring[i].length, lp->type) = -RX_BUFF_SIZE |
+                                                             0xf000;
+                *lib_ptr(ib, brx_ring[i].mblength, lp->type) = 0;
                 if (i < 3 && ZERO)
-                        printk("%d: 0x%8.8x(0x%8.8x)\n", i, leptr, (int) lp->rx_buf_ptr_cpu[i]);
+                        printk("%d: 0x%8.8x(0x%8.8x)\n",
+                               i, leptr, (uint)lp->rx_buf_ptr_cpu[i]);
         }
         iob();
 }
@@ -511,11 +528,13 @@ static int init_restart_lance(struct lance_private *lp)
                 udelay(10);
         }
         if ((i == 100) || (ll->rdp & LE_C0_ERR)) {
-                printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, ll->rdp);
+                printk("LANCE unopened after %d ticks, csr0=%4.4x.\n",
+                       i, ll->rdp);
                 return -1;
         }
         if ((ll->rdp & LE_C0_ERR)) {
-                printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, ll->rdp);
+                printk("LANCE unopened after %d ticks, csr0=%4.4x.\n",
+                       i, ll->rdp);
                 return -1;
         }
         writereg(&ll->rdp, LE_C0_IDON);
@@ -528,12 +547,11 @@ static int init_restart_lance(struct lance_private *lp)
 static int lance_rx(struct net_device *dev)
 {
         struct lance_private *lp = netdev_priv(dev);
-        volatile struct lance_init_block *ib;
-        volatile struct lance_rx_desc *rd = 0;
-        unsigned char bits;
-        int len = 0;
-        struct sk_buff *skb = 0;
-        ib = (struct lance_init_block *) (dev->mem_start);
+        volatile u16 *ib = (volatile u16 *)dev->mem_start;
+        volatile u16 *rd;
+        unsigned short bits;
+        int entry, len;
+        struct sk_buff *skb;
 
 #ifdef TEST_HITS
         {
@@ -542,19 +560,22 @@ static int lance_rx(struct net_device *dev)
                 printk("[");
                 for (i = 0; i < RX_RING_SIZE; i++) {
                         if (i == lp->rx_new)
-                                printk("%s", ib->brx_ring[i].rmd1_bits &
+                                printk("%s", *lib_ptr(ib, brx_ring[i].rmd1,
+                                                      lp->type) &
                                              LE_R1_OWN ? "_" : "X");
                         else
-                                printk("%s", ib->brx_ring[i].rmd1_bits &
+                                printk("%s", *lib_ptr(ib, brx_ring[i].rmd1,
+                                                      lp->type) &
                                              LE_R1_OWN ? "." : "1");
                 }
                 printk("]");
         }
 #endif
 
-        for (rd = &ib->brx_ring[lp->rx_new];
-             !((bits = rd->rmd1_bits) & LE_R1_OWN);
-             rd = &ib->brx_ring[lp->rx_new]) {
+        for (rd = lib_ptr(ib, brx_ring[lp->rx_new], lp->type);
+             !((bits = *rds_ptr(rd, rmd1, lp->type)) & LE_R1_OWN);
+             rd = lib_ptr(ib, brx_ring[lp->rx_new], lp->type)) {
+                entry = lp->rx_new;
 
                 /* We got an incomplete frame? */
                 if ((bits & LE_R1_POK) != LE_R1_POK) {
@@ -575,16 +596,18 @@ static int lance_rx(struct net_device *dev)
                         if (bits & LE_R1_EOP)
                                 lp->stats.rx_errors++;
                 } else {
-                        len = (rd->mblength & 0xfff) - 4;
+                        len = (*rds_ptr(rd, mblength, lp->type) & 0xfff) - 4;
                         skb = dev_alloc_skb(len + 2);
 
                         if (skb == 0) {
                                 printk("%s: Memory squeeze, deferring packet.\n",
                                        dev->name);
                                 lp->stats.rx_dropped++;
-                                rd->mblength = 0;
-                                rd->rmd1_bits = LE_R1_OWN;
-                                lp->rx_new = (lp->rx_new + 1) & RX_RING_MOD_MASK;
+                                *rds_ptr(rd, mblength, lp->type) = 0;
+                                *rds_ptr(rd, rmd1, lp->type) =
+                                        ((lp->rx_buf_ptr_lnc[entry] >> 16) &
+                                         0xff) | LE_R1_OWN;
+                                lp->rx_new = (entry + 1) & RX_RING_MOD_MASK;
                                 return 0;
                         }
                         lp->stats.rx_bytes += len;
@@ -594,8 +617,7 @@ static int lance_rx(struct net_device *dev)
                         skb_put(skb, len);      /* make room */
 
                         cp_from_buf(lp->type, skb->data,
-                                    (char *)lp->rx_buf_ptr_cpu[lp->rx_new],
-                                    len);
+                                    (char *)lp->rx_buf_ptr_cpu[entry], len);
 
                         skb->protocol = eth_type_trans(skb, dev);
                         netif_rx(skb);
@@ -604,10 +626,11 @@ static int lance_rx(struct net_device *dev)
                 }
 
                 /* Return the packet to the pool */
-                rd->mblength = 0;
-                rd->length = -RX_BUFF_SIZE | 0xf000;
-                rd->rmd1_bits = LE_R1_OWN;
-                lp->rx_new = (lp->rx_new + 1) & RX_RING_MOD_MASK;
+                *rds_ptr(rd, mblength, lp->type) = 0;
+                *rds_ptr(rd, length, lp->type) = -RX_BUFF_SIZE | 0xf000;
+                *rds_ptr(rd, rmd1, lp->type) =
+                        ((lp->rx_buf_ptr_lnc[entry] >> 16) & 0xff) | LE_R1_OWN;
+                lp->rx_new = (entry + 1) & RX_RING_MOD_MASK;
         }
         return 0;
 }
@@ -615,24 +638,24 @@ static int lance_rx(struct net_device *dev)
 static void lance_tx(struct net_device *dev)
 {
         struct lance_private *lp = netdev_priv(dev);
-        volatile struct lance_init_block *ib;
+        volatile u16 *ib = (volatile u16 *)dev->mem_start;
         volatile struct lance_regs *ll = lp->ll;
-        volatile struct lance_tx_desc *td;
+        volatile u16 *td;
         int i, j;
         int status;
-        ib = (struct lance_init_block *) (dev->mem_start);
+
         j = lp->tx_old;
 
         spin_lock(&lp->lock);
 
         for (i = j; i != lp->tx_new; i = j) {
-                td = &ib->btx_ring[i];
+                td = lib_ptr(ib, btx_ring[i], lp->type);
                 /* If we hit a packet not owned by us, stop */
-                if (td->tmd1_bits & LE_T1_OWN)
+                if (*tds_ptr(td, tmd1, lp->type) & LE_T1_OWN)
                         break;
 
-                if (td->tmd1_bits & LE_T1_ERR) {
-                        status = td->misc;
+                if (*tds_ptr(td, tmd1, lp->type) & LE_T1_ERR) {
+                        status = *tds_ptr(td, misc, lp->type);
 
                         lp->stats.tx_errors++;
                         if (status & LE_T3_RTY)
@@ -667,18 +690,19 @@ static void lance_tx(struct net_device *dev)
                                 init_restart_lance(lp);
                                 goto out;
                         }
-                } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
+                } else if ((*tds_ptr(td, tmd1, lp->type) & LE_T1_POK) ==
+                           LE_T1_POK) {
                         /*
                          * So we don't count the packet more than once.
                          */
-                        td->tmd1_bits &= ~(LE_T1_POK);
+                        *tds_ptr(td, tmd1, lp->type) &= ~(LE_T1_POK);
 
                         /* One collision before packet was sent. */
-                        if (td->tmd1_bits & LE_T1_EONE)
+                        if (*tds_ptr(td, tmd1, lp->type) & LE_T1_EONE)
                                 lp->stats.collisions++;
 
                         /* More than one collision, be optimistic. */
-                        if (td->tmd1_bits & LE_T1_EMORE)
+                        if (*tds_ptr(td, tmd1, lp->type) & LE_T1_EMORE)
                                 lp->stats.collisions += 2;
 
                         lp->stats.tx_packets++;
@@ -752,7 +776,7 @@ struct net_device *last_dev = 0;
 
 static int lance_open(struct net_device *dev)
 {
-        volatile struct lance_init_block *ib = (struct lance_init_block *) (dev->mem_start);
+        volatile u16 *ib = (volatile u16 *)dev->mem_start;
         struct lance_private *lp = netdev_priv(dev);
         volatile struct lance_regs *ll = lp->ll;
         int status = 0;
@@ -769,11 +793,11 @@ static int lance_open(struct net_device *dev)
          *
          * BTW it is common bug in all lance drivers! --ANK
          */
-        ib->mode = 0;
-        ib->filter [0] = 0;
-        ib->filter [2] = 0;
-        ib->filter [4] = 0;
-        ib->filter [6] = 0;
+        *lib_ptr(ib, mode, lp->type) = 0;
+        *lib_ptr(ib, filter[0], lp->type) = 0;
+        *lib_ptr(ib, filter[1], lp->type) = 0;
+        *lib_ptr(ib, filter[2], lp->type) = 0;
+        *lib_ptr(ib, filter[3], lp->type) = 0;
 
         lance_init_ring(dev);
         load_csrs(lp);
@@ -874,12 +898,10 @@ static int lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
         struct lance_private *lp = netdev_priv(dev);
         volatile struct lance_regs *ll = lp->ll;
-        volatile struct lance_init_block *ib = (struct lance_init_block *) (dev->mem_start);
-        int entry, skblen, len;
+        volatile u16 *ib = (volatile u16 *)dev->mem_start;
+        int entry, len;
 
-        skblen = skb->len;
-
-        len = skblen;
+        len = skb->len;
 
         if (len < ETH_ZLEN) {
                 if (skb_padto(skb, ETH_ZLEN))
@@ -889,23 +911,17 @@ static int lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         lp->stats.tx_bytes += len;
 
-        entry = lp->tx_new & TX_RING_MOD_MASK;
-        ib->btx_ring[entry].length = (-len);
-        ib->btx_ring[entry].misc = 0;
-
-        cp_to_buf(lp->type, (char *)lp->tx_buf_ptr_cpu[entry], skb->data,
-                  skblen);
+        entry = lp->tx_new;
+        *lib_ptr(ib, btx_ring[entry].length, lp->type) = (-len);
+        *lib_ptr(ib, btx_ring[entry].misc, lp->type) = 0;
 
-        /* Clear the slack of the packet, do I need this? */
-        /* For a firewall it's a good idea - AC */
-/*
-   if (len != skblen)
-   memset ((char *) &ib->tx_buf [entry][skblen], 0, (len - skblen) << 1);
- */
+        cp_to_buf(lp->type, (char *)lp->tx_buf_ptr_cpu[entry], skb->data, len);
 
         /* Now, give the packet to the lance */
-        ib->btx_ring[entry].tmd1_bits = (LE_T1_POK | LE_T1_OWN);
-        lp->tx_new = (lp->tx_new + 1) & TX_RING_MOD_MASK;
+        *lib_ptr(ib, btx_ring[entry].tmd1, lp->type) =
+                ((lp->tx_buf_ptr_lnc[entry] >> 16) & 0xff) |
+                (LE_T1_POK | LE_T1_OWN);
+        lp->tx_new = (entry + 1) & TX_RING_MOD_MASK;
 
         if (TX_BUFFS_AVAIL <= 0)
                 netif_stop_queue(dev);
@@ -930,8 +946,8 @@ static struct net_device_stats *lance_get_stats(struct net_device *dev)
 
 static void lance_load_multicast(struct net_device *dev)
 {
-        volatile struct lance_init_block *ib = (struct lance_init_block *) (dev->mem_start);
-        volatile u16 *mcast_table = (u16 *) & ib->filter;
+        struct lance_private *lp = netdev_priv(dev);
+        volatile u16 *ib = (volatile u16 *)dev->mem_start;
         struct dev_mc_list *dmi = dev->mc_list;
         char *addrs;
         int i;
@@ -939,17 +955,17 @@ static void lance_load_multicast(struct net_device *dev)
 
         /* set all multicast bits */
         if (dev->flags & IFF_ALLMULTI) {
-                ib->filter[0] = 0xffff;
-                ib->filter[2] = 0xffff;
-                ib->filter[4] = 0xffff;
-                ib->filter[6] = 0xffff;
+                *lib_ptr(ib, filter[0], lp->type) = 0xffff;
+                *lib_ptr(ib, filter[1], lp->type) = 0xffff;
+                *lib_ptr(ib, filter[2], lp->type) = 0xffff;
+                *lib_ptr(ib, filter[3], lp->type) = 0xffff;
                 return;
         }
         /* clear the multicast filter */
-        ib->filter[0] = 0;
-        ib->filter[2] = 0;
-        ib->filter[4] = 0;
-        ib->filter[6] = 0;
+        *lib_ptr(ib, filter[0], lp->type) = 0;
+        *lib_ptr(ib, filter[1], lp->type) = 0;
+        *lib_ptr(ib, filter[2], lp->type) = 0;
+        *lib_ptr(ib, filter[3], lp->type) = 0;
 
         /* Add addresses */
         for (i = 0; i < dev->mc_count; i++) {
@@ -962,7 +978,7 @@ static void lance_load_multicast(struct net_device *dev)
 
                 crc = ether_crc_le(ETH_ALEN, addrs);
                 crc = crc >> 26;
-                mcast_table[2 * (crc >> 4)] |= 1 << (crc & 0xf);
+                *lib_ptr(ib, filter[crc >> 4], lp->type) |= 1 << (crc & 0xf);
         }
         return;
 }
@@ -970,11 +986,9 @@ static void lance_load_multicast(struct net_device *dev)
 static void lance_set_multicast(struct net_device *dev)
 {
         struct lance_private *lp = netdev_priv(dev);
-        volatile struct lance_init_block *ib;
+        volatile u16 *ib = (volatile u16 *)dev->mem_start;
         volatile struct lance_regs *ll = lp->ll;
 
-        ib = (struct lance_init_block *) (dev->mem_start);
-
         if (!netif_running(dev))
                 return;
 
@@ -992,9 +1006,9 @@ static void lance_set_multicast(struct net_device *dev)
         lance_init_ring(dev);
 
         if (dev->flags & IFF_PROMISC) {
-                ib->mode |= LE_MO_PROM;
+                *lib_ptr(ib, mode, lp->type) |= LE_MO_PROM;
         } else {
-                ib->mode &= ~LE_MO_PROM;
+                *lib_ptr(ib, mode, lp->type) &= ~LE_MO_PROM;
                 lance_load_multicast(dev);
         }
         load_csrs(lp);
@@ -1051,7 +1065,6 @@ static int __init dec_lance_init(const int type, const int slot)
         lp->type = type;
         lp->slot = slot;
         switch (type) {
-#ifdef CONFIG_TC
         case ASIC_LANCE:
                 dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE);
 
@@ -1073,20 +1086,20 @@ static int __init dec_lance_init(const int type, const int slot)
                  */
                 for (i = 0; i < RX_RING_SIZE; i++) {
                         lp->rx_buf_ptr_cpu[i] =
-                                (char *)(dev->mem_start + BUF_OFFSET_CPU +
+                                (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
                                          2 * i * RX_BUFF_SIZE);
                         lp->rx_buf_ptr_lnc[i] =
-                                (char *)(BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
+                                (BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
                 }
                 for (i = 0; i < TX_RING_SIZE; i++) {
                         lp->tx_buf_ptr_cpu[i] =
-                                (char *)(dev->mem_start + BUF_OFFSET_CPU +
+                                (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
                                          2 * RX_RING_SIZE * RX_BUFF_SIZE +
                                          2 * i * TX_BUFF_SIZE);
                         lp->tx_buf_ptr_lnc[i] =
-                                (char *)(BUF_OFFSET_LNC +
-                                         RX_RING_SIZE * RX_BUFF_SIZE +
-                                         i * TX_BUFF_SIZE);
+                                (BUF_OFFSET_LNC +
+                                 RX_RING_SIZE * RX_BUFF_SIZE +
+                                 i * TX_BUFF_SIZE);
                 }
 
                 /* Setup I/O ASIC LANCE DMA.  */
@@ -1095,11 +1108,12 @@ static int __init dec_lance_init(const int type, const int slot)
                              CPHYSADDR(dev->mem_start) << 3);
 
                 break;
-
+#ifdef CONFIG_TC
         case PMAD_LANCE:
                 claim_tc_card(slot);
 
                 dev->mem_start = CKSEG1ADDR(get_tc_base_addr(slot));
+                dev->mem_end = dev->mem_start + 0x100000;
                 dev->base_addr = dev->mem_start + 0x100000;
                 dev->irq = get_tc_irq_nr(slot);
                 esar_base = dev->mem_start + 0x1c0002;
@@ -1110,7 +1124,7 @@ static int __init dec_lance_init(const int type, const int slot)
                                 (char *)(dev->mem_start + BUF_OFFSET_CPU +
                                          i * RX_BUFF_SIZE);
                         lp->rx_buf_ptr_lnc[i] =
-                                (char *)(BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
+                                (BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
                 }
                 for (i = 0; i < TX_RING_SIZE; i++) {
                         lp->tx_buf_ptr_cpu[i] =
@@ -1118,18 +1132,18 @@ static int __init dec_lance_init(const int type, const int slot)
                                          RX_RING_SIZE * RX_BUFF_SIZE +
                                          i * TX_BUFF_SIZE);
                         lp->tx_buf_ptr_lnc[i] =
-                                (char *)(BUF_OFFSET_LNC +
-                                         RX_RING_SIZE * RX_BUFF_SIZE +
-                                         i * TX_BUFF_SIZE);
+                                (BUF_OFFSET_LNC +
+                                 RX_RING_SIZE * RX_BUFF_SIZE +
+                                 i * TX_BUFF_SIZE);
                 }
 
                 break;
 #endif
-
         case PMAX_LANCE:
                 dev->irq = dec_interrupt[DEC_IRQ_LANCE];
                 dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE);
                 dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM);
+                dev->mem_end = dev->mem_start + KN01_SLOT_SIZE;
                 esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1);
                 lp->dma_irq = -1;
 
@@ -1138,20 +1152,20 @@ static int __init dec_lance_init(const int type, const int slot)
                  */
                 for (i = 0; i < RX_RING_SIZE; i++) {
                         lp->rx_buf_ptr_cpu[i] =
-                                (char *)(dev->mem_start + BUF_OFFSET_CPU +
+                                (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
                                          2 * i * RX_BUFF_SIZE);
                         lp->rx_buf_ptr_lnc[i] =
-                                (char *)(BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
+                                (BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
                 }
                 for (i = 0; i < TX_RING_SIZE; i++) {
                         lp->tx_buf_ptr_cpu[i] =
-                                (char *)(dev->mem_start + BUF_OFFSET_CPU +
+                                (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
                                          2 * RX_RING_SIZE * RX_BUFF_SIZE +
                                          2 * i * TX_BUFF_SIZE);
                         lp->tx_buf_ptr_lnc[i] =
-                                (char *)(BUF_OFFSET_LNC +
-                                         RX_RING_SIZE * RX_BUFF_SIZE +
-                                         i * TX_BUFF_SIZE);
+                                (BUF_OFFSET_LNC +
+                                 RX_RING_SIZE * RX_BUFF_SIZE +
+                                 i * TX_BUFF_SIZE);
                 }
 
                 break;
@@ -1279,10 +1293,8 @@ static int __init dec_lance_probe(void)
         /* Then handle onboard devices. */
         if (dec_interrupt[DEC_IRQ_LANCE] >= 0) {
                 if (dec_interrupt[DEC_IRQ_LANCE_MERR] >= 0) {
-#ifdef CONFIG_TC
                         if (dec_lance_init(ASIC_LANCE, -1) >= 0)
                                 count++;
-#endif
                 } else if (!TURBOCHANNEL) {
                         if (dec_lance_init(PMAX_LANCE, -1) >= 0)
                                 count++;
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index 3a8df479cbda..03bf164f9e8d 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -2102,9 +2102,10 @@ static void e100_tx_timeout(struct net_device *netdev)
         schedule_work(&nic->tx_timeout_task);
 }
 
-static void e100_tx_timeout_task(struct net_device *netdev)
+static void e100_tx_timeout_task(struct work_struct *work)
 {
-        struct nic *nic = netdev_priv(netdev);
+        struct nic *nic = container_of(work, struct nic, tx_timeout_task);
+        struct net_device *netdev = nic->netdev;
 
         DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
                 readb(&nic->csr->scb.status));
@@ -2637,8 +2638,7 @@ static int __devinit e100_probe(struct pci_dev *pdev,
         nic->blink_timer.function = e100_blink_led;
         nic->blink_timer.data = (unsigned long)nic;
 
-        INIT_WORK(&nic->tx_timeout_task,
-                (void (*)(void *))e100_tx_timeout_task, netdev);
+        INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
 
         if((err = e100_alloc(nic))) {
                 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 7a0828869ecf..73f3a85fd238 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -190,7 +190,7 @@ void e1000_set_ethtool_ops(struct net_device *netdev);
 static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
 static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
 static void e1000_tx_timeout(struct net_device *dev);
-static void e1000_reset_task(struct net_device *dev);
+static void e1000_reset_task(struct work_struct *work);
 static void e1000_smartspeed(struct e1000_adapter *adapter);
 static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
                                        struct sk_buff *skb);
@@ -914,8 +914,7 @@ e1000_probe(struct pci_dev *pdev,
         adapter->phy_info_timer.function = &e1000_update_phy_info;
         adapter->phy_info_timer.data = (unsigned long) adapter;
 
-        INIT_WORK(&adapter->reset_task,
-                (void (*)(void *))e1000_reset_task, netdev);
+        INIT_WORK(&adapter->reset_task, e1000_reset_task);
 
         e1000_check_options(adapter);
 
@@ -2826,7 +2825,7 @@ e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
                 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
 
                 context_desc->upper_setup.tcp_fields.tucss = css;
-                context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
+                context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
                 context_desc->upper_setup.tcp_fields.tucse = 0;
                 context_desc->tcp_seg_setup.data = 0;
                 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
@@ -3306,9 +3305,10 @@ e1000_tx_timeout(struct net_device *netdev)
 }
 
 static void
-e1000_reset_task(struct net_device *netdev)
+e1000_reset_task(struct work_struct *work)
 {
-        struct e1000_adapter *adapter = netdev_priv(netdev);
+        struct e1000_adapter *adapter =
+                container_of(work, struct e1000_adapter, reset_task);
 
         e1000_reinit_locked(adapter);
 }
diff --git a/drivers/net/e2100.c b/drivers/net/e2100.c
index d39e8480ca56..c62d9c6363c6 100644
--- a/drivers/net/e2100.c
+++ b/drivers/net/e2100.c
@@ -463,7 +463,7 @@ static void cleanup_card(struct net_device *dev)
         release_region(dev->base_addr, E21_IO_EXTENT);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/eepro.c b/drivers/net/eepro.c
index a4eb0dc99ecf..b4463094c93a 100644
--- a/drivers/net/eepro.c
+++ b/drivers/net/eepro.c
@@ -1827,7 +1827,7 @@ int __init init_module(void)
         return n_eepro ? 0 : -ENODEV;
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int i;
diff --git a/drivers/net/eexpress.c b/drivers/net/eexpress.c
index e14be020e562..4a50fcb5ad6b 100644
--- a/drivers/net/eexpress.c
+++ b/drivers/net/eexpress.c
@@ -1719,7 +1719,7 @@ int __init init_module(void)
         return -ENXIO;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index 6ad696101418..83fa32f72398 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -2224,11 +2224,12 @@ static int ehea_stop(struct net_device *dev)
         return ret;
 }
 
-static void ehea_reset_port(void *data)
+static void ehea_reset_port(struct work_struct *work)
 {
         int ret;
-        struct net_device *dev = data;
-        struct ehea_port *port = netdev_priv(dev);
+        struct ehea_port *port =
+                container_of(work, struct ehea_port, reset_task);
+        struct net_device *dev = port->netdev;
 
         port->resets++;
         down(&port->port_lock);
@@ -2379,7 +2380,7 @@ static int ehea_setup_single_port(struct ehea_port *port,
         dev->tx_timeout = &ehea_tx_watchdog;
         dev->watchdog_timeo = EHEA_WATCH_DOG_TIMEOUT;
 
-        INIT_WORK(&port->reset_task, ehea_reset_port, dev);
+        INIT_WORK(&port->reset_task, ehea_reset_port);
 
         ehea_set_ethtool_ops(dev);
 
diff --git a/drivers/net/ehea/ehea_qmr.c b/drivers/net/ehea/ehea_qmr.c
index 72ef7bde3346..f143e13b229d 100644
--- a/drivers/net/ehea/ehea_qmr.c
+++ b/drivers/net/ehea/ehea_qmr.c
@@ -26,6 +26,7 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/mm.h>
 #include "ehea.h"
 #include "ehea_phyp.h"
 #include "ehea_qmr.h"
diff --git a/drivers/net/es3210.c b/drivers/net/es3210.c
index fd7b32a24ea4..2d2ea94a00bb 100644
--- a/drivers/net/es3210.c
+++ b/drivers/net/es3210.c
@@ -455,7 +455,7 @@ static void cleanup_card(struct net_device *dev)
         iounmap(ei_status.mem);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/eth16i.c b/drivers/net/eth16i.c
index b7b8bc2a6307..93283e386f3a 100644
--- a/drivers/net/eth16i.c
+++ b/drivers/net/eth16i.c
@@ -1475,7 +1475,7 @@ int __init init_module(void)
         return -ENXIO;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/hamradio/baycom_epp.c b/drivers/net/hamradio/baycom_epp.c
index 1ed9cccd3c11..3c33d6f6a6a6 100644
--- a/drivers/net/hamradio/baycom_epp.c
+++ b/drivers/net/hamradio/baycom_epp.c
@@ -168,8 +168,9 @@ struct baycom_state {
         int magic;
 
         struct pardevice *pdev;
+        struct net_device *dev;
         unsigned int work_running;
-        struct work_struct run_work;
+        struct delayed_work run_work;
         unsigned int modem;
         unsigned int bitrate;
         unsigned char stat;
@@ -659,16 +660,18 @@ static int receive(struct net_device *dev, int cnt)
 #define GETTICK(x)
 #endif /* __i386__ */
 
-static void epp_bh(struct net_device *dev)
+static void epp_bh(struct work_struct *work)
 {
+        struct net_device *dev;
         struct baycom_state *bc;
         struct parport *pp;
         unsigned char stat;
         unsigned char tmp[2];
         unsigned int time1 = 0, time2 = 0, time3 = 0;
         int cnt, cnt2;
-        
-        bc = netdev_priv(dev);
+
+        bc = container_of(work, struct baycom_state, run_work.work);
+        dev = bc->dev;
         if (!bc->work_running)
                 return;
         baycom_int_freq(bc);
@@ -889,7 +892,7 @@ static int epp_open(struct net_device *dev)
                 return -EBUSY;
         }
         dev->irq = /*pp->irq*/ 0;
-        INIT_WORK(&bc->run_work, (void *)(void *)epp_bh, dev);
+        INIT_DELAYED_WORK(&bc->run_work, epp_bh);
         bc->work_running = 1;
         bc->modem = EPP_CONVENTIONAL;
         if (eppconfig(bc))
@@ -1213,6 +1216,7 @@ static void __init baycom_epp_dev_setup(struct net_device *dev)
         /*
          * initialize part of the baycom_state struct
          */
+        bc->dev = dev;
         bc->magic = BAYCOM_MAGIC;
         bc->cfg.fclk = 19666600;
         bc->cfg.bps = 9600;
diff --git a/drivers/net/hamradio/dmascc.c b/drivers/net/hamradio/dmascc.c
index 0f8b9afd55b4..e6e721aff6f6 100644
--- a/drivers/net/hamradio/dmascc.c
+++ b/drivers/net/hamradio/dmascc.c
@@ -252,7 +252,7 @@ static inline void z8530_isr(struct scc_info *info);
 static irqreturn_t scc_isr(int irq, void *dev_id);
 static void rx_isr(struct scc_priv *priv);
 static void special_condition(struct scc_priv *priv, int rc);
-static void rx_bh(void *arg);
+static void rx_bh(struct work_struct *);
 static void tx_isr(struct scc_priv *priv);
 static void es_isr(struct scc_priv *priv);
 static void tm_isr(struct scc_priv *priv);
@@ -579,7 +579,7 @@ static int __init setup_adapter(int card_base, int type, int n)
                 priv->param.clocks = TCTRxCP | RCRTxCP;
                 priv->param.persist = 256;
                 priv->param.dma = -1;
-                INIT_WORK(&priv->rx_work, rx_bh, priv);
+                INIT_WORK(&priv->rx_work, rx_bh);
                 dev->priv = priv;
                 sprintf(dev->name, "dmascc%i", 2 * n + i);
                 dev->base_addr = card_base;
@@ -1272,9 +1272,9 @@ static void special_condition(struct scc_priv *priv, int rc)
 }
 
 
-static void rx_bh(void *arg)
+static void rx_bh(struct work_struct *ugli_api)
 {
-        struct scc_priv *priv = arg;
+        struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work);
         int i = priv->rx_tail;
         int cb;
         unsigned long flags;
diff --git a/drivers/net/hp-plus.c b/drivers/net/hp-plus.c
index 6abcfd2a4b28..99a36cc3f8df 100644
--- a/drivers/net/hp-plus.c
+++ b/drivers/net/hp-plus.c
@@ -482,7 +482,7 @@ static void cleanup_card(struct net_device *dev)
         release_region(dev->base_addr - NIC_OFFSET, HP_IO_EXTENT);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/hp.c b/drivers/net/hp.c
index 29470970aa27..635b13c2e2aa 100644
--- a/drivers/net/hp.c
+++ b/drivers/net/hp.c
@@ -444,7 +444,7 @@ static void cleanup_card(struct net_device *dev)
         release_region(dev->base_addr - NIC_OFFSET, HP_IO_EXTENT);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h
index f73f10a0a562..407d2acbf7c7 100644
--- a/drivers/net/ibm_emac/ibm_emac_mal.h
+++ b/drivers/net/ibm_emac/ibm_emac_mal.h
@@ -24,6 +24,7 @@
 #include <linux/netdevice.h>
 
 #include <asm/io.h>
+#include <asm/dcr.h>
 
 /*
  * These MAL "versions" probably aren't the real versions IBM uses for these 
@@ -191,6 +192,7 @@ struct mal_commac {
 
 struct ibm_ocp_mal {
         int                     dcrbase;
+        dcr_host_t              dcrhost;
 
         struct list_head        poll_list;
         struct net_device       poll_dev;
@@ -207,12 +209,12 @@ struct ibm_ocp_mal {
 
 static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg)
 {
-        return mfdcr(mal->dcrbase + reg);
+        return dcr_read(mal->dcrhost, mal->dcrbase + reg);
 }
 
 static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val)
 {
-        mtdcr(mal->dcrbase + reg, val);
+        dcr_write(mal->dcrhost, mal->dcrbase + reg, val);
 }
 
 /* Register MAL devices */
diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c
index 44c9f993dcc4..99343b5836b8 100644
--- a/drivers/net/ibmveth.c
+++ b/drivers/net/ibmveth.c
@@ -50,7 +50,6 @@
 #include <asm/semaphore.h>
 #include <asm/hvcall.h>
 #include <asm/atomic.h>
-#include <asm/iommu.h>
 #include <asm/vio.h>
 #include <asm/uaccess.h>
 #include <linux/seq_file.h>
@@ -1000,8 +999,6 @@ static int __devinit ibmveth_probe(struct vio_dev *dev, const struct vio_device_
         adapter->mac_addr = 0;
         memcpy(&adapter->mac_addr, mac_addr_p, 6);
 
-        adapter->liobn = dev->iommu_table->it_index;
-
         netdev->irq = dev->irq;
         netdev->open               = ibmveth_open;
         netdev->poll               = ibmveth_poll;
@@ -1115,7 +1112,6 @@ static int ibmveth_seq_show(struct seq_file *seq, void *v)
         seq_printf(seq, "%s %s\n\n", ibmveth_driver_string, ibmveth_driver_version);
 
         seq_printf(seq, "Unit Address:    0x%x\n", adapter->vdev->unit_address);
-        seq_printf(seq, "LIOBN:           0x%lx\n", adapter->liobn);
         seq_printf(seq, "Current MAC:     %02X:%02X:%02X:%02X:%02X:%02X\n",
                    current_mac[0], current_mac[1], current_mac[2],
                    current_mac[3], current_mac[4], current_mac[5]);
diff --git a/drivers/net/ibmveth.h b/drivers/net/ibmveth.h
index f5b25bff1540..bb69ccae8ace 100644
--- a/drivers/net/ibmveth.h
+++ b/drivers/net/ibmveth.h
@@ -118,7 +118,6 @@ struct ibmveth_adapter {
     struct net_device_stats stats;
     unsigned int mcastFilterSize;
     unsigned long mac_addr;
-    unsigned long liobn;
     void * buffer_list_addr;
     void * filter_list_addr;
     dma_addr_t buffer_list_dma;
diff --git a/drivers/net/ioc3-eth.c b/drivers/net/ioc3-eth.c
index f56b00ee385e..f0d30cf67b5f 100644
--- a/drivers/net/ioc3-eth.c
+++ b/drivers/net/ioc3-eth.c
@@ -57,7 +57,6 @@
 #include <net/ip.h>
 
 #include <asm/byteorder.h>
-#include <asm/checksum.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/uaccess.h>
diff --git a/drivers/net/irda/mcs7780.c b/drivers/net/irda/mcs7780.c
index b32c52ed19d7..f0c61f3b2a82 100644
--- a/drivers/net/irda/mcs7780.c
+++ b/drivers/net/irda/mcs7780.c
@@ -560,9 +560,9 @@ static inline int mcs_find_endpoints(struct mcs_cb *mcs,
         return ret;
 }
 
-static void mcs_speed_work(void *arg)
+static void mcs_speed_work(struct work_struct *work)
 {
-        struct mcs_cb *mcs = arg;
+        struct mcs_cb *mcs = container_of(work, struct mcs_cb, work);
         struct net_device *netdev = mcs->netdev;
 
         mcs_speed_change(mcs);
@@ -927,7 +927,7 @@ static int mcs_probe(struct usb_interface *intf,
         irda_qos_bits_to_value(&mcs->qos);
 
         /* Speed change work initialisation*/
-        INIT_WORK(&mcs->work, mcs_speed_work, mcs);
+        INIT_WORK(&mcs->work, mcs_speed_work);
 
         /* Override the network functions we need to use */
         ndev->hard_start_xmit = mcs_hard_xmit;
diff --git a/drivers/net/irda/sir-dev.h b/drivers/net/irda/sir-dev.h
index 9fa294a546d6..2a57bc67ce35 100644
--- a/drivers/net/irda/sir-dev.h
+++ b/drivers/net/irda/sir-dev.h
@@ -22,7 +22,7 @@
 
 struct sir_fsm {
         struct semaphore        sem;
-        struct work_struct      work;
+        struct delayed_work     work;
         unsigned                state, substate;
         int                     param;
         int                     result;
diff --git a/drivers/net/irda/sir_dev.c b/drivers/net/irda/sir_dev.c
index 3b5854d10c17..17b0c3ab6201 100644
--- a/drivers/net/irda/sir_dev.c
+++ b/drivers/net/irda/sir_dev.c
@@ -100,9 +100,9 @@ static int sirdev_tx_complete_fsm(struct sir_dev *dev)
  * Both must be unlocked/restarted on completion - but only on final exit.
  */
 
-static void sirdev_config_fsm(void *data)
+static void sirdev_config_fsm(struct work_struct *work)
 {
-        struct sir_dev *dev = data;
+        struct sir_dev *dev = container_of(work, struct sir_dev, fsm.work.work);
         struct sir_fsm *fsm = &dev->fsm;
         int next_state;
         int ret = -1;
@@ -309,8 +309,8 @@ int sirdev_schedule_request(struct sir_dev *dev, int initial_state, unsigned par
         fsm->param = param;
         fsm->result = 0;
 
-        INIT_WORK(&fsm->work, sirdev_config_fsm, dev);
-        queue_work(irda_sir_wq, &fsm->work);
+        INIT_DELAYED_WORK(&fsm->work, sirdev_config_fsm);
+        queue_delayed_work(irda_sir_wq, &fsm->work, 0);
         return 0;
 }
 
diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c
index 2284e2ce1692..d6f4f185bf37 100644
--- a/drivers/net/iseries_veth.c
+++ b/drivers/net/iseries_veth.c
@@ -166,7 +166,7 @@ struct veth_msg {
 
 struct veth_lpar_connection {
         HvLpIndex remote_lp;
-        struct work_struct statemachine_wq;
+        struct delayed_work statemachine_wq;
         struct veth_msg *msgs;
         int num_events;
         struct veth_cap_data local_caps;
@@ -456,7 +456,7 @@ static struct kobj_type veth_port_ktype = {
 
 static inline void veth_kick_statemachine(struct veth_lpar_connection *cnx)
 {
-        schedule_work(&cnx->statemachine_wq);
+        schedule_delayed_work(&cnx->statemachine_wq, 0);
 }
 
 static void veth_take_cap(struct veth_lpar_connection *cnx,
@@ -638,9 +638,11 @@ static int veth_process_caps(struct veth_lpar_connection *cnx)
 }
 
 /* FIXME: The gotos here are a bit dubious */
-static void veth_statemachine(void *p)
+static void veth_statemachine(struct work_struct *work)
 {
-        struct veth_lpar_connection *cnx = (struct veth_lpar_connection *)p;
+        struct veth_lpar_connection *cnx =
+                container_of(work, struct veth_lpar_connection,
+                             statemachine_wq.work);
         int rlp = cnx->remote_lp;
         int rc;
 
@@ -827,7 +829,7 @@ static int veth_init_connection(u8 rlp)
 
         cnx->remote_lp = rlp;
         spin_lock_init(&cnx->lock);
-        INIT_WORK(&cnx->statemachine_wq, veth_statemachine, cnx);
+        INIT_DELAYED_WORK(&cnx->statemachine_wq, veth_statemachine);
 
         init_timer(&cnx->ack_timer);
         cnx->ack_timer.function = veth_timed_ack;
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index e09f575a3a38..e628126c9c49 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -106,7 +106,7 @@ static boolean_t ixgb_clean_rx_irq(struct ixgb_adapter *adapter);
 static void ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter);
 void ixgb_set_ethtool_ops(struct net_device *netdev);
 static void ixgb_tx_timeout(struct net_device *dev);
-static void ixgb_tx_timeout_task(struct net_device *dev);
+static void ixgb_tx_timeout_task(struct work_struct *work);
 static void ixgb_vlan_rx_register(struct net_device *netdev,
                                   struct vlan_group *grp);
 static void ixgb_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
@@ -489,8 +489,7 @@ ixgb_probe(struct pci_dev *pdev,
         adapter->watchdog_timer.function = &ixgb_watchdog;
         adapter->watchdog_timer.data = (unsigned long)adapter;
 
-        INIT_WORK(&adapter->tx_timeout_task,
-                  (void (*)(void *))ixgb_tx_timeout_task, netdev);
+        INIT_WORK(&adapter->tx_timeout_task, ixgb_tx_timeout_task);
 
         strcpy(netdev->name, "eth%d");
         if((err = register_netdev(netdev)))
@@ -1249,7 +1248,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
         if(likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
                 struct ixgb_buffer *buffer_info;
                 css = skb->h.raw - skb->data;
-                cso = (skb->h.raw + skb->csum) - skb->data;
+                cso = css + skb->csum_offset;
 
                 i = adapter->tx_ring.next_to_use;
                 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
@@ -1493,9 +1492,10 @@ ixgb_tx_timeout(struct net_device *netdev)
 }
 
 static void
-ixgb_tx_timeout_task(struct net_device *netdev)
+ixgb_tx_timeout_task(struct work_struct *work)
 {
-        struct ixgb_adapter *adapter = netdev_priv(netdev);
+        struct ixgb_adapter *adapter =
+                container_of(work, struct ixgb_adapter, tx_timeout_task);
 
         adapter->tx_timeout_count++;
         ixgb_down(adapter, TRUE);
diff --git a/drivers/net/lance.c b/drivers/net/lance.c
index 6efbd499d752..a3843320dbe1 100644
--- a/drivers/net/lance.c
+++ b/drivers/net/lance.c
@@ -57,6 +57,7 @@ static const char version[] = "lance.c:v1.16 2006/11/09 dplatt@3do.com, becker@c
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
+#include <linux/mm.h>
 #include <linux/bitops.h>
 
 #include <asm/io.h>
@@ -367,7 +368,7 @@ static void cleanup_card(struct net_device *dev)
         kfree(lp);
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/lne390.c b/drivers/net/lne390.c
index 5795ee116205..0a08d0c4e7b4 100644
--- a/drivers/net/lne390.c
+++ b/drivers/net/lne390.c
@@ -440,7 +440,7 @@ static void cleanup_card(struct net_device *dev)
         iounmap(ei_status.mem);
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/meth.c b/drivers/net/meth.c
index c1aa60b9a982..e1d97cdf649e 100644
--- a/drivers/net/meth.c
+++ b/drivers/net/meth.c
@@ -33,7 +33,6 @@
 #include <asm/ip32/ip32_ints.h>
 
 #include <asm/io.h>
-#include <asm/checksum.h>
 #include <asm/scatterlist.h>
 #include <linux/dma-mapping.h>
 
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 9997081c6dae..c41ae4286eea 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -277,9 +277,11 @@ static void mv643xx_eth_tx_timeout(struct net_device *dev)
  *
  * Actual routine to reset the adapter when a timeout on Tx has occurred
  */
-static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
+static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
 {
-        struct mv643xx_private *mp = netdev_priv(dev);
+        struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
+                                                  tx_timeout_task);
+        struct net_device *dev = mp->mii.dev; /* yuck */
 
         if (!netif_running(dev))
                 return;
@@ -1098,7 +1100,7 @@ static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
                                          ETH_TX_ENABLE_INTERRUPT;
                         mp->tx_skb[tx_index] = skb;
                 } else
-                        mp->tx_skb[tx_index] = 0;
+                        mp->tx_skb[tx_index] = NULL;
 
                 desc = &mp->p_tx_desc_area[tx_index];
                 desc->l4i_chk = 0;
@@ -1134,7 +1136,7 @@ static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
                 eth_tx_fill_frag_descs(mp, skb);
 
                 length = skb_headlen(skb);
-                mp->tx_skb[tx_index] = 0;
+                mp->tx_skb[tx_index] = NULL;
         } else {
                 cmd_sts |= ETH_ZERO_PADDING |
                            ETH_TX_LAST_DESC |
@@ -1360,8 +1362,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 #endif
 
         /* Configure the timeout task */
-        INIT_WORK(&mp->tx_timeout_task,
-                        (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
+        INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
 
         spin_lock_init(&mp->lock);
 
diff --git a/drivers/net/mvme147.c b/drivers/net/mvme147.c
index 56a82d8ee8f5..e246d00bba6d 100644
--- a/drivers/net/mvme147.c
+++ b/drivers/net/mvme147.c
@@ -184,7 +184,7 @@ static int m147lance_close(struct net_device *dev)
 MODULE_LICENSE("GPL");
 
 static struct net_device *dev_mvme147_lance;
-int init_module(void)
+int __init init_module(void)
 {
         dev_mvme147_lance = mvme147lance_probe(-1);
         if (IS_ERR(dev_mvme147_lance))
@@ -192,7 +192,7 @@ int init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         struct m147lance_private *lp = dev_mvme147_lance->priv;
         unregister_netdev(dev_mvme147_lance);
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 806081b59733..81f127a78afa 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -89,7 +89,7 @@ MODULE_LICENSE("Dual BSD/GPL");
 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
 
-#define MYRI10GE_NO_CONFIRM_DATA 0xffffffff
+#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 
 struct myri10ge_rx_buffer_state {
@@ -156,8 +156,8 @@ struct myri10ge_priv {
         int sram_size;
         unsigned long board_span;
         unsigned long iomem_base;
-        u32 __iomem *irq_claim;
-        u32 __iomem *irq_deassert;
+        __be32 __iomem *irq_claim;
+        __be32 __iomem *irq_deassert;
         char *mac_addr_string;
         struct mcp_cmd_response *cmd;
         dma_addr_t cmd_bus;
@@ -165,10 +165,10 @@ struct myri10ge_priv {
         dma_addr_t fw_stats_bus;
         struct pci_dev *pdev;
         int msi_enabled;
-        unsigned int link_state;
+        __be32 link_state;
         unsigned int rdma_tags_available;
         int intr_coal_delay;
-        u32 __iomem *intr_coal_delay_ptr;
+        __be32 __iomem *intr_coal_delay_ptr;
         int mtrr;
         int wake_queue;
         int stop_queue;
@@ -273,6 +273,11 @@ MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 
 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 
+static inline void put_be32(__be32 val, __be32 __iomem *p)
+{
+        __raw_writel((__force __u32)val, (__force void __iomem *)p);
+}
+
 static int
 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
                   struct myri10ge_cmd *data, int atomic)
@@ -296,7 +301,7 @@ myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 
         buf->response_addr.low = htonl(dma_low);
         buf->response_addr.high = htonl(dma_high);
-        response->result = MYRI10GE_NO_RESPONSE_RESULT;
+        response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
         mb();
         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 
@@ -311,14 +316,14 @@ myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
                  * (1ms will be enough for those commands) */
                 for (sleep_total = 0;
                      sleep_total < 1000
-                     && response->result == MYRI10GE_NO_RESPONSE_RESULT;
+                     && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
                      sleep_total += 10)
                         udelay(10);
         } else {
                 /* use msleep for most command */
                 for (sleep_total = 0;
                      sleep_total < 15
-                     && response->result == MYRI10GE_NO_RESPONSE_RESULT;
+                     && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
                      sleep_total++)
                         msleep(1);
         }
@@ -393,7 +398,7 @@ abort:
 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 {
         char __iomem *submit;
-        u32 buf[16];
+        __be32 buf[16];
         u32 dma_low, dma_high;
         int i;
 
@@ -410,7 +415,7 @@ static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 
         buf[0] = htonl(dma_high);       /* confirm addr MSW */
         buf[1] = htonl(dma_low);        /* confirm addr LSW */
-        buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA);       /* confirm data */
+        buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
         buf[3] = htonl(dma_high);       /* dummy addr MSW */
         buf[4] = htonl(dma_low);        /* dummy addr LSW */
         buf[5] = htonl(enable); /* enable? */
@@ -479,7 +484,7 @@ static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
         }
 
         /* check id */
-        hdr_offset = ntohl(*(u32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
+        hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
                 dev_err(dev, "Bad firmware file\n");
                 status = -EINVAL;
@@ -550,7 +555,7 @@ static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
 {
         char __iomem *submit;
-        u32 buf[16];
+        __be32 buf[16];
         u32 dma_low, dma_high, size;
         int status, i;
 
@@ -600,7 +605,7 @@ static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
 
         buf[0] = htonl(dma_high);       /* confirm addr MSW */
         buf[1] = htonl(dma_low);        /* confirm addr LSW */
-        buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA);       /* confirm data */
+        buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 
         /* FIX: All newest firmware should un-protect the bottom of
          * the sram before handoff. However, the very first interfaces
@@ -705,21 +710,21 @@ static int myri10ge_reset(struct myri10ge_priv *mgp)
 
         status |=
             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
-        mgp->irq_claim = (__iomem u32 *) (mgp->sram + cmd.data0);
+        mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
         if (!mgp->msi_enabled) {
                 status |= myri10ge_send_cmd
                     (mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd, 0);
-                mgp->irq_deassert = (__iomem u32 *) (mgp->sram + cmd.data0);
+                mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
 
         }
         status |= myri10ge_send_cmd
             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
-        mgp->intr_coal_delay_ptr = (__iomem u32 *) (mgp->sram + cmd.data0);
+        mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
         if (status != 0) {
                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
                 return status;
         }
-        __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
+        put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
 
         /* Run a small DMA test.
          * The magic multipliers to the length tell the firmware
@@ -786,14 +791,16 @@ static inline void
 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
                     struct mcp_kreq_ether_recv *src)
 {
-        u32 low;
+        __be32 low;
 
         low = src->addr_low;
-        src->addr_low = DMA_32BIT_MASK;
-        myri10ge_pio_copy(dst, src, 8 * sizeof(*src));
+        src->addr_low = htonl(DMA_32BIT_MASK);
+        myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
+        mb();
+        myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
         mb();
         src->addr_low = low;
-        __raw_writel(low, &dst->addr_low);
+        put_be32(low, &dst->addr_low);
         mb();
 }
 
@@ -939,11 +946,11 @@ done:
         return retval;
 }
 
-static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, u16 hw_csum)
+static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
 {
         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
 
-        if ((skb->protocol == ntohs(ETH_P_8021Q)) &&
+        if ((skb->protocol == htons(ETH_P_8021Q)) &&
             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
                 skb->csum = hw_csum;
@@ -953,7 +960,7 @@ static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, u16 hw_csum)
 
 static inline unsigned long
 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
-                 int bytes, int len, int csum)
+                 int bytes, int len, __wsum csum)
 {
         dma_addr_t bus;
         struct sk_buff *skb;
@@ -986,12 +993,12 @@ myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
 
         skb->protocol = eth_type_trans(skb, mgp->dev);
         if (mgp->csum_flag) {
-                if ((skb->protocol == ntohs(ETH_P_IP)) ||
-                    (skb->protocol == ntohs(ETH_P_IPV6))) {
-                        skb->csum = ntohs((u16) csum);
+                if ((skb->protocol == htons(ETH_P_IP)) ||
+                    (skb->protocol == htons(ETH_P_IPV6))) {
+                        skb->csum = csum;
                         skb->ip_summed = CHECKSUM_COMPLETE;
                 } else
-                        myri10ge_vlan_ip_csum(skb, ntohs((u16) csum));
+                        myri10ge_vlan_ip_csum(skb, csum);
         }
 
         netif_receive_skb(skb);
@@ -1060,12 +1067,12 @@ static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
         int idx = rx_done->idx;
         int cnt = rx_done->cnt;
         u16 length;
-        u16 checksum;
+        __wsum checksum;
 
         while (rx_done->entry[idx].length != 0 && *limit != 0) {
                 length = ntohs(rx_done->entry[idx].length);
                 rx_done->entry[idx].length = 0;
-                checksum = ntohs(rx_done->entry[idx].checksum);
+                checksum = csum_unfold(rx_done->entry[idx].checksum);
                 if (length <= mgp->small_bytes)
                         rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
                                                  mgp->small_bytes,
@@ -1142,7 +1149,7 @@ static int myri10ge_poll(struct net_device *netdev, int *budget)
 
         if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
                 netif_rx_complete(netdev);
-                __raw_writel(htonl(3), mgp->irq_claim);
+                put_be32(htonl(3), mgp->irq_claim);
                 return 0;
         }
         return 1;
@@ -1166,7 +1173,7 @@ static irqreturn_t myri10ge_intr(int irq, void *arg)
                 netif_rx_schedule(mgp->dev);
 
         if (!mgp->msi_enabled) {
-                __raw_writel(0, mgp->irq_deassert);
+                put_be32(0, mgp->irq_deassert);
                 if (!myri10ge_deassert_wait)
                         stats->valid = 0;
                 mb();
@@ -1195,7 +1202,7 @@ static irqreturn_t myri10ge_intr(int irq, void *arg)
 
         myri10ge_check_statblock(mgp);
 
-        __raw_writel(htonl(3), mgp->irq_claim + 1);
+        put_be32(htonl(3), mgp->irq_claim + 1);
         return (IRQ_HANDLED);
 }
 
@@ -1233,7 +1240,7 @@ myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
         struct myri10ge_priv *mgp = netdev_priv(netdev);
 
         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
-        __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
+        put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
         return 0;
 }
 
@@ -1748,7 +1755,7 @@ static int myri10ge_open(struct net_device *dev)
                 goto abort_with_rings;
         }
 
-        mgp->link_state = -1;
+        mgp->link_state = htonl(~0U);
         mgp->rdma_tags_available = 15;
 
         netif_poll_enable(mgp->dev);    /* must happen prior to any irq */
@@ -1876,7 +1883,7 @@ myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
 
         /* re-write the last 32-bits with the valid flags */
         src->flags = last_flags;
-        __raw_writel(*((u32 *) src + 3), (u32 __iomem *) dst + 3);
+        put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
         tx->req += cnt;
         mb();
 }
@@ -1919,7 +1926,8 @@ static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
         struct myri10ge_tx_buf *tx = &mgp->tx;
         struct skb_frag_struct *frag;
         dma_addr_t bus;
-        u32 low, high_swapped;
+        u32 low;
+        __be32 high_swapped;
         unsigned int len;
         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
         u16 pseudo_hdr_offset, cksum_offset;
@@ -1955,7 +1963,7 @@ again:
         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
                 cksum_offset = (skb->h.raw - skb->data);
-                pseudo_hdr_offset = (skb->h.raw + skb->csum) - skb->data;
+                pseudo_hdr_offset = cksum_offset + skb->csum_offset;
                 /* If the headers are excessively large, then we must
                  * fall back to a software checksum */
                 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
@@ -1964,7 +1972,6 @@ again:
                         cksum_offset = 0;
                         pseudo_hdr_offset = 0;
                 } else {
-                        pseudo_hdr_offset = htons(pseudo_hdr_offset);
                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
                         flags |= MXGEFW_FLAGS_CKSUM;
                 }
@@ -1986,7 +1993,7 @@ again:
                 /* for TSO, pseudo_hdr_offset holds mss.
                  * The firmware figures out where to put
                  * the checksum by parsing the header. */
-                pseudo_hdr_offset = htons(mss);
+                pseudo_hdr_offset = mss;
         } else
 #endif                          /*NETIF_F_TSO */
                 /* Mark small packets, and pad out tiny packets */
@@ -2086,7 +2093,7 @@ again:
 #endif                          /* NETIF_F_TSO */
                         req->addr_high = high_swapped;
                         req->addr_low = htonl(low);
-                        req->pseudo_hdr_offset = pseudo_hdr_offset;
+                        req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
                         req->rdma_count = 1;
                         req->length = htons(seglen);
@@ -2199,6 +2206,7 @@ static void myri10ge_set_multicast_list(struct net_device *dev)
         struct myri10ge_cmd cmd;
         struct myri10ge_priv *mgp;
         struct dev_mc_list *mc_list;
+        __be32 data[2] = {0, 0};
         int err;
 
         mgp = netdev_priv(dev);
@@ -2237,10 +2245,9 @@ static void myri10ge_set_multicast_list(struct net_device *dev)
 
         /* Walk the multicast list, and add each address */
         for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
-                memcpy(&cmd.data0, &mc_list->dmi_addr, 4);
-                memcpy(&cmd.data1, ((char *)&mc_list->dmi_addr) + 4, 2);
-                cmd.data0 = htonl(cmd.data0);
-                cmd.data1 = htonl(cmd.data1);
+                memcpy(data, &mc_list->dmi_addr, 6);
+                cmd.data0 = ntohl(data[0]);
+                cmd.data1 = ntohl(data[1]);
                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
                                         &cmd, 1);
 
@@ -2615,9 +2622,10 @@ static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
  * This watchdog is used to check whether the board has suffered
  * from a parity error and needs to be recovered.
  */
-static void myri10ge_watchdog(void *arg)
+static void myri10ge_watchdog(struct work_struct *work)
 {
-        struct myri10ge_priv *mgp = arg;
+        struct myri10ge_priv *mgp =
+                container_of(work, struct myri10ge_priv, watchdog_work);
         u32 reboot;
         int status;
         u16 cmd, vendor;
@@ -2887,7 +2895,7 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                     (unsigned long)mgp);
 
         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
-        INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog, mgp);
+        INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
         status = register_netdev(netdev);
         if (status != 0) {
                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h
index 9519ae7cd5ec..29463b301a84 100644
--- a/drivers/net/myri10ge/myri10ge_mcp.h
+++ b/drivers/net/myri10ge/myri10ge_mcp.h
@@ -6,23 +6,23 @@
 
 /* 8 Bytes */
 struct mcp_dma_addr {
-        u32 high;
-        u32 low;
+        __be32 high;
+        __be32 low;
 };
 
 /* 4 Bytes */
 struct mcp_slot {
-        u16 checksum;
-        u16 length;
+        __sum16 checksum;
+        __be16 length;
 };
 
 /* 64 Bytes */
 struct mcp_cmd {
-        u32 cmd;
-        u32 data0;              /* will be low portion if data > 32 bits */
+        __be32 cmd;
+        __be32 data0;           /* will be low portion if data > 32 bits */
         /* 8 */
-        u32 data1;              /* will be high portion if data > 32 bits */
-        u32 data2;              /* currently unused.. */
+        __be32 data1;           /* will be high portion if data > 32 bits */
+        __be32 data2;           /* currently unused.. */
         /* 16 */
         struct mcp_dma_addr response_addr;
         /* 24 */
@@ -31,8 +31,8 @@ struct mcp_cmd {
 
 /* 8 Bytes */
 struct mcp_cmd_response {
-        u32 data;
-        u32 result;
+        __be32 data;
+        __be32 result;
 };
 
 /*
@@ -73,10 +73,10 @@ union mcp_pso_or_cumlen {
 
 /* 16 Bytes */
 struct mcp_kreq_ether_send {
-        u32 addr_high;
-        u32 addr_low;
-        u16 pseudo_hdr_offset;
-        u16 length;
+        __be32 addr_high;
+        __be32 addr_low;
+        __be16 pseudo_hdr_offset;
+        __be16 length;
         u8 pad;
         u8 rdma_count;
         u8 cksum_offset;        /* where to start computing cksum */
@@ -85,8 +85,8 @@ struct mcp_kreq_ether_send {
 
 /* 8 Bytes */
 struct mcp_kreq_ether_recv {
-        u32 addr_high;
-        u32 addr_low;
+        __be32 addr_high;
+        __be32 addr_low;
 };
 
 /* Commands */
@@ -219,19 +219,19 @@ enum myri10ge_mcp_cmd_status {
 
 struct mcp_irq_data {
         /* add new counters at the beginning */
-        u32 future_use[5];
-        u32 dropped_multicast_filtered;
+        __be32 future_use[5];
+        __be32 dropped_multicast_filtered;
         /* 40 Bytes */
-        u32 send_done_count;
-
-        u32 link_up;
-        u32 dropped_link_overflow;
-        u32 dropped_link_error_or_filtered;
-        u32 dropped_runt;
-        u32 dropped_overrun;
-        u32 dropped_no_small_buffer;
-        u32 dropped_no_big_buffer;
-        u32 rdma_tags_available;
+        __be32 send_done_count;
+
+        __be32 link_up;
+        __be32 dropped_link_overflow;
+        __be32 dropped_link_error_or_filtered;
+        __be32 dropped_runt;
+        __be32 dropped_overrun;
+        __be32 dropped_no_small_buffer;
+        __be32 dropped_no_big_buffer;
+        __be32 rdma_tags_available;
 
         u8 tx_stopped;
         u8 link_down;
diff --git a/drivers/net/myri10ge/myri10ge_mcp_gen_header.h b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h
index 487f7792fd46..16a810dd6d51 100644
--- a/drivers/net/myri10ge/myri10ge_mcp_gen_header.h
+++ b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h
@@ -36,7 +36,7 @@
 struct mcp_gen_header {
         /* the first 4 fields are filled at compile time */
         unsigned header_length;
-        unsigned mcp_type;
+        __be32 mcp_type;
         char version[128];
         unsigned mcp_globals;   /* pointer to mcp-type specific structure */
 
diff --git a/drivers/net/myri_sbus.c b/drivers/net/myri_sbus.c
index 7747bfd99f91..ee26ef52289f 100644
--- a/drivers/net/myri_sbus.c
+++ b/drivers/net/myri_sbus.c
@@ -39,7 +39,6 @@ static char version[] =
 #include <asm/auxio.h>
 #include <asm/pgtable.h>
 #include <asm/irq.h>
-#include <asm/checksum.h>
 
 #include "myri_sbus.h"
 #include "myri_code.h"
diff --git a/drivers/net/ne.c b/drivers/net/ne.c
index 787aa4221528..a5c4199e2754 100644
--- a/drivers/net/ne.c
+++ b/drivers/net/ne.c
@@ -867,7 +867,7 @@ static void cleanup_card(struct net_device *dev)
         release_region(dev->base_addr, NE_IO_EXTENT);
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/ne2.c b/drivers/net/ne2.c
index 5fccfea66d87..089b5bb702fc 100644
--- a/drivers/net/ne2.c
+++ b/drivers/net/ne2.c
@@ -813,7 +813,7 @@ static void cleanup_card(struct net_device *dev)
         release_region(dev->base_addr, NE_IO_EXTENT);
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/ne3210.c b/drivers/net/ne3210.c
index d66328975425..1a6fed76d4cc 100644
--- a/drivers/net/ne3210.c
+++ b/drivers/net/ne3210.c
@@ -36,6 +36,7 @@
 #include <linux/interrupt.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
+#include <linux/mm.h>
 
 #include <asm/io.h>
 #include <asm/system.h>
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index bf58db29e2ed..69233f6aa05c 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -60,7 +60,6 @@ static struct netpoll np = {
         .local_port = 6665,
         .remote_port = 6666,
         .remote_mac = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-        .drop = netpoll_queue,
 };
 static int configured = 0;
 
@@ -102,6 +101,8 @@ __setup("netconsole=", option_setup);
 
 static int init_netconsole(void)
 {
+        int err;
+
         if(strlen(config))
                 option_setup(config);
 
@@ -110,8 +111,9 @@ static int init_netconsole(void)
                 return 0;
         }
 
-        if(netpoll_setup(&np))
-                return -EINVAL;
+        err = netpoll_setup(&np);
+        if (err)
+                return err;
 
         register_console(&netconsole);
         printk(KERN_INFO "netconsole: network logging started\n");
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index d925053fe597..b5410bee5f21 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -1,25 +1,25 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
- *                            
+ *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *                                   
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -63,40 +63,68 @@
 
 #include "netxen_nic_hw.h"
 
-#define NETXEN_NIC_BUILD_NO     "5"
-#define _NETXEN_NIC_LINUX_MAJOR 2
+#define NETXEN_NIC_BUILD_NO     "1"
+#define _NETXEN_NIC_LINUX_MAJOR 3
 #define _NETXEN_NIC_LINUX_MINOR 3
-#define _NETXEN_NIC_LINUX_SUBVERSION 59
-#define NETXEN_NIC_LINUX_VERSIONID  "2.3.59" "-" NETXEN_NIC_BUILD_NO
-#define NETXEN_NIC_FW_VERSIONID "2.3.59"
+#define _NETXEN_NIC_LINUX_SUBVERSION 2
+#define NETXEN_NIC_LINUX_VERSIONID  "3.3.2" "-" NETXEN_NIC_BUILD_NO
+#define NETXEN_NIC_FW_VERSIONID "3.3.2"
 
 #define RCV_DESC_RINGSIZE       \
         (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
 #define STATUS_DESC_RINGSIZE    \
         (sizeof(struct status_desc)* adapter->max_rx_desc_count)
+#define LRO_DESC_RINGSIZE       \
+        (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
 #define TX_RINGSIZE     \
         (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
 #define RCV_BUFFSIZE    \
         (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
 
-#define NETXEN_NETDEV_STATUS 0x1
+#define NETXEN_NETDEV_STATUS            0x1
+#define NETXEN_RCV_PRODUCER_OFFSET      0
+#define NETXEN_RCV_PEG_DB_ID            2
+#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
 
 #define ADDR_IN_WINDOW1(off)    \
         ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
+/*
+ * In netxen_nic_down(), we must wait for any pending callback requests into
+ * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be
+ * reenabled right after it is deleted in netxen_nic_down(). FLUSH_SCHEDULED_WORK()
+ * does this synchronization.
+ *
+ * Normally, schedule_work()/flush_scheduled_work() could have worked, but
+ * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off()
+ * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a
+ * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause
+ * linkwatch_event() to be executed which also attempts to acquire the rtnl
+ * lock thus causing a deadlock.
+ */
+
+#define SCHEDULE_WORK(tp)       queue_work(netxen_workq, tp)
+#define FLUSH_SCHEDULED_WORK()  flush_workqueue(netxen_workq)
+extern struct workqueue_struct *netxen_workq;
 
 /* 
  * normalize a 64MB crb address to 32MB PCI window 
  * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
  */
-#define NETXEN_CRB_NORMAL(reg)        \
-        (reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST
+#define NETXEN_CRB_NORMAL(reg)  \
+        ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
 
 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
         pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
 
+#define DB_NORMALIZE(adapter, off) \
+        (adapter->ahw.db_base + (off))
+
+#define NX_P2_C0                0x24
+#define NX_P2_C1                0x25
+
 #define FIRST_PAGE_GROUP_START  0
-#define FIRST_PAGE_GROUP_END    0x400000
+#define FIRST_PAGE_GROUP_END    0x100000
 
 #define SECOND_PAGE_GROUP_START 0x4000000
 #define SECOND_PAGE_GROUP_END   0x66BC000
@@ -108,11 +136,13 @@
 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
 #define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
 
-#define MAX_RX_BUFFER_LENGTH            2000
+#define MAX_RX_BUFFER_LENGTH            1760
 #define MAX_RX_JUMBO_BUFFER_LENGTH      9046
-#define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - NET_IP_ALIGN)
+#define MAX_RX_LRO_BUFFER_LENGTH        ((48*1024)-512)
+#define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - 2)
 #define RX_JUMBO_DMA_MAP_LEN    \
-        (MAX_RX_JUMBO_BUFFER_LENGTH - NET_IP_ALIGN)
+        (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
+#define RX_LRO_DMA_MAP_LEN              (MAX_RX_LRO_BUFFER_LENGTH - 2)
 #define NETXEN_ROM_ROUNDUP              0x80000000ULL
 
 /*
@@ -151,30 +181,38 @@ enum {
 /* Host writes the following to notify that it has done the init-handshake */
 #define PHAN_INITIALIZE_ACK     0xf00f
 
-#define NUM_RCV_DESC_RINGS      2       /* No of Rcv Descriptor contexts */
+#define NUM_RCV_DESC_RINGS      3       /* No of Rcv Descriptor contexts */
 
 /* descriptor types */
 #define RCV_DESC_NORMAL         0x01
 #define RCV_DESC_JUMBO          0x02
+#define RCV_DESC_LRO            0x04
 #define RCV_DESC_NORMAL_CTXID   0
 #define RCV_DESC_JUMBO_CTXID    1
+#define RCV_DESC_LRO_CTXID      2
 
 #define RCV_DESC_TYPE(ID) \
-        ((ID == RCV_DESC_JUMBO_CTXID) ? RCV_DESC_JUMBO : RCV_DESC_NORMAL)
+        ((ID == RCV_DESC_JUMBO_CTXID)   \
+                ? RCV_DESC_JUMBO        \
+                : ((ID == RCV_DESC_LRO_CTXID)   \
+                        ? RCV_DESC_LRO :        \
+                        (RCV_DESC_NORMAL)))
 
 #define MAX_CMD_DESCRIPTORS             1024
 #define MAX_RCV_DESCRIPTORS             32768
-#define MAX_JUMBO_RCV_DESCRIPTORS       1024
+#define MAX_JUMBO_RCV_DESCRIPTORS       4096
+#define MAX_LRO_RCV_DESCRIPTORS         2048
 #define MAX_RCVSTATUS_DESCRIPTORS       MAX_RCV_DESCRIPTORS
 #define MAX_JUMBO_RCV_DESC      MAX_JUMBO_RCV_DESCRIPTORS
 #define MAX_RCV_DESC            MAX_RCV_DESCRIPTORS
 #define MAX_RCVSTATUS_DESC      MAX_RCV_DESCRIPTORS
-#define NUM_RCV_DESC            (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS)
 #define MAX_EPG_DESCRIPTORS     (MAX_CMD_DESCRIPTORS * 8)
-
+#define NUM_RCV_DESC            (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
+                                 MAX_LRO_RCV_DESCRIPTORS)
 #define MIN_TX_COUNT    4096
 #define MIN_RX_COUNT    4096
-
+#define NETXEN_CTX_SIGNATURE    0xdee0
+#define NETXEN_RCV_PRODUCER(ringid)     (ringid)
 #define MAX_FRAME_SIZE  0x10000 /* 64K MAX size for LSO */
 
 #define PHAN_PEG_RCV_INITIALIZED        0xff01
@@ -186,6 +224,67 @@ enum {
 #define get_index_range(index,length,count)     \
         (((index) + (count)) & ((length) - 1))
 
+#define MPORT_SINGLE_FUNCTION_MODE 0x1111
+
+extern unsigned long long netxen_dma_mask;
+
+/*
+ * NetXen host-peg signal message structure
+ *
+ *      Bit 0-1         : peg_id => 0x2 for tx and 01 for rx
+ *      Bit 2           : priv_id => must be 1
+ *      Bit 3-17        : count => for doorbell
+ *      Bit 18-27       : ctx_id => Context id
+ *      Bit 28-31       : opcode
+ */
+
+typedef u32 netxen_ctx_msg;
+
+#define _netxen_set_bits(config_word, start, bits, val) {\
+        unsigned long long mask = (((1ULL << (bits)) - 1) << (start));  \
+        unsigned long long value = (val);       \
+        (config_word) &= ~mask; \
+        (config_word) |= (((value) << (start)) & mask); \
+}
+
+#define netxen_set_msg_peg_id(config_word, val) \
+        _netxen_set_bits(config_word, 0, 2, val)
+#define netxen_set_msg_privid(config_word)      \
+        set_bit(2, (unsigned long*)&config_word)
+#define netxen_set_msg_count(config_word, val)  \
+        _netxen_set_bits(config_word, 3, 15, val)
+#define netxen_set_msg_ctxid(config_word, val)  \
+        _netxen_set_bits(config_word, 18, 10, val)
+#define netxen_set_msg_opcode(config_word, val) \
+        _netxen_set_bits(config_word, 28, 4, val)
+
+struct netxen_rcv_context {
+        u32 rcv_ring_addr_lo;
+        u32 rcv_ring_addr_hi;
+        u32 rcv_ring_size;
+        u32 rsrvd;
+};
+
+struct netxen_ring_ctx {
+
+        /* one command ring */
+        u64 cmd_consumer_offset;
+        u32 cmd_ring_addr_lo;
+        u32 cmd_ring_addr_hi;
+        u32 cmd_ring_size;
+        u32 rsrvd;
+
+        /* three receive rings */
+        struct netxen_rcv_context rcv_ctx[3];
+
+        /* one status ring */
+        u32 sts_ring_addr_lo;
+        u32 sts_ring_addr_hi;
+        u32 sts_ring_size;
+
+        u32 ctx_id;
+} __attribute__ ((aligned(64)));
+
 /*
  * Following data structures describe the descriptors that will be used.
  * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
@@ -203,22 +302,32 @@ enum {
 #define FLAGS_IPSEC_SA_DELETE   0x08
 #define FLAGS_VLAN_TAGGED       0x10
 
-#define CMD_DESC_TOTAL_LENGTH(cmd_desc) \
-                ((cmd_desc)->length_tcp_hdr & 0x00FFFFFF)
-#define CMD_DESC_TCP_HDR_OFFSET(cmd_desc)       \
-                (((cmd_desc)->length_tcp_hdr >> 24) & 0x0FF)
-#define CMD_DESC_PORT(cmd_desc)         ((cmd_desc)->port_ctxid & 0x0F)
-#define CMD_DESC_CTX_ID(cmd_desc)       (((cmd_desc)->port_ctxid >> 4) & 0x0F)
+#define netxen_set_cmd_desc_port(cmd_desc, var) \
+        ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 
-#define CMD_DESC_TOTAL_LENGTH_WRT(cmd_desc, var)        \
-                ((cmd_desc)->length_tcp_hdr |= ((var) & 0x00FFFFFF))
-#define CMD_DESC_TCP_HDR_OFFSET_WRT(cmd_desc, var)      \
-                ((cmd_desc)->length_tcp_hdr |= (((var) << 24) & 0xFF000000))
-#define CMD_DESC_PORT_WRT(cmd_desc, var)        \
-                ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
+#define netxen_set_cmd_desc_flags(cmd_desc, val)        \
+        _netxen_set_bits((cmd_desc)->flags_opcode, 0, 7, val)
+#define netxen_set_cmd_desc_opcode(cmd_desc, val)       \
+        _netxen_set_bits((cmd_desc)->flags_opcode, 7, 6, val)
+
+#define netxen_set_cmd_desc_num_of_buff(cmd_desc, val)  \
+        _netxen_set_bits((cmd_desc)->num_of_buffers_total_length, 0, 8, val);
+#define netxen_set_cmd_desc_totallength(cmd_desc, val)  \
+        _netxen_set_bits((cmd_desc)->num_of_buffers_total_length, 8, 24, val);
+
+#define netxen_get_cmd_desc_opcode(cmd_desc)    \
+        (((cmd_desc)->flags_opcode >> 7) & 0x003F)
+#define netxen_get_cmd_desc_totallength(cmd_desc)       \
+        (((cmd_desc)->num_of_buffers_total_length >> 8) & 0x0FFFFFF)
 
 struct cmd_desc_type0 {
-        u64 netxen_next;        /* for fragments handled by Phantom */
+        u8 tcp_hdr_offset;      /* For LSO only */
+        u8 ip_hdr_offset;       /* For LSO only */
+        /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
+        u16 flags_opcode;
+        /* Bit pattern: 0-7 total number of segments,
+           8-31 Total size of the packet */
+        u32 num_of_buffers_total_length;
         union {
                 struct {
                         u32 addr_low_part2;
@@ -227,13 +336,6 @@ struct cmd_desc_type0 {
                 u64 addr_buffer2;
         };
 
-        /* Bit pattern: 0-23 total length, 24-32 tcp header offset */
-        u32 length_tcp_hdr;
-        u8 ip_hdr_offset;       /* For LSO only */
-        u8 num_of_buffers;      /* total number of segments */
-        u8 flags;               /* as defined above */
-        u8 opcode;
-
         u16 reference_handle;   /* changed to u16 to add mss */
         u16 mss;                /* passed by NDIS_PACKET for LSO */
         /* Bit pattern 0-3 port, 0-3 ctx id */
@@ -248,7 +350,6 @@ struct cmd_desc_type0 {
                 };
                 u64 addr_buffer3;
         };
-
         union {
                 struct {
                         u32 addr_low_part1;
@@ -270,6 +371,8 @@ struct cmd_desc_type0 {
                 u64 addr_buffer4;
         };
 
+        u64 unused;
+
 } __attribute__ ((aligned(64)));
 
 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
@@ -296,22 +399,49 @@ struct rcv_desc {
 #define NETXEN_PROT_UNKNOWN     (0)
 
 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
-#define STATUS_DESC_PORT(status_desc)   \
-                ((status_desc)->port_status_type_op & 0x0F)
-#define STATUS_DESC_STATUS(status_desc) \
-                (((status_desc)->port_status_type_op >> 4) & 0x0F)
-#define STATUS_DESC_TYPE(status_desc)   \
-                (((status_desc)->port_status_type_op >> 8) & 0x0F)
-#define STATUS_DESC_OPCODE(status_desc) \
-                (((status_desc)->port_status_type_op >> 12) & 0x0F)
+
+#define netxen_get_sts_desc_lro_cnt(status_desc)        \
+        ((status_desc)->lro & 0x7F)
+#define netxen_get_sts_desc_lro_last_frag(status_desc)  \
+        (((status_desc)->lro & 0x80) >> 7)
+
+#define netxen_get_sts_port(status_desc)        \
+        ((status_desc)->status_desc_data & 0x0F)
+#define netxen_get_sts_status(status_desc)      \
+        (((status_desc)->status_desc_data >> 4) & 0x0F)
+#define netxen_get_sts_type(status_desc)        \
+        (((status_desc)->status_desc_data >> 8) & 0x0F)
+#define netxen_get_sts_totallength(status_desc) \
+        (((status_desc)->status_desc_data >> 12) & 0xFFFF)
+#define netxen_get_sts_refhandle(status_desc)   \
+        (((status_desc)->status_desc_data >> 28) & 0xFFFF)
+#define netxen_get_sts_prot(status_desc)        \
+        (((status_desc)->status_desc_data >> 44) & 0x0F)
+#define netxen_get_sts_owner(status_desc)       \
+        (((status_desc)->status_desc_data >> 56) & 0x03)
+#define netxen_get_sts_opcode(status_desc)      \
+        (((status_desc)->status_desc_data >> 58) & 0x03F)
+
+#define netxen_clear_sts_owner(status_desc)     \
+        ((status_desc)->status_desc_data &=     \
+        ~(((unsigned long long)3) << 56 ))
+#define netxen_set_sts_owner(status_desc, val)  \
+        ((status_desc)->status_desc_data |=     \
+        (((unsigned long long)((val) & 0x3)) << 56 ))
 
 struct status_desc {
-        /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-15 opcode */
-        u16 port_status_type_op;
-        u16 total_length;       /* NIC mode */
-        u16 reference_handle;   /* handle for the associated packet */
-        /* Bit pattern: 0-1 owner, 2-5 protocol */
-        u16 owner;              /* Owner of the descriptor */
+        /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
+           28-43 reference_handle, 44-47 protocol, 48-52 unused
+           53-55 desc_cnt, 56-57 owner, 58-63 opcode
+         */
+        u64 status_desc_data;
+        u32 hash_value;
+        u8 hash_type;
+        u8 msg_type;
+        u8 unused;
+        /* Bit pattern: 0-6 lro_count indicates frag sequence,
+           7 last_frag indicates last frag */
+        u8 lro;
 } __attribute__ ((aligned(8)));
 
 enum {
@@ -559,11 +689,12 @@ typedef enum {
 #define PRIMARY_START           (BOOTLD_START)
 #define FLASH_CRBINIT_SIZE      (0x4000)
 #define FLASH_BRDCFG_SIZE       (sizeof(struct netxen_board_info))
-#define FLASH_USER_SIZE         (sizeof(netxen_user_info)/sizeof(u32))
+#define FLASH_USER_SIZE         (sizeof(struct netxen_user_info)/sizeof(u32))
 #define FLASH_SECONDARY_SIZE    (USER_START-SECONDARY_START)
 #define NUM_PRIMARY_SECTORS     (0x20)
 #define NUM_CONFIG_SECTORS      (1)
-#define PFX "netxen: "
+#define PFX "NetXen: "
+extern char netxen_nic_driver_name[];
 
 /* Note: Make sure to not call this before adapter->port is valid */
 #if !defined(NETXEN_DEBUG)
@@ -572,7 +703,7 @@ typedef enum {
 #else
 #define DPRINTK(klevel, fmt, args...)   do { \
         printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
-                (adapter != NULL && adapter->port != NULL && \
+                (adapter != NULL && \
                 adapter->port[0] != NULL && \
                 adapter->port[0]->netdev != NULL) ? \
                 adapter->port[0]->netdev->name : NULL, \
@@ -609,7 +740,6 @@ struct netxen_cmd_buffer {
         u8 frag_count;
         unsigned long time_stamp;
         u32 state;
-        u32 no_of_descriptors;
 };
 
 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
@@ -618,6 +748,9 @@ struct netxen_rx_buffer {
         u64 dma;
         u16 ref_handle;
         u16 state;
+        u32 lro_expected_frags;
+        u32 lro_current_frags;
+        u32 lro_length;
 };
 
 /* Board types */
@@ -633,6 +766,8 @@ struct netxen_hardware_context {
         void __iomem *pci_base0;
         void __iomem *pci_base1;
         void __iomem *pci_base2;
+        void __iomem *db_base;
+        unsigned long db_len;
 
         u8 revision_id;
         u16 board_type;
@@ -642,14 +777,13 @@ struct netxen_hardware_context {
         u32 qg_linksup;
         /* Address of cmd ring in Phantom */
         struct cmd_desc_type0 *cmd_desc_head;
-        char *pauseaddr;
         struct pci_dev *cmd_desc_pdev;
         dma_addr_t cmd_desc_phys_addr;
-        dma_addr_t pause_physaddr;
-        struct pci_dev *pause_pdev;
         struct netxen_adapter *adapter;
 };
 
+#define RCV_RING_LRO    RCV_DESC_LRO
+
 #define MINIMUM_ETHERNET_FRAME_SIZE     64      /* With FCS */
 #define ETHERNET_FCS_SIZE               4
 
@@ -702,8 +836,13 @@ struct netxen_recv_context {
 };
 
 #define NETXEN_NIC_MSI_ENABLED 0x02
+#define NETXEN_DMA_MASK 0xfffffffe
+#define NETXEN_DB_MAPSIZE_BYTES    0x1000
 
-struct netxen_drvops;
+struct netxen_dummy_dma {
+        void *addr;
+        dma_addr_t phys_addr;
+};
 
 struct netxen_adapter {
         struct netxen_hardware_context ahw;
@@ -714,17 +853,19 @@ struct netxen_adapter {
         spinlock_t lock;
         struct work_struct watchdog_task;
         struct work_struct tx_timeout_task;
+        struct net_device *netdev;
         struct timer_list watchdog_timer;
 
         u32 curr_window;
 
         u32 cmd_producer;
-        u32 cmd_consumer;
+        u32 *cmd_consumer;
 
         u32 last_cmd_consumer;
         u32 max_tx_desc_count;
         u32 max_rx_desc_count;
         u32 max_jumbo_rx_desc_count;
+        u32 max_lro_rx_desc_count;
         /* Num of instances active on cmd buffer ring */
         u32 proc_cmd_buf_counter;
 
@@ -746,8 +887,27 @@ struct netxen_adapter {
         struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
 
         int is_up;
-        int work_done;
-        struct netxen_drvops *ops;
+        int number;
+        struct netxen_dummy_dma dummy_dma;
+
+        /* Context interface shared between card and host */
+        struct netxen_ring_ctx *ctx_desc;
+        struct pci_dev *ctx_desc_pdev;
+        dma_addr_t ctx_desc_phys_addr;
+        int (*enable_phy_interrupts) (struct netxen_adapter *, int);
+        int (*disable_phy_interrupts) (struct netxen_adapter *, int);
+        void (*handle_phy_intr) (struct netxen_adapter *);
+        int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t);
+        int (*set_mtu) (struct netxen_port *, int);
+        int (*set_promisc) (struct netxen_adapter *, int,
+                            netxen_niu_prom_mode_t);
+        int (*unset_promisc) (struct netxen_adapter *, int,
+                              netxen_niu_prom_mode_t);
+        int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *);
+        int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val);
+        int (*init_port) (struct netxen_adapter *, int);
+        void (*init_niu) (struct netxen_adapter *);
+        int (*stop_port) (struct netxen_adapter *, int);
 };                              /* netxen_adapter structure */
 
 /* Max number of xmit producer threads that can run simultaneously */
@@ -829,25 +989,6 @@ static inline void __iomem *pci_base(struct netxen_adapter *adapter,
         return NULL;
 }
 
-struct netxen_drvops {
-        int (*enable_phy_interrupts) (struct netxen_adapter *, int);
-        int (*disable_phy_interrupts) (struct netxen_adapter *, int);
-        void (*handle_phy_intr) (struct netxen_adapter *);
-        int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t);
-        int (*set_mtu) (struct netxen_port *, int);
-        int (*set_promisc) (struct netxen_adapter *, int,
-                            netxen_niu_prom_mode_t);
-        int (*unset_promisc) (struct netxen_adapter *, int,
-                              netxen_niu_prom_mode_t);
-        int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *);
-        int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val);
-        int (*init_port) (struct netxen_adapter *, int);
-        void (*init_niu) (struct netxen_adapter *);
-        int (*stop_port) (struct netxen_adapter *, int);
-};
-
-extern char netxen_nic_driver_name[];
-
 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
                                           int port);
 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
@@ -886,10 +1027,20 @@ int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
                           int len);
 int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
                            int len);
+int netxen_nic_hw_read_ioctl(struct netxen_adapter *adapter, u64 off,
+                             void *data, int len);
+int netxen_nic_hw_write_ioctl(struct netxen_adapter *adapter, u64 off,
+                              void *data, int len);
+int netxen_nic_pci_mem_write_ioctl(struct netxen_adapter *adapter,
+                                   u64 off, void *data, int size);
+int netxen_nic_pci_mem_read_ioctl(struct netxen_adapter *adapter,
+                                  u64 off, void *data, int size);
 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
                                  unsigned long off, int data);
 
 /* Functions from netxen_nic_init.c */
+void netxen_free_adapter_offload(struct netxen_adapter *adapter);
+int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
 void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
 void netxen_load_firmware(struct netxen_adapter *adapter);
 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
@@ -921,10 +1072,12 @@ netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
                     struct netxen_port *port);
 int netxen_nic_rx_has_work(struct netxen_adapter *adapter);
 int netxen_nic_tx_has_work(struct netxen_adapter *adapter);
-void netxen_watchdog_task(unsigned long v);
+void netxen_watchdog_task(struct work_struct *work);
 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
                             u32 ringid);
-void netxen_process_cmd_ring(unsigned long data);
+void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, u32 ctx,
+                                 u32 ringid);
+int netxen_process_cmd_ring(unsigned long data);
 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
 void netxen_nic_set_multi(struct net_device *netdev);
 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
@@ -1018,7 +1171,6 @@ static inline void get_brd_name_by_type(u32 type, char *name)
 
 int netxen_is_flash_supported(struct netxen_adapter *adapter);
 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]);
-
 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
                                 int *valp);
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index 9a914aeba5bc..2ab4885cc950 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -1,25 +1,25 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
- *                            
+ *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *                                   
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -118,7 +118,7 @@ netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
         u32 fw_minor = 0;
         u32 fw_build = 0;
 
-        strncpy(drvinfo->driver, "netxen_nic", 32);
+        strncpy(drvinfo->driver, netxen_nic_driver_name, 32);
         strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
         fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
                                               NETXEN_FW_VERSION_MAJOR));
@@ -210,7 +210,6 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
                 printk(KERN_ERR "netxen-nic: Unsupported board model %d\n",
                        (netxen_brdtype_t) boardinfo->board_type);
                 return -EIO;
-
         }
 
         return 0;
@@ -226,18 +225,18 @@ netxen_nic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
         /* read which mode */
         if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
                 /* autonegotiation */
-                if (adapter->ops->phy_write
-                    && adapter->ops->phy_write(adapter, port->portnum,
-                                               NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
-                                               (__le32) ecmd->autoneg) != 0)
+                if (adapter->phy_write
+                    && adapter->phy_write(adapter, port->portnum,
+                                          NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
+                                          (__le32) ecmd->autoneg) != 0)
                         return -EIO;
                 else
                         port->link_autoneg = ecmd->autoneg;
 
-                if (adapter->ops->phy_read
-                    && adapter->ops->phy_read(adapter, port->portnum,
-                                              NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
-                                              &status) != 0)
+                if (adapter->phy_read
+                    && adapter->phy_read(adapter, port->portnum,
+                                         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+                                         &status) != 0)
                         return -EIO;
 
                 /* speed */
@@ -257,10 +256,10 @@ netxen_nic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
                         netxen_clear_phy_duplex(status);
                 if (ecmd->duplex == DUPLEX_FULL)
                         netxen_set_phy_duplex(status);
-                if (adapter->ops->phy_write
-                    && adapter->ops->phy_write(adapter, port->portnum,
-                                               NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
-                                               *((int *)&status)) != 0)
+                if (adapter->phy_write
+                    && adapter->phy_write(adapter, port->portnum,
+                                          NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+                                          *((int *)&status)) != 0)
                         return -EIO;
                 else {
                         port->link_speed = ecmd->speed;
@@ -422,10 +421,10 @@ static u32 netxen_nic_get_link(struct net_device *dev)
 
         /* read which mode */
         if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
-                if (adapter->ops->phy_read
-                    && adapter->ops->phy_read(adapter, port->portnum,
-                                              NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
-                                              &status) != 0)
+                if (adapter->phy_read
+                    && adapter->phy_read(adapter, port->portnum,
+                                         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+                                         &status) != 0)
                         return -EIO;
                 else
                         return (netxen_get_phy_link(status));
@@ -460,20 +459,22 @@ netxen_nic_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ring)
 {
         struct netxen_port *port = netdev_priv(dev);
         struct netxen_adapter *adapter = port->adapter;
-        int i, j;
+        int i;
 
         ring->rx_pending = 0;
+        ring->rx_jumbo_pending = 0;
         for (i = 0; i < MAX_RCV_CTX; ++i) {
-                for (j = 0; j < NUM_RCV_DESC_RINGS; j++)
-                        ring->rx_pending +=
-                            adapter->recv_ctx[i].rcv_desc[j].rcv_pending;
+                ring->rx_pending += adapter->recv_ctx[i].
+                    rcv_desc[RCV_DESC_NORMAL_CTXID].rcv_pending;
+                ring->rx_jumbo_pending += adapter->recv_ctx[i].
+                    rcv_desc[RCV_DESC_JUMBO_CTXID].rcv_pending;
         }
 
         ring->rx_max_pending = adapter->max_rx_desc_count;
         ring->tx_max_pending = adapter->max_tx_desc_count;
+        ring->rx_jumbo_max_pending = adapter->max_jumbo_rx_desc_count;
         ring->rx_mini_max_pending = 0;
         ring->rx_mini_pending = 0;
-        ring->rx_jumbo_max_pending = 0;
         ring->rx_jumbo_pending = 0;
 }
 
@@ -526,10 +527,10 @@ netxen_nic_set_pauseparam(struct net_device *dev,
                                     *(u32 *) (&val));
                 /* set autoneg */
                 autoneg = pause->autoneg;
-                if (adapter->ops->phy_write
-                    && adapter->ops->phy_write(adapter, port->portnum,
-                                               NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
-                                               (__le32) autoneg) != 0)
+                if (adapter->phy_write
+                    && adapter->phy_write(adapter, port->portnum,
+                                          NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
+                                          (__le32) autoneg) != 0)
                         return -EIO;
                 else {
                         port->link_autoneg = pause->autoneg;
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h
index 72c6ec4ee2a0..fe8b675f9e72 100644
--- a/drivers/net/netxen/netxen_nic_hdr.h
+++ b/drivers/net/netxen/netxen_nic_hdr.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -16,10 +16,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 105c24f0ad4c..9147b6048dfb 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -16,10 +16,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -42,7 +42,7 @@
 
 #define NETXEN_FLASH_BASE       (BOOTLD_START)
 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
-#define NETXEN_MAX_MTU          8000
+#define NETXEN_MAX_MTU          8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
 #define NETXEN_MIN_MTU          64
 #define NETXEN_ETH_FCS_SIZE     4
 #define NETXEN_ENET_HEADER_SIZE 14
@@ -81,8 +81,8 @@ int netxen_nic_set_mac(struct net_device *netdev, void *p)
         DPRINTK(INFO, "valid ether addr\n");
         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
 
-        if (adapter->ops->macaddr_set)
-                adapter->ops->macaddr_set(port, addr->sa_data);
+        if (adapter->macaddr_set)
+                adapter->macaddr_set(port, addr->sa_data);
 
         return 0;
 }
@@ -99,17 +99,17 @@ void netxen_nic_set_multi(struct net_device *netdev)
 
         mc_ptr = netdev->mc_list;
         if (netdev->flags & IFF_PROMISC) {
-                if (adapter->ops->set_promisc)
-                        adapter->ops->set_promisc(adapter,
-                                                  port->portnum,
-                                                  NETXEN_NIU_PROMISC_MODE);
+                if (adapter->set_promisc)
+                        adapter->set_promisc(adapter,
+                                             port->portnum,
+                                             NETXEN_NIU_PROMISC_MODE);
         } else {
-                if (adapter->ops->unset_promisc &&
+                if (adapter->unset_promisc &&
                     adapter->ahw.boardcfg.board_type
                     != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
-                        adapter->ops->unset_promisc(adapter,
-                                                    port->portnum,
-                                                    NETXEN_NIU_NON_PROMISC_MODE);
+                        adapter->unset_promisc(adapter,
+                                               port->portnum,
+                                               NETXEN_NIU_NON_PROMISC_MODE);
         }
         if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
                 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
@@ -160,8 +160,8 @@ int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
                 return -EINVAL;
         }
 
-        if (adapter->ops->set_mtu)
-                adapter->ops->set_mtu(port, mtu);
+        if (adapter->set_mtu)
+                adapter->set_mtu(port, mtu);
         netdev->mtu = mtu;
 
         return 0;
@@ -176,22 +176,18 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
         struct netxen_hardware_context *hw = &adapter->ahw;
         u32 state = 0;
         void *addr;
-        void *pause_addr;
         int loops = 0, err = 0;
         int ctx, ring;
         u32 card_cmdring = 0;
-        struct netxen_rcv_desc_crb *rcv_desc_crb = NULL;
         struct netxen_recv_context *recv_ctx;
         struct netxen_rcv_desc_ctx *rcv_desc;
 
-        DPRINTK(INFO, "crb_base: %lx %lx", NETXEN_PCI_CRBSPACE,
+        DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
                 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
-        DPRINTK(INFO, "cam base: %lx %lx", NETXEN_CRB_CAM,
+        DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
                 pci_base_offset(adapter, NETXEN_CRB_CAM));
-        DPRINTK(INFO, "cam RAM: %lx %lx", NETXEN_CAM_RAM_BASE,
+        DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
                 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
-        DPRINTK(INFO, "NIC base:%lx %lx\n", NIC_CRB_BASE_PORT1,
-                pci_base_offset(adapter, NIC_CRB_BASE_PORT1));
 
         /* Window 1 call */
         card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
@@ -226,33 +222,42 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
         DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
 
         addr = netxen_alloc(adapter->ahw.pdev,
-                            sizeof(struct cmd_desc_type0) *
-                            adapter->max_tx_desc_count,
-                            &hw->cmd_desc_phys_addr, &hw->cmd_desc_pdev);
+                            sizeof(struct netxen_ring_ctx) +
+                            sizeof(uint32_t),
+                            (dma_addr_t *) & adapter->ctx_desc_phys_addr,
+                            &adapter->ctx_desc_pdev);
 
+        printk("ctx_desc_phys_addr: 0x%llx\n",
+               (u64) adapter->ctx_desc_phys_addr);
         if (addr == NULL) {
                 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
-                return -ENOMEM;
+                err = -ENOMEM;
+                return err;
         }
+        memset(addr, 0, sizeof(struct netxen_ring_ctx));
+        adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
+        adapter->ctx_desc->cmd_consumer_offset = adapter->ctx_desc_phys_addr
+            + sizeof(struct netxen_ring_ctx);
+        adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
+                                              sizeof(struct netxen_ring_ctx));
+
+        addr = pci_alloc_consistent(adapter->ahw.pdev,
+                                    sizeof(struct cmd_desc_type0) *
+                                    adapter->max_tx_desc_count,
+                                    (dma_addr_t *) & hw->cmd_desc_phys_addr);
+        printk("cmd_desc_phys_addr: 0x%llx\n", (u64) hw->cmd_desc_phys_addr);
 
-        pause_addr = netxen_alloc(adapter->ahw.pdev, 512,
-                                  (dma_addr_t *) & hw->pause_physaddr,
-                                  &hw->pause_pdev);
-        if (pause_addr == NULL) {
-                DPRINTK(1, ERR, "bad return from pci_alloc_consistent\n");
+        if (addr == NULL) {
+                DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
+                netxen_free_hw_resources(adapter);
                 return -ENOMEM;
         }
 
-        hw->pauseaddr = (char *)pause_addr;
-        {
-                u64 *ptr = (u64 *) pause_addr;
-                *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
-                *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
-                *ptr++ = NETXEN_NIC_UNIT_PAUSE_ADDR;
-                *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
-                *ptr++ = NETXEN_NIC_EPG_PAUSE_ADDR1;
-                *ptr++ = NETXEN_NIC_EPG_PAUSE_ADDR2;
-        }
+        adapter->ctx_desc->cmd_ring_addr_lo =
+            hw->cmd_desc_phys_addr & 0xffffffffUL;
+        adapter->ctx_desc->cmd_ring_addr_hi =
+            ((u64) hw->cmd_desc_phys_addr >> 32);
+        adapter->ctx_desc->cmd_ring_size = adapter->max_tx_desc_count;
 
         hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
 
@@ -273,6 +278,12 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
                                 return err;
                         }
                         rcv_desc->desc_head = (struct rcv_desc *)addr;
+                        adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr_lo =
+                            rcv_desc->phys_addr & 0xffffffffUL;
+                        adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr_hi =
+                            ((u64) rcv_desc->phys_addr >> 32);
+                        adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
+                            rcv_desc->max_rx_desc_count;
                 }
 
                 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
@@ -286,47 +297,21 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
                         return err;
                 }
                 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
-                for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
-                        rcv_desc = &recv_ctx->rcv_desc[ring];
-                        rcv_desc_crb =
-                            &recv_crb_registers[ctx].rcv_desc_crb[ring];
-                        DPRINTK(INFO, "ring #%d crb global ring reg 0x%x\n",
-                                ring, rcv_desc_crb->crb_globalrcv_ring);
-                        /* Window = 1 */
-                        writel(lower32(rcv_desc->phys_addr),
-                               NETXEN_CRB_NORMALIZE(adapter,
-                                                    rcv_desc_crb->
-                                                    crb_globalrcv_ring));
-                        DPRINTK(INFO, "GLOBAL_RCV_RING ctx %d, addr 0x%x"
-                                " val 0x%llx,"
-                                " virt %p\n", ctx,
-                                rcv_desc_crb->crb_globalrcv_ring,
-                                (unsigned long long)rcv_desc->phys_addr,
-                                +rcv_desc->desc_head);
-                }
+                adapter->ctx_desc->sts_ring_addr_lo =
+                    recv_ctx->rcv_status_desc_phys_addr & 0xffffffffUL;
+                adapter->ctx_desc->sts_ring_addr_hi =
+                    ((u64) recv_ctx->rcv_status_desc_phys_addr >> 32);
+                adapter->ctx_desc->sts_ring_size = adapter->max_rx_desc_count;
 
-                /* Window = 1 */
-                writel(lower32(recv_ctx->rcv_status_desc_phys_addr),
-                       NETXEN_CRB_NORMALIZE(adapter,
-                                            recv_crb_registers[ctx].
-                                            crb_rcvstatus_ring));
-                DPRINTK(INFO, "RCVSTATUS_RING, ctx %d, addr 0x%x,"
-                        " val 0x%x,virt%p\n",
-                        ctx,
-                        recv_crb_registers[ctx].crb_rcvstatus_ring,
-                        (unsigned long long)recv_ctx->rcv_status_desc_phys_addr,
-                        recv_ctx->rcv_status_desc_head);
         }
         /* Window = 1 */
-        writel(lower32(hw->pause_physaddr),
-               NETXEN_CRB_NORMALIZE(adapter, CRB_PAUSE_ADDR_LO));
-        writel(upper32(hw->pause_physaddr),
-               NETXEN_CRB_NORMALIZE(adapter, CRB_PAUSE_ADDR_HI));
-
-        writel(lower32(hw->cmd_desc_phys_addr),
-               NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
-        writel(upper32(hw->cmd_desc_phys_addr),
-               NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_HI));
+
+        writel(lower32(adapter->ctx_desc_phys_addr),
+               NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO));
+        writel(upper32(adapter->ctx_desc_phys_addr),
+               NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI));
+        writel(NETXEN_CTX_SIGNATURE,
+               NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG));
         return err;
 }
 
@@ -336,6 +321,15 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
         struct netxen_rcv_desc_ctx *rcv_desc;
         int ctx, ring;
 
+        if (adapter->ctx_desc != NULL) {
+                pci_free_consistent(adapter->ctx_desc_pdev,
+                                    sizeof(struct netxen_ring_ctx) +
+                                    sizeof(uint32_t),
+                                    adapter->ctx_desc,
+                                    adapter->ctx_desc_phys_addr);
+                adapter->ctx_desc = NULL;
+        }
+
         if (adapter->ahw.cmd_desc_head != NULL) {
                 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
                                     sizeof(struct cmd_desc_type0) *
@@ -344,11 +338,9 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
                                     adapter->ahw.cmd_desc_phys_addr);
                 adapter->ahw.cmd_desc_head = NULL;
         }
-        if (adapter->ahw.pauseaddr != NULL) {
-                pci_free_consistent(adapter->ahw.pause_pdev, 512,
-                                    adapter->ahw.pauseaddr,
-                                    adapter->ahw.pause_physaddr);
-                adapter->ahw.pauseaddr = NULL;
+        /* Special handling: there are 2 ports on this board */
+        if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
+                adapter->ahw.max_ports = 2;
         }
 
         for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
@@ -383,19 +375,22 @@ void netxen_tso_check(struct netxen_adapter *adapter,
                 desc->total_hdr_length = sizeof(struct ethhdr) +
                     ((skb->nh.iph)->ihl * sizeof(u32)) +
                     ((skb->h.th)->doff * sizeof(u32));
-                desc->opcode = TX_TCP_LSO;
+                netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
         } else if (skb->ip_summed == CHECKSUM_COMPLETE) {
                 if (skb->nh.iph->protocol == IPPROTO_TCP) {
-                        desc->opcode = TX_TCP_PKT;
+                        netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
                 } else if (skb->nh.iph->protocol == IPPROTO_UDP) {
-                        desc->opcode = TX_UDP_PKT;
+                        netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
                 } else {
                         return;
                 }
         }
         adapter->stats.xmitcsummed++;
-        CMD_DESC_TCP_HDR_OFFSET_WRT(desc, skb->h.raw - skb->data);
-        desc->length_tcp_hdr = cpu_to_le32(desc->length_tcp_hdr);
+        desc->tcp_hdr_offset = skb->h.raw - skb->data;
+        netxen_set_cmd_desc_totallength(desc,
+                                        cpu_to_le32
+                                        (netxen_get_cmd_desc_totallength
+                                         (desc)));
         desc->ip_hdr_offset = skb->nh.raw - skb->data;
 }
 
@@ -648,7 +643,7 @@ void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
 
         addr = NETXEN_CRB_NORMALIZE(adapter, off);
         DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
-                pci_base(adapter, off), off, addr);
+                pci_base(adapter, off), off, addr, val);
         writel(val, addr);
 
 }
@@ -660,7 +655,7 @@ int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
 
         addr = NETXEN_CRB_NORMALIZE(adapter, off);
         DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
-                adapter->ahw.pci_base, off, addr);
+                pci_base(adapter, off), off, addr);
         val = readl(addr);
         writel(val, addr);
 
@@ -848,8 +843,8 @@ void netxen_nic_stop_all_ports(struct netxen_adapter *adapter)
 
         for (port_nr = 0; port_nr < adapter->ahw.max_ports; port_nr++) {
                 port = adapter->port[port_nr];
-                if (adapter->ops->stop_port)
-                        adapter->ops->stop_port(adapter, port->portnum);
+                if (adapter->stop_port)
+                        adapter->stop_port(adapter, port->portnum);
         }
 }
 
@@ -873,13 +868,13 @@ void netxen_nic_set_link_parameters(struct netxen_port *port)
 {
         struct netxen_adapter *adapter = port->adapter;
         __le32 status;
-        u16 autoneg;
+        __le32 autoneg;
         __le32 mode;
 
         netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
         if (netxen_get_niu_enable_ge(mode)) {   /* Gb 10/100/1000 Mbps mode */
-                if (adapter->ops->phy_read
-                    && adapter->ops->
+                if (adapter->phy_read
+                    && adapter->
                     phy_read(adapter, port->portnum,
                              NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
                              &status) == 0) {
@@ -909,11 +904,11 @@ void netxen_nic_set_link_parameters(struct netxen_port *port)
                                         port->link_duplex = -1;
                                         break;
                                 }
-                                if (adapter->ops->phy_read
-                                    && adapter->ops->
+                                if (adapter->phy_read
+                                    && adapter->
                                     phy_read(adapter, port->portnum,
                                              NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
-                                             (__le32 *) & autoneg) != 0)
+                                             &autoneg) != 0)
                                         port->link_autoneg = autoneg;
                         } else
                                 goto link_down;
@@ -1008,3 +1003,291 @@ int netxen_crb_read_val(struct netxen_adapter *adapter, unsigned long off)
         netxen_nic_hw_read_wx(adapter, off, &data, 4);
         return data;
 }
+
+int netxen_nic_hw_write_ioctl(struct netxen_adapter *adapter, u64 off,
+                              void *data, int len)
+{
+        void *addr;
+        u64 offset = off;
+        u8 *mem_ptr = NULL;
+        unsigned long mem_base;
+        unsigned long mem_page;
+
+        if (ADDR_IN_WINDOW1(off)) {
+                addr = NETXEN_CRB_NORMALIZE(adapter, off);
+                if (!addr) {
+                        mem_base = pci_resource_start(adapter->ahw.pdev, 0);
+                        offset = NETXEN_CRB_NORMAL(off);
+                        mem_page = offset & PAGE_MASK;
+                        if (mem_page != ((offset + len - 1) & PAGE_MASK))
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE * 2);
+                        else
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE);
+                        if (mem_ptr == 0UL) {
+                                return 1;
+                        }
+                        addr = mem_ptr;
+                        addr += offset & (PAGE_SIZE - 1);
+                }
+        } else {
+                addr = pci_base_offset(adapter, off);
+                if (!addr) {
+                        mem_base = pci_resource_start(adapter->ahw.pdev, 0);
+                        mem_page = off & PAGE_MASK;
+                        if (mem_page != ((off + len - 1) & PAGE_MASK))
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE * 2);
+                        else
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE);
+                        if (mem_ptr == 0UL) {
+                                return 1;
+                        }
+                        addr = mem_ptr;
+                        addr += off & (PAGE_SIZE - 1);
+                }
+                netxen_nic_pci_change_crbwindow(adapter, 0);
+        }
+        switch (len) {
+        case 1:
+                writeb(*(u8 *) data, addr);
+                break;
+        case 2:
+                writew(*(u16 *) data, addr);
+                break;
+        case 4:
+                writel(*(u32 *) data, addr);
+                break;
+        case 8:
+                writeq(*(u64 *) data, addr);
+                break;
+        default:
+                DPRINTK(INFO,
+                        "writing data %lx to offset %llx, num words=%d\n",
+                        *(unsigned long *)data, off, (len >> 3));
+
+                netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
+                                            (len >> 3));
+                break;
+        }
+
+        if (!ADDR_IN_WINDOW1(off))
+                netxen_nic_pci_change_crbwindow(adapter, 1);
+        if (mem_ptr)
+                iounmap(mem_ptr);
+        return 0;
+}
+
+int netxen_nic_hw_read_ioctl(struct netxen_adapter *adapter, u64 off,
+                             void *data, int len)
+{
+        void *addr;
+        u64 offset;
+        u8 *mem_ptr = NULL;
+        unsigned long mem_base;
+        unsigned long mem_page;
+
+        if (ADDR_IN_WINDOW1(off)) {
+                addr = NETXEN_CRB_NORMALIZE(adapter, off);
+                if (!addr) {
+                        mem_base = pci_resource_start(adapter->ahw.pdev, 0);
+                        offset = NETXEN_CRB_NORMAL(off);
+                        mem_page = offset & PAGE_MASK;
+                        if (mem_page != ((offset + len - 1) & PAGE_MASK))
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE * 2);
+                        else
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE);
+                        if (mem_ptr == 0UL) {
+                                *(u8 *) data = 0;
+                                return 1;
+                        }
+                        addr = mem_ptr;
+                        addr += offset & (PAGE_SIZE - 1);
+                }
+        } else {
+                addr = pci_base_offset(adapter, off);
+                if (!addr) {
+                        mem_base = pci_resource_start(adapter->ahw.pdev, 0);
+                        mem_page = off & PAGE_MASK;
+                        if (mem_page != ((off + len - 1) & PAGE_MASK))
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE * 2);
+                        else
+                                mem_ptr =
+                                    ioremap(mem_base + mem_page, PAGE_SIZE);
+                        if (mem_ptr == 0UL)
+                                return 1;
+                        addr = mem_ptr;
+                        addr += off & (PAGE_SIZE - 1);
+                }
+                netxen_nic_pci_change_crbwindow(adapter, 0);
+        }
+        switch (len) {
+        case 1:
+                *(u8 *) data = readb(addr);
+                break;
+        case 2:
+                *(u16 *) data = readw(addr);
+                break;
+        case 4:
+                *(u32 *) data = readl(addr);
+                break;
+        case 8:
+                *(u64 *) data = readq(addr);
+                break;
+        default:
+                netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
+                                           (len >> 3));
+                break;
+        }
+        if (!ADDR_IN_WINDOW1(off))
+                netxen_nic_pci_change_crbwindow(adapter, 1);
+        if (mem_ptr)
+                iounmap(mem_ptr);
+        return 0;
+}
+
+int netxen_nic_pci_mem_write_ioctl(struct netxen_adapter *adapter, u64 off,
+                                   void *data, int size)
+{
+        void *addr;
+        int ret = 0;
+        u8 *mem_ptr = NULL;
+        unsigned long mem_base;
+        unsigned long mem_page;
+
+        if (data == NULL || off > (128 * 1024 * 1024)) {
+                printk(KERN_ERR "%s: data: %p off:%llx\n",
+                       netxen_nic_driver_name, data, off);
+                return 1;
+        }
+        off = netxen_nic_pci_set_window(adapter, off);
+        /* Corner case : Malicious user tried to break the driver by reading
+           last few bytes in ranges and tries to read further addresses.
+         */
+        if (!pci_base(adapter, off + size - 1) && pci_base(adapter, off)) {
+                printk(KERN_ERR "%s: Invalid access to memory address range"
+                       " 0x%llx - 0x%llx\n", netxen_nic_driver_name, off,
+                       off + size);
+                return 1;
+        }
+        addr = pci_base_offset(adapter, off);
+        DPRINTK(INFO, "writing data %llx to offset %llx\n",
+                *(unsigned long long *)data, off);
+        if (!addr) {
+                mem_base = pci_resource_start(adapter->ahw.pdev, 0);
+                mem_page = off & PAGE_MASK;
+                /* Map two pages whenever user tries to access addresses in two
+                   consecutive pages.
+                 */
+                if (mem_page != ((off + size - 1) & PAGE_MASK))
+                        mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
+                else
+                        mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
+                if (mem_ptr == 0UL) {
+                        return 1;
+                }
+                addr = mem_ptr;
+                addr += off & (PAGE_SIZE - 1);
+        }
+        switch (size) {
+        case 1:
+                writeb(*(u8 *) data, addr);
+                break;
+        case 2:
+                writew(*(u16 *) data, addr);
+                break;
+        case 4:
+                writel(*(u32 *) data, addr);
+                break;
+        case 8:
+                writeq(*(u64 *) data, addr);
+                break;
+        default:
+                DPRINTK(INFO,
+                        "writing data %lx to offset %llx, num words=%d\n",
+                        *(unsigned long *)data, off, (size >> 3));
+
+                netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
+                                            (size >> 3));
+                break;
+        }
+
+        if (mem_ptr)
+                iounmap(mem_ptr);
+        DPRINTK(INFO, "wrote %llx\n", *(unsigned long long *)data);
+
+        return ret;
+}
+
+int netxen_nic_pci_mem_read_ioctl(struct netxen_adapter *adapter,
+                                  u64 off, void *data, int size)
+{
+        void *addr;
+        int ret = 0;
+        u8 *mem_ptr = NULL;
+        unsigned long mem_base;
+        unsigned long mem_page;
+
+        if (data == NULL || off > (128 * 1024 * 1024)) {
+                printk(KERN_ERR "%s: data: %p off:%llx\n",
+                       netxen_nic_driver_name, data, off);
+                return 1;
+        }
+        off = netxen_nic_pci_set_window(adapter, off);
+        /* Corner case : Malicious user tried to break the driver by reading
+           last few bytes in ranges and tries to read further addresses.
+         */
+        if (!pci_base(adapter, off + size - 1) && pci_base(adapter, off)) {
+                printk(KERN_ERR "%s: Invalid access to memory address range"
+                       " 0x%llx - 0x%llx\n", netxen_nic_driver_name, off,
+                       off + size);
+                return 1;
+        }
+        addr = pci_base_offset(adapter, off);
+        if (!addr) {
+                mem_base = pci_resource_start(adapter->ahw.pdev, 0);
+                mem_page = off & PAGE_MASK;
+                /* Map two pages whenever user tries to access addresses in two
+                   consecutive pages.
+                 */
+                if (mem_page != ((off + size - 1) & PAGE_MASK))
+                        mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
+                else
+                        mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
+                if (mem_ptr == 0UL) {
+                        *(u8 *) data = 0;
+                        return 1;
+                }
+                addr = mem_ptr;
+                addr += off & (PAGE_SIZE - 1);
+        }
+        switch (size) {
+        case 1:
+                *(u8 *) data = readb(addr);
+                break;
+        case 2:
+                *(u16 *) data = readw(addr);
+                break;
+        case 4:
+                *(u32 *) data = readl(addr);
+                break;
+        case 8:
+                *(u64 *) data = readq(addr);
+                break;
+        default:
+                netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
+                                           (size >> 3));
+                break;
+        }
+
+        if (mem_ptr)
+                iounmap(mem_ptr);
+        DPRINTK(INFO, "read %llx\n", *(unsigned long long *)data);
+
+        return ret;
+}
diff --git a/drivers/net/netxen/netxen_nic_hw.h b/drivers/net/netxen/netxen_nic_hw.h
index 201a636b7ab8..0685633a9c1e 100644
--- a/drivers/net/netxen/netxen_nic_hw.h
+++ b/drivers/net/netxen/netxen_nic_hw.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -16,10 +16,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -83,8 +83,8 @@ struct netxen_adapter;
 #define NETXEN_PCI_MAPSIZE_BYTES  (NETXEN_PCI_MAPSIZE << 20)
 
 #define NETXEN_NIC_LOCKED_READ_REG(X, Y)        \
-        addr = pci_base_offset(adapter, (X));   \
-        *(u32 *)Y = readl(addr);
+        addr = pci_base_offset(adapter, X);     \
+        *(u32 *)Y = readl((void __iomem*) addr);
 
 struct netxen_port;
 void netxen_nic_set_link_parameters(struct netxen_port *port);
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index 0dca029bc3e5..290145ec08e7 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -1,25 +1,25 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
- *                            
+ *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *                                   
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -137,6 +137,8 @@ int netxen_init_firmware(struct netxen_adapter *adapter)
                 return err;
         }
         /* Window 1 call */
+        writel(MPORT_SINGLE_FUNCTION_MODE,
+               NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
         writel(PHAN_INITIALIZE_ACK,
                NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
 
@@ -184,15 +186,12 @@ void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
                         for (i = 0; i < num_rx_bufs; i++) {
                                 rx_buf->ref_handle = i;
                                 rx_buf->state = NETXEN_BUFFER_FREE;
-
                                 DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
                                         "%p\n", ctxid, i, rx_buf);
                                 rx_buf++;
                         }
                 }
         }
-        DPRINTK(INFO, "initialized buffers for %s and %s\n",
-                "adapter->free_cmd_buf_list", "adapter->free_rxbuf");
 }
 
 void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
@@ -212,37 +211,36 @@ void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
 
 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
 {
-        struct netxen_drvops *ops = adapter->ops;
         switch (adapter->ahw.board_type) {
         case NETXEN_NIC_GBE:
-                ops->enable_phy_interrupts =
+                adapter->enable_phy_interrupts =
                     netxen_niu_gbe_enable_phy_interrupts;
-                ops->disable_phy_interrupts =
+                adapter->disable_phy_interrupts =
                     netxen_niu_gbe_disable_phy_interrupts;
-                ops->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
-                ops->macaddr_set = netxen_niu_macaddr_set;
-                ops->set_mtu = netxen_nic_set_mtu_gb;
-                ops->set_promisc = netxen_niu_set_promiscuous_mode;
-                ops->unset_promisc = netxen_niu_set_promiscuous_mode;
-                ops->phy_read = netxen_niu_gbe_phy_read;
-                ops->phy_write = netxen_niu_gbe_phy_write;
-                ops->init_port = netxen_niu_gbe_init_port;
-                ops->init_niu = netxen_nic_init_niu_gb;
-                ops->stop_port = netxen_niu_disable_gbe_port;
+                adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
+                adapter->macaddr_set = netxen_niu_macaddr_set;
+                adapter->set_mtu = netxen_nic_set_mtu_gb;
+                adapter->set_promisc = netxen_niu_set_promiscuous_mode;
+                adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
+                adapter->phy_read = netxen_niu_gbe_phy_read;
+                adapter->phy_write = netxen_niu_gbe_phy_write;
+                adapter->init_port = netxen_niu_gbe_init_port;
+                adapter->init_niu = netxen_nic_init_niu_gb;
+                adapter->stop_port = netxen_niu_disable_gbe_port;
                 break;
 
         case NETXEN_NIC_XGBE:
-                ops->enable_phy_interrupts =
+                adapter->enable_phy_interrupts =
                     netxen_niu_xgbe_enable_phy_interrupts;
-                ops->disable_phy_interrupts =
+                adapter->disable_phy_interrupts =
                     netxen_niu_xgbe_disable_phy_interrupts;
-                ops->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
-                ops->macaddr_set = netxen_niu_xg_macaddr_set;
-                ops->set_mtu = netxen_nic_set_mtu_xgb;
-                ops->init_port = netxen_niu_xg_init_port;
-                ops->set_promisc = netxen_niu_xg_set_promiscuous_mode;
-                ops->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
-                ops->stop_port = netxen_niu_disable_xg_port;
+                adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
+                adapter->macaddr_set = netxen_niu_xg_macaddr_set;
+                adapter->set_mtu = netxen_nic_set_mtu_xgb;
+                adapter->init_port = netxen_niu_xg_init_port;
+                adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
+                adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
+                adapter->stop_port = netxen_niu_disable_xg_port;
                 break;
 
         default:
@@ -383,8 +381,8 @@ int netxen_rom_wip_poll(struct netxen_adapter *adapter)
         return 0;
 }
 
-static inline int do_rom_fast_write(struct netxen_adapter *adapter,
-                                    int addr, int data)
+static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
+                                    int data)
 {
         if (netxen_rom_wren(adapter)) {
                 return -1;
@@ -622,6 +620,43 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
         return 0;
 }
 
+int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
+{
+        uint64_t addr;
+        uint32_t hi;
+        uint32_t lo;
+
+        adapter->dummy_dma.addr =
+            pci_alloc_consistent(adapter->ahw.pdev,
+                                 NETXEN_HOST_DUMMY_DMA_SIZE,
+                                 &adapter->dummy_dma.phys_addr);
+        if (adapter->dummy_dma.addr == NULL) {
+                printk("%s: ERROR: Could not allocate dummy DMA memory\n",
+                       __FUNCTION__);
+                return -ENOMEM;
+        }
+
+        addr = (uint64_t) adapter->dummy_dma.phys_addr;
+        hi = (addr >> 32) & 0xffffffff;
+        lo = addr & 0xffffffff;
+
+        writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
+        writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
+
+        return 0;
+}
+
+void netxen_free_adapter_offload(struct netxen_adapter *adapter)
+{
+        if (adapter->dummy_dma.addr) {
+                pci_free_consistent(adapter->ahw.pdev,
+                                    NETXEN_HOST_DUMMY_DMA_SIZE,
+                                    adapter->dummy_dma.addr,
+                                    adapter->dummy_dma.phys_addr);
+                adapter->dummy_dma.addr = NULL;
+        }
+}
+
 void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
 {
         u32 val = 0;
@@ -656,7 +691,8 @@ int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
                 desc_head = recv_ctx->rcv_status_desc_head;
                 desc = &desc_head[consumer];
 
-                if (((le16_to_cpu(desc->owner)) & STATUS_OWNER_HOST))
+                if (((le16_to_cpu(netxen_get_sts_owner(desc)))
+                     & STATUS_OWNER_HOST))
                         return 1;
         }
 
@@ -710,12 +746,13 @@ static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
         return rv;
 }
 
-void netxen_watchdog_task(unsigned long v)
+void netxen_watchdog_task(struct work_struct *work)
 {
         int port_num;
         struct netxen_port *port;
         struct net_device *netdev;
-        struct netxen_adapter *adapter = (struct netxen_adapter *)v;
+        struct netxen_adapter *adapter =
+                container_of(work, struct netxen_adapter, watchdog_task);
 
         if (netxen_nic_check_temp(adapter))
                 return;
@@ -734,8 +771,8 @@ void netxen_watchdog_task(unsigned long v)
                         netif_wake_queue(netdev);
         }
 
-        if (adapter->ops->handle_phy_intr)
-                adapter->ops->handle_phy_intr(adapter);
+        if (adapter->handle_phy_intr)
+                adapter->handle_phy_intr(adapter);
         mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
 }
 
@@ -748,19 +785,19 @@ void
 netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
                    struct status_desc *desc)
 {
-        struct netxen_port *port = adapter->port[STATUS_DESC_PORT(desc)];
+        struct netxen_port *port = adapter->port[netxen_get_sts_port(desc)];
         struct pci_dev *pdev = port->pdev;
         struct net_device *netdev = port->netdev;
-        int index = le16_to_cpu(desc->reference_handle);
+        int index = le16_to_cpu(netxen_get_sts_refhandle(desc));
         struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
         struct netxen_rx_buffer *buffer;
         struct sk_buff *skb;
-        u32 length = le16_to_cpu(desc->total_length);
+        u32 length = le16_to_cpu(netxen_get_sts_totallength(desc));
         u32 desc_ctx;
         struct netxen_rcv_desc_ctx *rcv_desc;
         int ret;
 
-        desc_ctx = STATUS_DESC_TYPE(desc);
+        desc_ctx = netxen_get_sts_type(desc);
         if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
                 printk("%s: %s Bad Rcv descriptor ring\n",
                        netxen_nic_driver_name, netdev->name);
@@ -768,20 +805,49 @@ netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
         }
 
         rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
+        if (unlikely(index > rcv_desc->max_rx_desc_count)) {
+                DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
+                        index, rcv_desc->max_rx_desc_count);
+                return;
+        }
         buffer = &rcv_desc->rx_buf_arr[index];
+        if (desc_ctx == RCV_DESC_LRO_CTXID) {
+                buffer->lro_current_frags++;
+                if (netxen_get_sts_desc_lro_last_frag(desc)) {
+                        buffer->lro_expected_frags =
+                            netxen_get_sts_desc_lro_cnt(desc);
+                        buffer->lro_length = length;
+                }
+                if (buffer->lro_current_frags != buffer->lro_expected_frags) {
+                        if (buffer->lro_expected_frags != 0) {
+                                printk("LRO: (refhandle:%x) recv frag."
+                                       "wait for last. flags: %x expected:%d"
+                                       "have:%d\n", index,
+                                       netxen_get_sts_desc_lro_last_frag(desc),
+                                       buffer->lro_expected_frags,
+                                       buffer->lro_current_frags);
+                        }
+                        return;
+                }
+        }
 
         pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
                          PCI_DMA_FROMDEVICE);
 
         skb = (struct sk_buff *)buffer->skb;
 
-        if (likely(STATUS_DESC_STATUS(desc) == STATUS_CKSUM_OK)) {
+        if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
                 port->stats.csummed++;
                 skb->ip_summed = CHECKSUM_UNNECESSARY;
-        } else
-                skb->ip_summed = CHECKSUM_NONE;
+        }
         skb->dev = netdev;
-        skb_put(skb, length);
+        if (desc_ctx == RCV_DESC_LRO_CTXID) {
+                /* True length was only available on the last pkt */
+                skb_put(skb, buffer->lro_length);
+        } else {
+                skb_put(skb, length);
+        }
+
         skb->protocol = eth_type_trans(skb, netdev);
 
         ret = netif_receive_skb(skb);
@@ -827,6 +893,8 @@ netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
         adapter->stats.post_called++;
         buffer->skb = NULL;
         buffer->state = NETXEN_BUFFER_FREE;
+        buffer->lro_current_frags = 0;
+        buffer->lro_expected_frags = 0;
 
         port->stats.no_rcv++;
         port->stats.rxbytes += length;
@@ -839,6 +907,7 @@ u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
         struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
         struct status_desc *desc;       /* used to read status desc here */
         u32 consumer = recv_ctx->status_rx_consumer;
+        u32 producer = 0;
         int count = 0, ring;
 
         DPRINTK(INFO, "procesing receive\n");
@@ -850,18 +919,22 @@ u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
          */
         while (count < max) {
                 desc = &desc_head[consumer];
-                if (!((le16_to_cpu(desc->owner)) & STATUS_OWNER_HOST)) {
-                        DPRINTK(ERR, "desc %p ownedby %x\n", desc, desc->owner);
+                if (!
+                    (le16_to_cpu(netxen_get_sts_owner(desc)) &
+                     STATUS_OWNER_HOST)) {
+                        DPRINTK(ERR, "desc %p ownedby %x\n", desc,
+                                netxen_get_sts_owner(desc));
                         break;
                 }
                 netxen_process_rcv(adapter, ctxid, desc);
-                desc->owner = STATUS_OWNER_PHANTOM;
+                netxen_clear_sts_owner(desc);
+                netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
                 consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
                 count++;
         }
         if (count) {
                 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
-                        netxen_post_rx_buffers(adapter, ctxid, ring);
+                        netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
                 }
         }
 
@@ -869,6 +942,7 @@ u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
         if (count) {
                 adapter->stats.process_rcv++;
                 recv_ctx->status_rx_consumer = consumer;
+                recv_ctx->status_rx_producer = producer;
 
                 /* Window = 1 */
                 writel(consumer,
@@ -881,12 +955,13 @@ u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
 }
 
 /* Process Command status ring */
-void netxen_process_cmd_ring(unsigned long data)
+int netxen_process_cmd_ring(unsigned long data)
 {
         u32 last_consumer;
         u32 consumer;
         struct netxen_adapter *adapter = (struct netxen_adapter *)data;
-        int count = 0;
+        int count1 = 0;
+        int count2 = 0;
         struct netxen_cmd_buffer *buffer;
         struct netxen_port *port;       /* port #1 */
         struct netxen_port *nport;
@@ -895,6 +970,7 @@ void netxen_process_cmd_ring(unsigned long data)
         u32 i;
         struct sk_buff *skb = NULL;
         int p;
+        int done;
 
         spin_lock(&adapter->tx_lock);
         last_consumer = adapter->last_cmd_consumer;
@@ -904,14 +980,13 @@ void netxen_process_cmd_ring(unsigned long data)
          * number as part of the descriptor. This way we will be able to get
          * the netdev which is associated with that device.
          */
-        consumer =
-            readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMD_CONSUMER_OFFSET));
 
+        consumer = *(adapter->cmd_consumer);
         if (last_consumer == consumer) {        /* Ring is empty    */
                 DPRINTK(INFO, "last_consumer %d == consumer %d\n",
                         last_consumer, consumer);
                 spin_unlock(&adapter->tx_lock);
-                return;
+                return 1;
         }
 
         adapter->proc_cmd_buf_counter++;
@@ -922,7 +997,7 @@ void netxen_process_cmd_ring(unsigned long data)
          */
         spin_unlock(&adapter->tx_lock);
 
-        while ((last_consumer != consumer) && (count < MAX_STATUS_HANDLE)) {
+        while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
                 buffer = &adapter->cmd_buf_arr[last_consumer];
                 port = adapter->port[buffer->port];
                 pdev = port->pdev;
@@ -948,24 +1023,25 @@ void netxen_process_cmd_ring(unsigned long data)
                              && netif_carrier_ok(port->netdev))
                     && ((jiffies - port->netdev->trans_start) >
                         port->netdev->watchdog_timeo)) {
-                        schedule_work(&port->adapter->tx_timeout_task);
+                        SCHEDULE_WORK(port->adapter->tx_timeout_task
+                                      + port->portnum);
                 }
 
                 last_consumer = get_next_index(last_consumer,
                                                adapter->max_tx_desc_count);
-                count++;
+                count1++;
         }
-        adapter->stats.noxmitdone += count;
+        adapter->stats.noxmitdone += count1;
 
-        count = 0;
+        count2 = 0;
         spin_lock(&adapter->tx_lock);
         if ((--adapter->proc_cmd_buf_counter) == 0) {
                 adapter->last_cmd_consumer = last_consumer;
                 while ((adapter->last_cmd_consumer != consumer)
-                       && (count < MAX_STATUS_HANDLE)) {
+                       && (count2 < MAX_STATUS_HANDLE)) {
                         buffer =
                             &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
-                        count++;
+                        count2++;
                         if (buffer->skb)
                                 break;
                         else
@@ -974,7 +1050,7 @@ void netxen_process_cmd_ring(unsigned long data)
                                                    adapter->max_tx_desc_count);
                 }
         }
-        if (count) {
+        if (count1 || count2) {
                 for (p = 0; p < adapter->ahw.max_ports; p++) {
                         nport = adapter->port[p];
                         if (netif_queue_stopped(nport->netdev)
@@ -984,10 +1060,30 @@ void netxen_process_cmd_ring(unsigned long data)
                         }
                 }
         }
+        /*
+         * If everything is freed up to consumer then check if the ring is full
+         * If the ring is full then check if more needs to be freed and
+         * schedule the call back again.
+         *
+         * This happens when there are 2 CPUs. One could be freeing and the
+         * other filling it. If the ring is full when we get out of here and
+         * the card has already interrupted the host then the host can miss the
+         * interrupt.
+         *
+         * There is still a possible race condition and the host could miss an
+         * interrupt. The card has to take care of this.
+         */
+        if (adapter->last_cmd_consumer == consumer &&
+            (((adapter->cmd_producer + 1) %
+              adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
+                consumer = *(adapter->cmd_consumer);
+        }
+        done = (adapter->last_cmd_consumer == consumer);
 
         spin_unlock(&adapter->tx_lock);
         DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
                 __FUNCTION__);
+        return (done);
 }
 
 /*
@@ -999,17 +1095,16 @@ void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
         struct sk_buff *skb;
         struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
         struct netxen_rcv_desc_ctx *rcv_desc = NULL;
-        struct netxen_recv_crb *crbarea = &recv_crb_registers[ctx];
-        struct netxen_rcv_desc_crb *rcv_desc_crb = NULL;
-        u32 producer;
+        uint producer;
         struct rcv_desc *pdesc;
         struct netxen_rx_buffer *buffer;
         int count = 0;
         int index = 0;
+        netxen_ctx_msg msg = 0;
+        dma_addr_t dma;
 
         adapter->stats.post_called++;
         rcv_desc = &recv_ctx->rcv_desc[ringid];
-        rcv_desc_crb = &crbarea->rcv_desc_crb[ringid];
 
         producer = rcv_desc->producer;
         index = rcv_desc->begin_alloc;
@@ -1019,6 +1114,7 @@ void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
                 skb = dev_alloc_skb(rcv_desc->skb_size);
                 if (unlikely(!skb)) {
                         /*
+                         * TODO
                          * We need to schedule the posting of buffers to the pegs.
                          */
                         rcv_desc->begin_alloc = index;
@@ -1026,9 +1122,105 @@ void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
                                 " allocated only %d buffers\n", count);
                         break;
                 }
+
                 count++;        /* now there should be no failure */
                 pdesc = &rcv_desc->desc_head[producer];
-                skb_reserve(skb, NET_IP_ALIGN);
+
+#if defined(XGB_DEBUG)
+                *(unsigned long *)(skb->head) = 0xc0debabe;
+                if (skb_is_nonlinear(skb)) {
+                        printk("Allocated SKB @%p is nonlinear\n");
+                }
+#endif
+                skb_reserve(skb, 2);
+                /* This will be setup when we receive the
+                 * buffer after it has been filled  FSL  TBD TBD
+                 * skb->dev = netdev;
+                 */
+                dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
+                                     PCI_DMA_FROMDEVICE);
+                pdesc->addr_buffer = dma;
+                buffer->skb = skb;
+                buffer->state = NETXEN_BUFFER_BUSY;
+                buffer->dma = dma;
+                /* make a rcv descriptor  */
+                pdesc->reference_handle = buffer->ref_handle;
+                pdesc->buffer_length = rcv_desc->dma_size;
+                DPRINTK(INFO, "done writing descripter\n");
+                producer =
+                    get_next_index(producer, rcv_desc->max_rx_desc_count);
+                index = get_next_index(index, rcv_desc->max_rx_desc_count);
+                buffer = &rcv_desc->rx_buf_arr[index];
+        }
+        /* if we did allocate buffers, then write the count to Phantom */
+        if (count) {
+                rcv_desc->begin_alloc = index;
+                rcv_desc->rcv_pending += count;
+                adapter->stats.lastposted = count;
+                adapter->stats.posted += count;
+                rcv_desc->producer = producer;
+                if (rcv_desc->rcv_free >= 32) {
+                        rcv_desc->rcv_free = 0;
+                        /* Window = 1 */
+                        writel((producer - 1) &
+                               (rcv_desc->max_rx_desc_count - 1),
+                               NETXEN_CRB_NORMALIZE(adapter,
+                                                    recv_crb_registers[0].
+                                                    rcv_desc_crb[ringid].
+                                                    crb_rcv_producer_offset));
+                        /*
+                         * Write a doorbell msg to tell phanmon of change in
+                         * receive ring producer
+                         */
+                        netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
+                        netxen_set_msg_privid(msg);
+                        netxen_set_msg_count(msg,
+                                             ((producer -
+                                               1) & (rcv_desc->
+                                                     max_rx_desc_count - 1)));
+                        netxen_set_msg_ctxid(msg, 0);
+                        netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
+                        writel(msg,
+                               DB_NORMALIZE(adapter,
+                                            NETXEN_RCV_PRODUCER_OFFSET));
+                }
+        }
+}
+
+void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
+                                 uint32_t ringid)
+{
+        struct pci_dev *pdev = adapter->ahw.pdev;
+        struct sk_buff *skb;
+        struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
+        struct netxen_rcv_desc_ctx *rcv_desc = NULL;
+        u32 producer;
+        struct rcv_desc *pdesc;
+        struct netxen_rx_buffer *buffer;
+        int count = 0;
+        int index = 0;
+
+        adapter->stats.post_called++;
+        rcv_desc = &recv_ctx->rcv_desc[ringid];
+
+        producer = rcv_desc->producer;
+        index = rcv_desc->begin_alloc;
+        buffer = &rcv_desc->rx_buf_arr[index];
+        /* We can start writing rx descriptors into the phantom memory. */
+        while (buffer->state == NETXEN_BUFFER_FREE) {
+                skb = dev_alloc_skb(rcv_desc->skb_size);
+                if (unlikely(!skb)) {
+                        /*
+                         * We need to schedule the posting of buffers to the pegs.
+                         */
+                        rcv_desc->begin_alloc = index;
+                        DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
+                                " allocated only %d buffers\n", count);
+                        break;
+                }
+                count++;        /* now there should be no failure */
+                pdesc = &rcv_desc->desc_head[producer];
+                skb_reserve(skb, 2);
                 /* 
                  * This will be setup when we receive the
                  * buffer after it has been filled
@@ -1039,6 +1231,7 @@ void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
                 buffer->dma = pci_map_single(pdev, skb->data,
                                              rcv_desc->dma_size,
                                              PCI_DMA_FROMDEVICE);
+
                 /* make a rcv descriptor  */
                 pdesc->reference_handle = le16_to_cpu(buffer->ref_handle);
                 pdesc->buffer_length = le16_to_cpu(rcv_desc->dma_size);
@@ -1063,7 +1256,8 @@ void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
                         writel((producer - 1) &
                                (rcv_desc->max_rx_desc_count - 1),
                                NETXEN_CRB_NORMALIZE(adapter,
-                                                    rcv_desc_crb->
+                                                    recv_crb_registers[0].
+                                                    rcv_desc_crb[ringid].
                                                     crb_rcv_producer_offset));
                         wmb();
                 }
@@ -1196,8 +1390,8 @@ netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
 
         switch (data.cmd) {
         case netxen_nic_cmd_pci_read:
-                if ((retval = netxen_nic_hw_read_wx(adapter, data.off,
-                                                    &(data.u), data.size)))
+                if ((retval = netxen_nic_hw_read_ioctl(adapter, data.off,
+                                                       &(data.u), data.size)))
                         goto error_out;
                 if (copy_to_user
                     ((void __user *)&(up_data->u), &(data.u), data.size)) {
@@ -1210,8 +1404,35 @@ netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
                 break;
 
         case netxen_nic_cmd_pci_write:
-                data.rv = netxen_nic_hw_write_wx(adapter, data.off, &(data.u),
-                                                 data.size);
+                if ((retval = netxen_nic_hw_write_ioctl(adapter, data.off,
+                                                        &(data.u), data.size)))
+                        goto error_out;
+                data.rv = 0;
+                break;
+
+        case netxen_nic_cmd_pci_mem_read:
+                if (netxen_nic_pci_mem_read_ioctl(adapter, data.off, &(data.u),
+                                                  data.size)) {
+                        DPRINTK(ERR, "Failed to read the data.\n");
+                        retval = -EFAULT;
+                        goto error_out;
+                }
+                if (copy_to_user
+                    ((void __user *)&(up_data->u), &(data.u), data.size)) {
+                        DPRINTK(ERR, "bad copy to userland: %d\n",
+                                (int)sizeof(data));
+                        retval = -EFAULT;
+                        goto error_out;
+                }
+                data.rv = 0;
+                break;
+
+        case netxen_nic_cmd_pci_mem_write:
+                if ((retval = netxen_nic_pci_mem_write_ioctl(adapter, data.off,
+                                                             &(data.u),
+                                                             data.size)))
+                        goto error_out;
+                data.rv = 0;
                 break;
 
         case netxen_nic_cmd_pci_config_read:
@@ -1296,7 +1517,7 @@ netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
                 retval = -EOPNOTSUPP;
                 goto error_out;
         }
-        put_user(data.rv, (u16 __user *) (&(up_data->rv)));
+        put_user(data.rv, (&(up_data->rv)));
         DPRINTK(INFO, "done ioctl for %p well.\n", adapter);
 
       error_out:
diff --git a/drivers/net/netxen/netxen_nic_ioctl.h b/drivers/net/netxen/netxen_nic_ioctl.h
index 23e53adbf123..1221fa527552 100644
--- a/drivers/net/netxen/netxen_nic_ioctl.h
+++ b/drivers/net/netxen/netxen_nic_ioctl.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -16,10 +16,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -36,7 +36,7 @@
 #define NETXEN_NIC_CMD          (NETXEN_CMD_START + 1)
 #define NETXEN_NIC_NAME         (NETXEN_CMD_START + 2)
 #define NETXEN_NIC_NAME_LEN     16
-#define NETXEN_NIC_NAME_RSP     "NETXEN"
+#define NETXEN_NIC_NAME_RSP     "NETXEN-UNM"
 
 typedef enum {
         netxen_nic_cmd_none = 0,
diff --git a/drivers/net/netxen/netxen_nic_isr.c b/drivers/net/netxen/netxen_nic_isr.c
index ae180fee8008..1b45f50fa6aa 100644
--- a/drivers/net/netxen/netxen_nic_isr.c
+++ b/drivers/net/netxen/netxen_nic_isr.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -16,10 +16,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -68,8 +68,7 @@ struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev)
 void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 portno,
                                  u32 link)
 {
-        struct netxen_port *pport = adapter->port[portno];
-        struct net_device *netdev = pport->netdev;
+        struct net_device *netdev = (adapter->port[portno])->netdev;
 
         if (link)
                 netif_carrier_on(netdev);
@@ -84,46 +83,41 @@ void netxen_handle_port_int(struct netxen_adapter *adapter, u32 portno,
         struct netxen_port *port;
 
         /*  This should clear the interrupt source */
-        if (adapter->ops->phy_read)
-                adapter->ops->phy_read(adapter, portno,
-                                       NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
-                                       &int_src);
+        if (adapter->phy_read)
+                adapter->phy_read(adapter, portno,
+                                  NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
+                                  &int_src);
         if (int_src == 0) {
                 DPRINTK(INFO, "No phy interrupts for port #%d\n", portno);
                 return;
         }
-        if (adapter->ops->disable_phy_interrupts)
-                adapter->ops->disable_phy_interrupts(adapter, portno);
+        if (adapter->disable_phy_interrupts)
+                adapter->disable_phy_interrupts(adapter, portno);
 
         port = adapter->port[portno];
 
         if (netxen_get_phy_int_jabber(int_src))
-                DPRINTK(INFO, "NetXen: %s Jabber interrupt \n",
-                        port->netdev->name);
+                DPRINTK(INFO, "Jabber interrupt \n");
 
         if (netxen_get_phy_int_polarity_changed(int_src))
-                DPRINTK(INFO, "NetXen: %s POLARITY CHANGED int \n",
-                        port->netdev->name);
+                DPRINTK(INFO, "POLARITY CHANGED int \n");
 
         if (netxen_get_phy_int_energy_detect(int_src))
-                DPRINTK(INFO, "NetXen: %s ENERGY DETECT INT \n",
-                        port->netdev->name);
+                DPRINTK(INFO, "ENERGY DETECT INT \n");
 
         if (netxen_get_phy_int_downshift(int_src))
-                DPRINTK(INFO, "NetXen: %s DOWNSHIFT INT \n",
-                        port->netdev->name);
+                DPRINTK(INFO, "DOWNSHIFT INT \n");
         /* write it down later.. */
         if ((netxen_get_phy_int_speed_changed(int_src))
             || (netxen_get_phy_int_link_status_changed(int_src))) {
                 __le32 status;
 
-                DPRINTK(INFO, "NetXen: %s SPEED CHANGED OR"
-                        " LINK STATUS CHANGED \n", port->netdev->name);
+                DPRINTK(INFO, "SPEED CHANGED OR LINK STATUS CHANGED \n");
 
-                if (adapter->ops->phy_read
-                    && adapter->ops->phy_read(adapter, portno,
-                                              NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
-                                              &status) == 0) {
+                if (adapter->phy_read
+                    && adapter->phy_read(adapter, portno,
+                                         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+                                         &status) == 0) {
                         if (netxen_get_phy_int_link_status_changed(int_src)) {
                                 if (netxen_get_phy_link(status)) {
                                         netxen_niu_gbe_init_port(adapter,
@@ -143,8 +137,8 @@ void netxen_handle_port_int(struct netxen_adapter *adapter, u32 portno,
                         }
                 }
         }
-        if (adapter->ops->enable_phy_interrupts)
-                adapter->ops->enable_phy_interrupts(adapter, portno);
+        if (adapter->enable_phy_interrupts)
+                adapter->enable_phy_interrupts(adapter, portno);
 }
 
 void netxen_nic_isr_other(struct netxen_adapter *adapter)
@@ -159,8 +153,7 @@ void netxen_nic_isr_other(struct netxen_adapter *adapter)
 
         qg_linksup = adapter->ahw.qg_linksup;
         adapter->ahw.qg_linksup = val;
-        DPRINTK(1, INFO, "%s: link update 0x%08x\n", netxen_nic_driver_name,
-                val);
+        DPRINTK(INFO, "link update 0x%08x\n", val);
         for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++) {
                 linkup = val & 1;
                 if (linkup != (qg_linksup & 1)) {
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index 1cb662d5bd76..913e8147114f 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -1,25 +1,25 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
- *                            
+ *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *                                   
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -32,6 +32,7 @@
  */
 
 #include <linux/vmalloc.h>
+#include <linux/highmem.h>
 #include "netxen_nic_hw.h"
 
 #include "netxen_nic.h"
@@ -48,14 +49,21 @@ MODULE_DESCRIPTION("NetXen Multi port (1/10) Gigabit Network Driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(NETXEN_NIC_LINUX_VERSIONID);
 
-char netxen_nic_driver_name[] = "netxen";
+char netxen_nic_driver_name[] = "netxen-nic";
 static char netxen_nic_driver_string[] = "NetXen Network Driver version "
     NETXEN_NIC_LINUX_VERSIONID;
 
+struct netxen_adapter *g_adapter = NULL;
+
 #define NETXEN_NETDEV_WEIGHT 120
 #define NETXEN_ADAPTER_UP_MAGIC 777
 #define NETXEN_NIC_PEG_TUNE 0
 
+u8 nx_p2_id = NX_P2_C0;
+
+#define DMA_32BIT_MASK  0x00000000ffffffffULL
+#define DMA_35BIT_MASK  0x00000007ffffffffULL
+
 /* Local functions to NetXen NIC driver */
 static int __devinit netxen_nic_probe(struct pci_dev *pdev,
                                       const struct pci_device_id *ent);
@@ -64,7 +72,7 @@ static int netxen_nic_open(struct net_device *netdev);
 static int netxen_nic_close(struct net_device *netdev);
 static int netxen_nic_xmit_frame(struct sk_buff *, struct net_device *);
 static void netxen_tx_timeout(struct net_device *netdev);
-static void netxen_tx_timeout_task(struct net_device *netdev);
+static void netxen_tx_timeout_task(struct work_struct *work);
 static void netxen_watchdog(unsigned long);
 static int netxen_handle_int(struct netxen_adapter *, struct net_device *);
 static int netxen_nic_ioctl(struct net_device *netdev,
@@ -87,6 +95,9 @@ static struct pci_device_id netxen_pci_tbl[] __devinitdata = {
 
 MODULE_DEVICE_TABLE(pci, netxen_pci_tbl);
 
+struct workqueue_struct *netxen_workq;
+static void netxen_watchdog(unsigned long);
+
 /*
  * netxen_nic_probe()
  *
@@ -105,20 +116,28 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         struct net_device *netdev = NULL;
         struct netxen_adapter *adapter = NULL;
         struct netxen_port *port = NULL;
-        u8 *mem_ptr0 = NULL;
-        u8 *mem_ptr1 = NULL;
-        u8 *mem_ptr2 = NULL;
+        void __iomem *mem_ptr0 = NULL;
+        void __iomem *mem_ptr1 = NULL;
+        void __iomem *mem_ptr2 = NULL;
 
-        unsigned long mem_base, mem_len;
+        u8 *db_ptr = NULL;
+        unsigned long mem_base, mem_len, db_base, db_len;
         int pci_using_dac, i, err;
         int ring;
         struct netxen_recv_context *recv_ctx = NULL;
         struct netxen_rcv_desc_ctx *rcv_desc = NULL;
         struct netxen_cmd_buffer *cmd_buf_arr = NULL;
         u64 mac_addr[FLASH_NUM_PORTS + 1];
-        int valid_mac;
+        int valid_mac = 0;
+        static int netxen_cards_found = 0;
 
         printk(KERN_INFO "%s \n", netxen_nic_driver_string);
+        /* In current scheme, we use only PCI function 0 */
+        if (PCI_FUNC(pdev->devfn) != 0) {
+                DPRINTK(ERR, "NetXen function %d will not be enabled.\n",
+                        PCI_FUNC(pdev->devfn));
+                return -ENODEV;
+        }
         if ((err = pci_enable_device(pdev)))
                 return err;
         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
@@ -130,10 +149,12 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 goto err_out_disable_pdev;
 
         pci_set_master(pdev);
-        if ((pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) &&
-            (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) == 0))
+        pci_read_config_byte(pdev, PCI_REVISION_ID, &nx_p2_id);
+        if (nx_p2_id == NX_P2_C1 &&
+            (pci_set_dma_mask(pdev, DMA_35BIT_MASK) == 0) &&
+            (pci_set_consistent_dma_mask(pdev, DMA_35BIT_MASK) == 0)) {
                 pci_using_dac = 1;
-        else {
+        } else {
                 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
                     (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)))
                         goto err_out_free_res;
@@ -153,21 +174,34 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
             ioremap(mem_base + THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE);
 
         if ((mem_ptr0 == 0UL) || (mem_ptr1 == 0UL) || (mem_ptr2 == 0UL)) {
-                DPRINTK(1, ERR,
+                DPRINTK(ERR,
                         "Cannot remap adapter memory aborting.:"
                         "0 -> %p, 1 -> %p, 2 -> %p\n",
                         mem_ptr0, mem_ptr1, mem_ptr2);
 
                 err = -EIO;
-                if (mem_ptr0)
-                        iounmap(mem_ptr0);
-                if (mem_ptr1)
-                        iounmap(mem_ptr1);
-                if (mem_ptr2)
-                        iounmap(mem_ptr2);
-
-                goto err_out_free_res;
+                goto err_out_iounmap;
+        }
+        db_base = pci_resource_start(pdev, 4);  /* doorbell is on bar 4 */
+        db_len = pci_resource_len(pdev, 4);
+
+        if (db_len == 0) {
+                printk(KERN_ERR "%s: doorbell is disabled\n",
+                       netxen_nic_driver_name);
+                err = -EIO;
+                goto err_out_iounmap;
+        }
+        DPRINTK(INFO, "doorbell ioremap from %lx a size of %lx\n", db_base,
+                db_len);
+
+        db_ptr = ioremap(db_base, NETXEN_DB_MAPSIZE_BYTES);
+        if (db_ptr == 0UL) {
+                printk(KERN_ERR "%s: Failed to allocate doorbell map.",
+                       netxen_nic_driver_name);
+                err = -EIO;
+                goto err_out_iounmap;
         }
+        DPRINTK(INFO, "doorbell ioremaped at %p\n", db_ptr);
 
 /*
  *      Allocate a adapter structure which will manage all the initialization
@@ -183,17 +217,24 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                        netxen_nic_driver_name,
                        (int)sizeof(struct netxen_adapter));
                 err = -ENOMEM;
-                goto err_out_iounmap;
+                goto err_out_dbunmap;
         }
 
+        if (netxen_cards_found == 0) {
+                g_adapter = adapter;
+        }
         adapter->max_tx_desc_count = MAX_CMD_DESCRIPTORS;
         adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS;
         adapter->max_jumbo_rx_desc_count = MAX_JUMBO_RCV_DESCRIPTORS;
+        adapter->max_lro_rx_desc_count = MAX_LRO_RCV_DESCRIPTORS;
 
         pci_set_drvdata(pdev, adapter);
 
         cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
         if (cmd_buf_arr == NULL) {
+                printk(KERN_ERR
+                       "%s: Could not allocate cmd_buf_arr memory:%d\n",
+                       netxen_nic_driver_name, (int)TX_RINGSIZE);
                 err = -ENOMEM;
                 goto err_out_free_adapter;
         }
@@ -220,11 +261,23 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                                 rcv_desc->skb_size = MAX_RX_JUMBO_BUFFER_LENGTH;
                                 break;
 
+                        case RCV_RING_LRO:
+                                rcv_desc->max_rx_desc_count =
+                                    adapter->max_lro_rx_desc_count;
+                                rcv_desc->flags = RCV_DESC_LRO;
+                                rcv_desc->dma_size = RX_LRO_DMA_MAP_LEN;
+                                rcv_desc->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
+                                break;
+
                         }
                         rcv_desc->rx_buf_arr = (struct netxen_rx_buffer *)
                             vmalloc(RCV_BUFFSIZE);
 
                         if (rcv_desc->rx_buf_arr == NULL) {
+                                printk(KERN_ERR "%s: Could not allocate"
+                                       "rcv_desc->rx_buf_arr memory:%d\n",
+                                       netxen_nic_driver_name,
+                                       (int)RCV_BUFFSIZE);
                                 err = -ENOMEM;
                                 goto err_out_free_rx_buffer;
                         }
@@ -233,30 +286,21 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         }
 
-        adapter->ops = kzalloc(sizeof(struct netxen_drvops), GFP_KERNEL);
-        if (adapter->ops == NULL) {
-                printk(KERN_ERR
-                       "%s: Could not allocate memory for adapter->ops:%d\n",
-                       netxen_nic_driver_name,
-                       (int)sizeof(struct netxen_adapter));
-                err = -ENOMEM;
-                goto err_out_free_rx_buffer;
-        }
-
         adapter->cmd_buf_arr = cmd_buf_arr;
         adapter->ahw.pci_base0 = mem_ptr0;
         adapter->ahw.pci_base1 = mem_ptr1;
         adapter->ahw.pci_base2 = mem_ptr2;
+        adapter->ahw.db_base = db_ptr;
+        adapter->ahw.db_len = db_len;
         spin_lock_init(&adapter->tx_lock);
         spin_lock_init(&adapter->lock);
+        netxen_initialize_adapter_sw(adapter);  /* initialize the buffers in adapter */
 #ifdef CONFIG_IA64
         netxen_pinit_from_rom(adapter, 0);
         udelay(500);
         netxen_load_firmware(adapter);
 #endif
 
-        /* initialize the buffers in adapter */
-        netxen_initialize_adapter_sw(adapter);
         /*
          * Set the CRB window to invalid. If any register in window 0 is
          * accessed it should set the window to 0 and then reset it to 1.
@@ -274,11 +318,10 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         adapter->ahw.xg_linkup = 0;
         adapter->watchdog_timer.function = &netxen_watchdog;
         adapter->watchdog_timer.data = (unsigned long)adapter;
-        INIT_WORK(&adapter->watchdog_task,
-                  (void (*)(void *))netxen_watchdog_task, adapter);
+        INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task);
         adapter->ahw.pdev = pdev;
         adapter->proc_cmd_buf_counter = 0;
-        pci_read_config_byte(pdev, PCI_REVISION_ID, &adapter->ahw.revision_id);
+        adapter->ahw.revision_id = nx_p2_id;
 
         if (pci_enable_msi(pdev)) {
                 adapter->flags &= ~NETXEN_NIC_MSI_ENABLED;
@@ -300,6 +343,12 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_CMD_CONSUMER_OFFSET));
         writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
 
+        /* do this before waking up pegs so that we have valid dummy dma addr */
+        err = netxen_initialize_adapter_offload(adapter);
+        if (err) {
+                goto err_out_free_dev;
+        }
+
         /* Unlock the HW, prompting the boot sequence */
         writel(1,
                NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE));
@@ -308,6 +357,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
 
         /* initialize the all the ports */
+        adapter->active_ports = 0;
 
         for (i = 0; i < adapter->ahw.max_ports; i++) {
                 netdev = alloc_etherdev(sizeof(struct netxen_port));
@@ -373,14 +423,13 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                                        netdev->dev_addr[4],
                                        netdev->dev_addr[5]);
                         } else {
-                                if (adapter->ops->macaddr_set)
-                                        adapter->ops->macaddr_set(port,
-                                                                  netdev->
-                                                                  dev_addr);
+                                if (adapter->macaddr_set)
+                                        adapter->macaddr_set(port,
+                                                             netdev->dev_addr);
                         }
                 }
-                INIT_WORK(&adapter->tx_timeout_task,
-                          (void (*)(void *))netxen_tx_timeout_task, netdev);
+                adapter->netdev = netdev;
+                INIT_WORK(&adapter->tx_timeout_task, netxen_tx_timeout_task);
                 netif_carrier_off(netdev);
                 netif_stop_queue(netdev);
 
@@ -392,7 +441,6 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                         goto err_out_free_dev;
                 }
                 adapter->port_count++;
-                adapter->active_ports = 0;
                 adapter->port[i] = port;
         }
 
@@ -413,6 +461,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 break;
         }
 
+        adapter->number = netxen_cards_found;
         adapter->driver_mismatch = 0;
 
         return 0;
@@ -427,7 +476,8 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                         free_netdev(port->netdev);
                 }
         }
-        kfree(adapter->ops);
+
+        netxen_free_adapter_offload(adapter);
 
       err_out_free_rx_buffer:
         for (i = 0; i < MAX_RCV_CTX; ++i) {
@@ -440,19 +490,23 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                         }
                 }
         }
-
         vfree(cmd_buf_arr);
 
-        kfree(adapter->port);
-
       err_out_free_adapter:
         pci_set_drvdata(pdev, NULL);
         kfree(adapter);
 
+      err_out_dbunmap:
+        if (db_ptr)
+                iounmap(db_ptr);
+
       err_out_iounmap:
-        iounmap(mem_ptr0);
-        iounmap(mem_ptr1);
-        iounmap(mem_ptr2);
+        if (mem_ptr0)
+                iounmap(mem_ptr0);
+        if (mem_ptr1)
+                iounmap(mem_ptr1);
+        if (mem_ptr2)
+                iounmap(mem_ptr2);
 
       err_out_free_res:
         pci_release_regions(pdev);
@@ -477,12 +531,8 @@ static void __devexit netxen_nic_remove(struct pci_dev *pdev)
 
         netxen_nic_stop_all_ports(adapter);
         /* leave the hw in the same state as reboot */
-        netxen_pinit_from_rom(adapter, 0);
-        udelay(500);
         netxen_load_firmware(adapter);
-
-        if ((adapter->flags & NETXEN_NIC_MSI_ENABLED))
-                netxen_nic_disable_int(adapter);
+        netxen_free_adapter_offload(adapter);
 
         udelay(500);            /* Delay for a while to drain the DMA engines */
         for (i = 0; i < adapter->port_count; i++) {
@@ -499,6 +549,7 @@ static void __devexit netxen_nic_remove(struct pci_dev *pdev)
         if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC)
                 netxen_free_hw_resources(adapter);
 
+        iounmap(adapter->ahw.db_base);
         iounmap(adapter->ahw.pci_base0);
         iounmap(adapter->ahw.pci_base1);
         iounmap(adapter->ahw.pci_base2);
@@ -525,7 +576,6 @@ static void __devexit netxen_nic_remove(struct pci_dev *pdev)
         }
 
         vfree(adapter->cmd_buf_arr);
-        kfree(adapter->ops);
         kfree(adapter);
 }
 
@@ -547,6 +597,8 @@ static int netxen_nic_open(struct net_device *netdev)
                         return -EIO;
                 }
                 netxen_nic_flash_print(adapter);
+                if (adapter->init_niu)
+                        adapter->init_niu(adapter);
 
                 /* setup all the resources for the Phantom... */
                 /* this include the descriptors for rcv, tx, and status */
@@ -557,32 +609,31 @@ static int netxen_nic_open(struct net_device *netdev)
                                err);
                         return err;
                 }
-                if (adapter->ops->init_port
-                    && adapter->ops->init_port(adapter, port->portnum) != 0) {
+                if (adapter->init_port
+                    && adapter->init_port(adapter, port->portnum) != 0) {
                         printk(KERN_ERR "%s: Failed to initialize port %d\n",
                                netxen_nic_driver_name, port->portnum);
                         netxen_free_hw_resources(adapter);
                         return -EIO;
                 }
-                if (adapter->ops->init_niu)
-                        adapter->ops->init_niu(adapter);
                 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
                         for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++)
                                 netxen_post_rx_buffers(adapter, ctx, ring);
                 }
-                adapter->is_up = NETXEN_ADAPTER_UP_MAGIC;
-        }
-        adapter->active_ports++;
-        if (adapter->active_ports == 1) {
+                adapter->irq = adapter->ahw.pdev->irq;
                 err = request_irq(adapter->ahw.pdev->irq, &netxen_intr,
                                   SA_SHIRQ | SA_SAMPLE_RANDOM, netdev->name,
                                   adapter);
                 if (err) {
                         printk(KERN_ERR "request_irq failed with: %d\n", err);
-                        adapter->active_ports--;
+                        netxen_free_hw_resources(adapter);
                         return err;
                 }
-                adapter->irq = adapter->ahw.pdev->irq;
+
+                adapter->is_up = NETXEN_ADAPTER_UP_MAGIC;
+        }
+        adapter->active_ports++;
+        if (adapter->active_ports == 1) {
                 if (!adapter->driver_mismatch)
                         mod_timer(&adapter->watchdog_timer, jiffies);
 
@@ -591,11 +642,14 @@ static int netxen_nic_open(struct net_device *netdev)
 
         /* Done here again so that even if phantom sw overwrote it,
          * we set it */
-        if (adapter->ops->macaddr_set)
-                adapter->ops->macaddr_set(port, netdev->dev_addr);
+        if (adapter->macaddr_set)
+                adapter->macaddr_set(port, netdev->dev_addr);
         netxen_nic_set_link_parameters(port);
 
         netxen_nic_set_multi(netdev);
+        if (adapter->set_mtu)
+                adapter->set_mtu(port, netdev->mtu);
+
         if (!adapter->driver_mismatch)
                 netif_start_queue(netdev);
 
@@ -648,6 +702,7 @@ static int netxen_nic_close(struct net_device *netdev)
                         }
                         cmd_buff++;
                 }
+                FLUSH_SCHEDULED_WORK();
                 del_timer_sync(&adapter->watchdog_timer);
         }
 
@@ -668,7 +723,6 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
         struct cmd_desc_type0 *hwdesc;
         int k;
         struct netxen_cmd_buffer *pbuf = NULL;
-        unsigned int tries = 0;
         static int dropped_packet = 0;
         int frag_count;
         u32 local_producer = 0;
@@ -730,7 +784,7 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
                         if (((skb->nh.iph)->ihl * sizeof(u32)) +
                             ((skb->h.th)->doff * sizeof(u32)) +
                             sizeof(struct ethhdr) >
-                            (sizeof(struct cmd_desc_type0) - NET_IP_ALIGN)) {
+                            (sizeof(struct cmd_desc_type0) - 2)) {
                                 no_of_desc++;
                         }
                 }
@@ -741,27 +795,17 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
         if ((k + no_of_desc) >=
             ((last_cmd_consumer <= k) ? last_cmd_consumer + max_tx_desc_count :
              last_cmd_consumer)) {
+                port->stats.nocmddescriptor++;
+                DPRINTK(ERR, "No command descriptors available,"
+                        " producer = %d, consumer = %d count=%llu,"
+                        " dropping packet\n", producer,
+                        adapter->last_cmd_consumer,
+                        port->stats.nocmddescriptor);
+
+                netif_stop_queue(netdev);
+                port->flags |= NETXEN_NETDEV_STATUS;
                 spin_unlock_bh(&adapter->tx_lock);
-                if (tries == 0) {
-                        local_bh_disable();
-                        netxen_process_cmd_ring((unsigned long)adapter);
-                        local_bh_enable();
-                        ++tries;
-                        goto retry_getting_window;
-                } else {
-                        port->stats.nocmddescriptor++;
-                        DPRINTK(ERR, "No command descriptors available,"
-                                " producer = %d, consumer = %d count=%llu,"
-                                " dropping packet\n", producer,
-                                adapter->last_cmd_consumer,
-                                port->stats.nocmddescriptor);
-
-                        spin_lock_bh(&adapter->tx_lock);
-                        netif_stop_queue(netdev);
-                        port->flags |= NETXEN_NETDEV_STATUS;
-                        spin_unlock_bh(&adapter->tx_lock);
-                        return NETDEV_TX_BUSY;
-                }
+                return NETDEV_TX_BUSY;
         }
         k = get_index_range(k, max_tx_desc_count, no_of_desc);
         adapter->cmd_producer = k;
@@ -783,7 +827,6 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
                 pbuf->mss = 0;
                 hwdesc->mss = 0;
         }
-        pbuf->no_of_descriptors = no_of_desc;
         pbuf->total_length = skb->len;
         pbuf->skb = skb;
         pbuf->cmd = TX_ETHER_PKT;
@@ -793,11 +836,11 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
         buffrag->dma = pci_map_single(port->pdev, skb->data, first_seg_len,
                                       PCI_DMA_TODEVICE);
         buffrag->length = first_seg_len;
-        CMD_DESC_TOTAL_LENGTH_WRT(hwdesc, skb->len);
-        hwdesc->num_of_buffers = frag_count;
-        hwdesc->opcode = TX_ETHER_PKT;
+        netxen_set_cmd_desc_totallength(hwdesc, skb->len);
+        netxen_set_cmd_desc_num_of_buff(hwdesc, frag_count);
+        netxen_set_cmd_desc_opcode(hwdesc, TX_ETHER_PKT);
 
-        CMD_DESC_PORT_WRT(hwdesc, port->portnum);
+        netxen_set_cmd_desc_port(hwdesc, port->portnum);
         hwdesc->buffer1_length = cpu_to_le16(first_seg_len);
         hwdesc->addr_buffer1 = cpu_to_le64(buffrag->dma);
 
@@ -856,12 +899,12 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
         /* For LSO, we need to copy the MAC/IP/TCP headers into
          * the descriptor ring
          */
-        if (hw->cmd_desc_head[saved_producer].opcode == TX_TCP_LSO) {
+        if (netxen_get_cmd_desc_opcode(&hw->cmd_desc_head[saved_producer])
+            == TX_TCP_LSO) {
                 int hdr_len, first_hdr_len, more_hdr;
                 hdr_len = hw->cmd_desc_head[saved_producer].total_hdr_length;
-                if (hdr_len > (sizeof(struct cmd_desc_type0) - NET_IP_ALIGN)) {
-                        first_hdr_len =
-                            sizeof(struct cmd_desc_type0) - NET_IP_ALIGN;
+                if (hdr_len > (sizeof(struct cmd_desc_type0) - 2)) {
+                        first_hdr_len = sizeof(struct cmd_desc_type0) - 2;
                         more_hdr = 1;
                 } else {
                         first_hdr_len = hdr_len;
@@ -871,7 +914,7 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
                 hwdesc = &hw->cmd_desc_head[producer];
 
                 /* copy the first 64 bytes */
-                memcpy(((void *)hwdesc) + NET_IP_ALIGN,
+                memcpy(((void *)hwdesc) + 2,
                        (void *)(skb->data), first_hdr_len);
                 producer = get_next_index(producer, max_tx_desc_count);
 
@@ -887,7 +930,7 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
         }
         spin_lock_bh(&adapter->tx_lock);
         port->stats.txbytes +=
-            CMD_DESC_TOTAL_LENGTH(&hw->cmd_desc_head[saved_producer]);
+            netxen_get_cmd_desc_totallength(&hw->cmd_desc_head[saved_producer]);
         /* Code to update the adapter considering how many producer threads
            are currently working */
         if ((--adapter->num_threads) == 0) {
@@ -897,20 +940,6 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
                        NETXEN_CRB_NORMALIZE(adapter, CRB_CMD_PRODUCER_OFFSET));
                 wmb();
                 adapter->total_threads = 0;
-        } else {
-                u32 crb_producer = 0;
-                crb_producer =
-                    readl(NETXEN_CRB_NORMALIZE
-                          (adapter, CRB_CMD_PRODUCER_OFFSET));
-                if (crb_producer == local_producer) {
-                        crb_producer = get_index_range(crb_producer,
-                                                       max_tx_desc_count,
-                                                       no_of_desc);
-                        writel(crb_producer,
-                               NETXEN_CRB_NORMALIZE(adapter,
-                                                    CRB_CMD_PRODUCER_OFFSET));
-                        wmb();
-                }
         }
 
         port->stats.xmitfinished++;
@@ -927,29 +956,36 @@ static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
 static void netxen_watchdog(unsigned long v)
 {
         struct netxen_adapter *adapter = (struct netxen_adapter *)v;
-        schedule_work(&adapter->watchdog_task);
+        if (adapter != g_adapter) {
+                printk("%s: ***BUG*** adapter[%p] != g_adapter[%p]\n",
+                       __FUNCTION__, adapter, g_adapter);
+                return;
+        }
+
+        SCHEDULE_WORK(&adapter->watchdog_task);
 }
 
 static void netxen_tx_timeout(struct net_device *netdev)
 {
         struct netxen_port *port = (struct netxen_port *)netdev_priv(netdev);
-        struct netxen_adapter *adapter = port->adapter;
 
-        schedule_work(&adapter->tx_timeout_task);
+        SCHEDULE_WORK(port->adapter->tx_timeout_task + port->portnum);
 }
 
-static void netxen_tx_timeout_task(struct net_device *netdev)
+static void netxen_tx_timeout_task(struct work_struct *work)
 {
-        struct netxen_port *port = (struct netxen_port *)netdev_priv(netdev);
+        struct netxen_adapter *adapter =
+                container_of(work, struct netxen_adapter, tx_timeout_task);
+        struct net_device *netdev = adapter->netdev;
         unsigned long flags;
 
         printk(KERN_ERR "%s %s: transmit timeout, resetting.\n",
                netxen_nic_driver_name, netdev->name);
 
-        spin_lock_irqsave(&port->adapter->lock, flags);
+        spin_lock_irqsave(&adapter->lock, flags);
         netxen_nic_close(netdev);
         netxen_nic_open(netdev);
-        spin_unlock_irqrestore(&port->adapter->lock, flags);
+        spin_unlock_irqrestore(&adapter->lock, flags);
         netdev->trans_start = jiffies;
         netif_wake_queue(netdev);
 }
@@ -966,6 +1002,11 @@ netxen_handle_int(struct netxen_adapter *adapter, struct net_device *netdev)
         if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
                 int count = 0;
                 u32 mask;
+                mask = readl(pci_base_offset(adapter, ISR_INT_VECTOR));
+                if ((mask & 0x80) == 0) {
+                        /* not our interrupt */
+                        return ret;
+                }
                 netxen_nic_disable_int(adapter);
                 /* Window = 0 or 1 */
                 do {
@@ -1025,7 +1066,10 @@ irqreturn_t netxen_intr(int irq, void *data)
                 netdev = port->netdev;
 
                 /* process our status queue (for all 4 ports) */
-                netxen_handle_int(adapter, netdev);
+                if (netif_running(netdev)) {
+                        netxen_handle_int(adapter, netdev);
+                        break;
+                }
         }
 
         return IRQ_HANDLED;
@@ -1039,11 +1083,12 @@ static int netxen_nic_poll(struct net_device *netdev, int *budget)
         int done = 1;
         int ctx;
         int this_work_done;
+        int work_done = 0;
 
         DPRINTK(INFO, "polling for %d descriptors\n", *budget);
         port->stats.polled++;
 
-        adapter->work_done = 0;
+        work_done = 0;
         for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
                 /*
                  * Fairness issue. This will give undue weight to the
@@ -1060,20 +1105,20 @@ static int netxen_nic_poll(struct net_device *netdev, int *budget)
                 this_work_done = netxen_process_rcv_ring(adapter, ctx,
                                                          work_to_do /
                                                          MAX_RCV_CTX);
-                adapter->work_done += this_work_done;
+                work_done += this_work_done;
         }
 
-        netdev->quota -= adapter->work_done;
-        *budget -= adapter->work_done;
+        netdev->quota -= work_done;
+        *budget -= work_done;
 
-        if (adapter->work_done >= work_to_do
-            && netxen_nic_rx_has_work(adapter) != 0)
+        if (work_done >= work_to_do && netxen_nic_rx_has_work(adapter) != 0)
                 done = 0;
 
-        netxen_process_cmd_ring((unsigned long)adapter);
+        if (netxen_process_cmd_ring((unsigned long)adapter) == 0)
+                done = 0;
 
         DPRINTK(INFO, "new work_done: %d work_to_do: %d\n",
-                adapter->work_done, work_to_do);
+                work_done, work_to_do);
         if (done) {
                 netif_rx_complete(netdev);
                 netxen_nic_enable_int(adapter);
@@ -1116,8 +1161,9 @@ netxen_nic_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
                 if (ifr->ifr_data) {
                         sprintf(dev_name, "%s-%d", NETXEN_NIC_NAME_RSP,
                                 port->portnum);
-                        nr_bytes = copy_to_user((char *)ifr->ifr_data, dev_name,
-                                                NETXEN_NIC_NAME_LEN);
+                        nr_bytes =
+                            copy_to_user((char __user *)ifr->ifr_data, dev_name,
+                                         NETXEN_NIC_NAME_LEN);
                         if (nr_bytes)
                                 err = -EIO;
 
@@ -1144,6 +1190,9 @@ static struct pci_driver netxen_driver = {
 
 static int __init netxen_init_module(void)
 {
+        if ((netxen_workq = create_singlethread_workqueue("netxen")) == 0)
+                return -ENOMEM;
+
         return pci_module_init(&netxen_driver);
 }
 
@@ -1154,7 +1203,7 @@ static void __exit netxen_exit_module(void)
         /*
          * Wait for some time to allow the dma to drain, if any.
          */
-        mdelay(5);
+        destroy_workqueue(netxen_workq);
         pci_unregister_driver(&netxen_driver);
 }
 
diff --git a/drivers/net/netxen/netxen_nic_niu.c b/drivers/net/netxen/netxen_nic_niu.c
index 7950a04532e6..4987dc765d99 100644
--- a/drivers/net/netxen/netxen_nic_niu.c
+++ b/drivers/net/netxen/netxen_nic_niu.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2003 - 2006 NetXen, Inc.
  * All rights reserved.
- * 
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -16,10 +16,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  * MA  02111-1307, USA.
- * 
+ *
  * The full GNU General Public License is included in this distribution
  * in the file called LICENSE.
- * 
+ *
  * Contact Information:
  *    info@netxen.com
  * NetXen,
@@ -40,13 +40,15 @@
 
 static long phy_lock_timeout = 100000000;
 
-static inline int phy_lock(void)
+static inline int phy_lock(struct netxen_adapter *adapter)
 {
         int i;
         int done = 0, timeout = 0;
 
         while (!done) {
-                done = readl((void __iomem *)NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
+                done =
+                    readl(pci_base_offset
+                          (adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK)));
                 if (done == 1)
                         break;
                 if (timeout >= phy_lock_timeout) {
@@ -61,13 +63,15 @@ static inline int phy_lock(void)
                 }
         }
 
-        writel(NETXEN_PHY_LOCK_ID, (void __iomem *)PHY_LOCK_DRIVER);
+        writel(PHY_LOCK_DRIVER,
+               NETXEN_CRB_NORMALIZE(adapter, NETXEN_PHY_LOCK_ID));
         return 0;
 }
 
-static inline int phy_unlock(void)
+static inline int phy_unlock(struct netxen_adapter *adapter)
 {
-        readl((void __iomem *)NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK));
+        readl(pci_base_offset(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK)));
+
         return 0;
 }
 
@@ -95,7 +99,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy,
         __le32 status;
         __le32 mac_cfg0;
 
-        if (phy_lock() != 0) {
+        if (phy_lock(adapter) != 0) {
                 return -1;
         }
 
@@ -162,7 +166,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy,
                                            NETXEN_NIU_GB_MAC_CONFIG_0(0),
                                            &mac_cfg0, 4))
                         return -EIO;
-        phy_unlock();
+        phy_unlock(adapter);
         return result;
 }
 
@@ -399,8 +403,8 @@ int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
 {
         int result = 0;
         __le32 status;
-        if (adapter->ops->disable_phy_interrupts)
-                adapter->ops->disable_phy_interrupts(adapter, port);
+        if (adapter->disable_phy_interrupts)
+                adapter->disable_phy_interrupts(adapter, port);
         mdelay(2);
 
         if (0 ==
@@ -612,7 +616,7 @@ int netxen_niu_macaddr_set(struct netxen_port *port,
         __le32 temp = 0;
         struct netxen_adapter *adapter = port->adapter;
         int phy = port->portnum;
-        unsigned char mac_addr[MAX_ADDR_LEN];
+        unsigned char mac_addr[6];
         int i;
 
         for (i = 0; i < 10; i++) {
@@ -631,7 +635,7 @@ int netxen_niu_macaddr_set(struct netxen_port *port,
 
                 netxen_niu_macaddr_get(adapter, phy,
                                        (netxen_ethernet_macaddr_t *) mac_addr);
-                if (memcmp(mac_addr, addr, MAX_ADDR_LEN == 0))
+                if (memcmp(mac_addr, addr, 6) == 0)
                         break;
         }
 
diff --git a/drivers/net/netxen/netxen_nic_phan_reg.h b/drivers/net/netxen/netxen_nic_phan_reg.h
index 8181d436783f..7879f855af0b 100644
--- a/drivers/net/netxen/netxen_nic_phan_reg.h
+++ b/drivers/net/netxen/netxen_nic_phan_reg.h
@@ -33,15 +33,74 @@
 /* 
  * CRB Registers or queue message done only at initialization time.
  */
+#define NIC_CRB_BASE               NETXEN_CAM_RAM(0x200)
+#define NETXEN_NIC_REG(X)             (NIC_CRB_BASE+(X))
 
-/*
- * The following 2 are the base adresses for the CRB registers and their
- * offsets will be added to get addresses for the index addresses.
- */
-#define NIC_CRB_BASE_PORT1      NETXEN_CAM_RAM(0x200)
-#define NIC_CRB_BASE_PORT2      NETXEN_CAM_RAM(0x250)
+#define CRB_PHAN_CNTRL_LO_OFFSET    NETXEN_NIC_REG(0x00)
+#define CRB_PHAN_CNTRL_HI_OFFSET    NETXEN_NIC_REG(0x04)
+#define CRB_CMD_PRODUCER_OFFSET     NETXEN_NIC_REG(0x08)
+#define CRB_CMD_CONSUMER_OFFSET     NETXEN_NIC_REG(0x0c)
+#define CRB_PAUSE_ADDR_LO           NETXEN_NIC_REG(0x10)        /* C0 EPG BUG  */
+#define CRB_PAUSE_ADDR_HI           NETXEN_NIC_REG(0x14)
+#define CRB_HOST_CMD_ADDR_HI        NETXEN_NIC_REG(0x18)        /* host add:cmd ring */
+#define CRB_HOST_CMD_ADDR_LO        NETXEN_NIC_REG(0x1c)
+#define CRB_CMD_INTR_LOOP           NETXEN_NIC_REG(0x20)        /* 4 regs for perf */
+#define CRB_CMD_DMA_LOOP            NETXEN_NIC_REG(0x24)
+#define CRB_RCV_INTR_LOOP           NETXEN_NIC_REG(0x28)
+#define CRB_RCV_DMA_LOOP            NETXEN_NIC_REG(0x2c)
+#define CRB_ENABLE_TX_INTR          NETXEN_NIC_REG(0x30)        /* phantom init status */
+#define CRB_MMAP_ADDR_3             NETXEN_NIC_REG(0x34)
+#define CRB_CMDPEG_CMDRING          NETXEN_NIC_REG(0x38)
+#define CRB_HOST_DUMMY_BUF_ADDR_HI  NETXEN_NIC_REG(0x3c)
+#define CRB_HOST_DUMMY_BUF_ADDR_LO  NETXEN_NIC_REG(0x40)
+#define CRB_MMAP_ADDR_0             NETXEN_NIC_REG(0x44)
+#define CRB_MMAP_ADDR_1             NETXEN_NIC_REG(0x48)
+#define CRB_MMAP_ADDR_2             NETXEN_NIC_REG(0x4c)
+#define CRB_CMDPEG_STATE            NETXEN_NIC_REG(0x50)
+#define CRB_MMAP_SIZE_0             NETXEN_NIC_REG(0x54)
+#define CRB_MMAP_SIZE_1             NETXEN_NIC_REG(0x58)
+#define CRB_MMAP_SIZE_2             NETXEN_NIC_REG(0x5c)
+#define CRB_MMAP_SIZE_3             NETXEN_NIC_REG(0x60)
+#define CRB_GLOBAL_INT_COAL         NETXEN_NIC_REG(0x64)        /* interrupt coalescing */
+#define CRB_INT_COAL_MODE           NETXEN_NIC_REG(0x68)
+#define CRB_MAX_RCV_BUFS            NETXEN_NIC_REG(0x6c)
+#define CRB_TX_INT_THRESHOLD        NETXEN_NIC_REG(0x70)
+#define CRB_RX_PKT_TIMER            NETXEN_NIC_REG(0x74)
+#define CRB_TX_PKT_TIMER            NETXEN_NIC_REG(0x78)
+#define CRB_RX_PKT_CNT              NETXEN_NIC_REG(0x7c)
+#define CRB_RX_TMR_CNT              NETXEN_NIC_REG(0x80)
+#define CRB_RX_LRO_TIMER            NETXEN_NIC_REG(0x84)
+#define CRB_RX_LRO_MID_TIMER        NETXEN_NIC_REG(0x88)
+#define CRB_DMA_MAX_RCV_BUFS        NETXEN_NIC_REG(0x8c)
+#define CRB_MAX_DMA_ENTRIES         NETXEN_NIC_REG(0x90)
+#define CRB_XG_STATE                NETXEN_NIC_REG(0x94)        /* XG Link status */
+#define CRB_AGENT_GO                NETXEN_NIC_REG(0x98)        /* NIC pkt gen agent */
+#define CRB_AGENT_TX_SIZE           NETXEN_NIC_REG(0x9c)
+#define CRB_AGENT_TX_TYPE           NETXEN_NIC_REG(0xa0)
+#define CRB_AGENT_TX_ADDR           NETXEN_NIC_REG(0xa4)
+#define CRB_AGENT_TX_MSS            NETXEN_NIC_REG(0xa8)
+#define CRB_TX_STATE                NETXEN_NIC_REG(0xac)        /* Debug -performance */
+#define CRB_TX_COUNT                NETXEN_NIC_REG(0xb0)
+#define CRB_RX_STATE                NETXEN_NIC_REG(0xb4)
+#define CRB_RX_PERF_DEBUG_1         NETXEN_NIC_REG(0xb8)
+#define CRB_RX_LRO_CONTROL          NETXEN_NIC_REG(0xbc)        /* LRO On/OFF */
+#define CRB_RX_LRO_START_NUM        NETXEN_NIC_REG(0xc0)
+#define CRB_MPORT_MODE              NETXEN_NIC_REG(0xc4)        /* Multiport Mode */
+#define CRB_CMD_RING_SIZE           NETXEN_NIC_REG(0xc8)
+#define CRB_INT_VECTOR              NETXEN_NIC_REG(0xd4)
+#define CRB_CTX_RESET               NETXEN_NIC_REG(0xd8)
+#define CRB_HOST_STS_PROD           NETXEN_NIC_REG(0xdc)
+#define CRB_HOST_STS_CONS           NETXEN_NIC_REG(0xe0)
+#define CRB_PEG_CMD_PROD            NETXEN_NIC_REG(0xe4)
+#define CRB_PEG_CMD_CONS            NETXEN_NIC_REG(0xe8)
+#define CRB_HOST_BUFFER_PROD        NETXEN_NIC_REG(0xec)
+#define CRB_HOST_BUFFER_CONS        NETXEN_NIC_REG(0xf0)
+#define CRB_JUMBO_BUFFER_PROD       NETXEN_NIC_REG(0xf4)
+#define CRB_JUMBO_BUFFER_CONS       NETXEN_NIC_REG(0xf8)
 
-#define NETXEN_NIC_REG(X)       (NIC_CRB_BASE_PORT1+(X))
+#define CRB_CMD_PRODUCER_OFFSET_1   NETXEN_NIC_REG(0x1ac)
+#define CRB_CMD_CONSUMER_OFFSET_1   NETXEN_NIC_REG(0x1b0)
+#define CRB_TEMP_STATE              NETXEN_NIC_REG(0x1b4)
 
 /*
  * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
@@ -51,74 +110,20 @@
  * on the Phantom.
  */
 
-#define CRB_PHAN_CNTRL_LO_OFFSET        NETXEN_NIC_REG(0x00)
-#define CRB_PHAN_CNTRL_HI_OFFSET        NETXEN_NIC_REG(0x04)
-
-/* point to the indexes */
-#define CRB_CMD_PRODUCER_OFFSET         NETXEN_NIC_REG(0x08)
-#define CRB_CMD_CONSUMER_OFFSET         NETXEN_NIC_REG(0x0c)
-
-#define CRB_PAUSE_ADDR_LO               NETXEN_NIC_REG(0x10)
-#define CRB_PAUSE_ADDR_HI               NETXEN_NIC_REG(0x14)
-
-/* address of command descriptors in the host memory */
-#define CRB_HOST_CMD_ADDR_HI            NETXEN_NIC_REG(0x30)
-#define CRB_HOST_CMD_ADDR_LO            NETXEN_NIC_REG(0x34)
-
-/* The following 4 CRB registers are for doing performance coal */
-#define CRB_CMD_INTR_LOOP               NETXEN_NIC_REG(0x38)
-#define CRB_CMD_DMA_LOOP                NETXEN_NIC_REG(0x3c)
-#define CRB_RCV_INTR_LOOP               NETXEN_NIC_REG(0x40)
-#define CRB_RCV_DMA_LOOP                NETXEN_NIC_REG(0x44)
-
-/* Needed by the host to find out the state of Phantom's initialization */
-#define CRB_ENABLE_TX_INTR              NETXEN_NIC_REG(0x4c)
-#define CRB_CMDPEG_STATE                NETXEN_NIC_REG(0x50)
-#define CRB_CMDPEG_CMDRING              NETXEN_NIC_REG(0x54)
-
-/* Interrupt coalescing parameters */
-#define CRB_GLOBAL_INT_COAL             NETXEN_NIC_REG(0x80)
-#define CRB_INT_COAL_MODE               NETXEN_NIC_REG(0x84)
-#define CRB_MAX_RCV_BUFS                NETXEN_NIC_REG(0x88)
-#define CRB_TX_INT_THRESHOLD            NETXEN_NIC_REG(0x8c)
-#define CRB_RX_PKT_TIMER                NETXEN_NIC_REG(0x90)
-#define CRB_TX_PKT_TIMER                NETXEN_NIC_REG(0x94)
-#define CRB_RX_PKT_CNT                  NETXEN_NIC_REG(0x98)
-#define CRB_RX_TMR_CNT                  NETXEN_NIC_REG(0x9c)
-#define CRB_INT_THRESH           NETXEN_NIC_REG(0xa4)
-
-/* Register for communicating XG link status */
-#define CRB_XG_STATE                    NETXEN_NIC_REG(0xa0)
-
-/* Register for communicating card temperature */
-/* Upper 16 bits are temperature value. Lower 16 bits are the state */
-#define CRB_TEMP_STATE           NETXEN_NIC_REG(0xa8)
-#define nx_get_temp_val(x)           ((x) >> 16)
-#define nx_get_temp_state(x)       ((x) & 0xffff)
-#define nx_encode_temp(val, state)     (((val) << 16) | (state))
-
-/* Debug registers for controlling NIC pkt gen agent */
-#define CRB_AGENT_GO                    NETXEN_NIC_REG(0xb0)
-#define CRB_AGENT_TX_SIZE               NETXEN_NIC_REG(0xb4)
-#define CRB_AGENT_TX_TYPE               NETXEN_NIC_REG(0xb8)
-#define CRB_AGENT_TX_ADDR               NETXEN_NIC_REG(0xbc)
-#define CRB_AGENT_TX_MSS                NETXEN_NIC_REG(0xc0)
-
-/* Debug registers for observing NIC performance */
-#define CRB_TX_STATE                    NETXEN_NIC_REG(0xd0)
-#define CRB_TX_COUNT                    NETXEN_NIC_REG(0xd4)
-#define CRB_RX_STATE                    NETXEN_NIC_REG(0xd8)
+#define nx_get_temp_val(x)              ((x) >> 16)
+#define nx_get_temp_state(x)            ((x) & 0xffff)
+#define nx_encode_temp(val, state)      (((val) << 16) | (state))
 
 /* CRB registers per Rcv Descriptor ring */
 struct netxen_rcv_desc_crb {
         u32 crb_rcv_producer_offset __attribute__ ((aligned(512)));
         u32 crb_rcv_consumer_offset;
         u32 crb_globalrcv_ring;
+        u32 crb_rcv_ring_size;
 };
 
 /*
- * CRB registers used by the receive peg logic. One instance of these
- * needs to be instantiated per instance of the receive peg.
+ * CRB registers used by the receive peg logic.
  */
 
 struct netxen_recv_crb {
@@ -127,6 +132,7 @@ struct netxen_recv_crb {
         u32 crb_rcv_status_producer;
         u32 crb_rcv_status_consumer;
         u32 crb_rcvpeg_state;
+        u32 crb_status_ring_size;
 };
 
 #if defined(DEFINE_GLOBAL_RECV_CRB)
@@ -139,30 +145,48 @@ struct netxen_recv_crb recv_crb_registers[] = {
          {
           {
            /* crb_rcv_producer_offset: */
-           NETXEN_NIC_REG(0x18),
+           NETXEN_NIC_REG(0x100),
            /* crb_rcv_consumer_offset: */
-           NETXEN_NIC_REG(0x1c),
+           NETXEN_NIC_REG(0x104),
            /* crb_gloablrcv_ring: */
-           NETXEN_NIC_REG(0x20),
+           NETXEN_NIC_REG(0x108),
+           /* crb_rcv_ring_size */
+           NETXEN_NIC_REG(0x10c),
+
            },
           /* Jumbo frames */
           {
            /* crb_rcv_producer_offset: */
-           NETXEN_NIC_REG(0x100),
+           NETXEN_NIC_REG(0x110),
            /* crb_rcv_consumer_offset: */
-           NETXEN_NIC_REG(0x104),
+           NETXEN_NIC_REG(0x114),
            /* crb_gloablrcv_ring: */
-           NETXEN_NIC_REG(0x108),
+           NETXEN_NIC_REG(0x118),
+           /* crb_rcv_ring_size */
+           NETXEN_NIC_REG(0x11c),
+           },
+          /* LRO */
+          {
+           /* crb_rcv_producer_offset: */
+           NETXEN_NIC_REG(0x120),
+           /* crb_rcv_consumer_offset: */
+           NETXEN_NIC_REG(0x124),
+           /* crb_gloablrcv_ring: */
+           NETXEN_NIC_REG(0x128),
+           /* crb_rcv_ring_size */
+           NETXEN_NIC_REG(0x12c),
            }
           },
          /* crb_rcvstatus_ring: */
-         NETXEN_NIC_REG(0x24),
+         NETXEN_NIC_REG(0x130),
          /* crb_rcv_status_producer: */
-         NETXEN_NIC_REG(0x28),
+         NETXEN_NIC_REG(0x134),
          /* crb_rcv_status_consumer: */
-         NETXEN_NIC_REG(0x2c),
+         NETXEN_NIC_REG(0x138),
          /* crb_rcvpeg_state: */
-         NETXEN_NIC_REG(0x48),
+         NETXEN_NIC_REG(0x13c),
+         /* crb_status_ring_size */
+         NETXEN_NIC_REG(0x140),
 
          },
         /*
@@ -173,34 +197,66 @@ struct netxen_recv_crb recv_crb_registers[] = {
          {
           {
            /* crb_rcv_producer_offset: */
-           NETXEN_NIC_REG(0x80),
+           NETXEN_NIC_REG(0x144),
            /* crb_rcv_consumer_offset: */
-           NETXEN_NIC_REG(0x84),
+           NETXEN_NIC_REG(0x148),
            /* crb_globalrcv_ring: */
-           NETXEN_NIC_REG(0x88),
+           NETXEN_NIC_REG(0x14c),
+           /* crb_rcv_ring_size */
+           NETXEN_NIC_REG(0x150),
+
            },
           /* Jumbo frames */
           {
            /* crb_rcv_producer_offset: */
-           NETXEN_NIC_REG(0x10C),
+           NETXEN_NIC_REG(0x154),
            /* crb_rcv_consumer_offset: */
-           NETXEN_NIC_REG(0x110),
+           NETXEN_NIC_REG(0x158),
            /* crb_globalrcv_ring: */
-           NETXEN_NIC_REG(0x114),
+           NETXEN_NIC_REG(0x15c),
+           /* crb_rcv_ring_size */
+           NETXEN_NIC_REG(0x160),
+           },
+          /* LRO */
+          {
+           /* crb_rcv_producer_offset: */
+           NETXEN_NIC_REG(0x164),
+           /* crb_rcv_consumer_offset: */
+           NETXEN_NIC_REG(0x168),
+           /* crb_globalrcv_ring: */
+           NETXEN_NIC_REG(0x16c),
+           /* crb_rcv_ring_size */
+           NETXEN_NIC_REG(0x170),
            }
+
           },
          /* crb_rcvstatus_ring: */
-         NETXEN_NIC_REG(0x8c),
+         NETXEN_NIC_REG(0x174),
          /* crb_rcv_status_producer: */
-         NETXEN_NIC_REG(0x90),
+         NETXEN_NIC_REG(0x178),
          /* crb_rcv_status_consumer: */
-         NETXEN_NIC_REG(0x94),
+         NETXEN_NIC_REG(0x17c),
          /* crb_rcvpeg_state: */
-         NETXEN_NIC_REG(0x98),
+         NETXEN_NIC_REG(0x180),
+         /* crb_status_ring_size */
+         NETXEN_NIC_REG(0x184),
+
          },
 };
+
+u64 ctx_addr_sig_regs[][3] = {
+        {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
+        {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
+        {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
+        {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
+};
+
 #else
 extern struct netxen_recv_crb recv_crb_registers[];
+extern u64 ctx_addr_sig_regs[][3];
+#define CRB_CTX_ADDR_REG_LO            (ctx_addr_sig_regs[0][0])
+#define CRB_CTX_ADDR_REG_HI            (ctx_addr_sig_regs[0][2])
+#define CRB_CTX_SIGNATURE_REG       (ctx_addr_sig_regs[0][1])
 #endif                          /* DEFINE_GLOBAL_RECEIVE_CRB */
 
 /*
diff --git a/drivers/net/ni52.c b/drivers/net/ni52.c
index 26e42f6e9fb1..196993a29b09 100644
--- a/drivers/net/ni52.c
+++ b/drivers/net/ni52.c
@@ -1335,7 +1335,7 @@ int __init init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(dev_ni52);
         release_region(dev_ni52->base_addr, NI52_TOTAL_SIZE);
diff --git a/drivers/net/ni65.c b/drivers/net/ni65.c
index 340ad0d5388a..1578f4d98498 100644
--- a/drivers/net/ni65.c
+++ b/drivers/net/ni65.c
@@ -1259,7 +1259,7 @@ int __init init_module(void)
         return IS_ERR(dev_ni65) ? PTR_ERR(dev_ni65) : 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(dev_ni65);
         cleanup_card(dev_ni65);
diff --git a/drivers/net/ns83820.c b/drivers/net/ns83820.c
index b0127c71a5b6..568daeb3e9d8 100644
--- a/drivers/net/ns83820.c
+++ b/drivers/net/ns83820.c
@@ -414,10 +414,10 @@ struct rx_info {
 
         struct sk_buff  *skbs[NR_RX_DESC];
 
-        u32             *next_rx_desc;
+        __le32          *next_rx_desc;
         u16             next_rx, next_empty;
 
-        u32             *descs;
+        __le32          *descs;
         dma_addr_t      phy_descs;
 };
 
@@ -427,6 +427,7 @@ struct ns83820 {
         u8                      __iomem *base;
 
         struct pci_dev          *pci_dev;
+        struct net_device       *ndev;
 
 #ifdef NS83820_VLAN_ACCEL_SUPPORT
         struct vlan_group       *vlgrp;
@@ -459,7 +460,7 @@ struct ns83820 {
         struct sk_buff  *tx_skbs[NR_TX_DESC];
 
         char            pad[16] __attribute__((aligned(16)));
-        u32             *tx_descs;
+        __le32          *tx_descs;
         dma_addr_t      tx_phy_descs;
 
         struct timer_list       tx_watchdog;
@@ -533,7 +534,7 @@ static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid
  * conditions, still route realtime traffic with as low jitter as
  * possible.
  */
-static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
+static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
 {
         desc_addr_set(desc + DESC_LINK, link);
         desc_addr_set(desc + DESC_BUFPTR, buf);
@@ -547,7 +548,7 @@ static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
 {
         unsigned next_empty;
         u32 cmdsts;
-        u32 *sg;
+        __le32 *sg;
         dma_addr_t buf;
 
         next_empty = dev->rx_info.next_empty;
@@ -631,10 +632,10 @@ static void fastcall rx_refill_atomic(struct net_device *ndev)
 }
 
 /* REFILL */
-static inline void queue_refill(void *_dev)
+static inline void queue_refill(struct work_struct *work)
 {
-        struct net_device *ndev = _dev;
-        struct ns83820 *dev = PRIV(ndev);
+        struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
+        struct net_device *ndev = dev->ndev;
 
         rx_refill(ndev, GFP_KERNEL);
         if (dev->rx_info.up)
@@ -874,7 +875,8 @@ static void fastcall rx_irq(struct net_device *ndev)
         struct rx_info *info = &dev->rx_info;
         unsigned next_rx;
         int rx_rc, len;
-        u32 cmdsts, *desc;
+        u32 cmdsts;
+        __le32 *desc;
         unsigned long flags;
         int nr = 0;
 
@@ -1010,7 +1012,8 @@ static inline void kick_tx(struct ns83820 *dev)
 static void do_tx_done(struct net_device *ndev)
 {
         struct ns83820 *dev = PRIV(ndev);
-        u32 cmdsts, tx_done_idx, *desc;
+        u32 cmdsts, tx_done_idx;
+        __le32 *desc;
 
         dprintk("do_tx_done(%p)\n", ndev);
         tx_done_idx = dev->tx_done_idx;
@@ -1077,7 +1080,7 @@ static void ns83820_cleanup_tx(struct ns83820 *dev)
                 struct sk_buff *skb = dev->tx_skbs[i];
                 dev->tx_skbs[i] = NULL;
                 if (skb) {
-                        u32 *desc = dev->tx_descs + (i * DESC_SIZE);
+                        __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
                         pci_unmap_single(dev->pci_dev,
                                         desc_addr_get(desc + DESC_BUFPTR),
                                         le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
@@ -1107,7 +1110,7 @@ static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
         skb_frag_t *frag;
         int stopped = 0;
         int do_intr = 0;
-        volatile u32 *first_desc;
+        volatile __le32 *first_desc;
 
         dprintk("ns83820_hard_start_xmit\n");
 
@@ -1180,7 +1183,7 @@ again:
         first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
 
         for (;;) {
-                volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
+                volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
 
                 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
                         (unsigned long long)buf);
@@ -1455,7 +1458,8 @@ static int ns83820_stop(struct net_device *ndev)
 static void ns83820_tx_timeout(struct net_device *ndev)
 {
         struct ns83820 *dev = PRIV(ndev);
-        u32 tx_done_idx, *desc;
+        u32 tx_done_idx;
+        __le32 *desc;
         unsigned long flags;
 
         spin_lock_irqsave(&dev->tx_lock, flags);
@@ -1841,6 +1845,7 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
 
         ndev = alloc_etherdev(sizeof(struct ns83820));
         dev = PRIV(ndev);
+        dev->ndev = ndev;
         err = -ENOMEM;
         if (!dev)
                 goto out;
@@ -1853,7 +1858,7 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
         SET_MODULE_OWNER(ndev);
         SET_NETDEV_DEV(ndev, &pci_dev->dev);
 
-        INIT_WORK(&dev->tq_refill, queue_refill, ndev);
+        INIT_WORK(&dev->tq_refill, queue_refill);
         tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
 
         err = pci_enable_device(pci_dev);
diff --git a/drivers/net/pcmcia/3c574_cs.c b/drivers/net/pcmcia/3c574_cs.c
index 046009928526..794cc61819dd 100644
--- a/drivers/net/pcmcia/3c574_cs.c
+++ b/drivers/net/pcmcia/3c574_cs.c
@@ -338,7 +338,6 @@ static int tc574_config(struct pcmcia_device *link)
         struct net_device *dev = link->priv;
         struct el3_private *lp = netdev_priv(dev);
         tuple_t tuple;
-        cisparse_t parse;
         unsigned short buf[32];
         int last_fn, last_ret, i, j;
         kio_addr_t ioaddr;
@@ -350,17 +349,6 @@ static int tc574_config(struct pcmcia_device *link)
 
         DEBUG(0, "3c574_config(0x%p)\n", link);
 
-        tuple.Attributes = 0;
-        tuple.DesiredTuple = CISTPL_CONFIG;
-        CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-        tuple.TupleData = (cisdata_t *)buf;
-        tuple.TupleDataMax = 64;
-        tuple.TupleOffset = 0;
-        CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-        link->conf.ConfigBase = parse.config.base;
-        link->conf.Present = parse.config.rmask[0];
-
         link->io.IOAddrLines = 16;
         for (i = j = 0; j < 0x400; j += 0x20) {
                 link->io.BasePort1 = j ^ 0x300;
@@ -382,6 +370,10 @@ static int tc574_config(struct pcmcia_device *link)
         /* The 3c574 normally uses an EEPROM for configuration info, including
            the hardware address.  The future products may include a modem chip
            and put the address in the CIS. */
+        tuple.Attributes = 0;
+        tuple.TupleData = (cisdata_t *)buf;
+        tuple.TupleDataMax = 64;
+        tuple.TupleOffset = 0;
         tuple.DesiredTuple = 0x88;
         if (pcmcia_get_first_tuple(link, &tuple) == CS_SUCCESS) {
                 pcmcia_get_tuple_data(link, &tuple);
@@ -397,12 +389,9 @@ static int tc574_config(struct pcmcia_device *link)
                         goto failed;
                 }
         }
-        tuple.DesiredTuple = CISTPL_VERS_1;
-        if (pcmcia_get_first_tuple(link, &tuple) == CS_SUCCESS &&
-                pcmcia_get_tuple_data(link, &tuple) == CS_SUCCESS &&
-                pcmcia_parse_tuple(link, &tuple, &parse) == CS_SUCCESS) {
-                cardname = parse.version_1.str + parse.version_1.ofs[1];
-        } else
+        if (link->prod_id[1])
+                cardname = link->prod_id[1];
+        else
                 cardname = "3Com 3c574";
 
         {
diff --git a/drivers/net/pcmcia/3c589_cs.c b/drivers/net/pcmcia/3c589_cs.c
index 231fa2c9ec6c..1e73ff7d5d8e 100644
--- a/drivers/net/pcmcia/3c589_cs.c
+++ b/drivers/net/pcmcia/3c589_cs.c
@@ -253,7 +253,6 @@ static int tc589_config(struct pcmcia_device *link)
     struct net_device *dev = link->priv;
     struct el3_private *lp = netdev_priv(dev);
     tuple_t tuple;
-    cisparse_t parse;
     u16 buf[32], *phys_addr;
     int last_fn, last_ret, i, j, multi = 0, fifo;
     kio_addr_t ioaddr;
@@ -263,26 +262,16 @@ static int tc589_config(struct pcmcia_device *link)
 
     phys_addr = (u16 *)dev->dev_addr;
     tuple.Attributes = 0;
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
     tuple.TupleData = (cisdata_t *)buf;
     tuple.TupleDataMax = sizeof(buf);
     tuple.TupleOffset = 0;
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-    link->conf.ConfigBase = parse.config.base;
-    link->conf.Present = parse.config.rmask[0];
-    
-    /* Is this a 3c562? */
-    tuple.DesiredTuple = CISTPL_MANFID;
     tuple.Attributes = TUPLE_RETURN_COMMON;
-    if ((pcmcia_get_first_tuple(link, &tuple) == CS_SUCCESS) &&
-        (pcmcia_get_tuple_data(link, &tuple) == CS_SUCCESS)) {
-        if (le16_to_cpu(buf[0]) != MANFID_3COM)
+
+    /* Is this a 3c562? */
+    if (link->manf_id != MANFID_3COM)
             printk(KERN_INFO "3c589_cs: hmmm, is this really a "
                    "3Com card??\n");
-        multi = (le16_to_cpu(buf[1]) == PRODID_3COM_3C562);
-    }
+    multi = (link->card_id == PRODID_3COM_3C562);
 
     /* For the 3c562, the base address must be xx00-xx7f */
     link->io.IOAddrLines = 16;
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c
index 5ddd5742f779..6139048f8117 100644
--- a/drivers/net/pcmcia/axnet_cs.c
+++ b/drivers/net/pcmcia/axnet_cs.c
@@ -299,11 +299,7 @@ static int axnet_config(struct pcmcia_device *link)
     tuple.TupleData = (cisdata_t *)buf;
     tuple.TupleDataMax = sizeof(buf);
     tuple.TupleOffset = 0;
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-    link->conf.ConfigBase = parse.config.base;
+
     /* don't trust the CIS on this; Linksys got it wrong */
     link->conf.Present = 0x63;
 
diff --git a/drivers/net/pcmcia/com20020_cs.c b/drivers/net/pcmcia/com20020_cs.c
index 48434d7924eb..91f65e91cd5f 100644
--- a/drivers/net/pcmcia/com20020_cs.c
+++ b/drivers/net/pcmcia/com20020_cs.c
@@ -249,12 +249,9 @@ do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 static int com20020_config(struct pcmcia_device *link)
 {
     struct arcnet_local *lp;
-    tuple_t tuple;
-    cisparse_t parse;
     com20020_dev_t *info;
     struct net_device *dev;
     int i, last_ret, last_fn;
-    u_char buf[64];
     int ioaddr;
 
     info = link->priv;
@@ -264,16 +261,6 @@ static int com20020_config(struct pcmcia_device *link)
 
     DEBUG(0, "com20020_config(0x%p)\n", link);
 
-    tuple.Attributes = 0;
-    tuple.TupleData = buf;
-    tuple.TupleDataMax = 64;
-    tuple.TupleOffset = 0;
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-    link->conf.ConfigBase = parse.config.base;
-
     DEBUG(1,"arcnet: baseport1 is %Xh\n", link->io.BasePort1);
     i = !CS_SUCCESS;
     if (!link->io.BasePort1)
diff --git a/drivers/net/pcmcia/fmvj18x_cs.c b/drivers/net/pcmcia/fmvj18x_cs.c
index 65f6fdf43725..0d7de617e535 100644
--- a/drivers/net/pcmcia/fmvj18x_cs.c
+++ b/drivers/net/pcmcia/fmvj18x_cs.c
@@ -342,7 +342,7 @@ static int fmvj18x_config(struct pcmcia_device *link)
     tuple_t tuple;
     cisparse_t parse;
     u_short buf[32];
-    int i, last_fn, last_ret, ret;
+    int i, last_fn = 0, last_ret = 0, ret;
     kio_addr_t ioaddr;
     cardtype_t cardtype;
     char *card_name = "unknown";
@@ -350,21 +350,9 @@ static int fmvj18x_config(struct pcmcia_device *link)
 
     DEBUG(0, "fmvj18x_config(0x%p)\n", link);
 
-    /*
-       This reads the card's CONFIG tuple to find its configuration
-       registers.
-    */
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
     tuple.TupleData = (u_char *)buf;
     tuple.TupleDataMax = 64;
     tuple.TupleOffset = 0;
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-
-    link->conf.ConfigBase = parse.config.base; 
-    link->conf.Present = parse.config.rmask[0];
-
     tuple.DesiredTuple = CISTPL_FUNCE;
     tuple.TupleOffset = 0;
     if (pcmcia_get_first_tuple(link, &tuple) == CS_SUCCESS) {
@@ -374,17 +362,12 @@ static int fmvj18x_config(struct pcmcia_device *link)
         CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
         CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
         link->conf.ConfigIndex = parse.cftable_entry.index;
-        tuple.DesiredTuple = CISTPL_MANFID;
-        if (pcmcia_get_first_tuple(link, &tuple) == CS_SUCCESS)
-            CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        else
-            buf[0] = 0xffff;
-        switch (le16_to_cpu(buf[0])) {
+        switch (link->manf_id) {
         case MANFID_TDK:
             cardtype = TDK;
-            if (le16_to_cpu(buf[1]) == PRODID_TDK_GN3410
-                        || le16_to_cpu(buf[1]) == PRODID_TDK_NP9610
-                        || le16_to_cpu(buf[1]) == PRODID_TDK_MN3200) {
+            if (link->card_id == PRODID_TDK_GN3410
+                        || link->card_id == PRODID_TDK_NP9610
+                        || link->card_id == PRODID_TDK_MN3200) {
                 /* MultiFunction Card */
                 link->conf.ConfigBase = 0x800;
                 link->conf.ConfigIndex = 0x47;
@@ -395,11 +378,11 @@ static int fmvj18x_config(struct pcmcia_device *link)
             cardtype = CONTEC;
             break;
         case MANFID_FUJITSU:
-            if (le16_to_cpu(buf[1]) == PRODID_FUJITSU_MBH10302)
+            if (link->card_id == PRODID_FUJITSU_MBH10302)
                 /* RATOC REX-5588/9822/4886's PRODID are 0004(=MBH10302),
                    but these are MBH10304 based card. */ 
                 cardtype = MBH10304;
-            else if (le16_to_cpu(buf[1]) == PRODID_FUJITSU_MBH10304)
+            else if (link->card_id == PRODID_FUJITSU_MBH10304)
                 cardtype = MBH10304;
             else
                 cardtype = LA501;
@@ -409,14 +392,9 @@ static int fmvj18x_config(struct pcmcia_device *link)
         }
     } else {
         /* old type card */
-        tuple.DesiredTuple = CISTPL_MANFID;
-        if (pcmcia_get_first_tuple(link, &tuple) == CS_SUCCESS)
-            CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        else
-            buf[0] = 0xffff;
-        switch (le16_to_cpu(buf[0])) {
+        switch (link->manf_id) {
         case MANFID_FUJITSU:
-            if (le16_to_cpu(buf[1]) == PRODID_FUJITSU_MBH10304) {
+            if (link->card_id == PRODID_FUJITSU_MBH10304) {
                 cardtype = XXX10304;    /* MBH10304 with buggy CIS */
                 link->conf.ConfigIndex = 0x20;
             } else {
diff --git a/drivers/net/pcmcia/ibmtr_cs.c b/drivers/net/pcmcia/ibmtr_cs.c
index bc0ca41a0542..a956a51d284f 100644
--- a/drivers/net/pcmcia/ibmtr_cs.c
+++ b/drivers/net/pcmcia/ibmtr_cs.c
@@ -222,24 +222,12 @@ static int ibmtr_config(struct pcmcia_device *link)
     ibmtr_dev_t *info = link->priv;
     struct net_device *dev = info->dev;
     struct tok_info *ti = netdev_priv(dev);
-    tuple_t tuple;
-    cisparse_t parse;
     win_req_t req;
     memreq_t mem;
     int i, last_ret, last_fn;
-    u_char buf[64];
 
     DEBUG(0, "ibmtr_config(0x%p)\n", link);
 
-    tuple.Attributes = 0;
-    tuple.TupleData = buf;
-    tuple.TupleDataMax = 64;
-    tuple.TupleOffset = 0;
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-    link->conf.ConfigBase = parse.config.base;
     link->conf.ConfigIndex = 0x61;
 
     /* Determine if this is PRIMARY or ALTERNATE. */
diff --git a/drivers/net/pcmcia/nmclan_cs.c b/drivers/net/pcmcia/nmclan_cs.c
index e77110e4c288..3b707747a811 100644
--- a/drivers/net/pcmcia/nmclan_cs.c
+++ b/drivers/net/pcmcia/nmclan_cs.c
@@ -656,23 +656,12 @@ static int nmclan_config(struct pcmcia_device *link)
   struct net_device *dev = link->priv;
   mace_private *lp = netdev_priv(dev);
   tuple_t tuple;
-  cisparse_t parse;
   u_char buf[64];
   int i, last_ret, last_fn;
   kio_addr_t ioaddr;
 
   DEBUG(0, "nmclan_config(0x%p)\n", link);
 
-  tuple.Attributes = 0;
-  tuple.TupleData = buf;
-  tuple.TupleDataMax = 64;
-  tuple.TupleOffset = 0;
-  tuple.DesiredTuple = CISTPL_CONFIG;
-  CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-  CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-  CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-  link->conf.ConfigBase = parse.config.base;
-
   CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));
   CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
   CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
@@ -686,6 +675,7 @@ static int nmclan_config(struct pcmcia_device *link)
   tuple.TupleData = buf;
   tuple.TupleDataMax = 64;
   tuple.TupleOffset = 0;
+  tuple.Attributes = 0;
   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
   memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index c51cc5d8789a..2b1238e2dbdb 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -519,31 +519,15 @@ static int pcnet_config(struct pcmcia_device *link)
     tuple_t tuple;
     cisparse_t parse;
     int i, last_ret, last_fn, start_pg, stop_pg, cm_offset;
-    int manfid = 0, prodid = 0, has_shmem = 0;
+    int has_shmem = 0;
     u_short buf[64];
     hw_info_t *hw_info;
 
     DEBUG(0, "pcnet_config(0x%p)\n", link);
 
-    tuple.Attributes = 0;
     tuple.TupleData = (cisdata_t *)buf;
     tuple.TupleDataMax = sizeof(buf);
     tuple.TupleOffset = 0;
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-    link->conf.ConfigBase = parse.config.base;
-    link->conf.Present = parse.config.rmask[0];
-
-    tuple.DesiredTuple = CISTPL_MANFID;
-    tuple.Attributes = TUPLE_RETURN_COMMON;
-    if ((pcmcia_get_first_tuple(link, &tuple) == CS_SUCCESS) &&
-        (pcmcia_get_tuple_data(link, &tuple) == CS_SUCCESS)) {
-        manfid = le16_to_cpu(buf[0]);
-        prodid = le16_to_cpu(buf[1]);
-    }
-
     tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
     tuple.Attributes = 0;
     CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
@@ -589,8 +573,8 @@ static int pcnet_config(struct pcmcia_device *link)
         link->conf.Attributes |= CONF_ENABLE_SPKR;
         link->conf.Status = CCSR_AUDIO_ENA;
     }
-    if ((manfid == MANFID_IBM) &&
-        (prodid == PRODID_IBM_HOME_AND_AWAY))
+    if ((link->manf_id == MANFID_IBM) &&
+        (link->card_id == PRODID_IBM_HOME_AND_AWAY))
         link->conf.ConfigIndex |= 0x10;
 
     CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
@@ -624,10 +608,10 @@ static int pcnet_config(struct pcmcia_device *link)
     info->flags = hw_info->flags;
     /* Check for user overrides */
     info->flags |= (delay_output) ? DELAY_OUTPUT : 0;
-    if ((manfid == MANFID_SOCKET) &&
-        ((prodid == PRODID_SOCKET_LPE) ||
-         (prodid == PRODID_SOCKET_LPE_CF) ||
-         (prodid == PRODID_SOCKET_EIO)))
+    if ((link->manf_id == MANFID_SOCKET) &&
+        ((link->card_id == PRODID_SOCKET_LPE) ||
+         (link->card_id == PRODID_SOCKET_LPE_CF) ||
+         (link->card_id == PRODID_SOCKET_EIO)))
         info->flags &= ~USE_BIG_BUF;
     if (!use_big_buf)
         info->flags &= ~USE_BIG_BUF;
diff --git a/drivers/net/pcmcia/smc91c92_cs.c b/drivers/net/pcmcia/smc91c92_cs.c
index 20fcc3576202..530df8883fe5 100644
--- a/drivers/net/pcmcia/smc91c92_cs.c
+++ b/drivers/net/pcmcia/smc91c92_cs.c
@@ -560,16 +560,8 @@ static int mhz_setup(struct pcmcia_device *link)
 
     /* Read the station address from the CIS.  It is stored as the last
        (fourth) string in the Version 1 Version/ID tuple. */
-    tuple->DesiredTuple = CISTPL_VERS_1;
-    if (first_tuple(link, tuple, parse) != CS_SUCCESS) {
-        rc = -1;
-        goto free_cfg_mem;
-    }
-    /* Ugh -- the EM1144 card has two VERS_1 tuples!?! */
-    if (next_tuple(link, tuple, parse) != CS_SUCCESS)
-        first_tuple(link, tuple, parse);
-    if (parse->version_1.ns > 3) {
-        station_addr = parse->version_1.str + parse->version_1.ofs[3];
+    if (link->prod_id[3]) {
+        station_addr = link->prod_id[3];
         if (cvt_ascii_address(dev, station_addr) == 0) {
                 rc = 0;
                 goto free_cfg_mem;
@@ -744,15 +736,12 @@ static int smc_setup(struct pcmcia_device *link)
         }
     }
     /* Try the third string in the Version 1 Version/ID tuple. */
-    tuple->DesiredTuple = CISTPL_VERS_1;
-    if (first_tuple(link, tuple, parse) != CS_SUCCESS) {
-        rc = -1;
-        goto free_cfg_mem;
-    }
-    station_addr = parse->version_1.str + parse->version_1.ofs[2];
-    if (cvt_ascii_address(dev, station_addr) == 0) {
-        rc = 0;
-        goto free_cfg_mem;
+    if (link->prod_id[2]) {
+        station_addr = link->prod_id[2];
+        if (cvt_ascii_address(dev, station_addr) == 0) {
+                rc = 0;
+                goto free_cfg_mem;
+        }
     }
 
     rc = -1;
@@ -970,10 +959,6 @@ static int smc91c92_config(struct pcmcia_device *link)
 {
     struct net_device *dev = link->priv;
     struct smc_private *smc = netdev_priv(dev);
-    struct smc_cfg_mem *cfg_mem;
-    tuple_t *tuple;
-    cisparse_t *parse;
-    u_char *buf;
     char *name;
     int i, j, rev;
     kio_addr_t ioaddr;
@@ -981,30 +966,8 @@ static int smc91c92_config(struct pcmcia_device *link)
 
     DEBUG(0, "smc91c92_config(0x%p)\n", link);
 
-    cfg_mem = kmalloc(sizeof(struct smc_cfg_mem), GFP_KERNEL);
-    if (!cfg_mem)
-        goto config_failed;
-
-    tuple = &cfg_mem->tuple;
-    parse = &cfg_mem->parse;
-    buf = cfg_mem->buf;
-
-    tuple->Attributes = tuple->TupleOffset = 0;
-    tuple->TupleData = (cisdata_t *)buf;
-    tuple->TupleDataMax = 64;
-
-    tuple->DesiredTuple = CISTPL_CONFIG;
-    i = first_tuple(link, tuple, parse);
-    CS_EXIT_TEST(i, ParseTuple, config_failed);
-    link->conf.ConfigBase = parse->config.base;
-    link->conf.Present = parse->config.rmask[0];
-
-    tuple->DesiredTuple = CISTPL_MANFID;
-    tuple->Attributes = TUPLE_RETURN_COMMON;
-    if (first_tuple(link, tuple, parse) == CS_SUCCESS) {
-        smc->manfid = parse->manfid.manf;
-        smc->cardid = parse->manfid.card;
-    }
+    smc->manfid = link->manf_id;
+    smc->cardid = link->card_id;
 
     if ((smc->manfid == MANFID_OSITECH) &&
         (smc->cardid != PRODID_OSITECH_SEVEN)) {
@@ -1134,14 +1097,12 @@ static int smc91c92_config(struct pcmcia_device *link)
             printk(KERN_NOTICE "  No MII transceivers found!\n");
         }
     }
-    kfree(cfg_mem);
     return 0;
 
 config_undo:
     unregister_netdev(dev);
 config_failed:                  /* CS_EXIT_TEST() calls jump to here... */
     smc91c92_release(link);
-    kfree(cfg_mem);
     return -ENODEV;
 } /* smc91c92_config */
 
diff --git a/drivers/net/pcmcia/xirc2ps_cs.c b/drivers/net/pcmcia/xirc2ps_cs.c
index f3914f58d67f..8478dca3d8d1 100644
--- a/drivers/net/pcmcia/xirc2ps_cs.c
+++ b/drivers/net/pcmcia/xirc2ps_cs.c
@@ -332,6 +332,7 @@ static irqreturn_t xirc2ps_interrupt(int irq, void *dev_id);
  */
 
 typedef struct local_info_t {
+        struct net_device       *dev;
         struct pcmcia_device    *p_dev;
     dev_node_t node;
     struct net_device_stats stats;
@@ -353,7 +354,7 @@ typedef struct local_info_t {
  */
 static int do_start_xmit(struct sk_buff *skb, struct net_device *dev);
 static void do_tx_timeout(struct net_device *dev);
-static void xirc2ps_tx_timeout_task(void *data);
+static void xirc2ps_tx_timeout_task(struct work_struct *work);
 static struct net_device_stats *do_get_stats(struct net_device *dev);
 static void set_addresses(struct net_device *dev);
 static void set_multicast_list(struct net_device *dev);
@@ -567,6 +568,7 @@ xirc2ps_probe(struct pcmcia_device *link)
     if (!dev)
             return -ENOMEM;
     local = netdev_priv(dev);
+    local->dev = dev;
     local->p_dev = link;
     link->priv = dev;
 
@@ -591,7 +593,7 @@ xirc2ps_probe(struct pcmcia_device *link)
 #ifdef HAVE_TX_TIMEOUT
     dev->tx_timeout = do_tx_timeout;
     dev->watchdog_timeo = TX_TIMEOUT;
-    INIT_WORK(&local->tx_timeout_task, xirc2ps_tx_timeout_task, dev);
+    INIT_WORK(&local->tx_timeout_task, xirc2ps_tx_timeout_task);
 #endif
 
     return xirc2ps_config(link);
@@ -707,22 +709,11 @@ set_card_type(struct pcmcia_device *link, const void *s)
  * Returns: true if this is a CE2
  */
 static int
-has_ce2_string(struct pcmcia_device * link)
+has_ce2_string(struct pcmcia_device * p_dev)
 {
-    tuple_t tuple;
-    cisparse_t parse;
-    u_char buf[256];
-
-    tuple.Attributes = 0;
-    tuple.TupleData = buf;
-    tuple.TupleDataMax = 254;
-    tuple.TupleOffset = 0;
-    tuple.DesiredTuple = CISTPL_VERS_1;
-    if (!first_tuple(link, &tuple, &parse) && parse.version_1.ns > 2) {
-        if (strstr(parse.version_1.str + parse.version_1.ofs[2], "CE2"))
-            return 1;
-    }
-    return 0;
+        if (p_dev->prod_id[2] && strstr(p_dev->prod_id[2], "CE2"))
+                return 1;
+        return 0;
 }
 
 /****************
@@ -792,13 +783,6 @@ xirc2ps_config(struct pcmcia_device * link)
         goto failure;
     }
 
-    /* get configuration stuff */
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    if ((err=first_tuple(link, &tuple, &parse)))
-        goto cis_error;
-    link->conf.ConfigBase = parse.config.base;
-    link->conf.Present =    parse.config.rmask[0];
-
     /* get the ethernet address from the CIS */
     tuple.DesiredTuple = CISTPL_FUNCE;
     for (err = first_tuple(link, &tuple, &parse); !err;
@@ -1062,8 +1046,6 @@ xirc2ps_config(struct pcmcia_device * link)
     xirc2ps_release(link);
     return -ENODEV;
 
-  cis_error:
-    printk(KNOT_XIRC "unable to parse CIS\n");
   failure:
     return -ENODEV;
 } /* xirc2ps_config */
@@ -1344,9 +1326,11 @@ xirc2ps_interrupt(int irq, void *dev_id)
 /*====================================================================*/
 
 static void
-xirc2ps_tx_timeout_task(void *data)
+xirc2ps_tx_timeout_task(struct work_struct *work)
 {
-    struct net_device *dev = data;
+        local_info_t *local =
+                container_of(work, local_info_t, tx_timeout_task);
+        struct net_device *dev = local->dev;
     /* reset the card */
     do_reset(dev,1);
     dev->trans_start = jiffies;
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index f14e99276dba..096d4a100bf2 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -254,7 +254,7 @@ static int fixed_mdio_register_device(int number, int speed, int duplex)
                 goto device_create_fail;
         }
 
-        phydev->irq = -1;
+        phydev->irq = PHY_IGNORE_INTERRUPT;
         phydev->dev.bus = &mdio_bus_type;
 
         if(number)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 88237bdb5255..4044bb1ada86 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -397,7 +397,7 @@ out_unlock:
 EXPORT_SYMBOL(phy_start_aneg);
 
 
-static void phy_change(void *data);
+static void phy_change(struct work_struct *work);
 static void phy_timer(unsigned long data);
 
 /* phy_start_machine:
@@ -555,7 +555,7 @@ int phy_start_interrupts(struct phy_device *phydev)
 {
         int err = 0;
 
-        INIT_WORK(&phydev->phy_queue, phy_change, phydev);
+        INIT_WORK(&phydev->phy_queue, phy_change);
 
         if (request_irq(phydev->irq, phy_interrupt,
                                 IRQF_SHARED,
@@ -598,10 +598,11 @@ EXPORT_SYMBOL(phy_stop_interrupts);
 
 
 /* Scheduled by the phy_interrupt/timer to handle PHY changes */
-static void phy_change(void *data)
+static void phy_change(struct work_struct *work)
 {
         int err;
-        struct phy_device *phydev = data;
+        struct phy_device *phydev =
+                container_of(work, struct phy_device, phy_queue);
 
         err = phy_disable_interrupts(phydev);
 
diff --git a/drivers/net/plip.c b/drivers/net/plip.c
index 71afb274498f..6bb085f54437 100644
--- a/drivers/net/plip.c
+++ b/drivers/net/plip.c
@@ -138,9 +138,9 @@ static const unsigned int net_debug = NET_DEBUG;
 #define PLIP_NIBBLE_WAIT        3000
 
 /* Bottom halves */
-static void plip_kick_bh(struct net_device *dev);
-static void plip_bh(struct net_device *dev);
-static void plip_timer_bh(struct net_device *dev);
+static void plip_kick_bh(struct work_struct *work);
+static void plip_bh(struct work_struct *work);
+static void plip_timer_bh(struct work_struct *work);
 
 /* Interrupt handler */
 static void plip_interrupt(int irq, void *dev_id);
@@ -207,9 +207,10 @@ struct plip_local {
 
 struct net_local {
         struct net_device_stats enet_stats;
+        struct net_device *dev;
         struct work_struct immediate;
-        struct work_struct deferred;
-        struct work_struct timer;
+        struct delayed_work deferred;
+        struct delayed_work timer;
         struct plip_local snd_data;
         struct plip_local rcv_data;
         struct pardevice *pardev;
@@ -306,11 +307,11 @@ plip_init_netdev(struct net_device *dev)
         nl->nibble      = PLIP_NIBBLE_WAIT;
 
         /* Initialize task queue structures */
-        INIT_WORK(&nl->immediate, (void (*)(void *))plip_bh, dev);
-        INIT_WORK(&nl->deferred, (void (*)(void *))plip_kick_bh, dev);
+        INIT_WORK(&nl->immediate, plip_bh);
+        INIT_DELAYED_WORK(&nl->deferred, plip_kick_bh);
 
         if (dev->irq == -1)
-                INIT_WORK(&nl->timer, (void (*)(void *))plip_timer_bh, dev);
+                INIT_DELAYED_WORK(&nl->timer, plip_timer_bh);
 
         spin_lock_init(&nl->lock);
 }
@@ -319,9 +320,10 @@ plip_init_netdev(struct net_device *dev)
    This routine is kicked by do_timer().
    Request `plip_bh' to be invoked. */
 static void
-plip_kick_bh(struct net_device *dev)
+plip_kick_bh(struct work_struct *work)
 {
-        struct net_local *nl = netdev_priv(dev);
+        struct net_local *nl =
+                container_of(work, struct net_local, deferred.work);
 
         if (nl->is_deferred)
                 schedule_work(&nl->immediate);
@@ -362,9 +364,9 @@ static const plip_func connection_state_table[] =
 
 /* Bottom half handler of PLIP. */
 static void
-plip_bh(struct net_device *dev)
+plip_bh(struct work_struct *work)
 {
-        struct net_local *nl = netdev_priv(dev);
+        struct net_local *nl = container_of(work, struct net_local, immediate);
         struct plip_local *snd = &nl->snd_data;
         struct plip_local *rcv = &nl->rcv_data;
         plip_func f;
@@ -372,20 +374,21 @@ plip_bh(struct net_device *dev)
 
         nl->is_deferred = 0;
         f = connection_state_table[nl->connection];
-        if ((r = (*f)(dev, nl, snd, rcv)) != OK
-            && (r = plip_bh_timeout_error(dev, nl, snd, rcv, r)) != OK) {
+        if ((r = (*f)(nl->dev, nl, snd, rcv)) != OK
+            && (r = plip_bh_timeout_error(nl->dev, nl, snd, rcv, r)) != OK) {
                 nl->is_deferred = 1;
                 schedule_delayed_work(&nl->deferred, 1);
         }
 }
 
 static void
-plip_timer_bh(struct net_device *dev)
+plip_timer_bh(struct work_struct *work)
 {
-        struct net_local *nl = netdev_priv(dev);
+        struct net_local *nl =
+                container_of(work, struct net_local, timer.work);
 
         if (!(atomic_read (&nl->kill_timer))) {
-                plip_interrupt (-1, dev);
+                plip_interrupt (-1, nl->dev);
 
                 schedule_delayed_work(&nl->timer, 1);
         }
@@ -1284,6 +1287,7 @@ static void plip_attach (struct parport *port)
                 }
 
                 nl = netdev_priv(dev);
+                nl->dev = dev;
                 nl->pardev = parport_register_device(port, name, plip_preempt,
                                                  plip_wakeup, plip_interrupt,
                                                  0, dev);
diff --git a/drivers/net/pppoe.c b/drivers/net/pppoe.c
index 0adee733b761..315d5c3fc66a 100644
--- a/drivers/net/pppoe.c
+++ b/drivers/net/pppoe.c
@@ -393,7 +393,7 @@ static int pppoe_rcv(struct sk_buff *skb,
 
         po = get_item((unsigned long) ph->sid, eth_hdr(skb)->h_source);
         if (po != NULL)
-                return sk_receive_skb(sk_pppox(po), skb);
+                return sk_receive_skb(sk_pppox(po), skb, 0);
 drop:
         kfree_skb(skb);
 out:
diff --git a/drivers/net/qla3xxx.c b/drivers/net/qla3xxx.c
index ec640f6229ae..d79d141a601d 100644
--- a/drivers/net/qla3xxx.c
+++ b/drivers/net/qla3xxx.c
@@ -2008,7 +2008,7 @@ static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
                                "%s: Another function issued a reset to the "
                                "chip. ISR value = %x.\n", ndev->name, value);
                 }
-                queue_work(qdev->workqueue, &qdev->reset_work);
+                queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
                 spin_unlock(&qdev->adapter_lock);
         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
                 ql_disable_interrupts(qdev);
@@ -3182,11 +3182,13 @@ static void ql3xxx_tx_timeout(struct net_device *ndev)
         /*
          * Wake up the worker to process this event.
          */
-        queue_work(qdev->workqueue, &qdev->tx_timeout_work);
+        queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
 }
 
-static void ql_reset_work(struct ql3_adapter *qdev)
+static void ql_reset_work(struct work_struct *work)
 {
+        struct ql3_adapter *qdev =
+                container_of(work, struct ql3_adapter, reset_work.work);
         struct net_device *ndev = qdev->ndev;
         u32 value;
         struct ql_tx_buf_cb *tx_cb;
@@ -3278,9 +3280,12 @@ static void ql_reset_work(struct ql3_adapter *qdev)
         }
 }
 
-static void ql_tx_timeout_work(struct ql3_adapter *qdev)
+static void ql_tx_timeout_work(struct work_struct *work)
 {
-        ql_cycle_adapter(qdev,QL_DO_RESET);
+        struct ql3_adapter *qdev =
+                container_of(work, struct ql3_adapter, tx_timeout_work.work);
+
+        ql_cycle_adapter(qdev, QL_DO_RESET);
 }
 
 static void ql_get_board_info(struct ql3_adapter *qdev)
@@ -3459,9 +3464,8 @@ static int __devinit ql3xxx_probe(struct pci_dev *pdev,
         netif_stop_queue(ndev);
 
         qdev->workqueue = create_singlethread_workqueue(ndev->name);
-        INIT_WORK(&qdev->reset_work, (void (*)(void *))ql_reset_work, qdev);
-        INIT_WORK(&qdev->tx_timeout_work,
-                  (void (*)(void *))ql_tx_timeout_work, qdev);
+        INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
+        INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
 
         init_timer(&qdev->adapter_timer);
         qdev->adapter_timer.function = ql3xxx_timer;
diff --git a/drivers/net/qla3xxx.h b/drivers/net/qla3xxx.h
index 65da2c0bfda6..ea94de7fd071 100644
--- a/drivers/net/qla3xxx.h
+++ b/drivers/net/qla3xxx.h
@@ -1186,8 +1186,8 @@ struct ql3_adapter {
         u32 numPorts;
         struct net_device_stats stats;
         struct workqueue_struct *workqueue;
-        struct work_struct reset_work;
-        struct work_struct tx_timeout_work;
+        struct delayed_work reset_work;
+        struct delayed_work tx_timeout_work;
         u32 max_frame_size;
 };
 
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 2379d83768d6..f83b41d4cb0e 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -425,6 +425,7 @@ struct ring_info {
 struct rtl8169_private {
         void __iomem *mmio_addr;        /* memory map physical address */
         struct pci_dev *pci_dev;        /* Index of PCI device */
+        struct net_device *dev;
         struct net_device_stats stats;  /* statistics of net device */
         spinlock_t lock;                /* spin lock flag */
         u32 msg_enable;
@@ -456,7 +457,7 @@ struct rtl8169_private {
         void (*phy_reset_enable)(void __iomem *);
         unsigned int (*phy_reset_pending)(void __iomem *);
         unsigned int (*link_ok)(void __iomem *);
-        struct work_struct task;
+        struct delayed_work task;
         unsigned wol_enabled : 1;
 };
 
@@ -1508,6 +1509,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         SET_MODULE_OWNER(dev);
         SET_NETDEV_DEV(dev, &pdev->dev);
         tp = netdev_priv(dev);
+        tp->dev = dev;
         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
 
         /* enable device (incl. PCI PM wakeup and hotplug setup) */
@@ -1780,7 +1782,7 @@ static int rtl8169_open(struct net_device *dev)
         if (retval < 0)
                 goto err_free_rx;
 
-        INIT_WORK(&tp->task, NULL, dev);
+        INIT_DELAYED_WORK(&tp->task, NULL);
 
         rtl8169_hw_start(dev);
 
@@ -2133,11 +2135,11 @@ static void rtl8169_tx_clear(struct rtl8169_private *tp)
         tp->cur_tx = tp->dirty_tx = 0;
 }
 
-static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
+static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
 
-        PREPARE_WORK(&tp->task, task, dev);
+        PREPARE_DELAYED_WORK(&tp->task, task);
         schedule_delayed_work(&tp->task, 4);
 }
 
@@ -2156,9 +2158,11 @@ static void rtl8169_wait_for_quiescence(struct net_device *dev)
         netif_poll_enable(dev);
 }
 
-static void rtl8169_reinit_task(void *_data)
+static void rtl8169_reinit_task(struct work_struct *work)
 {
-        struct net_device *dev = _data;
+        struct rtl8169_private *tp =
+                container_of(work, struct rtl8169_private, task.work);
+        struct net_device *dev = tp->dev;
         int ret;
 
         if (netif_running(dev)) {
@@ -2181,10 +2185,11 @@ static void rtl8169_reinit_task(void *_data)
         }
 }
 
-static void rtl8169_reset_task(void *_data)
+static void rtl8169_reset_task(struct work_struct *work)
 {
-        struct net_device *dev = _data;
-        struct rtl8169_private *tp = netdev_priv(dev);
+        struct rtl8169_private *tp =
+                container_of(work, struct rtl8169_private, task.work);
+        struct net_device *dev = tp->dev;
 
         if (!netif_running(dev))
                 return;
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index 33569ec9dbfc..250cdbeefdfd 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -5872,9 +5872,9 @@ static void s2io_tasklet(unsigned long dev_addr)
  * Description: Sets the link status for the adapter
  */
 
-static void s2io_set_link(unsigned long data)
+static void s2io_set_link(struct work_struct *work)
 {
-        nic_t *nic = (nic_t *) data;
+        nic_t *nic = container_of(work, nic_t, set_link_task);
         struct net_device *dev = nic->dev;
         XENA_dev_config_t __iomem *bar0 = nic->bar0;
         register u64 val64;
@@ -6379,10 +6379,10 @@ static int s2io_card_up(nic_t * sp)
  * spin lock.
  */
 
-static void s2io_restart_nic(unsigned long data)
+static void s2io_restart_nic(struct work_struct *work)
 {
-        struct net_device *dev = (struct net_device *) data;
-        nic_t *sp = dev->priv;
+        nic_t *sp = container_of(work, nic_t, rst_timer_task);
+        struct net_device *dev = sp->dev;
 
         s2io_card_down(sp);
         if (s2io_card_up(sp)) {
@@ -6992,10 +6992,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
 
         dev->tx_timeout = &s2io_tx_watchdog;
         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
-        INIT_WORK(&sp->rst_timer_task,
-                  (void (*)(void *)) s2io_restart_nic, dev);
-        INIT_WORK(&sp->set_link_task,
-                  (void (*)(void *)) s2io_set_link, sp);
+        INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
+        INIT_WORK(&sp->set_link_task, s2io_set_link);
 
         pci_save_state(sp->pdev);
 
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 12b719f4d00f..3b0bafd273c8 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -1000,7 +1000,7 @@ s2io_msix_fifo_handle(int irq, void *dev_id);
 static irqreturn_t s2io_isr(int irq, void *dev_id);
 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
 static const struct ethtool_ops netdev_ethtool_ops;
-static void s2io_set_link(unsigned long data);
+static void s2io_set_link(struct work_struct *work);
 static int s2io_set_swapper(nic_t * sp);
 static void s2io_card_down(nic_t *nic);
 static int s2io_card_up(nic_t *nic);
diff --git a/drivers/net/seeq8005.c b/drivers/net/seeq8005.c
index d9d0a3a3c558..0d6c95c7aedf 100644
--- a/drivers/net/seeq8005.c
+++ b/drivers/net/seeq8005.c
@@ -750,7 +750,7 @@ int __init init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(dev_seeq);
         release_region(dev_seeq->base_addr, SEEQ8005_IO_EXTENT);
diff --git a/drivers/net/sis190.c b/drivers/net/sis190.c
index aaba458584fb..b70ed79d4121 100644
--- a/drivers/net/sis190.c
+++ b/drivers/net/sis190.c
@@ -280,6 +280,7 @@ enum sis190_feature {
 struct sis190_private {
         void __iomem *mmio_addr;
         struct pci_dev *pci_dev;
+        struct net_device *dev;
         struct net_device_stats stats;
         spinlock_t lock;
         u32 rx_buf_sz;
@@ -897,10 +898,11 @@ static void sis190_hw_start(struct net_device *dev)
         netif_start_queue(dev);
 }
 
-static void sis190_phy_task(void * data)
+static void sis190_phy_task(struct work_struct *work)
 {
-        struct net_device *dev = data;
-        struct sis190_private *tp = netdev_priv(dev);
+        struct sis190_private *tp =
+                container_of(work, struct sis190_private, phy_task);
+        struct net_device *dev = tp->dev;
         void __iomem *ioaddr = tp->mmio_addr;
         int phy_id = tp->mii_if.phy_id;
         u16 val;
@@ -1047,7 +1049,7 @@ static int sis190_open(struct net_device *dev)
         if (rc < 0)
                 goto err_free_rx_1;
 
-        INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
+        INIT_WORK(&tp->phy_task, sis190_phy_task);
 
         sis190_request_timer(dev);
 
@@ -1436,6 +1438,7 @@ static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
         SET_NETDEV_DEV(dev, &pdev->dev);
 
         tp = netdev_priv(dev);
+        tp->dev = dev;
         tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
 
         rc = pci_enable_device(pdev);
@@ -1798,7 +1801,7 @@ static int __devinit sis190_init_one(struct pci_dev *pdev,
 
         sis190_init_rxfilter(dev);
 
-        INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
+        INIT_WORK(&tp->phy_task, sis190_phy_task);
 
         dev->open = sis190_open;
         dev->stop = sis190_close;
diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c
index a5d41ebc9fb4..92d11b961db8 100644
--- a/drivers/net/sk98lin/skge.c
+++ b/drivers/net/sk98lin/skge.c
@@ -114,6 +114,7 @@
 #include        <linux/dma-mapping.h>
 #include        <linux/ip.h>
 #include        <linux/mii.h>
+#include        <linux/mm.h>
 
 #include        "h/skdrv1st.h"
 #include        "h/skdrv2nd.h"
@@ -1562,7 +1563,7 @@ struct sk_buff	*pMessage)	/* pointer to send-message              */
 
         if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
                 u16 hdrlen = pMessage->h.raw - pMessage->data;
-                u16 offset = hdrlen + pMessage->csum;
+                u16 offset = hdrlen + pMessage->csum_offset;
 
                 if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
                         (pAC->GIni.GIChipRev == 0) &&
@@ -1681,7 +1682,7 @@ struct sk_buff	*pMessage)	/* pointer to send-message              */
         */
         if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
                 u16 hdrlen = pMessage->h.raw - pMessage->data;
-                u16 offset = hdrlen + pMessage->csum;
+                u16 offset = hdrlen + pMessage->csum_offset;
 
                 Control = BMU_STFWD;
 
diff --git a/drivers/net/sk98lin/skgesirq.c b/drivers/net/sk98lin/skgesirq.c
index ab66d80a4455..3e7aa49afd00 100644
--- a/drivers/net/sk98lin/skgesirq.c
+++ b/drivers/net/sk98lin/skgesirq.c
@@ -1319,7 +1319,7 @@ SK_BOOL	AutoNeg)	/* Is Auto-negotiation used ? */
         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc);
 
 #ifdef xDEBUG
-        if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) ==
+        if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) ==
                 (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) {
 
                 SK_U32  Stat1, Stat2, Stat3;
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 27b537c8d5e3..b60f0451f6cd 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -1327,10 +1327,11 @@ static void xm_check_link(struct net_device *dev)
  * Since internal PHY is wired to a level triggered pin, can't
  * get an interrupt when carrier is detected.
  */
-static void xm_link_timer(void *arg)
+static void xm_link_timer(struct work_struct *work)
 {
-        struct net_device *dev = arg;
-        struct skge_port *skge = netdev_priv(arg);
+        struct skge_port *skge =
+                container_of(work, struct skge_port, link_thread.work);
+        struct net_device *dev = skge->netdev;
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
 
@@ -2565,7 +2566,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
 
                 td->csum_offs = 0;
                 td->csum_start = offset;
-                td->csum_write = offset + skb->csum;
+                td->csum_write = offset + skb->csum_offset;
         } else
                 control = BMU_CHECK;
 
@@ -3072,9 +3073,9 @@ static void skge_error_irq(struct skge_hw *hw)
  * because accessing phy registers requires spin wait which might
  * cause excess interrupt latency.
  */
-static void skge_extirq(void *arg)
+static void skge_extirq(struct work_struct *work)
 {
-        struct skge_hw *hw = arg;
+        struct skge_hw *hw = container_of(work, struct skge_hw, phy_work);
         int port;
 
         mutex_lock(&hw->phy_mutex);
@@ -3456,7 +3457,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
         skge->port = port;
 
         /* Only used for Genesis XMAC */
-        INIT_WORK(&skge->link_thread, xm_link_timer, dev);
+        INIT_DELAYED_WORK(&skge->link_thread, xm_link_timer);
 
         if (hw->chip_id != CHIP_ID_GENESIS) {
                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
@@ -3543,7 +3544,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
 
         hw->pdev = pdev;
         mutex_init(&hw->phy_mutex);
-        INIT_WORK(&hw->phy_work, skge_extirq, hw);
+        INIT_WORK(&hw->phy_work, skge_extirq);
         spin_lock_init(&hw->hw_lock);
 
         hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index 537c0aaa1db8..f6223c533c01 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -389,10 +389,10 @@ enum {
 /* Packet Arbiter Registers */
 /*      B3_PA_CTRL              16 bit  Packet Arbiter Ctrl Register */
 enum {
-        PA_CLR_TO_TX2   = 1<<13,        /* Clear IRQ Packet Timeout TX2 */
-        PA_CLR_TO_TX1   = 1<<12,        /* Clear IRQ Packet Timeout TX1 */
-        PA_CLR_TO_RX2   = 1<<11,        /* Clear IRQ Packet Timeout RX2 */
-        PA_CLR_TO_RX1   = 1<<10,        /* Clear IRQ Packet Timeout RX1 */
+        PA_CLR_TO_TX2   = 1<<13,/* Clear IRQ Packet Timeout TX2 */
+        PA_CLR_TO_TX1   = 1<<12,/* Clear IRQ Packet Timeout TX1 */
+        PA_CLR_TO_RX2   = 1<<11,/* Clear IRQ Packet Timeout RX2 */
+        PA_CLR_TO_RX1   = 1<<10,/* Clear IRQ Packet Timeout RX1 */
         PA_ENA_TO_TX2   = 1<<9, /* Enable  Timeout Timer TX2 */
         PA_DIS_TO_TX2   = 1<<8, /* Disable Timeout Timer TX2 */
         PA_ENA_TO_TX1   = 1<<7, /* Enable  Timeout Timer TX1 */
@@ -481,14 +481,14 @@ enum {
 /* RAM Buffer Register Offsets */
 enum {
 
-        RB_START        = 0x00,/* 32 bit        RAM Buffer Start Address */
+        RB_START= 0x00,/* 32 bit        RAM Buffer Start Address */
         RB_END  = 0x04,/* 32 bit        RAM Buffer End Address */
         RB_WP   = 0x08,/* 32 bit        RAM Buffer Write Pointer */
         RB_RP   = 0x0c,/* 32 bit        RAM Buffer Read Pointer */
-        RB_RX_UTPP      = 0x10,/* 32 bit        Rx Upper Threshold, Pause Packet */
-        RB_RX_LTPP      = 0x14,/* 32 bit        Rx Lower Threshold, Pause Packet */
-        RB_RX_UTHP      = 0x18,/* 32 bit        Rx Upper Threshold, High Prio */
-        RB_RX_LTHP      = 0x1c,/* 32 bit        Rx Lower Threshold, High Prio */
+        RB_RX_UTPP= 0x10,/* 32 bit      Rx Upper Threshold, Pause Packet */
+        RB_RX_LTPP= 0x14,/* 32 bit      Rx Lower Threshold, Pause Packet */
+        RB_RX_UTHP= 0x18,/* 32 bit      Rx Upper Threshold, High Prio */
+        RB_RX_LTHP= 0x1c,/* 32 bit      Rx Lower Threshold, High Prio */
         /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
         RB_PC   = 0x20,/* 32 bit        RAM Buffer Packet Counter */
         RB_LEV  = 0x24,/* 32 bit        RAM Buffer Level Register */
@@ -532,7 +532,7 @@ enum {
         PHY_ADDR_MARV   = 0,
 };
 
-#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
+#define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
 
 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
 enum {
@@ -578,15 +578,15 @@ enum {
         MFF_DIS_TIST    = 1<<2, /* Disable Time Stamp Gener */
         MFF_CLR_INTIST  = 1<<1, /* Clear IRQ No Time Stamp */
         MFF_CLR_INSTAT  = 1<<0, /* Clear IRQ No Status */
-#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
+        MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
 };
 
 /*      TX_MFF_CTRL1    16 bit  Transmit MAC FIFO Control Reg 1 */
 enum {
-        MFF_CLR_PERR    = 1<<15,        /* Clear Parity Error IRQ */
-                                                                /* Bit 14:      reserved */
-        MFF_ENA_PKT_REC = 1<<13,        /* Enable  Packet Recovery */
-        MFF_DIS_PKT_REC = 1<<12,        /* Disable Packet Recovery */
+        MFF_CLR_PERR    = 1<<15, /* Clear Parity Error IRQ */
+
+        MFF_ENA_PKT_REC = 1<<13, /* Enable  Packet Recovery */
+        MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
 
         MFF_ENA_W4E     = 1<<7, /* Enable  Wait for Empty */
         MFF_DIS_W4E     = 1<<6, /* Disable Wait for Empty */
@@ -595,9 +595,10 @@ enum {
         MFF_DIS_LOOPB   = 1<<2, /* Disable Loopback */
         MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
         MFF_SET_MAC_RST = 1<<0, /* Set   XMAC Reset */
+
+        MFF_TX_CTRL_DEF  = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
 };
 
-#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
 
 /*      RX_MFF_TST2              8 bit  Receive MAC FIFO Test Register 2 */
 /*      TX_MFF_TST2              8 bit  Transmit MAC FIFO Test Register 2 */
@@ -1304,8 +1305,8 @@ enum {
 
 /* special defines for FIBER (88E1011S only) */
 enum {
-        PHY_M_AN_ASP_X  = 1<<8, /* Asymmetric Pause */
-        PHY_M_AN_PC_X   = 1<<7, /* MAC Pause implemented */
+        PHY_M_AN_ASP_X          = 1<<8, /* Asymmetric Pause */
+        PHY_M_AN_PC_X           = 1<<7, /* MAC Pause implemented */
         PHY_M_AN_1000X_AHD      = 1<<6, /* Advertise 10000Base-X Half Duplex */
         PHY_M_AN_1000X_AFD      = 1<<5, /* Advertise 10000Base-X Full Duplex */
 };
@@ -1320,7 +1321,7 @@ enum {
 
 /*****  PHY_MARV_1000T_CTRL     16 bit r/w      1000Base-T Control Reg *****/
 enum {
-        PHY_M_1000C_TEST        = 7<<13,/* Bit 15..13:  Test Modes */
+        PHY_M_1000C_TEST= 7<<13,/* Bit 15..13:  Test Modes */
         PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
         PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
         PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
@@ -1349,7 +1350,7 @@ enum {
         PHY_M_PC_EN_DET_PLUS    = 3<<8, /* Energy Detect Plus (Mode 2) */
 };
 
-#define PHY_M_PC_MDI_XMODE(x)   (((x)<<5) & PHY_M_PC_MDIX_MSK)
+#define PHY_M_PC_MDI_XMODE(x)   ((((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
 
 enum {
         PHY_M_PC_MAN_MDI        = 0, /* 00 = Manual MDI configuration */
@@ -1432,24 +1433,24 @@ enum {
         PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
         PHY_M_EC_M_DSC_MSK  = 3<<10, /* Bit 11..10:     Master Downshift Counter */
                                         /* (88E1011 only) */
-        PHY_M_EC_S_DSC_MSK      = 3<<8,/* Bit  9.. 8:   Slave  Downshift Counter */
+        PHY_M_EC_S_DSC_MSK  = 3<<8,  /* Bit  9.. 8:     Slave  Downshift Counter */
                                        /* (88E1011 only) */
-        PHY_M_EC_M_DSC_MSK2     = 7<<9,/* Bit 11.. 9:   Master Downshift Counter */
+        PHY_M_EC_M_DSC_MSK2  = 7<<9, /* Bit 11.. 9:     Master Downshift Counter */
                                         /* (88E1111 only) */
-        PHY_M_EC_DOWN_S_ENA     = 1<<8, /* Downshift Enable (88E1111 only) */
+        PHY_M_EC_DOWN_S_ENA  = 1<<8, /* Downshift Enable (88E1111 only) */
                                         /* !!! Errata in spec. (1 = disable) */
-        PHY_M_EC_RX_TIM_CT      = 1<<7, /* RGMII Rx Timing Control*/
-        PHY_M_EC_MAC_S_MSK      = 7<<4,/* Bit  6.. 4:   Def. MAC interface speed */
-        PHY_M_EC_FIB_AN_ENA     = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
-        PHY_M_EC_DTE_D_ENA      = 1<<2, /* DTE Detect Enable (88E1111 only) */
-        PHY_M_EC_TX_TIM_CT      = 1<<1, /* RGMII Tx Timing Control */
-        PHY_M_EC_TRANS_DIS      = 1<<0, /* Transmitter Disable (88E1111 only) */};
-
-#define PHY_M_EC_M_DSC(x)       ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
-#define PHY_M_EC_S_DSC(x)       ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
-#define PHY_M_EC_MAC_S(x)       ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
-
-#define PHY_M_EC_M_DSC_2(x)     ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
+        PHY_M_EC_RX_TIM_CT   = 1<<7, /* RGMII Rx Timing Control*/
+        PHY_M_EC_MAC_S_MSK   = 7<<4, /* Bit  6.. 4:     Def. MAC interface speed */
+        PHY_M_EC_FIB_AN_ENA  = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
+        PHY_M_EC_DTE_D_ENA   = 1<<2, /* DTE Detect Enable (88E1111 only) */
+        PHY_M_EC_TX_TIM_CT   = 1<<1, /* RGMII Tx Timing Control */
+        PHY_M_EC_TRANS_DIS   = 1<<0, /* Transmitter Disable (88E1111 only) */};
+
+#define PHY_M_EC_M_DSC(x)       ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
+#define PHY_M_EC_S_DSC(x)       ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
+#define PHY_M_EC_MAC_S(x)       ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
+
+#define PHY_M_EC_M_DSC_2(x)     ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
                                                                                         /* 100=5x; 101=6x; 110=7x; 111=8x */
 enum {
         MAC_TX_CLK_0_MHZ        = 2,
@@ -1468,10 +1469,12 @@ enum {
         PHY_M_LEDC_LK_C_MSK     = 7<<3,/* Bit  5.. 3: Link Control Mask */
                                         /* (88E1111 only) */
 };
+#define PHY_M_LED_PULS_DUR(x)   (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
+#define PHY_M_LED_BLINK_RT(x)   (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
 
 enum {
-        PHY_M_LEDC_LINK_MSK     = 3<<3,/* Bit  4.. 3: Link Control Mask */
-                                                                        /* (88E1011 only) */
+        PHY_M_LEDC_LINK_MSK     = 3<<3, /* Bit  4.. 3: Link Control Mask */
+                                        /* (88E1011 only) */
         PHY_M_LEDC_DP_CTRL      = 1<<2, /* Duplex Control */
         PHY_M_LEDC_DP_C_MSB     = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
         PHY_M_LEDC_RX_CTRL      = 1<<1, /* Rx Activity / Link */
@@ -1479,27 +1482,24 @@ enum {
         PHY_M_LEDC_TX_C_MSB     = 1<<0, /* Tx Control (MSB, 88E1111 only) */
 };
 
-#define PHY_M_LED_PULS_DUR(x)   (((x)<<12) & PHY_M_LEDC_PULS_MSK)
-
 enum {
-        PULS_NO_STR     = 0,/* no pulse stretching */
-        PULS_21MS       = 1,/* 21 ms to 42 ms */
-        PULS_42MS       = 2,/* 42 ms to 84 ms */
-        PULS_84MS       = 3,/* 84 ms to 170 ms */
-        PULS_170MS      = 4,/* 170 ms to 340 ms */
-        PULS_340MS      = 5,/* 340 ms to 670 ms */
-        PULS_670MS      = 6,/* 670 ms to 1.3 s */
-        PULS_1300MS     = 7,/* 1.3 s to 2.7 s */
+        PULS_NO_STR     = 0, /* no pulse stretching */
+        PULS_21MS       = 1, /* 21 ms to 42 ms */
+        PULS_42MS       = 2, /* 42 ms to 84 ms */
+        PULS_84MS       = 3, /* 84 ms to 170 ms */
+        PULS_170MS      = 4, /* 170 ms to 340 ms */
+        PULS_340MS      = 5, /* 340 ms to 670 ms */
+        PULS_670MS      = 6, /* 670 ms to 1.3 s */
+        PULS_1300MS     = 7, /* 1.3 s to 2.7 s */
 };
 
-#define PHY_M_LED_BLINK_RT(x)   (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
 
 enum {
-        BLINK_42MS      = 0,/* 42 ms */
-        BLINK_84MS      = 1,/* 84 ms */
-        BLINK_170MS     = 2,/* 170 ms */
-        BLINK_340MS     = 3,/* 340 ms */
-        BLINK_670MS     = 4,/* 670 ms */
+        BLINK_42MS      = 0, /* 42 ms */
+        BLINK_84MS      = 1, /* 84 ms */
+        BLINK_170MS     = 2, /* 170 ms */
+        BLINK_340MS     = 3, /* 340 ms */
+        BLINK_670MS     = 4, /* 670 ms */
 };
 
 /*****  PHY_MARV_LED_OVER       16 bit r/w      Manual LED Override Reg *****/
@@ -1525,7 +1525,7 @@ enum {
         PHY_M_EC2_FO_IMPED      = 1<<5, /* Fiber Output Impedance */
         PHY_M_EC2_FO_M_CLK      = 1<<4, /* Fiber Mode Clock Enable */
         PHY_M_EC2_FO_BOOST      = 1<<3, /* Fiber Output Boost */
-        PHY_M_EC2_FO_AM_MSK     = 7,/* Bit  2.. 0:      Fiber Output Amplitude */
+        PHY_M_EC2_FO_AM_MSK     = 7, /* Bit  2.. 0:     Fiber Output Amplitude */
 };
 
 /*****  PHY_MARV_EXT_P_STAT 16 bit r/w  Ext. PHY Specific Status *****/
@@ -1550,7 +1550,7 @@ enum {
         PHY_M_CABD_DIS_WAIT     = 1<<15, /* Disable Waiting Period (Page 1) */
                                         /* (88E1111 only) */
         PHY_M_CABD_STAT_MSK     = 3<<13, /* Bit 14..13: Status Mask */
-        PHY_M_CABD_AMPL_MSK     = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */
+        PHY_M_CABD_AMPL_MSK     = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
                                         /* (88E1111 only) */
         PHY_M_CABD_DIST_MSK     = 0xff, /* Bit  7.. 0: Distance Mask */
 };
@@ -1605,9 +1605,9 @@ enum {
 
 /*****  PHY_MARV_PHY_CTRL (page 3)              16 bit r/w      LED Control Reg. *****/
 enum {
-        PHY_M_LEDC_LOS_MSK      = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
+        PHY_M_LEDC_LOS_MSK      = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
         PHY_M_LEDC_INIT_MSK     = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
-        PHY_M_LEDC_STA1_MSK     = 0xf<<4,/* Bit  7.. 4: STAT1 LED Ctrl. Mask */
+        PHY_M_LEDC_STA1_MSK     = 0xf<<4, /* Bit  7.. 4: STAT1 LED Ctrl. Mask */
         PHY_M_LEDC_STA0_MSK     = 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
 };
 
@@ -1804,8 +1804,8 @@ enum {
 
 /*      GM_SMI_CTRL                     16 bit r/w      SMI Control Register */
 enum {
-        GM_SMI_CT_PHY_A_MSK     = 0x1f<<11,/* Bit 15..11:       PHY Device Address */
-        GM_SMI_CT_REG_A_MSK     = 0x1f<<6,/* Bit 10.. 6:        PHY Register Address */
+        GM_SMI_CT_PHY_A_MSK     = 0x1f<<11, /* Bit 15..11:      PHY Device Address */
+        GM_SMI_CT_REG_A_MSK     = 0x1f<<6, /* Bit 10.. 6:       PHY Register Address */
         GM_SMI_CT_OP_RD         = 1<<5, /* Bit  5:      OpCode Read (0=Write)*/
         GM_SMI_CT_RD_VAL        = 1<<4, /* Bit  4:      Read Valid (Read completed) */
         GM_SMI_CT_BUSY          = 1<<3, /* Bit  3:      Busy (Operation in progress) */
@@ -1875,9 +1875,9 @@ enum {
 
 /*      TX_GMF_CTRL_T   32 bit  Tx GMAC FIFO Control/Test */
 enum {
-        GMF_WSP_TST_ON  = 1<<18,/* Write Shadow Pointer Test On */
-        GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
-        GMF_WSP_STEP    = 1<<16,/* Write Shadow Pointer Step/Increment */
+        GMF_WSP_TST_ON  = 1<<18, /* Write Shadow Pointer Test On */
+        GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
+        GMF_WSP_STEP    = 1<<16, /* Write Shadow Pointer Step/Increment */
 
         GMF_CLI_TX_FU   = 1<<6, /* Clear IRQ Tx FIFO Underrun */
         GMF_CLI_TX_FC   = 1<<5, /* Clear IRQ Tx Frame Complete */
@@ -2111,18 +2111,18 @@ enum {
 
 /*      XM_MMU_CMD      16 bit r/w      MMU Command Register */
 enum {
-        XM_MMU_PHY_RDY  = 1<<12,/* Bit 12:      PHY Read Ready */
-        XM_MMU_PHY_BUSY = 1<<11,/* Bit 11:      PHY Busy */
-        XM_MMU_IGN_PF   = 1<<10,/* Bit 10:      Ignore Pause Frame */
-        XM_MMU_MAC_LB   = 1<<9, /* Bit  9:      Enable MAC Loopback */
-        XM_MMU_FRC_COL  = 1<<7, /* Bit  7:      Force Collision */
-        XM_MMU_SIM_COL  = 1<<6, /* Bit  6:      Simulate Collision */
-        XM_MMU_NO_PRE   = 1<<5, /* Bit  5:      No MDIO Preamble */
-        XM_MMU_GMII_FD  = 1<<4, /* Bit  4:      GMII uses Full Duplex */
-        XM_MMU_RAT_CTRL = 1<<3, /* Bit  3:      Enable Rate Control */
-        XM_MMU_GMII_LOOP= 1<<2, /* Bit  2:      PHY is in Loopback Mode */
-        XM_MMU_ENA_RX   = 1<<1, /* Bit  1:      Enable Receiver */
-        XM_MMU_ENA_TX   = 1<<0, /* Bit  0:      Enable Transmitter */
+        XM_MMU_PHY_RDY  = 1<<12, /* Bit 12:     PHY Read Ready */
+        XM_MMU_PHY_BUSY = 1<<11, /* Bit 11:     PHY Busy */
+        XM_MMU_IGN_PF   = 1<<10, /* Bit 10:     Ignore Pause Frame */
+        XM_MMU_MAC_LB   = 1<<9,  /* Bit  9:     Enable MAC Loopback */
+        XM_MMU_FRC_COL  = 1<<7,  /* Bit  7:     Force Collision */
+        XM_MMU_SIM_COL  = 1<<6,  /* Bit  6:     Simulate Collision */
+        XM_MMU_NO_PRE   = 1<<5,  /* Bit  5:     No MDIO Preamble */
+        XM_MMU_GMII_FD  = 1<<4,  /* Bit  4:     GMII uses Full Duplex */
+        XM_MMU_RAT_CTRL = 1<<3,  /* Bit  3:     Enable Rate Control */
+        XM_MMU_GMII_LOOP= 1<<2,  /* Bit  2:     PHY is in Loopback Mode */
+        XM_MMU_ENA_RX   = 1<<1,  /* Bit  1:     Enable Receiver */
+        XM_MMU_ENA_TX   = 1<<0,  /* Bit  0:     Enable Transmitter */
 };
 
 
@@ -2456,7 +2456,7 @@ struct skge_port {
 
         struct net_device_stats net_stats;
 
-        struct work_struct   link_thread;
+        struct delayed_work  link_thread;
         enum pause_control   flow_control;
         enum pause_status    flow_status;
         u8                   rx_csum;
@@ -2506,7 +2506,7 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
 }
 
 /* MAC Related Registers inside the device. */
-#define SK_REG(port,reg)        (((port)<<7)+(reg))
+#define SK_REG(port,reg)        (((port)<<7)+(u16)(reg))
 #define SK_XMAC_REG(port, reg) \
         ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
 
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 0ef1848b9761..fb1d2c30c1bb 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -100,33 +100,32 @@ module_param(idle_timeout, int, 0);
 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
 
 static const struct pci_device_id sky2_id_table[] = {
-        { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
-        { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
+        { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
+        { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
         { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },    /* DGE-560T */
         { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) },    /* DGE-550SX */
         { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) },    /* DGE-560SX */
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
-        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
         { 0 }
 };
 
@@ -522,7 +521,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
                 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
                 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
                 /* turn off the Rx LED (LED_RX) */
-                ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
+                ledover &= ~PHY_M_LED_MO_RX;
         }
 
         if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
@@ -545,7 +544,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
 
                 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
                         /* turn on 100 Mbps LED (LED_LINK100) */
-                        ledover |= PHY_M_LED_MO_100(MO_LED_ON);
+                        ledover |= PHY_M_LED_MO_100;
                 }
 
                 if (ledover)
@@ -697,10 +696,15 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
 
 }
 
-/* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
-static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
+/* Assign Ram Buffer allocation to queue */
+static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
 {
-        pr_debug(PFX "q %d %#x %#x\n", q, start, end);
+        u32 end;
+
+        /* convert from K bytes to qwords used for hw register */
+        start *= 1024/8;
+        space *= 1024/8;
+        end = start + space - 1;
 
         sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
         sky2_write32(hw, RB_ADDR(q, RB_START), start);
@@ -709,7 +713,6 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
         sky2_write32(hw, RB_ADDR(q, RB_RP), start);
 
         if (q == Q_R1 || q == Q_R2) {
-                u32 space = end - start + 1;
                 u32 tp = space - space/4;
 
                 /* On receive queue's set the thresholds
@@ -1059,11 +1062,16 @@ static int sky2_rx_start(struct sky2_port *sky2)
         sky2->rx_put = sky2->rx_next = 0;
         sky2_qset(hw, rxq);
 
+        /* On PCI express lowering the watermark gives better performance */
+        if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
+                sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
+
+        /* These chips have no ram buffer?
+         * MAC Rx RAM Read is controlled by hardware */
         if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
-            (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
-                /* MAC Rx RAM Read is controlled by hardware */
+            (hw->chip_rev == CHIP_REV_YU_EC_U_A1
+             || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
                 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
-        }
 
         sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
 
@@ -1139,7 +1147,7 @@ static int sky2_up(struct net_device *dev)
         struct sky2_port *sky2 = netdev_priv(dev);
         struct sky2_hw *hw = sky2->hw;
         unsigned port = sky2->port;
-        u32 ramsize, rxspace, imask;
+        u32 ramsize, imask;
         int cap, err = -ENOMEM;
         struct net_device *otherdev = hw->dev[sky2->port^1];
 
@@ -1192,20 +1200,25 @@ static int sky2_up(struct net_device *dev)
 
         sky2_mac_init(hw, port);
 
-        /* Determine available ram buffer space in qwords.  */
-        ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
+        /* Register is number of 4K blocks on internal RAM buffer. */
+        ramsize = sky2_read8(hw, B2_E_0) * 4;
+        printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
 
-        if (ramsize > 6*1024/8)
-                rxspace = ramsize - (ramsize + 2) / 3;
-        else
-                rxspace = ramsize / 2;
+        if (ramsize > 0) {
+                u32 rxspace;
 
-        sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
-        sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
+                if (ramsize < 16)
+                        rxspace = ramsize / 2;
+                else
+                        rxspace = 8 + (2*(ramsize - 16))/3;
+
+                sky2_ramset(hw, rxqaddr[port], 0, rxspace);
+                sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
 
-        /* Make sure SyncQ is disabled */
-        sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
-                    RB_RST_SET);
+                /* Make sure SyncQ is disabled */
+                sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
+                            RB_RST_SET);
+        }
 
         sky2_qset(hw, txqaddr[port]);
 
@@ -1350,7 +1363,7 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
                 u32 tcpsum;
 
                 tcpsum = offset << 16;          /* sum start */
-                tcpsum |= offset + skb->csum;   /* sum write */
+                tcpsum |= offset + skb->csum_offset;    /* sum write */
 
                 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
                 if (skb->nh.iph->protocol == IPPROTO_UDP)
@@ -2917,18 +2930,8 @@ static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
 
         default:
                 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
-                gm_phy_write(hw, port, PHY_MARV_LED_OVER,
-                             on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
-                             PHY_M_LED_MO_10(MO_LED_ON) |
-                             PHY_M_LED_MO_100(MO_LED_ON) |
-                             PHY_M_LED_MO_1000(MO_LED_ON) |
-                             PHY_M_LED_MO_RX(MO_LED_ON)
-                             : PHY_M_LED_MO_DUP(MO_LED_OFF) |
-                             PHY_M_LED_MO_10(MO_LED_OFF) |
-                             PHY_M_LED_MO_100(MO_LED_OFF) |
-                             PHY_M_LED_MO_1000(MO_LED_OFF) |
-                             PHY_M_LED_MO_RX(MO_LED_OFF));
-
+                gm_phy_write(hw, port, PHY_MARV_LED_OVER, 
+                             on ? PHY_M_LED_ALL : 0);
         }
 }
 
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 7760545edbf2..6ed1d47dbbd3 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -608,7 +608,7 @@ enum {
         PHY_ADDR_MARV   = 0,
 };
 
-#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
+#define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
 
 
 enum {
@@ -680,6 +680,7 @@ enum {
                           BMU_FIFO_ENA | BMU_OP_ON,
 
         BMU_WM_DEFAULT = 0x600,
+        BMU_WM_PEX     = 0x80,
 };
 
 /* Tx BMU Control / Status Registers (Yukon-2) */
@@ -1060,7 +1061,7 @@ enum {
         PHY_M_PC_EN_DET_PLUS    = 3<<8, /* Energy Detect Plus (Mode 2) */
 };
 
-#define PHY_M_PC_MDI_XMODE(x)   (((x)<<5) & PHY_M_PC_MDIX_MSK)
+#define PHY_M_PC_MDI_XMODE(x)   (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
 
 enum {
         PHY_M_PC_MAN_MDI        = 0, /* 00 = Manual MDI configuration */
@@ -1156,13 +1157,13 @@ enum {
         PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */
         PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */};
 
-#define PHY_M_EC_M_DSC(x)       ((x)<<10 & PHY_M_EC_M_DSC_MSK)
+#define PHY_M_EC_M_DSC(x)       ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
                                         /* 00=1x; 01=2x; 10=3x; 11=4x */
-#define PHY_M_EC_S_DSC(x)       ((x)<<8 & PHY_M_EC_S_DSC_MSK)
+#define PHY_M_EC_S_DSC(x)       ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
                                         /* 00=dis; 01=1x; 10=2x; 11=3x */
-#define PHY_M_EC_DSC_2(x)       ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
+#define PHY_M_EC_DSC_2(x)       ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
                                         /* 000=1x; 001=2x; 010=3x; 011=4x */
-#define PHY_M_EC_MAC_S(x)       ((x)<<4 & PHY_M_EC_MAC_S_MSK)
+#define PHY_M_EC_MAC_S(x)       ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
                                         /* 01X=0; 110=2.5; 111=25 (MHz) */
 
 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
@@ -1173,7 +1174,7 @@ enum {
 };
 /* !!! Errata in spec. (1 = disable) */
 
-#define PHY_M_PC_DSC(x)                 (((x)<<12) & PHY_M_PC_DSC_MSK)
+#define PHY_M_PC_DSC(x)                 (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
                                                                                         /* 100=5x; 101=6x; 110=7x; 111=8x */
 enum {
         MAC_TX_CLK_0_MHZ        = 2,
@@ -1203,7 +1204,7 @@ enum {
         PHY_M_LEDC_TX_C_MSB     = 1<<0, /* Tx Control (MSB, 88E1111 only) */
 };
 
-#define PHY_M_LED_PULS_DUR(x)   (((x)<<12) & PHY_M_LEDC_PULS_MSK)
+#define PHY_M_LED_PULS_DUR(x)   (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
 
 /*****  PHY_MARV_PHY_STAT (page 3)16 bit r/w    Polarity Control Reg. *****/
 enum {
@@ -1233,7 +1234,7 @@ enum {
         PULS_1300MS     = 7,/* 1.3 s to 2.7 s */
 };
 
-#define PHY_M_LED_BLINK_RT(x)   (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
+#define PHY_M_LED_BLINK_RT(x)   (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
 
 enum {
         BLINK_42MS      = 0,/* 42 ms */
@@ -1243,21 +1244,18 @@ enum {
         BLINK_670MS     = 4,/* 670 ms */
 };
 
-/*****  PHY_MARV_LED_OVER       16 bit r/w      Manual LED Override Reg *****/
-#define PHY_M_LED_MO_SGMII(x)   ((x)<<14) /* Bit 15..14:  SGMII AN Timer */
-                                                                                /* Bit 13..12:  reserved */
-#define PHY_M_LED_MO_DUP(x)     ((x)<<10) /* Bit 11..10:  Duplex */
-#define PHY_M_LED_MO_10(x)      ((x)<<8) /* Bit  9.. 8:  Link 10 */
-#define PHY_M_LED_MO_100(x)     ((x)<<6) /* Bit  7.. 6:  Link 100 */
-#define PHY_M_LED_MO_1000(x)    ((x)<<4) /* Bit  5.. 4:  Link 1000 */
-#define PHY_M_LED_MO_RX(x)      ((x)<<2) /* Bit  3.. 2:  Rx */
-#define PHY_M_LED_MO_TX(x)      ((x)<<0) /* Bit  1.. 0:  Tx */
-
+/**** PHY_MARV_LED_OVER    16 bit r/w LED control */
 enum {
-        MO_LED_NORM     = 0,
-        MO_LED_BLINK    = 1,
-        MO_LED_OFF      = 2,
-        MO_LED_ON       = 3,
+        PHY_M_LED_MO_DUP  = 3<<10,/* Bit 11..10:  Duplex */
+        PHY_M_LED_MO_10   = 3<<8, /* Bit  9.. 8:  Link 10 */
+        PHY_M_LED_MO_100  = 3<<6, /* Bit  7.. 6:  Link 100 */
+        PHY_M_LED_MO_1000 = 3<<4, /* Bit  5.. 4:  Link 1000 */
+        PHY_M_LED_MO_RX   = 3<<2, /* Bit  3.. 2:  Rx */
+        PHY_M_LED_MO_TX   = 3<<0, /* Bit  1.. 0:  Tx */
+
+        PHY_M_LED_ALL     = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10 
+                            | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000
+                            | PHY_M_LED_MO_RX,
 };
 
 /*****  PHY_MARV_EXT_CTRL_2     16 bit r/w      Ext. PHY Specific Ctrl 2 *****/
@@ -1294,9 +1292,9 @@ enum {
         PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
 };
 
-#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
-#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
-#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
+#define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
+#define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
+#define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
 
 enum {
         LED_PAR_CTRL_COLX       = 0x00,
@@ -1552,8 +1550,8 @@ enum {
         GM_SMI_CT_BUSY          = 1<<3, /* Bit  3:      Busy (Operation in progress) */
 };
 
-#define GM_SMI_CT_PHY_AD(x)     (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
-#define GM_SMI_CT_REG_AD(x)     (((x)<<6) & GM_SMI_CT_REG_A_MSK)
+#define GM_SMI_CT_PHY_AD(x)     (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
+#define GM_SMI_CT_REG_AD(x)     (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
 
 /*      GM_PHY_ADDR                             16 bit r/w      GPHY Address Register */
 enum {
diff --git a/drivers/net/smc-ultra.c b/drivers/net/smc-ultra.c
index 889ef0d7c374..d70bc9795346 100644
--- a/drivers/net/smc-ultra.c
+++ b/drivers/net/smc-ultra.c
@@ -593,7 +593,7 @@ static void cleanup_card(struct net_device *dev)
         iounmap(ei_status.mem);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/smc-ultra32.c b/drivers/net/smc-ultra32.c
index e10755ec5def..2c5319c62fa5 100644
--- a/drivers/net/smc-ultra32.c
+++ b/drivers/net/smc-ultra32.c
@@ -437,7 +437,7 @@ int __init init_module(void)
         return -ENXIO;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int this_dev;
 
diff --git a/drivers/net/smc9194.c b/drivers/net/smc9194.c
index c0d13d650913..bd6e84506c29 100644
--- a/drivers/net/smc9194.c
+++ b/drivers/net/smc9194.c
@@ -1616,7 +1616,7 @@ int __init init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(devSMC9194);
         free_irq(devSMC9194->irq, devSMC9194);
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 95b6478f55c6..e62a9586fb95 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -210,6 +210,7 @@ struct smc_local {
 
         /* work queue */
         struct work_struct phy_configure;
+        struct net_device *dev;
         int     work_pending;
 
         spinlock_t lock;
@@ -1114,10 +1115,11 @@ static void smc_phy_check_media(struct net_device *dev, int init)
  * of autonegotiation.)  If the RPC ANEG bit is cleared, the selection
  * is controlled by the RPC SPEED and RPC DPLX bits.
  */
-static void smc_phy_configure(void *data)
+static void smc_phy_configure(struct work_struct *work)
 {
-        struct net_device *dev = data;
-        struct smc_local *lp = netdev_priv(dev);
+        struct smc_local *lp =
+                container_of(work, struct smc_local, phy_configure);
+        struct net_device *dev = lp->dev;
         void __iomem *ioaddr = lp->base;
         int phyaddr = lp->mii.phy_id;
         int my_phy_caps; /* My PHY capabilities */
@@ -1592,7 +1594,7 @@ smc_open(struct net_device *dev)
 
         /* Configure the PHY, initialize the link state */
         if (lp->phy_type != 0)
-                smc_phy_configure(dev);
+                smc_phy_configure(&lp->phy_configure);
         else {
                 spin_lock_irq(&lp->lock);
                 smc_10bt_check_media(dev, 1);
@@ -1972,7 +1974,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr)
 #endif
 
         tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev);
-        INIT_WORK(&lp->phy_configure, smc_phy_configure, dev);
+        INIT_WORK(&lp->phy_configure, smc_phy_configure);
+        lp->dev = dev;
         lp->mii.phy_id_mask = 0x1f;
         lp->mii.reg_num_mask = 0x1f;
         lp->mii.force_media = 0;
@@ -2322,7 +2325,7 @@ static int smc_drv_resume(struct platform_device *dev)
                         smc_reset(ndev);
                         smc_enable(ndev);
                         if (lp->phy_type != 0)
-                                smc_phy_configure(ndev);
+                                smc_phy_configure(&lp->phy_configure);
                         netif_device_attach(ndev);
                 }
         }
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index a8640169fc77..9367c574477a 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -238,7 +238,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define SMC_CAN_USE_16BIT       1
 #define SMC_CAN_USE_32BIT       0
 
-#define SMC_inb(a, r)           inb((u32)a) + (r))
+#define SMC_inb(a, r)           inb(((u32)a) + (r))
 #define SMC_inw(a, r)           inw(((u32)a) + (r))
 #define SMC_outb(v, a, r)       outb(v, ((u32)a) + (r))
 #define SMC_outw(v, a, r)       outw(v, ((u32)a) + (r))
@@ -434,6 +434,24 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 
 #define SMC_IRQ_FLAGS           (0)
 
+#elif   defined(CONFIG_ARCH_VERSATILE)
+
+#define SMC_CAN_USE_8BIT        1
+#define SMC_CAN_USE_16BIT       1
+#define SMC_CAN_USE_32BIT       1
+#define SMC_NOWAIT              1
+
+#define SMC_inb(a, r)           readb((a) + (r))
+#define SMC_inw(a, r)           readw((a) + (r))
+#define SMC_inl(a, r)           readl((a) + (r))
+#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
+#define SMC_outw(v, a, r)       writew(v, (a) + (r))
+#define SMC_outl(v, a, r)       writel(v, (a) + (r))
+#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
+#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
+
+#define SMC_IRQ_FLAGS           (0)
+
 #else
 
 #define SMC_CAN_USE_8BIT        1
@@ -1216,7 +1234,7 @@ static const char * chip_ids[ 16 ] =  {
                 if (SMC_CAN_USE_32BIT) {                                \
                         void *__ptr = (p);                              \
                         int __len = (l);                                \
-                        void *__ioaddr = ioaddr;                        \
+                        void __iomem *__ioaddr = ioaddr;                \
                         if (__len >= 2 && (unsigned long)__ptr & 2) {   \
                                 __len -= 2;                             \
                                 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
@@ -1240,7 +1258,7 @@ static const char * chip_ids[ 16 ] =  {
                 if (SMC_CAN_USE_32BIT) {                                \
                         void *__ptr = (p);                              \
                         int __len = (l);                                \
-                        void *__ioaddr = ioaddr;                        \
+                        void __iomem *__ioaddr = ioaddr;                \
                         if ((unsigned long)__ptr & 2) {                 \
                                 /*                                      \
                                  * We want 32bit alignment here.        \
diff --git a/drivers/net/spider_net.c b/drivers/net/spider_net.c
index cef7e6671c49..ebb6aa39f9c7 100644
--- a/drivers/net/spider_net.c
+++ b/drivers/net/spider_net.c
@@ -88,12 +88,11 @@ MODULE_DEVICE_TABLE(pci, spider_net_pci_tbl);
 static inline u32
 spider_net_read_reg(struct spider_net_card *card, u32 reg)
 {
-        u32 value;
-
-        value = readl(card->regs + reg);
-        value = le32_to_cpu(value);
-
-        return value;
+        /* We use the powerpc specific variants instead of readl_be() because
+         * we know spidernet is not a real PCI device and we can thus avoid the
+         * performance hit caused by the PCI workarounds.
+         */
+        return in_be32(card->regs + reg);
 }
 
 /**
@@ -105,8 +104,11 @@ spider_net_read_reg(struct spider_net_card *card, u32 reg)
 static inline void
 spider_net_write_reg(struct spider_net_card *card, u32 reg, u32 value)
 {
-        value = cpu_to_le32(value);
-        writel(value, card->regs + reg);
+        /* We use the powerpc specific variants instead of writel_be() because
+         * we know spidernet is not a real PCI device and we can thus avoid the
+         * performance hit caused by the PCI workarounds.
+         */
+        out_be32(card->regs + reg, value);
 }
 
 /** spider_net_write_phy - write to phy register
@@ -1937,10 +1939,11 @@ spider_net_stop(struct net_device *netdev)
  * called as task when tx hangs, resets interface (if interface is up)
  */
 static void
-spider_net_tx_timeout_task(void *data)
+spider_net_tx_timeout_task(struct work_struct *work)
 {
-        struct net_device *netdev = data;
-        struct spider_net_card *card = netdev_priv(netdev);
+        struct spider_net_card *card =
+                container_of(work, struct spider_net_card, tx_timeout_task);
+        struct net_device *netdev = card->netdev;
 
         if (!(netdev->flags & IFF_UP))
                 goto out;
@@ -2114,7 +2117,7 @@ spider_net_alloc_card(void)
         card = netdev_priv(netdev);
         card->netdev = netdev;
         card->msg_enable = SPIDER_NET_DEFAULT_MSG;
-        INIT_WORK(&card->tx_timeout_task, spider_net_tx_timeout_task, netdev);
+        INIT_WORK(&card->tx_timeout_task, spider_net_tx_timeout_task);
         init_waitqueue_head(&card->waitq);
         atomic_set(&card->tx_timeout_task_counter, 0);
 
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index 7a0aee6c869d..bf873ea25797 100644
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -41,6 +41,7 @@
 #include <linux/ethtool.h>
 #include <linux/mii.h>
 #include <linux/if_vlan.h>
+#include <linux/mm.h>
 #include <asm/processor.h>              /* Processor type for cache alignment. */
 #include <asm/uaccess.h>
 #include <asm/io.h>
diff --git a/drivers/net/sun3lance.c b/drivers/net/sun3lance.c
index b865db363ba0..c62e85d89f41 100644
--- a/drivers/net/sun3lance.c
+++ b/drivers/net/sun3lance.c
@@ -38,6 +38,7 @@ static char *version = "sun3lance.c: v1.2 1/12/2001  Sam Creasey (sammy@sammy.ne
 #include <linux/skbuff.h>
 #include <linux/bitops.h>
 
+#include <asm/cacheflush.h>
 #include <asm/setup.h>
 #include <asm/irq.h>
 #include <asm/io.h>
@@ -944,7 +945,7 @@ static void set_multicast_list( struct net_device *dev )
 
 static struct net_device *sun3lance_dev;
 
-int init_module(void)
+int __init init_module(void)
 {
         sun3lance_dev = sun3lance_probe(-1);
         if (IS_ERR(sun3lance_dev))
@@ -952,7 +953,7 @@ int init_module(void)
         return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         unregister_netdev(sun3lance_dev);
 #ifdef CONFIG_SUN3
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index 253e96e7ad20..785e4a535f9e 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -56,6 +56,7 @@
 #include <linux/if_vlan.h>
 #include <linux/bitops.h>
 #include <linux/mutex.h>
+#include <linux/mm.h>
 
 #include <asm/system.h>
 #include <asm/io.h>
@@ -1030,7 +1031,7 @@ static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
                 u64 csum_start_off, csum_stuff_off;
 
                 csum_start_off = (u64) (skb->h.raw - skb->data);
-                csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
+                csum_stuff_off = csum_start_off + skb->csum_offset;
 
                 ctrl = (TXDCTRL_CENAB |
                         (csum_start_off << 15) |
@@ -2281,9 +2282,9 @@ static void gem_do_stop(struct net_device *dev, int wol)
         }
 }
 
-static void gem_reset_task(void *data)
+static void gem_reset_task(struct work_struct *work)
 {
-        struct gem *gp = (struct gem *) data;
+        struct gem *gp = container_of(work, struct gem, reset_task);
 
         mutex_lock(&gp->pm_mutex);
 
@@ -3043,7 +3044,7 @@ static int __devinit gem_init_one(struct pci_dev *pdev,
         gp->link_timer.function = gem_link_timer;
         gp->link_timer.data = (unsigned long) gp;
 
-        INIT_WORK(&gp->reset_task, gem_reset_task, gp);
+        INIT_WORK(&gp->reset_task, gem_reset_task);
 
         gp->lstate = link_down;
         gp->timer_ticks = 0;
diff --git a/drivers/net/sunhme.c b/drivers/net/sunhme.c
index 9d7cd130c19d..ef671739cfea 100644
--- a/drivers/net/sunhme.c
+++ b/drivers/net/sunhme.c
@@ -32,6 +32,7 @@
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
+#include <linux/mm.h>
 #include <linux/bitops.h>
 
 #include <asm/system.h>
@@ -2272,7 +2273,7 @@ static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
                 u32 csum_start_off, csum_stuff_off;
 
                 csum_start_off = (u32) (skb->h.raw - skb->data);
-                csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data);
+                csum_stuff_off = csum_start_off + skb->csum_offset;
 
                 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
                             ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
@@ -3012,6 +3013,11 @@ static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
 #endif
 
         err = -ENODEV;
+
+        if (pci_enable_device(pdev))
+                goto err_out;
+        pci_set_master(pdev);
+
         if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
                 qp = quattro_pci_find(pdev);
                 if (qp == NULL)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index c20bb998e0e5..d9123c9adc1e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3654,9 +3654,9 @@ static void tg3_poll_controller(struct net_device *dev)
 }
 #endif
 
-static void tg3_reset_task(void *_data)
+static void tg3_reset_task(struct work_struct *work)
 {
-        struct tg3 *tp = _data;
+        struct tg3 *tp = container_of(work, struct tg3, reset_task);
         unsigned int restart_timer;
 
         tg3_full_lock(tp, 0);
@@ -11734,7 +11734,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 #endif
         spin_lock_init(&tp->lock);
         spin_lock_init(&tp->indirect_lock);
-        INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
+        INIT_WORK(&tp->reset_task, tg3_reset_task);
 
         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
         if (tp->regs == 0UL) {
diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c
index e14f5a00f65a..f85f00251123 100644
--- a/drivers/net/tlan.c
+++ b/drivers/net/tlan.c
@@ -296,6 +296,7 @@ static void	TLan_SetMulticastList( struct net_device *);
 static int      TLan_ioctl( struct net_device *dev, struct ifreq *rq, int cmd);
 static int      TLan_probe1( struct pci_dev *pdev, long ioaddr, int irq, int rev, const struct pci_device_id *ent);
 static void     TLan_tx_timeout( struct net_device *dev);
+static void     TLan_tx_timeout_work(struct work_struct *work);
 static int      tlan_init_one( struct pci_dev *pdev, const struct pci_device_id *ent);
 
 static u32      TLan_HandleInvalid( struct net_device *, u16 );
@@ -562,6 +563,7 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
         priv = netdev_priv(dev);
 
         priv->pciDev = pdev;
+        priv->dev = dev;
 
         /* Is this a PCI device? */
         if (pdev) {
@@ -634,7 +636,7 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
 
         /* This will be used when we get an adapter error from
          * within our irq handler */
-        INIT_WORK(&priv->tlan_tqueue, (void *)(void*)TLan_tx_timeout, dev);
+        INIT_WORK(&priv->tlan_tqueue, TLan_tx_timeout_work);
 
         spin_lock_init(&priv->lock);
 
@@ -1040,6 +1042,25 @@ static void TLan_tx_timeout(struct net_device *dev)
 }
 
 
+        /***************************************************************
+         *      TLan_tx_timeout_work
+         *
+         *      Returns: nothing
+         *
+         *      Params:
+         *              work    work item of device which timed out
+         *
+         **************************************************************/
+
+static void TLan_tx_timeout_work(struct work_struct *work)
+{
+        TLanPrivateInfo *priv =
+                container_of(work, TLanPrivateInfo, tlan_tqueue);
+
+        TLan_tx_timeout(priv->dev);
+}
+
+
 
         /***************************************************************
          *      TLan_StartTx
diff --git a/drivers/net/tlan.h b/drivers/net/tlan.h
index a44e2f2ef62a..41ce0b665937 100644
--- a/drivers/net/tlan.h
+++ b/drivers/net/tlan.h
@@ -170,6 +170,7 @@ typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
 typedef struct tlan_private_tag {
         struct net_device       *nextDevice;
         struct pci_dev          *pciDev;
+        struct net_device       *dev;
         void                    *dmaStorage;
         dma_addr_t              dmaStorageDMA;
         unsigned int            dmaSize;
diff --git a/drivers/net/tokenring/ibmtr.c b/drivers/net/tokenring/ibmtr.c
index bfe59865b1dd..0d97e10ccac5 100644
--- a/drivers/net/tokenring/ibmtr.c
+++ b/drivers/net/tokenring/ibmtr.c
@@ -1826,7 +1826,7 @@ static void tr_rx(struct net_device *dev)
         skb->protocol = tr_type_trans(skb, dev);
         if (IPv4_p) {
                 skb->csum = chksum;
-                skb->ip_summed = 1;
+                skb->ip_summed = CHECKSUM_COMPLETE;
         }
         netif_rx(skb);
         dev->last_rx = jiffies;
diff --git a/drivers/net/tokenring/smctr.c b/drivers/net/tokenring/smctr.c
index 46dabdb12071..cec282a6f62d 100644
--- a/drivers/net/tokenring/smctr.c
+++ b/drivers/net/tokenring/smctr.c
@@ -5706,7 +5706,7 @@ int __init init_module(void)
         return found ? 0 : -ENODEV;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
         int i;
 
diff --git a/drivers/net/tulip/21142.c b/drivers/net/tulip/21142.c
index fa3a2bb105ad..942b839ccc5b 100644
--- a/drivers/net/tulip/21142.c
+++ b/drivers/net/tulip/21142.c
@@ -26,10 +26,11 @@ static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
 
 /* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list
    of available transceivers.  */
-void t21142_media_task(void *data)
+void t21142_media_task(struct work_struct *work)
 {
-        struct net_device *dev = data;
-        struct tulip_private *tp = netdev_priv(dev);
+        struct tulip_private *tp =
+                container_of(work, struct tulip_private, media_work);
+        struct net_device *dev = tp->dev;
         void __iomem *ioaddr = tp->base_addr;
         int csr12 = ioread32(ioaddr + CSR12);
         int next_tick = 60*HZ;
diff --git a/drivers/net/tulip/de4x5.c b/drivers/net/tulip/de4x5.c
index 3f4b6408b755..4b3cd3d8b62a 100644
--- a/drivers/net/tulip/de4x5.c
+++ b/drivers/net/tulip/de4x5.c
@@ -473,9 +473,9 @@
 #include <asm/byteorder.h>
 #include <asm/unaligned.h>
 #include <asm/uaccess.h>
-#ifdef CONFIG_PPC_MULTIPLATFORM
+#ifdef CONFIG_PPC_PMAC
 #include <asm/machdep.h>
-#endif /* CONFIG_PPC_MULTIPLATFORM */
+#endif /* CONFIG_PPC_PMAC */
 
 #include "de4x5.h"
 
@@ -4151,7 +4151,7 @@ get_hw_addr(struct net_device *dev)
     /* If possible, try to fix a broken card - SMC only so far */
     srom_repair(dev, broken);
 
-#ifdef CONFIG_PPC_MULTIPLATFORM
+#ifdef CONFIG_PPC_PMAC
     /*
     ** If the address starts with 00 a0, we have to bit-reverse
     ** each byte of the address.
@@ -4168,7 +4168,7 @@ get_hw_addr(struct net_device *dev)
                     dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
             }
     }
-#endif /* CONFIG_PPC_MULTIPLATFORM */
+#endif /* CONFIG_PPC_PMAC */
 
     /* Test for a bad enet address */
     status = test_bad_enet(dev, status);
diff --git a/drivers/net/tulip/timer.c b/drivers/net/tulip/timer.c
index 066e5d6bcbd8..df326fe1cc8f 100644
--- a/drivers/net/tulip/timer.c
+++ b/drivers/net/tulip/timer.c
@@ -18,10 +18,11 @@
 #include "tulip.h"
 
 
-void tulip_media_task(void *data)
+void tulip_media_task(struct work_struct *work)
 {
-        struct net_device *dev = data;
-        struct tulip_private *tp = netdev_priv(dev);
+        struct tulip_private *tp =
+                container_of(work, struct tulip_private, media_work);
+        struct net_device *dev = tp->dev;
         void __iomem *ioaddr = tp->base_addr;
         u32 csr12 = ioread32(ioaddr + CSR12);
         int next_tick = 2*HZ;
diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h
index ad107f45c7b1..25f25da76917 100644
--- a/drivers/net/tulip/tulip.h
+++ b/drivers/net/tulip/tulip.h
@@ -44,7 +44,7 @@ struct tulip_chip_table {
         int valid_intrs;        /* CSR7 interrupt enable settings */
         int flags;
         void (*media_timer) (unsigned long);
-        void (*media_task) (void *);
+        work_func_t media_task;
 };
 
 
@@ -392,6 +392,7 @@ struct tulip_private {
         int csr12_shadow;
         int pad0;               /* Used for 8-byte alignment */
         struct work_struct media_work;
+        struct net_device *dev;
 };
 
 
@@ -406,7 +407,7 @@ struct eeprom_fixup {
 
 /* 21142.c */
 extern u16 t21142_csr14[];
-void t21142_media_task(void *data);
+void t21142_media_task(struct work_struct *work);
 void t21142_start_nway(struct net_device *dev);
 void t21142_lnk_change(struct net_device *dev, int csr5);
 
@@ -444,7 +445,7 @@ void pnic_lnk_change(struct net_device *dev, int csr5);
 void pnic_timer(unsigned long data);
 
 /* timer.c */
-void tulip_media_task(void *data);
+void tulip_media_task(struct work_struct *work);
 void mxic_timer(unsigned long data);
 void comet_timer(unsigned long data);
 
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index 0aee618f883c..5a35354aa523 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -1367,6 +1367,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
          * it is zeroed and aligned in alloc_etherdev
          */
         tp = netdev_priv(dev);
+        tp->dev = dev;
 
         tp->rx_ring = pci_alloc_consistent(pdev,
                                            sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
@@ -1389,7 +1390,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
         tp->timer.data = (unsigned long)dev;
         tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
 
-        INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task, dev);
+        INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
 
         dev->base_addr = (unsigned long)ioaddr;
 
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c
index 3bf9e630404f..9781b16bb8b6 100644
--- a/drivers/net/typhoon.c
+++ b/drivers/net/typhoon.c
@@ -117,6 +117,7 @@ static const int multicast_filter_limit = 32;
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
+#include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/ethtool.h>
@@ -127,7 +128,6 @@ static const int multicast_filter_limit = 32;
 #include <asm/io.h>
 #include <asm/uaccess.h>
 #include <linux/in6.h>
-#include <asm/checksum.h>
 #include <linux/version.h>
 #include <linux/dma-mapping.h>
 
diff --git a/drivers/net/wan/pc300_tty.c b/drivers/net/wan/pc300_tty.c
index 931cbdf6d791..b2a23aed4428 100644
--- a/drivers/net/wan/pc300_tty.c
+++ b/drivers/net/wan/pc300_tty.c
@@ -125,8 +125,8 @@ static int cpc_tty_write_room(struct tty_struct *tty);
 static int cpc_tty_chars_in_buffer(struct tty_struct *tty);
 static void cpc_tty_flush_buffer(struct tty_struct *tty);
 static void cpc_tty_hangup(struct tty_struct *tty);
-static void cpc_tty_rx_work(void *data);
-static void cpc_tty_tx_work(void *data);
+static void cpc_tty_rx_work(struct work_struct *work);
+static void cpc_tty_tx_work(struct work_struct *work);
 static int cpc_tty_send_to_card(pc300dev_t *dev,void *buf, int len);
 static void cpc_tty_trace(pc300dev_t *dev, char* buf, int len, char rxtx);
 static void cpc_tty_signal_off(pc300dev_t *pc300dev, unsigned char);
@@ -261,8 +261,8 @@ void cpc_tty_init(pc300dev_t *pc300dev)
         cpc_tty->tty_minor = port + CPC_TTY_MINOR_START;
         cpc_tty->pc300dev = pc300dev; 
 
-        INIT_WORK(&cpc_tty->tty_tx_work, cpc_tty_tx_work, (void *)cpc_tty);
-        INIT_WORK(&cpc_tty->tty_rx_work, cpc_tty_rx_work, (void *)port);
+        INIT_WORK(&cpc_tty->tty_tx_work, cpc_tty_tx_work);
+        INIT_WORK(&cpc_tty->tty_rx_work, cpc_tty_rx_work);
         
         cpc_tty->buf_rx.first = cpc_tty->buf_rx.last = NULL;
 
@@ -659,21 +659,23 @@ static void cpc_tty_hangup(struct tty_struct *tty)
  * o call the line disc. read
  * o free memory
  */
-static void cpc_tty_rx_work(void * data)
+static void cpc_tty_rx_work(struct work_struct *work)
 {
+        st_cpc_tty_area *cpc_tty;
         unsigned long port;
         int i, j;
-        st_cpc_tty_area *cpc_tty; 
         volatile st_cpc_rx_buf *buf;
         char flags=0,flg_rx=1; 
         struct tty_ldisc *ld;
 
         if (cpc_tty_cnt == 0) return;
-
         
         for (i=0; (i < 4) && flg_rx ; i++) {
                 flg_rx = 0;
-                port = (unsigned long)data;
+
+                cpc_tty = container_of(work, st_cpc_tty_area, tty_rx_work);
+                port = cpc_tty - cpc_tty_area;
+
                 for (j=0; j < CPC_TTY_NPORTS; j++) {
                         cpc_tty = &cpc_tty_area[port];
                 
@@ -882,9 +884,10 @@ void cpc_tty_receive(pc300dev_t *pc300dev)
  * o if need call line discipline wakeup
  * o call wake_up_interruptible
  */
-static void cpc_tty_tx_work(void *data)
+static void cpc_tty_tx_work(struct work_struct *work)
 {
-        st_cpc_tty_area *cpc_tty = (st_cpc_tty_area *) data; 
+        st_cpc_tty_area *cpc_tty =
+                container_of(work, st_cpc_tty_area, tty_tx_work);
         struct tty_struct *tty; 
 
         CPC_TTY_DBG("%s: cpc_tty_tx_work init\n",cpc_tty->name);
diff --git a/drivers/net/wd.c b/drivers/net/wd.c
index 41f1d6778849..7f38012b9c92 100644
--- a/drivers/net/wd.c
+++ b/drivers/net/wd.c
@@ -538,7 +538,7 @@ static void cleanup_card(struct net_device *dev)
         iounmap(ei_status.mem);
 }
 
-void
+void __exit
 cleanup_module(void)
 {
         int this_dev;
diff --git a/drivers/net/wireless/airo_cs.c b/drivers/net/wireless/airo_cs.c
index ac9437d497f0..f12355398fe7 100644
--- a/drivers/net/wireless/airo_cs.c
+++ b/drivers/net/wireless/airo_cs.c
@@ -219,21 +219,6 @@ static int airo_config(struct pcmcia_device *link)
         dev = link->priv;
 
         DEBUG(0, "airo_config(0x%p)\n", link);
-        
-        /*
-          This reads the card's CONFIG tuple to find its configuration
-          registers.
-        */
-        tuple.DesiredTuple = CISTPL_CONFIG;
-        tuple.Attributes = 0;
-        tuple.TupleData = buf;
-        tuple.TupleDataMax = sizeof(buf);
-        tuple.TupleOffset = 0;
-        CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-        CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-        link->conf.ConfigBase = parse.config.base;
-        link->conf.Present = parse.config.rmask[0];
 
         /*
           In this loop, we scan the CIS for configuration table entries,
@@ -247,6 +232,10 @@ static int airo_config(struct pcmcia_device *link)
           these things without consulting the CIS, and most client drivers
           will only use the CIS to fill in implementation-defined details.
         */
+        tuple.Attributes = 0;
+        tuple.TupleData = buf;
+        tuple.TupleDataMax = sizeof(buf);
+        tuple.TupleOffset = 0;
         tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
         CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
         while (1) {
diff --git a/drivers/net/wireless/atmel_cs.c b/drivers/net/wireless/atmel_cs.c
index 5c410989c4d7..12617cd0b78e 100644
--- a/drivers/net/wireless/atmel_cs.c
+++ b/drivers/net/wireless/atmel_cs.c
@@ -244,17 +244,6 @@ static int atmel_config(struct pcmcia_device *link)
         tuple.TupleOffset = 0;
 
         /*
-          This reads the card's CONFIG tuple to find its configuration
-          registers.
-        */
-        tuple.DesiredTuple = CISTPL_CONFIG;
-        CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-        CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-        link->conf.ConfigBase = parse.config.base;
-        link->conf.Present = parse.config.rmask[0];
-
-        /*
           In this loop, we scan the CIS for configuration table entries,
           each of which describes a valid card configuration, including
           voltage, IO window, memory window, and interrupt settings.
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx.h b/drivers/net/wireless/bcm43xx/bcm43xx.h
index 94dfb92fab5c..8286678513b9 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx.h
+++ b/drivers/net/wireless/bcm43xx/bcm43xx.h
@@ -819,7 +819,7 @@ struct bcm43xx_private {
         struct tasklet_struct isr_tasklet;
 
         /* Periodic tasks */
-        struct work_struct periodic_work;
+        struct delayed_work periodic_work;
         unsigned int periodic_state;
 
         struct work_struct restart_work;
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_main.c b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
index 5b3c27359a18..2ec2e5afce67 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_main.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
@@ -3215,9 +3215,10 @@ static void do_periodic_work(struct bcm43xx_private *bcm)
         schedule_delayed_work(&bcm->periodic_work, HZ * 15);
 }
 
-static void bcm43xx_periodic_work_handler(void *d)
+static void bcm43xx_periodic_work_handler(struct work_struct *work)
 {
-        struct bcm43xx_private *bcm = d;
+        struct bcm43xx_private *bcm =
+                container_of(work, struct bcm43xx_private, periodic_work.work);
         struct net_device *net_dev = bcm->net_dev;
         unsigned long flags;
         u32 savedirqs = 0;
@@ -3279,11 +3280,11 @@ void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
 
 void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
 {
-        struct work_struct *work = &(bcm->periodic_work);
+        struct delayed_work *work = &bcm->periodic_work;
 
         assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
-        INIT_WORK(work, bcm43xx_periodic_work_handler, bcm);
-        schedule_work(work);
+        INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
+        schedule_delayed_work(work, 0);
 }
 
 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
@@ -3635,7 +3636,7 @@ static int bcm43xx_init_board(struct bcm43xx_private *bcm)
         bcm43xx_periodic_tasks_setup(bcm);
 
         /*FIXME: This should be handled by softmac instead. */
-        schedule_work(&bcm->softmac->associnfo.work);
+        schedule_delayed_work(&bcm->softmac->associnfo.work, 0);
 
 out:
         mutex_unlock(&(bcm)->mutex);
@@ -4182,9 +4183,10 @@ static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
 /* Hard-reset the chip. Do not call this directly.
  * Use bcm43xx_controller_restart()
  */
-static void bcm43xx_chip_reset(void *_bcm)
+static void bcm43xx_chip_reset(struct work_struct *work)
 {
-        struct bcm43xx_private *bcm = _bcm;
+        struct bcm43xx_private *bcm =
+                container_of(work, struct bcm43xx_private, restart_work);
         struct bcm43xx_phyinfo *phy;
         int err = -ENODEV;
 
@@ -4211,7 +4213,7 @@ void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
         if (bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)
                 return;
         printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
-        INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
+        INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset);
         schedule_work(&bcm->restart_work);
 }
 
diff --git a/drivers/net/wireless/hostap/hostap.h b/drivers/net/wireless/hostap/hostap.h
index e663518bd570..e89c890d16fd 100644
--- a/drivers/net/wireless/hostap/hostap.h
+++ b/drivers/net/wireless/hostap/hostap.h
@@ -35,7 +35,7 @@ int hostap_80211_get_hdrlen(u16 fc);
 struct net_device_stats *hostap_get_stats(struct net_device *dev);
 void hostap_setup_dev(struct net_device *dev, local_info_t *local,
                       int main_dev);
-void hostap_set_multicast_list_queue(void *data);
+void hostap_set_multicast_list_queue(struct work_struct *work);
 int hostap_set_hostapd(local_info_t *local, int val, int rtnl_locked);
 int hostap_set_hostapd_sta(local_info_t *local, int val, int rtnl_locked);
 void hostap_cleanup(local_info_t *local);
diff --git a/drivers/net/wireless/hostap/hostap_ap.c b/drivers/net/wireless/hostap/hostap_ap.c
index ba13125024cb..974a8e5bec8b 100644
--- a/drivers/net/wireless/hostap/hostap_ap.c
+++ b/drivers/net/wireless/hostap/hostap_ap.c
@@ -49,10 +49,10 @@ MODULE_PARM_DESC(autom_ap_wds, "Add WDS connections to other APs "
 static struct sta_info* ap_get_sta(struct ap_data *ap, u8 *sta);
 static void hostap_event_expired_sta(struct net_device *dev,
                                      struct sta_info *sta);
-static void handle_add_proc_queue(void *data);
+static void handle_add_proc_queue(struct work_struct *work);
 
 #ifndef PRISM2_NO_KERNEL_IEEE80211_MGMT
-static void handle_wds_oper_queue(void *data);
+static void handle_wds_oper_queue(struct work_struct *work);
 static void prism2_send_mgmt(struct net_device *dev,
                              u16 type_subtype, char *body,
                              int body_len, u8 *addr, u16 tx_cb_idx);
@@ -807,7 +807,7 @@ void hostap_init_data(local_info_t *local)
         INIT_LIST_HEAD(&ap->sta_list);
 
         /* Initialize task queue structure for AP management */
-        INIT_WORK(&local->ap->add_sta_proc_queue, handle_add_proc_queue, ap);
+        INIT_WORK(&local->ap->add_sta_proc_queue, handle_add_proc_queue);
 
         ap->tx_callback_idx =
                 hostap_tx_callback_register(local, hostap_ap_tx_cb, ap);
@@ -815,7 +815,7 @@ void hostap_init_data(local_info_t *local)
                 printk(KERN_WARNING "%s: failed to register TX callback for "
                        "AP\n", local->dev->name);
 #ifndef PRISM2_NO_KERNEL_IEEE80211_MGMT
-        INIT_WORK(&local->ap->wds_oper_queue, handle_wds_oper_queue, local);
+        INIT_WORK(&local->ap->wds_oper_queue, handle_wds_oper_queue);
 
         ap->tx_callback_auth =
                 hostap_tx_callback_register(local, hostap_ap_tx_cb_auth, ap);
@@ -1062,9 +1062,10 @@ static int prism2_sta_proc_read(char *page, char **start, off_t off,
 }
 
 
-static void handle_add_proc_queue(void *data)
+static void handle_add_proc_queue(struct work_struct *work)
 {
-        struct ap_data *ap = (struct ap_data *) data;
+        struct ap_data *ap = container_of(work, struct ap_data,
+                                          add_sta_proc_queue);
         struct sta_info *sta;
         char name[20];
         struct add_sta_proc_data *entry, *prev;
@@ -1099,15 +1100,13 @@ static struct sta_info * ap_add_sta(struct ap_data *ap, u8 *addr)
 {
         struct sta_info *sta;
 
-        sta = (struct sta_info *)
-                kmalloc(sizeof(struct sta_info), GFP_ATOMIC);
+        sta = kzalloc(sizeof(struct sta_info), GFP_ATOMIC);
         if (sta == NULL) {
                 PDEBUG(DEBUG_AP, "AP: kmalloc failed\n");
                 return NULL;
         }
 
         /* initialize STA info data */
-        memset(sta, 0, sizeof(struct sta_info));
         sta->local = ap->local;
         skb_queue_head_init(&sta->tx_buf);
         memcpy(sta->addr, addr, ETH_ALEN);
@@ -1952,9 +1951,11 @@ static void handle_pspoll(local_info_t *local,
 
 #ifndef PRISM2_NO_KERNEL_IEEE80211_MGMT
 
-static void handle_wds_oper_queue(void *data)
+static void handle_wds_oper_queue(struct work_struct *work)
 {
-        local_info_t *local = data;
+        struct ap_data *ap = container_of(work, struct ap_data,
+                                          wds_oper_queue);
+        local_info_t *local = ap->local;
         struct wds_oper_data *entry, *prev;
 
         spin_lock_bh(&local->lock);
diff --git a/drivers/net/wireless/hostap/hostap_cs.c b/drivers/net/wireless/hostap/hostap_cs.c
index f63909e4bc32..8d8f4b9b8b07 100644
--- a/drivers/net/wireless/hostap/hostap_cs.c
+++ b/drivers/net/wireless/hostap/hostap_cs.c
@@ -293,15 +293,12 @@ static int sandisk_enable_wireless(struct net_device *dev)
                 goto done;
         }
 
-        tuple.DesiredTuple = CISTPL_MANFID;
         tuple.Attributes = TUPLE_RETURN_COMMON;
         tuple.TupleData = buf;
         tuple.TupleDataMax = sizeof(buf);
         tuple.TupleOffset = 0;
-        if (pcmcia_get_first_tuple(hw_priv->link, &tuple) ||
-            pcmcia_get_tuple_data(hw_priv->link, &tuple) ||
-            pcmcia_parse_tuple(hw_priv->link, &tuple, parse) ||
-            parse->manfid.manf != 0xd601 || parse->manfid.card != 0x0101) {
+
+        if (hw_priv->link->manf_id != 0xd601 || hw_priv->link->card_id != 0x0101) {
                 /* No SanDisk manfid found */
                 ret = -ENODEV;
                 goto done;
@@ -566,23 +563,16 @@ static int prism2_config(struct pcmcia_device *link)
         PDEBUG(DEBUG_FLOW, "prism2_config()\n");
 
         parse = kmalloc(sizeof(cisparse_t), GFP_KERNEL);
-        hw_priv = kmalloc(sizeof(*hw_priv), GFP_KERNEL);
+        hw_priv = kzalloc(sizeof(*hw_priv), GFP_KERNEL);
         if (parse == NULL || hw_priv == NULL) {
                 ret = -ENOMEM;
                 goto failed;
         }
-        memset(hw_priv, 0, sizeof(*hw_priv));
 
-        tuple.DesiredTuple = CISTPL_CONFIG;
         tuple.Attributes = 0;
         tuple.TupleData = buf;
         tuple.TupleDataMax = sizeof(buf);
         tuple.TupleOffset = 0;
-        CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-        CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, parse));
-        link->conf.ConfigBase = parse->config.base;
-        link->conf.Present = parse->config.rmask[0];
 
         CS_CHECK(GetConfigurationInfo,
                  pcmcia_get_configuration_info(link, &conf));
diff --git a/drivers/net/wireless/hostap/hostap_download.c b/drivers/net/wireless/hostap/hostap_download.c
index ab26b52b3e76..24fc387bba67 100644
--- a/drivers/net/wireless/hostap/hostap_download.c
+++ b/drivers/net/wireless/hostap/hostap_download.c
@@ -685,14 +685,12 @@ static int prism2_download(local_info_t *local,
                 goto out;
         }
 
-        dl = kmalloc(sizeof(*dl) + param->num_areas *
+        dl = kzalloc(sizeof(*dl) + param->num_areas *
                      sizeof(struct prism2_download_data_area), GFP_KERNEL);
         if (dl == NULL) {
                 ret = -ENOMEM;
                 goto out;
         }
-        memset(dl, 0, sizeof(*dl) + param->num_areas *
-               sizeof(struct prism2_download_data_area));
         dl->dl_cmd = param->dl_cmd;
         dl->start_addr = param->start_addr;
         dl->num_areas = param->num_areas;
diff --git a/drivers/net/wireless/hostap/hostap_hw.c b/drivers/net/wireless/hostap/hostap_hw.c
index ed00ebb6e7f4..a394a23b9a20 100644
--- a/drivers/net/wireless/hostap/hostap_hw.c
+++ b/drivers/net/wireless/hostap/hostap_hw.c
@@ -347,14 +347,12 @@ static int hfa384x_cmd(struct net_device *dev, u16 cmd, u16 param0,
         if (signal_pending(current))
                 return -EINTR;
 
-        entry = (struct hostap_cmd_queue *)
-                kmalloc(sizeof(*entry), GFP_ATOMIC);
+        entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
         if (entry == NULL) {
                 printk(KERN_DEBUG "%s: hfa384x_cmd - kmalloc failed\n",
                        dev->name);
                 return -ENOMEM;
         }
-        memset(entry, 0, sizeof(*entry));
         atomic_set(&entry->usecnt, 1);
         entry->type = CMD_SLEEP;
         entry->cmd = cmd;
@@ -517,14 +515,12 @@ static int hfa384x_cmd_callback(struct net_device *dev, u16 cmd, u16 param0,
                 return -1;
         }
 
-        entry = (struct hostap_cmd_queue *)
-                kmalloc(sizeof(*entry), GFP_ATOMIC);
+        entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
         if (entry == NULL) {
                 printk(KERN_DEBUG "%s: hfa384x_cmd_callback - kmalloc "
                        "failed\n", dev->name);
                 return -ENOMEM;
         }
-        memset(entry, 0, sizeof(*entry));
         atomic_set(&entry->usecnt, 1);
         entry->type = CMD_CALLBACK;
         entry->cmd = cmd;
@@ -1645,9 +1641,9 @@ static void prism2_schedule_reset(local_info_t *local)
 
 /* Called only as scheduled task after noticing card timeout in interrupt
  * context */
-static void handle_reset_queue(void *data)
+static void handle_reset_queue(struct work_struct *work)
 {
-        local_info_t *local = (local_info_t *) data;
+        local_info_t *local = container_of(work, local_info_t, reset_queue);
 
         printk(KERN_DEBUG "%s: scheduled card reset\n", local->dev->name);
         prism2_hw_reset(local->dev);
@@ -2896,9 +2892,10 @@ static void hostap_passive_scan(unsigned long data)
 
 /* Called only as a scheduled task when communications quality values should
  * be updated. */
-static void handle_comms_qual_update(void *data)
+static void handle_comms_qual_update(struct work_struct *work)
 {
-        local_info_t *local = data;
+        local_info_t *local =
+                container_of(work, local_info_t, comms_qual_update);
         prism2_update_comms_qual(local->dev);
 }
 
@@ -3015,14 +3012,12 @@ static int prism2_set_tim(struct net_device *dev, int aid, int set)
         iface = netdev_priv(dev);
         local = iface->local;
 
-        new_entry = (struct set_tim_data *)
-                kmalloc(sizeof(*new_entry), GFP_ATOMIC);
+        new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
         if (new_entry == NULL) {
                 printk(KERN_DEBUG "%s: prism2_set_tim: kmalloc failed\n",
                        local->dev->name);
                 return -ENOMEM;
         }
-        memset(new_entry, 0, sizeof(*new_entry));
         new_entry->aid = aid;
         new_entry->set = set;
 
@@ -3050,9 +3045,9 @@ static int prism2_set_tim(struct net_device *dev, int aid, int set)
 }
 
 
-static void handle_set_tim_queue(void *data)
+static void handle_set_tim_queue(struct work_struct *work)
 {
-        local_info_t *local = (local_info_t *) data;
+        local_info_t *local = container_of(work, local_info_t, set_tim_queue);
         struct set_tim_data *entry;
         u16 val;
 
@@ -3209,15 +3204,15 @@ prism2_init_local_data(struct prism2_helper_functions *funcs, int card_idx,
         local->scan_channel_mask = 0xffff;
 
         /* Initialize task queue structures */
-        INIT_WORK(&local->reset_queue, handle_reset_queue, local);
+        INIT_WORK(&local->reset_queue, handle_reset_queue);
         INIT_WORK(&local->set_multicast_list_queue,
-                  hostap_set_multicast_list_queue, local->dev);
+                  hostap_set_multicast_list_queue);
 
-        INIT_WORK(&local->set_tim_queue, handle_set_tim_queue, local);
+        INIT_WORK(&local->set_tim_queue, handle_set_tim_queue);
         INIT_LIST_HEAD(&local->set_tim_list);
         spin_lock_init(&local->set_tim_lock);
 
-        INIT_WORK(&local->comms_qual_update, handle_comms_qual_update, local);
+        INIT_WORK(&local->comms_qual_update, handle_comms_qual_update);
 
         /* Initialize tasklets for handling hardware IRQ related operations
          * outside hw IRQ handler */
diff --git a/drivers/net/wireless/hostap/hostap_info.c b/drivers/net/wireless/hostap/hostap_info.c
index 50f72d831cf4..b6a02a02da74 100644
--- a/drivers/net/wireless/hostap/hostap_info.c
+++ b/drivers/net/wireless/hostap/hostap_info.c
@@ -327,11 +327,10 @@ static void prism2_info_hostscanresults(local_info_t *local,
         ptr = (u8 *) pos;
 
         new_count = left / result_size;
-        results = kmalloc(new_count * sizeof(struct hfa384x_hostscan_result),
+        results = kcalloc(new_count, sizeof(struct hfa384x_hostscan_result),
                           GFP_ATOMIC);
         if (results == NULL)
                 return;
-        memset(results, 0, new_count * sizeof(struct hfa384x_hostscan_result));
 
         for (i = 0; i < new_count; i++) {
                 memcpy(&results[i], ptr, copy_len);
@@ -474,9 +473,9 @@ static void handle_info_queue_scanresults(local_info_t *local)
 
 /* Called only as scheduled task after receiving info frames (used to avoid
  * pending too much time in HW IRQ handler). */
-static void handle_info_queue(void *data)
+static void handle_info_queue(struct work_struct *work)
 {
-        local_info_t *local = (local_info_t *) data;
+        local_info_t *local = container_of(work, local_info_t, info_queue);
 
         if (test_and_clear_bit(PRISM2_INFO_PENDING_LINKSTATUS,
                                &local->pending_info))
@@ -493,7 +492,7 @@ void hostap_info_init(local_info_t *local)
 {
         skb_queue_head_init(&local->info_list);
 #ifndef PRISM2_NO_STATION_MODES
-        INIT_WORK(&local->info_queue, handle_info_queue, local);
+        INIT_WORK(&local->info_queue, handle_info_queue);
 #endif /* PRISM2_NO_STATION_MODES */
 }
 
diff --git a/drivers/net/wireless/hostap/hostap_ioctl.c b/drivers/net/wireless/hostap/hostap_ioctl.c
index d061fb3443ff..3b7b8063ff1c 100644
--- a/drivers/net/wireless/hostap/hostap_ioctl.c
+++ b/drivers/net/wireless/hostap/hostap_ioctl.c
@@ -181,12 +181,10 @@ static int prism2_ioctl_siwencode(struct net_device *dev,
                 struct ieee80211_crypt_data *new_crypt;
 
                 /* take WEP into use */
-                new_crypt = (struct ieee80211_crypt_data *)
-                        kmalloc(sizeof(struct ieee80211_crypt_data),
+                new_crypt = kzalloc(sizeof(struct ieee80211_crypt_data),
                                 GFP_KERNEL);
                 if (new_crypt == NULL)
                         return -ENOMEM;
-                memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data));
                 new_crypt->ops = ieee80211_get_crypto_ops("WEP");
                 if (!new_crypt->ops) {
                         request_module("ieee80211_crypt_wep");
@@ -3320,14 +3318,12 @@ static int prism2_ioctl_siwencodeext(struct net_device *dev,
 
                 prism2_crypt_delayed_deinit(local, crypt);
 
-                new_crypt = (struct ieee80211_crypt_data *)
-                        kmalloc(sizeof(struct ieee80211_crypt_data),
+                new_crypt = kzalloc(sizeof(struct ieee80211_crypt_data),
                                 GFP_KERNEL);
                 if (new_crypt == NULL) {
                         ret = -ENOMEM;
                         goto done;
                 }
-                memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data));
                 new_crypt->ops = ops;
                 new_crypt->priv = new_crypt->ops->init(i);
                 if (new_crypt->priv == NULL) {
@@ -3538,14 +3534,12 @@ static int prism2_ioctl_set_encryption(local_info_t *local,
 
                 prism2_crypt_delayed_deinit(local, crypt);
 
-                new_crypt = (struct ieee80211_crypt_data *)
-                        kmalloc(sizeof(struct ieee80211_crypt_data),
+                new_crypt = kzalloc(sizeof(struct ieee80211_crypt_data),
                                 GFP_KERNEL);
                 if (new_crypt == NULL) {
                         ret = -ENOMEM;
                         goto done;
                 }
-                memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data));
                 new_crypt->ops = ops;
                 new_crypt->priv = new_crypt->ops->init(param->u.crypt.idx);
                 if (new_crypt->priv == NULL) {
diff --git a/drivers/net/wireless/hostap/hostap_main.c b/drivers/net/wireless/hostap/hostap_main.c
index 53374fcba77e..0796be9d9e77 100644
--- a/drivers/net/wireless/hostap/hostap_main.c
+++ b/drivers/net/wireless/hostap/hostap_main.c
@@ -767,14 +767,14 @@ static int prism2_set_mac_address(struct net_device *dev, void *p)
 
 /* TODO: to be further implemented as soon as Prism2 fully supports
  *       GroupAddresses and correct documentation is available */
-void hostap_set_multicast_list_queue(void *data)
+void hostap_set_multicast_list_queue(struct work_struct *work)
 {
-        struct net_device *dev = (struct net_device *) data;
+        local_info_t *local =
+                container_of(work, local_info_t, set_multicast_list_queue);
+        struct net_device *dev = local->dev;
         struct hostap_interface *iface;
-        local_info_t *local;
 
         iface = netdev_priv(dev);
-        local = iface->local;
         if (hostap_set_word(dev, HFA384X_RID_PROMISCUOUSMODE,
                             local->is_promisc)) {
                 printk(KERN_INFO "%s: %sabling promiscuous mode failed\n",
diff --git a/drivers/net/wireless/hostap/hostap_pci.c b/drivers/net/wireless/hostap/hostap_pci.c
index d1de9766c831..c4f6020baa9e 100644
--- a/drivers/net/wireless/hostap/hostap_pci.c
+++ b/drivers/net/wireless/hostap/hostap_pci.c
@@ -300,10 +300,9 @@ static int prism2_pci_probe(struct pci_dev *pdev,
         struct hostap_interface *iface;
         struct hostap_pci_priv *hw_priv;
 
-        hw_priv = kmalloc(sizeof(*hw_priv), GFP_KERNEL);
+        hw_priv = kzalloc(sizeof(*hw_priv), GFP_KERNEL);
         if (hw_priv == NULL)
                 return -ENOMEM;
-        memset(hw_priv, 0, sizeof(*hw_priv));
 
         if (pci_enable_device(pdev))
                 goto err_out_free;
diff --git a/drivers/net/wireless/hostap/hostap_plx.c b/drivers/net/wireless/hostap/hostap_plx.c
index bc81b13a5a2a..e235e0647897 100644
--- a/drivers/net/wireless/hostap/hostap_plx.c
+++ b/drivers/net/wireless/hostap/hostap_plx.c
@@ -447,10 +447,9 @@ static int prism2_plx_probe(struct pci_dev *pdev,
         int tmd7160;
         struct hostap_plx_priv *hw_priv;
 
-        hw_priv = kmalloc(sizeof(*hw_priv), GFP_KERNEL);
+        hw_priv = kzalloc(sizeof(*hw_priv), GFP_KERNEL);
         if (hw_priv == NULL)
                 return -ENOMEM;
-        memset(hw_priv, 0, sizeof(*hw_priv));
 
         if (pci_enable_device(pdev))
                 goto err_out_free;
diff --git a/drivers/net/wireless/ipw2100.c b/drivers/net/wireless/ipw2100.c
index 79607b8b877c..dd9ba4aad7bb 100644
--- a/drivers/net/wireless/ipw2100.c
+++ b/drivers/net/wireless/ipw2100.c
@@ -316,7 +316,7 @@ static void ipw2100_release_firmware(struct ipw2100_priv *priv,
                                      struct ipw2100_fw *fw);
 static int ipw2100_ucode_download(struct ipw2100_priv *priv,
                                   struct ipw2100_fw *fw);
-static void ipw2100_wx_event_work(struct ipw2100_priv *priv);
+static void ipw2100_wx_event_work(struct work_struct *work);
 static struct iw_statistics *ipw2100_wx_wireless_stats(struct net_device *dev);
 static struct iw_handler_def ipw2100_wx_handler_def;
 
@@ -679,7 +679,8 @@ static void schedule_reset(struct ipw2100_priv *priv)
                         queue_delayed_work(priv->workqueue, &priv->reset_work,
                                            priv->reset_backoff * HZ);
                 else
-                        queue_work(priv->workqueue, &priv->reset_work);
+                        queue_delayed_work(priv->workqueue, &priv->reset_work,
+                                           0);
 
                 if (priv->reset_backoff < MAX_RESET_BACKOFF)
                         priv->reset_backoff++;
@@ -1873,8 +1874,10 @@ static void ipw2100_down(struct ipw2100_priv *priv)
         netif_stop_queue(priv->net_dev);
 }
 
-static void ipw2100_reset_adapter(struct ipw2100_priv *priv)
+static void ipw2100_reset_adapter(struct work_struct *work)
 {
+        struct ipw2100_priv *priv =
+                container_of(work, struct ipw2100_priv, reset_work.work);
         unsigned long flags;
         union iwreq_data wrqu = {
                 .ap_addr = {
@@ -2071,9 +2074,9 @@ static void isr_indicate_association_lost(struct ipw2100_priv *priv, u32 status)
                 return;
 
         if (priv->status & STATUS_SECURITY_UPDATED)
-                queue_work(priv->workqueue, &priv->security_work);
+                queue_delayed_work(priv->workqueue, &priv->security_work, 0);
 
-        queue_work(priv->workqueue, &priv->wx_event_work);
+        queue_delayed_work(priv->workqueue, &priv->wx_event_work, 0);
 }
 
 static void isr_indicate_rf_kill(struct ipw2100_priv *priv, u32 status)
@@ -5524,8 +5527,11 @@ static int ipw2100_configure_security(struct ipw2100_priv *priv, int batch_mode)
         return err;
 }
 
-static void ipw2100_security_work(struct ipw2100_priv *priv)
+static void ipw2100_security_work(struct work_struct *work)
 {
+        struct ipw2100_priv *priv =
+                container_of(work, struct ipw2100_priv, security_work.work);
+
         /* If we happen to have reconnected before we get a chance to
          * process this, then update the security settings--which causes
          * a disassociation to occur */
@@ -5748,7 +5754,7 @@ static int ipw2100_set_address(struct net_device *dev, void *p)
 
         priv->reset_backoff = 0;
         mutex_unlock(&priv->action_mutex);
-        ipw2100_reset_adapter(priv);
+        ipw2100_reset_adapter(&priv->reset_work.work);
         return 0;
 
       done:
@@ -5910,9 +5916,10 @@ static const struct ethtool_ops ipw2100_ethtool_ops = {
         .get_drvinfo = ipw_ethtool_get_drvinfo,
 };
 
-static void ipw2100_hang_check(void *adapter)
+static void ipw2100_hang_check(struct work_struct *work)
 {
-        struct ipw2100_priv *priv = adapter;
+        struct ipw2100_priv *priv =
+                container_of(work, struct ipw2100_priv, hang_check.work);
         unsigned long flags;
         u32 rtc = 0xa5a5a5a5;
         u32 len = sizeof(rtc);
@@ -5952,9 +5959,10 @@ static void ipw2100_hang_check(void *adapter)
         spin_unlock_irqrestore(&priv->low_lock, flags);
 }
 
-static void ipw2100_rf_kill(void *adapter)
+static void ipw2100_rf_kill(struct work_struct *work)
 {
-        struct ipw2100_priv *priv = adapter;
+        struct ipw2100_priv *priv =
+                container_of(work, struct ipw2100_priv, rf_kill.work);
         unsigned long flags;
 
         spin_lock_irqsave(&priv->low_lock, flags);
@@ -6103,14 +6111,11 @@ static struct net_device *ipw2100_alloc_device(struct pci_dev *pci_dev,
 
         priv->workqueue = create_workqueue(DRV_NAME);
 
-        INIT_WORK(&priv->reset_work,
-                  (void (*)(void *))ipw2100_reset_adapter, priv);
-        INIT_WORK(&priv->security_work,
-                  (void (*)(void *))ipw2100_security_work, priv);
-        INIT_WORK(&priv->wx_event_work,
-                  (void (*)(void *))ipw2100_wx_event_work, priv);
-        INIT_WORK(&priv->hang_check, ipw2100_hang_check, priv);
-        INIT_WORK(&priv->rf_kill, ipw2100_rf_kill, priv);
+        INIT_DELAYED_WORK(&priv->reset_work, ipw2100_reset_adapter);
+        INIT_DELAYED_WORK(&priv->security_work, ipw2100_security_work);
+        INIT_DELAYED_WORK(&priv->wx_event_work, ipw2100_wx_event_work);
+        INIT_DELAYED_WORK(&priv->hang_check, ipw2100_hang_check);
+        INIT_DELAYED_WORK(&priv->rf_kill, ipw2100_rf_kill);
 
         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
                      ipw2100_irq_tasklet, (unsigned long)priv);
@@ -6215,7 +6220,7 @@ static int ipw2100_pci_init_one(struct pci_dev *pci_dev,
         /* Allocate and initialize the Tx/Rx queues and lists */
         if (ipw2100_queues_allocate(priv)) {
                 printk(KERN_WARNING DRV_NAME
-                       "Error calilng ipw2100_queues_allocate.\n");
+                       "Error calling ipw2100_queues_allocate.\n");
                 err = -ENOMEM;
                 goto fail;
         }
@@ -8281,8 +8286,10 @@ static struct iw_handler_def ipw2100_wx_handler_def = {
         .get_wireless_stats = ipw2100_wx_wireless_stats,
 };
 
-static void ipw2100_wx_event_work(struct ipw2100_priv *priv)
+static void ipw2100_wx_event_work(struct work_struct *work)
 {
+        struct ipw2100_priv *priv =
+                container_of(work, struct ipw2100_priv, wx_event_work.work);
         union iwreq_data wrqu;
         int len = ETH_ALEN;
 
diff --git a/drivers/net/wireless/ipw2100.h b/drivers/net/wireless/ipw2100.h
index 55b7227198df..de7d384d38af 100644
--- a/drivers/net/wireless/ipw2100.h
+++ b/drivers/net/wireless/ipw2100.h
@@ -583,11 +583,11 @@ struct ipw2100_priv {
         struct tasklet_struct irq_tasklet;
 
         struct workqueue_struct *workqueue;
-        struct work_struct reset_work;
-        struct work_struct security_work;
-        struct work_struct wx_event_work;
-        struct work_struct hang_check;
-        struct work_struct rf_kill;
+        struct delayed_work reset_work;
+        struct delayed_work security_work;
+        struct delayed_work wx_event_work;
+        struct delayed_work hang_check;
+        struct delayed_work rf_kill;
 
         u32 interrupts;
         int tx_interrupts;
diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c
index c692d01a76ca..22cb3fb7502e 100644
--- a/drivers/net/wireless/ipw2200.c
+++ b/drivers/net/wireless/ipw2200.c
@@ -70,7 +70,7 @@
 #define VQ
 #endif
 
-#define IPW2200_VERSION "1.1.4" VK VD VM VP VR VQ
+#define IPW2200_VERSION "1.2.0" VK VD VM VP VR VQ
 #define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver"
 #define DRV_COPYRIGHT   "Copyright(c) 2003-2006 Intel Corporation"
 #define DRV_VERSION     IPW2200_VERSION
@@ -187,9 +187,9 @@ static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *);
 static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *);
 static void ipw_rx_queue_replenish(void *);
 static int ipw_up(struct ipw_priv *);
-static void ipw_bg_up(void *);
+static void ipw_bg_up(struct work_struct *work);
 static void ipw_down(struct ipw_priv *);
-static void ipw_bg_down(void *);
+static void ipw_bg_down(struct work_struct *work);
 static int ipw_config(struct ipw_priv *);
 static int init_supported_rates(struct ipw_priv *priv,
                                 struct ipw_supported_rates *prates);
@@ -862,11 +862,12 @@ static void ipw_led_link_on(struct ipw_priv *priv)
         spin_unlock_irqrestore(&priv->lock, flags);
 }
 
-static void ipw_bg_led_link_on(void *data)
+static void ipw_bg_led_link_on(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, led_link_on.work);
         mutex_lock(&priv->mutex);
-        ipw_led_link_on(data);
+        ipw_led_link_on(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -906,11 +907,12 @@ static void ipw_led_link_off(struct ipw_priv *priv)
         spin_unlock_irqrestore(&priv->lock, flags);
 }
 
-static void ipw_bg_led_link_off(void *data)
+static void ipw_bg_led_link_off(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, led_link_off.work);
         mutex_lock(&priv->mutex);
-        ipw_led_link_off(data);
+        ipw_led_link_off(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -985,11 +987,12 @@ static void ipw_led_activity_off(struct ipw_priv *priv)
         spin_unlock_irqrestore(&priv->lock, flags);
 }
 
-static void ipw_bg_led_activity_off(void *data)
+static void ipw_bg_led_activity_off(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, led_act_off.work);
         mutex_lock(&priv->mutex);
-        ipw_led_activity_off(data);
+        ipw_led_activity_off(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -2228,11 +2231,12 @@ static void ipw_adapter_restart(void *adapter)
         }
 }
 
-static void ipw_bg_adapter_restart(void *data)
+static void ipw_bg_adapter_restart(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, adapter_restart);
         mutex_lock(&priv->mutex);
-        ipw_adapter_restart(data);
+        ipw_adapter_restart(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -2249,11 +2253,12 @@ static void ipw_scan_check(void *data)
         }
 }
 
-static void ipw_bg_scan_check(void *data)
+static void ipw_bg_scan_check(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, scan_check.work);
         mutex_lock(&priv->mutex);
-        ipw_scan_check(data);
+        ipw_scan_check(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -3831,17 +3836,19 @@ static int ipw_disassociate(void *data)
         return 1;
 }
 
-static void ipw_bg_disassociate(void *data)
+static void ipw_bg_disassociate(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, disassociate);
         mutex_lock(&priv->mutex);
-        ipw_disassociate(data);
+        ipw_disassociate(priv);
         mutex_unlock(&priv->mutex);
 }
 
-static void ipw_system_config(void *data)
+static void ipw_system_config(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, system_config);
 
 #ifdef CONFIG_IPW2200_PROMISCUOUS
         if (priv->prom_net_dev && netif_running(priv->prom_net_dev)) {
@@ -4208,11 +4215,12 @@ static void ipw_gather_stats(struct ipw_priv *priv)
                            IPW_STATS_INTERVAL);
 }
 
-static void ipw_bg_gather_stats(void *data)
+static void ipw_bg_gather_stats(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, gather_stats.work);
         mutex_lock(&priv->mutex);
-        ipw_gather_stats(data);
+        ipw_gather_stats(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -4268,8 +4276,8 @@ static void ipw_handle_missed_beacon(struct ipw_priv *priv,
                 if (!(priv->status & STATUS_ROAMING)) {
                         priv->status |= STATUS_ROAMING;
                         if (!(priv->status & STATUS_SCANNING))
-                                queue_work(priv->workqueue,
-                                           &priv->request_scan);
+                                queue_delayed_work(priv->workqueue,
+                                                   &priv->request_scan, 0);
                 }
                 return;
         }
@@ -4607,8 +4615,8 @@ static void ipw_rx_notification(struct ipw_priv *priv,
 #ifdef CONFIG_IPW2200_MONITOR
                         if (priv->ieee->iw_mode == IW_MODE_MONITOR) {
                                 priv->status |= STATUS_SCAN_FORCED;
-                                queue_work(priv->workqueue,
-                                           &priv->request_scan);
+                                queue_delayed_work(priv->workqueue,
+                                                   &priv->request_scan, 0);
                                 break;
                         }
                         priv->status &= ~STATUS_SCAN_FORCED;
@@ -4631,8 +4639,8 @@ static void ipw_rx_notification(struct ipw_priv *priv,
                                         /* Don't schedule if we aborted the scan */
                                         priv->status &= ~STATUS_ROAMING;
                         } else if (priv->status & STATUS_SCAN_PENDING)
-                                queue_work(priv->workqueue,
-                                           &priv->request_scan);
+                                queue_delayed_work(priv->workqueue,
+                                                   &priv->request_scan, 0);
                         else if (priv->config & CFG_BACKGROUND_SCAN
                                  && priv->status & STATUS_ASSOCIATED)
                                 queue_delayed_work(priv->workqueue,
@@ -5055,11 +5063,12 @@ static void ipw_rx_queue_replenish(void *data)
         ipw_rx_queue_restock(priv);
 }
 
-static void ipw_bg_rx_queue_replenish(void *data)
+static void ipw_bg_rx_queue_replenish(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, rx_replenish);
         mutex_lock(&priv->mutex);
-        ipw_rx_queue_replenish(data);
+        ipw_rx_queue_replenish(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -5489,9 +5498,10 @@ static int ipw_find_adhoc_network(struct ipw_priv *priv,
         return 1;
 }
 
-static void ipw_merge_adhoc_network(void *data)
+static void ipw_merge_adhoc_network(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, merge_networks);
         struct ieee80211_network *network = NULL;
         struct ipw_network_match match = {
                 .network = priv->assoc_network
@@ -5948,11 +5958,12 @@ static void ipw_adhoc_check(void *data)
                            priv->assoc_request.beacon_interval);
 }
 
-static void ipw_bg_adhoc_check(void *data)
+static void ipw_bg_adhoc_check(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, adhoc_check.work);
         mutex_lock(&priv->mutex);
-        ipw_adhoc_check(data);
+        ipw_adhoc_check(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -6299,19 +6310,26 @@ done:
         return err;
 }
 
-static int ipw_request_passive_scan(struct ipw_priv *priv) {
-        return ipw_request_scan_helper(priv, IW_SCAN_TYPE_PASSIVE);
+static void ipw_request_passive_scan(struct work_struct *work)
+{
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, request_passive_scan);
+        ipw_request_scan_helper(priv, IW_SCAN_TYPE_PASSIVE);
 }
 
-static int ipw_request_scan(struct ipw_priv *priv) {
-        return ipw_request_scan_helper(priv, IW_SCAN_TYPE_ACTIVE);
+static void ipw_request_scan(struct work_struct *work)
+{
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, request_scan.work);
+        ipw_request_scan_helper(priv, IW_SCAN_TYPE_ACTIVE);
 }
 
-static void ipw_bg_abort_scan(void *data)
+static void ipw_bg_abort_scan(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, abort_scan);
         mutex_lock(&priv->mutex);
-        ipw_abort_scan(data);
+        ipw_abort_scan(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -7084,9 +7102,10 @@ static int ipw_qos_set_tx_queue_command(struct ipw_priv *priv,
 /*
 * background support to run QoS activate functionality
 */
-static void ipw_bg_qos_activate(void *data)
+static void ipw_bg_qos_activate(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, qos_activate);
 
         if (priv == NULL)
                 return;
@@ -7394,11 +7413,12 @@ static void ipw_roam(void *data)
         priv->status &= ~STATUS_ROAMING;
 }
 
-static void ipw_bg_roam(void *data)
+static void ipw_bg_roam(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, roam);
         mutex_lock(&priv->mutex);
-        ipw_roam(data);
+        ipw_roam(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -7479,8 +7499,8 @@ static int ipw_associate(void *data)
                                                    &priv->request_scan,
                                                    SCAN_INTERVAL);
                         else
-                                queue_work(priv->workqueue,
-                                           &priv->request_scan);
+                                queue_delayed_work(priv->workqueue,
+                                                   &priv->request_scan, 0);
                 }
 
                 return 0;
@@ -7491,11 +7511,12 @@ static int ipw_associate(void *data)
         return 1;
 }
 
-static void ipw_bg_associate(void *data)
+static void ipw_bg_associate(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, associate);
         mutex_lock(&priv->mutex);
-        ipw_associate(data);
+        ipw_associate(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -7656,7 +7677,8 @@ static void ipw_handle_data_packet_monitor(struct ipw_priv *priv,
 
         /* Big bitfield of all the fields we provide in radiotap */
         ipw_rt->rt_hdr.it_present =
-            ((1 << IEEE80211_RADIOTAP_FLAGS) |
+            ((1 << IEEE80211_RADIOTAP_TSFT) |
+             (1 << IEEE80211_RADIOTAP_FLAGS) |
              (1 << IEEE80211_RADIOTAP_RATE) |
              (1 << IEEE80211_RADIOTAP_CHANNEL) |
              (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
@@ -7665,10 +7687,14 @@ static void ipw_handle_data_packet_monitor(struct ipw_priv *priv,
 
         /* Zero the flags, we'll add to them as we go */
         ipw_rt->rt_flags = 0;
-        ipw_rt->rt_tsf = 0ULL;
+        ipw_rt->rt_tsf = (u64)(frame->parent_tsf[3] << 24 |
+                               frame->parent_tsf[2] << 16 |
+                               frame->parent_tsf[1] << 8  |
+                               frame->parent_tsf[0]);
 
         /* Convert signal to DBM */
         ipw_rt->rt_dbmsignal = antsignal;
+        ipw_rt->rt_dbmnoise = frame->noise;
 
         /* Convert the channel data and set the flags */
         ipw_rt->rt_channel = cpu_to_le16(ieee80211chan2mhz(received_channel));
@@ -7868,7 +7894,8 @@ static void ipw_handle_promiscuous_rx(struct ipw_priv *priv,
 
         /* Big bitfield of all the fields we provide in radiotap */
         ipw_rt->rt_hdr.it_present =
-            ((1 << IEEE80211_RADIOTAP_FLAGS) |
+            ((1 << IEEE80211_RADIOTAP_TSFT) |
+             (1 << IEEE80211_RADIOTAP_FLAGS) |
              (1 << IEEE80211_RADIOTAP_RATE) |
              (1 << IEEE80211_RADIOTAP_CHANNEL) |
              (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
@@ -7877,7 +7904,10 @@ static void ipw_handle_promiscuous_rx(struct ipw_priv *priv,
 
         /* Zero the flags, we'll add to them as we go */
         ipw_rt->rt_flags = 0;
-        ipw_rt->rt_tsf = 0ULL;
+        ipw_rt->rt_tsf = (u64)(frame->parent_tsf[3] << 24 |
+                               frame->parent_tsf[2] << 16 |
+                               frame->parent_tsf[1] << 8  |
+                               frame->parent_tsf[0]);
 
         /* Convert to DBM */
         ipw_rt->rt_dbmsignal = signal;
@@ -8276,7 +8306,7 @@ static void ipw_rx(struct ipw_priv *priv)
                                     ("Notification: subtype=%02X flags=%02X size=%d\n",
                                      pkt->u.notification.subtype,
                                      pkt->u.notification.flags,
-                                     pkt->u.notification.size);
+                                     le16_to_cpu(pkt->u.notification.size));
                                 ipw_rx_notification(priv, &pkt->u.notification);
                                 break;
                         }
@@ -9410,7 +9440,7 @@ static int ipw_wx_set_scan(struct net_device *dev,
 
         IPW_DEBUG_WX("Start scan\n");
 
-        queue_work(priv->workqueue, &priv->request_scan);
+        queue_delayed_work(priv->workqueue, &priv->request_scan, 0);
 
         return 0;
 }
@@ -10547,11 +10577,12 @@ static void ipw_rf_kill(void *adapter)
         spin_unlock_irqrestore(&priv->lock, flags);
 }
 
-static void ipw_bg_rf_kill(void *data)
+static void ipw_bg_rf_kill(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, rf_kill.work);
         mutex_lock(&priv->mutex);
-        ipw_rf_kill(data);
+        ipw_rf_kill(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -10582,11 +10613,12 @@ static void ipw_link_up(struct ipw_priv *priv)
                 queue_delayed_work(priv->workqueue, &priv->request_scan, HZ);
 }
 
-static void ipw_bg_link_up(void *data)
+static void ipw_bg_link_up(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, link_up);
         mutex_lock(&priv->mutex);
-        ipw_link_up(data);
+        ipw_link_up(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -10606,15 +10638,16 @@ static void ipw_link_down(struct ipw_priv *priv)
 
         if (!(priv->status & STATUS_EXIT_PENDING)) {
                 /* Queue up another scan... */
-                queue_work(priv->workqueue, &priv->request_scan);
+                queue_delayed_work(priv->workqueue, &priv->request_scan, 0);
         }
 }
 
-static void ipw_bg_link_down(void *data)
+static void ipw_bg_link_down(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, link_down);
         mutex_lock(&priv->mutex);
-        ipw_link_down(data);
+        ipw_link_down(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -10626,38 +10659,30 @@ static int ipw_setup_deferred_work(struct ipw_priv *priv)
         init_waitqueue_head(&priv->wait_command_queue);
         init_waitqueue_head(&priv->wait_state);
 
-        INIT_WORK(&priv->adhoc_check, ipw_bg_adhoc_check, priv);
-        INIT_WORK(&priv->associate, ipw_bg_associate, priv);
-        INIT_WORK(&priv->disassociate, ipw_bg_disassociate, priv);
-        INIT_WORK(&priv->system_config, ipw_system_config, priv);
-        INIT_WORK(&priv->rx_replenish, ipw_bg_rx_queue_replenish, priv);
-        INIT_WORK(&priv->adapter_restart, ipw_bg_adapter_restart, priv);
-        INIT_WORK(&priv->rf_kill, ipw_bg_rf_kill, priv);
-        INIT_WORK(&priv->up, (void (*)(void *))ipw_bg_up, priv);
-        INIT_WORK(&priv->down, (void (*)(void *))ipw_bg_down, priv);
-        INIT_WORK(&priv->request_scan,
-                  (void (*)(void *))ipw_request_scan, priv);
-        INIT_WORK(&priv->request_passive_scan,
-                  (void (*)(void *))ipw_request_passive_scan, priv);
-        INIT_WORK(&priv->gather_stats,
-                  (void (*)(void *))ipw_bg_gather_stats, priv);
-        INIT_WORK(&priv->abort_scan, (void (*)(void *))ipw_bg_abort_scan, priv);
-        INIT_WORK(&priv->roam, ipw_bg_roam, priv);
-        INIT_WORK(&priv->scan_check, ipw_bg_scan_check, priv);
-        INIT_WORK(&priv->link_up, (void (*)(void *))ipw_bg_link_up, priv);
-        INIT_WORK(&priv->link_down, (void (*)(void *))ipw_bg_link_down, priv);
-        INIT_WORK(&priv->led_link_on, (void (*)(void *))ipw_bg_led_link_on,
-                  priv);
-        INIT_WORK(&priv->led_link_off, (void (*)(void *))ipw_bg_led_link_off,
-                  priv);
-        INIT_WORK(&priv->led_act_off, (void (*)(void *))ipw_bg_led_activity_off,
-                  priv);
-        INIT_WORK(&priv->merge_networks,
-                  (void (*)(void *))ipw_merge_adhoc_network, priv);
+        INIT_DELAYED_WORK(&priv->adhoc_check, ipw_bg_adhoc_check);
+        INIT_WORK(&priv->associate, ipw_bg_associate);
+        INIT_WORK(&priv->disassociate, ipw_bg_disassociate);
+        INIT_WORK(&priv->system_config, ipw_system_config);
+        INIT_WORK(&priv->rx_replenish, ipw_bg_rx_queue_replenish);
+        INIT_WORK(&priv->adapter_restart, ipw_bg_adapter_restart);
+        INIT_DELAYED_WORK(&priv->rf_kill, ipw_bg_rf_kill);
+        INIT_WORK(&priv->up, ipw_bg_up);
+        INIT_WORK(&priv->down, ipw_bg_down);
+        INIT_DELAYED_WORK(&priv->request_scan, ipw_request_scan);
+        INIT_WORK(&priv->request_passive_scan, ipw_request_passive_scan);
+        INIT_DELAYED_WORK(&priv->gather_stats, ipw_bg_gather_stats);
+        INIT_WORK(&priv->abort_scan, ipw_bg_abort_scan);
+        INIT_WORK(&priv->roam, ipw_bg_roam);
+        INIT_DELAYED_WORK(&priv->scan_check, ipw_bg_scan_check);
+        INIT_WORK(&priv->link_up, ipw_bg_link_up);
+        INIT_WORK(&priv->link_down, ipw_bg_link_down);
+        INIT_DELAYED_WORK(&priv->led_link_on, ipw_bg_led_link_on);
+        INIT_DELAYED_WORK(&priv->led_link_off, ipw_bg_led_link_off);
+        INIT_DELAYED_WORK(&priv->led_act_off, ipw_bg_led_activity_off);
+        INIT_WORK(&priv->merge_networks, ipw_merge_adhoc_network);
 
 #ifdef CONFIG_IPW2200_QOS
-        INIT_WORK(&priv->qos_activate, (void (*)(void *))ipw_bg_qos_activate,
-                  priv);
+        INIT_WORK(&priv->qos_activate, ipw_bg_qos_activate);
 #endif                          /* CONFIG_IPW2200_QOS */
 
         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
@@ -11129,14 +11154,13 @@ static int ipw_up(struct ipw_priv *priv)
                 return -EIO;
 
         if (cmdlog && !priv->cmdlog) {
-                priv->cmdlog = kmalloc(sizeof(*priv->cmdlog) * cmdlog,
+                priv->cmdlog = kcalloc(cmdlog, sizeof(*priv->cmdlog),
                                        GFP_KERNEL);
                 if (priv->cmdlog == NULL) {
                         IPW_ERROR("Error allocating %d command log entries.\n",
                                   cmdlog);
                         return -ENOMEM;
                 } else {
-                        memset(priv->cmdlog, 0, sizeof(*priv->cmdlog) * cmdlog);
                         priv->cmdlog_len = cmdlog;
                 }
         }
@@ -11190,7 +11214,8 @@ static int ipw_up(struct ipw_priv *priv)
 
                         /* If configure to try and auto-associate, kick
                          * off a scan. */
-                        queue_work(priv->workqueue, &priv->request_scan);
+                        queue_delayed_work(priv->workqueue,
+                                           &priv->request_scan, 0);
 
                         return 0;
                 }
@@ -11211,11 +11236,12 @@ static int ipw_up(struct ipw_priv *priv)
         return -EIO;
 }
 
-static void ipw_bg_up(void *data)
+static void ipw_bg_up(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, up);
         mutex_lock(&priv->mutex);
-        ipw_up(data);
+        ipw_up(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -11282,11 +11308,12 @@ static void ipw_down(struct ipw_priv *priv)
         ipw_led_radio_off(priv);
 }
 
-static void ipw_bg_down(void *data)
+static void ipw_bg_down(struct work_struct *work)
 {
-        struct ipw_priv *priv = data;
+        struct ipw_priv *priv =
+                container_of(work, struct ipw_priv, down);
         mutex_lock(&priv->mutex);
-        ipw_down(data);
+        ipw_down(priv);
         mutex_unlock(&priv->mutex);
 }
 
diff --git a/drivers/net/wireless/ipw2200.h b/drivers/net/wireless/ipw2200.h
index dad5eedefbf1..626a240a87d8 100644
--- a/drivers/net/wireless/ipw2200.h
+++ b/drivers/net/wireless/ipw2200.h
@@ -1290,21 +1290,21 @@ struct ipw_priv {
 
         struct workqueue_struct *workqueue;
 
-        struct work_struct adhoc_check;
+        struct delayed_work adhoc_check;
         struct work_struct associate;
         struct work_struct disassociate;
         struct work_struct system_config;
         struct work_struct rx_replenish;
-        struct work_struct request_scan;
+        struct delayed_work request_scan;
         struct work_struct request_passive_scan;
         struct work_struct adapter_restart;
-        struct work_struct rf_kill;
+        struct delayed_work rf_kill;
         struct work_struct up;
         struct work_struct down;
-        struct work_struct gather_stats;
+        struct delayed_work gather_stats;
         struct work_struct abort_scan;
         struct work_struct roam;
-        struct work_struct scan_check;
+        struct delayed_work scan_check;
         struct work_struct link_up;
         struct work_struct link_down;
 
@@ -1319,9 +1319,9 @@ struct ipw_priv {
         u32 led_ofdm_on;
         u32 led_ofdm_off;
 
-        struct work_struct led_link_on;
-        struct work_struct led_link_off;
-        struct work_struct led_act_off;
+        struct delayed_work led_link_on;
+        struct delayed_work led_link_off;
+        struct delayed_work led_act_off;
         struct work_struct merge_networks;
 
         struct ipw_cmd_log *cmdlog;
diff --git a/drivers/net/wireless/netwave_cs.c b/drivers/net/wireless/netwave_cs.c
index 6714e0dfa8d6..644b4741ef74 100644
--- a/drivers/net/wireless/netwave_cs.c
+++ b/drivers/net/wireless/netwave_cs.c
@@ -735,10 +735,7 @@ do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 static int netwave_pcmcia_config(struct pcmcia_device *link) {
     struct net_device *dev = link->priv;
     netwave_private *priv = netdev_priv(dev);
-    tuple_t tuple;
-    cisparse_t parse;
     int i, j, last_ret, last_fn;
-    u_char buf[64];
     win_req_t req;
     memreq_t mem;
     u_char __iomem *ramBase = NULL;
@@ -746,21 +743,6 @@ static int netwave_pcmcia_config(struct pcmcia_device *link) {
     DEBUG(0, "netwave_pcmcia_config(0x%p)\n", link);
 
     /*
-      This reads the card's CONFIG tuple to find its configuration
-      registers.
-    */
-    tuple.Attributes = 0;
-    tuple.TupleData = (cisdata_t *) buf;
-    tuple.TupleDataMax = 64;
-    tuple.TupleOffset = 0;
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-    link->conf.ConfigBase = parse.config.base;
-    link->conf.Present = parse.config.rmask[0];
-
-    /*
      *  Try allocating IO ports.  This tries a few fixed addresses.
      *  If you want, you can also read the card's config table to
      *  pick addresses -- see the serial driver for an example.
diff --git a/drivers/net/wireless/orinoco.c b/drivers/net/wireless/orinoco.c
index 336cabac13b3..936c888e03e1 100644
--- a/drivers/net/wireless/orinoco.c
+++ b/drivers/net/wireless/orinoco.c
@@ -980,9 +980,11 @@ static void print_linkstatus(struct net_device *dev, u16 status)
 }
 
 /* Search scan results for requested BSSID, join it if found */
-static void orinoco_join_ap(struct net_device *dev)
+static void orinoco_join_ap(struct work_struct *work)
 {
-        struct orinoco_private *priv = netdev_priv(dev);
+        struct orinoco_private *priv =
+                container_of(work, struct orinoco_private, join_work);
+        struct net_device *dev = priv->ndev;
         struct hermes *hw = &priv->hw;
         int err;
         unsigned long flags;
@@ -1055,9 +1057,11 @@ static void orinoco_join_ap(struct net_device *dev)
 }
 
 /* Send new BSSID to userspace */
-static void orinoco_send_wevents(struct net_device *dev)
+static void orinoco_send_wevents(struct work_struct *work)
 {
-        struct orinoco_private *priv = netdev_priv(dev);
+        struct orinoco_private *priv =
+                container_of(work, struct orinoco_private, wevent_work);
+        struct net_device *dev = priv->ndev;
         struct hermes *hw = &priv->hw;
         union iwreq_data wrqu;
         int err;
@@ -1864,9 +1868,11 @@ __orinoco_set_multicast_list(struct net_device *dev)
 
 /* This must be called from user context, without locks held - use
  * schedule_work() */
-static void orinoco_reset(struct net_device *dev)
+static void orinoco_reset(struct work_struct *work)
 {
-        struct orinoco_private *priv = netdev_priv(dev);
+        struct orinoco_private *priv =
+                container_of(work, struct orinoco_private, reset_work);
+        struct net_device *dev = priv->ndev;
         struct hermes *hw = &priv->hw;
         int err;
         unsigned long flags;
@@ -2434,9 +2440,9 @@ struct net_device *alloc_orinocodev(int sizeof_card,
         priv->hw_unavailable = 1; /* orinoco_init() must clear this
                                    * before anything else touches the
                                    * hardware */
-        INIT_WORK(&priv->reset_work, (void (*)(void *))orinoco_reset, dev);
-        INIT_WORK(&priv->join_work, (void (*)(void *))orinoco_join_ap, dev);
-        INIT_WORK(&priv->wevent_work, (void (*)(void *))orinoco_send_wevents, dev);
+        INIT_WORK(&priv->reset_work, orinoco_reset);
+        INIT_WORK(&priv->join_work, orinoco_join_ap);
+        INIT_WORK(&priv->wevent_work, orinoco_send_wevents);
 
         netif_carrier_off(dev);
         priv->last_linkstatus = 0xffff;
@@ -3608,7 +3614,7 @@ static int orinoco_ioctl_reset(struct net_device *dev,
                 printk(KERN_DEBUG "%s: Forcing reset!\n", dev->name);
 
                 /* Firmware reset */
-                orinoco_reset(dev);
+                orinoco_reset(&priv->reset_work);
         } else {
                 printk(KERN_DEBUG "%s: Force scheduling reset!\n", dev->name);
 
@@ -4154,7 +4160,7 @@ static int orinoco_ioctl_commit(struct net_device *dev,
                 return 0;
 
         if (priv->broken_disableport) {
-                orinoco_reset(dev);
+                orinoco_reset(&priv->reset_work);
                 return 0;
         }
 
diff --git a/drivers/net/wireless/orinoco_cs.c b/drivers/net/wireless/orinoco_cs.c
index bc14689cbf24..d08ae8d2726c 100644
--- a/drivers/net/wireless/orinoco_cs.c
+++ b/drivers/net/wireless/orinoco_cs.c
@@ -178,21 +178,6 @@ orinoco_cs_config(struct pcmcia_device *link)
         cisparse_t parse;
         void __iomem *mem;
 
-        /*
-         * This reads the card's CONFIG tuple to find its
-         * configuration registers.
-         */
-        tuple.DesiredTuple = CISTPL_CONFIG;
-        tuple.Attributes = 0;
-        tuple.TupleData = buf;
-        tuple.TupleDataMax = sizeof(buf);
-        tuple.TupleOffset = 0;
-        CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-        CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-        link->conf.ConfigBase = parse.config.base;
-        link->conf.Present = parse.config.rmask[0];
-
         /* Look up the current Vcc */
         CS_CHECK(GetConfigurationInfo,
                  pcmcia_get_configuration_info(link, &conf));
@@ -211,6 +196,10 @@ orinoco_cs_config(struct pcmcia_device *link)
          * and most client drivers will only use the CIS to fill in
          * implementation-defined details.
          */
+        tuple.Attributes = 0;
+        tuple.TupleData = buf;
+        tuple.TupleDataMax = sizeof(buf);
+        tuple.TupleOffset = 0;
         tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
         CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
         while (1) {
diff --git a/drivers/net/wireless/prism54/isl_ioctl.c b/drivers/net/wireless/prism54/isl_ioctl.c
index 4a20e45de3ca..96606ed10076 100644
--- a/drivers/net/wireless/prism54/isl_ioctl.c
+++ b/drivers/net/wireless/prism54/isl_ioctl.c
@@ -157,8 +157,9 @@ prism54_mib_init(islpci_private *priv)
  * schedule_work(), thus we can as well use sleeping semaphore
  * locking */
 void
-prism54_update_stats(islpci_private *priv)
+prism54_update_stats(struct work_struct *work)
 {
+        islpci_private *priv = container_of(work, islpci_private, stats_work);
         char *data;
         int j;
         struct obj_bss bss, *bss2;
@@ -2140,11 +2141,9 @@ prism54_wpa_bss_ie_add(islpci_private *priv, u8 *bssid,
                                          struct islpci_bss_wpa_ie, list);
                         list_del(&bss->list);
                 } else {
-                        bss = kmalloc(sizeof (*bss), GFP_ATOMIC);
-                        if (bss != NULL) {
+                        bss = kzalloc(sizeof (*bss), GFP_ATOMIC);
+                        if (bss != NULL)
                                 priv->num_bss_wpa++;
-                                memset(bss, 0, sizeof (*bss));
-                        }
                 }
                 if (bss != NULL) {
                         memcpy(bss->bssid, bssid, ETH_ALEN);
@@ -2493,9 +2492,10 @@ prism54_process_trap_helper(islpci_private *priv, enum oid_num_t oid,
  * interrupt context, no locks held.
  */
 void
-prism54_process_trap(void *data)
+prism54_process_trap(struct work_struct *work)
 {
-        struct islpci_mgmtframe *frame = data;
+        struct islpci_mgmtframe *frame =
+                container_of(work, struct islpci_mgmtframe, ws);
         struct net_device *ndev = frame->ndev;
         enum oid_num_t n = mgt_oidtonum(frame->header->oid);
 
@@ -2684,11 +2684,10 @@ prism2_ioctl_set_generic_element(struct net_device *ndev,
                return -EINVAL;
 
        alen = sizeof(*attach) + len;
-       attach = kmalloc(alen, GFP_KERNEL);
+       attach = kzalloc(alen, GFP_KERNEL);
        if (attach == NULL)
                return -ENOMEM;
 
-       memset(attach, 0, alen);
 #define WLAN_FC_TYPE_MGMT 0
 #define WLAN_FC_STYPE_ASSOC_REQ 0
 #define WLAN_FC_STYPE_REASSOC_REQ 2
diff --git a/drivers/net/wireless/prism54/isl_ioctl.h b/drivers/net/wireless/prism54/isl_ioctl.h
index e8183d30c52e..bcfbfb9281d2 100644
--- a/drivers/net/wireless/prism54/isl_ioctl.h
+++ b/drivers/net/wireless/prism54/isl_ioctl.h
@@ -31,12 +31,12 @@
 void prism54_mib_init(islpci_private *);
 
 struct iw_statistics *prism54_get_wireless_stats(struct net_device *);
-void prism54_update_stats(islpci_private *);
+void prism54_update_stats(struct work_struct *);
 
 void prism54_acl_init(struct islpci_acl *);
 void prism54_acl_clean(struct islpci_acl *);
 
-void prism54_process_trap(void *);
+void prism54_process_trap(struct work_struct *);
 
 void prism54_wpa_bss_ie_init(islpci_private *priv);
 void prism54_wpa_bss_ie_clean(islpci_private *priv);
diff --git a/drivers/net/wireless/prism54/islpci_dev.c b/drivers/net/wireless/prism54/islpci_dev.c
index 1e0603ca436c..f057fd9fcd79 100644
--- a/drivers/net/wireless/prism54/islpci_dev.c
+++ b/drivers/net/wireless/prism54/islpci_dev.c
@@ -860,11 +860,10 @@ islpci_setup(struct pci_dev *pdev)
         priv->state_off = 1;
 
         /* initialize workqueue's */
-        INIT_WORK(&priv->stats_work,
-                  (void (*)(void *)) prism54_update_stats, priv);
+        INIT_WORK(&priv->stats_work, prism54_update_stats);
         priv->stats_timestamp = 0;
 
-        INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake, priv);
+        INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake);
         priv->reset_task_pending = 0;
 
         /* allocate various memory areas */
diff --git a/drivers/net/wireless/prism54/islpci_eth.c b/drivers/net/wireless/prism54/islpci_eth.c
index 676d83813dc8..b1122912ee2d 100644
--- a/drivers/net/wireless/prism54/islpci_eth.c
+++ b/drivers/net/wireless/prism54/islpci_eth.c
@@ -480,9 +480,9 @@ islpci_eth_receive(islpci_private *priv)
 }
 
 void
-islpci_do_reset_and_wake(void *data)
+islpci_do_reset_and_wake(struct work_struct *work)
 {
-        islpci_private *priv = data;
+        islpci_private *priv = container_of(work, islpci_private, reset_task);
 
         islpci_reset(priv, 1);
         priv->reset_task_pending = 0;
diff --git a/drivers/net/wireless/prism54/islpci_eth.h b/drivers/net/wireless/prism54/islpci_eth.h
index 26789454067c..5bf820defbd0 100644
--- a/drivers/net/wireless/prism54/islpci_eth.h
+++ b/drivers/net/wireless/prism54/islpci_eth.h
@@ -67,6 +67,6 @@ void islpci_eth_cleanup_transmit(islpci_private *, isl38xx_control_block *);
 int islpci_eth_transmit(struct sk_buff *, struct net_device *);
 int islpci_eth_receive(islpci_private *);
 void islpci_eth_tx_timeout(struct net_device *);
-void islpci_do_reset_and_wake(void *data);
+void islpci_do_reset_and_wake(struct work_struct *);
 
 #endif                          /* _ISL_GEN_H */
diff --git a/drivers/net/wireless/prism54/islpci_mgt.c b/drivers/net/wireless/prism54/islpci_mgt.c
index 036a875054c9..2246f7930b4e 100644
--- a/drivers/net/wireless/prism54/islpci_mgt.c
+++ b/drivers/net/wireless/prism54/islpci_mgt.c
@@ -386,7 +386,7 @@ islpci_mgt_receive(struct net_device *ndev)
 
                         /* Create work to handle trap out of interrupt
                          * context. */
-                        INIT_WORK(&frame->ws, prism54_process_trap, frame);
+                        INIT_WORK(&frame->ws, prism54_process_trap);
                         schedule_work(&frame->ws);
 
                 } else {
diff --git a/drivers/net/wireless/prism54/oid_mgt.c b/drivers/net/wireless/prism54/oid_mgt.c
index fbc52b6a3024..e6cf9df2c206 100644
--- a/drivers/net/wireless/prism54/oid_mgt.c
+++ b/drivers/net/wireless/prism54/oid_mgt.c
@@ -235,12 +235,10 @@ mgt_init(islpci_private *priv)
 {
         int i;
 
-        priv->mib = kmalloc(OID_NUM_LAST * sizeof (void *), GFP_KERNEL);
+        priv->mib = kcalloc(OID_NUM_LAST, sizeof (void *), GFP_KERNEL);
         if (!priv->mib)
                 return -ENOMEM;
 
-        memset(priv->mib, 0, OID_NUM_LAST * sizeof (void *));
-
         /* Alloc the cache */
         for (i = 0; i < OID_NUM_LAST; i++) {
                 if (isl_oid[i].flags & OID_FLAG_CACHED) {
diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c
index 7fbfc9e41d07..88e10c9bc4ac 100644
--- a/drivers/net/wireless/ray_cs.c
+++ b/drivers/net/wireless/ray_cs.c
@@ -408,11 +408,8 @@ do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 #define MAX_TUPLE_SIZE 128
 static int ray_config(struct pcmcia_device *link)
 {
-    tuple_t tuple;
-    cisparse_t parse;
     int last_fn = 0, last_ret = 0;
     int i;
-    u_char buf[MAX_TUPLE_SIZE];
     win_req_t req;
     memreq_t mem;
     struct net_device *dev = (struct net_device *)link->priv;
@@ -420,29 +417,12 @@ static int ray_config(struct pcmcia_device *link)
 
     DEBUG(1, "ray_config(0x%p)\n", link);
 
-    /* This reads the card's CONFIG tuple to find its configuration regs */
-    tuple.DesiredTuple = CISTPL_CONFIG;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-    tuple.TupleData = buf;
-    tuple.TupleDataMax = MAX_TUPLE_SIZE;
-    tuple.TupleOffset = 0;
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-    CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-    link->conf.ConfigBase = parse.config.base;
-    link->conf.Present = parse.config.rmask[0];
-
     /* Determine card type and firmware version */
-    buf[0] = buf[MAX_TUPLE_SIZE - 1] = 0;
-    tuple.DesiredTuple = CISTPL_VERS_1;
-    CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-    tuple.TupleData = buf;
-    tuple.TupleDataMax = MAX_TUPLE_SIZE;
-    tuple.TupleOffset = 2;
-    CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-
-    for (i=0; i<tuple.TupleDataLen - 4; i++) 
-        if (buf[i] == 0) buf[i] = ' ';
-    printk(KERN_INFO "ray_cs Detected: %s\n",buf);
+    printk(KERN_INFO "ray_cs Detected: %s%s%s%s\n",
+           link->prod_id[0] ? link->prod_id[0] : " ",
+           link->prod_id[1] ? link->prod_id[1] : " ",
+           link->prod_id[2] ? link->prod_id[2] : " ",
+           link->prod_id[3] ? link->prod_id[3] : " ");
 
     /* Now allocate an interrupt line.  Note that this does not
        actually assign a handler to the interrupt.
diff --git a/drivers/net/wireless/spectrum_cs.c b/drivers/net/wireless/spectrum_cs.c
index bcc7038130f6..cf2d1486b01d 100644
--- a/drivers/net/wireless/spectrum_cs.c
+++ b/drivers/net/wireless/spectrum_cs.c
@@ -647,21 +647,6 @@ spectrum_cs_config(struct pcmcia_device *link)
         cisparse_t parse;
         void __iomem *mem;
 
-        /*
-         * This reads the card's CONFIG tuple to find its
-         * configuration registers.
-         */
-        tuple.DesiredTuple = CISTPL_CONFIG;
-        tuple.Attributes = 0;
-        tuple.TupleData = buf;
-        tuple.TupleDataMax = sizeof(buf);
-        tuple.TupleOffset = 0;
-        CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-        CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-        link->conf.ConfigBase = parse.config.base;
-        link->conf.Present = parse.config.rmask[0];
-
         /* Look up the current Vcc */
         CS_CHECK(GetConfigurationInfo,
                  pcmcia_get_configuration_info(link, &conf));
@@ -681,6 +666,10 @@ spectrum_cs_config(struct pcmcia_device *link)
          * implementation-defined details.
          */
         tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
+        tuple.Attributes = 0;
+        tuple.TupleData = buf;
+        tuple.TupleDataMax = sizeof(buf);
+        tuple.TupleOffset = 0;
         CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
         while (1) {
                 cistpl_cftable_entry_t *cfg = &(parse.cftable_entry);
diff --git a/drivers/net/wireless/wavelan_cs.c b/drivers/net/wireless/wavelan_cs.c
index aafb301041b1..233d906c08f0 100644
--- a/drivers/net/wireless/wavelan_cs.c
+++ b/drivers/net/wireless/wavelan_cs.c
@@ -3939,11 +3939,8 @@ wv_hw_reset(struct net_device *	dev)
 static inline int
 wv_pcmcia_config(struct pcmcia_device * link)
 {
-  tuple_t               tuple;
-  cisparse_t            parse;
   struct net_device *   dev = (struct net_device *) link->priv;
   int                   i;
-  u_char                buf[64];
   win_req_t             req;
   memreq_t              mem;
   net_local *           lp = netdev_priv(dev);
@@ -3953,36 +3950,6 @@ wv_pcmcia_config(struct pcmcia_device *	link)
   printk(KERN_DEBUG "->wv_pcmcia_config(0x%p)\n", link);
 #endif
 
-  /*
-   * This reads the card's CONFIG tuple to find its configuration
-   * registers.
-   */
-  do
-    {
-      tuple.Attributes = 0;
-      tuple.DesiredTuple = CISTPL_CONFIG;
-      i = pcmcia_get_first_tuple(link, &tuple);
-      if(i != CS_SUCCESS)
-        break;
-      tuple.TupleData = (cisdata_t *)buf;
-      tuple.TupleDataMax = 64;
-      tuple.TupleOffset = 0;
-      i = pcmcia_get_tuple_data(link, &tuple);
-      if(i != CS_SUCCESS)
-        break;
-      i = pcmcia_parse_tuple(link, &tuple, &parse);
-      if(i != CS_SUCCESS)
-        break;
-      link->conf.ConfigBase = parse.config.base;
-      link->conf.Present = parse.config.rmask[0];
-    }
-  while(0);
-  if(i != CS_SUCCESS)
-    {
-      cs_error(link, ParseTuple, i);
-      return FALSE;
-    }
-
   do
     {
       i = pcmcia_request_io(link, &link->io);
diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c
index 5b98a7876982..583e0d655a98 100644
--- a/drivers/net/wireless/wl3501_cs.c
+++ b/drivers/net/wireless/wl3501_cs.c
@@ -1966,25 +1966,10 @@ do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
  */
 static int wl3501_config(struct pcmcia_device *link)
 {
-        tuple_t tuple;
-        cisparse_t parse;
         struct net_device *dev = link->priv;
         int i = 0, j, last_fn, last_ret;
-        unsigned char bf[64];
         struct wl3501_card *this;
 
-        /* This reads the card's CONFIG tuple to find its config registers. */
-        tuple.Attributes        = 0;
-        tuple.DesiredTuple      = CISTPL_CONFIG;
-        CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
-        tuple.TupleData         = bf;
-        tuple.TupleDataMax      = sizeof(bf);
-        tuple.TupleOffset       = 0;
-        CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
-        CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
-        link->conf.ConfigBase   = parse.config.base;
-        link->conf.Present      = parse.config.rmask[0];
-
         /* Try allocating IO ports.  This tries a few fixed addresses.  If you
          * want, you can also read the card's config table to pick addresses --
          * see the serial driver for an example. */
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c
index 8be99ebbe1cd..77e11ddad836 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.c
+++ b/drivers/net/wireless/zd1211rw/zd_chip.c
@@ -1673,3 +1673,16 @@ int zd_rfwritev_cr_locked(struct zd_chip *chip,
 
         return 0;
 }
+
+int zd_chip_set_multicast_hash(struct zd_chip *chip,
+                               struct zd_mc_hash *hash)
+{
+        struct zd_ioreq32 ioreqs[] = {
+                { CR_GROUP_HASH_P1, hash->low },
+                { CR_GROUP_HASH_P2, hash->high },
+        };
+
+        dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n",
+                ioreqs[0].value, ioreqs[1].value);
+        return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
+}
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.h b/drivers/net/wireless/zd1211rw/zd_chip.h
index ca892b9a6448..a4e3cee9b59d 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.h
+++ b/drivers/net/wireless/zd1211rw/zd_chip.h
@@ -390,10 +390,19 @@
 #define CR_BSSID_P1                     CTL_REG(0x0618)
 #define CR_BSSID_P2                     CTL_REG(0x061C)
 #define CR_BCN_PLCP_CFG                 CTL_REG(0x0620)
+
+/* Group hash table for filtering incoming packets.
+ *
+ * The group hash table is 64 bit large and split over two parts. The first
+ * part is the lower part. The upper 6 bits of the last byte of the target
+ * address are used as index. Packets are received if the hash table bit is
+ * set. This is used for multicast handling, but for broadcasts (address
+ * ff:ff:ff:ff:ff:ff) the highest bit in the second table must also be set.
+ */
 #define CR_GROUP_HASH_P1                CTL_REG(0x0624)
 #define CR_GROUP_HASH_P2                CTL_REG(0x0628)
-#define CR_RX_TIMEOUT                   CTL_REG(0x062C)
 
+#define CR_RX_TIMEOUT                   CTL_REG(0x062C)
 /* Basic rates supported by the BSS. When producing ACK or CTS messages, the
  * device will use a rate in this table that is less than or equal to the rate
  * of the incoming frame which prompted the response */
@@ -864,4 +873,36 @@ u8 zd_rx_strength_percent(u8 rssi);
 
 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status);
 
+struct zd_mc_hash {
+        u32 low;
+        u32 high;
+};
+
+static inline void zd_mc_clear(struct zd_mc_hash *hash)
+{
+        hash->low = 0;
+        /* The interfaces must always received broadcasts.
+         * The hash of the broadcast address ff:ff:ff:ff:ff:ff is 63.
+         */
+        hash->high = 0x80000000;
+}
+
+static inline void zd_mc_add_all(struct zd_mc_hash *hash)
+{
+        hash->low = hash->high = 0xffffffff;
+}
+
+static inline void zd_mc_add_addr(struct zd_mc_hash *hash, u8 *addr)
+{
+        unsigned int i = addr[5] >> 2;
+        if (i < 32) {
+                hash->low |= 1 << i;
+        } else {
+                hash->high |= 1 << (i-32);
+        }
+}
+
+int zd_chip_set_multicast_hash(struct zd_chip *chip,
+                               struct zd_mc_hash *hash);
+
 #endif /* _ZD_CHIP_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c
index 2696f95b9278..61c7916b7656 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.c
+++ b/drivers/net/wireless/zd1211rw/zd_mac.c
@@ -32,13 +32,15 @@
 
 static void ieee_init(struct ieee80211_device *ieee);
 static void softmac_init(struct ieee80211softmac_device *sm);
-static void set_rts_cts_work(void *d);
-static void set_basic_rates_work(void *d);
+static void set_rts_cts_work(struct work_struct *work);
+static void set_basic_rates_work(struct work_struct *work);
 
 static void housekeeping_init(struct zd_mac *mac);
 static void housekeeping_enable(struct zd_mac *mac);
 static void housekeeping_disable(struct zd_mac *mac);
 
+static void set_multicast_hash_handler(void *mac_ptr);
+
 int zd_mac_init(struct zd_mac *mac,
                 struct net_device *netdev,
                 struct usb_interface *intf)
@@ -48,13 +50,15 @@ int zd_mac_init(struct zd_mac *mac,
         memset(mac, 0, sizeof(*mac));
         spin_lock_init(&mac->lock);
         mac->netdev = netdev;
-        INIT_WORK(&mac->set_rts_cts_work, set_rts_cts_work, mac);
-        INIT_WORK(&mac->set_basic_rates_work, set_basic_rates_work, mac);
+        INIT_DELAYED_WORK(&mac->set_rts_cts_work, set_rts_cts_work);
+        INIT_DELAYED_WORK(&mac->set_basic_rates_work, set_basic_rates_work);
 
         ieee_init(ieee);
         softmac_init(ieee80211_priv(netdev));
         zd_chip_init(&mac->chip, netdev, intf);
         housekeeping_init(mac);
+        INIT_WORK(&mac->set_multicast_hash_work, set_multicast_hash_handler,
+                  mac);
         return 0;
 }
 
@@ -136,6 +140,7 @@ out:
 
 void zd_mac_clear(struct zd_mac *mac)
 {
+        flush_workqueue(zd_workqueue);
         zd_chip_clear(&mac->chip);
         ZD_ASSERT(!spin_is_locked(&mac->lock));
         ZD_MEMCLEAR(mac, sizeof(struct zd_mac));
@@ -256,6 +261,42 @@ int zd_mac_set_mac_address(struct net_device *netdev, void *p)
         return 0;
 }
 
+static void set_multicast_hash_handler(void *mac_ptr)
+{
+        struct zd_mac *mac = mac_ptr;
+        struct zd_mc_hash hash;
+
+        spin_lock_irq(&mac->lock);
+        hash = mac->multicast_hash;
+        spin_unlock_irq(&mac->lock);
+
+        zd_chip_set_multicast_hash(&mac->chip, &hash);
+}
+
+void zd_mac_set_multicast_list(struct net_device *dev)
+{
+        struct zd_mc_hash hash;
+        struct zd_mac *mac = zd_netdev_mac(dev);
+        struct dev_mc_list *mc;
+        unsigned long flags;
+
+        if (dev->flags & (IFF_PROMISC|IFF_ALLMULTI)) {
+                zd_mc_add_all(&hash);
+        } else {
+                zd_mc_clear(&hash);
+                for (mc = dev->mc_list; mc; mc = mc->next) {
+                        dev_dbg_f(zd_mac_dev(mac), "mc addr " MAC_FMT "\n",
+                                  MAC_ARG(mc->dmi_addr));
+                        zd_mc_add_addr(&hash, mc->dmi_addr);
+                }
+        }
+
+        spin_lock_irqsave(&mac->lock, flags);
+        mac->multicast_hash = hash;
+        spin_unlock_irqrestore(&mac->lock, flags);
+        queue_work(zd_workqueue, &mac->set_multicast_hash_work);
+}
+
 int zd_mac_set_regdomain(struct zd_mac *mac, u8 regdomain)
 {
         int r;
@@ -366,9 +407,10 @@ static void try_enable_tx(struct zd_mac *mac)
         spin_unlock_irqrestore(&mac->lock, flags);
 }
 
-static void set_rts_cts_work(void *d)
+static void set_rts_cts_work(struct work_struct *work)
 {
-        struct zd_mac *mac = d;
+        struct zd_mac *mac =
+                container_of(work, struct zd_mac, set_rts_cts_work.work);
         unsigned long flags;
         u8 rts_rate;
         unsigned int short_preamble;
@@ -387,9 +429,10 @@ static void set_rts_cts_work(void *d)
         try_enable_tx(mac);
 }
 
-static void set_basic_rates_work(void *d)
+static void set_basic_rates_work(struct work_struct *work)
 {
-        struct zd_mac *mac = d;
+        struct zd_mac *mac =
+                container_of(work, struct zd_mac, set_basic_rates_work.work);
         unsigned long flags;
         u16 basic_rates;
 
@@ -467,12 +510,13 @@ static void bssinfo_change(struct net_device *netdev, u32 changes)
         if (need_set_rts_cts && !mac->updating_rts_rate) {
                 mac->updating_rts_rate = 1;
                 netif_stop_queue(mac->netdev);
-                queue_work(zd_workqueue, &mac->set_rts_cts_work);
+                queue_delayed_work(zd_workqueue, &mac->set_rts_cts_work, 0);
         }
         if (need_set_rates && !mac->updating_basic_rates) {
                 mac->updating_basic_rates = 1;
                 netif_stop_queue(mac->netdev);
-                queue_work(zd_workqueue, &mac->set_basic_rates_work);
+                queue_delayed_work(zd_workqueue, &mac->set_basic_rates_work,
+                                   0);
         }
         spin_unlock_irqrestore(&mac->lock, flags);
 }
@@ -615,6 +659,9 @@ int zd_mac_get_range(struct zd_mac *mac, struct iw_range *range)
         range->we_version_compiled = WIRELESS_EXT;
         range->we_version_source = 20;
 
+        range->enc_capa = IW_ENC_CAPA_WPA |  IW_ENC_CAPA_WPA2 |
+                          IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP;
+
         ZD_ASSERT(!irqs_disabled());
         spin_lock_irq(&mac->lock);
         regdomain = mac->regdomain;
@@ -927,7 +974,8 @@ static int is_data_packet_for_us(struct ieee80211_device *ieee,
         }
 
         return memcmp(hdr->addr1, netdev->dev_addr, ETH_ALEN) == 0 ||
-               is_multicast_ether_addr(hdr->addr1) ||
+               (is_multicast_ether_addr(hdr->addr1) &&
+                memcmp(hdr->addr3, netdev->dev_addr, ETH_ALEN) != 0) ||
                (netdev->flags & IFF_PROMISC);
 }
 
@@ -1059,10 +1107,8 @@ int zd_mac_rx(struct zd_mac *mac, const u8 *buffer, unsigned int length)
         memcpy(skb_put(skb, length), buffer, length);
 
         r = ieee80211_rx(ieee, skb, &stats);
-        if (!r) {
-                ZD_ASSERT(in_irq());
-                dev_kfree_skb_irq(skb);
-        }
+        if (!r)
+                dev_kfree_skb_any(skb);
         return 0;
 }
 
@@ -1182,9 +1228,10 @@ struct iw_statistics *zd_mac_get_wireless_stats(struct net_device *ndev)
 
 #define LINK_LED_WORK_DELAY HZ
 
-static void link_led_handler(void *p)
+static void link_led_handler(struct work_struct *work)
 {
-        struct zd_mac *mac = p;
+        struct zd_mac *mac =
+                container_of(work, struct zd_mac, housekeeping.link_led_work.work);
         struct zd_chip *chip = &mac->chip;
         struct ieee80211softmac_device *sm = ieee80211_priv(mac->netdev);
         int is_associated;
@@ -1205,7 +1252,7 @@ static void link_led_handler(void *p)
 
 static void housekeeping_init(struct zd_mac *mac)
 {
-        INIT_WORK(&mac->housekeeping.link_led_work, link_led_handler, mac);
+        INIT_DELAYED_WORK(&mac->housekeeping.link_led_work, link_led_handler);
 }
 
 static void housekeeping_enable(struct zd_mac *mac)
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.h b/drivers/net/wireless/zd1211rw/zd_mac.h
index 5dcfb251f02e..f0cf05dc7d3e 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.h
+++ b/drivers/net/wireless/zd1211rw/zd_mac.h
@@ -119,7 +119,7 @@ struct rx_status {
 #define ZD_RX_ERROR                     0x80
 
 struct housekeeping {
-        struct work_struct link_led_work;
+        struct delayed_work link_led_work;
 };
 
 #define ZD_MAC_STATS_BUFFER_SIZE 16
@@ -133,8 +133,10 @@ struct zd_mac {
         struct iw_statistics iw_stats;
 
         struct housekeeping housekeeping;
-        struct work_struct set_rts_cts_work;
-        struct work_struct set_basic_rates_work;
+        struct work_struct set_multicast_hash_work;
+        struct zd_mc_hash multicast_hash;
+        struct delayed_work set_rts_cts_work;
+        struct delayed_work set_basic_rates_work;
 
         unsigned int stats_count;
         u8 qual_buffer[ZD_MAC_STATS_BUFFER_SIZE];
@@ -189,6 +191,7 @@ int zd_mac_init_hw(struct zd_mac *mac, u8 device_type);
 int zd_mac_open(struct net_device *netdev);
 int zd_mac_stop(struct net_device *netdev);
 int zd_mac_set_mac_address(struct net_device *dev, void *p);
+void zd_mac_set_multicast_list(struct net_device *netdev);
 
 int zd_mac_rx(struct zd_mac *mac, const u8 *buffer, unsigned int length);
 
diff --git a/drivers/net/wireless/zd1211rw/zd_netdev.c b/drivers/net/wireless/zd1211rw/zd_netdev.c
index 60f1b0f6d45b..8bda48de31ef 100644
--- a/drivers/net/wireless/zd1211rw/zd_netdev.c
+++ b/drivers/net/wireless/zd1211rw/zd_netdev.c
@@ -242,7 +242,7 @@ struct net_device *zd_netdev_alloc(struct usb_interface *intf)
         netdev->open = zd_mac_open;
         netdev->stop = zd_mac_stop;
         /* netdev->get_stats = */
-        /* netdev->set_multicast_list = */
+        netdev->set_multicast_list = zd_mac_set_multicast_list;
         netdev->set_mac_address = zd_mac_set_mac_address;
         netdev->wireless_handlers = &iw_handler_def;
         /* netdev->ethtool_ops = */