diff options
Diffstat (limited to 'drivers/net')
23 files changed, 220 insertions, 101 deletions
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c index dc15d248443f..ef8d2a080d17 100644 --- a/drivers/net/bonding/bond_sysfs.c +++ b/drivers/net/bonding/bond_sysfs.c | |||
| @@ -1060,7 +1060,7 @@ static ssize_t bonding_store_primary(struct device *d, | |||
| 1060 | goto out; | 1060 | goto out; |
| 1061 | } | 1061 | } |
| 1062 | 1062 | ||
| 1063 | sscanf(buf, "%16s", ifname); /* IFNAMSIZ */ | 1063 | sscanf(buf, "%15s", ifname); /* IFNAMSIZ */ |
| 1064 | 1064 | ||
| 1065 | /* check to see if we are clearing primary */ | 1065 | /* check to see if we are clearing primary */ |
| 1066 | if (!strlen(ifname) || buf[0] == '\n') { | 1066 | if (!strlen(ifname) || buf[0] == '\n') { |
| @@ -1237,7 +1237,7 @@ static ssize_t bonding_store_active_slave(struct device *d, | |||
| 1237 | goto out; | 1237 | goto out; |
| 1238 | } | 1238 | } |
| 1239 | 1239 | ||
| 1240 | sscanf(buf, "%16s", ifname); /* IFNAMSIZ */ | 1240 | sscanf(buf, "%15s", ifname); /* IFNAMSIZ */ |
| 1241 | 1241 | ||
| 1242 | /* check to see if we are clearing active */ | 1242 | /* check to see if we are clearing active */ |
| 1243 | if (!strlen(ifname) || buf[0] == '\n') { | 1243 | if (!strlen(ifname) || buf[0] == '\n') { |
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c index c65295dded39..6e5bdd1a31d9 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c | |||
| @@ -1702,7 +1702,7 @@ static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) | |||
| 1702 | SHMEM_EEE_ADV_STATUS_SHIFT); | 1702 | SHMEM_EEE_ADV_STATUS_SHIFT); |
| 1703 | if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { | 1703 | if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { |
| 1704 | DP(BNX2X_MSG_ETHTOOL, | 1704 | DP(BNX2X_MSG_ETHTOOL, |
| 1705 | "Direct manipulation of EEE advertisment is not supported\n"); | 1705 | "Direct manipulation of EEE advertisement is not supported\n"); |
| 1706 | return -EINVAL; | 1706 | return -EINVAL; |
| 1707 | } | 1707 | } |
| 1708 | 1708 | ||
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c index e2e45ee5df33..f6cfdc6cf20f 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | |||
| @@ -137,7 +137,16 @@ | |||
| 137 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD | 137 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD |
| 138 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD | 138 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD |
| 139 | 139 | ||
| 140 | 140 | #define LINK_UPDATE_MASK \ | |
| 141 | (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ | ||
| 142 | LINK_STATUS_LINK_UP | \ | ||
| 143 | LINK_STATUS_PHYSICAL_LINK_FLAG | \ | ||
| 144 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ | ||
| 145 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ | ||
| 146 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ | ||
| 147 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ | ||
| 148 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ | ||
| 149 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) | ||
| 141 | 150 | ||
| 142 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 | 151 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
| 143 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 | 152 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
| @@ -3295,6 +3304,21 @@ static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) | |||
| 3295 | DEFAULT_PHY_DEV_ADDR); | 3304 | DEFAULT_PHY_DEV_ADDR); |
| 3296 | } | 3305 | } |
| 3297 | 3306 | ||
| 3307 | static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, | ||
| 3308 | struct link_params *params, | ||
| 3309 | u32 action) | ||
| 3310 | { | ||
| 3311 | struct bnx2x *bp = params->bp; | ||
| 3312 | switch (action) { | ||
| 3313 | case PHY_INIT: | ||
| 3314 | /* Set correct devad */ | ||
| 3315 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); | ||
| 3316 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, | ||
| 3317 | phy->def_md_devad); | ||
| 3318 | break; | ||
| 3319 | } | ||
| 3320 | } | ||
| 3321 | |||
| 3298 | static void bnx2x_xgxs_deassert(struct link_params *params) | 3322 | static void bnx2x_xgxs_deassert(struct link_params *params) |
| 3299 | { | 3323 | { |
| 3300 | struct bnx2x *bp = params->bp; | 3324 | struct bnx2x *bp = params->bp; |
| @@ -3309,10 +3333,8 @@ static void bnx2x_xgxs_deassert(struct link_params *params) | |||
| 3309 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | 3333 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
| 3310 | udelay(500); | 3334 | udelay(500); |
| 3311 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | 3335 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); |
| 3312 | 3336 | bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, | |
| 3313 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0); | 3337 | PHY_INIT); |
| 3314 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, | ||
| 3315 | params->phy[INT_PHY].def_md_devad); | ||
| 3316 | } | 3338 | } |
| 3317 | 3339 | ||
| 3318 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, | 3340 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
| @@ -3545,14 +3567,11 @@ static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, | |||
| 3545 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | 3567 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, |
| 3546 | struct link_params *params, | 3568 | struct link_params *params, |
| 3547 | struct link_vars *vars) { | 3569 | struct link_vars *vars) { |
| 3548 | u16 val16 = 0, lane, i; | 3570 | u16 lane, i, cl72_ctrl, an_adv = 0; |
| 3571 | u16 ucode_ver; | ||
| 3549 | struct bnx2x *bp = params->bp; | 3572 | struct bnx2x *bp = params->bp; |
| 3550 | static struct bnx2x_reg_set reg_set[] = { | 3573 | static struct bnx2x_reg_set reg_set[] = { |
| 3551 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | 3574 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, |
| 3552 | {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, | ||
| 3553 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0}, | ||
| 3554 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff}, | ||
| 3555 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555}, | ||
| 3556 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, | 3575 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, |
| 3557 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, | 3576 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, |
| 3558 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, | 3577 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, |
| @@ -3565,12 +3584,19 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |||
| 3565 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | 3584 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
| 3566 | reg_set[i].val); | 3585 | reg_set[i].val); |
| 3567 | 3586 | ||
| 3587 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | ||
| 3588 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); | ||
| 3589 | cl72_ctrl &= 0xf8ff; | ||
| 3590 | cl72_ctrl |= 0x3800; | ||
| 3591 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
| 3592 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); | ||
| 3593 | |||
| 3568 | /* Check adding advertisement for 1G KX */ | 3594 | /* Check adding advertisement for 1G KX */ |
| 3569 | if (((vars->line_speed == SPEED_AUTO_NEG) && | 3595 | if (((vars->line_speed == SPEED_AUTO_NEG) && |
| 3570 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | 3596 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
| 3571 | (vars->line_speed == SPEED_1000)) { | 3597 | (vars->line_speed == SPEED_1000)) { |
| 3572 | u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; | 3598 | u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; |
| 3573 | val16 |= (1<<5); | 3599 | an_adv |= (1<<5); |
| 3574 | 3600 | ||
| 3575 | /* Enable CL37 1G Parallel Detect */ | 3601 | /* Enable CL37 1G Parallel Detect */ |
| 3576 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); | 3602 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); |
| @@ -3580,11 +3606,14 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |||
| 3580 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | 3606 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || |
| 3581 | (vars->line_speed == SPEED_10000)) { | 3607 | (vars->line_speed == SPEED_10000)) { |
| 3582 | /* Check adding advertisement for 10G KR */ | 3608 | /* Check adding advertisement for 10G KR */ |
| 3583 | val16 |= (1<<7); | 3609 | an_adv |= (1<<7); |
| 3584 | /* Enable 10G Parallel Detect */ | 3610 | /* Enable 10G Parallel Detect */ |
| 3611 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | ||
| 3612 | MDIO_AER_BLOCK_AER_REG, 0); | ||
| 3613 | |||
| 3585 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | 3614 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 3586 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); | 3615 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); |
| 3587 | 3616 | bnx2x_set_aer_mmd(params, phy); | |
| 3588 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); | 3617 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); |
| 3589 | } | 3618 | } |
| 3590 | 3619 | ||
| @@ -3604,7 +3633,7 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |||
| 3604 | 3633 | ||
| 3605 | /* Advertised speeds */ | 3634 | /* Advertised speeds */ |
| 3606 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | 3635 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| 3607 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16); | 3636 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); |
| 3608 | 3637 | ||
| 3609 | /* Advertised and set FEC (Forward Error Correction) */ | 3638 | /* Advertised and set FEC (Forward Error Correction) */ |
| 3610 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | 3639 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
| @@ -3628,9 +3657,10 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |||
| 3628 | /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 | 3657 | /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 |
| 3629 | */ | 3658 | */ |
| 3630 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | 3659 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
| 3631 | MDIO_WC_REG_UC_INFO_B1_VERSION, &val16); | 3660 | MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver); |
| 3632 | if (val16 < 0xd108) { | 3661 | if (ucode_ver < 0xd108) { |
| 3633 | DP(NETIF_MSG_LINK, "Enable AN KR work-around\n"); | 3662 | DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n", |
| 3663 | ucode_ver); | ||
| 3634 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | 3664 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; |
| 3635 | } | 3665 | } |
| 3636 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | 3666 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| @@ -3651,21 +3681,16 @@ static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, | |||
| 3651 | struct link_vars *vars) | 3681 | struct link_vars *vars) |
| 3652 | { | 3682 | { |
| 3653 | struct bnx2x *bp = params->bp; | 3683 | struct bnx2x *bp = params->bp; |
| 3654 | u16 i; | 3684 | u16 val16, i, lane; |
| 3655 | static struct bnx2x_reg_set reg_set[] = { | 3685 | static struct bnx2x_reg_set reg_set[] = { |
| 3656 | /* Disable Autoneg */ | 3686 | /* Disable Autoneg */ |
| 3657 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | 3687 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, |
| 3658 | {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, | ||
| 3659 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | 3688 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, |
| 3660 | 0x3f00}, | 3689 | 0x3f00}, |
| 3661 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, | 3690 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, |
| 3662 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, | 3691 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, |
| 3663 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, | 3692 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, |
| 3664 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, | 3693 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, |
| 3665 | /* Disable CL36 PCS Tx */ | ||
| 3666 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0}, | ||
| 3667 | /* Double Wide Single Data Rate @ pll rate */ | ||
| 3668 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF}, | ||
| 3669 | /* Leave cl72 training enable, needed for KR */ | 3694 | /* Leave cl72 training enable, needed for KR */ |
| 3670 | {MDIO_PMA_DEVAD, | 3695 | {MDIO_PMA_DEVAD, |
| 3671 | MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150, | 3696 | MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150, |
| @@ -3676,11 +3701,24 @@ static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, | |||
| 3676 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | 3701 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
| 3677 | reg_set[i].val); | 3702 | reg_set[i].val); |
| 3678 | 3703 | ||
| 3679 | /* Leave CL72 enabled */ | 3704 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 3680 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | 3705 | /* Global registers */ |
| 3681 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | 3706 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
| 3682 | 0x3800); | 3707 | MDIO_AER_BLOCK_AER_REG, 0); |
| 3708 | /* Disable CL36 PCS Tx */ | ||
| 3709 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | ||
| 3710 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | ||
| 3711 | val16 &= ~(0x0011 << lane); | ||
| 3712 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
| 3713 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | ||
| 3683 | 3714 | ||
| 3715 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | ||
| 3716 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | ||
| 3717 | val16 |= (0x0303 << (lane << 1)); | ||
| 3718 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
| 3719 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | ||
| 3720 | /* Restore AER */ | ||
| 3721 | bnx2x_set_aer_mmd(params, phy); | ||
| 3684 | /* Set speed via PMA/PMD register */ | 3722 | /* Set speed via PMA/PMD register */ |
| 3685 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | 3723 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, |
| 3686 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | 3724 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); |
| @@ -4303,7 +4341,7 @@ static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, | |||
| 4303 | struct link_params *params) | 4341 | struct link_params *params) |
| 4304 | { | 4342 | { |
| 4305 | struct bnx2x *bp = params->bp; | 4343 | struct bnx2x *bp = params->bp; |
| 4306 | u16 val16; | 4344 | u16 val16, lane; |
| 4307 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); | 4345 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); |
| 4308 | bnx2x_set_mdio_clk(bp, params->chip_id, params->port); | 4346 | bnx2x_set_mdio_clk(bp, params->chip_id, params->port); |
| 4309 | bnx2x_set_aer_mmd(params, phy); | 4347 | bnx2x_set_aer_mmd(params, phy); |
| @@ -4340,6 +4378,30 @@ static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, | |||
| 4340 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | 4378 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, |
| 4341 | val16 & 0xff00); | 4379 | val16 & 0xff00); |
| 4342 | 4380 | ||
| 4381 | lane = bnx2x_get_warpcore_lane(phy, params); | ||
| 4382 | /* Disable CL36 PCS Tx */ | ||
| 4383 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | ||
| 4384 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | ||
| 4385 | val16 |= (0x11 << lane); | ||
| 4386 | if (phy->flags & FLAGS_WC_DUAL_MODE) | ||
| 4387 | val16 |= (0x22 << lane); | ||
| 4388 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
| 4389 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | ||
| 4390 | |||
| 4391 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | ||
| 4392 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | ||
| 4393 | val16 &= ~(0x0303 << (lane << 1)); | ||
| 4394 | val16 |= (0x0101 << (lane << 1)); | ||
| 4395 | if (phy->flags & FLAGS_WC_DUAL_MODE) { | ||
| 4396 | val16 &= ~(0x0c0c << (lane << 1)); | ||
| 4397 | val16 |= (0x0404 << (lane << 1)); | ||
| 4398 | } | ||
| 4399 | |||
| 4400 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | ||
| 4401 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | ||
| 4402 | /* Restore AER */ | ||
| 4403 | bnx2x_set_aer_mmd(params, phy); | ||
| 4404 | |||
| 4343 | } | 4405 | } |
| 4344 | 4406 | ||
| 4345 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, | 4407 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, |
| @@ -6296,15 +6358,7 @@ static int bnx2x_update_link_down(struct link_params *params, | |||
| 6296 | vars->mac_type = MAC_TYPE_NONE; | 6358 | vars->mac_type = MAC_TYPE_NONE; |
| 6297 | 6359 | ||
| 6298 | /* Update shared memory */ | 6360 | /* Update shared memory */ |
| 6299 | vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK | | 6361 | vars->link_status &= ~LINK_UPDATE_MASK; |
| 6300 | LINK_STATUS_LINK_UP | | ||
| 6301 | LINK_STATUS_PHYSICAL_LINK_FLAG | | ||
| 6302 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | | ||
| 6303 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | | ||
| 6304 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | | ||
| 6305 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | | ||
| 6306 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | | ||
| 6307 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE); | ||
| 6308 | vars->line_speed = 0; | 6362 | vars->line_speed = 0; |
| 6309 | bnx2x_update_mng(params, vars->link_status); | 6363 | bnx2x_update_mng(params, vars->link_status); |
| 6310 | 6364 | ||
| @@ -6452,6 +6506,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars) | |||
| 6452 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | 6506 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; |
| 6453 | u8 active_external_phy = INT_PHY; | 6507 | u8 active_external_phy = INT_PHY; |
| 6454 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; | 6508 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; |
| 6509 | vars->link_status &= ~LINK_UPDATE_MASK; | ||
| 6455 | for (phy_index = INT_PHY; phy_index < params->num_phys; | 6510 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
| 6456 | phy_index++) { | 6511 | phy_index++) { |
| 6457 | phy_vars[phy_index].flow_ctrl = 0; | 6512 | phy_vars[phy_index].flow_ctrl = 0; |
| @@ -7579,7 +7634,7 @@ static void bnx2x_warpcore_power_module(struct link_params *params, | |||
| 7579 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, | 7634 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7580 | struct link_params *params, | 7635 | struct link_params *params, |
| 7581 | u16 addr, u8 byte_cnt, | 7636 | u16 addr, u8 byte_cnt, |
| 7582 | u8 *o_buf) | 7637 | u8 *o_buf, u8 is_init) |
| 7583 | { | 7638 | { |
| 7584 | int rc = 0; | 7639 | int rc = 0; |
| 7585 | u8 i, j = 0, cnt = 0; | 7640 | u8 i, j = 0, cnt = 0; |
| @@ -7596,10 +7651,10 @@ static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, | |||
| 7596 | /* 4 byte aligned address */ | 7651 | /* 4 byte aligned address */ |
| 7597 | addr32 = addr & (~0x3); | 7652 | addr32 = addr & (~0x3); |
| 7598 | do { | 7653 | do { |
| 7599 | if (cnt == I2C_WA_PWR_ITER) { | 7654 | if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { |
| 7600 | bnx2x_warpcore_power_module(params, phy, 0); | 7655 | bnx2x_warpcore_power_module(params, phy, 0); |
| 7601 | /* Note that 100us are not enough here */ | 7656 | /* Note that 100us are not enough here */ |
| 7602 | usleep_range(1000,1000); | 7657 | usleep_range(1000, 2000); |
| 7603 | bnx2x_warpcore_power_module(params, phy, 1); | 7658 | bnx2x_warpcore_power_module(params, phy, 1); |
| 7604 | } | 7659 | } |
| 7605 | rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, | 7660 | rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, |
| @@ -7719,7 +7774,7 @@ int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, | |||
| 7719 | break; | 7774 | break; |
| 7720 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | 7775 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
| 7721 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, | 7776 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, |
| 7722 | byte_cnt, o_buf); | 7777 | byte_cnt, o_buf, 0); |
| 7723 | break; | 7778 | break; |
| 7724 | } | 7779 | } |
| 7725 | return rc; | 7780 | return rc; |
| @@ -7923,6 +7978,7 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, | |||
| 7923 | 7978 | ||
| 7924 | { | 7979 | { |
| 7925 | u8 val; | 7980 | u8 val; |
| 7981 | int rc; | ||
| 7926 | struct bnx2x *bp = params->bp; | 7982 | struct bnx2x *bp = params->bp; |
| 7927 | u16 timeout; | 7983 | u16 timeout; |
| 7928 | /* Initialization time after hot-plug may take up to 300ms for | 7984 | /* Initialization time after hot-plug may take up to 300ms for |
| @@ -7930,8 +7986,14 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, | |||
| 7930 | */ | 7986 | */ |
| 7931 | 7987 | ||
| 7932 | for (timeout = 0; timeout < 60; timeout++) { | 7988 | for (timeout = 0; timeout < 60; timeout++) { |
| 7933 | if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val) | 7989 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
| 7934 | == 0) { | 7990 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, |
| 7991 | params, 1, | ||
| 7992 | 1, &val, 1); | ||
| 7993 | else | ||
| 7994 | rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, | ||
| 7995 | &val); | ||
| 7996 | if (rc == 0) { | ||
| 7935 | DP(NETIF_MSG_LINK, | 7997 | DP(NETIF_MSG_LINK, |
| 7936 | "SFP+ module initialization took %d ms\n", | 7998 | "SFP+ module initialization took %d ms\n", |
| 7937 | timeout * 5); | 7999 | timeout * 5); |
| @@ -7939,7 +8001,8 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, | |||
| 7939 | } | 8001 | } |
| 7940 | usleep_range(5000, 10000); | 8002 | usleep_range(5000, 10000); |
| 7941 | } | 8003 | } |
| 7942 | return -EINVAL; | 8004 | rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val); |
| 8005 | return rc; | ||
| 7943 | } | 8006 | } |
| 7944 | 8007 | ||
| 7945 | static void bnx2x_8727_power_module(struct bnx2x *bp, | 8008 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
| @@ -9878,7 +9941,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
| 9878 | else | 9941 | else |
| 9879 | rc = bnx2x_8483x_disable_eee(phy, params, vars); | 9942 | rc = bnx2x_8483x_disable_eee(phy, params, vars); |
| 9880 | if (rc) { | 9943 | if (rc) { |
| 9881 | DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n"); | 9944 | DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); |
| 9882 | return rc; | 9945 | return rc; |
| 9883 | } | 9946 | } |
| 9884 | } else { | 9947 | } else { |
| @@ -10993,7 +11056,7 @@ static struct bnx2x_phy phy_xgxs = { | |||
| 10993 | .format_fw_ver = (format_fw_ver_t)NULL, | 11056 | .format_fw_ver = (format_fw_ver_t)NULL, |
| 10994 | .hw_reset = (hw_reset_t)NULL, | 11057 | .hw_reset = (hw_reset_t)NULL, |
| 10995 | .set_link_led = (set_link_led_t)NULL, | 11058 | .set_link_led = (set_link_led_t)NULL, |
| 10996 | .phy_specific_func = (phy_specific_func_t)NULL | 11059 | .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func |
| 10997 | }; | 11060 | }; |
| 10998 | static struct bnx2x_phy phy_warpcore = { | 11061 | static struct bnx2x_phy phy_warpcore = { |
| 10999 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | 11062 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
| @@ -11465,6 +11528,11 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, | |||
| 11465 | phy->media_type = ETH_PHY_BASE_T; | 11528 | phy->media_type = ETH_PHY_BASE_T; |
| 11466 | break; | 11529 | break; |
| 11467 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | 11530 | case PORT_HW_CFG_NET_SERDES_IF_XFI: |
| 11531 | phy->supported &= (SUPPORTED_1000baseT_Full | | ||
| 11532 | SUPPORTED_10000baseT_Full | | ||
| 11533 | SUPPORTED_FIBRE | | ||
| 11534 | SUPPORTED_Pause | | ||
| 11535 | SUPPORTED_Asym_Pause); | ||
| 11468 | phy->media_type = ETH_PHY_XFP_FIBER; | 11536 | phy->media_type = ETH_PHY_XFP_FIBER; |
| 11469 | break; | 11537 | break; |
| 11470 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | 11538 | case PORT_HW_CFG_NET_SERDES_IF_SFI: |
| @@ -12919,7 +12987,7 @@ static u8 bnx2x_analyze_link_error(struct link_params *params, | |||
| 12919 | DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); | 12987 | DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); |
| 12920 | break; | 12988 | break; |
| 12921 | default: | 12989 | default: |
| 12922 | DP(NETIF_MSG_LINK, "Analyze UNKOWN\n"); | 12990 | DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); |
| 12923 | } | 12991 | } |
| 12924 | DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, | 12992 | DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, |
| 12925 | old_status, status); | 12993 | old_status, status); |
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index d5648fc666bd..bd1fd3d87c24 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | |||
| @@ -6794,8 +6794,9 @@ static int bnx2x_init_hw_port(struct bnx2x *bp) | |||
| 6794 | 6794 | ||
| 6795 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | 6795 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
| 6796 | 6796 | ||
| 6797 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | ||
| 6798 | |||
| 6797 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | 6799 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
| 6798 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | ||
| 6799 | 6800 | ||
| 6800 | if (IS_MF(bp)) | 6801 | if (IS_MF(bp)) |
| 6801 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | 6802 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); |
| @@ -11902,7 +11903,15 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, | |||
| 11902 | /* disable FCOE L2 queue for E1x */ | 11903 | /* disable FCOE L2 queue for E1x */ |
| 11903 | if (CHIP_IS_E1x(bp)) | 11904 | if (CHIP_IS_E1x(bp)) |
| 11904 | bp->flags |= NO_FCOE_FLAG; | 11905 | bp->flags |= NO_FCOE_FLAG; |
| 11905 | 11906 | /* disable FCOE for 57840 device, until FW supports it */ | |
| 11907 | switch (ent->driver_data) { | ||
| 11908 | case BCM57840_O: | ||
| 11909 | case BCM57840_4_10: | ||
| 11910 | case BCM57840_2_20: | ||
| 11911 | case BCM57840_MFO: | ||
| 11912 | case BCM57840_MF: | ||
| 11913 | bp->flags |= NO_FCOE_FLAG; | ||
| 11914 | } | ||
| 11906 | #endif | 11915 | #endif |
| 11907 | 11916 | ||
| 11908 | 11917 | ||
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c index c1cde11b0c6d..0df1284df497 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | |||
| @@ -3416,16 +3416,6 @@ static int adap_init0_config(struct adapter *adapter, int reset) | |||
| 3416 | finicsum, cfcsum); | 3416 | finicsum, cfcsum); |
| 3417 | 3417 | ||
| 3418 | /* | 3418 | /* |
| 3419 | * If we're a pure NIC driver then disable all offloading facilities. | ||
| 3420 | * This will allow the firmware to optimize aspects of the hardware | ||
| 3421 | * configuration which will result in improved performance. | ||
| 3422 | */ | ||
| 3423 | caps_cmd.ofldcaps = 0; | ||
| 3424 | caps_cmd.iscsicaps = 0; | ||
| 3425 | caps_cmd.rdmacaps = 0; | ||
| 3426 | caps_cmd.fcoecaps = 0; | ||
| 3427 | |||
| 3428 | /* | ||
| 3429 | * And now tell the firmware to use the configuration we just loaded. | 3419 | * And now tell the firmware to use the configuration we just loaded. |
| 3430 | */ | 3420 | */ |
| 3431 | caps_cmd.op_to_write = | 3421 | caps_cmd.op_to_write = |
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c index 32eec15fe4c2..730ae2cfa49e 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | |||
| @@ -2519,6 +2519,7 @@ int t4_fw_bye(struct adapter *adap, unsigned int mbox) | |||
| 2519 | { | 2519 | { |
| 2520 | struct fw_bye_cmd c; | 2520 | struct fw_bye_cmd c; |
| 2521 | 2521 | ||
| 2522 | memset(&c, 0, sizeof(c)); | ||
| 2522 | INIT_CMD(c, BYE, WRITE); | 2523 | INIT_CMD(c, BYE, WRITE); |
| 2523 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | 2524 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
| 2524 | } | 2525 | } |
| @@ -2535,6 +2536,7 @@ int t4_early_init(struct adapter *adap, unsigned int mbox) | |||
| 2535 | { | 2536 | { |
| 2536 | struct fw_initialize_cmd c; | 2537 | struct fw_initialize_cmd c; |
| 2537 | 2538 | ||
| 2539 | memset(&c, 0, sizeof(c)); | ||
| 2538 | INIT_CMD(c, INITIALIZE, WRITE); | 2540 | INIT_CMD(c, INITIALIZE, WRITE); |
| 2539 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | 2541 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
| 2540 | } | 2542 | } |
| @@ -2551,6 +2553,7 @@ int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) | |||
| 2551 | { | 2553 | { |
| 2552 | struct fw_reset_cmd c; | 2554 | struct fw_reset_cmd c; |
| 2553 | 2555 | ||
| 2556 | memset(&c, 0, sizeof(c)); | ||
| 2554 | INIT_CMD(c, RESET, WRITE); | 2557 | INIT_CMD(c, RESET, WRITE); |
| 2555 | c.val = htonl(reset); | 2558 | c.val = htonl(reset); |
| 2556 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | 2559 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
| @@ -2828,7 +2831,7 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, | |||
| 2828 | HOSTPAGESIZEPF7(sge_hps)); | 2831 | HOSTPAGESIZEPF7(sge_hps)); |
| 2829 | 2832 | ||
| 2830 | t4_set_reg_field(adap, SGE_CONTROL, | 2833 | t4_set_reg_field(adap, SGE_CONTROL, |
| 2831 | INGPADBOUNDARY(INGPADBOUNDARY_MASK) | | 2834 | INGPADBOUNDARY_MASK | |
| 2832 | EGRSTATUSPAGESIZE_MASK, | 2835 | EGRSTATUSPAGESIZE_MASK, |
| 2833 | INGPADBOUNDARY(fl_align_log - 5) | | 2836 | INGPADBOUNDARY(fl_align_log - 5) | |
| 2834 | EGRSTATUSPAGESIZE(stat_len != 64)); | 2837 | EGRSTATUSPAGESIZE(stat_len != 64)); |
| @@ -3278,6 +3281,7 @@ int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | |||
| 3278 | { | 3281 | { |
| 3279 | struct fw_vi_enable_cmd c; | 3282 | struct fw_vi_enable_cmd c; |
| 3280 | 3283 | ||
| 3284 | memset(&c, 0, sizeof(c)); | ||
| 3281 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST | | 3285 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST | |
| 3282 | FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid)); | 3286 | FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid)); |
| 3283 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); | 3287 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); |
diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c index 1d03dcdd5e56..19ac096cb07b 100644 --- a/drivers/net/ethernet/freescale/gianfar.c +++ b/drivers/net/ethernet/freescale/gianfar.c | |||
| @@ -1353,8 +1353,11 @@ static int gfar_restore(struct device *dev) | |||
| 1353 | struct gfar_private *priv = dev_get_drvdata(dev); | 1353 | struct gfar_private *priv = dev_get_drvdata(dev); |
| 1354 | struct net_device *ndev = priv->ndev; | 1354 | struct net_device *ndev = priv->ndev; |
| 1355 | 1355 | ||
| 1356 | if (!netif_running(ndev)) | 1356 | if (!netif_running(ndev)) { |
| 1357 | netif_device_attach(ndev); | ||
| 1358 | |||
| 1357 | return 0; | 1359 | return 0; |
| 1360 | } | ||
| 1358 | 1361 | ||
| 1359 | gfar_init_bds(ndev); | 1362 | gfar_init_bds(ndev); |
| 1360 | init_registers(ndev); | 1363 | init_registers(ndev); |
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c index 56b20d17d0e4..116f0e901bee 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | |||
| @@ -2673,6 +2673,9 @@ static int ixgbe_get_ts_info(struct net_device *dev, | |||
| 2673 | case ixgbe_mac_X540: | 2673 | case ixgbe_mac_X540: |
| 2674 | case ixgbe_mac_82599EB: | 2674 | case ixgbe_mac_82599EB: |
| 2675 | info->so_timestamping = | 2675 | info->so_timestamping = |
| 2676 | SOF_TIMESTAMPING_TX_SOFTWARE | | ||
| 2677 | SOF_TIMESTAMPING_RX_SOFTWARE | | ||
| 2678 | SOF_TIMESTAMPING_SOFTWARE | | ||
| 2676 | SOF_TIMESTAMPING_TX_HARDWARE | | 2679 | SOF_TIMESTAMPING_TX_HARDWARE | |
| 2677 | SOF_TIMESTAMPING_RX_HARDWARE | | 2680 | SOF_TIMESTAMPING_RX_HARDWARE | |
| 2678 | SOF_TIMESTAMPING_RAW_HARDWARE; | 2681 | SOF_TIMESTAMPING_RAW_HARDWARE; |
diff --git a/drivers/net/ethernet/jme.c b/drivers/net/ethernet/jme.c index f8064df10cc4..92317e9c0f73 100644 --- a/drivers/net/ethernet/jme.c +++ b/drivers/net/ethernet/jme.c | |||
| @@ -1948,10 +1948,10 @@ jme_close(struct net_device *netdev) | |||
| 1948 | 1948 | ||
| 1949 | JME_NAPI_DISABLE(jme); | 1949 | JME_NAPI_DISABLE(jme); |
| 1950 | 1950 | ||
| 1951 | tasklet_disable(&jme->linkch_task); | 1951 | tasklet_kill(&jme->linkch_task); |
| 1952 | tasklet_disable(&jme->txclean_task); | 1952 | tasklet_kill(&jme->txclean_task); |
| 1953 | tasklet_disable(&jme->rxclean_task); | 1953 | tasklet_kill(&jme->rxclean_task); |
| 1954 | tasklet_disable(&jme->rxempty_task); | 1954 | tasklet_kill(&jme->rxempty_task); |
| 1955 | 1955 | ||
| 1956 | jme_disable_rx_engine(jme); | 1956 | jme_disable_rx_engine(jme); |
| 1957 | jme_disable_tx_engine(jme); | 1957 | jme_disable_tx_engine(jme); |
diff --git a/drivers/net/ethernet/marvell/skge.c b/drivers/net/ethernet/marvell/skge.c index 9b9c2ac5c4c2..d19a143aa5a8 100644 --- a/drivers/net/ethernet/marvell/skge.c +++ b/drivers/net/ethernet/marvell/skge.c | |||
| @@ -4026,7 +4026,7 @@ static void __devexit skge_remove(struct pci_dev *pdev) | |||
| 4026 | dev0 = hw->dev[0]; | 4026 | dev0 = hw->dev[0]; |
| 4027 | unregister_netdev(dev0); | 4027 | unregister_netdev(dev0); |
| 4028 | 4028 | ||
| 4029 | tasklet_disable(&hw->phy_task); | 4029 | tasklet_kill(&hw->phy_task); |
| 4030 | 4030 | ||
| 4031 | spin_lock_irq(&hw->hw_lock); | 4031 | spin_lock_irq(&hw->hw_lock); |
| 4032 | hw->intr_mask = 0; | 4032 | hw->intr_mask = 0; |
diff --git a/drivers/net/ethernet/micrel/ksz884x.c b/drivers/net/ethernet/micrel/ksz884x.c index 318fee91c79d..e558edd1cb6c 100644 --- a/drivers/net/ethernet/micrel/ksz884x.c +++ b/drivers/net/ethernet/micrel/ksz884x.c | |||
| @@ -5407,8 +5407,8 @@ static int netdev_close(struct net_device *dev) | |||
| 5407 | /* Delay for receive task to stop scheduling itself. */ | 5407 | /* Delay for receive task to stop scheduling itself. */ |
| 5408 | msleep(2000 / HZ); | 5408 | msleep(2000 / HZ); |
| 5409 | 5409 | ||
| 5410 | tasklet_disable(&hw_priv->rx_tasklet); | 5410 | tasklet_kill(&hw_priv->rx_tasklet); |
| 5411 | tasklet_disable(&hw_priv->tx_tasklet); | 5411 | tasklet_kill(&hw_priv->tx_tasklet); |
| 5412 | free_irq(dev->irq, hw_priv->dev); | 5412 | free_irq(dev->irq, hw_priv->dev); |
| 5413 | 5413 | ||
| 5414 | transmit_cleanup(hw_priv, 0); | 5414 | transmit_cleanup(hw_priv, 0); |
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index 53743f7a2ca9..af8b4142088c 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c | |||
| @@ -1524,6 +1524,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev) | |||
| 1524 | pldat->dma_buff_base_p); | 1524 | pldat->dma_buff_base_p); |
| 1525 | free_irq(ndev->irq, ndev); | 1525 | free_irq(ndev->irq, ndev); |
| 1526 | iounmap(pldat->net_base); | 1526 | iounmap(pldat->net_base); |
| 1527 | mdiobus_unregister(pldat->mii_bus); | ||
| 1527 | mdiobus_free(pldat->mii_bus); | 1528 | mdiobus_free(pldat->mii_bus); |
| 1528 | clk_disable(pldat->clk); | 1529 | clk_disable(pldat->clk); |
| 1529 | clk_put(pldat->clk); | 1530 | clk_put(pldat->clk); |
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index e7ff886e8047..927aa33d4349 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c | |||
| @@ -3827,6 +3827,8 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) | |||
| 3827 | void __iomem *ioaddr = tp->mmio_addr; | 3827 | void __iomem *ioaddr = tp->mmio_addr; |
| 3828 | 3828 | ||
| 3829 | switch (tp->mac_version) { | 3829 | switch (tp->mac_version) { |
| 3830 | case RTL_GIGA_MAC_VER_25: | ||
| 3831 | case RTL_GIGA_MAC_VER_26: | ||
| 3830 | case RTL_GIGA_MAC_VER_29: | 3832 | case RTL_GIGA_MAC_VER_29: |
| 3831 | case RTL_GIGA_MAC_VER_30: | 3833 | case RTL_GIGA_MAC_VER_30: |
| 3832 | case RTL_GIGA_MAC_VER_32: | 3834 | case RTL_GIGA_MAC_VER_32: |
| @@ -4519,6 +4521,9 @@ static void rtl_set_rx_mode(struct net_device *dev) | |||
| 4519 | mc_filter[1] = swab32(data); | 4521 | mc_filter[1] = swab32(data); |
| 4520 | } | 4522 | } |
| 4521 | 4523 | ||
| 4524 | if (tp->mac_version == RTL_GIGA_MAC_VER_35) | ||
| 4525 | mc_filter[1] = mc_filter[0] = 0xffffffff; | ||
| 4526 | |||
| 4522 | RTL_W32(MAR0 + 4, mc_filter[1]); | 4527 | RTL_W32(MAR0 + 4, mc_filter[1]); |
| 4523 | RTL_W32(MAR0 + 0, mc_filter[0]); | 4528 | RTL_W32(MAR0 + 0, mc_filter[0]); |
| 4524 | 4529 | ||
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 0793299bd39e..1d04754a6637 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c | |||
| @@ -990,7 +990,7 @@ static int axienet_stop(struct net_device *ndev) | |||
| 990 | axienet_setoptions(ndev, lp->options & | 990 | axienet_setoptions(ndev, lp->options & |
| 991 | ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); | 991 | ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); |
| 992 | 992 | ||
| 993 | tasklet_disable(&lp->dma_err_tasklet); | 993 | tasklet_kill(&lp->dma_err_tasklet); |
| 994 | 994 | ||
| 995 | free_irq(lp->tx_irq, ndev); | 995 | free_irq(lp->tx_irq, ndev); |
| 996 | free_irq(lp->rx_irq, ndev); | 996 | free_irq(lp->rx_irq, ndev); |
diff --git a/drivers/net/phy/mdio-bitbang.c b/drivers/net/phy/mdio-bitbang.c index daec9b05d168..6428fcbbdd4b 100644 --- a/drivers/net/phy/mdio-bitbang.c +++ b/drivers/net/phy/mdio-bitbang.c | |||
| @@ -234,6 +234,7 @@ void free_mdio_bitbang(struct mii_bus *bus) | |||
| 234 | struct mdiobb_ctrl *ctrl = bus->priv; | 234 | struct mdiobb_ctrl *ctrl = bus->priv; |
| 235 | 235 | ||
| 236 | module_put(ctrl->ops->owner); | 236 | module_put(ctrl->ops->owner); |
| 237 | mdiobus_unregister(bus); | ||
| 237 | mdiobus_free(bus); | 238 | mdiobus_free(bus); |
| 238 | } | 239 | } |
| 239 | EXPORT_SYMBOL(free_mdio_bitbang); | 240 | EXPORT_SYMBOL(free_mdio_bitbang); |
diff --git a/drivers/net/usb/cdc_eem.c b/drivers/net/usb/cdc_eem.c index c81e278629ff..08d55b6bf272 100644 --- a/drivers/net/usb/cdc_eem.c +++ b/drivers/net/usb/cdc_eem.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #include <linux/usb/cdc.h> | 31 | #include <linux/usb/cdc.h> |
| 32 | #include <linux/usb/usbnet.h> | 32 | #include <linux/usb/usbnet.h> |
| 33 | #include <linux/gfp.h> | 33 | #include <linux/gfp.h> |
| 34 | #include <linux/if_vlan.h> | ||
| 34 | 35 | ||
| 35 | 36 | ||
| 36 | /* | 37 | /* |
| @@ -92,7 +93,7 @@ static int eem_bind(struct usbnet *dev, struct usb_interface *intf) | |||
| 92 | 93 | ||
| 93 | /* no jumbogram (16K) support for now */ | 94 | /* no jumbogram (16K) support for now */ |
| 94 | 95 | ||
| 95 | dev->net->hard_header_len += EEM_HEAD + ETH_FCS_LEN; | 96 | dev->net->hard_header_len += EEM_HEAD + ETH_FCS_LEN + VLAN_HLEN; |
| 96 | dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; | 97 | dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; |
| 97 | 98 | ||
| 98 | return 0; | 99 | return 0; |
diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c index 7479a5761d0d..3286166415b4 100644 --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c | |||
| @@ -1344,6 +1344,7 @@ static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev, | |||
| 1344 | } else { | 1344 | } else { |
| 1345 | u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); | 1345 | u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); |
| 1346 | skb_push(skb, 4); | 1346 | skb_push(skb, 4); |
| 1347 | cpu_to_le32s(&csum_preamble); | ||
| 1347 | memcpy(skb->data, &csum_preamble, 4); | 1348 | memcpy(skb->data, &csum_preamble, 4); |
| 1348 | } | 1349 | } |
| 1349 | } | 1350 | } |
diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c index cb04f900cc46..edb81ed06950 100644 --- a/drivers/net/usb/usbnet.c +++ b/drivers/net/usb/usbnet.c | |||
| @@ -359,10 +359,12 @@ static enum skb_state defer_bh(struct usbnet *dev, struct sk_buff *skb, | |||
| 359 | void usbnet_defer_kevent (struct usbnet *dev, int work) | 359 | void usbnet_defer_kevent (struct usbnet *dev, int work) |
| 360 | { | 360 | { |
| 361 | set_bit (work, &dev->flags); | 361 | set_bit (work, &dev->flags); |
| 362 | if (!schedule_work (&dev->kevent)) | 362 | if (!schedule_work (&dev->kevent)) { |
| 363 | netdev_err(dev->net, "kevent %d may have been dropped\n", work); | 363 | if (net_ratelimit()) |
| 364 | else | 364 | netdev_err(dev->net, "kevent %d may have been dropped\n", work); |
| 365 | } else { | ||
| 365 | netdev_dbg(dev->net, "kevent %d scheduled\n", work); | 366 | netdev_dbg(dev->net, "kevent %d scheduled\n", work); |
| 367 | } | ||
| 366 | } | 368 | } |
| 367 | EXPORT_SYMBOL_GPL(usbnet_defer_kevent); | 369 | EXPORT_SYMBOL_GPL(usbnet_defer_kevent); |
| 368 | 370 | ||
diff --git a/drivers/net/vmxnet3/vmxnet3_drv.c b/drivers/net/vmxnet3/vmxnet3_drv.c index ce9d4f2c9776..0ae1bcc6da73 100644 --- a/drivers/net/vmxnet3/vmxnet3_drv.c +++ b/drivers/net/vmxnet3/vmxnet3_drv.c | |||
| @@ -744,28 +744,43 @@ vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, | |||
| 744 | 744 | ||
| 745 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | 745 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
| 746 | const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; | 746 | const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; |
| 747 | u32 buf_size; | ||
| 747 | 748 | ||
| 748 | tbi = tq->buf_info + tq->tx_ring.next2fill; | 749 | buf_offset = 0; |
| 749 | tbi->map_type = VMXNET3_MAP_PAGE; | 750 | len = skb_frag_size(frag); |
| 750 | tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, | 751 | while (len) { |
| 751 | 0, skb_frag_size(frag), | 752 | tbi = tq->buf_info + tq->tx_ring.next2fill; |
| 752 | DMA_TO_DEVICE); | 753 | if (len < VMXNET3_MAX_TX_BUF_SIZE) { |
| 754 | buf_size = len; | ||
| 755 | dw2 |= len; | ||
| 756 | } else { | ||
| 757 | buf_size = VMXNET3_MAX_TX_BUF_SIZE; | ||
| 758 | /* spec says that for TxDesc.len, 0 == 2^14 */ | ||
| 759 | } | ||
| 760 | tbi->map_type = VMXNET3_MAP_PAGE; | ||
| 761 | tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, | ||
| 762 | buf_offset, buf_size, | ||
| 763 | DMA_TO_DEVICE); | ||
| 753 | 764 | ||
| 754 | tbi->len = skb_frag_size(frag); | 765 | tbi->len = buf_size; |
| 755 | 766 | ||
| 756 | gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; | 767 | gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; |
| 757 | BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); | 768 | BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); |
| 758 | 769 | ||
| 759 | gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); | 770 | gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); |
| 760 | gdesc->dword[2] = cpu_to_le32(dw2 | skb_frag_size(frag)); | 771 | gdesc->dword[2] = cpu_to_le32(dw2); |
| 761 | gdesc->dword[3] = 0; | 772 | gdesc->dword[3] = 0; |
| 762 | 773 | ||
| 763 | dev_dbg(&adapter->netdev->dev, | 774 | dev_dbg(&adapter->netdev->dev, |
| 764 | "txd[%u]: 0x%llu %u %u\n", | 775 | "txd[%u]: 0x%llu %u %u\n", |
| 765 | tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), | 776 | tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), |
| 766 | le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); | 777 | le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); |
| 767 | vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); | 778 | vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); |
| 768 | dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; | 779 | dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; |
| 780 | |||
| 781 | len -= buf_size; | ||
| 782 | buf_offset += buf_size; | ||
| 783 | } | ||
| 769 | } | 784 | } |
| 770 | 785 | ||
| 771 | ctx->eop_txd = gdesc; | 786 | ctx->eop_txd = gdesc; |
| @@ -886,6 +901,18 @@ vmxnet3_prepare_tso(struct sk_buff *skb, | |||
| 886 | } | 901 | } |
| 887 | } | 902 | } |
| 888 | 903 | ||
| 904 | static int txd_estimate(const struct sk_buff *skb) | ||
| 905 | { | ||
| 906 | int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; | ||
| 907 | int i; | ||
| 908 | |||
| 909 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | ||
| 910 | const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; | ||
| 911 | |||
| 912 | count += VMXNET3_TXD_NEEDED(skb_frag_size(frag)); | ||
| 913 | } | ||
| 914 | return count; | ||
| 915 | } | ||
| 889 | 916 | ||
| 890 | /* | 917 | /* |
| 891 | * Transmits a pkt thru a given tq | 918 | * Transmits a pkt thru a given tq |
| @@ -914,9 +941,7 @@ vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, | |||
| 914 | union Vmxnet3_GenericDesc tempTxDesc; | 941 | union Vmxnet3_GenericDesc tempTxDesc; |
| 915 | #endif | 942 | #endif |
| 916 | 943 | ||
| 917 | /* conservatively estimate # of descriptors to use */ | 944 | count = txd_estimate(skb); |
| 918 | count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + | ||
| 919 | skb_shinfo(skb)->nr_frags + 1; | ||
| 920 | 945 | ||
| 921 | ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); | 946 | ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); |
| 922 | 947 | ||
diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c index 607976c00162..7b4adde93c01 100644 --- a/drivers/net/vxlan.c +++ b/drivers/net/vxlan.c | |||
| @@ -816,7 +816,7 @@ static void vxlan_cleanup(unsigned long arg) | |||
| 816 | = container_of(p, struct vxlan_fdb, hlist); | 816 | = container_of(p, struct vxlan_fdb, hlist); |
| 817 | unsigned long timeout; | 817 | unsigned long timeout; |
| 818 | 818 | ||
| 819 | if (f->state == NUD_PERMANENT) | 819 | if (f->state & NUD_PERMANENT) |
| 820 | continue; | 820 | continue; |
| 821 | 821 | ||
| 822 | timeout = f->used + vxlan->age_interval * HZ; | 822 | timeout = f->used + vxlan->age_interval * HZ; |
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c index 378bd70256b2..741918a2027b 100644 --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c | |||
| @@ -312,6 +312,7 @@ static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) | |||
| 312 | } | 312 | } |
| 313 | 313 | ||
| 314 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | 314 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
| 315 | bf->bf_next = NULL; | ||
| 315 | list_del(&bf->list); | 316 | list_del(&bf->list); |
| 316 | 317 | ||
| 317 | spin_unlock_bh(&sc->tx.txbuflock); | 318 | spin_unlock_bh(&sc->tx.txbuflock); |
| @@ -393,7 +394,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 393 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; | 394 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; |
| 394 | u32 ba[WME_BA_BMP_SIZE >> 5]; | 395 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
| 395 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; | 396 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
| 396 | bool rc_update = true; | 397 | bool rc_update = true, isba; |
| 397 | struct ieee80211_tx_rate rates[4]; | 398 | struct ieee80211_tx_rate rates[4]; |
| 398 | struct ath_frame_info *fi; | 399 | struct ath_frame_info *fi; |
| 399 | int nframes; | 400 | int nframes; |
| @@ -437,13 +438,17 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |||
| 437 | tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; | 438 | tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; |
| 438 | tid = ATH_AN_2_TID(an, tidno); | 439 | tid = ATH_AN_2_TID(an, tidno); |
| 439 | seq_first = tid->seq_start; | 440 | seq_first = tid->seq_start; |
| 441 | isba = ts->ts_flags & ATH9K_TX_BA; | ||
| 440 | 442 | ||
| 441 | /* | 443 | /* |
| 442 | * The hardware occasionally sends a tx status for the wrong TID. | 444 | * The hardware occasionally sends a tx status for the wrong TID. |
| 443 | * In this case, the BA status cannot be considered valid and all | 445 | * In this case, the BA status cannot be considered valid and all |
| 444 | * subframes need to be retransmitted | 446 | * subframes need to be retransmitted |
| 447 | * | ||
| 448 | * Only BlockAcks have a TID and therefore normal Acks cannot be | ||
| 449 | * checked | ||
| 445 | */ | 450 | */ |
| 446 | if (tidno != ts->tid) | 451 | if (isba && tidno != ts->tid) |
| 447 | txok = false; | 452 | txok = false; |
| 448 | 453 | ||
| 449 | isaggr = bf_isaggr(bf); | 454 | isaggr = bf_isaggr(bf); |
| @@ -1774,6 +1779,7 @@ static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, | |||
| 1774 | list_add_tail(&bf->list, &bf_head); | 1779 | list_add_tail(&bf->list, &bf_head); |
| 1775 | bf->bf_state.bf_type = 0; | 1780 | bf->bf_state.bf_type = 0; |
| 1776 | 1781 | ||
| 1782 | bf->bf_next = NULL; | ||
| 1777 | bf->bf_lastbf = bf; | 1783 | bf->bf_lastbf = bf; |
| 1778 | ath_tx_fill_desc(sc, bf, txq, fi->framelen); | 1784 | ath_tx_fill_desc(sc, bf, txq, fi->framelen); |
| 1779 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); | 1785 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); |
diff --git a/drivers/net/wireless/b43legacy/pio.c b/drivers/net/wireless/b43legacy/pio.c index 192251adf986..282eedec675e 100644 --- a/drivers/net/wireless/b43legacy/pio.c +++ b/drivers/net/wireless/b43legacy/pio.c | |||
| @@ -382,7 +382,7 @@ static void cancel_transfers(struct b43legacy_pioqueue *queue) | |||
| 382 | { | 382 | { |
| 383 | struct b43legacy_pio_txpacket *packet, *tmp_packet; | 383 | struct b43legacy_pio_txpacket *packet, *tmp_packet; |
| 384 | 384 | ||
| 385 | tasklet_disable(&queue->txtask); | 385 | tasklet_kill(&queue->txtask); |
| 386 | 386 | ||
| 387 | list_for_each_entry_safe(packet, tmp_packet, &queue->txrunning, list) | 387 | list_for_each_entry_safe(packet, tmp_packet, &queue->txrunning, list) |
| 388 | free_txpacket(packet, 0); | 388 | free_txpacket(packet, 0); |
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c index 01dc8891070c..59474ae0aec0 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/rt2x00/rt2800lib.c | |||
| @@ -2449,7 +2449,7 @@ static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) | |||
| 2449 | /* | 2449 | /* |
| 2450 | * Check if temperature compensation is supported. | 2450 | * Check if temperature compensation is supported. |
| 2451 | */ | 2451 | */ |
| 2452 | if (tssi_bounds[4] == 0xff) | 2452 | if (tssi_bounds[4] == 0xff || step == 0xff) |
| 2453 | return 0; | 2453 | return 0; |
| 2454 | 2454 | ||
| 2455 | /* | 2455 | /* |
