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-rw-r--r--drivers/net/tg3.c46
-rw-r--r--drivers/net/tg3.h4
2 files changed, 12 insertions, 38 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 7841a8f69998..b944cc64a409 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -8227,8 +8227,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8227 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { 8227 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8228 val = tr32(TG3_RDMA_RSRVCTRL_REG); 8228 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { 8229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8230 val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK; 8230 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8231 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B; 8231 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8232 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8233 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8234 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8235 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8232 } 8236 }
8233 tw32(TG3_RDMA_RSRVCTRL_REG, 8237 tw32(TG3_RDMA_RSRVCTRL_REG,
8234 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 8238 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
@@ -13394,42 +13398,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13394 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 13398 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13395 13399
13396 tp->pcie_readrq = 4096; 13400 tp->pcie_readrq = 4096;
13397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { 13401 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13398 u16 word; 13402 tp->pcie_readrq = 2048;
13399
13400 pci_read_config_word(tp->pdev,
13401 tp->pcie_cap + PCI_EXP_LNKSTA,
13402 &word);
13403 switch (word & PCI_EXP_LNKSTA_CLS) {
13404 case PCI_EXP_LNKSTA_CLS_2_5GB:
13405 word &= PCI_EXP_LNKSTA_NLW;
13406 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13407 switch (word) {
13408 case 2:
13409 tp->pcie_readrq = 2048;
13410 break;
13411 case 4:
13412 tp->pcie_readrq = 1024;
13413 break;
13414 }
13415 break;
13416
13417 case PCI_EXP_LNKSTA_CLS_5_0GB:
13418 word &= PCI_EXP_LNKSTA_NLW;
13419 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13420 switch (word) {
13421 case 1:
13422 tp->pcie_readrq = 2048;
13423 break;
13424 case 2:
13425 tp->pcie_readrq = 1024;
13426 break;
13427 case 4:
13428 tp->pcie_readrq = 512;
13429 break;
13430 }
13431 }
13432 }
13433 13403
13434 pcie_set_readrq(tp->pdev, tp->pcie_readrq); 13404 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13435 13405
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index d62c8d937c82..0a0987aeb32e 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1333,6 +1333,10 @@
1333 1333
1334#define TG3_RDMA_RSRVCTRL_REG 0x00004900 1334#define TG3_RDMA_RSRVCTRL_REG 0x00004900
1335#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1335#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1336#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1337#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1338#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1339#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1336#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1340#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1337#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 1341#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1338/* 0x4904 --> 0x4910 unused */ 1342/* 0x4904 --> 0x4910 unused */