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-rw-r--r--drivers/net/wireless/rtlwifi/Kconfig13
-rw-r--r--drivers/net/wireless/rtlwifi/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/debug.h1
-rw-r--r--drivers/net/wireless/rtlwifi/pwrseqcmd.h94
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/Makefile19
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/def.h450
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/dm.c3019
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/dm.h356
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/fw.c1889
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/fw.h351
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/hw.c4222
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/hw.h70
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/led.c237
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/led.h37
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/phy.c4855
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/phy.h259
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.c182
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.h738
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/reg.h2464
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/rf.c465
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/rf.h43
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/sw.c484
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/sw.h34
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/table.c4572
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/table.h60
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/trx.c1243
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/trx.h620
-rw-r--r--drivers/net/wireless/rtlwifi/wifi.h93
28 files changed, 26865 insertions, 6 deletions
diff --git a/drivers/net/wireless/rtlwifi/Kconfig b/drivers/net/wireless/rtlwifi/Kconfig
index bf3cf124e4ea..e88bc7348a33 100644
--- a/drivers/net/wireless/rtlwifi/Kconfig
+++ b/drivers/net/wireless/rtlwifi/Kconfig
@@ -5,7 +5,7 @@ menuconfig RTL_CARDS
5 ---help--- 5 ---help---
6 This option will enable support for the Realtek mac80211-based 6 This option will enable support for the Realtek mac80211-based
7 wireless drivers. Drivers rtl8192ce, rtl8192cu, rtl8192se, rtl8192de, 7 wireless drivers. Drivers rtl8192ce, rtl8192cu, rtl8192se, rtl8192de,
8 rtl8723ae, rtl8723be, and rtl8188ae share some common code. 8 rtl8723ae, rtl8723be, rtl8188ee, and rtl8821ae share some common code.
9 9
10if RTL_CARDS 10if RTL_CARDS
11 11
@@ -80,6 +80,17 @@ config RTL8188EE
80 80
81 If you choose to build it as a module, it will be called rtl8188ee 81 If you choose to build it as a module, it will be called rtl8188ee
82 82
83config RTL8821AE
84 tristate "Realtek RTL8821AE/RTL8812AE Wireless Network Adapter"
85 depends on PCI
86 select RTLWIFI
87 select RTLWIFI_PCI
88 ---help---
89 This is the driver for Realtek RTL8i821AE/RTL8812AE 802.11av PCIe
90 wireless network adapters.
91
92 If you choose to build it as a module, it will be called rtl8821ae
93
83config RTL8192CU 94config RTL8192CU
84 tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter" 95 tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter"
85 depends on USB 96 depends on USB
diff --git a/drivers/net/wireless/rtlwifi/Makefile b/drivers/net/wireless/rtlwifi/Makefile
index bba36a06abcc..9bfa9d53b826 100644
--- a/drivers/net/wireless/rtlwifi/Makefile
+++ b/drivers/net/wireless/rtlwifi/Makefile
@@ -28,5 +28,6 @@ obj-$(CONFIG_RTL8723BE) += rtl8723be/
28obj-$(CONFIG_RTL8188EE) += rtl8188ee/ 28obj-$(CONFIG_RTL8188EE) += rtl8188ee/
29obj-$(CONFIG_RTLBTCOEXIST) += btcoexist/ 29obj-$(CONFIG_RTLBTCOEXIST) += btcoexist/
30obj-$(CONFIG_RTL8723_COMMON) += rtl8723com/ 30obj-$(CONFIG_RTL8723_COMMON) += rtl8723com/
31obj-$(CONFIG_RTL8821AE) += rtl8821ae/
31 32
32ccflags-y += -D__CHECK_ENDIAN__ 33ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/debug.h b/drivers/net/wireless/rtlwifi/debug.h
index 534c224440e1..fc794b3e9f4a 100644
--- a/drivers/net/wireless/rtlwifi/debug.h
+++ b/drivers/net/wireless/rtlwifi/debug.h
@@ -104,6 +104,7 @@
104#define COMP_USB BIT(29) 104#define COMP_USB BIT(29)
105#define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */ 105#define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */
106#define COMP_BT_COEXIST BIT(30) 106#define COMP_BT_COEXIST BIT(30)
107#define COMP_IQK BIT(31)
107 108
108/*-------------------------------------------------------------- 109/*--------------------------------------------------------------
109 Define the rt_print components 110 Define the rt_print components
diff --git a/drivers/net/wireless/rtlwifi/pwrseqcmd.h b/drivers/net/wireless/rtlwifi/pwrseqcmd.h
new file mode 100644
index 000000000000..17ce0cb2c35c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/pwrseqcmd.h
@@ -0,0 +1,94 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8723E_PWRSEQCMD_H__
27#define __RTL8723E_PWRSEQCMD_H__
28
29#include "wifi.h"
30/*---------------------------------------------
31 * 3 The value of cmd: 4 bits
32 *---------------------------------------------
33 */
34#define PWR_CMD_READ 0x00
35#define PWR_CMD_WRITE 0x01
36#define PWR_CMD_POLLING 0x02
37#define PWR_CMD_DELAY 0x03
38#define PWR_CMD_END 0x04
39
40/* define the base address of each block */
41#define PWR_BASEADDR_MAC 0x00
42#define PWR_BASEADDR_USB 0x01
43#define PWR_BASEADDR_PCIE 0x02
44#define PWR_BASEADDR_SDIO 0x03
45
46#define PWR_INTF_SDIO_MSK BIT(0)
47#define PWR_INTF_USB_MSK BIT(1)
48#define PWR_INTF_PCI_MSK BIT(2)
49#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
50
51#define PWR_FAB_TSMC_MSK BIT(0)
52#define PWR_FAB_UMC_MSK BIT(1)
53#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
54
55#define PWR_CUT_TESTCHIP_MSK BIT(0)
56#define PWR_CUT_A_MSK BIT(1)
57#define PWR_CUT_B_MSK BIT(2)
58#define PWR_CUT_C_MSK BIT(3)
59#define PWR_CUT_D_MSK BIT(4)
60#define PWR_CUT_E_MSK BIT(5)
61#define PWR_CUT_F_MSK BIT(6)
62#define PWR_CUT_G_MSK BIT(7)
63#define PWR_CUT_ALL_MSK 0xFF
64
65enum pwrseq_delay_unit {
66 PWRSEQ_DELAY_US,
67 PWRSEQ_DELAY_MS,
68};
69
70struct wlan_pwr_cfg {
71 u16 offset;
72 u8 cut_msk;
73 u8 fab_msk:4;
74 u8 interface_msk:4;
75 u8 base:4;
76 u8 cmd:4;
77 u8 msk;
78 u8 value;
79};
80
81#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
82#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
83#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
84#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
85#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
86#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
87#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
88#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
89
90bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
91 u8 fab_version, u8 interface_type,
92 struct wlan_pwr_cfg pwrcfgcmd[]);
93
94#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/Makefile b/drivers/net/wireless/rtlwifi/rtl8821ae/Makefile
new file mode 100644
index 000000000000..87ad604a1eb3
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/Makefile
@@ -0,0 +1,19 @@
1obj-m := rtl8821ae.o
2
3
4rtl8821ae-objs := \
5 dm.o \
6 fw.o \
7 hw.o \
8 led.o \
9 phy.o \
10 pwrseq.o \
11 rf.o \
12 sw.o \
13 table.o \
14 trx.o \
15
16
17obj-$(CONFIG_RTL8821AE) += rtl8821ae.o
18
19ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/def.h b/drivers/net/wireless/rtlwifi/rtl8821ae/def.h
new file mode 100644
index 000000000000..a730985ae81d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/def.h
@@ -0,0 +1,450 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_DEF_H__
27#define __RTL8821AE_DEF_H__
28
29/*--------------------------Define -------------------------------------------*/
30#define USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN 1
31
32/* BIT 7 HT Rate*/
33/*TxHT = 0*/
34#define MGN_1M 0x02
35#define MGN_2M 0x04
36#define MGN_5_5M 0x0b
37#define MGN_11M 0x16
38
39#define MGN_6M 0x0c
40#define MGN_9M 0x12
41#define MGN_12M 0x18
42#define MGN_18M 0x24
43#define MGN_24M 0x30
44#define MGN_36M 0x48
45#define MGN_48M 0x60
46#define MGN_54M 0x6c
47
48/* TxHT = 1 */
49#define MGN_MCS0 0x80
50#define MGN_MCS1 0x81
51#define MGN_MCS2 0x82
52#define MGN_MCS3 0x83
53#define MGN_MCS4 0x84
54#define MGN_MCS5 0x85
55#define MGN_MCS6 0x86
56#define MGN_MCS7 0x87
57#define MGN_MCS8 0x88
58#define MGN_MCS9 0x89
59#define MGN_MCS10 0x8a
60#define MGN_MCS11 0x8b
61#define MGN_MCS12 0x8c
62#define MGN_MCS13 0x8d
63#define MGN_MCS14 0x8e
64#define MGN_MCS15 0x8f
65/* VHT rate */
66#define MGN_VHT1SS_MCS0 0x90
67#define MGN_VHT1SS_MCS1 0x91
68#define MGN_VHT1SS_MCS2 0x92
69#define MGN_VHT1SS_MCS3 0x93
70#define MGN_VHT1SS_MCS4 0x94
71#define MGN_VHT1SS_MCS5 0x95
72#define MGN_VHT1SS_MCS6 0x96
73#define MGN_VHT1SS_MCS7 0x97
74#define MGN_VHT1SS_MCS8 0x98
75#define MGN_VHT1SS_MCS9 0x99
76#define MGN_VHT2SS_MCS0 0x9a
77#define MGN_VHT2SS_MCS1 0x9b
78#define MGN_VHT2SS_MCS2 0x9c
79#define MGN_VHT2SS_MCS3 0x9d
80#define MGN_VHT2SS_MCS4 0x9e
81#define MGN_VHT2SS_MCS5 0x9f
82#define MGN_VHT2SS_MCS6 0xa0
83#define MGN_VHT2SS_MCS7 0xa1
84#define MGN_VHT2SS_MCS8 0xa2
85#define MGN_VHT2SS_MCS9 0xa3
86
87#define MGN_VHT3SS_MCS0 0xa4
88#define MGN_VHT3SS_MCS1 0xa5
89#define MGN_VHT3SS_MCS2 0xa6
90#define MGN_VHT3SS_MCS3 0xa7
91#define MGN_VHT3SS_MCS4 0xa8
92#define MGN_VHT3SS_MCS5 0xa9
93#define MGN_VHT3SS_MCS6 0xaa
94#define MGN_VHT3SS_MCS7 0xab
95#define MGN_VHT3SS_MCS8 0xac
96#define MGN_VHT3SS_MCS9 0xad
97
98#define MGN_MCS0_SG 0xc0
99#define MGN_MCS1_SG 0xc1
100#define MGN_MCS2_SG 0xc2
101#define MGN_MCS3_SG 0xc3
102#define MGN_MCS4_SG 0xc4
103#define MGN_MCS5_SG 0xc5
104#define MGN_MCS6_SG 0xc6
105#define MGN_MCS7_SG 0xc7
106#define MGN_MCS8_SG 0xc8
107#define MGN_MCS9_SG 0xc9
108#define MGN_MCS10_SG 0xca
109#define MGN_MCS11_SG 0xcb
110#define MGN_MCS12_SG 0xcc
111#define MGN_MCS13_SG 0xcd
112#define MGN_MCS14_SG 0xce
113#define MGN_MCS15_SG 0xcf
114
115#define MGN_UNKNOWN 0xff
116
117/* 30 ms */
118#define WIFI_NAV_UPPER_US 30000
119#define HAL_92C_NAV_UPPER_UNIT 128
120
121#define HAL_RETRY_LIMIT_INFRA 48
122#define HAL_RETRY_LIMIT_AP_ADHOC 7
123
124#define RESET_DELAY_8185 20
125
126#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
127#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
128
129#define NUM_OF_FIRMWARE_QUEUE 10
130#define NUM_OF_PAGES_IN_FW 0x100
131#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
132#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
133#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
134#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
135#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
136#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
137#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
138#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
139#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
140#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
141
142#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
143#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
144#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
145#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
146#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
147
148#define MAX_RX_DMA_BUFFER_SIZE 0x3E80
149
150#define MAX_LINES_HWCONFIG_TXT 1000
151#define MAX_BYTES_LINE_HWCONFIG_TXT 256
152
153#define SW_THREE_WIRE 0
154#define HW_THREE_WIRE 2
155
156#define BT_DEMO_BOARD 0
157#define BT_QA_BOARD 1
158#define BT_FPGA 2
159
160#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
161#define HAL_PRIME_CHNL_OFFSET_LOWER 1
162#define HAL_PRIME_CHNL_OFFSET_UPPER 2
163
164#define MAX_H2C_QUEUE_NUM 10
165
166#define RX_MPDU_QUEUE 0
167#define RX_CMD_QUEUE 1
168#define RX_MAX_QUEUE 2
169#define AC2QUEUEID(_AC) (_AC)
170
171#define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80
172
173#define C2H_RX_CMD_HDR_LEN 8
174#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
175 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
176#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
177 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
178#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
179 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
180#define GET_C2H_CMD_CONTINUE(__prxhdr) \
181 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
182#define GET_C2H_CMD_CONTENT(__prxhdr) \
183 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
184
185#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
186 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
187#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
188 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
189#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
190 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
191#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
192 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
193#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
194 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
195#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
196 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
197#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
198 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
199#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
200 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
201#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
202 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
203
204#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
205
206#define CHIP_8812 BIT(2)
207#define CHIP_8821 (BIT(0)|BIT(2))
208
209#define CHIP_8821A (BIT(0)|BIT(2))
210#define NORMAL_CHIP BIT(3)
211#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
212#define RF_TYPE_1T2R BIT(4)
213#define RF_TYPE_2T2R BIT(5)
214#define CHIP_VENDOR_UMC BIT(7)
215#define B_CUT_VERSION BIT(12)
216#define C_CUT_VERSION BIT(13)
217#define D_CUT_VERSION ((BIT(12)|BIT(13)))
218#define E_CUT_VERSION BIT(14)
219#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
220
221enum version_8821ae {
222 VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
223 VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
224 VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
225 VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
226 VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
227 VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
228 VERSION_TEST_CHIP_8821 = 0x0005,
229 VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
230 VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
231 VERSION_UNKNOWN = 0xFF,
232};
233
234enum vht_data_sc {
235 VHT_DATA_SC_DONOT_CARE = 0,
236 VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
237 VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
238 VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
239 VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
240 VHT_DATA_SC_20_RECV1 = 5,
241 VHT_DATA_SC_20_RECV2 = 6,
242 VHT_DATA_SC_20_RECV3 = 7,
243 VHT_DATA_SC_20_RECV4 = 8,
244 VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
245 VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
246};
247
248/* MASK */
249#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
250#define CHIP_TYPE_MASK BIT(3)
251#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
252#define MANUFACTUER_MASK BIT(7)
253#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
254#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
255
256/* Get element */
257#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
258#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
259#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
260#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
261#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
262#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
263
264#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
265#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
266 ? true : false)
267#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
268 ? true : false)
269
270#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
271 true : false)
272#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
273 true : false)
274
275#define IS_VENDOR_8812A_TEST_CHIP(version) ((IS_8812_SERIES(version)) ? \
276 ((IS_NORMAL_CHIP(version)) ? \
277 false : true) : false)
278#define IS_VENDOR_8812A_MP_CHIP(version) ((IS_8812_SERIES(version)) ? \
279 ((IS_NORMAL_CHIP(version)) ? \
280 true : false) : false)
281#define IS_VENDOR_8812A_C_CUT(version) ((IS_8812_SERIES(version)) ? \
282 ((GET_CVID_CUT_VERSION(version) == \
283 C_CUT_VERSION) ? \
284 true : false) : false)
285
286#define IS_VENDOR_8821A_TEST_CHIP(version) ((IS_8821_SERIES(version)) ? \
287 ((IS_NORMAL_CHIP(version)) ? \
288 false : true) : false)
289#define IS_VENDOR_8821A_MP_CHIP(version) ((IS_8821_SERIES(version)) ? \
290 ((IS_NORMAL_CHIP(version)) ? \
291 true : false) : false)
292#define IS_VENDOR_8821A_B_CUT(version) ((IS_8821_SERIES(version)) ? \
293 ((GET_CVID_CUT_VERSION(version) == \
294 B_CUT_VERSION) ? \
295 true : false) : false)
296enum board_type {
297 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
298 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */
299 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
300 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
301 ODM_BOARD_EXT_PA = BIT(3), /* 1 = existing 2G ext-PA */
302 ODM_BOARD_EXT_LNA = BIT(4), /* 1 = existing 2G ext-LNA */
303 ODM_BOARD_EXT_TRSW = BIT(5), /* 1 = existing ext-TRSW */
304 ODM_BOARD_EXT_PA_5G = BIT(6), /* 1 = existing 5G ext-PA */
305 ODM_BOARD_EXT_LNA_5G = BIT(7), /* 1 = existing 5G ext-LNA */
306};
307
308enum rf_optype {
309 RF_OP_BY_SW_3WIRE = 0,
310 RF_OP_BY_FW,
311 RF_OP_MAX
312};
313
314enum rf_power_state {
315 RF_ON,
316 RF_OFF,
317 RF_SLEEP,
318 RF_SHUT_DOWN,
319};
320
321enum power_save_mode {
322 POWER_SAVE_MODE_ACTIVE,
323 POWER_SAVE_MODE_SAVE,
324};
325
326enum power_polocy_config {
327 POWERCFG_MAX_POWER_SAVINGS,
328 POWERCFG_GLOBAL_POWER_SAVINGS,
329 POWERCFG_LOCAL_POWER_SAVINGS,
330 POWERCFG_LENOVO,
331};
332
333enum interface_select_pci {
334 INTF_SEL1_MINICARD = 0,
335 INTF_SEL0_PCIE = 1,
336 INTF_SEL2_RSV = 2,
337 INTF_SEL3_RSV = 3,
338};
339
340enum hal_fw_c2h_cmd_id {
341 HAL_FW_C2H_CMD_READ_MACREG = 0,
342 HAL_FW_C2H_CMD_READ_BBREG = 1,
343 HAL_FW_C2H_CMD_READ_RFREG = 2,
344 HAL_FW_C2H_CMD_READ_EEPROM = 3,
345 HAL_FW_C2H_CMD_READ_EFUSE = 4,
346 HAL_FW_C2H_CMD_READ_CAM = 5,
347 HAL_FW_C2H_CMD_GET_BASICRATE = 6,
348 HAL_FW_C2H_CMD_GET_DATARATE = 7,
349 HAL_FW_C2H_CMD_SURVEY = 8,
350 HAL_FW_C2H_CMD_SURVEYDONE = 9,
351 HAL_FW_C2H_CMD_JOINBSS = 10,
352 HAL_FW_C2H_CMD_ADDSTA = 11,
353 HAL_FW_C2H_CMD_DELSTA = 12,
354 HAL_FW_C2H_CMD_ATIMDONE = 13,
355 HAL_FW_C2H_CMD_TX_REPORT = 14,
356 HAL_FW_C2H_CMD_CCX_REPORT = 15,
357 HAL_FW_C2H_CMD_DTM_REPORT = 16,
358 HAL_FW_C2H_CMD_TX_RATE_STATISTICS = 17,
359 HAL_FW_C2H_CMD_C2HLBK = 18,
360 HAL_FW_C2H_CMD_C2HDBG = 19,
361 HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
362 HAL_FW_C2H_CMD_MAX
363};
364
365enum rtl_desc_qsel {
366 QSLT_BK = 0x2,
367 QSLT_BE = 0x0,
368 QSLT_VI = 0x5,
369 QSLT_VO = 0x7,
370 QSLT_BEACON = 0x10,
371 QSLT_HIGH = 0x11,
372 QSLT_MGNT = 0x12,
373 QSLT_CMD = 0x13,
374};
375
376enum rtl_desc8821ae_rate {
377 DESC_RATE1M = 0x00,
378 DESC_RATE2M = 0x01,
379 DESC_RATE5_5M = 0x02,
380 DESC_RATE11M = 0x03,
381
382 DESC_RATE6M = 0x04,
383 DESC_RATE9M = 0x05,
384 DESC_RATE12M = 0x06,
385 DESC_RATE18M = 0x07,
386 DESC_RATE24M = 0x08,
387 DESC_RATE36M = 0x09,
388 DESC_RATE48M = 0x0a,
389 DESC_RATE54M = 0x0b,
390
391 DESC_RATEMCS0 = 0x0c,
392 DESC_RATEMCS1 = 0x0d,
393 DESC_RATEMCS2 = 0x0e,
394 DESC_RATEMCS3 = 0x0f,
395 DESC_RATEMCS4 = 0x10,
396 DESC_RATEMCS5 = 0x11,
397 DESC_RATEMCS6 = 0x12,
398 DESC_RATEMCS7 = 0x13,
399 DESC_RATEMCS8 = 0x14,
400 DESC_RATEMCS9 = 0x15,
401 DESC_RATEMCS10 = 0x16,
402 DESC_RATEMCS11 = 0x17,
403 DESC_RATEMCS12 = 0x18,
404 DESC_RATEMCS13 = 0x19,
405 DESC_RATEMCS14 = 0x1a,
406 DESC_RATEMCS15 = 0x1b,
407
408 DESC_RATEVHT1SS_MCS0 = 0x2c,
409 DESC_RATEVHT1SS_MCS1 = 0x2d,
410 DESC_RATEVHT1SS_MCS2 = 0x2e,
411 DESC_RATEVHT1SS_MCS3 = 0x2f,
412 DESC_RATEVHT1SS_MCS4 = 0x30,
413 DESC_RATEVHT1SS_MCS5 = 0x31,
414 DESC_RATEVHT1SS_MCS6 = 0x32,
415 DESC_RATEVHT1SS_MCS7 = 0x33,
416 DESC_RATEVHT1SS_MCS8 = 0x34,
417 DESC_RATEVHT1SS_MCS9 = 0x35,
418 DESC_RATEVHT2SS_MCS0 = 0x36,
419 DESC_RATEVHT2SS_MCS1 = 0x37,
420 DESC_RATEVHT2SS_MCS2 = 0x38,
421 DESC_RATEVHT2SS_MCS3 = 0x39,
422 DESC_RATEVHT2SS_MCS4 = 0x3a,
423 DESC_RATEVHT2SS_MCS5 = 0x3b,
424 DESC_RATEVHT2SS_MCS6 = 0x3c,
425 DESC_RATEVHT2SS_MCS7 = 0x3d,
426 DESC_RATEVHT2SS_MCS8 = 0x3e,
427 DESC_RATEVHT2SS_MCS9 = 0x3f,
428};
429
430enum rx_packet_type {
431 NORMAL_RX,
432 TX_REPORT1,
433 TX_REPORT2,
434 HIS_REPORT,
435 C2H_PACKET,
436};
437
438struct phy_sts_cck_8821ae_t {
439 u8 adc_pwdb_X[4];
440 u8 sq_rpt;
441 u8 cck_agc_rpt;
442};
443
444struct h2c_cmd_8821ae {
445 u8 element_id;
446 u32 cmd_len;
447 u8 *p_cmdbuffer;
448};
449
450#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/dm.c b/drivers/net/wireless/rtlwifi/rtl8821ae/dm.c
new file mode 100644
index 000000000000..9be106109921
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/dm.c
@@ -0,0 +1,3019 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../base.h"
28#include "../pci.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "dm.h"
33#include "fw.h"
34#include "trx.h"
35#include "../btcoexist/rtl_btc.h"
36
37static const u32 txscaling_tbl[TXSCALE_TABLE_SIZE] = {
38 0x081, /* 0, -12.0dB */
39 0x088, /* 1, -11.5dB */
40 0x090, /* 2, -11.0dB */
41 0x099, /* 3, -10.5dB */
42 0x0A2, /* 4, -10.0dB */
43 0x0AC, /* 5, -9.5dB */
44 0x0B6, /* 6, -9.0dB */
45 0x0C0, /* 7, -8.5dB */
46 0x0CC, /* 8, -8.0dB */
47 0x0D8, /* 9, -7.5dB */
48 0x0E5, /* 10, -7.0dB */
49 0x0F2, /* 11, -6.5dB */
50 0x101, /* 12, -6.0dB */
51 0x110, /* 13, -5.5dB */
52 0x120, /* 14, -5.0dB */
53 0x131, /* 15, -4.5dB */
54 0x143, /* 16, -4.0dB */
55 0x156, /* 17, -3.5dB */
56 0x16A, /* 18, -3.0dB */
57 0x180, /* 19, -2.5dB */
58 0x197, /* 20, -2.0dB */
59 0x1AF, /* 21, -1.5dB */
60 0x1C8, /* 22, -1.0dB */
61 0x1E3, /* 23, -0.5dB */
62 0x200, /* 24, +0 dB */
63 0x21E, /* 25, +0.5dB */
64 0x23E, /* 26, +1.0dB */
65 0x261, /* 27, +1.5dB */
66 0x285, /* 28, +2.0dB */
67 0x2AB, /* 29, +2.5dB */
68 0x2D3, /* 30, +3.0dB */
69 0x2FE, /* 31, +3.5dB */
70 0x32B, /* 32, +4.0dB */
71 0x35C, /* 33, +4.5dB */
72 0x38E, /* 34, +5.0dB */
73 0x3C4, /* 35, +5.5dB */
74 0x3FE /* 36, +6.0dB */
75};
76
77static const u32 rtl8821ae_txscaling_table[TXSCALE_TABLE_SIZE] = {
78 0x081, /* 0, -12.0dB */
79 0x088, /* 1, -11.5dB */
80 0x090, /* 2, -11.0dB */
81 0x099, /* 3, -10.5dB */
82 0x0A2, /* 4, -10.0dB */
83 0x0AC, /* 5, -9.5dB */
84 0x0B6, /* 6, -9.0dB */
85 0x0C0, /* 7, -8.5dB */
86 0x0CC, /* 8, -8.0dB */
87 0x0D8, /* 9, -7.5dB */
88 0x0E5, /* 10, -7.0dB */
89 0x0F2, /* 11, -6.5dB */
90 0x101, /* 12, -6.0dB */
91 0x110, /* 13, -5.5dB */
92 0x120, /* 14, -5.0dB */
93 0x131, /* 15, -4.5dB */
94 0x143, /* 16, -4.0dB */
95 0x156, /* 17, -3.5dB */
96 0x16A, /* 18, -3.0dB */
97 0x180, /* 19, -2.5dB */
98 0x197, /* 20, -2.0dB */
99 0x1AF, /* 21, -1.5dB */
100 0x1C8, /* 22, -1.0dB */
101 0x1E3, /* 23, -0.5dB */
102 0x200, /* 24, +0 dB */
103 0x21E, /* 25, +0.5dB */
104 0x23E, /* 26, +1.0dB */
105 0x261, /* 27, +1.5dB */
106 0x285, /* 28, +2.0dB */
107 0x2AB, /* 29, +2.5dB */
108 0x2D3, /* 30, +3.0dB */
109 0x2FE, /* 31, +3.5dB */
110 0x32B, /* 32, +4.0dB */
111 0x35C, /* 33, +4.5dB */
112 0x38E, /* 34, +5.0dB */
113 0x3C4, /* 35, +5.5dB */
114 0x3FE /* 36, +6.0dB */
115};
116
117static const u32 ofdmswing_table[] = {
118 0x0b40002d, /* 0, -15.0dB */
119 0x0c000030, /* 1, -14.5dB */
120 0x0cc00033, /* 2, -14.0dB */
121 0x0d800036, /* 3, -13.5dB */
122 0x0e400039, /* 4, -13.0dB */
123 0x0f00003c, /* 5, -12.5dB */
124 0x10000040, /* 6, -12.0dB */
125 0x11000044, /* 7, -11.5dB */
126 0x12000048, /* 8, -11.0dB */
127 0x1300004c, /* 9, -10.5dB */
128 0x14400051, /* 10, -10.0dB */
129 0x15800056, /* 11, -9.5dB */
130 0x16c0005b, /* 12, -9.0dB */
131 0x18000060, /* 13, -8.5dB */
132 0x19800066, /* 14, -8.0dB */
133 0x1b00006c, /* 15, -7.5dB */
134 0x1c800072, /* 16, -7.0dB */
135 0x1e400079, /* 17, -6.5dB */
136 0x20000080, /* 18, -6.0dB */
137 0x22000088, /* 19, -5.5dB */
138 0x24000090, /* 20, -5.0dB */
139 0x26000098, /* 21, -4.5dB */
140 0x288000a2, /* 22, -4.0dB */
141 0x2ac000ab, /* 23, -3.5dB */
142 0x2d4000b5, /* 24, -3.0dB */
143 0x300000c0, /* 25, -2.5dB */
144 0x32c000cb, /* 26, -2.0dB */
145 0x35c000d7, /* 27, -1.5dB */
146 0x390000e4, /* 28, -1.0dB */
147 0x3c8000f2, /* 29, -0.5dB */
148 0x40000100, /* 30, +0dB */
149 0x43c0010f, /* 31, +0.5dB */
150 0x47c0011f, /* 32, +1.0dB */
151 0x4c000130, /* 33, +1.5dB */
152 0x50800142, /* 34, +2.0dB */
153 0x55400155, /* 35, +2.5dB */
154 0x5a400169, /* 36, +3.0dB */
155 0x5fc0017f, /* 37, +3.5dB */
156 0x65400195, /* 38, +4.0dB */
157 0x6b8001ae, /* 39, +4.5dB */
158 0x71c001c7, /* 40, +5.0dB */
159 0x788001e2, /* 41, +5.5dB */
160 0x7f8001fe /* 42, +6.0dB */
161};
162
163static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
164 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
165 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
166 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */
167 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */
168 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */
169 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */
170 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */
171 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */
172 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */
173 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */
174 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */
175 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */
176 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */
177 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */
178 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
179 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */
180 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
181 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */
182 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
183 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */
184 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */
185 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */
186 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
187 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */
188 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
189 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */
190 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */
191 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */
192 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
193 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */
194 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */
195 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */
196 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */
197};
198
199static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
200 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */
201 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */
202 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */
203 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */
204 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */
205 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */
206 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */
207 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */
208 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */
209 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */
210 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */
211 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */
212 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */
213 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */
214 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */
215 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */
216 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
217 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */
218 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
219 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
220 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
221 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */
222 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
223 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */
224 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
225 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
226 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
227 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */
228 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
229 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */
230 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
231 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
232 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
233};
234
235static const u32 edca_setting_dl[PEER_MAX] = {
236 0xa44f, /* 0 UNKNOWN */
237 0x5ea44f, /* 1 REALTEK_90 */
238 0x5e4322, /* 2 REALTEK_92SE */
239 0x5ea42b, /* 3 BROAD */
240 0xa44f, /* 4 RAL */
241 0xa630, /* 5 ATH */
242 0x5ea630, /* 6 CISCO */
243 0x5ea42b, /* 7 MARVELL */
244};
245
246static const u32 edca_setting_ul[PEER_MAX] = {
247 0x5e4322, /* 0 UNKNOWN */
248 0xa44f, /* 1 REALTEK_90 */
249 0x5ea44f, /* 2 REALTEK_92SE */
250 0x5ea32b, /* 3 BROAD */
251 0x5ea422, /* 4 RAL */
252 0x5ea322, /* 5 ATH */
253 0x3ea430, /* 6 CISCO */
254 0x5ea44f, /* 7 MARV */
255};
256
257static u8 rtl8818e_delta_swing_table_idx_24gb_p[] = {
258 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4,
259 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
260
261static u8 rtl8818e_delta_swing_table_idx_24gb_n[] = {
262 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
263 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
264
265static u8 rtl8812ae_delta_swing_table_idx_24gb_n[] = {
266 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
267 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11};
268
269static u8 rtl8812ae_delta_swing_table_idx_24gb_p[] = {
270 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6,
271 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
272
273static u8 rtl8812ae_delta_swing_table_idx_24ga_n[] = {
274 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
275 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11};
276
277static u8 rtl8812ae_delta_swing_table_idx_24ga_p[] = {
278 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6,
279 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
280
281static u8 rtl8812ae_delta_swing_table_idx_24gcckb_n[] = {
282 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
283 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11};
284
285static u8 rtl8812ae_delta_swing_table_idx_24gcckb_p[] = {
286 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6,
287 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
288
289static u8 rtl8812ae_delta_swing_table_idx_24gccka_n[] = {
290 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
291 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11};
292
293static u8 rtl8812ae_delta_swing_table_idx_24gccka_p[] = {
294 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6,
295 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
296
297static u8 rtl8812ae_delta_swing_table_idx_5gb_n[][DEL_SW_IDX_SZ] = {
298 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7,
299 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13},
300 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
301 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13},
302 {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11,
303 12, 12, 13, 14, 14, 14, 15, 16, 17, 17, 17, 18, 18, 18},
304};
305
306static u8 rtl8812ae_delta_swing_table_idx_5gb_p[][DEL_SW_IDX_SZ] = {
307 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8,
308 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11},
309 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8,
310 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11},
311 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9,
312 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
313};
314
315static u8 rtl8812ae_delta_swing_table_idx_5ga_n[][DEL_SW_IDX_SZ] = {
316 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8,
317 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13},
318 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9,
319 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13},
320 {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11,
321 12, 13, 14, 14, 15, 15, 15, 16, 16, 16, 17, 17, 18, 18},
322};
323
324static u8 rtl8812ae_delta_swing_table_idx_5ga_p[][DEL_SW_IDX_SZ] = {
325 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 8,
326 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11},
327 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8,
328 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
329 {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9,
330 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
331};
332
333static u8 rtl8821ae_delta_swing_table_idx_24gb_n[] = {
334 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6,
335 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
336
337static u8 rtl8821ae_delta_swing_table_idx_24gb_p[] = {
338 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8,
339 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
340
341static u8 rtl8821ae_delta_swing_table_idx_24ga_n[] = {
342 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6,
343 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
344
345static u8 rtl8821ae_delta_swing_table_idx_24ga_p[] = {
346 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8,
347 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
348
349static u8 rtl8821ae_delta_swing_table_idx_24gcckb_n[] = {
350 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6,
351 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
352
353static u8 rtl8821ae_delta_swing_table_idx_24gcckb_p[] = {
354 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8,
355 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
356
357static u8 rtl8821ae_delta_swing_table_idx_24gccka_n[] = {
358 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6,
359 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
360
361static u8 rtl8821ae_delta_swing_table_idx_24gccka_p[] = {
362 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8,
363 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
364
365static u8 rtl8821ae_delta_swing_table_idx_5gb_n[][DEL_SW_IDX_SZ] = {
366 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
367 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
368 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
369 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
370 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
371 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
372};
373
374static u8 rtl8821ae_delta_swing_table_idx_5gb_p[][DEL_SW_IDX_SZ] = {
375 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
376 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
377 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
378 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
379 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
380 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
381};
382
383static u8 rtl8821ae_delta_swing_table_idx_5ga_n[][DEL_SW_IDX_SZ] = {
384 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
385 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
386 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
387 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
388 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
389 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
390};
391
392static u8 rtl8821ae_delta_swing_table_idx_5ga_p[][DEL_SW_IDX_SZ] = {
393 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
394 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
395 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
396 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
397 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
398 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
399};
400
401void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
402 u8 type, u8 *pdirection,
403 u32 *poutwrite_val)
404{
405 struct rtl_priv *rtlpriv = rtl_priv(hw);
406 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
407 u8 pwr_val = 0;
408
409 if (type == 0) {
410 if (rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A] <=
411 rtlpriv->dm.swing_idx_ofdm_base[RF90_PATH_A]) {
412 *pdirection = 1;
413 pwr_val = rtldm->swing_idx_ofdm_base[RF90_PATH_A] -
414 rtldm->swing_idx_ofdm[RF90_PATH_A];
415 } else {
416 *pdirection = 2;
417 pwr_val = rtldm->swing_idx_ofdm[RF90_PATH_A] -
418 rtldm->swing_idx_ofdm_base[RF90_PATH_A];
419 }
420 } else if (type == 1) {
421 if (rtldm->swing_idx_cck <= rtldm->swing_idx_cck_base) {
422 *pdirection = 1;
423 pwr_val = rtldm->swing_idx_cck_base -
424 rtldm->swing_idx_cck;
425 } else {
426 *pdirection = 2;
427 pwr_val = rtldm->swing_idx_cck -
428 rtldm->swing_idx_cck_base;
429 }
430 }
431
432 if (pwr_val >= TXPWRTRACK_MAX_IDX && (*pdirection == 1))
433 pwr_val = TXPWRTRACK_MAX_IDX;
434
435 *poutwrite_val = pwr_val | (pwr_val << 8)|
436 (pwr_val << 16)|
437 (pwr_val << 24);
438}
439
440void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw)
441{
442 struct rtl_priv *rtlpriv = rtl_priv(hw);
443 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
444 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
445 u8 p = 0;
446
447 rtldm->swing_idx_cck_base = rtldm->default_cck_index;
448 rtldm->swing_idx_cck = rtldm->default_cck_index;
449 rtldm->cck_index = 0;
450
451 for (p = RF90_PATH_A; p <= RF90_PATH_B; ++p) {
452 rtldm->swing_idx_ofdm_base[p] = rtldm->default_ofdm_index;
453 rtldm->swing_idx_ofdm[p] = rtldm->default_ofdm_index;
454 rtldm->ofdm_index[p] = rtldm->default_ofdm_index;
455
456 rtldm->power_index_offset[p] = 0;
457 rtldm->delta_power_index[p] = 0;
458 rtldm->delta_power_index_last[p] = 0;
459 /*Initial Mix mode power tracking*/
460 rtldm->absolute_ofdm_swing_idx[p] = 0;
461 rtldm->remnant_ofdm_swing_idx[p] = 0;
462 }
463 /*Initial at Modify Tx Scaling Mode*/
464 rtldm->modify_txagc_flag_path_a = false;
465 /*Initial at Modify Tx Scaling Mode*/
466 rtldm->modify_txagc_flag_path_b = false;
467 rtldm->remnant_cck_idx = 0;
468 rtldm->thermalvalue = rtlefuse->eeprom_thermalmeter;
469 rtldm->thermalvalue_iqk = rtlefuse->eeprom_thermalmeter;
470 rtldm->thermalvalue_lck = rtlefuse->eeprom_thermalmeter;
471}
472
473static u8 rtl8821ae_dm_get_swing_index(struct ieee80211_hw *hw)
474{
475 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
476 u8 i = 0;
477 u32 bb_swing;
478
479 bb_swing = phy_get_tx_swing_8812A(hw, rtlhal->current_bandtype,
480 RF90_PATH_A);
481
482 for (i = 0; i < TXSCALE_TABLE_SIZE; ++i)
483 if (bb_swing == rtl8821ae_txscaling_table[i])
484 break;
485
486 return i;
487}
488
489void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(
490 struct ieee80211_hw *hw)
491{
492 struct rtl_priv *rtlpriv = rtl_priv(hw);
493 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
494 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
495 u8 default_swing_index = 0;
496 u8 p = 0;
497
498 rtlpriv->dm.txpower_track_control = true;
499 rtldm->thermalvalue = rtlefuse->eeprom_thermalmeter;
500 rtldm->thermalvalue_iqk = rtlefuse->eeprom_thermalmeter;
501 rtldm->thermalvalue_lck = rtlefuse->eeprom_thermalmeter;
502 default_swing_index = rtl8821ae_dm_get_swing_index(hw);
503
504 rtldm->default_ofdm_index =
505 (default_swing_index == TXSCALE_TABLE_SIZE) ?
506 24 : default_swing_index;
507 rtldm->default_cck_index = 24;
508
509 rtldm->swing_idx_cck_base = rtldm->default_cck_index;
510 rtldm->cck_index = rtldm->default_cck_index;
511
512 for (p = RF90_PATH_A; p < MAX_RF_PATH; ++p) {
513 rtldm->swing_idx_ofdm_base[p] =
514 rtldm->default_ofdm_index;
515 rtldm->ofdm_index[p] = rtldm->default_ofdm_index;
516 rtldm->delta_power_index[p] = 0;
517 rtldm->power_index_offset[p] = 0;
518 rtldm->delta_power_index_last[p] = 0;
519 }
520}
521
522static void rtl8821ae_dm_diginit(struct ieee80211_hw *hw)
523{
524 struct rtl_priv *rtlpriv = rtl_priv(hw);
525 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
526
527 dm_digtable->cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f);
528 dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
529 dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
530 dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
531 dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
532 dm_digtable->rx_gain_max = DM_DIG_MAX;
533 dm_digtable->rx_gain_min = DM_DIG_MIN;
534 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
535 dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
536 dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
537 dm_digtable->pre_cck_cca_thres = 0xff;
538 dm_digtable->cur_cck_cca_thres = 0x83;
539 dm_digtable->forbidden_igi = DM_DIG_MIN;
540 dm_digtable->large_fa_hit = 0;
541 dm_digtable->recover_cnt = 0;
542 dm_digtable->dig_dynamic_min = DM_DIG_MIN;
543 dm_digtable->dig_dynamic_min_1 = DM_DIG_MIN;
544 dm_digtable->media_connect_0 = false;
545 dm_digtable->media_connect_1 = false;
546 rtlpriv->dm.dm_initialgain_enable = true;
547 dm_digtable->bt30_cur_igi = 0x32;
548}
549
550void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw)
551{
552 struct rtl_priv *rtlpriv = rtl_priv(hw);
553
554 rtlpriv->dm.current_turbo_edca = false;
555 rtlpriv->dm.is_any_nonbepkts = false;
556 rtlpriv->dm.is_cur_rdlstate = false;
557}
558
559void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
560{
561 struct rtl_priv *rtlpriv = rtl_priv(hw);
562 struct rate_adaptive *p_ra = &rtlpriv->ra;
563
564 p_ra->ratr_state = DM_RATR_STA_INIT;
565 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
566
567 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
568 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
569 rtlpriv->dm.useramask = true;
570 else
571 rtlpriv->dm.useramask = false;
572
573 p_ra->high_rssi_thresh_for_ra = 50;
574 p_ra->low_rssi_thresh_for_ra40m = 20;
575}
576
577static void rtl8821ae_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
578{
579 struct rtl_priv *rtlpriv = rtl_priv(hw);
580
581 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
582
583 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
584 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
585}
586
587static void rtl8821ae_dm_common_info_self_init(struct ieee80211_hw *hw)
588{
589 struct rtl_priv *rtlpriv = rtl_priv(hw);
590 struct rtl_phy *rtlphy = &rtlpriv->phy;
591 u8 tmp;
592
593 rtlphy->cck_high_power =
594 (bool)rtl_get_bbreg(hw, ODM_REG_CCK_RPT_FORMAT_11AC,
595 ODM_BIT_CCK_RPT_FORMAT_11AC);
596
597 tmp = (u8)rtl_get_bbreg(hw, ODM_REG_BB_RX_PATH_11AC,
598 ODM_BIT_BB_RX_PATH_11AC);
599 if (tmp & BIT(0))
600 rtlpriv->dm.rfpath_rxenable[0] = true;
601 if (tmp & BIT(1))
602 rtlpriv->dm.rfpath_rxenable[1] = true;
603}
604
605void rtl8821ae_dm_init(struct ieee80211_hw *hw)
606{
607 struct rtl_priv *rtlpriv = rtl_priv(hw);
608 struct rtl_phy *rtlphy = &rtlpriv->phy;
609
610 spin_lock(&rtlpriv->locks.iqk_lock);
611 rtlphy->lck_inprogress = false;
612 spin_unlock(&rtlpriv->locks.iqk_lock);
613
614 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
615 rtl8821ae_dm_common_info_self_init(hw);
616 rtl8821ae_dm_diginit(hw);
617 rtl8821ae_dm_init_rate_adaptive_mask(hw);
618 rtl8821ae_dm_init_edca_turbo(hw);
619 rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(hw);
620 rtl8821ae_dm_init_dynamic_atc_switch(hw);
621}
622
623static void rtl8821ae_dm_find_minimum_rssi(struct ieee80211_hw *hw)
624{
625 struct rtl_priv *rtlpriv = rtl_priv(hw);
626 struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
627 struct rtl_mac *mac = rtl_mac(rtlpriv);
628
629 /* Determine the minimum RSSI */
630 if ((mac->link_state < MAC80211_LINKED) &&
631 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
632 rtl_dm_dig->min_undec_pwdb_for_dm = 0;
633 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
634 "Not connected to any\n");
635 }
636 if (mac->link_state >= MAC80211_LINKED) {
637 if (mac->opmode == NL80211_IFTYPE_AP ||
638 mac->opmode == NL80211_IFTYPE_ADHOC) {
639 rtl_dm_dig->min_undec_pwdb_for_dm =
640 rtlpriv->dm.entry_min_undec_sm_pwdb;
641 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
642 "AP Client PWDB = 0x%lx\n",
643 rtlpriv->dm.entry_min_undec_sm_pwdb);
644 } else {
645 rtl_dm_dig->min_undec_pwdb_for_dm =
646 rtlpriv->dm.undec_sm_pwdb;
647 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
648 "STA Default Port PWDB = 0x%x\n",
649 rtl_dm_dig->min_undec_pwdb_for_dm);
650 }
651 } else {
652 rtl_dm_dig->min_undec_pwdb_for_dm =
653 rtlpriv->dm.entry_min_undec_sm_pwdb;
654 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
655 "AP Ext Port or disconnet PWDB = 0x%x\n",
656 rtl_dm_dig->min_undec_pwdb_for_dm);
657 }
658 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
659 "MinUndecoratedPWDBForDM =%d\n",
660 rtl_dm_dig->min_undec_pwdb_for_dm);
661}
662
663static void rtl8812ae_dm_rssi_dump_to_register(struct ieee80211_hw *hw)
664{
665 struct rtl_priv *rtlpriv = rtl_priv(hw);
666
667 rtl_write_byte(rtlpriv, RA_RSSI_DUMP,
668 rtlpriv->stats.rx_rssi_percentage[0]);
669 rtl_write_byte(rtlpriv, RB_RSSI_DUMP,
670 rtlpriv->stats.rx_rssi_percentage[1]);
671
672 /* Rx EVM*/
673 rtl_write_byte(rtlpriv, RS1_RX_EVM_DUMP,
674 rtlpriv->stats.rx_evm_dbm[0]);
675 rtl_write_byte(rtlpriv, RS2_RX_EVM_DUMP,
676 rtlpriv->stats.rx_evm_dbm[1]);
677
678 /*Rx SNR*/
679 rtl_write_byte(rtlpriv, RA_RX_SNR_DUMP,
680 (u8)(rtlpriv->stats.rx_snr_db[0]));
681 rtl_write_byte(rtlpriv, RB_RX_SNR_DUMP,
682 (u8)(rtlpriv->stats.rx_snr_db[1]));
683
684 /*Rx Cfo_Short*/
685 rtl_write_word(rtlpriv, RA_CFO_SHORT_DUMP,
686 rtlpriv->stats.rx_cfo_short[0]);
687 rtl_write_word(rtlpriv, RB_CFO_SHORT_DUMP,
688 rtlpriv->stats.rx_cfo_short[1]);
689
690 /*Rx Cfo_Tail*/
691 rtl_write_word(rtlpriv, RA_CFO_LONG_DUMP,
692 rtlpriv->stats.rx_cfo_tail[0]);
693 rtl_write_word(rtlpriv, RB_CFO_LONG_DUMP,
694 rtlpriv->stats.rx_cfo_tail[1]);
695}
696
697static void rtl8821ae_dm_check_rssi_monitor(struct ieee80211_hw *hw)
698{
699 struct rtl_priv *rtlpriv = rtl_priv(hw);
700 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
701 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
702 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
703 struct rtl_sta_info *drv_priv;
704 u8 h2c_parameter[4] = { 0 };
705 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
706 u8 stbc_tx = 0;
707 u64 cur_txokcnt = 0, cur_rxokcnt = 0;
708 static u64 last_txokcnt = 0, last_rxokcnt;
709
710 cur_txokcnt = rtlpriv->stats.txbytesunicast - last_txokcnt;
711 cur_rxokcnt = rtlpriv->stats.rxbytesunicast - last_rxokcnt;
712 last_txokcnt = rtlpriv->stats.txbytesunicast;
713 last_rxokcnt = rtlpriv->stats.rxbytesunicast;
714 if (cur_rxokcnt > (last_txokcnt * 6))
715 h2c_parameter[3] = 0x01;
716 else
717 h2c_parameter[3] = 0x00;
718
719 /* AP & ADHOC & MESH */
720 if (mac->opmode == NL80211_IFTYPE_AP ||
721 mac->opmode == NL80211_IFTYPE_ADHOC ||
722 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
723 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
724 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
725 if (drv_priv->rssi_stat.undec_sm_pwdb <
726 tmp_entry_min_pwdb)
727 tmp_entry_min_pwdb =
728 drv_priv->rssi_stat.undec_sm_pwdb;
729 if (drv_priv->rssi_stat.undec_sm_pwdb >
730 tmp_entry_max_pwdb)
731 tmp_entry_max_pwdb =
732 drv_priv->rssi_stat.undec_sm_pwdb;
733 }
734 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
735
736 /* If associated entry is found */
737 if (tmp_entry_max_pwdb != 0) {
738 rtlpriv->dm.entry_max_undec_sm_pwdb =
739 tmp_entry_max_pwdb;
740 RTPRINT(rtlpriv, FDM, DM_PWDB,
741 "EntryMaxPWDB = 0x%lx(%ld)\n",
742 tmp_entry_max_pwdb, tmp_entry_max_pwdb);
743 } else {
744 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
745 }
746 /* If associated entry is found */
747 if (tmp_entry_min_pwdb != 0xff) {
748 rtlpriv->dm.entry_min_undec_sm_pwdb =
749 tmp_entry_min_pwdb;
750 RTPRINT(rtlpriv, FDM, DM_PWDB,
751 "EntryMinPWDB = 0x%lx(%ld)\n",
752 tmp_entry_min_pwdb, tmp_entry_min_pwdb);
753 } else {
754 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
755 }
756 }
757 /* Indicate Rx signal strength to FW. */
758 if (rtlpriv->dm.useramask) {
759 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
760 if (mac->mode == WIRELESS_MODE_AC_24G ||
761 mac->mode == WIRELESS_MODE_AC_5G ||
762 mac->mode == WIRELESS_MODE_AC_ONLY)
763 stbc_tx = (mac->vht_cur_stbc &
764 STBC_VHT_ENABLE_TX) ? 1 : 0;
765 else
766 stbc_tx = (mac->ht_cur_stbc &
767 STBC_HT_ENABLE_TX) ? 1 : 0;
768 h2c_parameter[3] |= stbc_tx << 1;
769 }
770 h2c_parameter[2] =
771 (u8)(rtlpriv->dm.undec_sm_pwdb & 0xFF);
772 h2c_parameter[1] = 0x20;
773 h2c_parameter[0] = 0;
774 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
775 rtl8821ae_fill_h2c_cmd(hw, H2C_RSSI_21AE_REPORT, 4,
776 h2c_parameter);
777 else
778 rtl8821ae_fill_h2c_cmd(hw, H2C_RSSI_21AE_REPORT, 3,
779 h2c_parameter);
780 } else {
781 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undec_sm_pwdb);
782 }
783 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
784 rtl8812ae_dm_rssi_dump_to_register(hw);
785 rtl8821ae_dm_find_minimum_rssi(hw);
786 dm_digtable->rssi_val_min = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
787}
788
789void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca)
790{
791 struct rtl_priv *rtlpriv = rtl_priv(hw);
792 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
793
794 if (dm_digtable->cur_cck_cca_thres != current_cca)
795 rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11AC, current_cca);
796
797 dm_digtable->pre_cck_cca_thres = dm_digtable->cur_cck_cca_thres;
798 dm_digtable->cur_cck_cca_thres = current_cca;
799}
800
801void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
802{
803 struct rtl_priv *rtlpriv = rtl_priv(hw);
804 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
805
806 if (dm_digtable->stop_dig)
807 return;
808
809 if (dm_digtable->cur_igvalue != current_igi) {
810 rtl_set_bbreg(hw, DM_REG_IGI_A_11AC,
811 DM_BIT_IGI_11AC, current_igi);
812 if (rtlpriv->phy.rf_type != RF_1T1R)
813 rtl_set_bbreg(hw, DM_REG_IGI_B_11AC,
814 DM_BIT_IGI_11AC, current_igi);
815 }
816 dm_digtable->cur_igvalue = current_igi;
817}
818
819static void rtl8821ae_dm_dig(struct ieee80211_hw *hw)
820{
821 struct rtl_priv *rtlpriv = rtl_priv(hw);
822 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
823 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
824 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
825 u8 dig_dynamic_min;
826 u8 dig_max_of_min;
827 bool first_connect, first_disconnect;
828 u8 dm_dig_max, dm_dig_min, offset;
829 u8 current_igi = dm_digtable->cur_igvalue;
830
831 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "\n");
832
833 if (mac->act_scanning) {
834 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
835 "Return: In Scan Progress\n");
836 return;
837 }
838
839 /*add by Neil Chen to avoid PSD is processing*/
840 dig_dynamic_min = dm_digtable->dig_dynamic_min;
841 first_connect = (mac->link_state >= MAC80211_LINKED) &&
842 (!dm_digtable->media_connect_0);
843 first_disconnect = (mac->link_state < MAC80211_LINKED) &&
844 (dm_digtable->media_connect_0);
845
846 /*1 Boundary Decision*/
847
848 dm_dig_max = 0x5A;
849
850 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8821AE)
851 dm_dig_min = DM_DIG_MIN;
852 else
853 dm_dig_min = 0x1C;
854
855 dig_max_of_min = DM_DIG_MAX_AP;
856
857 if (mac->link_state >= MAC80211_LINKED) {
858 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8821AE)
859 offset = 20;
860 else
861 offset = 10;
862
863 if ((dm_digtable->rssi_val_min + offset) > dm_dig_max)
864 dm_digtable->rx_gain_max = dm_dig_max;
865 else if ((dm_digtable->rssi_val_min + offset) < dm_dig_min)
866 dm_digtable->rx_gain_max = dm_dig_min;
867 else
868 dm_digtable->rx_gain_max =
869 dm_digtable->rssi_val_min + offset;
870
871 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
872 "dm_digtable->rssi_val_min=0x%x,dm_digtable->rx_gain_max = 0x%x",
873 dm_digtable->rssi_val_min,
874 dm_digtable->rx_gain_max);
875 if (rtlpriv->dm.one_entry_only) {
876 offset = 0;
877
878 if (dm_digtable->rssi_val_min - offset < dm_dig_min)
879 dig_dynamic_min = dm_dig_min;
880 else if (dm_digtable->rssi_val_min -
881 offset > dig_max_of_min)
882 dig_dynamic_min = dig_max_of_min;
883 else
884 dig_dynamic_min =
885 dm_digtable->rssi_val_min - offset;
886
887 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
888 "bOneEntryOnly=TRUE, dig_dynamic_min=0x%x\n",
889 dig_dynamic_min);
890 } else {
891 dig_dynamic_min = dm_dig_min;
892 }
893 } else {
894 dm_digtable->rx_gain_max = dm_dig_max;
895 dig_dynamic_min = dm_dig_min;
896 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
897 "No Link\n");
898 }
899
900 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
901 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
902 "Abnornally false alarm case.\n");
903
904 if (dm_digtable->large_fa_hit != 3)
905 dm_digtable->large_fa_hit++;
906 if (dm_digtable->forbidden_igi < current_igi) {
907 dm_digtable->forbidden_igi = current_igi;
908 dm_digtable->large_fa_hit = 1;
909 }
910
911 if (dm_digtable->large_fa_hit >= 3) {
912 if ((dm_digtable->forbidden_igi + 1) >
913 dm_digtable->rx_gain_max)
914 dm_digtable->rx_gain_min =
915 dm_digtable->rx_gain_max;
916 else
917 dm_digtable->rx_gain_min =
918 (dm_digtable->forbidden_igi + 1);
919 dm_digtable->recover_cnt = 3600;
920 }
921 } else {
922 /*Recovery mechanism for IGI lower bound*/
923 if (dm_digtable->recover_cnt != 0) {
924 dm_digtable->recover_cnt--;
925 } else {
926 if (dm_digtable->large_fa_hit < 3) {
927 if ((dm_digtable->forbidden_igi - 1) <
928 dig_dynamic_min) {
929 dm_digtable->forbidden_igi =
930 dig_dynamic_min;
931 dm_digtable->rx_gain_min =
932 dig_dynamic_min;
933 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
934 "Normal Case: At Lower Bound\n");
935 } else {
936 dm_digtable->forbidden_igi--;
937 dm_digtable->rx_gain_min =
938 (dm_digtable->forbidden_igi + 1);
939 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
940 "Normal Case: Approach Lower Bound\n");
941 }
942 } else {
943 dm_digtable->large_fa_hit = 0;
944 }
945 }
946 }
947 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
948 "pDM_DigTable->LargeFAHit=%d\n",
949 dm_digtable->large_fa_hit);
950
951 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 10)
952 dm_digtable->rx_gain_min = dm_dig_min;
953
954 if (dm_digtable->rx_gain_min > dm_digtable->rx_gain_max)
955 dm_digtable->rx_gain_min = dm_digtable->rx_gain_max;
956
957 /*Adjust initial gain by false alarm*/
958 if (mac->link_state >= MAC80211_LINKED) {
959 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
960 "DIG AfterLink\n");
961 if (first_connect) {
962 if (dm_digtable->rssi_val_min <= dig_max_of_min)
963 current_igi = dm_digtable->rssi_val_min;
964 else
965 current_igi = dig_max_of_min;
966 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
967 "First Connect\n");
968 } else {
969 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
970 current_igi = current_igi + 4;
971 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
972 current_igi = current_igi + 2;
973 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
974 current_igi = current_igi - 2;
975
976 if ((rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 10) &&
977 (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)) {
978 current_igi = dm_digtable->rx_gain_min;
979 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
980 "Beacon is less than 10 and FA is less than 768, IGI GOES TO 0x1E!!!!!!!!!!!!\n");
981 }
982 }
983 } else {
984 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
985 "DIG BeforeLink\n");
986 if (first_disconnect) {
987 current_igi = dm_digtable->rx_gain_min;
988 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
989 "First DisConnect\n");
990 } else {
991 /* 2012.03.30 LukeLee: enable DIG before
992 * link but with very high thresholds
993 */
994 if (rtlpriv->falsealm_cnt.cnt_all > 2000)
995 current_igi = current_igi + 4;
996 else if (rtlpriv->falsealm_cnt.cnt_all > 600)
997 current_igi = current_igi + 2;
998 else if (rtlpriv->falsealm_cnt.cnt_all < 300)
999 current_igi = current_igi - 2;
1000
1001 if (current_igi >= 0x3e)
1002 current_igi = 0x3e;
1003
1004 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "England DIG\n");
1005 }
1006 }
1007 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1008 "DIG End Adjust IGI\n");
1009 /* Check initial gain by upper/lower bound*/
1010
1011 if (current_igi > dm_digtable->rx_gain_max)
1012 current_igi = dm_digtable->rx_gain_max;
1013 if (current_igi < dm_digtable->rx_gain_min)
1014 current_igi = dm_digtable->rx_gain_min;
1015
1016 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1017 "rx_gain_max=0x%x, rx_gain_min=0x%x\n",
1018 dm_digtable->rx_gain_max, dm_digtable->rx_gain_min);
1019 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1020 "TotalFA=%d\n", rtlpriv->falsealm_cnt.cnt_all);
1021 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1022 "CurIGValue=0x%x\n", current_igi);
1023
1024 rtl8821ae_dm_write_dig(hw, current_igi);
1025 dm_digtable->media_connect_0 =
1026 ((mac->link_state >= MAC80211_LINKED) ? true : false);
1027 dm_digtable->dig_dynamic_min = dig_dynamic_min;
1028}
1029
1030static void rtl8821ae_dm_common_info_self_update(struct ieee80211_hw *hw)
1031{
1032 struct rtl_priv *rtlpriv = rtl_priv(hw);
1033 u8 cnt = 0;
1034 struct rtl_sta_info *drv_priv;
1035
1036 rtlpriv->dm.tx_rate = 0xff;
1037
1038 rtlpriv->dm.one_entry_only = false;
1039
1040 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
1041 rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
1042 rtlpriv->dm.one_entry_only = true;
1043 return;
1044 }
1045
1046 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1047 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
1048 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
1049 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1050 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list)
1051 cnt++;
1052 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1053
1054 if (cnt == 1)
1055 rtlpriv->dm.one_entry_only = true;
1056 }
1057}
1058
1059static void rtl8821ae_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
1060{
1061 struct rtl_priv *rtlpriv = rtl_priv(hw);
1062 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
1063 u32 cck_enable = 0;
1064
1065 /*read OFDM FA counter*/
1066 falsealm_cnt->cnt_ofdm_fail =
1067 rtl_get_bbreg(hw, ODM_REG_OFDM_FA_11AC, BMASKLWORD);
1068 falsealm_cnt->cnt_cck_fail =
1069 rtl_get_bbreg(hw, ODM_REG_CCK_FA_11AC, BMASKLWORD);
1070
1071 cck_enable = rtl_get_bbreg(hw, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1072 if (cck_enable) /*if(pDM_Odm->pBandType == ODM_BAND_2_4G)*/
1073 falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail +
1074 falsealm_cnt->cnt_cck_fail;
1075 else
1076 falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail;
1077
1078 /*reset OFDM FA coutner*/
1079 rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1);
1080 rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0);
1081 /* reset CCK FA counter*/
1082 rtl_set_bbreg(hw, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0);
1083 rtl_set_bbreg(hw, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1);
1084
1085 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "Cnt_Cck_fail=%d\n",
1086 falsealm_cnt->cnt_cck_fail);
1087 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "cnt_ofdm_fail=%d\n",
1088 falsealm_cnt->cnt_ofdm_fail);
1089 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "Total False Alarm=%d\n",
1090 falsealm_cnt->cnt_all);
1091}
1092
1093static void rtl8812ae_dm_check_txpower_tracking_thermalmeter(
1094 struct ieee80211_hw *hw)
1095{
1096 struct rtl_priv *rtlpriv = rtl_priv(hw);
1097 static u8 tm_trigger;
1098
1099 if (!tm_trigger) {
1100 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER_88E,
1101 BIT(17) | BIT(16), 0x03);
1102 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1103 "Trigger 8812 Thermal Meter!!\n");
1104 tm_trigger = 1;
1105 return;
1106 }
1107 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1108 "Schedule TxPowerTracking direct call!!\n");
1109 rtl8812ae_dm_txpower_tracking_callback_thermalmeter(hw);
1110 tm_trigger = 0;
1111}
1112
1113static void rtl8821ae_dm_iq_calibrate(struct ieee80211_hw *hw)
1114{
1115 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1116 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1117 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1118
1119 if (mac->link_state >= MAC80211_LINKED) {
1120 if (rtldm->linked_interval < 3)
1121 rtldm->linked_interval++;
1122
1123 if (rtldm->linked_interval == 2) {
1124 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1125 rtl8812ae_phy_iq_calibrate(hw, false);
1126 else
1127 rtl8821ae_phy_iq_calibrate(hw, false);
1128 }
1129 } else {
1130 rtldm->linked_interval = 0;
1131 }
1132}
1133
1134static void rtl8812ae_get_delta_swing_table(struct ieee80211_hw *hw,
1135 u8 **up_a, u8 **down_a,
1136 u8 **up_b, u8 **down_b)
1137{
1138 struct rtl_priv *rtlpriv = rtl_priv(hw);
1139 struct rtl_phy *rtlphy = &rtlpriv->phy;
1140 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1141 u8 channel = rtlphy->current_channel;
1142 u8 rate = rtldm->tx_rate;
1143
1144 if (1 <= channel && channel <= 14) {
1145 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) {
1146 *up_a = rtl8812ae_delta_swing_table_idx_24gccka_p;
1147 *down_a = rtl8812ae_delta_swing_table_idx_24gccka_n;
1148 *up_b = rtl8812ae_delta_swing_table_idx_24gcckb_p;
1149 *down_b = rtl8812ae_delta_swing_table_idx_24gcckb_n;
1150 } else {
1151 *up_a = rtl8812ae_delta_swing_table_idx_24ga_p;
1152 *down_a = rtl8812ae_delta_swing_table_idx_24ga_n;
1153 *up_b = rtl8812ae_delta_swing_table_idx_24gb_p;
1154 *down_b = rtl8812ae_delta_swing_table_idx_24gb_n;
1155 }
1156 } else if (36 <= channel && channel <= 64) {
1157 *up_a = rtl8812ae_delta_swing_table_idx_5ga_p[0];
1158 *down_a = rtl8812ae_delta_swing_table_idx_5ga_n[0];
1159 *up_b = rtl8812ae_delta_swing_table_idx_5gb_p[0];
1160 *down_b = rtl8812ae_delta_swing_table_idx_5gb_n[0];
1161 } else if (100 <= channel && channel <= 140) {
1162 *up_a = rtl8812ae_delta_swing_table_idx_5ga_p[1];
1163 *down_a = rtl8812ae_delta_swing_table_idx_5ga_n[1];
1164 *up_b = rtl8812ae_delta_swing_table_idx_5gb_p[1];
1165 *down_b = rtl8812ae_delta_swing_table_idx_5gb_n[1];
1166 } else if (149 <= channel && channel <= 173) {
1167 *up_a = rtl8812ae_delta_swing_table_idx_5ga_p[2];
1168 *down_a = rtl8812ae_delta_swing_table_idx_5ga_n[2];
1169 *up_b = rtl8812ae_delta_swing_table_idx_5gb_p[2];
1170 *down_b = rtl8812ae_delta_swing_table_idx_5gb_n[2];
1171 } else {
1172 *up_a = (u8 *)rtl8818e_delta_swing_table_idx_24gb_p;
1173 *down_a = (u8 *)rtl8818e_delta_swing_table_idx_24gb_n;
1174 *up_b = (u8 *)rtl8818e_delta_swing_table_idx_24gb_p;
1175 *down_b = (u8 *)rtl8818e_delta_swing_table_idx_24gb_n;
1176 }
1177}
1178
1179void rtl8821ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate)
1180{
1181 struct rtl_priv *rtlpriv = rtl_priv(hw);
1182 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1183 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1184 u8 p = 0;
1185
1186 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1187 "Get C2H Command! Rate=0x%x\n", rate);
1188
1189 rtldm->tx_rate = rate;
1190
1191 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1192 rtl8821ae_dm_txpwr_track_set_pwr(hw, MIX_MODE, RF90_PATH_A, 0);
1193 } else {
1194 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1195 rtl8812ae_dm_txpwr_track_set_pwr(hw, MIX_MODE, p, 0);
1196 }
1197}
1198
1199u8 rtl8821ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate)
1200{
1201 struct rtl_priv *rtlpriv = rtl_priv(hw);
1202 u8 ret_rate = MGN_1M;
1203
1204 switch (rate) {
1205 case DESC_RATE1M:
1206 ret_rate = MGN_1M;
1207 break;
1208 case DESC_RATE2M:
1209 ret_rate = MGN_2M;
1210 break;
1211 case DESC_RATE5_5M:
1212 ret_rate = MGN_5_5M;
1213 break;
1214 case DESC_RATE11M:
1215 ret_rate = MGN_11M;
1216 break;
1217 case DESC_RATE6M:
1218 ret_rate = MGN_6M;
1219 break;
1220 case DESC_RATE9M:
1221 ret_rate = MGN_9M;
1222 break;
1223 case DESC_RATE12M:
1224 ret_rate = MGN_12M;
1225 break;
1226 case DESC_RATE18M:
1227 ret_rate = MGN_18M;
1228 break;
1229 case DESC_RATE24M:
1230 ret_rate = MGN_24M;
1231 break;
1232 case DESC_RATE36M:
1233 ret_rate = MGN_36M;
1234 break;
1235 case DESC_RATE48M:
1236 ret_rate = MGN_48M;
1237 break;
1238 case DESC_RATE54M:
1239 ret_rate = MGN_54M;
1240 break;
1241 case DESC_RATEMCS0:
1242 ret_rate = MGN_MCS0;
1243 break;
1244 case DESC_RATEMCS1:
1245 ret_rate = MGN_MCS1;
1246 break;
1247 case DESC_RATEMCS2:
1248 ret_rate = MGN_MCS2;
1249 break;
1250 case DESC_RATEMCS3:
1251 ret_rate = MGN_MCS3;
1252 break;
1253 case DESC_RATEMCS4:
1254 ret_rate = MGN_MCS4;
1255 break;
1256 case DESC_RATEMCS5:
1257 ret_rate = MGN_MCS5;
1258 break;
1259 case DESC_RATEMCS6:
1260 ret_rate = MGN_MCS6;
1261 break;
1262 case DESC_RATEMCS7:
1263 ret_rate = MGN_MCS7;
1264 break;
1265 case DESC_RATEMCS8:
1266 ret_rate = MGN_MCS8;
1267 break;
1268 case DESC_RATEMCS9:
1269 ret_rate = MGN_MCS9;
1270 break;
1271 case DESC_RATEMCS10:
1272 ret_rate = MGN_MCS10;
1273 break;
1274 case DESC_RATEMCS11:
1275 ret_rate = MGN_MCS11;
1276 break;
1277 case DESC_RATEMCS12:
1278 ret_rate = MGN_MCS12;
1279 break;
1280 case DESC_RATEMCS13:
1281 ret_rate = MGN_MCS13;
1282 break;
1283 case DESC_RATEMCS14:
1284 ret_rate = MGN_MCS14;
1285 break;
1286 case DESC_RATEMCS15:
1287 ret_rate = MGN_MCS15;
1288 break;
1289 case DESC_RATEVHT1SS_MCS0:
1290 ret_rate = MGN_VHT1SS_MCS0;
1291 break;
1292 case DESC_RATEVHT1SS_MCS1:
1293 ret_rate = MGN_VHT1SS_MCS1;
1294 break;
1295 case DESC_RATEVHT1SS_MCS2:
1296 ret_rate = MGN_VHT1SS_MCS2;
1297 break;
1298 case DESC_RATEVHT1SS_MCS3:
1299 ret_rate = MGN_VHT1SS_MCS3;
1300 break;
1301 case DESC_RATEVHT1SS_MCS4:
1302 ret_rate = MGN_VHT1SS_MCS4;
1303 break;
1304 case DESC_RATEVHT1SS_MCS5:
1305 ret_rate = MGN_VHT1SS_MCS5;
1306 break;
1307 case DESC_RATEVHT1SS_MCS6:
1308 ret_rate = MGN_VHT1SS_MCS6;
1309 break;
1310 case DESC_RATEVHT1SS_MCS7:
1311 ret_rate = MGN_VHT1SS_MCS7;
1312 break;
1313 case DESC_RATEVHT1SS_MCS8:
1314 ret_rate = MGN_VHT1SS_MCS8;
1315 break;
1316 case DESC_RATEVHT1SS_MCS9:
1317 ret_rate = MGN_VHT1SS_MCS9;
1318 break;
1319 case DESC_RATEVHT2SS_MCS0:
1320 ret_rate = MGN_VHT2SS_MCS0;
1321 break;
1322 case DESC_RATEVHT2SS_MCS1:
1323 ret_rate = MGN_VHT2SS_MCS1;
1324 break;
1325 case DESC_RATEVHT2SS_MCS2:
1326 ret_rate = MGN_VHT2SS_MCS2;
1327 break;
1328 case DESC_RATEVHT2SS_MCS3:
1329 ret_rate = MGN_VHT2SS_MCS3;
1330 break;
1331 case DESC_RATEVHT2SS_MCS4:
1332 ret_rate = MGN_VHT2SS_MCS4;
1333 break;
1334 case DESC_RATEVHT2SS_MCS5:
1335 ret_rate = MGN_VHT2SS_MCS5;
1336 break;
1337 case DESC_RATEVHT2SS_MCS6:
1338 ret_rate = MGN_VHT2SS_MCS6;
1339 break;
1340 case DESC_RATEVHT2SS_MCS7:
1341 ret_rate = MGN_VHT2SS_MCS7;
1342 break;
1343 case DESC_RATEVHT2SS_MCS8:
1344 ret_rate = MGN_VHT2SS_MCS8;
1345 break;
1346 case DESC_RATEVHT2SS_MCS9:
1347 ret_rate = MGN_VHT2SS_MCS9;
1348 break;
1349 default:
1350 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1351 "HwRateToMRate8812(): Non supported Rate [%x]!!!\n",
1352 rate);
1353 break;
1354 }
1355 return ret_rate;
1356}
1357
1358/*-----------------------------------------------------------------------------
1359 * Function: odm_TxPwrTrackSetPwr88E()
1360 *
1361 * Overview: 88E change all channel tx power accordign to flag.
1362 * OFDM & CCK are all different.
1363 *
1364 * Input: NONE
1365 *
1366 * Output: NONE
1367 *
1368 * Return: NONE
1369 *
1370 * Revised History:
1371 * When Who Remark
1372 * 04/23/2012 MHC Create Version 0.
1373 *
1374 *---------------------------------------------------------------------------
1375 */
1376void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
1377 enum pwr_track_control_method method,
1378 u8 rf_path, u8 channel_mapped_index)
1379{
1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1381 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1382 struct rtl_phy *rtlphy = &rtlpriv->phy;
1383 u32 final_swing_idx[2];
1384 u8 pwr_tracking_limit = 26; /*+1.0dB*/
1385 u8 tx_rate = 0xFF;
1386 char final_ofdm_swing_index = 0;
1387
1388 if (rtldm->tx_rate != 0xFF)
1389 tx_rate =
1390 rtl8821ae_hw_rate_to_mrate(hw, rtldm->tx_rate);
1391
1392 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1393 "===>rtl8812ae_dm_txpwr_track_set_pwr\n");
1394 /*20130429 Mimic Modify High Rate BBSwing Limit.*/
1395 if (tx_rate != 0xFF) {
1396 /*CCK*/
1397 if ((tx_rate >= MGN_1M) && (tx_rate <= MGN_11M))
1398 pwr_tracking_limit = 32; /*+4dB*/
1399 /*OFDM*/
1400 else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
1401 pwr_tracking_limit = 30; /*+3dB*/
1402 else if (tx_rate == MGN_54M)
1403 pwr_tracking_limit = 28; /*+2dB*/
1404 /*HT*/
1405 /*QPSK/BPSK*/
1406 else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2))
1407 pwr_tracking_limit = 34; /*+5dB*/
1408 /*16QAM*/
1409 else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4))
1410 pwr_tracking_limit = 30; /*+3dB*/
1411 /*64QAM*/
1412 else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7))
1413 pwr_tracking_limit = 28; /*+2dB*/
1414 /*QPSK/BPSK*/
1415 else if ((tx_rate >= MGN_MCS8) && (tx_rate <= MGN_MCS10))
1416 pwr_tracking_limit = 34; /*+5dB*/
1417 /*16QAM*/
1418 else if ((tx_rate >= MGN_MCS11) && (tx_rate <= MGN_MCS12))
1419 pwr_tracking_limit = 30; /*+3dB*/
1420 /*64QAM*/
1421 else if ((tx_rate >= MGN_MCS13) && (tx_rate <= MGN_MCS15))
1422 pwr_tracking_limit = 28; /*+2dB*/
1423
1424 /*2 VHT*/
1425 /*QPSK/BPSK*/
1426 else if ((tx_rate >= MGN_VHT1SS_MCS0) &&
1427 (tx_rate <= MGN_VHT1SS_MCS2))
1428 pwr_tracking_limit = 34; /*+5dB*/
1429 /*16QAM*/
1430 else if ((tx_rate >= MGN_VHT1SS_MCS3) &&
1431 (tx_rate <= MGN_VHT1SS_MCS4))
1432 pwr_tracking_limit = 30; /*+3dB*/
1433 /*64QAM*/
1434 else if ((tx_rate >= MGN_VHT1SS_MCS5) &&
1435 (tx_rate <= MGN_VHT1SS_MCS6))
1436 pwr_tracking_limit = 28; /*+2dB*/
1437 else if (tx_rate == MGN_VHT1SS_MCS7) /*64QAM*/
1438 pwr_tracking_limit = 26; /*+1dB*/
1439 else if (tx_rate == MGN_VHT1SS_MCS8) /*256QAM*/
1440 pwr_tracking_limit = 24; /*+0dB*/
1441 else if (tx_rate == MGN_VHT1SS_MCS9) /*256QAM*/
1442 pwr_tracking_limit = 22; /*-1dB*/
1443 /*QPSK/BPSK*/
1444 else if ((tx_rate >= MGN_VHT2SS_MCS0) &&
1445 (tx_rate <= MGN_VHT2SS_MCS2))
1446 pwr_tracking_limit = 34; /*+5dB*/
1447 /*16QAM*/
1448 else if ((tx_rate >= MGN_VHT2SS_MCS3) &&
1449 (tx_rate <= MGN_VHT2SS_MCS4))
1450 pwr_tracking_limit = 30; /*+3dB*/
1451 /*64QAM*/
1452 else if ((tx_rate >= MGN_VHT2SS_MCS5) &&
1453 (tx_rate <= MGN_VHT2SS_MCS6))
1454 pwr_tracking_limit = 28; /*+2dB*/
1455 else if (tx_rate == MGN_VHT2SS_MCS7) /*64QAM*/
1456 pwr_tracking_limit = 26; /*+1dB*/
1457 else if (tx_rate == MGN_VHT2SS_MCS8) /*256QAM*/
1458 pwr_tracking_limit = 24; /*+0dB*/
1459 else if (tx_rate == MGN_VHT2SS_MCS9) /*256QAM*/
1460 pwr_tracking_limit = 22; /*-1dB*/
1461 else
1462 pwr_tracking_limit = 24;
1463 }
1464 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1465 "TxRate=0x%x, PwrTrackingLimit=%d\n",
1466 tx_rate, pwr_tracking_limit);
1467
1468 if (method == BBSWING) {
1469 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1470 "===>rtl8812ae_dm_txpwr_track_set_pwr\n");
1471
1472 if (rf_path == RF90_PATH_A) {
1473 u32 tmp;
1474
1475 final_swing_idx[RF90_PATH_A] =
1476 (rtldm->ofdm_index[RF90_PATH_A] >
1477 pwr_tracking_limit) ?
1478 pwr_tracking_limit :
1479 rtldm->ofdm_index[RF90_PATH_A];
1480 tmp = final_swing_idx[RF90_PATH_A];
1481 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1482 "pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d,pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n",
1483 rtldm->ofdm_index[RF90_PATH_A],
1484 final_swing_idx[RF90_PATH_A]);
1485
1486 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
1487 txscaling_tbl[tmp]);
1488 } else {
1489 u32 tmp;
1490
1491 final_swing_idx[RF90_PATH_B] =
1492 rtldm->ofdm_index[RF90_PATH_B] >
1493 pwr_tracking_limit ?
1494 pwr_tracking_limit :
1495 rtldm->ofdm_index[RF90_PATH_B];
1496 tmp = final_swing_idx[RF90_PATH_B];
1497 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1498 "pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_B]=%d\n",
1499 rtldm->ofdm_index[RF90_PATH_B],
1500 final_swing_idx[RF90_PATH_B]);
1501
1502 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
1503 txscaling_tbl[tmp]);
1504 }
1505 } else if (method == MIX_MODE) {
1506 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1507 "pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->Aboslute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
1508 rtldm->default_ofdm_index,
1509 rtldm->absolute_ofdm_swing_idx[rf_path],
1510 rf_path);
1511
1512 final_ofdm_swing_index = rtldm->default_ofdm_index +
1513 rtldm->absolute_ofdm_swing_idx[rf_path];
1514
1515 if (rf_path == RF90_PATH_A) {
1516 /*BBSwing higher then Limit*/
1517 if (final_ofdm_swing_index > pwr_tracking_limit) {
1518 rtldm->remnant_cck_idx =
1519 final_ofdm_swing_index -
1520 pwr_tracking_limit;
1521 /* CCK Follow the same compensation value
1522 * as Path A
1523 */
1524 rtldm->remnant_ofdm_swing_idx[rf_path] =
1525 final_ofdm_swing_index -
1526 pwr_tracking_limit;
1527
1528 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
1529 txscaling_tbl[pwr_tracking_limit]);
1530
1531 rtldm->modify_txagc_flag_path_a = true;
1532
1533 /*Set TxAGC Page C{};*/
1534 rtl8821ae_phy_set_txpower_level_by_path(hw,
1535 rtlphy->current_channel,
1536 RF90_PATH_A);
1537
1538 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1539 "******Path_A Over BBSwing Limit ,PwrTrackingLimit = %d ,Remnant TxAGC Value = %d\n",
1540 pwr_tracking_limit,
1541 rtldm->remnant_ofdm_swing_idx[rf_path]);
1542 } else if (final_ofdm_swing_index < 0) {
1543 rtldm->remnant_cck_idx = final_ofdm_swing_index;
1544 /* CCK Follow the same compensate value as Path A*/
1545 rtldm->remnant_ofdm_swing_idx[rf_path] =
1546 final_ofdm_swing_index;
1547
1548 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
1549 txscaling_tbl[0]);
1550
1551 rtldm->modify_txagc_flag_path_a = true;
1552
1553 /*Set TxAGC Page C{};*/
1554 rtl8821ae_phy_set_txpower_level_by_path(hw,
1555 rtlphy->current_channel, RF90_PATH_A);
1556
1557 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1558 "******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n",
1559 rtldm->remnant_ofdm_swing_idx[rf_path]);
1560 } else {
1561 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
1562 txscaling_tbl[(u8)final_ofdm_swing_index]);
1563
1564 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1565 "******Path_A Compensate with BBSwing, Final_OFDM_Swing_Index = %d\n",
1566 final_ofdm_swing_index);
1567 /*If TxAGC has changed, reset TxAGC again*/
1568 if (rtldm->modify_txagc_flag_path_a) {
1569 rtldm->remnant_cck_idx = 0;
1570 rtldm->remnant_ofdm_swing_idx[rf_path] = 0;
1571
1572 /*Set TxAGC Page C{};*/
1573 rtl8821ae_phy_set_txpower_level_by_path(hw,
1574 rtlphy->current_channel, RF90_PATH_A);
1575 rtldm->modify_txagc_flag_path_a = false;
1576
1577 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
1578 DBG_LOUD,
1579 "******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n");
1580 }
1581 }
1582 }
1583 /*BBSwing higher then Limit*/
1584 if (rf_path == RF90_PATH_B) {
1585 if (final_ofdm_swing_index > pwr_tracking_limit) {
1586 rtldm->remnant_ofdm_swing_idx[rf_path] =
1587 final_ofdm_swing_index -
1588 pwr_tracking_limit;
1589
1590 rtl_set_bbreg(hw, RB_TXSCALE,
1591 0xFFE00000,
1592 txscaling_tbl[pwr_tracking_limit]);
1593
1594 rtldm->modify_txagc_flag_path_b = true;
1595
1596 /*Set TxAGC Page E{};*/
1597 rtl8821ae_phy_set_txpower_level_by_path(hw,
1598 rtlphy->current_channel, RF90_PATH_B);
1599
1600 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1601 "******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n",
1602 pwr_tracking_limit,
1603 rtldm->remnant_ofdm_swing_idx[rf_path]);
1604 } else if (final_ofdm_swing_index < 0) {
1605 rtldm->remnant_ofdm_swing_idx[rf_path] =
1606 final_ofdm_swing_index;
1607
1608 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
1609 txscaling_tbl[0]);
1610
1611 rtldm->modify_txagc_flag_path_b = true;
1612
1613 /*Set TxAGC Page E{};*/
1614 rtl8821ae_phy_set_txpower_level_by_path(hw,
1615 rtlphy->current_channel, RF90_PATH_B);
1616
1617 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1618 "******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n",
1619 rtldm->remnant_ofdm_swing_idx[rf_path]);
1620 } else {
1621 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
1622 txscaling_tbl[(u8)final_ofdm_swing_index]);
1623
1624 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1625 "******Path_B Compensate with BBSwing ,Final_OFDM_Swing_Index = %d\n",
1626 final_ofdm_swing_index);
1627 /*If TxAGC has changed, reset TxAGC again*/
1628 if (rtldm->modify_txagc_flag_path_b) {
1629 rtldm->remnant_ofdm_swing_idx[rf_path] = 0;
1630
1631 /*Set TxAGC Page E{};*/
1632 rtl8821ae_phy_set_txpower_level_by_path(hw,
1633 rtlphy->current_channel, RF90_PATH_B);
1634
1635 rtldm->modify_txagc_flag_path_b =
1636 false;
1637
1638 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1639 "******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE\n");
1640 }
1641 }
1642 }
1643 } else {
1644 return;
1645 }
1646}
1647
1648void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(
1649 struct ieee80211_hw *hw)
1650{
1651 struct rtl_priv *rtlpriv = rtl_priv(hw);
1652 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1653 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1654 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1655 u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;
1656 u8 thermal_value_avg_count = 0;
1657 u32 thermal_value_avg = 0;
1658 /* OFDM BB Swing should be less than +3.0dB, */
1659 u8 ofdm_min_index = 6;
1660 /* GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
1661 u8 index_for_channel = 0;
1662 /* 1. The following TWO tables decide
1663 * the final index of OFDM/CCK swing table.
1664 */
1665 u8 *delta_swing_table_idx_tup_a;
1666 u8 *delta_swing_table_idx_tdown_a;
1667 u8 *delta_swing_table_idx_tup_b;
1668 u8 *delta_swing_table_idx_tdown_b;
1669
1670 /*2. Initilization ( 7 steps in total )*/
1671 rtl8812ae_get_delta_swing_table(hw,
1672 (u8 **)&delta_swing_table_idx_tup_a,
1673 (u8 **)&delta_swing_table_idx_tdown_a,
1674 (u8 **)&delta_swing_table_idx_tup_b,
1675 (u8 **)&delta_swing_table_idx_tdown_b);
1676
1677 rtldm->txpower_trackinginit = true;
1678
1679 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1680 "pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]:%d, pDM_Odm->DefaultOfdmIndex: %d\n",
1681 rtldm->swing_idx_cck_base,
1682 rtldm->swing_idx_ofdm_base[RF90_PATH_A],
1683 rtldm->default_ofdm_index);
1684
1685 thermal_value = (u8)rtl_get_rfreg(hw, RF90_PATH_A,
1686 /*0x42: RF Reg[15:10] 88E*/
1687 RF_T_METER_8812A, 0xfc00);
1688 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1689 "Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n",
1690 thermal_value, rtlefuse->eeprom_thermalmeter);
1691 if (!rtldm->txpower_track_control ||
1692 rtlefuse->eeprom_thermalmeter == 0 ||
1693 rtlefuse->eeprom_thermalmeter == 0xFF)
1694 return;
1695
1696 /* 3. Initialize ThermalValues of RFCalibrateInfo*/
1697
1698 if (rtlhal->reloadtxpowerindex)
1699 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1700 "reload ofdm index for band switch\n");
1701
1702 /*4. Calculate average thermal meter*/
1703 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermal_value;
1704 rtldm->thermalvalue_avg_index++;
1705 if (rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_8812A)
1706 /*Average times = c.AverageThermalNum*/
1707 rtldm->thermalvalue_avg_index = 0;
1708
1709 for (i = 0; i < AVG_THERMAL_NUM_8812A; i++) {
1710 if (rtldm->thermalvalue_avg[i]) {
1711 thermal_value_avg += rtldm->thermalvalue_avg[i];
1712 thermal_value_avg_count++;
1713 }
1714 }
1715 /*Calculate Average ThermalValue after average enough times*/
1716 if (thermal_value_avg_count) {
1717 thermal_value = (u8)(thermal_value_avg /
1718 thermal_value_avg_count);
1719 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1720 "AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n",
1721 thermal_value, rtlefuse->eeprom_thermalmeter);
1722 }
1723
1724 /*5. Calculate delta, delta_LCK, delta_IQK.
1725 *"delta" here is used to determine whether
1726 *thermal value changes or not.
1727 */
1728 delta = (thermal_value > rtldm->thermalvalue) ?
1729 (thermal_value - rtldm->thermalvalue) :
1730 (rtldm->thermalvalue - thermal_value);
1731 delta_lck = (thermal_value > rtldm->thermalvalue_lck) ?
1732 (thermal_value - rtldm->thermalvalue_lck) :
1733 (rtldm->thermalvalue_lck - thermal_value);
1734 delta_iqk = (thermal_value > rtldm->thermalvalue_iqk) ?
1735 (thermal_value - rtldm->thermalvalue_iqk) :
1736 (rtldm->thermalvalue_iqk - thermal_value);
1737
1738 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1739 "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
1740 delta, delta_lck, delta_iqk);
1741
1742 /* 6. If necessary, do LCK.
1743 * Delta temperature is equal to or larger than 20 centigrade.
1744 */
1745 if (delta_lck >= IQK_THRESHOLD) {
1746 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1747 "delta_LCK(%d) >= Threshold_IQK(%d)\n",
1748 delta_lck, IQK_THRESHOLD);
1749 rtldm->thermalvalue_lck = thermal_value;
1750 rtl8821ae_phy_lc_calibrate(hw);
1751 }
1752
1753 /*7. If necessary, move the index of swing table to adjust Tx power.*/
1754
1755 if (delta > 0 && rtldm->txpower_track_control) {
1756 /* "delta" here is used to record the
1757 * absolute value of differrence.
1758 */
1759 delta = thermal_value > rtlefuse->eeprom_thermalmeter ?
1760 (thermal_value - rtlefuse->eeprom_thermalmeter) :
1761 (rtlefuse->eeprom_thermalmeter - thermal_value);
1762
1763 if (delta >= TXPWR_TRACK_TABLE_SIZE)
1764 delta = TXPWR_TRACK_TABLE_SIZE - 1;
1765
1766 /*7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
1767
1768 if (thermal_value > rtlefuse->eeprom_thermalmeter) {
1769 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1770 "delta_swing_table_idx_tup_a[%d] = %d\n",
1771 delta, delta_swing_table_idx_tup_a[delta]);
1772 rtldm->delta_power_index_last[RF90_PATH_A] =
1773 rtldm->delta_power_index[RF90_PATH_A];
1774 rtldm->delta_power_index[RF90_PATH_A] =
1775 delta_swing_table_idx_tup_a[delta];
1776
1777 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A] =
1778 delta_swing_table_idx_tup_a[delta];
1779 /*Record delta swing for mix mode power tracking*/
1780
1781 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1782 "******Temp is higher and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
1783 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A]);
1784
1785 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1786 "delta_swing_table_idx_tup_b[%d] = %d\n",
1787 delta, delta_swing_table_idx_tup_b[delta]);
1788 rtldm->delta_power_index_last[RF90_PATH_B] =
1789 rtldm->delta_power_index[RF90_PATH_B];
1790 rtldm->delta_power_index[RF90_PATH_B] =
1791 delta_swing_table_idx_tup_b[delta];
1792
1793 rtldm->absolute_ofdm_swing_idx[RF90_PATH_B] =
1794 delta_swing_table_idx_tup_b[delta];
1795 /*Record delta swing for mix mode power tracking*/
1796
1797 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1798 "******Temp is higher and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n",
1799 rtldm->absolute_ofdm_swing_idx[RF90_PATH_B]);
1800 } else {
1801 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1802 "delta_swing_table_idx_tdown_a[%d] = %d\n",
1803 delta, delta_swing_table_idx_tdown_a[delta]);
1804
1805 rtldm->delta_power_index_last[RF90_PATH_A] =
1806 rtldm->delta_power_index[RF90_PATH_A];
1807 rtldm->delta_power_index[RF90_PATH_A] =
1808 -1 * delta_swing_table_idx_tdown_a[delta];
1809
1810 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A] =
1811 -1 * delta_swing_table_idx_tdown_a[delta];
1812 /* Record delta swing for mix mode power tracking*/
1813 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1814 "******Temp is lower and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
1815 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A]);
1816
1817 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1818 "deltaSwingTableIdx_TDOWN_B[%d] = %d\n",
1819 delta, delta_swing_table_idx_tdown_b[delta]);
1820
1821 rtldm->delta_power_index_last[RF90_PATH_B] =
1822 rtldm->delta_power_index[RF90_PATH_B];
1823 rtldm->delta_power_index[RF90_PATH_B] =
1824 -1 * delta_swing_table_idx_tdown_b[delta];
1825
1826 rtldm->absolute_ofdm_swing_idx[RF90_PATH_B] =
1827 -1 * delta_swing_table_idx_tdown_b[delta];
1828 /*Record delta swing for mix mode power tracking*/
1829
1830 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1831 "******Temp is lower and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n",
1832 rtldm->absolute_ofdm_swing_idx[RF90_PATH_B]);
1833 }
1834
1835 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++) {
1836 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1837 "============================= [Path-%c]Calculating PowerIndexOffset =============================\n",
1838 (p == RF90_PATH_A ? 'A' : 'B'));
1839
1840 if (rtldm->delta_power_index[p] ==
1841 rtldm->delta_power_index_last[p])
1842 /*If Thermal value changes but lookup
1843 table value still the same*/
1844 rtldm->power_index_offset[p] = 0;
1845 else
1846 rtldm->power_index_offset[p] =
1847 rtldm->delta_power_index[p] -
1848 rtldm->delta_power_index_last[p];
1849 /* Power Index Diff between 2
1850 * times Power Tracking
1851 */
1852 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1853 "[Path-%c] PowerIndexOffset(%d) =DeltaPowerIndex(%d) -DeltaPowerIndexLast(%d)\n",
1854 (p == RF90_PATH_A ? 'A' : 'B'),
1855 rtldm->power_index_offset[p],
1856 rtldm->delta_power_index[p] ,
1857 rtldm->delta_power_index_last[p]);
1858
1859 rtldm->ofdm_index[p] =
1860 rtldm->swing_idx_ofdm_base[p] +
1861 rtldm->power_index_offset[p];
1862 rtldm->cck_index =
1863 rtldm->swing_idx_cck_base +
1864 rtldm->power_index_offset[p];
1865
1866 rtldm->swing_idx_cck = rtldm->cck_index;
1867 rtldm->swing_idx_ofdm[p] = rtldm->ofdm_index[p];
1868
1869 /****Print BB Swing Base and Index Offset */
1870
1871 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1872 "The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
1873 rtldm->swing_idx_cck,
1874 rtldm->swing_idx_cck_base,
1875 rtldm->power_index_offset[p]);
1876 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1877 "The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
1878 rtldm->swing_idx_ofdm[p],
1879 (p == RF90_PATH_A ? 'A' : 'B'),
1880 rtldm->swing_idx_ofdm_base[p],
1881 rtldm->power_index_offset[p]);
1882
1883 /*7.1 Handle boundary conditions of index.*/
1884
1885 if (rtldm->ofdm_index[p] > TXSCALE_TABLE_SIZE - 1)
1886 rtldm->ofdm_index[p] = TXSCALE_TABLE_SIZE - 1;
1887 else if (rtldm->ofdm_index[p] < ofdm_min_index)
1888 rtldm->ofdm_index[p] = ofdm_min_index;
1889 }
1890 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1891 "\n\n====================================================================================\n");
1892 if (rtldm->cck_index > TXSCALE_TABLE_SIZE - 1)
1893 rtldm->cck_index = TXSCALE_TABLE_SIZE - 1;
1894 else if (rtldm->cck_index < 0)
1895 rtldm->cck_index = 0;
1896 } else {
1897 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1898 "The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
1899 rtldm->txpower_track_control,
1900 thermal_value,
1901 rtldm->thermalvalue);
1902
1903 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1904 rtldm->power_index_offset[p] = 0;
1905 }
1906 /*Print Swing base & current*/
1907 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1908 "TxPowerTracking: [CCK] Swing Current Index: %d,Swing Base Index: %d\n",
1909 rtldm->cck_index, rtldm->swing_idx_cck_base);
1910 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++) {
1911 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1912 "TxPowerTracking: [OFDM] Swing Current Index: %d,Swing Base Index[%c]: %d\n",
1913 rtldm->ofdm_index[p],
1914 (p == RF90_PATH_A ? 'A' : 'B'),
1915 rtldm->swing_idx_ofdm_base[p]);
1916 }
1917
1918 if ((rtldm->power_index_offset[RF90_PATH_A] != 0 ||
1919 rtldm->power_index_offset[RF90_PATH_B] != 0) &&
1920 rtldm->txpower_track_control) {
1921 /*7.2 Configure the Swing Table to adjust Tx Power.
1922 *Always TRUE after Tx Power is adjusted by power tracking.
1923 *
1924 *2012/04/23 MH According to Luke's suggestion,
1925 *we can not write BB digital
1926 *to increase TX power. Otherwise, EVM will be bad.
1927 *
1928 *2012/04/25 MH Add for tx power tracking to set
1929 *tx power in tx agc for 88E.
1930 */
1931 if (thermal_value > rtldm->thermalvalue) {
1932 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1933 "Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d,EFUSE_t: %d, Last_t: %d\n",
1934 rtldm->power_index_offset[RF90_PATH_A],
1935 delta, thermal_value,
1936 rtlefuse->eeprom_thermalmeter,
1937 rtldm->thermalvalue);
1938
1939 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1940 "Temperature Increasing(B): delta_pi: %d ,delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
1941 rtldm->power_index_offset[RF90_PATH_B],
1942 delta, thermal_value,
1943 rtlefuse->eeprom_thermalmeter,
1944 rtldm->thermalvalue);
1945 } else if (thermal_value < rtldm->thermalvalue) { /*Low temperature*/
1946 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1947 "Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
1948 rtldm->power_index_offset[RF90_PATH_A],
1949 delta, thermal_value,
1950 rtlefuse->eeprom_thermalmeter,
1951 rtldm->thermalvalue);
1952
1953 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1954 "Temperature Decreasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
1955 rtldm->power_index_offset[RF90_PATH_B],
1956 delta, thermal_value,
1957 rtlefuse->eeprom_thermalmeter,
1958 rtldm->thermalvalue);
1959 }
1960
1961 if (thermal_value > rtlefuse->eeprom_thermalmeter) {
1962 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1963 "Temperature(%d) higher than PG value(%d)\n",
1964 thermal_value, rtlefuse->eeprom_thermalmeter);
1965
1966 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1967 "**********Enter POWER Tracking MIX_MODE**********\n");
1968 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1969 rtl8812ae_dm_txpwr_track_set_pwr(hw, MIX_MODE,
1970 p, 0);
1971 } else {
1972 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1973 "Temperature(%d) lower than PG value(%d)\n",
1974 thermal_value, rtlefuse->eeprom_thermalmeter);
1975
1976 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1977 "**********Enter POWER Tracking MIX_MODE**********\n");
1978 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1979 rtl8812ae_dm_txpwr_track_set_pwr(hw, MIX_MODE,
1980 p, index_for_channel);
1981 }
1982 /*Record last time Power Tracking result as base.*/
1983 rtldm->swing_idx_cck_base = rtldm->swing_idx_cck;
1984 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1985 rtldm->swing_idx_ofdm_base[p] =
1986 rtldm->swing_idx_ofdm[p];
1987
1988 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1989 "pDM_Odm->RFCalibrateInfo.ThermalValue =%d ThermalValue= %d\n",
1990 rtldm->thermalvalue, thermal_value);
1991 /*Record last Power Tracking Thermal Value*/
1992 rtldm->thermalvalue = thermal_value;
1993 }
1994 /*Delta temperature is equal to or larger than
1995 20 centigrade (When threshold is 8).*/
1996 if (delta_iqk >= IQK_THRESHOLD)
1997 rtl8812ae_do_iqk(hw, delta_iqk, thermal_value, 8);
1998
1999 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2000 "<===rtl8812ae_dm_txpower_tracking_callback_thermalmeter\n");
2001}
2002
2003static void rtl8821ae_get_delta_swing_table(struct ieee80211_hw *hw, u8 **up_a,
2004 u8 **down_a, u8 **up_b, u8 **down_b)
2005{
2006 struct rtl_priv *rtlpriv = rtl_priv(hw);
2007 struct rtl_phy *rtlphy = &rtlpriv->phy;
2008 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2009 u8 channel = rtlphy->current_channel;
2010 u8 rate = rtldm->tx_rate;
2011
2012 if (1 <= channel && channel <= 14) {
2013 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) {
2014 *up_a = rtl8821ae_delta_swing_table_idx_24gccka_p;
2015 *down_a = rtl8821ae_delta_swing_table_idx_24gccka_n;
2016 *up_b = rtl8821ae_delta_swing_table_idx_24gcckb_p;
2017 *down_b = rtl8821ae_delta_swing_table_idx_24gcckb_n;
2018 } else {
2019 *up_a = rtl8821ae_delta_swing_table_idx_24ga_p;
2020 *down_a = rtl8821ae_delta_swing_table_idx_24ga_n;
2021 *up_b = rtl8821ae_delta_swing_table_idx_24gb_p;
2022 *down_b = rtl8821ae_delta_swing_table_idx_24gb_n;
2023 }
2024 } else if (36 <= channel && channel <= 64) {
2025 *up_a = rtl8821ae_delta_swing_table_idx_5ga_p[0];
2026 *down_a = rtl8821ae_delta_swing_table_idx_5ga_n[0];
2027 *up_b = rtl8821ae_delta_swing_table_idx_5gb_p[0];
2028 *down_b = rtl8821ae_delta_swing_table_idx_5gb_n[0];
2029 } else if (100 <= channel && channel <= 140) {
2030 *up_a = rtl8821ae_delta_swing_table_idx_5ga_p[1];
2031 *down_a = rtl8821ae_delta_swing_table_idx_5ga_n[1];
2032 *up_b = rtl8821ae_delta_swing_table_idx_5gb_p[1];
2033 *down_b = rtl8821ae_delta_swing_table_idx_5gb_n[1];
2034 } else if (149 <= channel && channel <= 173) {
2035 *up_a = rtl8821ae_delta_swing_table_idx_5ga_p[2];
2036 *down_a = rtl8821ae_delta_swing_table_idx_5ga_n[2];
2037 *up_b = rtl8821ae_delta_swing_table_idx_5gb_p[2];
2038 *down_b = rtl8821ae_delta_swing_table_idx_5gb_n[2];
2039 } else {
2040 *up_a = (u8 *)rtl8818e_delta_swing_table_idx_24gb_p;
2041 *down_a = (u8 *)rtl8818e_delta_swing_table_idx_24gb_n;
2042 *up_b = (u8 *)rtl8818e_delta_swing_table_idx_24gb_p;
2043 *down_b = (u8 *)rtl8818e_delta_swing_table_idx_24gb_n;
2044 }
2045 return;
2046}
2047
2048/*-----------------------------------------------------------------------------
2049 * Function: odm_TxPwrTrackSetPwr88E()
2050 *
2051 * Overview: 88E change all channel tx power accordign to flag.
2052 * OFDM & CCK are all different.
2053 *
2054 * Input: NONE
2055 *
2056 * Output: NONE
2057 *
2058 * Return: NONE
2059 *
2060 * Revised History:
2061 * When Who Remark
2062 * 04/23/2012 MHC Create Version 0.
2063 *
2064 *---------------------------------------------------------------------------
2065 */
2066void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
2067 enum pwr_track_control_method method,
2068 u8 rf_path, u8 channel_mapped_index)
2069{
2070 struct rtl_priv *rtlpriv = rtl_priv(hw);
2071 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2072 struct rtl_phy *rtlphy = &rtlpriv->phy;
2073 u32 final_swing_idx[1];
2074 u8 pwr_tracking_limit = 26; /*+1.0dB*/
2075 u8 tx_rate = 0xFF;
2076 char final_ofdm_swing_index = 0;
2077
2078 if (rtldm->tx_rate != 0xFF)
2079 tx_rate = rtl8821ae_hw_rate_to_mrate(hw, rtldm->tx_rate);
2080
2081 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2082 "===>rtl8812ae_dm_txpwr_track_set_pwr\n");
2083
2084 if (tx_rate != 0xFF) { /* Mimic Modify High Rate BBSwing Limit.*/
2085 /*CCK*/
2086 if ((tx_rate >= MGN_1M) && (tx_rate <= MGN_11M))
2087 pwr_tracking_limit = 32; /*+4dB*/
2088 /*OFDM*/
2089 else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
2090 pwr_tracking_limit = 30; /*+3dB*/
2091 else if (tx_rate == MGN_54M)
2092 pwr_tracking_limit = 28; /*+2dB*/
2093 /*HT*/
2094 /*QPSK/BPSK*/
2095 else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2))
2096 pwr_tracking_limit = 34; /*+5dB*/
2097 /*16QAM*/
2098 else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4))
2099 pwr_tracking_limit = 30; /*+3dB*/
2100 /*64QAM*/
2101 else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7))
2102 pwr_tracking_limit = 28; /*+2dB*/
2103 /*2 VHT*/
2104 /*QPSK/BPSK*/
2105 else if ((tx_rate >= MGN_VHT1SS_MCS0) &&
2106 (tx_rate <= MGN_VHT1SS_MCS2))
2107 pwr_tracking_limit = 34; /*+5dB*/
2108 /*16QAM*/
2109 else if ((tx_rate >= MGN_VHT1SS_MCS3) &&
2110 (tx_rate <= MGN_VHT1SS_MCS4))
2111 pwr_tracking_limit = 30; /*+3dB*/
2112 /*64QAM*/
2113 else if ((tx_rate >= MGN_VHT1SS_MCS5) &&
2114 (tx_rate <= MGN_VHT1SS_MCS6))
2115 pwr_tracking_limit = 28; /*+2dB*/
2116 else if (tx_rate == MGN_VHT1SS_MCS7) /*64QAM*/
2117 pwr_tracking_limit = 26; /*+1dB*/
2118 else if (tx_rate == MGN_VHT1SS_MCS8) /*256QAM*/
2119 pwr_tracking_limit = 24; /*+0dB*/
2120 else if (tx_rate == MGN_VHT1SS_MCS9) /*256QAM*/
2121 pwr_tracking_limit = 22; /*-1dB*/
2122 else
2123 pwr_tracking_limit = 24;
2124 }
2125 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2126 "TxRate=0x%x, PwrTrackingLimit=%d\n",
2127 tx_rate, pwr_tracking_limit);
2128
2129 if (method == BBSWING) {
2130 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2131 "===>rtl8812ae_dm_txpwr_track_set_pwr\n");
2132 if (rf_path == RF90_PATH_A) {
2133 final_swing_idx[RF90_PATH_A] =
2134 (rtldm->ofdm_index[RF90_PATH_A] >
2135 pwr_tracking_limit) ?
2136 pwr_tracking_limit :
2137 rtldm->ofdm_index[RF90_PATH_A];
2138 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2139 "pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d,pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n",
2140 rtldm->ofdm_index[RF90_PATH_A],
2141 final_swing_idx[RF90_PATH_A]);
2142
2143 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
2144 txscaling_tbl[final_swing_idx[RF90_PATH_A]]);
2145 }
2146 } else if (method == MIX_MODE) {
2147 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2148 "pDM_Odm->DefaultOfdmIndex=%d,pDM_Odm->Aboslute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
2149 rtldm->default_ofdm_index,
2150 rtldm->absolute_ofdm_swing_idx[rf_path],
2151 rf_path);
2152
2153 final_ofdm_swing_index =
2154 rtldm->default_ofdm_index +
2155 rtldm->absolute_ofdm_swing_idx[rf_path];
2156 /*BBSwing higher then Limit*/
2157 if (rf_path == RF90_PATH_A) {
2158 if (final_ofdm_swing_index > pwr_tracking_limit) {
2159 rtldm->remnant_cck_idx =
2160 final_ofdm_swing_index -
2161 pwr_tracking_limit;
2162 /* CCK Follow the same compensate value as Path A*/
2163 rtldm->remnant_ofdm_swing_idx[rf_path] =
2164 final_ofdm_swing_index -
2165 pwr_tracking_limit;
2166
2167 rtl_set_bbreg(hw, RA_TXSCALE,
2168 0xFFE00000,
2169 txscaling_tbl[pwr_tracking_limit]);
2170
2171 rtldm->modify_txagc_flag_path_a = true;
2172
2173 /*Set TxAGC Page C{};*/
2174 rtl8821ae_phy_set_txpower_level_by_path(hw,
2175 rtlphy->current_channel,
2176 RF90_PATH_A);
2177
2178 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2179 " ******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n",
2180 pwr_tracking_limit,
2181 rtldm->remnant_ofdm_swing_idx[rf_path]);
2182 } else if (final_ofdm_swing_index < 0) {
2183 rtldm->remnant_cck_idx = final_ofdm_swing_index;
2184 /* CCK Follow the same compensate value as Path A*/
2185 rtldm->remnant_ofdm_swing_idx[rf_path] =
2186 final_ofdm_swing_index;
2187
2188 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
2189 txscaling_tbl[0]);
2190
2191 rtldm->modify_txagc_flag_path_a = true;
2192
2193 /*Set TxAGC Page C{};*/
2194 rtl8821ae_phy_set_txpower_level_by_path(hw,
2195 rtlphy->current_channel, RF90_PATH_A);
2196
2197 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2198 "******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n",
2199 rtldm->remnant_ofdm_swing_idx[rf_path]);
2200 } else {
2201 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
2202 txscaling_tbl[(u8)final_ofdm_swing_index]);
2203
2204 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2205 "******Path_A Compensate with BBSwing ,Final_OFDM_Swing_Index = %d\n",
2206 final_ofdm_swing_index);
2207 /*If TxAGC has changed, reset TxAGC again*/
2208 if (rtldm->modify_txagc_flag_path_a) {
2209 rtldm->remnant_cck_idx = 0;
2210 rtldm->remnant_ofdm_swing_idx[rf_path] = 0;
2211
2212 /*Set TxAGC Page C{};*/
2213 rtl8821ae_phy_set_txpower_level_by_path(hw,
2214 rtlphy->current_channel, RF90_PATH_A);
2215
2216 rtldm->modify_txagc_flag_path_a = false;
2217
2218 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
2219 DBG_LOUD,
2220 "******Path_A pDM_Odm->Modify_TxAGC_Flag= FALSE\n");
2221 }
2222 }
2223 }
2224 } else {
2225 return;
2226 }
2227}
2228
2229void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(
2230 struct ieee80211_hw *hw)
2231{
2232 struct rtl_priv *rtlpriv = rtl_priv(hw);
2233 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2234 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2235 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2236 struct rtl_phy *rtlphy = &rtlpriv->phy;
2237
2238 u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;
2239 u8 thermal_value_avg_count = 0;
2240 u32 thermal_value_avg = 0;
2241
2242 u8 ofdm_min_index = 6; /*OFDM BB Swing should be less than +3.0dB */
2243 /* GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
2244 u8 index_for_channel = 0;
2245
2246 /* 1. The following TWO tables decide the final
2247 * index of OFDM/CCK swing table.
2248 */
2249 u8 *delta_swing_table_idx_tup_a;
2250 u8 *delta_swing_table_idx_tdown_a;
2251 u8 *delta_swing_table_idx_tup_b;
2252 u8 *delta_swing_table_idx_tdown_b;
2253
2254 /*2. Initilization ( 7 steps in total )*/
2255 rtl8821ae_get_delta_swing_table(hw, (u8 **)&delta_swing_table_idx_tup_a,
2256 (u8 **)&delta_swing_table_idx_tdown_a,
2257 (u8 **)&delta_swing_table_idx_tup_b,
2258 (u8 **)&delta_swing_table_idx_tdown_b);
2259
2260 rtldm->txpower_trackinginit = true;
2261
2262 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2263 "===>rtl8812ae_dm_txpower_tracking_callback_thermalmeter,\n pDM_Odm->BbSwingIdxCckBase: %d,pDM_Odm->BbSwingIdxOfdmBase[A]:%d, pDM_Odm->DefaultOfdmIndex: %d\n",
2264 rtldm->swing_idx_cck_base,
2265 rtldm->swing_idx_ofdm_base[RF90_PATH_A],
2266 rtldm->default_ofdm_index);
2267 /*0x42: RF Reg[15:10] 88E*/
2268 thermal_value = (u8)rtl_get_rfreg(hw,
2269 RF90_PATH_A, RF_T_METER_8812A, 0xfc00);
2270 if (!rtldm->txpower_track_control ||
2271 rtlefuse->eeprom_thermalmeter == 0 ||
2272 rtlefuse->eeprom_thermalmeter == 0xFF)
2273 return;
2274
2275 /* 3. Initialize ThermalValues of RFCalibrateInfo*/
2276
2277 if (rtlhal->reloadtxpowerindex) {
2278 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2279 "reload ofdm index for band switch\n");
2280 }
2281
2282 /*4. Calculate average thermal meter*/
2283 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermal_value;
2284 rtldm->thermalvalue_avg_index++;
2285 if (rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_8812A)
2286 /*Average times = c.AverageThermalNum*/
2287 rtldm->thermalvalue_avg_index = 0;
2288
2289 for (i = 0; i < AVG_THERMAL_NUM_8812A; i++) {
2290 if (rtldm->thermalvalue_avg[i]) {
2291 thermal_value_avg += rtldm->thermalvalue_avg[i];
2292 thermal_value_avg_count++;
2293 }
2294 }
2295 /*Calculate Average ThermalValue after average enough times*/
2296 if (thermal_value_avg_count) {
2297 thermal_value = (u8)(thermal_value_avg /
2298 thermal_value_avg_count);
2299 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2300 "AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n",
2301 thermal_value, rtlefuse->eeprom_thermalmeter);
2302 }
2303
2304 /*5. Calculate delta, delta_LCK, delta_IQK.
2305 *"delta" here is used to determine whether
2306 * thermal value changes or not.
2307 */
2308 delta = (thermal_value > rtldm->thermalvalue) ?
2309 (thermal_value - rtldm->thermalvalue) :
2310 (rtldm->thermalvalue - thermal_value);
2311 delta_lck = (thermal_value > rtldm->thermalvalue_lck) ?
2312 (thermal_value - rtldm->thermalvalue_lck) :
2313 (rtldm->thermalvalue_lck - thermal_value);
2314 delta_iqk = (thermal_value > rtldm->thermalvalue_iqk) ?
2315 (thermal_value - rtldm->thermalvalue_iqk) :
2316 (rtldm->thermalvalue_iqk - thermal_value);
2317
2318 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2319 "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
2320 delta, delta_lck, delta_iqk);
2321
2322 /* 6. If necessary, do LCK. */
2323 /*Delta temperature is equal to or larger than 20 centigrade.*/
2324 if (delta_lck >= IQK_THRESHOLD) {
2325 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2326 "delta_LCK(%d) >= Threshold_IQK(%d)\n",
2327 delta_lck, IQK_THRESHOLD);
2328 rtldm->thermalvalue_lck = thermal_value;
2329 rtl8821ae_phy_lc_calibrate(hw);
2330 }
2331
2332 /*7. If necessary, move the index of swing table to adjust Tx power.*/
2333
2334 if (delta > 0 && rtldm->txpower_track_control) {
2335 /*"delta" here is used to record the
2336 * absolute value of differrence.
2337 */
2338 delta = thermal_value > rtlefuse->eeprom_thermalmeter ?
2339 (thermal_value - rtlefuse->eeprom_thermalmeter) :
2340 (rtlefuse->eeprom_thermalmeter - thermal_value);
2341
2342 if (delta >= TXSCALE_TABLE_SIZE)
2343 delta = TXSCALE_TABLE_SIZE - 1;
2344
2345 /*7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
2346
2347 if (thermal_value > rtlefuse->eeprom_thermalmeter) {
2348 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2349 "delta_swing_table_idx_tup_a[%d] = %d\n",
2350 delta, delta_swing_table_idx_tup_a[delta]);
2351 rtldm->delta_power_index_last[RF90_PATH_A] =
2352 rtldm->delta_power_index[RF90_PATH_A];
2353 rtldm->delta_power_index[RF90_PATH_A] =
2354 delta_swing_table_idx_tup_a[delta];
2355
2356 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A] =
2357 delta_swing_table_idx_tup_a[delta];
2358 /*Record delta swing for mix mode power tracking*/
2359
2360 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2361 "******Temp is higher and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
2362 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A]);
2363 } else {
2364 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2365 "delta_swing_table_idx_tdown_a[%d] = %d\n",
2366 delta, delta_swing_table_idx_tdown_a[delta]);
2367
2368 rtldm->delta_power_index_last[RF90_PATH_A] =
2369 rtldm->delta_power_index[RF90_PATH_A];
2370 rtldm->delta_power_index[RF90_PATH_A] =
2371 -1 * delta_swing_table_idx_tdown_a[delta];
2372
2373 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A] =
2374 -1 * delta_swing_table_idx_tdown_a[delta];
2375 /* Record delta swing for mix mode power tracking*/
2376 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2377 "******Temp is lower and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
2378 rtldm->absolute_ofdm_swing_idx[RF90_PATH_A]);
2379 }
2380
2381 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++) {
2382 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2383 "\n\n================================ [Path-%c]Calculating PowerIndexOffset ================================\n",
2384 (p == RF90_PATH_A ? 'A' : 'B'));
2385 /*If Thermal value changes but lookup table value
2386 * still the same
2387 */
2388 if (rtldm->delta_power_index[p] ==
2389 rtldm->delta_power_index_last[p])
2390
2391 rtldm->power_index_offset[p] = 0;
2392 else
2393 rtldm->power_index_offset[p] =
2394 rtldm->delta_power_index[p] -
2395 rtldm->delta_power_index_last[p];
2396 /*Power Index Diff between 2 times Power Tracking*/
2397
2398 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2399 "[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
2400 (p == RF90_PATH_A ? 'A' : 'B'),
2401 rtldm->power_index_offset[p],
2402 rtldm->delta_power_index[p] ,
2403 rtldm->delta_power_index_last[p]);
2404
2405 rtldm->ofdm_index[p] =
2406 rtldm->swing_idx_ofdm_base[p] +
2407 rtldm->power_index_offset[p];
2408 rtldm->cck_index =
2409 rtldm->swing_idx_cck_base +
2410 rtldm->power_index_offset[p];
2411
2412 rtldm->swing_idx_cck = rtldm->cck_index;
2413 rtldm->swing_idx_ofdm[p] = rtldm->ofdm_index[p];
2414
2415 /*********Print BB Swing Base and Index Offset********/
2416
2417 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2418 "The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
2419 rtldm->swing_idx_cck,
2420 rtldm->swing_idx_cck_base,
2421 rtldm->power_index_offset[p]);
2422 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2423 "The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
2424 rtldm->swing_idx_ofdm[p],
2425 (p == RF90_PATH_A ? 'A' : 'B'),
2426 rtldm->swing_idx_ofdm_base[p],
2427 rtldm->power_index_offset[p]);
2428
2429 /*7.1 Handle boundary conditions of index.*/
2430
2431 if (rtldm->ofdm_index[p] > TXSCALE_TABLE_SIZE - 1)
2432 rtldm->ofdm_index[p] = TXSCALE_TABLE_SIZE - 1;
2433 else if (rtldm->ofdm_index[p] < ofdm_min_index)
2434 rtldm->ofdm_index[p] = ofdm_min_index;
2435 }
2436 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2437 "\n\n========================================================================================================\n");
2438 if (rtldm->cck_index > TXSCALE_TABLE_SIZE - 1)
2439 rtldm->cck_index = TXSCALE_TABLE_SIZE - 1;
2440 else if (rtldm->cck_index < 0)
2441 rtldm->cck_index = 0;
2442 } else {
2443 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2444 "The thermal meter is unchanged or TxPowerTracking OFF(%d):ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
2445 rtldm->txpower_track_control,
2446 thermal_value,
2447 rtldm->thermalvalue);
2448
2449 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2450 rtldm->power_index_offset[p] = 0;
2451 }
2452 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2453 "TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
2454 /*Print Swing base & current*/
2455 rtldm->cck_index, rtldm->swing_idx_cck_base);
2456 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++) {
2457 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2458 "TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
2459 rtldm->ofdm_index[p],
2460 (p == RF90_PATH_A ? 'A' : 'B'),
2461 rtldm->swing_idx_ofdm_base[p]);
2462 }
2463
2464 if ((rtldm->power_index_offset[RF90_PATH_A] != 0 ||
2465 rtldm->power_index_offset[RF90_PATH_B] != 0) &&
2466 rtldm->txpower_track_control) {
2467 /*7.2 Configure the Swing Table to adjust Tx Power.*/
2468 /*Always TRUE after Tx Power is adjusted by power tracking.*/
2469 /*
2470 * 2012/04/23 MH According to Luke's suggestion,
2471 * we can not write BB digital
2472 * to increase TX power. Otherwise, EVM will be bad.
2473 *
2474 * 2012/04/25 MH Add for tx power tracking to
2475 * set tx power in tx agc for 88E.
2476 */
2477 if (thermal_value > rtldm->thermalvalue) {
2478 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2479 "Temperature Increasing(A): delta_pi: %d , delta_t: %d,Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
2480 rtldm->power_index_offset[RF90_PATH_A],
2481 delta, thermal_value,
2482 rtlefuse->eeprom_thermalmeter,
2483 rtldm->thermalvalue);
2484 } else if (thermal_value < rtldm->thermalvalue) { /*Low temperature*/
2485 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2486 "Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
2487 rtldm->power_index_offset[RF90_PATH_A],
2488 delta, thermal_value,
2489 rtlefuse->eeprom_thermalmeter,
2490 rtldm->thermalvalue);
2491 }
2492
2493 if (thermal_value > rtlefuse->eeprom_thermalmeter) {
2494 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2495 "Temperature(%d) higher than PG value(%d)\n",
2496 thermal_value, rtlefuse->eeprom_thermalmeter);
2497
2498 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2499 "****Enter POWER Tracking MIX_MODE****\n");
2500 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2501 rtl8821ae_dm_txpwr_track_set_pwr(hw,
2502 MIX_MODE, p, index_for_channel);
2503 } else {
2504 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2505 "Temperature(%d) lower than PG value(%d)\n",
2506 thermal_value, rtlefuse->eeprom_thermalmeter);
2507
2508 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2509 "*****Enter POWER Tracking MIX_MODE*****\n");
2510 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2511 rtl8812ae_dm_txpwr_track_set_pwr(hw,
2512 MIX_MODE, p, index_for_channel);
2513 }
2514 /*Record last time Power Tracking result as base.*/
2515 rtldm->swing_idx_cck_base = rtldm->swing_idx_cck;
2516 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2517 rtldm->swing_idx_ofdm_base[p] = rtldm->swing_idx_ofdm[p];
2518
2519 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2520 "pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n",
2521 rtldm->thermalvalue, thermal_value);
2522 /*Record last Power Tracking Thermal Value*/
2523 rtldm->thermalvalue = thermal_value;
2524 }
2525 /* Delta temperature is equal to or larger than
2526 * 20 centigrade (When threshold is 8).
2527 */
2528 if (delta_iqk >= IQK_THRESHOLD) {
2529 if (!rtlphy->lck_inprogress) {
2530 spin_lock(&rtlpriv->locks.iqk_lock);
2531 rtlphy->lck_inprogress = true;
2532 spin_unlock(&rtlpriv->locks.iqk_lock);
2533
2534 rtl8821ae_do_iqk(hw, delta_iqk, thermal_value, 8);
2535
2536 spin_lock(&rtlpriv->locks.iqk_lock);
2537 rtlphy->lck_inprogress = false;
2538 spin_unlock(&rtlpriv->locks.iqk_lock);
2539 }
2540 }
2541
2542 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2543 "<===rtl8812ae_dm_txpower_tracking_callback_thermalmeter\n");
2544}
2545
2546void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw)
2547{
2548 struct rtl_priv *rtlpriv = rtl_priv(hw);
2549 static u8 tm_trigger;
2550
2551 if (!tm_trigger) {
2552 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER_88E, BIT(17)|BIT(16),
2553 0x03);
2554 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2555 "Trigger 8821ae Thermal Meter!!\n");
2556 tm_trigger = 1;
2557 return;
2558 } else {
2559 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2560 "Schedule TxPowerTracking !!\n");
2561
2562 rtl8821ae_dm_txpower_tracking_callback_thermalmeter(hw);
2563 tm_trigger = 0;
2564 }
2565}
2566
2567static void rtl8821ae_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
2568{
2569 struct rtl_priv *rtlpriv = rtl_priv(hw);
2570 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2571 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2572 struct rate_adaptive *p_ra = &rtlpriv->ra;
2573 u32 low_rssithresh_for_ra = p_ra->low2high_rssi_thresh_for_ra40m;
2574 u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
2575 u8 go_up_gap = 5;
2576 struct ieee80211_sta *sta = NULL;
2577
2578 if (is_hal_stop(rtlhal)) {
2579 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
2580 "driver is going to unload\n");
2581 return;
2582 }
2583
2584 if (!rtlpriv->dm.useramask) {
2585 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
2586 "driver does not control rate adaptive mask\n");
2587 return;
2588 }
2589
2590 if (mac->link_state == MAC80211_LINKED &&
2591 mac->opmode == NL80211_IFTYPE_STATION) {
2592 switch (p_ra->pre_ratr_state) {
2593 case DM_RATR_STA_MIDDLE:
2594 high_rssithresh_for_ra += go_up_gap;
2595 break;
2596 case DM_RATR_STA_LOW:
2597 high_rssithresh_for_ra += go_up_gap;
2598 low_rssithresh_for_ra += go_up_gap;
2599 break;
2600 default:
2601 break;
2602 }
2603
2604 if (rtlpriv->dm.undec_sm_pwdb >
2605 (long)high_rssithresh_for_ra)
2606 p_ra->ratr_state = DM_RATR_STA_HIGH;
2607 else if (rtlpriv->dm.undec_sm_pwdb >
2608 (long)low_rssithresh_for_ra)
2609 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
2610 else
2611 p_ra->ratr_state = DM_RATR_STA_LOW;
2612
2613 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
2614 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
2615 "RSSI = %ld\n",
2616 rtlpriv->dm.undec_sm_pwdb);
2617 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
2618 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
2619 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
2620 "PreState = %d, CurState = %d\n",
2621 p_ra->pre_ratr_state, p_ra->ratr_state);
2622
2623 rcu_read_lock();
2624 sta = rtl_find_sta(hw, mac->bssid);
2625 if (sta)
2626 rtlpriv->cfg->ops->update_rate_tbl(hw,
2627 sta, p_ra->ratr_state);
2628 rcu_read_unlock();
2629
2630 p_ra->pre_ratr_state = p_ra->ratr_state;
2631 }
2632 }
2633}
2634
2635static void rtl8821ae_dm_refresh_basic_rate_mask(struct ieee80211_hw *hw)
2636{
2637 struct rtl_priv *rtlpriv = rtl_priv(hw);
2638 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
2639 struct rtl_mac *mac = &rtlpriv->mac80211;
2640 static u8 stage;
2641 u8 cur_stage = 0;
2642 u16 basic_rate = RRSR_1M | RRSR_2M | RRSR_5_5M | RRSR_11M | RRSR_6M;
2643
2644 if (mac->link_state < MAC80211_LINKED)
2645 cur_stage = 0;
2646 else if (dm_digtable->rssi_val_min < 25)
2647 cur_stage = 1;
2648 else if (dm_digtable->rssi_val_min > 30)
2649 cur_stage = 3;
2650 else
2651 cur_stage = 2;
2652
2653 if (cur_stage != stage) {
2654 if (cur_stage == 1) {
2655 basic_rate &= (!(basic_rate ^ mac->basic_rates));
2656 rtlpriv->cfg->ops->set_hw_reg(hw,
2657 HW_VAR_BASIC_RATE, (u8 *)&basic_rate);
2658 } else if (cur_stage == 3 && (stage == 1 || stage == 2)) {
2659 rtlpriv->cfg->ops->set_hw_reg(hw,
2660 HW_VAR_BASIC_RATE, (u8 *)&mac->basic_rates);
2661 }
2662 }
2663 stage = cur_stage;
2664}
2665
2666static void rtl8821ae_dm_edca_choose_traffic_idx(
2667 struct ieee80211_hw *hw, u64 cur_tx_bytes,
2668 u64 cur_rx_bytes, bool b_bias_on_rx,
2669 bool *pb_is_cur_rdl_state)
2670{
2671 struct rtl_priv *rtlpriv = rtl_priv(hw);
2672
2673 if (b_bias_on_rx) {
2674 if (cur_tx_bytes > (cur_rx_bytes*4)) {
2675 *pb_is_cur_rdl_state = false;
2676 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2677 "Uplink Traffic\n ");
2678 } else {
2679 *pb_is_cur_rdl_state = true;
2680 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2681 "Balance Traffic\n");
2682 }
2683 } else {
2684 if (cur_rx_bytes > (cur_tx_bytes*4)) {
2685 *pb_is_cur_rdl_state = true;
2686 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2687 "Downlink Traffic\n");
2688 } else {
2689 *pb_is_cur_rdl_state = false;
2690 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2691 "Balance Traffic\n");
2692 }
2693 }
2694 return;
2695}
2696
2697static void rtl8821ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
2698{
2699 struct rtl_priv *rtlpriv = rtl_priv(hw);
2700 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2701 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2702
2703 /*Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.*/
2704 u64 cur_tx_ok_cnt = 0;
2705 u64 cur_rx_ok_cnt = 0;
2706 u32 edca_be_ul = 0x5ea42b;
2707 u32 edca_be_dl = 0x5ea42b;
2708 u32 edca_be = 0x5ea42b;
2709 u8 iot_peer = 0;
2710 bool *pb_is_cur_rdl_state = NULL;
2711 bool b_last_is_cur_rdl_state = false;
2712 bool b_bias_on_rx = false;
2713 bool b_edca_turbo_on = false;
2714
2715 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2716 "rtl8821ae_dm_check_edca_turbo=====>");
2717 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2718 "Orginial BE PARAM: 0x%x\n",
2719 rtl_read_dword(rtlpriv, DM_REG_EDCA_BE_11N));
2720
2721 if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
2722 rtlpriv->dm.is_any_nonbepkts = true;
2723 rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
2724
2725 /*===============================
2726 * list paramter for different platform
2727 *===============================
2728 */
2729 b_last_is_cur_rdl_state = rtlpriv->dm.is_cur_rdlstate;
2730 pb_is_cur_rdl_state = &rtlpriv->dm.is_cur_rdlstate;
2731
2732 cur_tx_ok_cnt = rtlpriv->stats.txbytesunicast - rtldm->last_tx_ok_cnt;
2733 cur_rx_ok_cnt = rtlpriv->stats.rxbytesunicast - rtldm->last_rx_ok_cnt;
2734
2735 rtldm->last_tx_ok_cnt = rtlpriv->stats.txbytesunicast;
2736 rtldm->last_rx_ok_cnt = rtlpriv->stats.rxbytesunicast;
2737
2738 iot_peer = rtlpriv->mac80211.vendor;
2739 b_bias_on_rx = false;
2740 b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
2741 (!rtlpriv->dm.disable_framebursting)) ?
2742 true : false;
2743
2744 if (rtlpriv->rtlhal.hw_type != HARDWARE_TYPE_RTL8812AE) {
2745 if ((iot_peer == PEER_CISCO) &&
2746 (mac->mode == WIRELESS_MODE_N_24G)) {
2747 edca_be_dl = edca_setting_dl[iot_peer];
2748 edca_be_ul = edca_setting_ul[iot_peer];
2749 }
2750 }
2751
2752 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2753 "bIsAnyNonBEPkts : 0x%x bDisableFrameBursting : 0x%x\n",
2754 rtlpriv->dm.is_any_nonbepkts,
2755 rtlpriv->dm.disable_framebursting);
2756
2757 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2758 "bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",
2759 b_edca_turbo_on, b_bias_on_rx);
2760
2761 if (b_edca_turbo_on) {
2762 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2763 "curTxOkCnt : 0x%llx\n", cur_tx_ok_cnt);
2764 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2765 "curRxOkCnt : 0x%llx\n", cur_rx_ok_cnt);
2766 if (b_bias_on_rx)
2767 rtl8821ae_dm_edca_choose_traffic_idx(hw, cur_tx_ok_cnt,
2768 cur_rx_ok_cnt, true, pb_is_cur_rdl_state);
2769 else
2770 rtl8821ae_dm_edca_choose_traffic_idx(hw, cur_tx_ok_cnt,
2771 cur_rx_ok_cnt, false, pb_is_cur_rdl_state);
2772
2773 edca_be = (*pb_is_cur_rdl_state) ? edca_be_dl : edca_be_ul;
2774
2775 rtl_write_dword(rtlpriv, DM_REG_EDCA_BE_11N, edca_be);
2776
2777 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2778 "EDCA Turbo on: EDCA_BE:0x%x\n", edca_be);
2779
2780 rtlpriv->dm.current_turbo_edca = true;
2781
2782 RT_TRACE(rtlpriv, COMP_TURBO, DBG_LOUD,
2783 "EDCA_BE_DL : 0x%x EDCA_BE_UL : 0x%x EDCA_BE : 0x%x\n",
2784 edca_be_dl, edca_be_ul, edca_be);
2785 } else {
2786 if (rtlpriv->dm.current_turbo_edca) {
2787 u8 tmp = AC0_BE;
2788 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
2789 (u8 *)(&tmp));
2790 }
2791 rtlpriv->dm.current_turbo_edca = false;
2792 }
2793
2794 rtlpriv->dm.is_any_nonbepkts = false;
2795 rtldm->last_tx_ok_cnt = rtlpriv->stats.txbytesunicast;
2796 rtldm->last_rx_ok_cnt = rtlpriv->stats.rxbytesunicast;
2797}
2798
2799static void rtl8821ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
2800{
2801 struct rtl_priv *rtlpriv = rtl_priv(hw);
2802 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
2803 u8 cur_cck_cca_thresh;
2804
2805 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
2806 if (dm_digtable->rssi_val_min > 25) {
2807 cur_cck_cca_thresh = 0xcd;
2808 } else if ((dm_digtable->rssi_val_min <= 25) &&
2809 (dm_digtable->rssi_val_min > 10)) {
2810 cur_cck_cca_thresh = 0x83;
2811 } else {
2812 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
2813 cur_cck_cca_thresh = 0x83;
2814 else
2815 cur_cck_cca_thresh = 0x40;
2816 }
2817 } else {
2818 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
2819 cur_cck_cca_thresh = 0x83;
2820 else
2821 cur_cck_cca_thresh = 0x40;
2822 }
2823
2824 if (dm_digtable->cur_cck_cca_thres != cur_cck_cca_thresh)
2825 rtl_write_byte(rtlpriv, ODM_REG_CCK_CCA_11AC,
2826 cur_cck_cca_thresh);
2827
2828 dm_digtable->pre_cck_cca_thres = dm_digtable->cur_cck_cca_thres;
2829 dm_digtable->cur_cck_cca_thres = cur_cck_cca_thresh;
2830 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
2831 "CCK cca thresh hold =%x\n", dm_digtable->cur_cck_cca_thres);
2832}
2833
2834static void rtl8821ae_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
2835{
2836 struct rtl_priv *rtlpriv = rtl_priv(hw);
2837 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2838 u8 crystal_cap;
2839 u32 packet_count;
2840 int cfo_khz_a, cfo_khz_b, cfo_ave = 0, adjust_xtal = 0;
2841 int cfo_ave_diff;
2842
2843 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
2844 /*1.Enable ATC*/
2845 if (rtldm->atc_status == ATC_STATUS_OFF) {
2846 rtl_set_bbreg(hw, RFC_AREA, BIT(14), ATC_STATUS_ON);
2847 rtldm->atc_status = ATC_STATUS_ON;
2848 }
2849
2850 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "No link!!\n");
2851 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2852 "atc_status = %d\n", rtldm->atc_status);
2853
2854 if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap) {
2855 rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
2856 crystal_cap = rtldm->crystal_cap & 0x3f;
2857 crystal_cap = crystal_cap & 0x3f;
2858 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE)
2859 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL,
2860 0x7ff80000, (crystal_cap |
2861 (crystal_cap << 6)));
2862 else
2863 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL,
2864 0xfff000, (crystal_cap |
2865 (crystal_cap << 6)));
2866 }
2867 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "crystal_cap = 0x%x\n",
2868 rtldm->crystal_cap);
2869 } else{
2870 /*1. Calculate CFO for path-A & path-B*/
2871 cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
2872 cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
2873 packet_count = rtldm->packet_count;
2874
2875 /*2.No new packet*/
2876 if (packet_count == rtldm->packet_count_pre) {
2877 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2878 "packet counter doesn't change\n");
2879 return;
2880 }
2881
2882 rtldm->packet_count_pre = packet_count;
2883 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2884 "packet counter = %d\n",
2885 rtldm->packet_count);
2886
2887 /*3.Average CFO*/
2888 if (rtlpriv->phy.rf_type == RF_1T1R)
2889 cfo_ave = cfo_khz_a;
2890 else
2891 cfo_ave = (cfo_khz_a + cfo_khz_b) >> 1;
2892
2893 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2894 "cfo_khz_a = %dkHz, cfo_khz_b = %dkHz, cfo_ave = %dkHz\n",
2895 cfo_khz_a, cfo_khz_b, cfo_ave);
2896
2897 /*4.Avoid abnormal large CFO*/
2898 cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave) ?
2899 (rtldm->cfo_ave_pre - cfo_ave) :
2900 (cfo_ave - rtldm->cfo_ave_pre);
2901
2902 if (cfo_ave_diff > 20 && rtldm->large_cfo_hit == 0) {
2903 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2904 "first large CFO hit\n");
2905 rtldm->large_cfo_hit = 1;
2906 return;
2907 } else
2908 rtldm->large_cfo_hit = 0;
2909
2910 rtldm->cfo_ave_pre = cfo_ave;
2911
2912 /*CFO tracking by adjusting Xtal cap.*/
2913
2914 /*1.Dynamic Xtal threshold*/
2915 if (cfo_ave >= -rtldm->cfo_threshold &&
2916 cfo_ave <= rtldm->cfo_threshold &&
2917 rtldm->is_freeze == 0) {
2918 if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL) {
2919 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
2920 rtldm->is_freeze = 1;
2921 } else {
2922 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
2923 }
2924 }
2925 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2926 "Dynamic threshold = %d\n",
2927 rtldm->cfo_threshold);
2928
2929 /* 2.Calculate Xtal offset*/
2930 if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
2931 adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
2932 else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) &&
2933 rtlpriv->dm.crystal_cap > 0)
2934 adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
2935 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2936 "Crystal cap = 0x%x, Crystal cap offset = %d\n",
2937 rtldm->crystal_cap, adjust_xtal);
2938
2939 /*3.Adjudt Crystal Cap.*/
2940 if (adjust_xtal != 0) {
2941 rtldm->is_freeze = 0;
2942 rtldm->crystal_cap += adjust_xtal;
2943
2944 if (rtldm->crystal_cap > 0x3f)
2945 rtldm->crystal_cap = 0x3f;
2946 else if (rtldm->crystal_cap < 0)
2947 rtldm->crystal_cap = 0;
2948
2949 crystal_cap = rtldm->crystal_cap & 0x3f;
2950 crystal_cap = crystal_cap & 0x3f;
2951 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE)
2952 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL,
2953 0x7ff80000, (crystal_cap |
2954 (crystal_cap << 6)));
2955 else
2956 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL,
2957 0xfff000, (crystal_cap |
2958 (crystal_cap << 6)));
2959 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
2960 "New crystal cap = 0x%x\n",
2961 rtldm->crystal_cap);
2962 }
2963 }
2964}
2965
2966void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw)
2967{
2968 struct rtl_priv *rtlpriv = rtl_priv(hw);
2969 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2970 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2971 bool fw_current_inpsmode = false;
2972 bool fw_ps_awake = true;
2973
2974 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
2975 (u8 *)(&fw_current_inpsmode));
2976
2977 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
2978 (u8 *)(&fw_ps_awake));
2979
2980 if (ppsc->p2p_ps_info.p2p_ps_mode)
2981 fw_ps_awake = false;
2982
2983 if ((ppsc->rfpwr_state == ERFON) &&
2984 ((!fw_current_inpsmode) && fw_ps_awake) &&
2985 (!ppsc->rfchange_inprogress)) {
2986 rtl8821ae_dm_common_info_self_update(hw);
2987 rtl8821ae_dm_false_alarm_counter_statistics(hw);
2988 rtl8821ae_dm_check_rssi_monitor(hw);
2989 rtl8821ae_dm_dig(hw);
2990 rtl8821ae_dm_cck_packet_detection_thresh(hw);
2991 rtl8821ae_dm_refresh_rate_adaptive_mask(hw);
2992 rtl8821ae_dm_refresh_basic_rate_mask(hw);
2993 rtl8821ae_dm_check_edca_turbo(hw);
2994 rtl8821ae_dm_dynamic_atc_switch(hw);
2995 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2996 rtl8812ae_dm_check_txpower_tracking_thermalmeter(hw);
2997 else
2998 rtl8821ae_dm_check_txpower_tracking_thermalmeter(hw);
2999 rtl8821ae_dm_iq_calibrate(hw);
3000 }
3001
3002 rtlpriv->dm.dbginfo.num_qry_beacon_pkt = 0;
3003 RT_TRACE(rtlpriv, COMP_DIG, DBG_DMESG, "\n");
3004}
3005
3006void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
3007 u8 *pdesc, u32 mac_id)
3008{
3009 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3010 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3011 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
3012 struct fast_ant_training *pfat_table = &rtldm->fat_table;
3013
3014 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8812AE)
3015 return;
3016
3017 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
3018 SET_TX_DESC_TX_ANT(pdesc, pfat_table->antsel_a[mac_id]);
3019}
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/dm.h b/drivers/net/wireless/rtlwifi/rtl8821ae/dm.h
new file mode 100644
index 000000000000..9dd40dd316c1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/dm.h
@@ -0,0 +1,356 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_DM_H__
27#define __RTL8821AE_DM_H__
28
29#define MAIN_ANT 0
30#define AUX_ANT 1
31#define MAIN_ANT_CG_TRX 1
32#define AUX_ANT_CG_TRX 0
33#define MAIN_ANT_CGCS_RX 0
34#define AUX_ANT_CGCS_RX 1
35
36#define TXSCALE_TABLE_SIZE 37
37
38/*RF REG LIST*/
39#define DM_REG_RF_MODE_11N 0x00
40#define DM_REG_RF_0B_11N 0x0B
41#define DM_REG_CHNBW_11N 0x18
42#define DM_REG_T_METER_11N 0x24
43#define DM_REG_RF_25_11N 0x25
44#define DM_REG_RF_26_11N 0x26
45#define DM_REG_RF_27_11N 0x27
46#define DM_REG_RF_2B_11N 0x2B
47#define DM_REG_RF_2C_11N 0x2C
48#define DM_REG_RXRF_A3_11N 0x3C
49#define DM_REG_T_METER_92D_11N 0x42
50#define DM_REG_T_METER_88E_11N 0x42
51
52/*BB REG LIST*/
53/*PAGE 8 */
54#define DM_REG_BB_CTRL_11N 0x800
55#define DM_REG_RF_PIN_11N 0x804
56#define DM_REG_PSD_CTRL_11N 0x808
57#define DM_REG_TX_ANT_CTRL_11N 0x80C
58#define DM_REG_BB_PWR_SAV5_11N 0x818
59#define DM_REG_CCK_RPT_FORMAT_11N 0x824
60#define DM_REG_RX_DEFUALT_A_11N 0x858
61#define DM_REG_RX_DEFUALT_B_11N 0x85A
62#define DM_REG_BB_PWR_SAV3_11N 0x85C
63#define DM_REG_ANTSEL_CTRL_11N 0x860
64#define DM_REG_RX_ANT_CTRL_11N 0x864
65#define DM_REG_PIN_CTRL_11N 0x870
66#define DM_REG_BB_PWR_SAV1_11N 0x874
67#define DM_REG_ANTSEL_PATH_11N 0x878
68#define DM_REG_BB_3WIRE_11N 0x88C
69#define DM_REG_SC_CNT_11N 0x8C4
70#define DM_REG_PSD_DATA_11N 0x8B4
71/*PAGE 9*/
72#define DM_REG_ANT_MAPPING1_11N 0x914
73#define DM_REG_ANT_MAPPING2_11N 0x918
74/*PAGE A*/
75#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
76#define DM_REG_CCK_CCA_11N 0xA0A
77#define DM_REG_CCK_CCA_11AC 0xA0A
78#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
79#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
80#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
81#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
82#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
83#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
84#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
85#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
86#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
87#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
88#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
89#define DM_REG_CCK_FA_RST_11N 0xA2C
90#define DM_REG_CCK_FA_MSB_11N 0xA58
91#define DM_REG_CCK_FA_LSB_11N 0xA5C
92#define DM_REG_CCK_CCA_CNT_11N 0xA60
93#define DM_REG_BB_PWR_SAV4_11N 0xA74
94/*PAGE B */
95#define DM_REG_LNA_SWITCH_11N 0xB2C
96#define DM_REG_PATH_SWITCH_11N 0xB30
97#define DM_REG_RSSI_CTRL_11N 0xB38
98#define DM_REG_CONFIG_ANTA_11N 0xB68
99#define DM_REG_RSSI_BT_11N 0xB9C
100/*PAGE C */
101#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
102#define DM_REG_RX_PATH_11N 0xC04
103#define DM_REG_TRMUX_11N 0xC08
104#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
105#define DM_REG_RXIQI_MATRIX_11N 0xC14
106#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
107#define DM_REG_IGI_A_11N 0xC50
108#define DM_REG_IGI_A_11AC 0xC50
109#define DM_REG_ANTDIV_PARA2_11N 0xC54
110#define DM_REG_IGI_B_11N 0xC58
111#define DM_REG_IGI_B_11AC 0xE50
112#define DM_REG_ANTDIV_PARA3_11N 0xC5C
113#define DM_REG_BB_PWR_SAV2_11N 0xC70
114#define DM_REG_RX_OFF_11N 0xC7C
115#define DM_REG_TXIQK_MATRIXA_11N 0xC80
116#define DM_REG_TXIQK_MATRIXB_11N 0xC88
117#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
118#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
119#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
120#define DM_REG_ANTDIV_PARA1_11N 0xCA4
121#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
122/*PAGE D */
123#define DM_REG_OFDM_FA_RSTD_11N 0xD00
124#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
125#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
126#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
127/*PAGE E */
128#define DM_REG_TXAGC_A_6_18_11N 0xE00
129#define DM_REG_TXAGC_A_24_54_11N 0xE04
130#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
131#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
132#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
133#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
134#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
135#define DM_REG_FPGA0_IQK_11N 0xE28
136#define DM_REG_TXIQK_TONE_A_11N 0xE30
137#define DM_REG_RXIQK_TONE_A_11N 0xE34
138#define DM_REG_TXIQK_PI_A_11N 0xE38
139#define DM_REG_RXIQK_PI_A_11N 0xE3C
140#define DM_REG_TXIQK_11N 0xE40
141#define DM_REG_RXIQK_11N 0xE44
142#define DM_REG_IQK_AGC_PTS_11N 0xE48
143#define DM_REG_IQK_AGC_RSP_11N 0xE4C
144#define DM_REG_BLUETOOTH_11N 0xE6C
145#define DM_REG_RX_WAIT_CCA_11N 0xE70
146#define DM_REG_TX_CCK_RFON_11N 0xE74
147#define DM_REG_TX_CCK_BBON_11N 0xE78
148#define DM_REG_OFDM_RFON_11N 0xE7C
149#define DM_REG_OFDM_BBON_11N 0xE80
150#define DM_REG_TX2RX_11N 0xE84
151#define DM_REG_TX2TX_11N 0xE88
152#define DM_REG_RX_CCK_11N 0xE8C
153#define DM_REG_RX_OFDM_11N 0xED0
154#define DM_REG_RX_WAIT_RIFS_11N 0xED4
155#define DM_REG_RX2RX_11N 0xED8
156#define DM_REG_STANDBY_11N 0xEDC
157#define DM_REG_SLEEP_11N 0xEE0
158#define DM_REG_PMPD_ANAEN_11N 0xEEC
159
160/*MAC REG LIST*/
161#define DM_REG_BB_RST_11N 0x02
162#define DM_REG_ANTSEL_PIN_11N 0x4C
163#define DM_REG_EARLY_MODE_11N 0x4D0
164#define DM_REG_RSSI_MONITOR_11N 0x4FE
165#define DM_REG_EDCA_VO_11N 0x500
166#define DM_REG_EDCA_VI_11N 0x504
167#define DM_REG_EDCA_BE_11N 0x508
168#define DM_REG_EDCA_BK_11N 0x50C
169#define DM_REG_TXPAUSE_11N 0x522
170#define DM_REG_RESP_TX_11N 0x6D8
171#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
172#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
173
174/*DIG Related*/
175#define DM_BIT_IGI_11N 0x0000007F
176#define DM_BIT_IGI_11AC 0xFFFFFFFF
177
178#define HAL_DM_DIG_DISABLE BIT(0)
179#define HAL_DM_HIPWR_DISABLE BIT(1)
180
181#define OFDM_TABLE_LENGTH 43
182#define CCK_TABLE_LENGTH 33
183
184#define OFDM_TABLE_SIZE 37
185#define CCK_TABLE_SIZE 33
186
187#define BW_AUTO_SWITCH_HIGH_LOW 25
188#define BW_AUTO_SWITCH_LOW_HIGH 30
189
190#define DM_DIG_THRESH_HIGH 40
191#define DM_DIG_THRESH_LOW 35
192
193#define DM_FALSEALARM_THRESH_LOW 400
194#define DM_FALSEALARM_THRESH_HIGH 1000
195
196#define DM_DIG_MAX 0x3e
197#define DM_DIG_MIN 0x1e
198
199#define DM_DIG_MAX_AP 0x32
200#define DM_DIG_MIN_AP 0x20
201
202#define DM_DIG_FA_UPPER 0x3e
203#define DM_DIG_FA_LOWER 0x1e
204#define DM_DIG_FA_TH0 200
205#define DM_DIG_FA_TH1 0x300
206#define DM_DIG_FA_TH2 0x400
207
208#define DM_DIG_BACKOFF_MAX 12
209#define DM_DIG_BACKOFF_MIN -4
210#define DM_DIG_BACKOFF_DEFAULT 10
211
212#define RXPATHSELECTION_SS_TH_LOW 30
213#define RXPATHSELECTION_DIFF_TH 18
214
215#define DM_RATR_STA_INIT 0
216#define DM_RATR_STA_HIGH 1
217#define DM_RATR_STA_MIDDLE 2
218#define DM_RATR_STA_LOW 3
219
220#define CTS2SELF_THVAL 30
221#define REGC38_TH 20
222
223#define WAIOTTHVAL 25
224
225#define TXHIGHPWRLEVEL_NORMAL 0
226#define TXHIGHPWRLEVEL_LEVEL1 1
227#define TXHIGHPWRLEVEL_LEVEL2 2
228#define TXHIGHPWRLEVEL_BT1 3
229#define TXHIGHPWRLEVEL_BT2 4
230
231#define DM_TYPE_BYFW 0
232#define DM_TYPE_BYDRIVER 1
233
234#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
235#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
236#define TXPWRTRACK_MAX_IDX 6
237
238/* Dynamic ATC switch */
239#define ATC_STATUS_OFF 0x0 /* enable */
240#define ATC_STATUS_ON 0x1 /* disable */
241#define CFO_THRESHOLD_XTAL 10 /* kHz */
242#define CFO_THRESHOLD_ATC 80 /* kHz */
243
244#define AVG_THERMAL_NUM_8812A 4
245#define TXPWR_TRACK_TABLE_SIZE 30
246#define MAX_PATH_NUM_8812A 2
247#define MAX_PATH_NUM_8821A 1
248
249enum FAT_STATE {
250 FAT_NORMAL_STATE = 0,
251 FAT_TRAINING_STATE = 1,
252};
253
254enum tag_dynamic_init_gain_operation_type_definition {
255 DIG_TYPE_THRESH_HIGH = 0,
256 DIG_TYPE_THRESH_LOW = 1,
257 DIG_TYPE_BACKOFF = 2,
258 DIG_TYPE_RX_GAIN_MIN = 3,
259 DIG_TYPE_RX_GAIN_MAX = 4,
260 DIG_TYPE_ENABLE = 5,
261 DIG_TYPE_DISABLE = 6,
262 DIG_OP_TYPE_MAX
263};
264
265enum tag_cck_packet_detection_threshold_type_definition {
266 CCK_PD_STAGE_LOWRSSI = 0,
267 CCK_PD_STAGE_HIGHRSSI = 1,
268 CCK_FA_STAGE_LOW = 2,
269 CCK_FA_STAGE_HIGH = 3,
270 CCK_PD_STAGE_MAX = 4,
271};
272
273enum dm_1r_cca_e {
274 CCA_1R = 0,
275 CCA_2R = 1,
276 CCA_MAX = 2,
277};
278
279enum dm_rf_e {
280 RF_SAVE = 0,
281 RF_NORMAL = 1,
282 RF_MAX = 2,
283};
284
285enum dm_sw_ant_switch_e {
286 ANS_ANTENNA_B = 1,
287 ANS_ANTENNA_A = 2,
288 ANS_ANTENNA_MAX = 3,
289};
290
291enum dm_dig_ext_port_alg_e {
292 DIG_EXT_PORT_STAGE_0 = 0,
293 DIG_EXT_PORT_STAGE_1 = 1,
294 DIG_EXT_PORT_STAGE_2 = 2,
295 DIG_EXT_PORT_STAGE_3 = 3,
296 DIG_EXT_PORT_STAGE_MAX = 4,
297};
298
299enum dm_dig_connect_e {
300 DIG_STA_DISCONNECT = 0,
301 DIG_STA_CONNECT = 1,
302 DIG_STA_BEFORE_CONNECT = 2,
303 DIG_MULTISTA_DISCONNECT = 3,
304 DIG_MULTISTA_CONNECT = 4,
305 DIG_CONNECT_MAX
306};
307
308enum pwr_track_control_method {
309 BBSWING,
310 TXAGC,
311 MIX_MODE
312};
313
314#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
315#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
316#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
317#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
318#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
319#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
320 ((((struct rtl_priv *)(_priv))->mac80211.opmode == \
321 NL80211_IFTYPE_ADHOC) ? \
322 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \
323 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb))
324
325void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
326 u8 *pdesc, u32 mac_id);
327void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw,
328 u8 antsel_tr_mux, u32 mac_id,
329 u32 rx_pwdb_all);
330void rtl8821ae_dm_fast_antenna_training_callback(unsigned long data);
331void rtl8821ae_dm_init(struct ieee80211_hw *hw);
332void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw);
333void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
334void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw);
335void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
336void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
337void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
338 u8 type, u8 *pdirection,
339 u32 *poutwrite_val);
340void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw);
341void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca);
342void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
343void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
344 enum pwr_track_control_method method,
345 u8 rf_path,
346 u8 channel_mapped_index);
347void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
348 enum pwr_track_control_method method,
349 u8 rf_path, u8 channel_mapped_index);
350
351void rtl8821ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate);
352u8 rtl8821ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate);
353void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
354void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
355
356#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/fw.c b/drivers/net/wireless/rtlwifi/rtl8821ae/fw.c
new file mode 100644
index 000000000000..6f71aaa76db7
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/fw.c
@@ -0,0 +1,1889 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "../base.h"
29#include "reg.h"
30#include "def.h"
31#include "fw.h"
32#include "dm.h"
33
34static void _rtl8821ae_enable_fw_download(struct ieee80211_hw *hw, bool enable)
35{
36 struct rtl_priv *rtlpriv = rtl_priv(hw);
37 u8 tmp;
38
39 if (enable) {
40 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x05);
41
42 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
43 rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
44
45 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
46 } else {
47 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
48 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
49 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
50 }
51}
52
53static void _rtl8821ae_fw_block_write(struct ieee80211_hw *hw,
54 const u8 *buffer, u32 size)
55{
56 struct rtl_priv *rtlpriv = rtl_priv(hw);
57 u32 blocksize = sizeof(u32);
58 u8 *bufferptr = (u8 *)buffer;
59 u32 *pu4byteptr = (u32 *)buffer;
60 u32 i, offset, blockcount, remainsize;
61
62 blockcount = size / blocksize;
63 remainsize = size % blocksize;
64
65 for (i = 0; i < blockcount; i++) {
66 offset = i * blocksize;
67 rtl_write_dword(rtlpriv, (FW_8821AE_START_ADDRESS + offset),
68 *(pu4byteptr + i));
69 }
70
71 if (remainsize) {
72 offset = blockcount * blocksize;
73 bufferptr += offset;
74 for (i = 0; i < remainsize; i++) {
75 rtl_write_byte(rtlpriv, (FW_8821AE_START_ADDRESS +
76 offset + i), *(bufferptr + i));
77 }
78 }
79}
80
81static void _rtl8821ae_fw_page_write(struct ieee80211_hw *hw,
82 u32 page, const u8 *buffer, u32 size)
83{
84 struct rtl_priv *rtlpriv = rtl_priv(hw);
85 u8 value8;
86 u8 u8page = (u8)(page & 0x07);
87
88 value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
89
90 rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
91 _rtl8821ae_fw_block_write(hw, buffer, size);
92}
93
94static void _rtl8821ae_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
95{
96 u32 fwlen = *pfwlen;
97 u8 remain = (u8)(fwlen % 4);
98
99 remain = (remain == 0) ? 0 : (4 - remain);
100
101 while (remain > 0) {
102 pfwbuf[fwlen] = 0;
103 fwlen++;
104 remain--;
105 }
106
107 *pfwlen = fwlen;
108}
109
110static void _rtl8821ae_write_fw(struct ieee80211_hw *hw,
111 enum version_8821ae version,
112 u8 *buffer, u32 size)
113{
114 struct rtl_priv *rtlpriv = rtl_priv(hw);
115 u8 *bufferptr = (u8 *)buffer;
116 u32 pagenums, remainsize;
117 u32 page, offset;
118
119 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size);
120
121 _rtl8821ae_fill_dummy(bufferptr, &size);
122
123 pagenums = size / FW_8821AE_PAGE_SIZE;
124 remainsize = size % FW_8821AE_PAGE_SIZE;
125
126 if (pagenums > 8) {
127 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
128 "Page numbers should not greater then 8\n");
129 }
130
131 for (page = 0; page < pagenums; page++) {
132 offset = page * FW_8821AE_PAGE_SIZE;
133 _rtl8821ae_fw_page_write(hw, page, (bufferptr + offset),
134 FW_8821AE_PAGE_SIZE);
135 }
136
137 if (remainsize) {
138 offset = pagenums * FW_8821AE_PAGE_SIZE;
139 page = pagenums;
140 _rtl8821ae_fw_page_write(hw, page, (bufferptr + offset),
141 remainsize);
142 }
143}
144
145static int _rtl8821ae_fw_free_to_go(struct ieee80211_hw *hw)
146{
147 struct rtl_priv *rtlpriv = rtl_priv(hw);
148 int err = -EIO;
149 u32 counter = 0;
150 u32 value32;
151
152 do {
153 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
154 } while ((counter++ < FW_8821AE_POLLING_TIMEOUT_COUNT) &&
155 (!(value32 & FWDL_CHKSUM_RPT)));
156
157 if (counter >= FW_8821AE_POLLING_TIMEOUT_COUNT) {
158 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
159 "chksum report faill ! REG_MCUFWDL:0x%08x .\n",
160 value32);
161 goto exit;
162 }
163
164 RT_TRACE(rtlpriv, COMP_FW, DBG_EMERG,
165 "Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
166
167 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
168 value32 |= MCUFWDL_RDY;
169 value32 &= ~WINTINI_RDY;
170 rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
171
172 rtl8821ae_firmware_selfreset(hw);
173
174 counter = 0;
175 do {
176 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
177 if (value32 & WINTINI_RDY) {
178 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
179 "Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",
180 value32);
181 err = 0;
182 goto exit;
183 }
184
185 udelay(FW_8821AE_POLLING_DELAY);
186 } while (counter++ < FW_8821AE_POLLING_TIMEOUT_COUNT);
187
188 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
189 "Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n",
190 value32);
191
192exit:
193 return err;
194}
195
196static void _rtl8821ae_wait_for_h2c_cmd_finish(struct rtl_priv *rtlpriv)
197{
198 u8 val;
199 u16 count = 0;
200
201 do {
202 val = rtl_read_byte(rtlpriv, REG_HMETFR);
203 mdelay(1);
204 count++;
205 } while ((val & 0x0F) && (count < 1000));
206}
207
208int rtl8821ae_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
209{
210 struct rtl_priv *rtlpriv = rtl_priv(hw);
211 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
212 struct rtl8821a_firmware_header *pfwheader;
213 u8 *pfwdata;
214 u32 fwsize;
215 int err;
216 bool support_remote_wakeup;
217 enum version_8821ae version = rtlhal->version;
218
219 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
220 (u8 *)(&support_remote_wakeup));
221
222 if (support_remote_wakeup)
223 _rtl8821ae_wait_for_h2c_cmd_finish(rtlpriv);
224
225 if (buse_wake_on_wlan_fw) {
226 if (!rtlhal->wowlan_firmware)
227 return 1;
228
229 pfwheader =
230 (struct rtl8821a_firmware_header *)rtlhal->wowlan_firmware;
231 rtlhal->fw_version = pfwheader->version;
232 rtlhal->fw_subversion = pfwheader->subversion;
233 pfwdata = (u8 *)rtlhal->wowlan_firmware;
234 fwsize = rtlhal->wowlan_fwsize;
235 } else {
236 if (!rtlhal->pfirmware)
237 return 1;
238
239 pfwheader =
240 (struct rtl8821a_firmware_header *)rtlhal->pfirmware;
241 rtlhal->fw_version = pfwheader->version;
242 rtlhal->fw_subversion = pfwheader->subversion;
243 pfwdata = (u8 *)rtlhal->pfirmware;
244 fwsize = rtlhal->fwsize;
245 }
246
247 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
248 "%s Firmware SIZE %d\n",
249 buse_wake_on_wlan_fw ? "Wowlan" : "Normal", fwsize);
250
251 if (IS_FW_HEADER_EXIST_8812(pfwheader) ||
252 IS_FW_HEADER_EXIST_8821(pfwheader)) {
253 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
254 "Firmware Version(%d), Signature(%#x)\n",
255 pfwheader->version, pfwheader->signature);
256
257 pfwdata = pfwdata + sizeof(struct rtl8821a_firmware_header);
258 fwsize = fwsize - sizeof(struct rtl8821a_firmware_header);
259 }
260
261 if (rtlhal->mac_func_enable) {
262 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
263 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
264 rtl8821ae_firmware_selfreset(hw);
265 }
266 }
267 _rtl8821ae_enable_fw_download(hw, true);
268 _rtl8821ae_write_fw(hw, version, pfwdata, fwsize);
269 _rtl8821ae_enable_fw_download(hw, false);
270
271 err = _rtl8821ae_fw_free_to_go(hw);
272 if (err) {
273 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
274 "Firmware is not ready to run!\n");
275 } else {
276 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
277 "Firmware is ready to run!\n");
278 }
279
280 return 0;
281}
282
283#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
284void rtl8821ae_set_fw_related_for_wowlan(struct ieee80211_hw *hw,
285 bool used_wowlan_fw)
286{
287 struct rtl_priv *rtlpriv = rtl_priv(hw);
288 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
289 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
290 /* 1. Before WoWLAN or After WOWLAN we need to re-download Fw. */
291 if (rtl8821ae_download_fw(hw, used_wowlan_fw)) {
292 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
293 "Re-Download Firmware failed!!\n");
294 rtlhal->fw_ready = false;
295 return;
296 }
297 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
298 "Re-Download Firmware Success !!\n");
299 rtlhal->fw_ready = true;
300
301 /* 2. Re-Init the variables about Fw related setting. */
302 ppsc->fw_current_inpsmode = false;
303 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
304 rtlhal->fw_clk_change_in_progress = false;
305 rtlhal->allow_sw_to_change_hwclc = false;
306 rtlhal->last_hmeboxnum = 0;
307}
308#endif
309
310static bool _rtl8821ae_check_fw_read_last_h2c(struct ieee80211_hw *hw,
311 u8 boxnum)
312{
313 struct rtl_priv *rtlpriv = rtl_priv(hw);
314 u8 val_hmetfr;
315 bool result = false;
316
317 val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
318 if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
319 result = true;
320 return result;
321}
322
323static void _rtl8821ae_fill_h2c_command(struct ieee80211_hw *hw,
324 u8 element_id, u32 cmd_len,
325 u8 *cmdbuffer)
326{
327 struct rtl_priv *rtlpriv = rtl_priv(hw);
328 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
329 u8 boxnum = 0;
330 u16 box_reg = 0, box_extreg = 0;
331 u8 u1b_tmp = 0;
332 bool isfw_read = false;
333 u8 buf_index = 0;
334 bool bwrite_sucess = false;
335 u8 wait_h2c_limmit = 100;
336 /*u8 wait_writeh2c_limmit = 100;*/
337 u8 boxcontent[4], boxextcontent[4];
338 u32 h2c_waitcounter = 0;
339 unsigned long flag = 0;
340 u8 idx = 0;
341
342 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
343
344 while (true) {
345 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
346 if (rtlhal->h2c_setinprogress) {
347 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
348 "H2C set in progress! Wait to set..element_id(%d).\n",
349 element_id);
350
351 while (rtlhal->h2c_setinprogress) {
352 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
353 flag);
354 h2c_waitcounter++;
355 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
356 "Wait 100 us (%d times)...\n",
357 h2c_waitcounter);
358 udelay(100);
359
360 if (h2c_waitcounter > 1000)
361 return;
362 spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
363 flag);
364 }
365 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
366 } else {
367 rtlhal->h2c_setinprogress = true;
368 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
369 break;
370 }
371 }
372
373 while (!bwrite_sucess) {
374 boxnum = rtlhal->last_hmeboxnum;
375 switch (boxnum) {
376 case 0:
377 box_reg = REG_HMEBOX_0;
378 box_extreg = REG_HMEBOX_EXT_0;
379 break;
380 case 1:
381 box_reg = REG_HMEBOX_1;
382 box_extreg = REG_HMEBOX_EXT_1;
383 break;
384 case 2:
385 box_reg = REG_HMEBOX_2;
386 box_extreg = REG_HMEBOX_EXT_2;
387 break;
388 case 3:
389 box_reg = REG_HMEBOX_3;
390 box_extreg = REG_HMEBOX_EXT_3;
391 break;
392 default:
393 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
394 "switch case not process\n");
395 break;
396 }
397
398 isfw_read = false;
399 u1b_tmp = rtl_read_byte(rtlpriv, REG_CR);
400
401 if (u1b_tmp != 0xEA) {
402 isfw_read = true;
403 } else {
404 if (rtl_read_byte(rtlpriv, REG_TXDMA_STATUS) == 0xEA ||
405 rtl_read_byte(rtlpriv, REG_TXPKT_EMPTY) == 0xEA)
406 rtl_write_byte(rtlpriv, REG_SYS_CFG1 + 3, 0xFF);
407 }
408
409 if (isfw_read) {
410 wait_h2c_limmit = 100;
411 isfw_read =
412 _rtl8821ae_check_fw_read_last_h2c(hw, boxnum);
413 while (!isfw_read) {
414 /*wait until Fw read*/
415 wait_h2c_limmit--;
416 if (wait_h2c_limmit == 0) {
417 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
418 "Waiting too long for FW read clear HMEBox(%d)!\n",
419 boxnum);
420 break;
421 }
422
423 udelay(10);
424
425 isfw_read =
426 _rtl8821ae_check_fw_read_last_h2c(hw, boxnum);
427 u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
428 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
429 "Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
430 boxnum, u1b_tmp);
431 }
432 }
433
434 if (!isfw_read) {
435 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
436 "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
437 boxnum);
438 break;
439 }
440
441 memset(boxcontent, 0, sizeof(boxcontent));
442 memset(boxextcontent, 0, sizeof(boxextcontent));
443 boxcontent[0] = element_id;
444 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
445 "Write element_id box_reg(%4x) = %2x\n",
446 box_reg, element_id);
447
448 switch (cmd_len) {
449 case 1:
450 case 2:
451 case 3:
452 /*boxcontent[0] &= ~(BIT(7));*/
453 memcpy((u8 *)(boxcontent) + 1,
454 cmdbuffer + buf_index, cmd_len);
455
456 for (idx = 0; idx < 4; idx++) {
457 rtl_write_byte(rtlpriv, box_reg + idx,
458 boxcontent[idx]);
459 }
460 break;
461 case 4:
462 case 5:
463 case 6:
464 case 7:
465 /*boxcontent[0] |= (BIT(7));*/
466 memcpy((u8 *)(boxextcontent),
467 cmdbuffer + buf_index+3, cmd_len-3);
468 memcpy((u8 *)(boxcontent) + 1,
469 cmdbuffer + buf_index, 3);
470
471 for (idx = 0; idx < 4; idx++) {
472 rtl_write_byte(rtlpriv, box_extreg + idx,
473 boxextcontent[idx]);
474 }
475
476 for (idx = 0; idx < 4; idx++) {
477 rtl_write_byte(rtlpriv, box_reg + idx,
478 boxcontent[idx]);
479 }
480 break;
481 default:
482 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
483 "switch case not process\n");
484 break;
485 }
486
487 bwrite_sucess = true;
488
489 rtlhal->last_hmeboxnum = boxnum + 1;
490 if (rtlhal->last_hmeboxnum == 4)
491 rtlhal->last_hmeboxnum = 0;
492
493 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
494 "pHalData->last_hmeboxnum = %d\n",
495 rtlhal->last_hmeboxnum);
496 }
497
498 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
499 rtlhal->h2c_setinprogress = false;
500 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
501
502 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
503}
504
505void rtl8821ae_fill_h2c_cmd(struct ieee80211_hw *hw,
506 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
507{
508 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
509 u32 tmp_cmdbuf[2];
510
511 if (!rtlhal->fw_ready) {
512 RT_ASSERT(false,
513 "return H2C cmd because of Fw download fail!!!\n");
514 return;
515 }
516
517 memset(tmp_cmdbuf, 0, 8);
518 memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
519 _rtl8821ae_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
520}
521
522void rtl8821ae_firmware_selfreset(struct ieee80211_hw *hw)
523{
524 struct rtl_priv *rtlpriv = rtl_priv(hw);
525 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
526 u8 u1b_tmp;
527
528 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
529 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
530 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
531 } else {
532 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
533 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(0))));
534 }
535
536 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
537 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
538 udelay(50);
539
540 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
541 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
542 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
543 } else {
544 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
545 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(0)));
546 }
547
548 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
549 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2)));
550
551 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
552 "_8051Reset8812ae(): 8051 reset success .\n");
553}
554
555void rtl8821ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
556{
557 struct rtl_priv *rtlpriv = rtl_priv(hw);
558 u8 u1_h2c_set_pwrmode[H2C_8821AE_PWEMODE_LENGTH] = { 0 };
559 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
560 u8 rlbm, power_state = 0;
561
562 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
563
564 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
565 rlbm = 0;/*YJ,temp,120316. FW now not support RLBM=2.*/
566 SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
567 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
568 (rtlpriv->mac80211.p2p) ?
569 ppsc->smart_ps : 1);
570 SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
571 ppsc->reg_max_lps_awakeintvl);
572 SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
573 if (mode == FW_PS_ACTIVE_MODE)
574 power_state |= FW_PWR_STATE_ACTIVE;
575 else
576 power_state |= FW_PWR_STATE_RF_OFF;
577
578 SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
579
580 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
581 "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
582 u1_h2c_set_pwrmode, H2C_8821AE_PWEMODE_LENGTH);
583 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_SETPWRMODE,
584 H2C_8821AE_PWEMODE_LENGTH,
585 u1_h2c_set_pwrmode);
586}
587
588void rtl8821ae_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw,
589 u8 mstatus)
590{
591 u8 parm[3] = { 0, 0, 0 };
592 /* parm[0]: bit0=0-->Disconnect, bit0=1-->Connect
593 * bit1=0-->update Media Status to MACID
594 * bit1=1-->update Media Status from MACID to MACID_End
595 * parm[1]: MACID, if this is INFRA_STA, MacID = 0
596 * parm[2]: MACID_End
597 */
598
599 SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
600 SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
601
602 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_MSRRPT, 3, parm);
603}
604
605void rtl8821ae_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
606 u8 ap_offload_enable)
607{
608 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
609 u8 u1_apoffload_parm[H2C_8821AE_AP_OFFLOAD_LENGTH] = { 0 };
610
611 SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable);
612 SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid);
613 SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
614
615 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_AP_OFFLOAD,
616 H2C_8821AE_AP_OFFLOAD_LENGTH,
617 u1_apoffload_parm);
618}
619
620void rtl8821ae_set_fw_wowlan_mode(struct ieee80211_hw *hw, bool func_en)
621{
622 struct rtl_priv *rtlpriv = rtl_priv(hw);
623 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
624 u8 fw_wowlan_info[H2C_8821AE_WOWLAN_LENGTH] = {0};
625
626 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "enable(%d)\n", func_en);
627
628 SET_8812_H2CCMD_WOWLAN_FUNC_ENABLE(fw_wowlan_info,
629 (func_en ? true : false));
630
631 SET_8812_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(fw_wowlan_info,
632 ((ppsc->wo_wlan_mode & WAKE_ON_PATTERN_MATCH) ? 1 : 0));
633 SET_8812_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(fw_wowlan_info,
634 ((ppsc->wo_wlan_mode & WAKE_ON_MAGIC_PACKET) ? 1 : 0));
635
636 SET_8812_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(fw_wowlan_info, 0);
637 SET_8812_H2CCMD_WOWLAN_ALL_PKT_DROP(fw_wowlan_info, false);
638 SET_8812_H2CCMD_WOWLAN_GPIO_ACTIVE(fw_wowlan_info, 0);
639 SET_8812_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(fw_wowlan_info, 1);
640 SET_8812_H2CCMD_WOWLAN_GPIONUM(fw_wowlan_info, 0);
641 SET_8812_H2CCMD_WOWLAN_GPIO_DURATION(fw_wowlan_info, 0);
642
643 RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_DMESG,
644 "wowlan mode: cmd 0x80: Content:\n",
645 fw_wowlan_info, H2C_8821AE_WOWLAN_LENGTH);
646
647 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_WO_WLAN,
648 H2C_8821AE_WOWLAN_LENGTH,
649 fw_wowlan_info);
650}
651
652void rtl8821ae_set_fw_remote_wake_ctrl_cmd(struct ieee80211_hw *hw,
653 u8 enable)
654{
655 struct rtl_priv *rtlpriv = rtl_priv(hw);
656 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
657 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
658 u8 remote_wake_ctrl_parm[H2C_8821AE_REMOTE_WAKE_CTRL_LEN] = {0};
659
660 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
661 "enable=%d, ARP offload=%d, GTK offload=%d\n",
662 enable, ppsc->arp_offload_enable, ppsc->gtk_offload_enable);
663
664 SET_8812_H2CCMD_REMOTE_WAKECTRL_ENABLE(remote_wake_ctrl_parm, enable);
665 SET_8812_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(remote_wake_ctrl_parm,
666 (ppsc->arp_offload_enable ? 1 : 0));
667 SET_8812_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(remote_wake_ctrl_parm,
668 (ppsc->gtk_offload_enable ? 1 : 0));
669 SET_8812_H2CCMD_REMOTE_WAKE_CTRL_REALWOWV2_EN(remote_wake_ctrl_parm,
670 (rtlhal->real_wow_v2_enable ? 1 : 0));
671
672 RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_TRACE,
673 "remote_wake_ctrl: cmd 0x4: Content:\n",
674 remote_wake_ctrl_parm, H2C_8821AE_REMOTE_WAKE_CTRL_LEN);
675
676 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_REMOTE_WAKE_CTRL,
677 H2C_8821AE_REMOTE_WAKE_CTRL_LEN,
678 remote_wake_ctrl_parm);
679}
680
681void rtl8821ae_set_fw_keep_alive_cmd(struct ieee80211_hw *hw,
682 bool func_en)
683{
684 struct rtl_priv *rtlpriv = rtl_priv(hw);
685 u8 keep_alive_info[H2C_8821AE_KEEP_ALIVE_CTRL_LENGTH] = {0};
686
687 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable(%d)\n", func_en);
688
689 SET_8812_H2CCMD_KEEP_ALIVE_ENABLE(keep_alive_info, func_en);
690 /* 1: the period is controled by driver, 0: by Fw default */
691 SET_8812_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(keep_alive_info, 1);
692 SET_8812_H2CCMD_KEEP_ALIVE_PERIOD(keep_alive_info, 10); /* 10 sec */
693
694 RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_TRACE,
695 "keep alive: cmd 0x3: Content:\n",
696 keep_alive_info, H2C_8821AE_KEEP_ALIVE_CTRL);
697 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL,
698 H2C_8821AE_KEEP_ALIVE_CTRL_LENGTH,
699 keep_alive_info);
700}
701
702void rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(struct ieee80211_hw *hw,
703 bool enabled)
704{
705 struct rtl_priv *rtlpriv = rtl_priv(hw);
706 u8 parm[H2C_8821AE_DISCONNECT_DECISION_CTRL_LEN] = {0};
707
708 SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_ENABLE(parm, enabled);
709 SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_USER_SETTING(parm, 1);
710 SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_CHECK_PERIOD(parm, 30);
711 SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_TRYPKT_NUM(parm, 3);
712
713 RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_TRACE,
714 "disconnect_decision_ctrl: cmd 0x4: Content:\n",
715 parm, H2C_8821AE_DISCONNECT_DECISION_CTRL_LEN);
716 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_DISCONNECT_DECISION,
717 H2C_8821AE_DISCONNECT_DECISION_CTRL_LEN, parm);
718}
719
720void rtl8821ae_set_fw_global_info_cmd(struct ieee80211_hw *hw)
721{
722 struct rtl_priv *rtlpriv = rtl_priv(hw);
723 struct rtl_security *sec = &rtlpriv->sec;
724 u8 remote_wakeup_sec_info[H2C_8821AE_AOAC_GLOBAL_INFO_LEN] = {0};
725
726 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
727 "PairwiseEncAlgorithm=%d, GroupEncAlgorithm=%d\n",
728 sec->pairwise_enc_algorithm, sec->group_enc_algorithm);
729
730 SET_8812_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(
731 remote_wakeup_sec_info,
732 sec->pairwise_enc_algorithm);
733 SET_8812_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(remote_wakeup_sec_info,
734 sec->group_enc_algorithm);
735
736 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_AOAC_GLOBAL_INFO,
737 H2C_8821AE_AOAC_GLOBAL_INFO_LEN,
738 remote_wakeup_sec_info);
739
740 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_TRACE,
741 "rtl8821ae_set_global_info: cmd 0x82:\n",
742 remote_wakeup_sec_info, H2C_8821AE_AOAC_GLOBAL_INFO_LEN);
743}
744
745static bool _rtl8821ae_cmd_send_packet(struct ieee80211_hw *hw,
746 struct sk_buff *skb)
747{
748 struct rtl_priv *rtlpriv = rtl_priv(hw);
749 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
750 struct rtl8192_tx_ring *ring;
751 struct rtl_tx_desc *pdesc;
752 struct sk_buff *pskb = NULL;
753 u8 own;
754 unsigned long flags;
755
756 ring = &rtlpci->tx_ring[BEACON_QUEUE];
757
758 pskb = __skb_dequeue(&ring->queue);
759 if (pskb)
760 kfree_skb(pskb);
761
762 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
763
764 pdesc = &ring->desc[0];
765 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc, true, HW_DESC_OWN);
766
767 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
768
769 __skb_queue_tail(&ring->queue, skb);
770
771 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
772
773 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
774
775 return true;
776}
777
778#define BEACON_PG 0
779#define PSPOLL_PG 1
780#define NULL_PG 2
781#define QOSNULL_PG 3
782#define ARPRESP_PG 4
783#define REMOTE_PG 5
784#define GTKEXT_PG 6
785
786#define TOTAL_RESERVED_PKT_LEN_8812 3584
787#define TOTAL_RESERVED_PKT_LEN_8821 1792
788
789static u8 reserved_page_packet_8821[TOTAL_RESERVED_PKT_LEN_8821] = {
790 /* page 0: beacon */
791 0x80, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
792 0xff, 0xff, 0x00, 0xe0, 0x4c, 0x02, 0xe2, 0x64,
793 0x40, 0x16, 0x9f, 0x23, 0xd4, 0x46, 0x20, 0x00,
794 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
795 0x64, 0x00, 0x20, 0x04, 0x00, 0x06, 0x64, 0x6c,
796 0x69, 0x6e, 0x6b, 0x31, 0x01, 0x08, 0x82, 0x84,
797 0x8b, 0x96, 0x0c, 0x18, 0x30, 0x48, 0x03, 0x01,
798 0x0b, 0x06, 0x02, 0x00, 0x00, 0x2a, 0x01, 0x8b,
799 0x32, 0x04, 0x12, 0x24, 0x60, 0x6c, 0x00, 0x00,
800 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
801 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
802 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
803 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
804 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
806 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
810 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
811 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
812 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
813 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
814 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
817 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
818 0x10, 0x00, 0x28, 0x8c, 0x00, 0x12, 0x00, 0x00,
819 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
820 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823 /* page 1: ps-poll */
824 0xa4, 0x10, 0x01, 0xc0, 0x40, 0x16, 0x9f, 0x23,
825 0xd4, 0x46, 0x00, 0xe0, 0x4c, 0x02, 0xe2, 0x64,
826 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
827 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
829 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
830 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
832 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
833 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
836 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
837 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
839 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
846 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
847 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851 0x18, 0x00, 0x28, 0x8c, 0x00, 0x12, 0x00, 0x00,
852 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
854 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
855 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
856 /* page 2: null data */
857 0x48, 0x01, 0x00, 0x00, 0x40, 0x16, 0x9f, 0x23,
858 0xd4, 0x46, 0x00, 0xe0, 0x4c, 0x02, 0xe2, 0x64,
859 0x40, 0x16, 0x9f, 0x23, 0xd4, 0x46, 0x00, 0x00,
860 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
861 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
862 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
869 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
871 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
876 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
877 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
878 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
879 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
880 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
881 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
882 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
883 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
884 0x1A, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
885 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
886 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
887 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
888 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
889 /* page 3: qos null data */
890 0xC8, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
891 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
892 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
893 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
894 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
896 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
897 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
899 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
900 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
901 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
903 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
904 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
906 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
907 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
908 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
909 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
911 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
912 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
913 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
914 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
916 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
917 0x3C, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
918 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
919 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
920 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
921 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
922 /* page 4~6 is for wowlan */
923 /* page 4: ARP resp */
924 0x08, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
925 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
926 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
927 0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06,
928 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x02,
929 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02, 0x00, 0x00,
930 0x00, 0x00, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
931 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
932 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
933 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
934 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
936 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
937 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
938 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
939 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
940 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
941 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
942 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
943 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
944 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
946 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
947 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
948 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
949 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
950 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
951 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
952 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
953 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
954 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
956 /* page 5: H2C_REMOTE_WAKE_CTRL_INFO */
957 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
959 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
961 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
962 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
963 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
964 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
966 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
967 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
968 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
969 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
970 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
971 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
972 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
973 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
974 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
976 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
978 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
979 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
981 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
982 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
983 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
984 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
986 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
987 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
989 /* page 6: Rsvd GTK extend memory (zero memory) */
990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
993 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
994 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
996 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
997 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
998 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
999 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1000 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1001 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1002 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1003 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1004 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1006 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1007 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1008 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1009 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1011 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1013 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1014 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1016 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1017 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1018 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1019 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1020 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1021 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1022};
1023
1024static u8 reserved_page_packet_8812[TOTAL_RESERVED_PKT_LEN_8812] = {
1025 /* page 0: beacon */
1026 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
1027 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
1028 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x60, 0x00,
1029 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1030 0x64, 0x00, 0x20, 0x04, 0x00, 0x03, 0x32, 0x31,
1031 0x35, 0x01, 0x08, 0x82, 0x84, 0x8B, 0x96, 0x0C,
1032 0x12, 0x18, 0x24, 0x03, 0x01, 0x01, 0x06, 0x02,
1033 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32, 0x04, 0x30,
1034 0x48, 0x60, 0x6C, 0x2D, 0x1A, 0xED, 0x09, 0x03,
1035 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1036 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1037 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3D,
1038 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C, 0x02, 0x02,
1039 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1040 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1041 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1042 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1043 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1044 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1046 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1047 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1048 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1049 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1050 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1053 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1054 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1056 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1059 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1060 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1061 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1062 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1063 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1064 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1066 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1067 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1069 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1073 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1074 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1076 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1077 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1078 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1079 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1080 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1081 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1082 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1083 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1084 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1085 0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
1086 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
1087 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1088 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1089 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1090 /* page 1: ps-poll */
1091 0xA4, 0x10, 0x09, 0xC0, 0x84, 0xC9, 0xB2, 0xA7,
1092 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
1093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1094 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1096 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1097 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1098 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1099 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1103 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1104 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1106 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1107 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1108 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1109 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1110 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1113 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1116 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1122 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1128 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1136 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1138 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1140 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1144 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1146 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1150 0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
1151 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
1152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1154 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1155 /* page 2: null data */
1156 0x48, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
1157 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
1158 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
1159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1162 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1163 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1164 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1166 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1167 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1169 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1172 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1173 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1174 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1201 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1202 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1204 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1206 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1207 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1208 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1209 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1210 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1211 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1212 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1213 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1214 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1215 0x1A, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
1216 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
1217 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1218 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1219 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1220 /* page 3: Qos null data */
1221 0xC8, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
1222 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
1223 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
1224 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1225 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1226 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1227 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1228 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1229 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1230 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1231 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1232 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1233 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1234 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1236 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1237 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1238 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1239 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1240 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1241 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1243 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1244 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1246 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1247 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1249 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1251 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1252 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1253 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1254 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1256 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1269 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1270 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1271 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1272 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1273 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1274 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1275 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1276 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1277 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1278 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1279 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1280 0x3C, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
1281 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
1282 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1283 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1284 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1285 /* page 4~6 is for wowlan */
1286 /* page 4: ARP resp */
1287 0x08, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
1288 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
1289 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
1290 0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06,
1291 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x02,
1292 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02, 0x00, 0x00,
1293 0x00, 0x00, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
1294 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1295 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1296 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1297 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1298 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1299 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1301 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1302 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1303 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1305 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1306 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1307 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1308 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1309 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1310 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1311 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1312 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1314 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1316 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1319 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1322 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1323 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1324 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1326 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1330 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1331 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1332 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1333 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1334 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1336 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1339 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1340 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1343 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1344 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1346 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1347 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1348 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1349 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1350 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1351 /* page 5: H2C_REMOTE_WAKE_CTRL_INFO */
1352 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1353 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1354 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1356 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1357 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1358 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1359 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1360 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1361 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1362 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1363 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1364 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1366 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1367 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1368 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1369 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1370 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1372 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1373 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1374 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1377 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1378 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1379 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1380 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1382 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1383 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1384 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1386 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1388 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1389 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1390 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1391 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1392 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1393 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1394 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1396 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1397 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1399 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1400 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1402 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1403 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1404 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1406 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1407 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1408 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1409 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1410 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1412 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1413 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1414 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1416 /* page 6: Rsvd GTK extend memory (zero memory) */
1417 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1418 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1419 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1420 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1422 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1423 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1424 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1427 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1428 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1429 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1430 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1432 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1433 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1434 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1435 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1436 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1437 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1438 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1439 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1440 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1442 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1443 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1444 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1446 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1447 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1448 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1449 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1450 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1451 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1452 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1453 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1454 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1455 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1456 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1457 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1459 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1460 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1462 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1463 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1464 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1466 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1467 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1468 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1469 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1470 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1471 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1472 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1473 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1474 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1476 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1477 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1478 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1479 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1480 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1481};
1482
1483void rtl8812ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
1484 bool b_dl_finished, bool dl_whole_packets)
1485{
1486 struct rtl_priv *rtlpriv = rtl_priv(hw);
1487 struct rtl_mac *mac = rtl_mac(rtlpriv);
1488 struct sk_buff *skb = NULL;
1489 u32 totalpacketlen;
1490 bool rtstatus;
1491 u8 u1RsvdPageLoc[5] = { 0 };
1492 u8 u1RsvdPageLoc2[7] = { 0 };
1493 bool b_dlok = false;
1494 u8 *beacon;
1495 u8 *p_pspoll;
1496 u8 *nullfunc;
1497 u8 *qosnull;
1498 u8 *arpresp;
1499
1500 /*---------------------------------------------------------
1501 * (1) beacon
1502 *---------------------------------------------------------
1503 */
1504 beacon = &reserved_page_packet_8812[BEACON_PG * 512];
1505 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
1506 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
1507
1508 if (b_dl_finished) {
1509 totalpacketlen = 512 - 40;
1510 goto out;
1511 }
1512 /*-------------------------------------------------------
1513 * (2) ps-poll
1514 *--------------------------------------------------------
1515 */
1516 p_pspoll = &reserved_page_packet_8812[PSPOLL_PG * 512];
1517 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
1518 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
1519 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
1520
1521 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
1522
1523 /*--------------------------------------------------------
1524 * (3) null data
1525 *---------------------------------------------------------
1526 */
1527 nullfunc = &reserved_page_packet_8812[NULL_PG * 512];
1528 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
1529 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
1530 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
1531
1532 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
1533
1534 /*---------------------------------------------------------
1535 * (4) Qos null data
1536 *----------------------------------------------------------
1537 */
1538 qosnull = &reserved_page_packet_8812[QOSNULL_PG * 512];
1539 SET_80211_HDR_ADDRESS1(qosnull, mac->bssid);
1540 SET_80211_HDR_ADDRESS2(qosnull, mac->mac_addr);
1541 SET_80211_HDR_ADDRESS3(qosnull, mac->bssid);
1542
1543 SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1RsvdPageLoc, QOSNULL_PG);
1544
1545 if (!dl_whole_packets) {
1546 totalpacketlen = 512 * (QOSNULL_PG + 1) - 40;
1547 goto out;
1548 }
1549 /*---------------------------------------------------------
1550 * (5) ARP Resp
1551 *----------------------------------------------------------
1552 */
1553 arpresp = &reserved_page_packet_8812[ARPRESP_PG * 512];
1554 SET_80211_HDR_ADDRESS1(arpresp, mac->bssid);
1555 SET_80211_HDR_ADDRESS2(arpresp, mac->mac_addr);
1556 SET_80211_HDR_ADDRESS3(arpresp, mac->bssid);
1557
1558 SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1RsvdPageLoc2, ARPRESP_PG);
1559
1560 /*---------------------------------------------------------
1561 * (6) Remote Wake Ctrl
1562 *----------------------------------------------------------
1563 */
1564 SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1RsvdPageLoc2,
1565 REMOTE_PG);
1566
1567 /*---------------------------------------------------------
1568 * (7) GTK Ext Memory
1569 *----------------------------------------------------------
1570 */
1571 SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1RsvdPageLoc2, GTKEXT_PG);
1572
1573 totalpacketlen = TOTAL_RESERVED_PKT_LEN_8812 - 40;
1574
1575out:
1576 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1577 "rtl8812ae_set_fw_rsvdpagepkt(): packet data\n",
1578 &reserved_page_packet_8812[0], totalpacketlen);
1579
1580 skb = dev_alloc_skb(totalpacketlen);
1581 memcpy((u8 *)skb_put(skb, totalpacketlen),
1582 &reserved_page_packet_8812, totalpacketlen);
1583
1584 rtstatus = _rtl8821ae_cmd_send_packet(hw, skb);
1585
1586 if (rtstatus)
1587 b_dlok = true;
1588
1589 if (!b_dl_finished && b_dlok) {
1590 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1591 "H2C_RSVDPAGE:\n", u1RsvdPageLoc, 5);
1592 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RSVDPAGE,
1593 sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
1594 if (dl_whole_packets) {
1595 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1596 "wowlan H2C_RSVDPAGE:\n", u1RsvdPageLoc2, 7);
1597 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_AOAC_RSVDPAGE,
1598 sizeof(u1RsvdPageLoc2), u1RsvdPageLoc2);
1599 }
1600 }
1601
1602 if (!b_dlok)
1603 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1604 "Set RSVD page location to Fw FAIL!!!!!!.\n");
1605}
1606
1607void rtl8821ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
1608 bool b_dl_finished, bool dl_whole_packets)
1609{
1610 struct rtl_priv *rtlpriv = rtl_priv(hw);
1611 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1612 struct sk_buff *skb = NULL;
1613 u32 totalpacketlen;
1614 bool rtstatus;
1615 u8 u1RsvdPageLoc[5] = { 0 };
1616 u8 u1RsvdPageLoc2[7] = { 0 };
1617 bool b_dlok = false;
1618 u8 *beacon;
1619 u8 *p_pspoll;
1620 u8 *nullfunc;
1621 u8 *qosnull;
1622 u8 *arpresp;
1623
1624 /*---------------------------------------------------------
1625 * (1) beacon
1626 *---------------------------------------------------------
1627 */
1628 beacon = &reserved_page_packet_8821[BEACON_PG * 256];
1629 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
1630 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
1631
1632 if (b_dl_finished) {
1633 totalpacketlen = 256 - 40;
1634 goto out;
1635 }
1636 /*-------------------------------------------------------
1637 * (2) ps-poll
1638 *--------------------------------------------------------
1639 */
1640 p_pspoll = &reserved_page_packet_8821[PSPOLL_PG * 256];
1641 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
1642 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
1643 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
1644
1645 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
1646
1647 /*--------------------------------------------------------
1648 * (3) null data
1649 *---------------------------------------------------------i
1650 */
1651 nullfunc = &reserved_page_packet_8821[NULL_PG * 256];
1652 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
1653 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
1654 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
1655
1656 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
1657
1658 /*---------------------------------------------------------
1659 * (4) Qos null data
1660 *----------------------------------------------------------
1661 */
1662 qosnull = &reserved_page_packet_8821[QOSNULL_PG * 256];
1663 SET_80211_HDR_ADDRESS1(qosnull, mac->bssid);
1664 SET_80211_HDR_ADDRESS2(qosnull, mac->mac_addr);
1665 SET_80211_HDR_ADDRESS3(qosnull, mac->bssid);
1666
1667 SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1RsvdPageLoc, QOSNULL_PG);
1668
1669 if (!dl_whole_packets) {
1670 totalpacketlen = 256 * (QOSNULL_PG + 1) - 40;
1671 goto out;
1672 }
1673 /*---------------------------------------------------------
1674 * (5) ARP Resp
1675 *----------------------------------------------------------
1676 */
1677 arpresp = &reserved_page_packet_8821[ARPRESP_PG * 256];
1678 SET_80211_HDR_ADDRESS1(arpresp, mac->bssid);
1679 SET_80211_HDR_ADDRESS2(arpresp, mac->mac_addr);
1680 SET_80211_HDR_ADDRESS3(arpresp, mac->bssid);
1681
1682 SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1RsvdPageLoc2, ARPRESP_PG);
1683
1684 /*---------------------------------------------------------
1685 * (6) Remote Wake Ctrl
1686 *----------------------------------------------------------
1687 */
1688 SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1RsvdPageLoc2,
1689 REMOTE_PG);
1690
1691 /*---------------------------------------------------------
1692 * (7) GTK Ext Memory
1693 *----------------------------------------------------------
1694 */
1695 SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1RsvdPageLoc2, GTKEXT_PG);
1696
1697 totalpacketlen = TOTAL_RESERVED_PKT_LEN_8821 - 40;
1698
1699out:
1700
1701 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1702 "rtl8821ae_set_fw_rsvdpagepkt(): packet data\n",
1703 &reserved_page_packet_8821[0], totalpacketlen);
1704
1705 skb = dev_alloc_skb(totalpacketlen);
1706 memcpy((u8 *)skb_put(skb, totalpacketlen),
1707 &reserved_page_packet_8821, totalpacketlen);
1708
1709 rtstatus = _rtl8821ae_cmd_send_packet(hw, skb);
1710
1711 if (rtstatus)
1712 b_dlok = true;
1713
1714 if (!b_dl_finished && b_dlok) {
1715 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1716 "Set RSVD page location to Fw.\n");
1717 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1718 "H2C_RSVDPAGE:\n", u1RsvdPageLoc, 5);
1719 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RSVDPAGE,
1720 sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
1721 if (dl_whole_packets) {
1722 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1723 "wowlan H2C_RSVDPAGE:\n",
1724 u1RsvdPageLoc2, 7);
1725 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_AOAC_RSVDPAGE,
1726 sizeof(u1RsvdPageLoc2),
1727 u1RsvdPageLoc2);
1728 }
1729 }
1730
1731 if (!b_dlok) {
1732 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1733 "Set RSVD page location to Fw FAIL!!!!!!.\n");
1734 }
1735}
1736
1737/*Should check FW support p2p or not.*/
1738static void rtl8821ae_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
1739{
1740 u8 u1_ctwindow_period[1] = { ctwindow};
1741
1742 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_P2P_PS_CTW_CMD, 1,
1743 u1_ctwindow_period);
1744}
1745
1746void rtl8821ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
1747{
1748 struct rtl_priv *rtlpriv = rtl_priv(hw);
1749 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
1750 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1751 struct rtl_p2p_ps_info *p2pinfo = &rtlps->p2p_ps_info;
1752 struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
1753 u8 i;
1754 u16 ctwindow;
1755 u32 start_time, tsf_low;
1756
1757 switch (p2p_ps_state) {
1758 case P2P_PS_DISABLE:
1759 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
1760 memset(p2p_ps_offload, 0, 1);
1761 break;
1762 case P2P_PS_ENABLE:
1763 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
1764 /* update CTWindow value. */
1765 if (p2pinfo->ctwindow > 0) {
1766 p2p_ps_offload->ctwindow_en = 1;
1767 ctwindow = p2pinfo->ctwindow;
1768 rtl8821ae_set_p2p_ctw_period_cmd(hw, ctwindow);
1769 }
1770
1771 /* hw only support 2 set of NoA */
1772 for (i = 0 ; i < p2pinfo->noa_num ; i++) {
1773 /* To control the register setting for which NOA*/
1774 rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
1775 if (i == 0)
1776 p2p_ps_offload->noa0_en = 1;
1777 else
1778 p2p_ps_offload->noa1_en = 1;
1779
1780 /* config P2P NoA Descriptor Register */
1781 rtl_write_dword(rtlpriv, 0x5E0, p2pinfo->noa_duration[i]);
1782 rtl_write_dword(rtlpriv, 0x5E4, p2pinfo->noa_interval[i]);
1783
1784 /*Get Current TSF value */
1785 tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1786
1787 start_time = p2pinfo->noa_start_time[i];
1788 if (p2pinfo->noa_count_type[i] != 1) {
1789 while (start_time <= (tsf_low+(50*1024))) {
1790 start_time += p2pinfo->noa_interval[i];
1791 if (p2pinfo->noa_count_type[i] != 255)
1792 p2pinfo->noa_count_type[i]--;
1793 }
1794 }
1795 rtl_write_dword(rtlpriv, 0x5E8, start_time);
1796 rtl_write_dword(rtlpriv, 0x5EC,
1797 p2pinfo->noa_count_type[i]);
1798 }
1799
1800 if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
1801 /* rst p2p circuit */
1802 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
1803
1804 p2p_ps_offload->offload_en = 1;
1805
1806 if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
1807 p2p_ps_offload->role = 1;
1808 p2p_ps_offload->allstasleep = 0;
1809 } else {
1810 p2p_ps_offload->role = 0;
1811 }
1812
1813 p2p_ps_offload->discovery = 0;
1814 }
1815 break;
1816 case P2P_PS_SCAN:
1817 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
1818 p2p_ps_offload->discovery = 1;
1819 break;
1820 case P2P_PS_SCAN_DONE:
1821 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
1822 p2p_ps_offload->discovery = 0;
1823 p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
1824 break;
1825 default:
1826 break;
1827 }
1828
1829 rtl8821ae_fill_h2c_cmd(hw,
1830 H2C_8821AE_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
1831}
1832
1833static void rtl8821ae_c2h_ra_report_handler(struct ieee80211_hw *hw,
1834 u8 *cmd_buf, u8 cmd_len)
1835{
1836 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1837 u8 rate = cmd_buf[0] & 0x3F;
1838
1839 rtlhal->current_ra_rate = rtl8821ae_hw_rate_to_mrate(hw, rate);
1840
1841 rtl8821ae_dm_update_init_rate(hw, rate);
1842}
1843
1844static void _rtl8821ae_c2h_content_parsing(struct ieee80211_hw *hw,
1845 u8 c2h_cmd_id, u8 c2h_cmd_len,
1846 u8 *tmp_buf)
1847{
1848 struct rtl_priv *rtlpriv = rtl_priv(hw);
1849
1850 switch (c2h_cmd_id) {
1851 case C2H_8812_DBG:
1852 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "[C2H], C2H_8812_DBG!!\n");
1853 break;
1854 case C2H_8812_RA_RPT:
1855 rtl8821ae_c2h_ra_report_handler(hw, tmp_buf, c2h_cmd_len);
1856 break;
1857 case C2H_8812_BT_INFO:
1858 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
1859 "[C2H], C2H_8812_BT_INFO!!\n");
1860 if (rtlpriv->cfg->ops->get_btc_status())
1861 rtlpriv->btcoexist.btc_ops->btc_btinfo_notify(rtlpriv,
1862 tmp_buf,
1863 c2h_cmd_len);
1864 break;
1865 default:
1866 break;
1867 }
1868}
1869
1870void rtl8821ae_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer,
1871 u8 length)
1872{
1873 struct rtl_priv *rtlpriv = rtl_priv(hw);
1874 u8 c2h_cmd_id = 0, c2h_cmd_seq = 0, c2h_cmd_len = 0;
1875 u8 *tmp_buf = NULL;
1876
1877 c2h_cmd_id = buffer[0];
1878 c2h_cmd_seq = buffer[1];
1879 c2h_cmd_len = length - 2;
1880 tmp_buf = buffer + 2;
1881
1882 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
1883 "[C2H packet], c2hCmdId=0x%x, c2hCmdSeq=0x%x, c2hCmdLen=%d\n",
1884 c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len);
1885
1886 RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_LOUD,
1887 "[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
1888 _rtl8821ae_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
1889}
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/fw.h b/drivers/net/wireless/rtlwifi/rtl8821ae/fw.h
new file mode 100644
index 000000000000..591c14c0b9b5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/fw.h
@@ -0,0 +1,351 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 * Larry Finger <Larry.Finger@lwfinger.net>
22 *
23 *****************************************************************************/
24
25#ifndef __RTL8821AE__FW__H__
26#define __RTL8821AE__FW__H__
27#include "def.h"
28
29#define FW_8821AE_SIZE 0x8000
30#define FW_8821AE_START_ADDRESS 0x1000
31#define FW_8821AE_END_ADDRESS 0x5FFF
32#define FW_8821AE_PAGE_SIZE 4096
33#define FW_8821AE_POLLING_DELAY 5
34#define FW_8821AE_POLLING_TIMEOUT_COUNT 6000
35
36#define IS_FW_HEADER_EXIST_8812(_pfwhdr) \
37 ((_pfwhdr->signature&0xFFF0) == 0x9500)
38
39#define IS_FW_HEADER_EXIST_8821(_pfwhdr) \
40 ((_pfwhdr->signature&0xFFF0) == 0x2100)
41
42#define USE_OLD_WOWLAN_DEBUG_FW 0
43
44#define H2C_8821AE_RSVDPAGE_LOC_LEN 5
45#define H2C_8821AE_PWEMODE_LENGTH 5
46#define H2C_8821AE_JOINBSSRPT_LENGTH 1
47#define H2C_8821AE_AP_OFFLOAD_LENGTH 3
48#define H2C_8821AE_WOWLAN_LENGTH 3
49#define H2C_8821AE_KEEP_ALIVE_CTRL_LENGTH 3
50#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
51#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 1
52#else
53#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 3
54#endif
55#define H2C_8821AE_AOAC_GLOBAL_INFO_LEN 2
56#define H2C_8821AE_AOAC_RSVDPAGE_LOC_LEN 7
57#define H2C_8821AE_DISCONNECT_DECISION_CTRL_LEN 3
58
59/* Fw PS state for RPWM.
60*BIT[2:0] = HW state
61
62*BIT[3] = Protocol PS state,
631: register active state ,
640: register sleep state
65
66*BIT[4] = sub-state
67*/
68#define FW_PS_GO_ON BIT(0)
69#define FW_PS_TX_NULL BIT(1)
70#define FW_PS_RF_ON BIT(2)
71#define FW_PS_REGISTER_ACTIVE BIT(3)
72
73#define FW_PS_DPS BIT(0)
74#define FW_PS_LCLK (FW_PS_DPS)
75#define FW_PS_RF_OFF BIT(1)
76#define FW_PS_ALL_ON BIT(2)
77#define FW_PS_ST_ACTIVE BIT(3)
78#define FW_PS_ISR_ENABLE BIT(4)
79#define FW_PS_IMR_ENABLE BIT(5)
80
81#define FW_PS_ACK BIT(6)
82#define FW_PS_TOGGLE BIT(7)
83
84 /* 8821AE RPWM value*/
85 /* BIT[0] = 1: 32k, 0: 40M*/
86 /* 32k*/
87#define FW_PS_CLOCK_OFF BIT(0)
88/*40M*/
89#define FW_PS_CLOCK_ON 0
90
91#define FW_PS_STATE_MASK (0x0F)
92#define FW_PS_STATE_HW_MASK (0x07)
93/*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/
94#define FW_PS_STATE_INT_MASK (0x3F)
95
96#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
97#define FW_PS_STATE_HW(x) (FW_PS_STATE_HW_MASK & (x))
98#define FW_PS_STATE_INT(x) (FW_PS_STATE_INT_MASK & (x))
99#define FW_PS_ISR_VAL(x) ((x) & 0x70)
100#define FW_PS_IMR_MASK(x) ((x) & 0xDF)
101#define FW_PS_KEEP_IMR(x) ((x) & 0x20)
102
103#define FW_PS_STATE_S0 (FW_PS_DPS)
104#define FW_PS_STATE_S1 (FW_PS_LCLK)
105#define FW_PS_STATE_S2 (FW_PS_RF_OFF)
106#define FW_PS_STATE_S3 (FW_PS_ALL_ON)
107#define FW_PS_STATE_S4 ((FW_PS_ST_ACTIVE) | (FW_PS_ALL_ON))
108 /* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/
109#define FW_PS_STATE_ALL_ON_8821AE (FW_PS_CLOCK_ON)
110 /* (FW_PS_RF_ON)*/
111#define FW_PS_STATE_RF_ON_8821AE (FW_PS_CLOCK_ON)
112 /* 0x0*/
113#define FW_PS_STATE_RF_OFF_8821AE (FW_PS_CLOCK_ON)
114 /* (FW_PS_STATE_RF_OFF)*/
115#define FW_PS_STATE_RF_OFF_LOW_PWR_8821AE (FW_PS_CLOCK_OFF)
116
117#define FW_PS_STATE_ALL_ON_92C (FW_PS_STATE_S4)
118#define FW_PS_STATE_RF_ON_92C (FW_PS_STATE_S3)
119#define FW_PS_STATE_RF_OFF_92C (FW_PS_STATE_S2)
120#define FW_PS_STATE_RF_OFF_LOW_PWR_92C (FW_PS_STATE_S1)
121
122/* For 8821AE H2C PwrMode Cmd ID 5.*/
123#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
124#define FW_PWR_STATE_RF_OFF 0
125
126#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
127#define FW_PS_IS_CLK_ON(x) ((x) & (FW_PS_RF_OFF | FW_PS_ALL_ON))
128#define FW_PS_IS_RF_ON(x) ((x) & (FW_PS_ALL_ON))
129#define FW_PS_IS_ACTIVE(x) ((x) & (FW_PS_ST_ACTIVE))
130#define FW_PS_IS_CPWM_INT(x) ((x) & 0x40)
131
132#define FW_CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
133
134#define IS_IN_LOW_POWER_STATE_8821AE(__state) \
135 (FW_PS_STATE(__state) == FW_PS_CLOCK_OFF)
136
137#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
138#define FW_PWR_STATE_RF_OFF 0
139
140struct rtl8821a_firmware_header {
141 u16 signature;
142 u8 category;
143 u8 function;
144 u16 version;
145 u8 subversion;
146 u8 rsvd1;
147 u8 month;
148 u8 date;
149 u8 hour;
150 u8 minute;
151 u16 ramcodeSize;
152 u16 rsvd2;
153 u32 svnindex;
154 u32 rsvd3;
155 u32 rsvd4;
156 u32 rsvd5;
157};
158
159enum rtl8812_c2h_evt {
160 C2H_8812_DBG = 0,
161 C2H_8812_LB = 1,
162 C2H_8812_TXBF = 2,
163 C2H_8812_TX_REPORT = 3,
164 C2H_8812_BT_INFO = 9,
165 C2H_8812_BT_MP = 11,
166 C2H_8812_RA_RPT = 12,
167
168 C2H_8812_FW_SWCHNL = 0x10,
169 C2H_8812_IQK_FINISH = 0x11,
170 MAX_8812_C2HEVENT
171};
172
173enum rtl8821a_h2c_cmd {
174 H2C_8821AE_RSVDPAGE = 0,
175 H2C_8821AE_MSRRPT = 1,
176 H2C_8821AE_SCAN = 2,
177 H2C_8821AE_KEEP_ALIVE_CTRL = 3,
178 H2C_8821AE_DISCONNECT_DECISION = 4,
179 H2C_8821AE_INIT_OFFLOAD = 6,
180 H2C_8821AE_AP_OFFLOAD = 8,
181 H2C_8821AE_BCN_RSVDPAGE = 9,
182 H2C_8821AE_PROBERSP_RSVDPAGE = 10,
183
184 H2C_8821AE_SETPWRMODE = 0x20,
185 H2C_8821AE_PS_TUNING_PARA = 0x21,
186 H2C_8821AE_PS_TUNING_PARA2 = 0x22,
187 H2C_8821AE_PS_LPS_PARA = 0x23,
188 H2C_8821AE_P2P_PS_OFFLOAD = 024,
189
190 H2C_8821AE_WO_WLAN = 0x80,
191 H2C_8821AE_REMOTE_WAKE_CTRL = 0x81,
192 H2C_8821AE_AOAC_GLOBAL_INFO = 0x82,
193 H2C_8821AE_AOAC_RSVDPAGE = 0x83,
194
195 H2C_RSSI_21AE_REPORT = 0x42,
196 H2C_8821AE_RA_MASK = 0x40,
197 H2C_8821AE_SELECTIVE_SUSPEND_ROF_CMD,
198 H2C_8821AE_P2P_PS_MODE,
199 H2C_8821AE_PSD_RESULT,
200 /*Not defined CTW CMD for P2P yet*/
201 H2C_8821AE_P2P_PS_CTW_CMD,
202 MAX_8821AE_H2CCMD
203};
204
205#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
206
207#define SET_8812_H2CCMD_WOWLAN_FUNC_ENABLE(__cmd, __value) \
208 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
209#define SET_8812_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__cmd, __value) \
210 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
211#define SET_8812_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__cmd, __value) \
212 SET_BITS_TO_LE_1BYTE(__cmd, 2, 1, __value)
213#define SET_8812_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__cmd, __value) \
214 SET_BITS_TO_LE_1BYTE(__cmd, 3, 1, __value)
215#define SET_8812_H2CCMD_WOWLAN_ALL_PKT_DROP(__cmd, __value) \
216 SET_BITS_TO_LE_1BYTE(__cmd, 4, 1, __value)
217#define SET_8812_H2CCMD_WOWLAN_GPIO_ACTIVE(__cmd, __value) \
218 SET_BITS_TO_LE_1BYTE(__cmd, 5, 1, __value)
219#define SET_8812_H2CCMD_WOWLAN_REKEY_WAKE_UP(__cmd, __value) \
220 SET_BITS_TO_LE_1BYTE(__cmd, 6, 1, __value)
221#define SET_8812_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__cmd, __value) \
222 SET_BITS_TO_LE_1BYTE(__cmd, 7, 1, __value)
223#define SET_8812_H2CCMD_WOWLAN_GPIONUM(__cmd, __value) \
224 SET_BITS_TO_LE_1BYTE((__cmd) + 1, 0, 8, __value)
225#define SET_8812_H2CCMD_WOWLAN_GPIO_DURATION(__cmd, __value) \
226 SET_BITS_TO_LE_1BYTE((__cmd) + 2, 0, 8, __value)
227
228#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
229 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
230#define SET_H2CCMD_PWRMODE_PARM_RLBM(__cmd, __value) \
231 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 4, __value)
232#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__cmd, __value) \
233 SET_BITS_TO_LE_1BYTE((__cmd)+1, 4, 4, __value)
234#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__cmd, __value) \
235 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
236#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__cmd, __value) \
237 SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
238#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__cmd, __value) \
239 SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __value)
240#define GET_8821AE_H2CCMD_PWRMODE_PARM_MODE(__cmd) \
241 LE_BITS_TO_1BYTE(__cmd, 0, 8)
242
243#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
244 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
245#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
246 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
247#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
248 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
249#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__ph2ccmd, __val) \
250 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+3, 0, 8, __val)
251
252/* _MEDIA_STATUS_RPT_PARM_CMD1 */
253#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__cmd, __value) \
254 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
255#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__cmd, __value) \
256 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
257#define SET_H2CCMD_MSRRPT_PARM_MACID(__cmd, __value) \
258 SET_BITS_TO_LE_1BYTE(__cmd+1, 0, 8, __value)
259#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__cmd, __value) \
260 SET_BITS_TO_LE_1BYTE(__cmd+2, 0, 8, __value)
261
262/* AP_OFFLOAD */
263#define SET_H2CCMD_AP_OFFLOAD_ON(__cmd, __value) \
264 SET_BITS_TO_LE_1BYTE(__cmd, 0, 8, __value)
265#define SET_H2CCMD_AP_OFFLOAD_HIDDEN(__cmd, __value) \
266 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
267#define SET_H2CCMD_AP_OFFLOAD_DENYANY(__cmd, __value) \
268 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
269#define SET_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__cmd, __value) \
270 SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
271
272/* Keep Alive Control*/
273#define SET_8812_H2CCMD_KEEP_ALIVE_ENABLE(__cmd, __value) \
274 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
275#define SET_8812_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__cmd, __value) \
276 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
277#define SET_8812_H2CCMD_KEEP_ALIVE_PERIOD(__cmd, __value) \
278 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
279
280/*REMOTE_WAKE_CTRL */
281#define SET_8812_H2CCMD_REMOTE_WAKECTRL_ENABLE(__cmd, __value) \
282 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
283#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__cmd, __value)\
284 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
285#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__cmd, __value)\
286 SET_BITS_TO_LE_1BYTE(__cmd, 2, 1, __value)
287#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__cmd, __value)\
288 SET_BITS_TO_LE_1BYTE(__cmd, 3, 1, __value)
289#define SET_8812_H2CCMD_REMOTE_WAKE_CTRL_REALWOWV2_EN(__cmd, __value)\
290 SET_BITS_TO_LE_1BYTE(__cmd, 6, 1, __value)
291
292/* GTK_OFFLOAD */
293#define SET_8812_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__cmd, __value)\
294 SET_BITS_TO_LE_1BYTE(__cmd, 0, 8, __value)
295#define SET_8812_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__cmd, __value) \
296 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
297
298/* AOAC_RSVDPAGE_LOC */
299#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__cmd, __value) \
300 SET_BITS_TO_LE_1BYTE((__cmd), 0, 8, __value)
301#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__cmd, __value) \
302 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
303#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__cmd, __value)\
304 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
305#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__cmd, __value) \
306 SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
307#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__cmd, __value) \
308 SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __value)
309#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__cmd, __value) \
310 SET_BITS_TO_LE_1BYTE((__cmd)+5, 0, 8, __value)
311
312/* Disconnect_Decision_Control */
313#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_ENABLE(__cmd, __value) \
314 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
315#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_USER_SETTING(__cmd, __value)\
316 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
317#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_CHECK_PERIOD(__cmd, __value)\
318 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value) /* unit: beacon period */
319#define SET_8812_H2CCMD_DISCONNECT_DECISION_CTRL_TRYPKT_NUM(__cmd, __value)\
320 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
321
322int rtl8821ae_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw);
323#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
324void rtl8821ae_set_fw_related_for_wowlan(struct ieee80211_hw *hw,
325 bool used_wowlan_fw);
326
327#endif
328void rtl8821ae_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
329 u32 cmd_len, u8 *cmdbuffer);
330void rtl8821ae_firmware_selfreset(struct ieee80211_hw *hw);
331void rtl8821ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
332void rtl8821ae_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw,
333 u8 mstatus);
334void rtl8821ae_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
335 u8 ap_offload_enable);
336void rtl8821ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
337 bool b_dl_finished, bool dl_whole_packet);
338void rtl8812ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
339 bool b_dl_finished, bool dl_whole_packet);
340void rtl8821ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
341 u8 p2p_ps_state);
342void rtl8821ae_set_fw_wowlan_mode(struct ieee80211_hw *hw, bool func_en);
343void rtl8821ae_set_fw_remote_wake_ctrl_cmd(struct ieee80211_hw *hw,
344 u8 enable);
345void rtl8821ae_set_fw_keep_alive_cmd(struct ieee80211_hw *hw, bool func_en);
346void rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(struct ieee80211_hw *hw,
347 bool enabled);
348void rtl8821ae_set_fw_global_info_cmd(struct ieee80211_hw *hw);
349void rtl8821ae_c2h_packet_handler(struct ieee80211_hw *hw,
350 u8 *buffer, u8 length);
351#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
new file mode 100644
index 000000000000..edb7557e0d44
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
@@ -0,0 +1,4222 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../efuse.h"
28#include "../base.h"
29#include "../regd.h"
30#include "../cam.h"
31#include "../ps.h"
32#include "../pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "dm.h"
37#include "fw.h"
38#include "led.h"
39#include "hw.h"
40#include "../pwrseqcmd.h"
41#include "pwrseq.h"
42#include "../btcoexist/rtl_btc.h"
43
44#define LLT_CONFIG 5
45
46bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
47 u8 faversion, u8 interface_type,
48 struct wlan_pwr_cfg pwrcfgcmd[])
49{
50 return false;
51}
52
53static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
54{
55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
57 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
58
59 while (skb_queue_len(&ring->queue)) {
60 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
61 struct sk_buff *skb = __skb_dequeue(&ring->queue);
62
63 pci_unmap_single(rtlpci->pdev,
64 rtlpriv->cfg->ops->get_desc(
65 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
66 skb->len, PCI_DMA_TODEVICE);
67 kfree_skb(skb);
68 ring->idx = (ring->idx + 1) % ring->entries;
69 }
70}
71
72static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
73 u8 set_bits, u8 clear_bits)
74{
75 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77
78 rtlpci->reg_bcn_ctrl_val |= set_bits;
79 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
80
81 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
82}
83
84void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
85{
86 struct rtl_priv *rtlpriv = rtl_priv(hw);
87 u8 tmp1byte;
88
89 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
90 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
91 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
92 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
93 tmp1byte &= ~(BIT(0));
94 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
95}
96
97void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
98{
99 struct rtl_priv *rtlpriv = rtl_priv(hw);
100 u8 tmp1byte;
101
102 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
103 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
104 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
105 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
106 tmp1byte |= BIT(0);
107 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
108}
109
110static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
111{
112 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
113}
114
115static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
116{
117 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
118}
119
120static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
121 u8 rpwm_val, bool b_need_turn_off_ckk)
122{
123 struct rtl_priv *rtlpriv = rtl_priv(hw);
124 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
125 bool b_support_remote_wake_up;
126 u32 count = 0, isr_regaddr, content;
127 bool b_schedule_timer = b_need_turn_off_ckk;
128
129 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
130 (u8 *)(&b_support_remote_wake_up));
131
132 if (!rtlhal->fw_ready)
133 return;
134 if (!rtlpriv->psc.fw_current_inpsmode)
135 return;
136
137 while (1) {
138 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
139 if (rtlhal->fw_clk_change_in_progress) {
140 while (rtlhal->fw_clk_change_in_progress) {
141 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
142 count++;
143 udelay(100);
144 if (count > 1000)
145 goto change_done;
146 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
147 }
148 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
149 } else {
150 rtlhal->fw_clk_change_in_progress = false;
151 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
152 goto change_done;
153 }
154 }
155change_done:
156 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
157 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
158 (u8 *)(&rpwm_val));
159 if (FW_PS_IS_ACK(rpwm_val)) {
160 isr_regaddr = REG_HISR;
161 content = rtl_read_dword(rtlpriv, isr_regaddr);
162 while (!(content & IMR_CPWM) && (count < 500)) {
163 udelay(50);
164 count++;
165 content = rtl_read_dword(rtlpriv, isr_regaddr);
166 }
167
168 if (content & IMR_CPWM) {
169 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
170 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
171 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
172 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
173 rtlhal->fw_ps_state);
174 }
175 }
176
177 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
178 rtlhal->fw_clk_change_in_progress = false;
179 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
180 if (b_schedule_timer)
181 mod_timer(&rtlpriv->works.fw_clockoff_timer,
182 jiffies + MSECS(10));
183 } else {
184 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
185 rtlhal->fw_clk_change_in_progress = false;
186 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
187 }
188}
189
190static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
191 u8 rpwm_val)
192{
193 struct rtl_priv *rtlpriv = rtl_priv(hw);
194 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
195 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
196 struct rtl8192_tx_ring *ring;
197 enum rf_pwrstate rtstate;
198 bool b_schedule_timer = false;
199 u8 queue;
200
201 if (!rtlhal->fw_ready)
202 return;
203 if (!rtlpriv->psc.fw_current_inpsmode)
204 return;
205 if (!rtlhal->allow_sw_to_change_hwclc)
206 return;
207 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
208 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
209 return;
210
211 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
212 ring = &rtlpci->tx_ring[queue];
213 if (skb_queue_len(&ring->queue)) {
214 b_schedule_timer = true;
215 break;
216 }
217 }
218
219 if (b_schedule_timer) {
220 mod_timer(&rtlpriv->works.fw_clockoff_timer,
221 jiffies + MSECS(10));
222 return;
223 }
224
225 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
226 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
227 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
228 if (!rtlhal->fw_clk_change_in_progress) {
229 rtlhal->fw_clk_change_in_progress = true;
230 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
231 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
232 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
233 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
234 (u8 *)(&rpwm_val));
235 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
236 rtlhal->fw_clk_change_in_progress = false;
237 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
238 } else {
239 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
240 mod_timer(&rtlpriv->works.fw_clockoff_timer,
241 jiffies + MSECS(10));
242 }
243 }
244}
245
246static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
247{
248 u8 rpwm_val = 0;
249
250 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
251 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
252}
253
254static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
255{
256 struct rtl_priv *rtlpriv = rtl_priv(hw);
257 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
258 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
259 bool fw_current_inps = false;
260 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
261
262 if (ppsc->low_power_enable) {
263 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
264 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
265 rtlhal->allow_sw_to_change_hwclc = false;
266 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
267 (u8 *)(&fw_pwrmode));
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
269 (u8 *)(&fw_current_inps));
270 } else {
271 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
273 (u8 *)(&rpwm_val));
274 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
275 (u8 *)(&fw_pwrmode));
276 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
277 (u8 *)(&fw_current_inps));
278 }
279}
280
281static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
282{
283 struct rtl_priv *rtlpriv = rtl_priv(hw);
284 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
285 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
286 bool fw_current_inps = true;
287 u8 rpwm_val;
288
289 if (ppsc->low_power_enable) {
290 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
291 rtlpriv->cfg->ops->set_hw_reg(hw,
292 HW_VAR_FW_PSMODE_STATUS,
293 (u8 *)(&fw_current_inps));
294 rtlpriv->cfg->ops->set_hw_reg(hw,
295 HW_VAR_H2C_FW_PWRMODE,
296 (u8 *)(&ppsc->fwctrl_psmode));
297 rtlhal->allow_sw_to_change_hwclc = true;
298 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
299 } else {
300 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
301 rtlpriv->cfg->ops->set_hw_reg(hw,
302 HW_VAR_FW_PSMODE_STATUS,
303 (u8 *)(&fw_current_inps));
304 rtlpriv->cfg->ops->set_hw_reg(hw,
305 HW_VAR_H2C_FW_PWRMODE,
306 (u8 *)(&ppsc->fwctrl_psmode));
307 rtlpriv->cfg->ops->set_hw_reg(hw,
308 HW_VAR_SET_RPWM,
309 (u8 *)(&rpwm_val));
310 }
311}
312
313static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
314 bool dl_whole_packets)
315{
316 struct rtl_priv *rtlpriv = rtl_priv(hw);
317 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
318 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
319 u8 count = 0, dlbcn_count = 0;
320 bool send_beacon = false;
321
322 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
323 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
324
325 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
326 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
327
328 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
329 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
330 tmp_reg422 & (~BIT(6)));
331 if (tmp_reg422 & BIT(6))
332 send_beacon = true;
333
334 do {
335 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
336 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
337 (bcnvalid_reg | BIT(0)));
338 _rtl8821ae_return_beacon_queue_skb(hw);
339
340 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
341 rtl8812ae_set_fw_rsvdpagepkt(hw, false,
342 dl_whole_packets);
343 else
344 rtl8821ae_set_fw_rsvdpagepkt(hw, false,
345 dl_whole_packets);
346
347 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
348 count = 0;
349 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
350 count++;
351 udelay(10);
352 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
353 }
354 dlbcn_count++;
355 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
356
357 if (!(bcnvalid_reg & BIT(0)))
358 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
359 "Download RSVD page failed!\n");
360 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
361 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
362 _rtl8821ae_return_beacon_queue_skb(hw);
363 if (send_beacon) {
364 dlbcn_count = 0;
365 do {
366 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
367 bcnvalid_reg | BIT(0));
368
369 _rtl8821ae_return_beacon_queue_skb(hw);
370
371 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
372 rtl8812ae_set_fw_rsvdpagepkt(hw, true,
373 false);
374 else
375 rtl8821ae_set_fw_rsvdpagepkt(hw, true,
376 false);
377
378 /* check rsvd page download OK. */
379 bcnvalid_reg = rtl_read_byte(rtlpriv,
380 REG_TDECTRL + 2);
381 count = 0;
382 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
383 count++;
384 udelay(10);
385 bcnvalid_reg =
386 rtl_read_byte(rtlpriv,
387 REG_TDECTRL + 2);
388 }
389 dlbcn_count++;
390 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
391
392 if (!(bcnvalid_reg & BIT(0)))
393 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
394 "2 Download RSVD page failed!\n");
395 }
396 }
397
398 if (bcnvalid_reg & BIT(0))
399 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
400
401 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
402 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
403
404 if (send_beacon)
405 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
406
407 if (!rtlhal->enter_pnp_sleep) {
408 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
409 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
410 }
411}
412
413void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
414{
415 struct rtl_priv *rtlpriv = rtl_priv(hw);
416 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
417 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
418 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
419
420 switch (variable) {
421 case HW_VAR_ETHER_ADDR:
422 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
423 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
424 break;
425 case HW_VAR_BSSID:
426 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
427 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
428 break;
429 case HW_VAR_MEDIA_STATUS:
430 val[0] = rtl_read_byte(rtlpriv, REG_CR+2) & 0x3;
431 break;
432 case HW_VAR_SLOT_TIME:
433 *((u8 *)(val)) = mac->slot_time;
434 break;
435 case HW_VAR_BEACON_INTERVAL:
436 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
437 break;
438 case HW_VAR_ATIM_WINDOW:
439 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
440 break;
441 case HW_VAR_RCR:
442 *((u32 *)(val)) = rtlpci->receive_config;
443 break;
444 case HW_VAR_RF_STATE:
445 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
446 break;
447 case HW_VAR_FWLPS_RF_ON:{
448 enum rf_pwrstate rfstate;
449 u32 val_rcr;
450
451 rtlpriv->cfg->ops->get_hw_reg(hw,
452 HW_VAR_RF_STATE,
453 (u8 *)(&rfstate));
454 if (rfstate == ERFOFF) {
455 *((bool *)(val)) = true;
456 } else {
457 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
458 val_rcr &= 0x00070000;
459 if (val_rcr)
460 *((bool *)(val)) = false;
461 else
462 *((bool *)(val)) = true;
463 }
464 break; }
465 case HW_VAR_FW_PSMODE_STATUS:
466 *((bool *)(val)) = ppsc->fw_current_inpsmode;
467 break;
468 case HW_VAR_CORRECT_TSF:{
469 u64 tsf;
470 u32 *ptsf_low = (u32 *)&tsf;
471 u32 *ptsf_high = ((u32 *)&tsf) + 1;
472
473 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
474 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
475
476 *((u64 *)(val)) = tsf;
477
478 break; }
479 case HAL_DEF_WOWLAN:
480 if (ppsc->wo_wlan_mode)
481 *((bool *)(val)) = true;
482 else
483 *((bool *)(val)) = false;
484 break;
485 default:
486 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
487 "switch case not process %x\n", variable);
488 break;
489 }
490}
491
492void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
493{
494 struct rtl_priv *rtlpriv = rtl_priv(hw);
495 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
496 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
497 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
498 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
499 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
500 u8 idx;
501
502 switch (variable) {
503 case HW_VAR_ETHER_ADDR:{
504 for (idx = 0; idx < ETH_ALEN; idx++) {
505 rtl_write_byte(rtlpriv, (REG_MACID + idx),
506 val[idx]);
507 }
508 break;
509 }
510 case HW_VAR_BASIC_RATE:{
511 u16 b_rate_cfg = ((u16 *)val)[0];
512 b_rate_cfg = b_rate_cfg & 0x15f;
513 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
514 break;
515 }
516 case HW_VAR_BSSID:{
517 for (idx = 0; idx < ETH_ALEN; idx++) {
518 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
519 val[idx]);
520 }
521 break;
522 }
523 case HW_VAR_SIFS:
524 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
525 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
526
527 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
528 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
529
530 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
531 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
532 break;
533 case HW_VAR_R2T_SIFS:
534 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
535 break;
536 case HW_VAR_SLOT_TIME:{
537 u8 e_aci;
538
539 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
540 "HW_VAR_SLOT_TIME %x\n", val[0]);
541
542 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
543
544 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
545 rtlpriv->cfg->ops->set_hw_reg(hw,
546 HW_VAR_AC_PARAM,
547 (u8 *)(&e_aci));
548 }
549 break; }
550 case HW_VAR_ACK_PREAMBLE:{
551 u8 reg_tmp;
552 u8 short_preamble = (bool)(*(u8 *)val);
553
554 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
555 if (short_preamble) {
556 reg_tmp |= BIT(1);
557 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
558 reg_tmp);
559 } else {
560 reg_tmp &= (~BIT(1));
561 rtl_write_byte(rtlpriv,
562 REG_TRXPTCL_CTL + 2,
563 reg_tmp);
564 }
565 break; }
566 case HW_VAR_WPA_CONFIG:
567 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
568 break;
569 case HW_VAR_AMPDU_MIN_SPACE:{
570 u8 min_spacing_to_set;
571 u8 sec_min_space;
572
573 min_spacing_to_set = *((u8 *)val);
574 if (min_spacing_to_set <= 7) {
575 sec_min_space = 0;
576
577 if (min_spacing_to_set < sec_min_space)
578 min_spacing_to_set = sec_min_space;
579
580 mac->min_space_cfg = ((mac->min_space_cfg &
581 0xf8) |
582 min_spacing_to_set);
583
584 *val = min_spacing_to_set;
585
586 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
587 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
588 mac->min_space_cfg);
589
590 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
591 mac->min_space_cfg);
592 }
593 break; }
594 case HW_VAR_SHORTGI_DENSITY:{
595 u8 density_to_set;
596
597 density_to_set = *((u8 *)val);
598 mac->min_space_cfg |= (density_to_set << 3);
599
600 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
601 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
602 mac->min_space_cfg);
603
604 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
605 mac->min_space_cfg);
606
607 break; }
608 case HW_VAR_AMPDU_FACTOR:{
609 u32 ampdu_len = (*((u8 *)val));
610
611 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
612 if (ampdu_len < VHT_AGG_SIZE_128K)
613 ampdu_len =
614 (0x2000 << (*((u8 *)val))) - 1;
615 else
616 ampdu_len = 0x1ffff;
617 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
618 if (ampdu_len < HT_AGG_SIZE_64K)
619 ampdu_len =
620 (0x2000 << (*((u8 *)val))) - 1;
621 else
622 ampdu_len = 0xffff;
623 }
624 ampdu_len |= BIT(31);
625
626 rtl_write_dword(rtlpriv,
627 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
628 break; }
629 case HW_VAR_AC_PARAM:{
630 u8 e_aci = *((u8 *)val);
631
632 rtl8821ae_dm_init_edca_turbo(hw);
633 if (rtlpci->acm_method != EACMWAY2_SW)
634 rtlpriv->cfg->ops->set_hw_reg(hw,
635 HW_VAR_ACM_CTRL,
636 (u8 *)(&e_aci));
637 break; }
638 case HW_VAR_ACM_CTRL:{
639 u8 e_aci = *((u8 *)val);
640 union aci_aifsn *p_aci_aifsn =
641 (union aci_aifsn *)(&mac->ac[0].aifs);
642 u8 acm = p_aci_aifsn->f.acm;
643 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
644
645 acm_ctrl =
646 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
647
648 if (acm) {
649 switch (e_aci) {
650 case AC0_BE:
651 acm_ctrl |= ACMHW_BEQEN;
652 break;
653 case AC2_VI:
654 acm_ctrl |= ACMHW_VIQEN;
655 break;
656 case AC3_VO:
657 acm_ctrl |= ACMHW_VOQEN;
658 break;
659 default:
660 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
661 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
662 acm);
663 break;
664 }
665 } else {
666 switch (e_aci) {
667 case AC0_BE:
668 acm_ctrl &= (~ACMHW_BEQEN);
669 break;
670 case AC2_VI:
671 acm_ctrl &= (~ACMHW_VIQEN);
672 break;
673 case AC3_VO:
674 acm_ctrl &= (~ACMHW_BEQEN);
675 break;
676 default:
677 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
678 "switch case not process\n");
679 break;
680 }
681 }
682
683 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
684 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
685 acm_ctrl);
686 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
687 break; }
688 case HW_VAR_RCR:
689 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
690 rtlpci->receive_config = ((u32 *)(val))[0];
691 break;
692 case HW_VAR_RETRY_LIMIT:{
693 u8 retry_limit = ((u8 *)(val))[0];
694
695 rtl_write_word(rtlpriv, REG_RL,
696 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
697 retry_limit << RETRY_LIMIT_LONG_SHIFT);
698 break; }
699 case HW_VAR_DUAL_TSF_RST:
700 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
701 break;
702 case HW_VAR_EFUSE_BYTES:
703 rtlefuse->efuse_usedbytes = *((u16 *)val);
704 break;
705 case HW_VAR_EFUSE_USAGE:
706 rtlefuse->efuse_usedpercentage = *((u8 *)val);
707 break;
708 case HW_VAR_IO_CMD:
709 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
710 break;
711 case HW_VAR_SET_RPWM:{
712 u8 rpwm_val;
713
714 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
715 udelay(1);
716
717 if (rpwm_val & BIT(7)) {
718 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
719 (*(u8 *)val));
720 } else {
721 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
722 ((*(u8 *)val) | BIT(7)));
723 }
724
725 break; }
726 case HW_VAR_H2C_FW_PWRMODE:
727 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
728 break;
729 case HW_VAR_FW_PSMODE_STATUS:
730 ppsc->fw_current_inpsmode = *((bool *)val);
731 break;
732 case HW_VAR_INIT_RTS_RATE:
733 break;
734 case HW_VAR_RESUME_CLK_ON:
735 _rtl8821ae_set_fw_ps_rf_on(hw);
736 break;
737 case HW_VAR_FW_LPS_ACTION:{
738 bool b_enter_fwlps = *((bool *)val);
739
740 if (b_enter_fwlps)
741 _rtl8821ae_fwlps_enter(hw);
742 else
743 _rtl8821ae_fwlps_leave(hw);
744 break; }
745 case HW_VAR_H2C_FW_JOINBSSRPT:{
746 u8 mstatus = (*(u8 *)val);
747
748 if (mstatus == RT_MEDIA_CONNECT) {
749 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
750 NULL);
751 _rtl8821ae_download_rsvd_page(hw, false);
752 }
753 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
754
755 break; }
756 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
757 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
758 break;
759 case HW_VAR_AID:{
760 u16 u2btmp;
761 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
762 u2btmp &= 0xC000;
763 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
764 mac->assoc_id));
765 break; }
766 case HW_VAR_CORRECT_TSF:{
767 u8 btype_ibss = ((u8 *)(val))[0];
768
769 if (btype_ibss)
770 _rtl8821ae_stop_tx_beacon(hw);
771
772 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
773
774 rtl_write_dword(rtlpriv, REG_TSFTR,
775 (u32)(mac->tsf & 0xffffffff));
776 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
777 (u32)((mac->tsf >> 32) & 0xffffffff));
778
779 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
780
781 if (btype_ibss)
782 _rtl8821ae_resume_tx_beacon(hw);
783 break; }
784 case HW_VAR_NAV_UPPER: {
785 u32 us_nav_upper = ((u32)*val);
786
787 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
788 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
789 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
790 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
791 break;
792 }
793 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
794 ((u8)((us_nav_upper +
795 HAL_92C_NAV_UPPER_UNIT - 1) /
796 HAL_92C_NAV_UPPER_UNIT)));
797 break; }
798 case HW_VAR_KEEP_ALIVE: {
799 u8 array[2];
800 array[0] = 0xff;
801 array[1] = *((u8 *)val);
802 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
803 array);
804 break; }
805 default:
806 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
807 "switch case not process %x\n", variable);
808 break;
809 }
810}
811
812static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
813{
814 struct rtl_priv *rtlpriv = rtl_priv(hw);
815 bool status = true;
816 long count = 0;
817 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
818 _LLT_OP(_LLT_WRITE_ACCESS);
819
820 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
821
822 do {
823 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
824 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
825 break;
826
827 if (count > POLLING_LLT_THRESHOLD) {
828 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
829 "Failed to polling write LLT done at address %d!\n",
830 address);
831 status = false;
832 break;
833 }
834 } while (++count);
835
836 return status;
837}
838
839static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
840{
841 struct rtl_priv *rtlpriv = rtl_priv(hw);
842 unsigned short i;
843 u8 txpktbuf_bndy;
844 u32 rqpn;
845 u8 maxpage;
846 bool status;
847
848 maxpage = 255;
849 txpktbuf_bndy = 0xF8;
850 rqpn = 0x80e70808;
851 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
852 txpktbuf_bndy = 0xFA;
853 rqpn = 0x80e90808;
854 }
855
856 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
857 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
858
859 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
860
861 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
862 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
863
864 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
865 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
866
867 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
868 status = _rtl8821ae_llt_write(hw, i, i + 1);
869 if (!status)
870 return status;
871 }
872
873 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
874 if (!status)
875 return status;
876
877 for (i = txpktbuf_bndy; i < maxpage; i++) {
878 status = _rtl8821ae_llt_write(hw, i, (i + 1));
879 if (!status)
880 return status;
881 }
882
883 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
884 if (!status)
885 return status;
886
887 rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
888
889 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
890
891 return true;
892}
893
894static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
895{
896 struct rtl_priv *rtlpriv = rtl_priv(hw);
897 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
898 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
899 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
900 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
901
902 if (rtlpriv->rtlhal.up_first_time)
903 return;
904
905 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
906 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
907 rtl8812ae_sw_led_on(hw, pled0);
908 else
909 rtl8821ae_sw_led_on(hw, pled0);
910 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
911 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
912 rtl8812ae_sw_led_on(hw, pled0);
913 else
914 rtl8821ae_sw_led_on(hw, pled0);
915 else
916 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
917 rtl8812ae_sw_led_off(hw, pled0);
918 else
919 rtl8821ae_sw_led_off(hw, pled0);
920}
921
922static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
923{
924 struct rtl_priv *rtlpriv = rtl_priv(hw);
925 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
926 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
927
928 u8 bytetmp = 0;
929 u16 wordtmp = 0;
930 bool mac_func_enable = rtlhal->mac_func_enable;
931
932 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
933
934 /*Auto Power Down to CHIP-off State*/
935 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
936 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
937
938 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
939 /* HW Power on sequence*/
940 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
941 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
942 RTL8812_NIC_ENABLE_FLOW)) {
943 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
944 "init 8812 MAC Fail as power on failure\n");
945 return false;
946 }
947 } else {
948 /* HW Power on sequence */
949 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
950 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
951 RTL8821A_NIC_ENABLE_FLOW)){
952 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
953 "init 8821 MAC Fail as power on failure\n");
954 return false;
955 }
956 }
957
958 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
959 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
960
961 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
962 bytetmp = 0xff;
963 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
964 mdelay(2);
965
966 bytetmp = 0xff;
967 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
968 mdelay(2);
969
970 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
971 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
972 if (bytetmp & BIT(0)) {
973 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
974 bytetmp |= BIT(6);
975 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
976 }
977 }
978
979 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
980 bytetmp &= ~BIT(4);
981 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
982
983 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
984
985 if (!mac_func_enable) {
986 if (!_rtl8821ae_llt_table_init(hw))
987 return false;
988 }
989
990 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
991 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
992
993 /* Enable FW Beamformer Interrupt */
994 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
995 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
996
997 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
998 wordtmp &= 0xf;
999 wordtmp |= 0xF5B1;
1000 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
1001
1002 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
1003 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1004 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1005 /*low address*/
1006 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1007 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1008 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1009 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1010 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1011 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1012 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1013 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1014 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1015 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1016 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1017 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1018 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1019 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1020 rtl_write_dword(rtlpriv, REG_RX_DESA,
1021 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1022
1023 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1024
1025 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1026
1027 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1028
1029 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1030 _rtl8821ae_gen_refresh_led_state(hw);
1031
1032 return true;
1033}
1034
1035static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1036{
1037 struct rtl_priv *rtlpriv = rtl_priv(hw);
1038 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1039 u32 reg_rrsr;
1040
1041 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1042
1043 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1044 /* ARFB table 9 for 11ac 5G 2SS */
1045 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1046 /* ARFB table 10 for 11ac 5G 1SS */
1047 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1048 /* ARFB table 11 for 11ac 24G 1SS */
1049 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1050 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1051 /* ARFB table 12 for 11ac 24G 1SS */
1052 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1053 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1054 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1055 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1056 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1057
1058 /*Set retry limit*/
1059 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1060
1061 /* Set Data / Response auto rate fallack retry count*/
1062 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1063 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1064 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1065 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1066
1067 rtlpci->reg_bcn_ctrl_val = 0x1d;
1068 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1069
1070 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1071 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1072
1073 /* AGGR_BK_TIME Reg51A 0x16 */
1074 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1075
1076 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1077 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1078
1079 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1080 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1081 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1082}
1083
1084static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1085{
1086 u16 ret = 0;
1087 u8 tmp = 0, count = 0;
1088
1089 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1090 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1091 count = 0;
1092 while (tmp && count < 20) {
1093 udelay(10);
1094 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1095 count++;
1096 }
1097 if (0 == tmp)
1098 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1099
1100 return ret;
1101}
1102
1103static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1104{
1105 u8 tmp = 0, count = 0;
1106
1107 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1108 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1109 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1110 count = 0;
1111 while (tmp && count < 20) {
1112 udelay(10);
1113 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1114 count++;
1115 }
1116}
1117
1118static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1119{
1120 u16 read_addr = addr & 0xfffc;
1121 u8 tmp = 0, count = 0, ret = 0;
1122
1123 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1124 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1125 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1126 count = 0;
1127 while (tmp && count < 20) {
1128 udelay(10);
1129 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1130 count++;
1131 }
1132 if (0 == tmp) {
1133 read_addr = REG_DBI_RDATA + addr % 4;
1134 ret = rtl_read_word(rtlpriv, read_addr);
1135 }
1136 return ret;
1137}
1138
1139static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1140{
1141 u8 tmp = 0, count = 0;
1142 u16 wrtie_addr, remainder = addr % 4;
1143
1144 wrtie_addr = REG_DBI_WDATA + remainder;
1145 rtl_write_byte(rtlpriv, wrtie_addr, data);
1146
1147 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1148 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1149
1150 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1151
1152 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1153 count = 0;
1154 while (tmp && count < 20) {
1155 udelay(10);
1156 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1157 count++;
1158 }
1159}
1160
1161static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1162{
1163 struct rtl_priv *rtlpriv = rtl_priv(hw);
1164 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1165 u8 tmp;
1166
1167 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1168 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1169 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1170
1171 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1172 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1173 }
1174
1175 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1176 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1177
1178 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1179 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1180
1181 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1182 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1183 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1184 }
1185}
1186
1187void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1188{
1189 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190 u8 sec_reg_value;
1191 u8 tmp;
1192
1193 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1194 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1195 rtlpriv->sec.pairwise_enc_algorithm,
1196 rtlpriv->sec.group_enc_algorithm);
1197
1198 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1199 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1200 "not open hw encryption\n");
1201 return;
1202 }
1203
1204 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1205
1206 if (rtlpriv->sec.use_defaultkey) {
1207 sec_reg_value |= SCR_TXUSEDK;
1208 sec_reg_value |= SCR_RXUSEDK;
1209 }
1210
1211 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1212
1213 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1214 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1215
1216 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1217 "The SECR-value %x\n", sec_reg_value);
1218
1219 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1220}
1221
1222/* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1223#define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1224#define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1225#define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1226#define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1227/* ----------------------------------------------------------- */
1228
1229static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1230{
1231 struct rtl_priv *rtlpriv = rtl_priv(hw);
1232 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1233 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1234 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1235
1236 rtlpriv->cfg->ops->set_hw_reg(hw,
1237 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1238
1239 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1240 "Initialize MacId media status: from %d to %d\n",
1241 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1242 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1243}
1244
1245static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1246{
1247 struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 u8 tmp;
1249
1250 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1251 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1252 if (!(tmp & BIT(2))) {
1253 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1254 mdelay(100);
1255 }
1256
1257 /* read reg 0x350 Bit[25] if 1 : RX hang */
1258 /* read reg 0x350 Bit[24] if 1 : TX hang */
1259 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1260 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1261 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1262 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1263 return true;
1264 } else {
1265 return false;
1266 }
1267}
1268
1269static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1270 bool mac_power_on,
1271 bool in_watchdog)
1272{
1273 struct rtl_priv *rtlpriv = rtl_priv(hw);
1274 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1275 u8 tmp;
1276 bool release_mac_rx_pause;
1277 u8 backup_pcie_dma_pause;
1278
1279 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1280
1281 /* 1. Disable register write lock. 0x1c[1] = 0 */
1282 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1283 tmp &= ~(BIT(1));
1284 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1285 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1286 /* write 0xCC bit[2] = 1'b1 */
1287 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1288 tmp |= BIT(2);
1289 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1290 }
1291
1292 /* 2. Check and pause TRX DMA */
1293 /* write 0x284 bit[18] = 1'b1 */
1294 /* write 0x301 = 0xFF */
1295 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1296 if (tmp & BIT(2)) {
1297 /* Already pause before the function for another purpose. */
1298 release_mac_rx_pause = false;
1299 } else {
1300 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1301 release_mac_rx_pause = true;
1302 }
1303 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1304 if (backup_pcie_dma_pause != 0xFF)
1305 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1306
1307 if (mac_power_on) {
1308 /* 3. reset TRX function */
1309 /* write 0x100 = 0x00 */
1310 rtl_write_byte(rtlpriv, REG_CR, 0);
1311 }
1312
1313 /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1314 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1315 tmp &= ~(BIT(0));
1316 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1317
1318 /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1319 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1320 tmp |= BIT(0);
1321 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1322
1323 if (mac_power_on) {
1324 /* 6. enable TRX function */
1325 /* write 0x100 = 0xFF */
1326 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1327
1328 /* We should init LLT & RQPN and
1329 * prepare Tx/Rx descrptor address later
1330 * because MAC function is reset.*/
1331 }
1332
1333 /* 7. Restore PCIe autoload down bit */
1334 /* 8812AE does not has the defination. */
1335 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1336 /* write 0xF8 bit[17] = 1'b1 */
1337 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1338 tmp |= BIT(1);
1339 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1340 }
1341
1342 /* In MAC power on state, BB and RF maybe in ON state,
1343 * if we release TRx DMA here.
1344 * it will cause packets to be started to Tx/Rx,
1345 * so we release Tx/Rx DMA later.*/
1346 if (!mac_power_on/* || in_watchdog*/) {
1347 /* 8. release TRX DMA */
1348 /* write 0x284 bit[18] = 1'b0 */
1349 /* write 0x301 = 0x00 */
1350 if (release_mac_rx_pause) {
1351 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1352 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1353 tmp & (~BIT(2)));
1354 }
1355 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1356 backup_pcie_dma_pause);
1357 }
1358
1359 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1360 /* 9. lock system register */
1361 /* write 0xCC bit[2] = 1'b0 */
1362 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1363 tmp &= ~(BIT(2));
1364 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1365 }
1366 return true;
1367}
1368
1369static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1370{
1371 struct rtl_priv *rtlpriv = rtl_priv(hw);
1372 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1373 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1374 u8 fw_reason = 0;
1375 struct timeval ts;
1376
1377 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1378
1379 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1380 fw_reason);
1381
1382 ppsc->wakeup_reason = 0;
1383
1384 rtlhal->last_suspend_sec = ts.tv_sec;
1385
1386 switch (fw_reason) {
1387 case FW_WOW_V2_PTK_UPDATE_EVENT:
1388 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1389 do_gettimeofday(&ts);
1390 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1391 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1392 "It's a WOL PTK Key update event!\n");
1393 break;
1394 case FW_WOW_V2_GTK_UPDATE_EVENT:
1395 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1396 do_gettimeofday(&ts);
1397 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1398 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1399 "It's a WOL GTK Key update event!\n");
1400 break;
1401 case FW_WOW_V2_DISASSOC_EVENT:
1402 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1403 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1404 "It's a disassociation event!\n");
1405 break;
1406 case FW_WOW_V2_DEAUTH_EVENT:
1407 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1408 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1409 "It's a deauth event!\n");
1410 break;
1411 case FW_WOW_V2_FW_DISCONNECT_EVENT:
1412 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1413 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1414 "It's a Fw disconnect decision (AP lost) event!\n");
1415 break;
1416 case FW_WOW_V2_MAGIC_PKT_EVENT:
1417 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1418 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1419 "It's a magic packet event!\n");
1420 break;
1421 case FW_WOW_V2_UNICAST_PKT_EVENT:
1422 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1423 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1424 "It's an unicast packet event!\n");
1425 break;
1426 case FW_WOW_V2_PATTERN_PKT_EVENT:
1427 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1428 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1429 "It's a pattern match event!\n");
1430 break;
1431 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1432 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1433 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1434 "It's an RTD3 Ssid match event!\n");
1435 break;
1436 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1437 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1438 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1439 "It's an RealWoW wake packet event!\n");
1440 break;
1441 case FW_WOW_V2_REALWOW_V2_ACKLOST:
1442 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1443 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1444 "It's an RealWoW ack lost event!\n");
1445 break;
1446 default:
1447 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1448 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1449 fw_reason);
1450 break;
1451 }
1452}
1453
1454static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1455{
1456 struct rtl_priv *rtlpriv = rtl_priv(hw);
1457 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1458
1459 /*low address*/
1460 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1461 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1462 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1463 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1464 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1465 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1466 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1467 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1468 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1469 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1470 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1471 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1472 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1473 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1474 rtl_write_dword(rtlpriv, REG_RX_DESA,
1475 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1476}
1477
1478static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1479{
1480 bool status = true;
1481 u32 i;
1482 u32 txpktbuf_bndy = boundary;
1483 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1484
1485 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1486 status = _rtl8821ae_llt_write(hw, i , i + 1);
1487 if (!status)
1488 return status;
1489 }
1490
1491 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1492 if (!status)
1493 return status;
1494
1495 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1496 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1497 if (!status)
1498 return status;
1499 }
1500
1501 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1502 txpktbuf_bndy);
1503 if (!status)
1504 return status;
1505
1506 return status;
1507}
1508
1509static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1510 u16 npq_rqpn_value, u32 rqpn_val)
1511{
1512 struct rtl_priv *rtlpriv = rtl_priv(hw);
1513 u8 tmp;
1514 bool ret = true;
1515 u16 count = 0, tmp16;
1516 bool support_remote_wakeup;
1517
1518 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1519 (u8 *)(&support_remote_wakeup));
1520
1521 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1522 "boundary=0x%#X, NPQ_RQPNValue=0x%#X, RQPNValue=0x%#X\n",
1523 boundary, npq_rqpn_value, rqpn_val);
1524
1525 /* stop PCIe DMA
1526 * 1. 0x301[7:0] = 0xFE */
1527 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1528
1529 /* wait TXFF empty
1530 * 2. polling till 0x41A[15:0]=0x07FF */
1531 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1532 while ((tmp16 & 0x07FF) != 0x07FF) {
1533 udelay(100);
1534 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1535 count++;
1536 if ((count % 200) == 0) {
1537 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1538 "Tx queue is not empty for 20ms!\n");
1539 }
1540 if (count >= 1000) {
1541 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1542 "Wait for Tx FIFO empty timeout!\n");
1543 break;
1544 }
1545 }
1546
1547 /* TX pause
1548 * 3. reg 0x522=0xFF */
1549 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1550
1551 /* Wait TX State Machine OK
1552 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1553 count = 0;
1554 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1555 udelay(100);
1556 count++;
1557 if (count >= 500) {
1558 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1559 "Wait for TX State Machine ready timeout !!\n");
1560 break;
1561 }
1562 }
1563
1564 /* stop RX DMA path
1565 * 5. 0x284[18] = 1
1566 * 6. wait till 0x284[17] == 1
1567 * wait RX DMA idle */
1568 count = 0;
1569 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1570 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1571 do {
1572 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1573 udelay(10);
1574 count++;
1575 } while (!(tmp & BIT(1)) && count < 100);
1576
1577 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1578 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1579 count, tmp);
1580
1581 /* reset BB
1582 * 7. 0x02 [0] = 0 */
1583 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1584 tmp &= ~(BIT(0));
1585 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1586
1587 /* Reset TRX MAC
1588 * 8. 0x100 = 0x00
1589 * Delay (1ms) */
1590 rtl_write_byte(rtlpriv, REG_CR, 0x00);
1591 udelay(1000);
1592
1593 /* Disable MAC Security Engine
1594 * 9. 0x100 bit[9]=0 */
1595 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1596 tmp &= ~(BIT(1));
1597 rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1598
1599 /* To avoid DD-Tim Circuit hang
1600 * 10. 0x553 bit[5]=1 */
1601 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1602 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1603
1604 /* Enable MAC Security Engine
1605 * 11. 0x100 bit[9]=1 */
1606 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1607 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1608
1609 /* Enable TRX MAC
1610 * 12. 0x100 = 0xFF
1611 * Delay (1ms) */
1612 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1613 udelay(1000);
1614
1615 /* Enable BB
1616 * 13. 0x02 [0] = 1 */
1617 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1618 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1619
1620 /* beacon setting
1621 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1622 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1623 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1624 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1625
1626 /* 16. WMAC_LBK_BF_HD 0x45D[7:0]
1627 * WMAC_LBK_BF_HD */
1628 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1629 (u8)boundary);
1630
1631 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1632
1633 /* init LLT
1634 * 17. init LLT */
1635 if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1636 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1637 "Failed to init LLT table!\n");
1638 return false;
1639 }
1640
1641 /* reallocate RQPN
1642 * 18. reallocate RQPN and init LLT */
1643 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1644 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1645
1646 /* release Tx pause
1647 * 19. 0x522=0x00 */
1648 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1649
1650 /* enable PCIE DMA
1651 * 20. 0x301[7:0] = 0x00
1652 * 21. 0x284[18] = 0 */
1653 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1654 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1655 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1656
1657 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1658 return ret;
1659}
1660
1661static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1662{
1663 struct rtl_priv *rtlpriv = rtl_priv(hw);
1664 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1665 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1666
1667#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1668 /* Re-download normal Fw. */
1669 rtl8821ae_set_fw_related_for_wowlan(hw, false);
1670#endif
1671
1672 /* Re-Initialize LLT table. */
1673 if (rtlhal->re_init_llt_table) {
1674 u32 rqpn = 0x80e70808;
1675 u8 rqpn_npq = 0, boundary = 0xF8;
1676 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1677 rqpn = 0x80e90808;
1678 boundary = 0xFA;
1679 }
1680 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1681 rtlhal->re_init_llt_table = false;
1682 }
1683
1684 ppsc->rfpwr_state = ERFON;
1685}
1686
1687static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1688{
1689 u8 tmp = 0;
1690 struct rtl_priv *rtlpriv = rtl_priv(hw);
1691
1692 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1693
1694 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1695 if (!(tmp & (BIT(2) | BIT(3)))) {
1696 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1697 "0x160(%#x)return!!\n", tmp);
1698 return;
1699 }
1700
1701 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1702 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1703
1704 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1705 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1706
1707 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1708}
1709
1710static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1711{
1712 u8 tmp = 0;
1713 struct rtl_priv *rtlpriv = rtl_priv(hw);
1714
1715 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1716
1717 /* Check 0x98[10] */
1718 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1719 if (!(tmp & BIT(2))) {
1720 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1721 "<---0x99(%#x) return!!\n", tmp);
1722 return;
1723 }
1724
1725 /* LTR idle latency, 0x90 for 144us */
1726 rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1727
1728 /* LTR active latency, 0x3c for 60us */
1729 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1730
1731 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1732 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1733
1734 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1735 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1736 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1737
1738 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1739}
1740
1741static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1742{
1743 struct rtl_priv *rtlpriv = rtl_priv(hw);
1744 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1745 bool init_finished = true;
1746 u8 tmp = 0;
1747
1748 /* Get Fw wake up reason. */
1749 _rtl8821ae_get_wakeup_reason(hw);
1750
1751 /* Patch Pcie Rx DMA hang after S3/S4 several times.
1752 * The root cause has not be found. */
1753 if (_rtl8821ae_check_pcie_dma_hang(hw))
1754 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1755
1756 /* Prepare Tx/Rx Desc Hw address. */
1757 _rtl8821ae_init_trx_desc_hw_address(hw);
1758
1759 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1760 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1761 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1762
1763 /* Check wake up event.
1764 * We should check wake packet bit before disable wowlan by H2C or
1765 * Fw will clear the bit. */
1766 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1767 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1768 "Read REG_FTISR 0x13f = %#X\n", tmp);
1769
1770 /* Set the WoWLAN related function control disable. */
1771 rtl8821ae_set_fw_wowlan_mode(hw, false);
1772 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1773
1774 if (rtlhal->hw_rof_enable) {
1775 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1776 if (tmp & BIT(1)) {
1777 /* Clear GPIO9 ISR */
1778 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1779 init_finished = false;
1780 } else {
1781 init_finished = true;
1782 }
1783 }
1784
1785 if (init_finished) {
1786 _rtl8821ae_simple_initialize_adapter(hw);
1787
1788 /* Release Pcie Interface Tx DMA. */
1789 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1790 /* Release Pcie RX DMA */
1791 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1792
1793 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1794 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1795
1796 _rtl8821ae_enable_l1off(hw);
1797 _rtl8821ae_enable_ltr(hw);
1798 }
1799
1800 return init_finished;
1801}
1802
1803static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1804{
1805 /* BB OFDM RX Path_A */
1806 rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1807 /* BB OFDM TX Path_A */
1808 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1809 /* BB CCK R/Rx Path_A */
1810 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1811 /* MCS support */
1812 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1813 /* RF Path_B HSSI OFF */
1814 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1815 /* RF Path_B Power Down */
1816 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1817 /* ADDA Path_B OFF */
1818 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1819 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1820}
1821
1822static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1823{
1824 struct rtl_priv *rtlpriv = rtl_priv(hw);
1825 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1826 u8 u1b_tmp;
1827
1828 rtlhal->mac_func_enable = false;
1829
1830 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1831 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1832 /* 1. Run LPS WL RFOFF flow */
1833 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1834 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1835 */
1836 rtl_hal_pwrseqcmdparsing(rtlpriv,
1837 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1838 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1839 }
1840 /* 2. 0x1F[7:0] = 0 */
1841 /* turn off RF */
1842 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1843 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1844 rtlhal->fw_ready) {
1845 rtl8821ae_firmware_selfreset(hw);
1846 }
1847
1848 /* Reset MCU. Suggested by Filen. */
1849 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1850 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1851
1852 /* g. MCUFWDL 0x80[1:0]=0 */
1853 /* reset MCU ready status */
1854 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1855
1856 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1857 /* HW card disable configuration. */
1858 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1859 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1860 } else {
1861 /* HW card disable configuration. */
1862 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1863 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1864 }
1865
1866 /* Reset MCU IO Wrapper */
1867 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1868 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1869 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1870 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1871
1872 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1873 /* lock ISO/CLK/Power control register */
1874 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1875}
1876
1877int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1878{
1879 struct rtl_priv *rtlpriv = rtl_priv(hw);
1880 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1881 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1882 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1883 bool rtstatus = true;
1884 int err;
1885 u8 tmp_u1b;
1886 bool support_remote_wakeup;
1887 u32 nav_upper = WIFI_NAV_UPPER_US;
1888
1889 rtlhal->being_init_adapter = true;
1890 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1891 (u8 *)(&support_remote_wakeup));
1892 rtlpriv->intf_ops->disable_aspm(hw);
1893
1894 /*YP wowlan not considered*/
1895
1896 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1897 if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1898 rtlhal->mac_func_enable = true;
1899 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1900 "MAC has already power on.\n");
1901 } else {
1902 rtlhal->mac_func_enable = false;
1903 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1904 }
1905
1906 if (support_remote_wakeup &&
1907 rtlhal->wake_from_pnp_sleep &&
1908 rtlhal->mac_func_enable) {
1909 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1910 rtlhal->being_init_adapter = false;
1911 return 0;
1912 }
1913 }
1914
1915 if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1916 _rtl8821ae_reset_pcie_interface_dma(hw,
1917 rtlhal->mac_func_enable,
1918 false);
1919 rtlhal->mac_func_enable = false;
1920 }
1921
1922 /* Reset MAC/BB/RF status if it is not powered off
1923 * before calling initialize Hw flow to prevent
1924 * from interface and MAC status mismatch.
1925 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1926 if (rtlhal->mac_func_enable) {
1927 _rtl8821ae_poweroff_adapter(hw);
1928 rtlhal->mac_func_enable = false;
1929 }
1930
1931 rtstatus = _rtl8821ae_init_mac(hw);
1932 if (rtstatus != true) {
1933 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1934 err = 1;
1935 return err;
1936 }
1937
1938 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1939 tmp_u1b &= 0x7F;
1940 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1941
1942 err = rtl8821ae_download_fw(hw, false);
1943 if (err) {
1944 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1945 "Failed to download FW. Init HW without FW now\n");
1946 err = 1;
1947 rtlhal->fw_ready = false;
1948 return err;
1949 } else {
1950 rtlhal->fw_ready = true;
1951 }
1952 ppsc->fw_current_inpsmode = false;
1953 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1954 rtlhal->fw_clk_change_in_progress = false;
1955 rtlhal->allow_sw_to_change_hwclc = false;
1956 rtlhal->last_hmeboxnum = 0;
1957
1958 /*SIC_Init(Adapter);
1959 if(rtlhal->AMPDUBurstMode)
1960 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1961
1962 rtl8821ae_phy_mac_config(hw);
1963 /* because last function modify RCR, so we update
1964 * rcr var here, or TP will unstable for receive_config
1965 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1966 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1967 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1968 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1969 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1970 rtl8821ae_phy_bb_config(hw);
1971
1972 rtl8821ae_phy_rf_config(hw);
1973
1974 if (rtlpriv->phy.rf_type == RF_1T1R &&
1975 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1976 _rtl8812ae_bb8812_config_1t(hw);
1977
1978 _rtl8821ae_hw_configure(hw);
1979
1980 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1981
1982 /*set wireless mode*/
1983
1984 rtlhal->mac_func_enable = true;
1985
1986 rtl_cam_reset_all_entry(hw);
1987
1988 rtl8821ae_enable_hw_security_config(hw);
1989
1990 ppsc->rfpwr_state = ERFON;
1991
1992 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1993 _rtl8821ae_enable_aspm_back_door(hw);
1994 rtlpriv->intf_ops->enable_aspm(hw);
1995
1996 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1997 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1998 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1999
2000 rtl8821ae_bt_hw_init(hw);
2001 rtlpriv->rtlhal.being_init_adapter = false;
2002
2003 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2004
2005 /* rtl8821ae_dm_check_txpower_tracking(hw); */
2006 /* rtl8821ae_phy_lc_calibrate(hw); */
2007 if (support_remote_wakeup)
2008 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2009
2010 /* Release Rx DMA*/
2011 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2012 if (tmp_u1b & BIT(2)) {
2013 /* Release Rx DMA if needed*/
2014 tmp_u1b &= ~BIT(2);
2015 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2016 }
2017
2018 /* Release Tx/Rx PCIE DMA if*/
2019 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2020
2021 rtl8821ae_dm_init(hw);
2022 rtl8821ae_macid_initialize_mediastatus(hw);
2023
2024 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2025 return err;
2026}
2027
2028static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2029{
2030 struct rtl_priv *rtlpriv = rtl_priv(hw);
2031 struct rtl_phy *rtlphy = &rtlpriv->phy;
2032 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2033 enum version_8821ae version = VERSION_UNKNOWN;
2034 u32 value32;
2035
2036 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2037 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2038 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2039
2040 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2041 rtlphy->rf_type = RF_2T2R;
2042 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2043 rtlphy->rf_type = RF_1T1R;
2044
2045 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2046 "RF_Type is %x!!\n", rtlphy->rf_type);
2047
2048 if (value32 & TRP_VAUX_EN) {
2049 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2050 if (rtlphy->rf_type == RF_2T2R)
2051 version = VERSION_TEST_CHIP_2T2R_8812;
2052 else
2053 version = VERSION_TEST_CHIP_1T1R_8812;
2054 } else
2055 version = VERSION_TEST_CHIP_8821;
2056 } else {
2057 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2058 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2059
2060 if (rtlphy->rf_type == RF_2T2R)
2061 version =
2062 (enum version_8821ae)(CHIP_8812
2063 | NORMAL_CHIP |
2064 RF_TYPE_2T2R);
2065 else
2066 version = (enum version_8821ae)(CHIP_8812
2067 | NORMAL_CHIP);
2068
2069 version = (enum version_8821ae)(version | (rtl_id << 12));
2070 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2071 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2072
2073 version = (enum version_8821ae)(CHIP_8821
2074 | NORMAL_CHIP | rtl_id);
2075 }
2076 }
2077
2078 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2079 /*WL_HWROF_EN.*/
2080 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2081 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2082 }
2083
2084 switch (version) {
2085 case VERSION_TEST_CHIP_1T1R_8812:
2086 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2087 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2088 break;
2089 case VERSION_TEST_CHIP_2T2R_8812:
2090 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2092 break;
2093 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2094 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2096 break;
2097 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2098 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2099 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2100 break;
2101 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2104 break;
2105 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2106 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2108 break;
2109 case VERSION_TEST_CHIP_8821:
2110 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2112 break;
2113 case VERSION_NORMAL_TSMC_CHIP_8821:
2114 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2115 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2116 break;
2117 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2118 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2119 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2120 break;
2121 default:
2122 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2123 "Chip Version ID: Unknow (0x%X)\n", version);
2124 break;
2125 }
2126
2127 return version;
2128}
2129
2130static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2131 enum nl80211_iftype type)
2132{
2133 struct rtl_priv *rtlpriv = rtl_priv(hw);
2134 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2135 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2136 bt_msr &= 0xfc;
2137
2138 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2139 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2140 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2141
2142 if (type == NL80211_IFTYPE_UNSPECIFIED ||
2143 type == NL80211_IFTYPE_STATION) {
2144 _rtl8821ae_stop_tx_beacon(hw);
2145 _rtl8821ae_enable_bcn_sub_func(hw);
2146 } else if (type == NL80211_IFTYPE_ADHOC ||
2147 type == NL80211_IFTYPE_AP) {
2148 _rtl8821ae_resume_tx_beacon(hw);
2149 _rtl8821ae_disable_bcn_sub_func(hw);
2150 } else {
2151 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2152 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2153 type);
2154 }
2155
2156 switch (type) {
2157 case NL80211_IFTYPE_UNSPECIFIED:
2158 bt_msr |= MSR_NOLINK;
2159 ledaction = LED_CTL_LINK;
2160 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2161 "Set Network type to NO LINK!\n");
2162 break;
2163 case NL80211_IFTYPE_ADHOC:
2164 bt_msr |= MSR_ADHOC;
2165 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2166 "Set Network type to Ad Hoc!\n");
2167 break;
2168 case NL80211_IFTYPE_STATION:
2169 bt_msr |= MSR_INFRA;
2170 ledaction = LED_CTL_LINK;
2171 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2172 "Set Network type to STA!\n");
2173 break;
2174 case NL80211_IFTYPE_AP:
2175 bt_msr |= MSR_AP;
2176 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2177 "Set Network type to AP!\n");
2178 break;
2179 default:
2180 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2181 "Network type %d not support!\n", type);
2182 return 1;
2183 }
2184
2185 rtl_write_byte(rtlpriv, (MSR), bt_msr);
2186 rtlpriv->cfg->ops->led_control(hw, ledaction);
2187 if ((bt_msr & 0xfc) == MSR_AP)
2188 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2189 else
2190 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2191
2192 return 0;
2193}
2194
2195void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2196{
2197 struct rtl_priv *rtlpriv = rtl_priv(hw);
2198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2199 u32 reg_rcr = rtlpci->receive_config;
2200
2201 if (rtlpriv->psc.rfpwr_state != ERFON)
2202 return;
2203
2204 if (check_bssid) {
2205 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2207 (u8 *)(&reg_rcr));
2208 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2209 } else if (!check_bssid) {
2210 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2211 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2212 rtlpriv->cfg->ops->set_hw_reg(hw,
2213 HW_VAR_RCR, (u8 *)(&reg_rcr));
2214 }
2215}
2216
2217int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2218{
2219 struct rtl_priv *rtlpriv = rtl_priv(hw);
2220
2221 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2222
2223 if (_rtl8821ae_set_media_status(hw, type))
2224 return -EOPNOTSUPP;
2225
2226 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2227 if (type != NL80211_IFTYPE_AP)
2228 rtl8821ae_set_check_bssid(hw, true);
2229 } else {
2230 rtl8821ae_set_check_bssid(hw, false);
2231 }
2232
2233 return 0;
2234}
2235
2236/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2237void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2238{
2239 struct rtl_priv *rtlpriv = rtl_priv(hw);
2240 rtl8821ae_dm_init_edca_turbo(hw);
2241 switch (aci) {
2242 case AC1_BK:
2243 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2244 break;
2245 case AC0_BE:
2246 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2247 break;
2248 case AC2_VI:
2249 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2250 break;
2251 case AC3_VO:
2252 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2253 break;
2254 default:
2255 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2256 break;
2257 }
2258}
2259
2260static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2261{
2262 struct rtl_priv *rtlpriv = rtl_priv(hw);
2263 u32 tmp;
2264 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2265 /*printk("clear interrupt first:\n");
2266 printk("0x%x = 0x%08x\n",REG_HISR, tmp);*/
2267 rtl_write_dword(rtlpriv, REG_HISR, tmp);
2268
2269 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2270 /*printk("0x%x = 0x%08x\n",REG_HISRE, tmp);*/
2271 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2272
2273 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2274 /*printk("0x%x = 0x%08x\n",REG_HSISR, tmp);*/
2275 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2276}
2277
2278void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2279{
2280 struct rtl_priv *rtlpriv = rtl_priv(hw);
2281 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2282
2283 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2284
2285 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2286 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2287 rtlpci->irq_enabled = true;
2288 /* there are some C2H CMDs have been sent before
2289 system interrupt is enabled, e.g., C2H, CPWM.
2290 *So we need to clear all C2H events that FW has
2291 notified, otherwise FW won't schedule any commands anymore.
2292 */
2293 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2294 /*enable system interrupt*/
2295 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2296}
2297
2298void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2299{
2300 struct rtl_priv *rtlpriv = rtl_priv(hw);
2301 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2302
2303 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2304 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2305 rtlpci->irq_enabled = false;
2306 /*synchronize_irq(rtlpci->pdev->irq);*/
2307}
2308
2309static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2310{
2311 struct rtl_priv *rtlpriv = rtl_priv(hw);
2312 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2313 u16 cap_hdr;
2314 u8 cap_pointer;
2315 u8 cap_id = 0xff;
2316 u8 pmcs_reg;
2317 u8 cnt = 0;
2318
2319 /* Get the Capability pointer first,
2320 * the Capability Pointer is located at
2321 * offset 0x34 from the Function Header */
2322
2323 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2324 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2325 "PCI configration 0x34 = 0x%2x\n", cap_pointer);
2326
2327 do {
2328 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2329 cap_id = cap_hdr & 0xFF;
2330
2331 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2332 "in pci configration, cap_pointer%x = %x\n",
2333 cap_pointer, cap_id);
2334
2335 if (cap_id == 0x01) {
2336 break;
2337 } else {
2338 /* point to next Capability */
2339 cap_pointer = (cap_hdr >> 8) & 0xFF;
2340 /* 0: end of pci capability, 0xff: invalid value */
2341 if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2342 cap_id = 0xff;
2343 break;
2344 }
2345 }
2346 } while (cnt++ < 200);
2347
2348 if (cap_id == 0x01) {
2349 /* Get the PM CSR (Control/Status Register),
2350 * The PME_Status is located at PM Capatibility offset 5, bit 7
2351 */
2352 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2353
2354 if (pmcs_reg & BIT(7)) {
2355 /* PME event occured, clear the PM_Status by write 1 */
2356 pmcs_reg = pmcs_reg | BIT(7);
2357
2358 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2359 pmcs_reg);
2360 /* Read it back to check */
2361 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2362 &pmcs_reg);
2363 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2364 "Clear PME status 0x%2x to 0x%2x\n",
2365 cap_pointer + 5, pmcs_reg);
2366 } else {
2367 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2368 "PME status(0x%2x) = 0x%2x\n",
2369 cap_pointer + 5, pmcs_reg);
2370 }
2371 } else {
2372 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2373 "Cannot find PME Capability\n");
2374 }
2375}
2376
2377void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2378{
2379 struct rtl_priv *rtlpriv = rtl_priv(hw);
2380 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2381 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2382 struct rtl_mac *mac = rtl_mac(rtlpriv);
2383 enum nl80211_iftype opmode;
2384 bool support_remote_wakeup;
2385 u8 tmp;
2386 u32 count = 0;
2387
2388 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2389 (u8 *)(&support_remote_wakeup));
2390
2391 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2392
2393 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2394 || !rtlhal->enter_pnp_sleep) {
2395 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2396 mac->link_state = MAC80211_NOLINK;
2397 opmode = NL80211_IFTYPE_UNSPECIFIED;
2398 _rtl8821ae_set_media_status(hw, opmode);
2399 _rtl8821ae_poweroff_adapter(hw);
2400 } else {
2401 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2402 /* 3 <1> Prepare for configuring wowlan related infomations */
2403 /* Clear Fw WoWLAN event. */
2404 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2405
2406#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2407 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2408#endif
2409 /* Dynamically adjust Tx packet boundary
2410 * for download reserved page packet.
2411 * reserve 30 pages for rsvd page */
2412 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2413 rtlhal->re_init_llt_table = true;
2414
2415 /* 3 <2> Set Fw releted H2C cmd. */
2416
2417 /* Set WoWLAN related security information. */
2418 rtl8821ae_set_fw_global_info_cmd(hw);
2419
2420 _rtl8821ae_download_rsvd_page(hw, true);
2421
2422 /* Just enable AOAC related functions when we connect to AP. */
2423 printk("mac->link_state = %d\n", mac->link_state);
2424 if (mac->link_state >= MAC80211_LINKED &&
2425 mac->opmode == NL80211_IFTYPE_STATION) {
2426 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2427 rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2428 RT_MEDIA_CONNECT);
2429
2430 rtl8821ae_set_fw_wowlan_mode(hw, true);
2431 /* Enable Fw Keep alive mechanism. */
2432 rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2433
2434 /* Enable disconnect decision control. */
2435 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2436 }
2437
2438 /* 3 <3> Hw Configutations */
2439
2440 /* Wait untill Rx DMA Finished before host sleep.
2441 * FW Pause Rx DMA may happens when received packet doing dma.
2442 */
2443 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2444
2445 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2446 count = 0;
2447 while (!(tmp & BIT(1)) && (count++ < 100)) {
2448 udelay(10);
2449 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2450 }
2451 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2452 "Wait Rx DMA Finished before host sleep. count=%d\n",
2453 count);
2454
2455 /* reset trx ring */
2456 rtlpriv->intf_ops->reset_trx_ring(hw);
2457
2458 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2459
2460 _rtl8821ae_clear_pci_pme_status(hw);
2461 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2462 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2463 /* prevent 8051 to be reset by PERST */
2464 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2465 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2466 }
2467
2468 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2469 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2470 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2471 /* For wowlan+LPS+32k. */
2472 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2473 /* Set the WoWLAN related function control enable.
2474 * It should be the last H2C cmd in the WoWLAN flow. */
2475 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2476
2477 /* Stop Pcie Interface Tx DMA. */
2478 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2479 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2480
2481 /* Wait for TxDMA idle. */
2482 count = 0;
2483 do {
2484 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2485 udelay(10);
2486 count++;
2487 } while ((tmp != 0) && (count < 100));
2488 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2489 "Wait Tx DMA Finished before host sleep. count=%d\n",
2490 count);
2491
2492 if (rtlhal->hw_rof_enable) {
2493 printk("hw_rof_enable\n");
2494 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2495 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2496 }
2497 }
2498 /* after power off we should do iqk again */
2499 rtlpriv->phy.iqk_initialized = false;
2500}
2501
2502void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2503 u32 *p_inta, u32 *p_intb)
2504{
2505 struct rtl_priv *rtlpriv = rtl_priv(hw);
2506 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2507
2508 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2509 rtl_write_dword(rtlpriv, ISR, *p_inta);
2510
2511 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2512 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2513}
2514
2515void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2516{
2517 struct rtl_priv *rtlpriv = rtl_priv(hw);
2518 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2519 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2520 u16 bcn_interval, atim_window;
2521
2522 bcn_interval = mac->beacon_interval;
2523 atim_window = 2; /*FIX MERGE */
2524 rtl8821ae_disable_interrupt(hw);
2525 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2526 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2527 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2528 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2529 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2530 rtl_write_byte(rtlpriv, 0x606, 0x30);
2531 rtlpci->reg_bcn_ctrl_val |= BIT(3);
2532 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2533 rtl8821ae_enable_interrupt(hw);
2534}
2535
2536void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2537{
2538 struct rtl_priv *rtlpriv = rtl_priv(hw);
2539 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2540 u16 bcn_interval = mac->beacon_interval;
2541
2542 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2543 "beacon_interval:%d\n", bcn_interval);
2544 rtl8821ae_disable_interrupt(hw);
2545 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2546 rtl8821ae_enable_interrupt(hw);
2547}
2548
2549void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2550 u32 add_msr, u32 rm_msr)
2551{
2552 struct rtl_priv *rtlpriv = rtl_priv(hw);
2553 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2554
2555 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2556 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2557
2558 if (add_msr)
2559 rtlpci->irq_mask[0] |= add_msr;
2560 if (rm_msr)
2561 rtlpci->irq_mask[0] &= (~rm_msr);
2562 rtl8821ae_disable_interrupt(hw);
2563 rtl8821ae_enable_interrupt(hw);
2564}
2565
2566static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2567{
2568 u8 group = 0;
2569
2570 if (chnl <= 14) {
2571 if (1 <= chnl && chnl <= 2)
2572 group = 0;
2573 else if (3 <= chnl && chnl <= 5)
2574 group = 1;
2575 else if (6 <= chnl && chnl <= 8)
2576 group = 2;
2577 else if (9 <= chnl && chnl <= 11)
2578 group = 3;
2579 else /*if (12 <= chnl && chnl <= 14)*/
2580 group = 4;
2581 } else {
2582 if (36 <= chnl && chnl <= 42)
2583 group = 0;
2584 else if (44 <= chnl && chnl <= 48)
2585 group = 1;
2586 else if (50 <= chnl && chnl <= 58)
2587 group = 2;
2588 else if (60 <= chnl && chnl <= 64)
2589 group = 3;
2590 else if (100 <= chnl && chnl <= 106)
2591 group = 4;
2592 else if (108 <= chnl && chnl <= 114)
2593 group = 5;
2594 else if (116 <= chnl && chnl <= 122)
2595 group = 6;
2596 else if (124 <= chnl && chnl <= 130)
2597 group = 7;
2598 else if (132 <= chnl && chnl <= 138)
2599 group = 8;
2600 else if (140 <= chnl && chnl <= 144)
2601 group = 9;
2602 else if (149 <= chnl && chnl <= 155)
2603 group = 10;
2604 else if (157 <= chnl && chnl <= 161)
2605 group = 11;
2606 else if (165 <= chnl && chnl <= 171)
2607 group = 12;
2608 else if (173 <= chnl && chnl <= 177)
2609 group = 13;
2610 else
2611 /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2612 "5G, Channel %d in Group not found\n",chnl);*/
2613 RT_ASSERT(!COMP_EFUSE,
2614 "5G, Channel %d in Group not found\n", chnl);
2615 }
2616 return group;
2617}
2618
2619static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2620 struct txpower_info_2g *pwrinfo24g,
2621 struct txpower_info_5g *pwrinfo5g,
2622 bool autoload_fail,
2623 u8 *hwinfo)
2624{
2625 struct rtl_priv *rtlpriv = rtl_priv(hw);
2626 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2627
2628 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2629 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2630 (eeAddr+1), hwinfo[eeAddr+1]);
2631 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/
2632 autoload_fail = true;
2633
2634 if (autoload_fail) {
2635 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2636 "auto load fail : Use Default value!\n");
2637 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2638 /*2.4G default value*/
2639 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2640 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2641 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2642 }
2643 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2644 if (TxCount == 0) {
2645 pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2646 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2647 } else {
2648 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2649 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2650 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2651 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2652 }
2653 }
2654 /*5G default value*/
2655 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2656 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2657
2658 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2659 if (TxCount == 0) {
2660 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2661 pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2662 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2663 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2664 } else {
2665 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2666 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2667 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2668 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2669 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2670 }
2671 }
2672 }
2673 return;
2674 }
2675
2676 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2677
2678 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2679 /*2.4G default value*/
2680 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2681 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2682 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2683 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2684 }
2685 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2686 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2687 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2688 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2689 }
2690 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2691 if (TxCount == 0) {
2692 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2693 /*bit sign number to 8 bit sign number*/
2694 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2695 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2696 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2697 /*bit sign number to 8 bit sign number*/
2698 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2699 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2700 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2701
2702 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2703 eeAddr++;
2704 } else {
2705 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2706 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2707 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2708
2709 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2710 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2711 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2712
2713 eeAddr++;
2714
2715 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2716 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2717 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2718
2719 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2720 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2721 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2722
2723 eeAddr++;
2724 }
2725 }
2726
2727 /*5G default value*/
2728 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2729 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2730 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2731 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2732 }
2733
2734 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2735 if (TxCount == 0) {
2736 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2737
2738 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2739 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2740 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2741
2742 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2743 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2744 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2745
2746 eeAddr++;
2747 } else {
2748 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2749 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2750 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2751
2752 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2753 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2754 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2755
2756 eeAddr++;
2757 }
2758 }
2759
2760 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4;
2761 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f);
2762
2763 eeAddr++;
2764
2765 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2766
2767 eeAddr++;
2768
2769 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2770 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2771 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2772 }
2773 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2774 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2775 /* 4bit sign number to 8 bit sign number */
2776 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2777 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2778 /* 4bit sign number to 8 bit sign number */
2779 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2780 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2781 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2782
2783 eeAddr++;
2784 }
2785 }
2786}
2787#if 0
2788static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2789 bool autoload_fail,
2790 u8 *hwinfo)
2791{
2792 struct rtl_priv *rtlpriv = rtl_priv(hw);
2793 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2794 struct txpower_info_2g pwrinfo24g;
2795 struct txpower_info_5g pwrinfo5g;
2796 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2797 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2798 56, 58, 60, 62, 64, 100, 102, 104, 106,
2799 108, 110, 112, 114, 116, 118, 120, 122,
2800 124, 126, 128, 130, 132, 134, 136, 138,
2801 140, 142, 144, 149, 151, 153, 155, 157,
2802 159, 161, 163, 165, 167, 168, 169, 171, 173, 175, 177};
2803 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2804 u8 rf_path, index;
2805 u8 i;
2806
2807 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2808 &pwrinfo5g, autoload_fail, hwinfo);
2809
2810 for (rf_path = 0; rf_path < 2; rf_path++) {
2811 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2812 index = _rtl8821ae_get_chnl_group(i + 1);
2813
2814 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2815 rtlefuse->txpwrlevel_cck[rf_path][i] =
2816 pwrinfo24g.index_cck_base[rf_path][5];
2817 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2818 pwrinfo24g.index_bw40_base[rf_path][index];
2819 } else {
2820 rtlefuse->txpwrlevel_cck[rf_path][i] =
2821 pwrinfo24g.index_cck_base[rf_path][index];
2822 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2823 pwrinfo24g.index_bw40_base[rf_path][index];
2824 }
2825 }
2826
2827 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2828 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2829 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2830 pwrinfo5g.index_bw40_base[rf_path][index];
2831 }
2832 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2833 u8 upper, lower;
2834 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2835 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2836 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2837
2838 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2839 }
2840 for (i = 0; i < MAX_TX_COUNT; i++) {
2841 rtlefuse->txpwr_cckdiff[rf_path][i] =
2842 pwrinfo24g.cck_diff[rf_path][i];
2843 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2844 pwrinfo24g.ofdm_diff[rf_path][i];
2845 rtlefuse->txpwr_ht20diff[rf_path][i] =
2846 pwrinfo24g.bw20_diff[rf_path][i];
2847 rtlefuse->txpwr_ht40diff[rf_path][i] =
2848 pwrinfo24g.bw40_diff[rf_path][i];
2849
2850 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2851 pwrinfo5g.ofdm_diff[rf_path][i];
2852 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2853 pwrinfo5g.bw20_diff[rf_path][i];
2854 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2855 pwrinfo5g.bw40_diff[rf_path][i];
2856 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2857 pwrinfo5g.bw80_diff[rf_path][i];
2858 }
2859 }
2860
2861 if (!autoload_fail) {
2862 rtlefuse->eeprom_regulatory =
2863 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2864 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2865 rtlefuse->eeprom_regulatory = 0;
2866 } else {
2867 rtlefuse->eeprom_regulatory = 0;
2868 }
2869
2870 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2871 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2872}
2873#endif
2874static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2875 bool autoload_fail,
2876 u8 *hwinfo)
2877{
2878 struct rtl_priv *rtlpriv = rtl_priv(hw);
2879 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2880 struct txpower_info_2g pwrinfo24g;
2881 struct txpower_info_5g pwrinfo5g;
2882 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2883 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2884 56, 58, 60, 62, 64, 100, 102, 104, 106,
2885 108, 110, 112, 114, 116, 118, 120, 122,
2886 124, 126, 128, 130, 132, 134, 136, 138,
2887 140, 142, 144, 149, 151, 153, 155, 157,
2888 159, 161, 163, 165, 167, 168, 169, 171,
2889 173, 175, 177};
2890 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2891 42, 58, 106, 122, 138, 155, 171};
2892 u8 rf_path, index;
2893 u8 i;
2894
2895 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2896 &pwrinfo5g, autoload_fail, hwinfo);
2897
2898 for (rf_path = 0; rf_path < 2; rf_path++) {
2899 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2900 index = _rtl8821ae_get_chnl_group(i + 1);
2901
2902 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2903 rtlefuse->txpwrlevel_cck[rf_path][i] =
2904 pwrinfo24g.index_cck_base[rf_path][5];
2905 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2906 pwrinfo24g.index_bw40_base[rf_path][index];
2907 } else {
2908 rtlefuse->txpwrlevel_cck[rf_path][i] =
2909 pwrinfo24g.index_cck_base[rf_path][index];
2910 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2911 pwrinfo24g.index_bw40_base[rf_path][index];
2912 }
2913 }
2914
2915 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2916 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2917 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2918 pwrinfo5g.index_bw40_base[rf_path][index];
2919 }
2920 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2921 u8 upper, lower;
2922 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2923 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2924 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2925
2926 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2927 }
2928 for (i = 0; i < MAX_TX_COUNT; i++) {
2929 rtlefuse->txpwr_cckdiff[rf_path][i] =
2930 pwrinfo24g.cck_diff[rf_path][i];
2931 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2932 pwrinfo24g.ofdm_diff[rf_path][i];
2933 rtlefuse->txpwr_ht20diff[rf_path][i] =
2934 pwrinfo24g.bw20_diff[rf_path][i];
2935 rtlefuse->txpwr_ht40diff[rf_path][i] =
2936 pwrinfo24g.bw40_diff[rf_path][i];
2937
2938 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2939 pwrinfo5g.ofdm_diff[rf_path][i];
2940 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2941 pwrinfo5g.bw20_diff[rf_path][i];
2942 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2943 pwrinfo5g.bw40_diff[rf_path][i];
2944 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2945 pwrinfo5g.bw80_diff[rf_path][i];
2946 }
2947 }
2948 /*bit0~2*/
2949 if (!autoload_fail) {
2950 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2951 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2952 rtlefuse->eeprom_regulatory = 0;
2953 } else {
2954 rtlefuse->eeprom_regulatory = 0;
2955 }
2956
2957 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2958 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2959}
2960
2961static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2962 bool autoload_fail)
2963{
2964 struct rtl_priv *rtlpriv = rtl_priv(hw);
2965 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2966
2967 if (!autoload_fail) {
2968 rtlhal->pa_type_2g = hwinfo[0xBC];
2969 rtlhal->lna_type_2g = hwinfo[0xBD];
2970 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2971 rtlhal->pa_type_2g = 0;
2972 rtlhal->lna_type_2g = 0;
2973 }
2974 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2975 (rtlhal->pa_type_2g & BIT(4))) ?
2976 1 : 0;
2977 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2978 (rtlhal->lna_type_2g & BIT(3))) ?
2979 1 : 0;
2980
2981 rtlhal->pa_type_5g = hwinfo[0xBC];
2982 rtlhal->lna_type_5g = hwinfo[0xBF];
2983 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2984 rtlhal->pa_type_5g = 0;
2985 rtlhal->lna_type_5g = 0;
2986 }
2987 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2988 (rtlhal->pa_type_5g & BIT(0))) ?
2989 1 : 0;
2990 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2991 (rtlhal->lna_type_5g & BIT(3))) ?
2992 1 : 0;
2993 } else {
2994 rtlhal->external_pa_2g = 0;
2995 rtlhal->external_lna_2g = 0;
2996 rtlhal->external_pa_5g = 0;
2997 rtlhal->external_lna_5g = 0;
2998 }
2999}
3000
3001static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
3002 bool autoload_fail)
3003{
3004 struct rtl_priv *rtlpriv = rtl_priv(hw);
3005 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3006
3007 if (!autoload_fail) {
3008 rtlhal->pa_type_2g = hwinfo[0xBC];
3009 rtlhal->lna_type_2g = hwinfo[0xBD];
3010 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
3011 rtlhal->pa_type_2g = 0;
3012 rtlhal->lna_type_2g = 0;
3013 }
3014 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
3015 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
3016
3017 rtlhal->pa_type_5g = hwinfo[0xBC];
3018 rtlhal->lna_type_5g = hwinfo[0xBF];
3019 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3020 rtlhal->pa_type_5g = 0;
3021 rtlhal->lna_type_5g = 0;
3022 }
3023 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3024 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3025 } else {
3026 rtlhal->external_pa_2g = 0;
3027 rtlhal->external_lna_2g = 0;
3028 rtlhal->external_pa_5g = 0;
3029 rtlhal->external_lna_5g = 0;
3030 }
3031}
3032
3033static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3034 bool autoload_fail)
3035{
3036 struct rtl_priv *rtlpriv = rtl_priv(hw);
3037 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3038
3039 if (!autoload_fail) {
3040 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3041 if (rtlhal->external_lna_5g) {
3042 if (rtlhal->external_pa_5g) {
3043 if (rtlhal->external_lna_2g &&
3044 rtlhal->external_pa_2g)
3045 rtlhal->rfe_type = 3;
3046 else
3047 rtlhal->rfe_type = 0;
3048 } else {
3049 rtlhal->rfe_type = 2;
3050 }
3051 } else {
3052 rtlhal->rfe_type = 4;
3053 }
3054 } else {
3055 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3056
3057 if (rtlhal->rfe_type == 4 &&
3058 (rtlhal->external_pa_5g ||
3059 rtlhal->external_pa_2g ||
3060 rtlhal->external_lna_5g ||
3061 rtlhal->external_lna_2g)) {
3062 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3063 rtlhal->rfe_type = 2;
3064 }
3065 }
3066 } else {
3067 rtlhal->rfe_type = 0x04;
3068 }
3069
3070 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3071 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3072}
3073
3074static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3075 bool auto_load_fail, u8 *hwinfo)
3076{
3077 struct rtl_priv *rtlpriv = rtl_priv(hw);
3078 u8 value;
3079
3080 if (!auto_load_fail) {
3081 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3082 if (((value & 0xe0) >> 5) == 0x1)
3083 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3084 else
3085 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3086 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3087
3088 value = hwinfo[EEPROM_RF_BT_SETTING];
3089 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3090 } else {
3091 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3092 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3093 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3094 }
3095 /*move BT_InitHalVars() to init_sw_vars*/
3096}
3097
3098static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3099 bool auto_load_fail, u8 *hwinfo)
3100{
3101 struct rtl_priv *rtlpriv = rtl_priv(hw);
3102 u8 value;
3103 u32 tmpu_32;
3104
3105 if (!auto_load_fail) {
3106 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3107 if (tmpu_32 & BIT(18))
3108 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3109 else
3110 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3111 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3112
3113 value = hwinfo[EEPROM_RF_BT_SETTING];
3114 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3115 } else {
3116 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3117 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3118 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3119 }
3120 /*move BT_InitHalVars() to init_sw_vars*/
3121}
3122
3123static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3124{
3125 struct rtl_priv *rtlpriv = rtl_priv(hw);
3126 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3127 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3128 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3129 u16 i, usvalue;
3130 u8 hwinfo[HWSET_MAX_SIZE];
3131 u16 eeprom_id;
3132
3133 if (b_pseudo_test) {
3134 ;/* need add */
3135 }
3136
3137 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
3138 rtl_efuse_shadow_map_update(hw);
3139 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
3140 HWSET_MAX_SIZE);
3141 } else if (rtlefuse->epromtype == EEPROM_93C46) {
3142 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3143 "RTL819X Not boot from eeprom, check it !!");
3144 }
3145
3146 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
3147 hwinfo, HWSET_MAX_SIZE);
3148
3149 eeprom_id = *((u16 *)&hwinfo[0]);
3150 if (eeprom_id != RTL_EEPROM_ID) {
3151 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3152 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
3153 rtlefuse->autoload_failflag = true;
3154 } else {
3155 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3156 rtlefuse->autoload_failflag = false;
3157 }
3158
3159 if (rtlefuse->autoload_failflag) {
3160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3161 "RTL8812AE autoload_failflag, check it !!");
3162 return;
3163 }
3164
3165 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
3166 if (rtlefuse->eeprom_version == 0xff)
3167 rtlefuse->eeprom_version = 0;
3168
3169 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3170 "EEPROM version: 0x%2x\n", rtlefuse->eeprom_version);
3171
3172 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
3173 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
3174 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
3175 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
3176 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3177 "EEPROMId = 0x%4x\n", eeprom_id);
3178 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3179 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
3180 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3181 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
3182 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3183 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
3184 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3185 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
3186
3187 /*customer ID*/
3188 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
3189 if (rtlefuse->eeprom_oemid == 0xFF)
3190 rtlefuse->eeprom_oemid = 0;
3191
3192 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3193 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
3194
3195 for (i = 0; i < 6; i += 2) {
3196 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
3197 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
3198 }
3199
3200 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3201 "dev_addr: %pM\n", rtlefuse->dev_addr);
3202
3203 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3204 hwinfo);
3205
3206 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3207 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3208 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3209 rtlefuse->autoload_failflag, hwinfo);
3210 } else {
3211 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3212 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3213 rtlefuse->autoload_failflag, hwinfo);
3214 }
3215
3216 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3217 /*board type*/
3218 rtlefuse->board_type = ODM_BOARD_DEFAULT;
3219 if (rtlhal->external_lna_2g != 0)
3220 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3221 if (rtlhal->external_lna_5g != 0)
3222 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3223 if (rtlhal->external_pa_2g != 0)
3224 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3225 if (rtlhal->external_pa_5g != 0)
3226 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3227
3228 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3229 rtlefuse->board_type |= ODM_BOARD_BT;
3230
3231 rtlhal->board_type = rtlefuse->board_type;
3232 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3233 "board_type = 0x%x\n", rtlefuse->board_type);
3234
3235 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3236 if (rtlefuse->eeprom_channelplan == 0xff)
3237 rtlefuse->eeprom_channelplan = 0x7F;
3238
3239 /* set channel paln to world wide 13 */
3240 /* rtlefuse->channel_plan = (u8)rtlefuse->eeprom_channelplan; */
3241
3242 /*parse xtal*/
3243 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3244 if (rtlefuse->crystalcap == 0xFF)
3245 rtlefuse->crystalcap = 0x20;
3246
3247 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3248 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3249 rtlefuse->autoload_failflag) {
3250 rtlefuse->apk_thermalmeterignore = true;
3251 rtlefuse->eeprom_thermalmeter = 0xff;
3252 }
3253
3254 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3255 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3256 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3257
3258 if (!rtlefuse->autoload_failflag) {
3259 rtlefuse->antenna_div_cfg =
3260 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3261 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3262 rtlefuse->antenna_div_cfg = 0;
3263
3264 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3265 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3266 rtlefuse->antenna_div_cfg = 0;
3267
3268 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3269 if (rtlefuse->antenna_div_type == 0xff)
3270 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3271 } else {
3272 rtlefuse->antenna_div_cfg = 0;
3273 rtlefuse->antenna_div_type = 0;
3274 }
3275
3276 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3277 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3278 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3279
3280 pcipriv->ledctl.led_opendrain = true;
3281
3282 if (rtlhal->oem_id == RT_CID_DEFAULT) {
3283 switch (rtlefuse->eeprom_oemid) {
3284 case RT_CID_DEFAULT:
3285 break;
3286 case EEPROM_CID_TOSHIBA:
3287 rtlhal->oem_id = RT_CID_TOSHIBA;
3288 break;
3289 case EEPROM_CID_CCX:
3290 rtlhal->oem_id = RT_CID_CCX;
3291 break;
3292 case EEPROM_CID_QMI:
3293 rtlhal->oem_id = RT_CID_819X_QMI;
3294 break;
3295 case EEPROM_CID_WHQL:
3296 break;
3297 default:
3298 break;
3299 }
3300 }
3301}
3302
3303/*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3304{
3305 struct rtl_priv *rtlpriv = rtl_priv(hw);
3306 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3307 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3308
3309 pcipriv->ledctl.led_opendrain = true;
3310 switch (rtlhal->oem_id) {
3311 case RT_CID_819X_HP:
3312 pcipriv->ledctl.led_opendrain = true;
3313 break;
3314 case RT_CID_819X_LENOVO:
3315 case RT_CID_DEFAULT:
3316 case RT_CID_TOSHIBA:
3317 case RT_CID_CCX:
3318 case RT_CID_819X_ACER:
3319 case RT_CID_WHQL:
3320 default:
3321 break;
3322 }
3323 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3324 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3325}*/
3326
3327void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3328{
3329 struct rtl_priv *rtlpriv = rtl_priv(hw);
3330 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3331 struct rtl_phy *rtlphy = &rtlpriv->phy;
3332 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3333 u8 tmp_u1b;
3334
3335 rtlhal->version = _rtl8821ae_read_chip_version(hw);
3336 if (get_rf_type(rtlphy) == RF_1T1R)
3337 rtlpriv->dm.rfpath_rxenable[0] = true;
3338 else
3339 rtlpriv->dm.rfpath_rxenable[0] =
3340 rtlpriv->dm.rfpath_rxenable[1] = true;
3341 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3342 rtlhal->version);
3343
3344 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3345 if (tmp_u1b & BIT(4)) {
3346 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3347 rtlefuse->epromtype = EEPROM_93C46;
3348 } else {
3349 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3350 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3351 }
3352
3353 if (tmp_u1b & BIT(5)) {
3354 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3355 rtlefuse->autoload_failflag = false;
3356 _rtl8821ae_read_adapter_info(hw, false);
3357 } else {
3358 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3359 }
3360 /*hal_ReadRFType_8812A()*/
3361 /* _rtl8821ae_hal_customized_behavior(hw); */
3362}
3363
3364static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3365 struct ieee80211_sta *sta)
3366{
3367 struct rtl_priv *rtlpriv = rtl_priv(hw);
3368 struct rtl_phy *rtlphy = &rtlpriv->phy;
3369 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3370 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3371 u32 ratr_value;
3372 u8 ratr_index = 0;
3373 u8 b_nmode = mac->ht_enable;
3374 u8 mimo_ps = IEEE80211_SMPS_OFF;
3375 u16 shortgi_rate;
3376 u32 tmp_ratr_value;
3377 u8 curtxbw_40mhz = mac->bw_40;
3378 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3379 1 : 0;
3380 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3381 1 : 0;
3382 enum wireless_mode wirelessmode = mac->mode;
3383
3384 if (rtlhal->current_bandtype == BAND_ON_5G)
3385 ratr_value = sta->supp_rates[1] << 4;
3386 else
3387 ratr_value = sta->supp_rates[0];
3388 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3389 ratr_value = 0xfff;
3390 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3391 sta->ht_cap.mcs.rx_mask[0] << 12);
3392 switch (wirelessmode) {
3393 case WIRELESS_MODE_B:
3394 if (ratr_value & 0x0000000c)
3395 ratr_value &= 0x0000000d;
3396 else
3397 ratr_value &= 0x0000000f;
3398 break;
3399 case WIRELESS_MODE_G:
3400 ratr_value &= 0x00000FF5;
3401 break;
3402 case WIRELESS_MODE_N_24G:
3403 case WIRELESS_MODE_N_5G:
3404 b_nmode = 1;
3405 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3406 ratr_value &= 0x0007F005;
3407 } else {
3408 u32 ratr_mask;
3409
3410 if (get_rf_type(rtlphy) == RF_1T2R ||
3411 get_rf_type(rtlphy) == RF_1T1R)
3412 ratr_mask = 0x000ff005;
3413 else
3414 ratr_mask = 0x0f0ff005;
3415
3416 ratr_value &= ratr_mask;
3417 }
3418 break;
3419 default:
3420 if (rtlphy->rf_type == RF_1T2R)
3421 ratr_value &= 0x000ff0ff;
3422 else
3423 ratr_value &= 0x0f0ff0ff;
3424
3425 break;
3426 }
3427
3428 if ((rtlpriv->btcoexist.bt_coexistence) &&
3429 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3430 (rtlpriv->btcoexist.bt_cur_state) &&
3431 (rtlpriv->btcoexist.bt_ant_isolation) &&
3432 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3433 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3434 ratr_value &= 0x0fffcfc0;
3435 else
3436 ratr_value &= 0x0FFFFFFF;
3437
3438 if (b_nmode && ((curtxbw_40mhz &&
3439 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3440 b_curshortgi_20mhz))) {
3441 ratr_value |= 0x10000000;
3442 tmp_ratr_value = (ratr_value >> 12);
3443
3444 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3445 if ((1 << shortgi_rate) & tmp_ratr_value)
3446 break;
3447 }
3448
3449 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3450 (shortgi_rate << 4) | (shortgi_rate);
3451 }
3452
3453 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3454
3455 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3456 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3457}
3458
3459static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3460 struct ieee80211_hw *hw, u8 rate_index,
3461 enum wireless_mode wirelessmode)
3462{
3463 struct rtl_priv *rtlpriv = rtl_priv(hw);
3464 struct rtl_phy *rtlphy = &rtlpriv->phy;
3465 u8 ret = 0;
3466 switch (rate_index) {
3467 case RATR_INX_WIRELESS_NGB:
3468 if (rtlphy->rf_type == RF_1T1R)
3469 ret = 1;
3470 else
3471 ret = 0;
3472 ; break;
3473 case RATR_INX_WIRELESS_N:
3474 case RATR_INX_WIRELESS_NG:
3475 if (rtlphy->rf_type == RF_1T1R)
3476 ret = 5;
3477 else
3478 ret = 4;
3479 ; break;
3480 case RATR_INX_WIRELESS_NB:
3481 if (rtlphy->rf_type == RF_1T1R)
3482 ret = 3;
3483 else
3484 ret = 2;
3485 ; break;
3486 case RATR_INX_WIRELESS_GB:
3487 ret = 6;
3488 break;
3489 case RATR_INX_WIRELESS_G:
3490 ret = 7;
3491 break;
3492 case RATR_INX_WIRELESS_B:
3493 ret = 8;
3494 break;
3495 case RATR_INX_WIRELESS_MC:
3496 if ((wirelessmode == WIRELESS_MODE_B)
3497 || (wirelessmode == WIRELESS_MODE_G)
3498 || (wirelessmode == WIRELESS_MODE_N_24G)
3499 || (wirelessmode == WIRELESS_MODE_AC_24G))
3500 ret = 6;
3501 else
3502 ret = 7;
3503 case RATR_INX_WIRELESS_AC_5N:
3504 if (rtlphy->rf_type == RF_1T1R)
3505 ret = 10;
3506 else
3507 ret = 9;
3508 break;
3509 case RATR_INX_WIRELESS_AC_24N:
3510 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3511 if (rtlphy->rf_type == RF_1T1R)
3512 ret = 10;
3513 else
3514 ret = 9;
3515 } else {
3516 if (rtlphy->rf_type == RF_1T1R)
3517 ret = 11;
3518 else
3519 ret = 12;
3520 }
3521 break;
3522 default:
3523 ret = 0; break;
3524 }
3525 return ret;
3526}
3527
3528static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3529{
3530 u8 i, j, tmp_rate;
3531 u32 rate_bitmap = 0;
3532
3533 for (i = j = 0; i < 4; i += 2, j += 10) {
3534 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3535
3536 switch (tmp_rate) {
3537 case 2:
3538 rate_bitmap = rate_bitmap | (0x03ff << j);
3539 break;
3540 case 1:
3541 rate_bitmap = rate_bitmap | (0x01ff << j);
3542 break;
3543 case 0:
3544 rate_bitmap = rate_bitmap | (0x00ff << j);
3545 break;
3546 default:
3547 break;
3548 }
3549 }
3550
3551 return rate_bitmap;
3552}
3553
3554static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3555 enum wireless_mode wirelessmode,
3556 u32 ratr_bitmap)
3557{
3558 struct rtl_priv *rtlpriv = rtl_priv(hw);
3559 struct rtl_phy *rtlphy = &rtlpriv->phy;
3560 u32 ret_bitmap = ratr_bitmap;
3561
3562 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3563 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3564 ret_bitmap = ratr_bitmap;
3565 else if (wirelessmode == WIRELESS_MODE_AC_5G
3566 || wirelessmode == WIRELESS_MODE_AC_24G) {
3567 if (rtlphy->rf_type == RF_1T1R)
3568 ret_bitmap = ratr_bitmap & (~BIT21);
3569 else
3570 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3571 }
3572
3573 return ret_bitmap;
3574}
3575
3576static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3577 u32 ratr_bitmap)
3578{
3579 u8 ret = 0;
3580 if (wirelessmode < WIRELESS_MODE_N_24G)
3581 ret = 0;
3582 else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3583 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
3584 ret = 3;
3585 else /* Mix, 1SS */
3586 ret = 2;
3587 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3588 ret = 1;
3589 } /* VHT */
3590
3591 return ret << 4;
3592}
3593
3594static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3595 u8 mac_id, struct rtl_sta_info *sta_entry,
3596 enum wireless_mode wirelessmode)
3597{
3598 u8 b_ldpc = 0;
3599 /*not support ldpc, do not open*/
3600 return b_ldpc << 2;
3601}
3602
3603static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3604 enum wireless_mode wirelessmode,
3605 u32 ratr_bitmap)
3606{
3607 struct rtl_priv *rtlpriv = rtl_priv(hw);
3608 struct rtl_phy *rtlphy = &rtlpriv->phy;
3609 u8 rf_type = RF_1T1R;
3610
3611 if (rtlphy->rf_type == RF_1T1R)
3612 rf_type = RF_1T1R;
3613 else if (wirelessmode == WIRELESS_MODE_AC_5G
3614 || wirelessmode == WIRELESS_MODE_AC_24G
3615 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3616 if (ratr_bitmap & 0xffc00000)
3617 rf_type = RF_2T2R;
3618 } else if (wirelessmode == WIRELESS_MODE_N_5G
3619 || wirelessmode == WIRELESS_MODE_N_24G) {
3620 if (ratr_bitmap & 0xfff00000)
3621 rf_type = RF_2T2R;
3622 }
3623
3624 return rf_type;
3625}
3626
3627static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3628 u8 mac_id)
3629{
3630 bool b_short_gi = false;
3631 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3632 1 : 0;
3633 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3634 1 : 0;
3635 u8 b_curshortgi_80mhz = 0;
3636 b_curshortgi_80mhz = (sta->vht_cap.cap &
3637 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3638
3639 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3640 b_short_gi = false;
3641
3642 if (b_curshortgi_40mhz || b_curshortgi_80mhz
3643 || b_curshortgi_20mhz)
3644 b_short_gi = true;
3645
3646 return b_short_gi;
3647}
3648
3649static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3650 struct ieee80211_sta *sta, u8 rssi_level)
3651{
3652 struct rtl_priv *rtlpriv = rtl_priv(hw);
3653 struct rtl_phy *rtlphy = &rtlpriv->phy;
3654 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3655 struct rtl_sta_info *sta_entry = NULL;
3656 u32 ratr_bitmap;
3657 u8 ratr_index;
3658 enum wireless_mode wirelessmode = 0;
3659 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3660 ? 1 : 0;
3661 bool b_shortgi = false;
3662 u8 rate_mask[7];
3663 u8 macid = 0;
3664 u8 mimo_ps = IEEE80211_SMPS_OFF;
3665 u8 rf_type;
3666
3667 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3668 wirelessmode = sta_entry->wireless_mode;
3669
3670 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3671 "wireless mode = 0x%x\n", wirelessmode);
3672 if (mac->opmode == NL80211_IFTYPE_STATION ||
3673 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3674 curtxbw_40mhz = mac->bw_40;
3675 } else if (mac->opmode == NL80211_IFTYPE_AP ||
3676 mac->opmode == NL80211_IFTYPE_ADHOC)
3677 macid = sta->aid + 1;
3678 if (wirelessmode == WIRELESS_MODE_N_5G ||
3679 wirelessmode == WIRELESS_MODE_AC_5G)
3680 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ];
3681 else
3682 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3683
3684 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3685 ratr_bitmap = 0xfff;
3686
3687 if (wirelessmode == WIRELESS_MODE_N_24G
3688 || wirelessmode == WIRELESS_MODE_N_5G)
3689 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3690 sta->ht_cap.mcs.rx_mask[0] << 12);
3691 else if (wirelessmode == WIRELESS_MODE_AC_24G
3692 || wirelessmode == WIRELESS_MODE_AC_5G
3693 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3694 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3695 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3696
3697 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3698 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3699
3700/*mac id owner*/
3701 switch (wirelessmode) {
3702 case WIRELESS_MODE_B:
3703 ratr_index = RATR_INX_WIRELESS_B;
3704 if (ratr_bitmap & 0x0000000c)
3705 ratr_bitmap &= 0x0000000d;
3706 else
3707 ratr_bitmap &= 0x0000000f;
3708 break;
3709 case WIRELESS_MODE_G:
3710 ratr_index = RATR_INX_WIRELESS_GB;
3711
3712 if (rssi_level == 1)
3713 ratr_bitmap &= 0x00000f00;
3714 else if (rssi_level == 2)
3715 ratr_bitmap &= 0x00000ff0;
3716 else
3717 ratr_bitmap &= 0x00000ff5;
3718 break;
3719 case WIRELESS_MODE_A:
3720 ratr_index = RATR_INX_WIRELESS_G;
3721 ratr_bitmap &= 0x00000ff0;
3722 break;
3723 case WIRELESS_MODE_N_24G:
3724 case WIRELESS_MODE_N_5G:
3725 if (wirelessmode == WIRELESS_MODE_N_24G)
3726 ratr_index = RATR_INX_WIRELESS_NGB;
3727 else
3728 ratr_index = RATR_INX_WIRELESS_NG;
3729
3730 if (mimo_ps == IEEE80211_SMPS_STATIC
3731 || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3732 if (rssi_level == 1)
3733 ratr_bitmap &= 0x000f0000;
3734 else if (rssi_level == 2)
3735 ratr_bitmap &= 0x000ff000;
3736 else
3737 ratr_bitmap &= 0x000ff005;
3738 } else {
3739 if (rf_type == RF_1T1R) {
3740 if (curtxbw_40mhz) {
3741 if (rssi_level == 1)
3742 ratr_bitmap &= 0x000f0000;
3743 else if (rssi_level == 2)
3744 ratr_bitmap &= 0x000ff000;
3745 else
3746 ratr_bitmap &= 0x000ff015;
3747 } else {
3748 if (rssi_level == 1)
3749 ratr_bitmap &= 0x000f0000;
3750 else if (rssi_level == 2)
3751 ratr_bitmap &= 0x000ff000;
3752 else
3753 ratr_bitmap &= 0x000ff005;
3754 }
3755 } else {
3756 if (curtxbw_40mhz) {
3757 if (rssi_level == 1)
3758 ratr_bitmap &= 0x0fff0000;
3759 else if (rssi_level == 2)
3760 ratr_bitmap &= 0x0ffff000;
3761 else
3762 ratr_bitmap &= 0x0ffff015;
3763 } else {
3764 if (rssi_level == 1)
3765 ratr_bitmap &= 0x0fff0000;
3766 else if (rssi_level == 2)
3767 ratr_bitmap &= 0x0ffff000;
3768 else
3769 ratr_bitmap &= 0x0ffff005;
3770 }
3771 }
3772 }
3773 break;
3774
3775 case WIRELESS_MODE_AC_24G:
3776 ratr_index = RATR_INX_WIRELESS_AC_24N;
3777 if (rssi_level == 1)
3778 ratr_bitmap &= 0xfc3f0000;
3779 else if (rssi_level == 2)
3780 ratr_bitmap &= 0xfffff000;
3781 else
3782 ratr_bitmap &= 0xffffffff;
3783 break;
3784
3785 case WIRELESS_MODE_AC_5G:
3786 ratr_index = RATR_INX_WIRELESS_AC_5N;
3787
3788 if (rf_type == RF_1T1R) {
3789 if (rssi_level == 1) /*add by Gary for ac-series*/
3790 ratr_bitmap &= 0x003f8000;
3791 else if (rssi_level == 2)
3792 ratr_bitmap &= 0x003ff000;
3793 else
3794 ratr_bitmap &= 0x003ff010;
3795 } else {
3796 if (rssi_level == 1)
3797 ratr_bitmap &= 0xfe3f8000;
3798 else if (rssi_level == 2)
3799 ratr_bitmap &= 0xfffff000;
3800 else
3801 ratr_bitmap &= 0xfffff010;
3802 }
3803 break;
3804
3805 default:
3806 ratr_index = RATR_INX_WIRELESS_NGB;
3807
3808 if (rf_type == RF_1T2R)
3809 ratr_bitmap &= 0x000ff0ff;
3810 else
3811 ratr_bitmap &= 0x0f8ff0ff;
3812 break;
3813 }
3814
3815 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3816 sta_entry->ratr_index = ratr_index;
3817 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3818 ratr_bitmap);
3819
3820 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3821 "ratr_bitmap :%x\n", ratr_bitmap);
3822
3823 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3824 (ratr_index << 28)); */
3825
3826 rate_mask[0] = macid;
3827 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3828 rate_mask[2] = rtlphy->current_chan_bw
3829 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3830 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3831
3832 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3833 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3834 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3835 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3836
3837 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3838 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3839 ratr_index, ratr_bitmap,
3840 rate_mask[0], rate_mask[1],
3841 rate_mask[2], rate_mask[3],
3842 rate_mask[4], rate_mask[5],
3843 rate_mask[6]);
3844 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3845 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3846}
3847
3848void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3849 struct ieee80211_sta *sta, u8 rssi_level)
3850{
3851 struct rtl_priv *rtlpriv = rtl_priv(hw);
3852 if (rtlpriv->dm.useramask)
3853 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3854 else
3855 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3856 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only");*/
3857 rtl8821ae_update_hal_rate_table(hw, sta);
3858}
3859
3860void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3861{
3862 struct rtl_priv *rtlpriv = rtl_priv(hw);
3863 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3864 u8 wireless_mode = mac->mode;
3865 u8 sifs_timer, r2t_sifs;
3866
3867 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3868 (u8 *)&mac->slot_time);
3869 if (wireless_mode == WIRELESS_MODE_G)
3870 sifs_timer = 0x0a;
3871 else
3872 sifs_timer = 0x0e;
3873 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3874
3875 r2t_sifs = 0xa;
3876
3877 if (wireless_mode == WIRELESS_MODE_AC_5G &&
3878 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3879 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3880 if (mac->vendor == PEER_ATH)
3881 r2t_sifs = 0x8;
3882 else
3883 r2t_sifs = 0xa;
3884 } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3885 r2t_sifs = 0xa;
3886 }
3887
3888 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3889}
3890
3891bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3892{
3893 struct rtl_priv *rtlpriv = rtl_priv(hw);
3894 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3895 struct rtl_phy *rtlphy = &rtlpriv->phy;
3896 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3897 u8 u1tmp = 0;
3898 bool b_actuallyset = false;
3899
3900 if (rtlpriv->rtlhal.being_init_adapter)
3901 return false;
3902
3903 if (ppsc->swrf_processing)
3904 return false;
3905
3906 spin_lock(&rtlpriv->locks.rf_ps_lock);
3907 if (ppsc->rfchange_inprogress) {
3908 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3909 return false;
3910 } else {
3911 ppsc->rfchange_inprogress = true;
3912 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3913 }
3914
3915 cur_rfstate = ppsc->rfpwr_state;
3916
3917 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3918 rtl_read_byte(rtlpriv,
3919 REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3920
3921 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3922
3923 if (rtlphy->polarity_ctl)
3924 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3925 else
3926 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3927
3928 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3929 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3930 "GPIOChangeRF - HW Radio ON, RF ON\n");
3931
3932 e_rfpowerstate_toset = ERFON;
3933 ppsc->hwradiooff = false;
3934 b_actuallyset = true;
3935 } else if ((!ppsc->hwradiooff)
3936 && (e_rfpowerstate_toset == ERFOFF)) {
3937 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3938 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
3939
3940 e_rfpowerstate_toset = ERFOFF;
3941 ppsc->hwradiooff = true;
3942 b_actuallyset = true;
3943 }
3944
3945 if (b_actuallyset) {
3946 spin_lock(&rtlpriv->locks.rf_ps_lock);
3947 ppsc->rfchange_inprogress = false;
3948 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3949 } else {
3950 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3951 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3952
3953 spin_lock(&rtlpriv->locks.rf_ps_lock);
3954 ppsc->rfchange_inprogress = false;
3955 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3956 }
3957
3958 *valid = 1;
3959 return !ppsc->hwradiooff;
3960}
3961
3962void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3963 u8 *p_macaddr, bool is_group, u8 enc_algo,
3964 bool is_wepkey, bool clear_all)
3965{
3966 struct rtl_priv *rtlpriv = rtl_priv(hw);
3967 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3968 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3969 u8 *macaddr = p_macaddr;
3970 u32 entry_id = 0;
3971 bool is_pairwise = false;
3972
3973 static u8 cam_const_addr[4][6] = {
3974 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3975 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3976 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3977 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3978 };
3979 static u8 cam_const_broad[] = {
3980 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3981 };
3982
3983 if (clear_all) {
3984 u8 idx = 0;
3985 u8 cam_offset = 0;
3986 u8 clear_number = 5;
3987
3988 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3989
3990 for (idx = 0; idx < clear_number; idx++) {
3991 rtl_cam_mark_invalid(hw, cam_offset + idx);
3992 rtl_cam_empty_entry(hw, cam_offset + idx);
3993
3994 if (idx < 5) {
3995 memset(rtlpriv->sec.key_buf[idx], 0,
3996 MAX_KEY_LEN);
3997 rtlpriv->sec.key_len[idx] = 0;
3998 }
3999 }
4000 } else {
4001 switch (enc_algo) {
4002 case WEP40_ENCRYPTION:
4003 enc_algo = CAM_WEP40;
4004 break;
4005 case WEP104_ENCRYPTION:
4006 enc_algo = CAM_WEP104;
4007 break;
4008 case TKIP_ENCRYPTION:
4009 enc_algo = CAM_TKIP;
4010 break;
4011 case AESCCMP_ENCRYPTION:
4012 enc_algo = CAM_AES;
4013 break;
4014 default:
4015 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
4016 "switch case not process\n");
4017 enc_algo = CAM_TKIP;
4018 break;
4019 }
4020
4021 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
4022 macaddr = cam_const_addr[key_index];
4023 entry_id = key_index;
4024 } else {
4025 if (is_group) {
4026 macaddr = cam_const_broad;
4027 entry_id = key_index;
4028 } else {
4029 if (mac->opmode == NL80211_IFTYPE_AP) {
4030 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
4031 if (entry_id >= TOTAL_CAM_ENTRY) {
4032 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
4033 "Can not find free hwsecurity cam entry\n");
4034 return;
4035 }
4036 } else {
4037 entry_id = CAM_PAIRWISE_KEY_POSITION;
4038 }
4039
4040 key_index = PAIRWISE_KEYIDX;
4041 is_pairwise = true;
4042 }
4043 }
4044
4045 if (rtlpriv->sec.key_len[key_index] == 0) {
4046 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4047 "delete one entry, entry_id is %d\n",
4048 entry_id);
4049 if (mac->opmode == NL80211_IFTYPE_AP)
4050 rtl_cam_del_entry(hw, p_macaddr);
4051 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
4052 } else {
4053 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4054 "add one entry\n");
4055 if (is_pairwise) {
4056 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4057 "set Pairwise key\n");
4058
4059 rtl_cam_add_one_entry(hw, macaddr, key_index,
4060 entry_id, enc_algo,
4061 CAM_CONFIG_NO_USEDK,
4062 rtlpriv->sec.key_buf[key_index]);
4063 } else {
4064 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4065 "set group key\n");
4066
4067 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
4068 rtl_cam_add_one_entry(hw,
4069 rtlefuse->dev_addr,
4070 PAIRWISE_KEYIDX,
4071 CAM_PAIRWISE_KEY_POSITION,
4072 enc_algo,
4073 CAM_CONFIG_NO_USEDK,
4074 rtlpriv->sec.key_buf
4075 [entry_id]);
4076 }
4077
4078 rtl_cam_add_one_entry(hw, macaddr, key_index,
4079 entry_id, enc_algo,
4080 CAM_CONFIG_NO_USEDK,
4081 rtlpriv->sec.key_buf[entry_id]);
4082 }
4083 }
4084 }
4085}
4086
4087void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4088{
4089 struct rtl_priv *rtlpriv = rtl_priv(hw);
4090
4091 /* 0:Low, 1:High, 2:From Efuse. */
4092 rtlpriv->btcoexist.reg_bt_iso = 2;
4093 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4094 rtlpriv->btcoexist.reg_bt_sco = 3;
4095 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4096 rtlpriv->btcoexist.reg_bt_sco = 0;
4097}
4098
4099void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4100{
4101 struct rtl_priv *rtlpriv = rtl_priv(hw);
4102
4103 if (rtlpriv->cfg->ops->get_btc_status())
4104 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4105}
4106
4107void rtl8821ae_suspend(struct ieee80211_hw *hw)
4108{
4109}
4110
4111void rtl8821ae_resume(struct ieee80211_hw *hw)
4112{
4113}
4114
4115/* Turn on AAP (RCR:bit 0) for promicuous mode. */
4116void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4117 bool allow_all_da, bool write_into_reg)
4118{
4119 struct rtl_priv *rtlpriv = rtl_priv(hw);
4120 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4121
4122 if (allow_all_da) /* Set BIT0 */
4123 rtlpci->receive_config |= RCR_AAP;
4124 else /* Clear BIT0 */
4125 rtlpci->receive_config &= ~RCR_AAP;
4126
4127 if (write_into_reg)
4128 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4129
4130 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4131 "receive_config=0x%08X, write_into_reg=%d\n",
4132 rtlpci->receive_config, write_into_reg);
4133}
4134
4135/* WKFMCAMAddAllEntry8812 */
4136void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4137 struct rtl_wow_pattern *rtl_pattern,
4138 u8 index)
4139{
4140 struct rtl_priv *rtlpriv = rtl_priv(hw);
4141 u32 cam = 0;
4142 u8 addr = 0;
4143 u16 rxbuf_addr;
4144 u8 tmp, count = 0;
4145 u16 cam_start;
4146 u16 offset;
4147
4148 /* Count the WFCAM entry start offset. */
4149
4150 /* RX page size = 128 byte */
4151 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4152 /* We should start from the boundry */
4153 cam_start = offset * 128;
4154
4155 /* Enable Rx packet buffer access. */
4156 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4157 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4158 /* Set Rx packet buffer offset.
4159 * RxBufer pointer increases 1,
4160 * we can access 8 bytes in Rx packet buffer.
4161 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE
4162 * RxBufer addr = (CAM start offset +
4163 * per entry offset of a WKFM CAM)/8
4164 * * index: The index of the wake up frame mask
4165 * * WKFMCAM_SIZE: the total size of one WKFM CAM
4166 * * per entry offset of a WKFM CAM: Addr*4 bytes
4167 */
4168 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4169 /* Set R/W start offset */
4170 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4171
4172 if (addr == 0) {
4173 cam = BIT(31) | rtl_pattern->crc;
4174
4175 if (rtl_pattern->type == UNICAST_PATTERN)
4176 cam |= BIT(24);
4177 else if (rtl_pattern->type == MULTICAST_PATTERN)
4178 cam |= BIT(25);
4179 else if (rtl_pattern->type == BROADCAST_PATTERN)
4180 cam |= BIT(26);
4181
4182 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4183 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4184 "WRITE entry[%d] 0x%x: %x\n", addr,
4185 REG_PKTBUF_DBG_DATA_L, cam);
4186
4187 /* Write to Rx packet buffer. */
4188 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4189 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4190 cam = rtl_pattern->mask[addr - 2];
4191
4192 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4193 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4194 "WRITE entry[%d] 0x%x: %x\n", addr,
4195 REG_PKTBUF_DBG_DATA_L, cam);
4196
4197 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4198 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4199 cam = rtl_pattern->mask[addr - 2];
4200
4201 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4202 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4203 "WRITE entry[%d] 0x%x: %x\n", addr,
4204 REG_PKTBUF_DBG_DATA_H, cam);
4205
4206 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4207 }
4208
4209 count = 0;
4210 do {
4211 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4212 udelay(2);
4213 count++;
4214 } while (tmp && count < 100);
4215
4216 RT_ASSERT((count < 100),
4217 "Write wake up frame mask FAIL %d value!\n", tmp);
4218 }
4219 /* Disable Rx packet buffer access. */
4220 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4221 DISABLE_TRXPKT_BUF_ACCESS);
4222}
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/hw.h b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.h
new file mode 100644
index 000000000000..a3553e3abaa1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.h
@@ -0,0 +1,70 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_HW_H__
27#define __RTL8821AE_HW_H__
28
29void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
30void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw);
31
32void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
33 u32 *p_inta, u32 *p_intb);
34int rtl8821ae_hw_init(struct ieee80211_hw *hw);
35void rtl8821ae_card_disable(struct ieee80211_hw *hw);
36void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw);
37void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw);
38int rtl8821ae_set_network_type(struct ieee80211_hw *hw,
39 enum nl80211_iftype type);
40void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
41void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci);
42void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw);
43void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw);
44void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
45 u32 add_msr, u32 rm_msr);
46void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
47void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
48 struct ieee80211_sta *sta,
49 u8 rssi_level);
50void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw);
51bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
52void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw);
53void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
54 u8 *p_macaddr, bool is_group, u8 enc_algo,
55 bool is_wepkey, bool clear_all);
56
57void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw);
58void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw);
59void rtl8821ae_suspend(struct ieee80211_hw *hw);
60void rtl8821ae_resume(struct ieee80211_hw *hw);
61void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
62 bool allow_all_da,
63 bool write_into_reg);
64void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw);
65void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw);
66void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
67 struct rtl_wow_pattern *rtl_pattern,
68 u8 index);
69
70#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/led.c b/drivers/net/wireless/rtlwifi/rtl8821ae/led.c
new file mode 100644
index 000000000000..ba1946a0280e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/led.c
@@ -0,0 +1,237 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "reg.h"
29#include "led.h"
30
31static void _rtl8821ae_init_led(struct ieee80211_hw *hw,
32 struct rtl_led *pled,
33 enum rtl_led_pin ledpin)
34{
35 pled->hw = hw;
36 pled->ledpin = ledpin;
37 pled->ledon = false;
38}
39
40void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
41{
42 u8 ledcfg;
43 struct rtl_priv *rtlpriv = rtl_priv(hw);
44
45 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
46 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
47
48 switch (pled->ledpin) {
49 case LED_PIN_GPIO0:
50 break;
51 case LED_PIN_LED0:
52 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
53 ledcfg &= ~BIT(6);
54 rtl_write_byte(rtlpriv,
55 REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5));
56 break;
57 case LED_PIN_LED1:
58 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
59 rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
60 break;
61 default:
62 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
63 "switch case not process\n");
64 break;
65 }
66 pled->ledon = true;
67}
68
69void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
70{
71 u16 ledreg = REG_LEDCFG1;
72 u8 ledcfg = 0;
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74
75 switch (pled->ledpin) {
76 case LED_PIN_LED0:
77 ledreg = REG_LEDCFG1;
78 break;
79
80 case LED_PIN_LED1:
81 ledreg = REG_LEDCFG2;
82 break;
83
84 case LED_PIN_GPIO0:
85 default:
86 break;
87 }
88
89 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
90 "In SwLedOn, LedAddr:%X LEDPIN=%d\n",
91 ledreg, pled->ledpin);
92
93 ledcfg = rtl_read_byte(rtlpriv, ledreg);
94 ledcfg |= BIT(5); /*Set 0x4c[21]*/
95 ledcfg &= ~(BIT(7) | BIT(6) | BIT(3) | BIT(2) | BIT(1) | BIT(0));
96 /*Clear 0x4c[23:22] and 0x4c[19:16]*/
97 rtl_write_byte(rtlpriv, ledreg, ledcfg); /*SW control led0 on.*/
98 pled->ledon = true;
99}
100
101void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
102{
103 struct rtl_priv *rtlpriv = rtl_priv(hw);
104 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
105 u8 ledcfg;
106
107 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
108 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
109
110 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
111
112 switch (pled->ledpin) {
113 case LED_PIN_GPIO0:
114 break;
115 case LED_PIN_LED0:
116 ledcfg &= 0xf0;
117 if (pcipriv->ledctl.led_opendrain) {
118 ledcfg &= 0x90; /* Set to software control. */
119 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3)));
120 ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
121 ledcfg &= 0xFE;
122 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
123 } else {
124 ledcfg &= ~BIT(6);
125 rtl_write_byte(rtlpriv, REG_LEDCFG2,
126 (ledcfg | BIT(3) | BIT(5)));
127 }
128 break;
129 case LED_PIN_LED1:
130 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
131 ledcfg &= 0x10; /* Set to software control. */
132 rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3));
133 break;
134 default:
135 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
136 "switch case not process\n");
137 break;
138 }
139 pled->ledon = false;
140}
141
142void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
143{
144 u16 ledreg = REG_LEDCFG1;
145 struct rtl_priv *rtlpriv = rtl_priv(hw);
146 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
147
148 switch (pled->ledpin) {
149 case LED_PIN_LED0:
150 ledreg = REG_LEDCFG1;
151 break;
152
153 case LED_PIN_LED1:
154 ledreg = REG_LEDCFG2;
155 break;
156
157 case LED_PIN_GPIO0:
158 default:
159 break;
160 }
161
162 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
163 "In SwLedOff,LedAddr:%X LEDPIN=%d\n",
164 ledreg, pled->ledpin);
165 /*Open-drain arrangement for controlling the LED*/
166 if (pcipriv->ledctl.led_opendrain) {
167 u8 ledcfg = rtl_read_byte(rtlpriv, ledreg);
168
169 ledreg &= 0xd0; /* Set to software control.*/
170 rtl_write_byte(rtlpriv, ledreg, (ledcfg | BIT(3)));
171
172 /*Open-drain arrangement*/
173 ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
174 ledcfg &= 0xFE;/*Set GPIO[8] to input mode*/
175 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
176 } else {
177 rtl_write_byte(rtlpriv, ledreg, 0x28);
178 }
179
180 pled->ledon = false;
181}
182
183void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw)
184{
185 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
186
187 _rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
188 _rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
189}
190
191static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw,
192 enum led_ctl_mode ledaction)
193{
194 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
195 struct rtl_led *pLed0 = &pcipriv->ledctl.sw_led0;
196 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
197
198 switch (ledaction) {
199 case LED_CTL_POWER_ON:
200 case LED_CTL_LINK:
201 case LED_CTL_NO_LINK:
202 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
203 rtl8812ae_sw_led_on(hw, pLed0);
204 else
205 rtl8821ae_sw_led_on(hw, pLed0);
206 break;
207 case LED_CTL_POWER_OFF:
208 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
209 rtl8812ae_sw_led_off(hw, pLed0);
210 else
211 rtl8821ae_sw_led_off(hw, pLed0);
212 break;
213 default:
214 break;
215 }
216}
217
218void rtl8821ae_led_control(struct ieee80211_hw *hw,
219 enum led_ctl_mode ledaction)
220{
221 struct rtl_priv *rtlpriv = rtl_priv(hw);
222 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
223
224 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
225 (ledaction == LED_CTL_TX ||
226 ledaction == LED_CTL_RX ||
227 ledaction == LED_CTL_SITE_SURVEY ||
228 ledaction == LED_CTL_LINK ||
229 ledaction == LED_CTL_NO_LINK ||
230 ledaction == LED_CTL_START_TO_LINK ||
231 ledaction == LED_CTL_POWER_ON)) {
232 return;
233 }
234 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d,\n",
235 ledaction);
236 _rtl8821ae_sw_led_control(hw, ledaction);
237}
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/led.h b/drivers/net/wireless/rtlwifi/rtl8821ae/led.h
new file mode 100644
index 000000000000..038e64e18ae8
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/led.h
@@ -0,0 +1,37 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_LED_H__
27#define __RTL8821AE_LED_H__
28
29void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw);
30void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
31void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
32void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
33void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
34void rtl8821ae_led_control(struct ieee80211_hw *hw,
35 enum led_ctl_mode ledaction);
36
37#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/phy.c b/drivers/net/wireless/rtlwifi/rtl8821ae/phy.c
new file mode 100644
index 000000000000..9786313dc62f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/phy.c
@@ -0,0 +1,4855 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "../ps.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "rf.h"
33#include "dm.h"
34#include "table.h"
35#include "trx.h"
36#include "../btcoexist/halbt_precomp.h"
37#include "hw.h"
38#include "../efuse.h"
39
40#define READ_NEXT_PAIR(array_table, v1, v2, i) \
41 do { \
42 i += 2; \
43 v1 = array_table[i]; \
44 v2 = array_table[i+1]; \
45 } while (0)
46
47static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
48 enum radio_path rfpath, u32 offset);
49static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
50 enum radio_path rfpath, u32 offset,
51 u32 data);
52static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask);
53static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw);
54/*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/
55static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
56static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
57 u8 configtype);
58static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
59 u8 configtype);
60static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
61
62static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
63 enum wireless_mode wirelessmode,
64 u8 txpwridx);
65static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw);
66static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw);
67
68static void rtl8812ae_fixspur(struct ieee80211_hw *hw,
69 enum ht_channel_width band_width, u8 channel)
70{
71 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
72
73 /*C cut Item12 ADC FIFO CLOCK*/
74 if (IS_VENDOR_8812A_C_CUT(rtlhal->version)) {
75 if (band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11)
76 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3);
77 /* 0x8AC[11:10] = 2'b11*/
78 else
79 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2);
80 /* 0x8AC[11:10] = 2'b10*/
81
82 /* <20120914, Kordan> A workarould to resolve
83 * 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)
84 */
85 if (band_width == HT_CHANNEL_WIDTH_20 &&
86 (channel == 13 || channel == 14)) {
87 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
88 /*0x8AC[9:8] = 2'b11*/
89 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
90 /* 0x8C4[30] = 1*/
91 } else if (band_width == HT_CHANNEL_WIDTH_20_40 &&
92 channel == 11) {
93 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
94 /*0x8C4[30] = 1*/
95 } else if (band_width != HT_CHANNEL_WIDTH_80) {
96 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
97 /*0x8AC[9:8] = 2'b10*/
98 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
99 /*0x8C4[30] = 0*/
100 }
101 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
102 /* <20120914, Kordan> A workarould to resolve
103 * 2480Mhz spur by setting ADC clock as 160M.
104 */
105 if (band_width == HT_CHANNEL_WIDTH_20 &&
106 (channel == 13 || channel == 14))
107 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
108 /*0x8AC[9:8] = 11*/
109 else if (channel <= 14) /*2.4G only*/
110 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
111 /*0x8AC[9:8] = 10*/
112 }
113}
114
115u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
116 u32 bitmask)
117{
118 struct rtl_priv *rtlpriv = rtl_priv(hw);
119 u32 returnvalue, originalvalue, bitshift;
120
121 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
122 "regaddr(%#x), bitmask(%#x)\n",
123 regaddr, bitmask);
124 originalvalue = rtl_read_dword(rtlpriv, regaddr);
125 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
126 returnvalue = (originalvalue & bitmask) >> bitshift;
127
128 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
129 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
130 bitmask, regaddr, originalvalue);
131 return returnvalue;
132}
133
134void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
135 u32 regaddr, u32 bitmask, u32 data)
136{
137 struct rtl_priv *rtlpriv = rtl_priv(hw);
138 u32 originalvalue, bitshift;
139
140 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
141 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
142 regaddr, bitmask, data);
143
144 if (bitmask != MASKDWORD) {
145 originalvalue = rtl_read_dword(rtlpriv, regaddr);
146 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
147 data = ((originalvalue & (~bitmask)) |
148 ((data << bitshift) & bitmask));
149 }
150
151 rtl_write_dword(rtlpriv, regaddr, data);
152
153 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
154 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
155 regaddr, bitmask, data);
156}
157
158u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
159 enum radio_path rfpath, u32 regaddr,
160 u32 bitmask)
161{
162 struct rtl_priv *rtlpriv = rtl_priv(hw);
163 u32 original_value, readback_value, bitshift;
164 unsigned long flags;
165
166 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
167 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
168 regaddr, rfpath, bitmask);
169
170 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
171
172 original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
173 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
174 readback_value = (original_value & bitmask) >> bitshift;
175
176 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
177
178 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
179 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
180 regaddr, rfpath, bitmask, original_value);
181
182 return readback_value;
183}
184
185void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
186 enum radio_path rfpath,
187 u32 regaddr, u32 bitmask, u32 data)
188{
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 u32 original_value, bitshift;
191 unsigned long flags;
192
193 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
194 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
195 regaddr, bitmask, data, rfpath);
196
197 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
198
199 if (bitmask != RFREG_OFFSET_MASK) {
200 original_value =
201 _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
202 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
203 data = ((original_value & (~bitmask)) | (data << bitshift));
204 }
205
206 _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data);
207
208 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
209
210 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
211 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
212 regaddr, bitmask, data, rfpath);
213}
214
215static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
216 enum radio_path rfpath, u32 offset)
217{
218 struct rtl_priv *rtlpriv = rtl_priv(hw);
219 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
220 bool is_pi_mode = false;
221 u32 retvalue = 0;
222
223 /* 2009/06/17 MH We can not execute IO for power
224 save or other accident mode.*/
225 if (RT_CANNOT_IO(hw)) {
226 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
227 return 0xFFFFFFFF;
228 }
229 /* <20120809, Kordan> CCA OFF(when entering),
230 asked by James to avoid reading the wrong value.
231 <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
232 if (offset != 0x0 &&
233 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
234 (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
235 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1);
236 offset &= 0xff;
237
238 if (rfpath == RF90_PATH_A)
239 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xC00, 0x4);
240 else if (rfpath == RF90_PATH_B)
241 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xE00, 0x4);
242
243 rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset);
244
245 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
246 (IS_VENDOR_8812A_C_CUT(rtlhal->version)))
247 udelay(20);
248
249 if (is_pi_mode) {
250 if (rfpath == RF90_PATH_A)
251 retvalue =
252 rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA);
253 else if (rfpath == RF90_PATH_B)
254 retvalue =
255 rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA);
256 } else {
257 if (rfpath == RF90_PATH_A)
258 retvalue =
259 rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA);
260 else if (rfpath == RF90_PATH_B)
261 retvalue =
262 rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA);
263 }
264
265 /*<20120809, Kordan> CCA ON(when exiting),
266 * asked by James to avoid reading the wrong value.
267 * <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!
268 */
269 if (offset != 0x0 &&
270 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
271 (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
272 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0);
273 return retvalue;
274}
275
276static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
277 enum radio_path rfpath, u32 offset,
278 u32 data)
279{
280 struct rtl_priv *rtlpriv = rtl_priv(hw);
281 struct rtl_phy *rtlphy = &rtlpriv->phy;
282 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
283 u32 data_and_addr;
284 u32 newoffset;
285
286 if (RT_CANNOT_IO(hw)) {
287 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
288 return;
289 }
290 offset &= 0xff;
291 newoffset = offset;
292 data_and_addr = ((newoffset << 20) |
293 (data & 0x000fffff)) & 0x0fffffff;
294 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
295 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
296 "RFW-%d Addr[0x%x]=0x%x\n",
297 rfpath, pphyreg->rf3wire_offset, data_and_addr);
298}
299
300static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask)
301{
302 u32 i;
303
304 for (i = 0; i <= 31; i++) {
305 if (((bitmask >> i) & 0x1) == 1)
306 break;
307 }
308 return i;
309}
310
311bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw)
312{
313 bool rtstatus = 0;
314
315 rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw);
316
317 return rtstatus;
318}
319
320bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw)
321{
322 bool rtstatus = true;
323 struct rtl_priv *rtlpriv = rtl_priv(hw);
324 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
325 struct rtl_phy *rtlphy = &rtlpriv->phy;
326 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
327 u8 regval;
328 u8 crystal_cap;
329
330 phy_init_bb_rf_register_definition(hw);
331
332 regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
333 regval |= FEN_PCIEA;
334 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval);
335 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
336 regval | FEN_BB_GLB_RSTN | FEN_BBRSTB);
337
338 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7);
339 rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7);
340
341 rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw);
342
343 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
344 crystal_cap = rtlefuse->crystalcap & 0x3F;
345 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000,
346 (crystal_cap | (crystal_cap << 6)));
347 } else {
348 crystal_cap = rtlefuse->crystalcap & 0x3F;
349 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
350 (crystal_cap | (crystal_cap << 6)));
351 }
352 rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837);
353
354 return rtstatus;
355}
356
357bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw)
358{
359 return rtl8821ae_phy_rf6052_config(hw);
360}
361
362u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band,
363 u8 rf_path)
364{
365 struct rtl_priv *rtlpriv = rtl_priv(hw);
366 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
367 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
368 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
369 char reg_swing_2g = -1;/* 0xff; */
370 char reg_swing_5g = -1;/* 0xff; */
371 char swing_2g = -1 * reg_swing_2g;
372 char swing_5g = -1 * reg_swing_5g;
373 u32 out = 0x200;
374 const char auto_temp = -1;
375
376 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
377 "===> PHY_GetTxBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d,autoload_failflag=%d.\n",
378 (int)swing_2g, (int)swing_5g,
379 (int)rtlefuse->autoload_failflag);
380
381 if (rtlefuse->autoload_failflag) {
382 if (band == BAND_ON_2_4G) {
383 rtldm->swing_diff_2g = swing_2g;
384 if (swing_2g == 0) {
385 out = 0x200; /* 0 dB */
386 } else if (swing_2g == -3) {
387 out = 0x16A; /* -3 dB */
388 } else if (swing_2g == -6) {
389 out = 0x101; /* -6 dB */
390 } else if (swing_2g == -9) {
391 out = 0x0B6; /* -9 dB */
392 } else {
393 rtldm->swing_diff_2g = 0;
394 out = 0x200;
395 }
396 } else if (band == BAND_ON_5G) {
397 rtldm->swing_diff_5g = swing_5g;
398 if (swing_5g == 0) {
399 out = 0x200; /* 0 dB */
400 } else if (swing_5g == -3) {
401 out = 0x16A; /* -3 dB */
402 } else if (swing_5g == -6) {
403 out = 0x101; /* -6 dB */
404 } else if (swing_5g == -9) {
405 out = 0x0B6; /* -9 dB */
406 } else {
407 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
408 rtldm->swing_diff_5g = -3;
409 out = 0x16A;
410 } else {
411 rtldm->swing_diff_5g = 0;
412 out = 0x200;
413 }
414 }
415 } else {
416 rtldm->swing_diff_2g = -3;
417 rtldm->swing_diff_5g = -3;
418 out = 0x16A; /* -3 dB */
419 }
420 } else {
421 u32 swing = 0, swing_a = 0, swing_b = 0;
422
423 if (band == BAND_ON_2_4G) {
424 if (reg_swing_2g == auto_temp) {
425 efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing);
426 swing = (swing == 0xFF) ? 0x00 : swing;
427 } else if (swing_2g == 0) {
428 swing = 0x00; /* 0 dB */
429 } else if (swing_2g == -3) {
430 swing = 0x05; /* -3 dB */
431 } else if (swing_2g == -6) {
432 swing = 0x0A; /* -6 dB */
433 } else if (swing_2g == -9) {
434 swing = 0xFF; /* -9 dB */
435 } else {
436 swing = 0x00;
437 }
438 } else {
439 if (reg_swing_5g == auto_temp) {
440 efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing);
441 swing = (swing == 0xFF) ? 0x00 : swing;
442 } else if (swing_5g == 0) {
443 swing = 0x00; /* 0 dB */
444 } else if (swing_5g == -3) {
445 swing = 0x05; /* -3 dB */
446 } else if (swing_5g == -6) {
447 swing = 0x0A; /* -6 dB */
448 } else if (swing_5g == -9) {
449 swing = 0xFF; /* -9 dB */
450 } else {
451 swing = 0x00;
452 }
453 }
454
455 swing_a = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */
456 swing_b = (swing & 0xC) >> 2; /* 0xC6/C7[3:2] */
457 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
458 "===> PHY_GetTxBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n",
459 swing_a, swing_b);
460
461 /* 3 Path-A */
462 if (swing_a == 0x0) {
463 if (band == BAND_ON_2_4G)
464 rtldm->swing_diff_2g = 0;
465 else
466 rtldm->swing_diff_5g = 0;
467 out = 0x200; /* 0 dB */
468 } else if (swing_a == 0x1) {
469 if (band == BAND_ON_2_4G)
470 rtldm->swing_diff_2g = -3;
471 else
472 rtldm->swing_diff_5g = -3;
473 out = 0x16A; /* -3 dB */
474 } else if (swing_a == 0x2) {
475 if (band == BAND_ON_2_4G)
476 rtldm->swing_diff_2g = -6;
477 else
478 rtldm->swing_diff_5g = -6;
479 out = 0x101; /* -6 dB */
480 } else if (swing_a == 0x3) {
481 if (band == BAND_ON_2_4G)
482 rtldm->swing_diff_2g = -9;
483 else
484 rtldm->swing_diff_5g = -9;
485 out = 0x0B6; /* -9 dB */
486 }
487 /* 3 Path-B */
488 if (swing_b == 0x0) {
489 if (band == BAND_ON_2_4G)
490 rtldm->swing_diff_2g = 0;
491 else
492 rtldm->swing_diff_5g = 0;
493 out = 0x200; /* 0 dB */
494 } else if (swing_b == 0x1) {
495 if (band == BAND_ON_2_4G)
496 rtldm->swing_diff_2g = -3;
497 else
498 rtldm->swing_diff_5g = -3;
499 out = 0x16A; /* -3 dB */
500 } else if (swing_b == 0x2) {
501 if (band == BAND_ON_2_4G)
502 rtldm->swing_diff_2g = -6;
503 else
504 rtldm->swing_diff_5g = -6;
505 out = 0x101; /* -6 dB */
506 } else if (swing_b == 0x3) {
507 if (band == BAND_ON_2_4G)
508 rtldm->swing_diff_2g = -9;
509 else
510 rtldm->swing_diff_5g = -9;
511 out = 0x0B6; /* -9 dB */
512 }
513 }
514
515 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
516 "<=== PHY_GetTxBBSwing_8812A, out = 0x%X\n", out);
517 return out;
518}
519
520void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
521{
522 struct rtl_priv *rtlpriv = rtl_priv(hw);
523 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
524 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
525 u8 current_band = rtlhal->current_bandtype;
526 u32 txpath, rxpath;
527 char bb_diff_between_band;
528
529 txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0);
530 rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000);
531 rtlhal->current_bandtype = (enum band_type) band;
532 /* reconfig BB/RF according to wireless mode */
533 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
534 /* BB & RF Config */
535 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
536
537 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
538 /* 0xCB0[15:12] = 0x7 (LNA_On)*/
539 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7);
540 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
541 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7);
542 }
543
544 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
545 /*0x834[1:0] = 0x1*/
546 rtl_set_bbreg(hw, 0x834, 0x3, 0x1);
547 }
548
549 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
550 /* 0xC1C[11:8] = 0 */
551 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0);
552 } else {
553 /* 0x82C[1:0] = 2b'00 */
554 rtl_set_bbreg(hw, 0x82c, 0x3, 0);
555 }
556 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
557 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD,
558 0x77777777);
559 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
560 0x77777777);
561 rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x000);
562 rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x000);
563 }
564
565 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1);
566 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1);
567
568 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0);
569 } else {/* 5G band */
570 u16 count, reg_41a;
571
572 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
573 /*0xCB0[15:12] = 0x5 (LNA_On)*/
574 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5);
575 /*0xCB0[7:4] = 0x4 (PAPE_A)*/
576 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4);
577 }
578 /*CCK_CHECK_en*/
579 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80);
580
581 count = 0;
582 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
583 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
584 "Reg41A value %d", reg_41a);
585 reg_41a &= 0x30;
586 while ((reg_41a != 0x30) && (count < 50)) {
587 udelay(50);
588 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "Delay 50us\n");
589
590 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
591 reg_41a &= 0x30;
592 count++;
593 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
594 "Reg41A value %d", reg_41a);
595 }
596 if (count != 0)
597 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
598 "PHY_SwitchWirelessBand8812(): Switch to 5G Band. Count = %d reg41A=0x%x\n",
599 count, reg_41a);
600
601 /* 2012/02/01, Sinda add registry to switch workaround
602 without long-run verification for scan issue. */
603 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
604
605 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
606 /*0x834[1:0] = 0x2*/
607 rtl_set_bbreg(hw, 0x834, 0x3, 0x2);
608 }
609
610 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
611 /* AGC table select */
612 /* 0xC1C[11:8] = 1*/
613 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1);
614 } else
615 /* 0x82C[1:0] = 2'b00 */
616 rtl_set_bbreg(hw, 0x82c, 0x3, 1);
617
618 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
619 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD,
620 0x77337777);
621 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
622 0x77337777);
623 rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x010);
624 rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x010);
625 }
626
627 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0);
628 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf);
629
630 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
631 "==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n",
632 rtlpriv->dm.ofdm_index[RF90_PATH_A]);
633 }
634
635 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
636 (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) {
637 /* 0xC1C[31:21] */
638 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
639 phy_get_tx_swing_8812A(hw, band, RF90_PATH_A));
640 /* 0xE1C[31:21] */
641 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
642 phy_get_tx_swing_8812A(hw, band, RF90_PATH_B));
643
644 /* <20121005, Kordan> When TxPowerTrack is ON,
645 * we should take care of the change of BB swing.
646 * That is, reset all info to trigger Tx power tracking.
647 */
648 if (band != current_band) {
649 bb_diff_between_band =
650 (rtldm->swing_diff_2g - rtldm->swing_diff_5g);
651 bb_diff_between_band = (band == BAND_ON_2_4G) ?
652 bb_diff_between_band :
653 (-1 * bb_diff_between_band);
654 rtldm->default_ofdm_index += bb_diff_between_band * 2;
655 }
656 rtl8821ae_dm_clear_txpower_tracking_state(hw);
657 }
658
659 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
660 "<==rtl8821ae_phy_switch_wirelessband():Switch Band OK.\n");
661 return;
662}
663
664static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw,
665 const u32 condition)
666{
667 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
668 u32 _board = rtlefuse->board_type; /*need efuse define*/
669 u32 _interface = 0x01; /* ODM_ITRF_PCIE */
670 u32 _platform = 0x08;/* ODM_WIN */
671 u32 cond = condition;
672
673 if (condition == 0xCDCDCDCD)
674 return true;
675
676 cond = condition & 0xFF;
677 if ((_board != cond) && cond != 0xFF)
678 return false;
679
680 cond = condition & 0xFF00;
681 cond = cond >> 8;
682 if ((_interface & cond) == 0 && cond != 0x07)
683 return false;
684
685 cond = condition & 0xFF0000;
686 cond = cond >> 16;
687 if ((_platform & cond) == 0 && cond != 0x0F)
688 return false;
689 return true;
690}
691
692static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw,
693 u32 addr, u32 data,
694 enum radio_path rfpath, u32 regaddr)
695{
696 if (addr == 0xfe || addr == 0xffe) {
697 /* In order not to disturb BT music when
698 * wifi init.(1ant NIC only)
699 */
700 mdelay(50);
701 } else {
702 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
703 udelay(1);
704 }
705}
706
707static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw,
708 u32 addr, u32 data)
709{
710 u32 content = 0x1000; /*RF Content: radio_a_txt*/
711 u32 maskforphyset = (u32)(content & 0xE000);
712
713 _rtl8821ae_config_rf_reg(hw, addr, data,
714 RF90_PATH_A, addr | maskforphyset);
715}
716
717static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw,
718 u32 addr, u32 data)
719{
720 u32 content = 0x1001; /*RF Content: radio_b_txt*/
721 u32 maskforphyset = (u32)(content & 0xE000);
722
723 _rtl8821ae_config_rf_reg(hw, addr, data,
724 RF90_PATH_B, addr | maskforphyset);
725}
726
727static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw,
728 u32 addr, u32 data)
729{
730 if (addr == 0xfe)
731 mdelay(50);
732 else if (addr == 0xfd)
733 mdelay(5);
734 else if (addr == 0xfc)
735 mdelay(1);
736 else if (addr == 0xfb)
737 udelay(50);
738 else if (addr == 0xfa)
739 udelay(5);
740 else if (addr == 0xf9)
741 udelay(1);
742 else
743 rtl_set_bbreg(hw, addr, MASKDWORD, data);
744
745 udelay(1);
746}
747
748static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
749{
750 struct rtl_priv *rtlpriv = rtl_priv(hw);
751 struct rtl_phy *rtlphy = &rtlpriv->phy;
752 u8 band, rfpath, txnum, rate_section;
753
754 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
755 for (rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath)
756 for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
757 for (rate_section = 0;
758 rate_section < TX_PWR_BY_RATE_NUM_SECTION;
759 ++rate_section)
760 rtlphy->tx_power_by_rate_offset[band]
761 [rfpath][txnum][rate_section] = 0;
762}
763
764static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
765 u8 band, u8 path,
766 u8 rate_section,
767 u8 txnum, u8 value)
768{
769 struct rtl_priv *rtlpriv = rtl_priv(hw);
770 struct rtl_phy *rtlphy = &rtlpriv->phy;
771
772 if (path > RF90_PATH_D) {
773 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
774 "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path);
775 return;
776 }
777
778 if (band == BAND_ON_2_4G) {
779 switch (rate_section) {
780 case CCK:
781 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
782 break;
783 case OFDM:
784 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
785 break;
786 case HT_MCS0_MCS7:
787 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
788 break;
789 case HT_MCS8_MCS15:
790 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
791 break;
792 case VHT_1SSMCS0_1SSMCS9:
793 rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value;
794 break;
795 case VHT_2SSMCS0_2SSMCS9:
796 rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value;
797 break;
798 default:
799 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
800 "Invalid RateSection %d in Band 2.4G,Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
801 rate_section, path, txnum);
802 break;
803 };
804 } else if (band == BAND_ON_5G) {
805 switch (rate_section) {
806 case OFDM:
807 rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value;
808 break;
809 case HT_MCS0_MCS7:
810 rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value;
811 break;
812 case HT_MCS8_MCS15:
813 rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value;
814 break;
815 case VHT_1SSMCS0_1SSMCS9:
816 rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value;
817 break;
818 case VHT_2SSMCS0_2SSMCS9:
819 rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value;
820 break;
821 default:
822 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
823 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
824 rate_section, path, txnum);
825 break;
826 };
827 } else {
828 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
829 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band);
830 }
831}
832
833static u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
834 u8 band, u8 path,
835 u8 txnum, u8 rate_section)
836{
837 struct rtl_priv *rtlpriv = rtl_priv(hw);
838 struct rtl_phy *rtlphy = &rtlpriv->phy;
839 u8 value = 0;
840
841 if (path > RF90_PATH_D) {
842 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
843 "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
844 path);
845 return 0;
846 }
847
848 if (band == BAND_ON_2_4G) {
849 switch (rate_section) {
850 case CCK:
851 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
852 break;
853 case OFDM:
854 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
855 break;
856 case HT_MCS0_MCS7:
857 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
858 break;
859 case HT_MCS8_MCS15:
860 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
861 break;
862 case VHT_1SSMCS0_1SSMCS9:
863 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4];
864 break;
865 case VHT_2SSMCS0_2SSMCS9:
866 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5];
867 break;
868 default:
869 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
870 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
871 rate_section, path, txnum);
872 break;
873 };
874 } else if (band == BAND_ON_5G) {
875 switch (rate_section) {
876 case OFDM:
877 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0];
878 break;
879 case HT_MCS0_MCS7:
880 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1];
881 break;
882 case HT_MCS8_MCS15:
883 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2];
884 break;
885 case VHT_1SSMCS0_1SSMCS9:
886 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3];
887 break;
888 case VHT_2SSMCS0_2SSMCS9:
889 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4];
890 break;
891 default:
892 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
893 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
894 rate_section, path, txnum);
895 break;
896 };
897 } else {
898 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
899 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band);
900 }
901
902 return value;
903}
904
905static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
906{
907 struct rtl_priv *rtlpriv = rtl_priv(hw);
908 struct rtl_phy *rtlphy = &rtlpriv->phy;
909 u16 rawValue = 0;
910 u8 base = 0, path = 0;
911
912 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
913 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF;
914 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
915 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base);
916
917 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF;
918 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
919 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base);
920
921 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF;
922 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
923 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base);
924
925 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF;
926 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
927 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base);
928
929 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF;
930 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
931 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
932
933 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF;
934 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
935 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
936
937 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF;
938 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
939 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base);
940
941 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF;
942 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
943 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base);
944
945 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF;
946 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
947 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base);
948
949 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF;
950 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
951 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
952
953 rawValue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF;
954 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
955 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
956 }
957}
958
959static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
960 u8 end, u8 base_val)
961{
962 char i = 0;
963 u8 temp_value = 0;
964 u32 temp_data = 0;
965
966 for (i = 3; i >= 0; --i) {
967 if (i >= start && i <= end) {
968 /* Get the exact value */
969 temp_value = (u8)(*data >> (i * 8)) & 0xF;
970 temp_value += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10;
971
972 /* Change the value to a relative value */
973 temp_value = (temp_value > base_val) ? temp_value -
974 base_val : base_val - temp_value;
975 } else {
976 temp_value = (u8)(*data >> (i * 8)) & 0xFF;
977 }
978 temp_data <<= 8;
979 temp_data |= temp_value;
980 }
981 *data = temp_data;
982}
983
984static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw)
985{
986 struct rtl_priv *rtlpriv = rtl_priv(hw);
987 struct rtl_phy *rtlphy = &rtlpriv->phy;
988 u8 regulation, bw, channel, rate_section;
989 char temp_pwrlmt = 0;
990
991 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
992 for (bw = 0; bw < MAX_5G_BANDWITH_NUM; ++bw) {
993 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
994 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
995 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
996 [bw][rate_section][channel][RF90_PATH_A];
997 if (temp_pwrlmt == MAX_POWER_INDEX) {
998 if (bw == 0 || bw == 1) { /*5G 20M 40M VHT and HT can cross reference*/
999 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1000 "No power limit table of the specified band %d, bandwidth %d, ratesection %d, channel %d, rf path %d\n",
1001 1, bw, rate_section, channel, RF90_PATH_A);
1002 if (rate_section == 2) {
1003 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A] =
1004 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A];
1005 } else if (rate_section == 4) {
1006 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A] =
1007 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A];
1008 } else if (rate_section == 3) {
1009 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A] =
1010 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A];
1011 } else if (rate_section == 5) {
1012 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A] =
1013 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A];
1014 }
1015
1016 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "use other value %d", temp_pwrlmt);
1017 }
1018 }
1019 }
1020 }
1021 }
1022 }
1023}
1024
1025static u8 _rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw *hw,
1026 enum band_type band, u8 rate)
1027{
1028 struct rtl_priv *rtlpriv = rtl_priv(hw);
1029 u8 index = 0;
1030 if (band == BAND_ON_2_4G) {
1031 switch (rate) {
1032 case MGN_1M:
1033 case MGN_2M:
1034 case MGN_5_5M:
1035 case MGN_11M:
1036 index = 0;
1037 break;
1038
1039 case MGN_6M:
1040 case MGN_9M:
1041 case MGN_12M:
1042 case MGN_18M:
1043 case MGN_24M:
1044 case MGN_36M:
1045 case MGN_48M:
1046 case MGN_54M:
1047 index = 1;
1048 break;
1049
1050 case MGN_MCS0:
1051 case MGN_MCS1:
1052 case MGN_MCS2:
1053 case MGN_MCS3:
1054 case MGN_MCS4:
1055 case MGN_MCS5:
1056 case MGN_MCS6:
1057 case MGN_MCS7:
1058 index = 2;
1059 break;
1060
1061 case MGN_MCS8:
1062 case MGN_MCS9:
1063 case MGN_MCS10:
1064 case MGN_MCS11:
1065 case MGN_MCS12:
1066 case MGN_MCS13:
1067 case MGN_MCS14:
1068 case MGN_MCS15:
1069 index = 3;
1070 break;
1071
1072 default:
1073 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1074 "Wrong rate 0x%x to obtain index in 2.4G in PHY_GetTxPowerByRateBaseIndex()\n",
1075 rate);
1076 break;
1077 }
1078 } else if (band == BAND_ON_5G) {
1079 switch (rate) {
1080 case MGN_6M:
1081 case MGN_9M:
1082 case MGN_12M:
1083 case MGN_18M:
1084 case MGN_24M:
1085 case MGN_36M:
1086 case MGN_48M:
1087 case MGN_54M:
1088 index = 0;
1089 break;
1090
1091 case MGN_MCS0:
1092 case MGN_MCS1:
1093 case MGN_MCS2:
1094 case MGN_MCS3:
1095 case MGN_MCS4:
1096 case MGN_MCS5:
1097 case MGN_MCS6:
1098 case MGN_MCS7:
1099 index = 1;
1100 break;
1101
1102 case MGN_MCS8:
1103 case MGN_MCS9:
1104 case MGN_MCS10:
1105 case MGN_MCS11:
1106 case MGN_MCS12:
1107 case MGN_MCS13:
1108 case MGN_MCS14:
1109 case MGN_MCS15:
1110 index = 2;
1111 break;
1112
1113 case MGN_VHT1SS_MCS0:
1114 case MGN_VHT1SS_MCS1:
1115 case MGN_VHT1SS_MCS2:
1116 case MGN_VHT1SS_MCS3:
1117 case MGN_VHT1SS_MCS4:
1118 case MGN_VHT1SS_MCS5:
1119 case MGN_VHT1SS_MCS6:
1120 case MGN_VHT1SS_MCS7:
1121 case MGN_VHT1SS_MCS8:
1122 case MGN_VHT1SS_MCS9:
1123 index = 3;
1124 break;
1125
1126 case MGN_VHT2SS_MCS0:
1127 case MGN_VHT2SS_MCS1:
1128 case MGN_VHT2SS_MCS2:
1129 case MGN_VHT2SS_MCS3:
1130 case MGN_VHT2SS_MCS4:
1131 case MGN_VHT2SS_MCS5:
1132 case MGN_VHT2SS_MCS6:
1133 case MGN_VHT2SS_MCS7:
1134 case MGN_VHT2SS_MCS8:
1135 case MGN_VHT2SS_MCS9:
1136 index = 4;
1137 break;
1138
1139 default:
1140 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1141 "Wrong rate 0x%x to obtain index in 5G in PHY_GetTxPowerByRateBaseIndex()\n",
1142 rate);
1143 break;
1144 }
1145 }
1146
1147 return index;
1148}
1149
1150static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw)
1151{
1152 struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 struct rtl_phy *rtlphy = &rtlpriv->phy;
1154 u8 bw40_pwr_base_dbm2_4G, bw40_pwr_base_dbm5G;
1155 u8 regulation, bw, channel, rate_section;
1156 u8 base_index2_4G = 0;
1157 u8 base_index5G = 0;
1158 char temp_value = 0, temp_pwrlmt = 0;
1159 u8 rf_path = 0;
1160
1161 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1162 "=====> _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n");
1163
1164 _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw);
1165
1166 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1167 for (bw = 0; bw < MAX_2_4G_BANDWITH_NUM; ++bw) {
1168 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
1169 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1170 /* obtain the base dBm values in 2.4G band
1171 CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15*/
1172 if (rate_section == 0) { /*CCK*/
1173 base_index2_4G =
1174 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1175 BAND_ON_2_4G, MGN_11M);
1176 } else if (rate_section == 1) { /*OFDM*/
1177 base_index2_4G =
1178 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1179 BAND_ON_2_4G, MGN_54M);
1180 } else if (rate_section == 2) { /*HT IT*/
1181 base_index2_4G =
1182 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1183 BAND_ON_2_4G, MGN_MCS7);
1184 } else if (rate_section == 3) { /*HT 2T*/
1185 base_index2_4G =
1186 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1187 BAND_ON_2_4G, MGN_MCS15);
1188 }
1189
1190 temp_pwrlmt = rtlphy->txpwr_limit_2_4g[regulation]
1191 [bw][rate_section][channel][RF90_PATH_A];
1192
1193 for (rf_path = RF90_PATH_A;
1194 rf_path < MAX_RF_PATH_NUM;
1195 ++rf_path) {
1196 if (rate_section == 3)
1197 bw40_pwr_base_dbm2_4G =
1198 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_2TX][base_index2_4G];
1199 else
1200 bw40_pwr_base_dbm2_4G =
1201 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_1TX][base_index2_4G];
1202
1203 if (temp_pwrlmt != MAX_POWER_INDEX) {
1204 temp_value = temp_pwrlmt - bw40_pwr_base_dbm2_4G;
1205 rtlphy->txpwr_limit_2_4g[regulation]
1206 [bw][rate_section][channel][rf_path] =
1207 temp_value;
1208 }
1209
1210 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1211 "TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfPath %d] %d)\n",
1212 regulation, bw, rate_section, channel,
1213 rtlphy->txpwr_limit_2_4g[regulation][bw]
1214 [rate_section][channel][rf_path], (temp_pwrlmt == 63)
1215 ? 0 : temp_pwrlmt/2, channel, rf_path,
1216 bw40_pwr_base_dbm2_4G);
1217 }
1218 }
1219 }
1220 }
1221 }
1222 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1223 for (bw = 0; bw < MAX_5G_BANDWITH_NUM; ++bw) {
1224 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1225 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1226 /* obtain the base dBm values in 5G band
1227 OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15,
1228 VHT => 1SSMCS7, VHT 2T => 2SSMCS7*/
1229 if (rate_section == 1) { /*OFDM*/
1230 base_index5G =
1231 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1232 BAND_ON_5G, MGN_54M);
1233 } else if (rate_section == 2) { /*HT 1T*/
1234 base_index5G =
1235 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1236 BAND_ON_5G, MGN_MCS7);
1237 } else if (rate_section == 3) { /*HT 2T*/
1238 base_index5G =
1239 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1240 BAND_ON_5G, MGN_MCS15);
1241 } else if (rate_section == 4) { /*VHT 1T*/
1242 base_index5G =
1243 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1244 BAND_ON_5G, MGN_VHT1SS_MCS7);
1245 } else if (rate_section == 5) { /*VHT 2T*/
1246 base_index5G =
1247 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1248 BAND_ON_5G, MGN_VHT2SS_MCS7);
1249 }
1250
1251 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
1252 [bw][rate_section][channel]
1253 [RF90_PATH_A];
1254
1255 for (rf_path = RF90_PATH_A;
1256 rf_path < MAX_RF_PATH_NUM;
1257 ++rf_path) {
1258 if (rate_section == 3 || rate_section == 5)
1259 bw40_pwr_base_dbm5G =
1260 rtlphy->txpwr_by_rate_base_5g[rf_path]
1261 [RF_2TX][base_index5G];
1262 else
1263 bw40_pwr_base_dbm5G =
1264 rtlphy->txpwr_by_rate_base_5g[rf_path]
1265 [RF_1TX][base_index5G];
1266
1267 if (temp_pwrlmt != MAX_POWER_INDEX) {
1268 temp_value =
1269 temp_pwrlmt - bw40_pwr_base_dbm5G;
1270 rtlphy->txpwr_limit_5g[regulation]
1271 [bw][rate_section][channel]
1272 [rf_path] = temp_value;
1273 }
1274
1275 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1276 "TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfPath %d] %d)\n",
1277 regulation, bw, rate_section,
1278 channel, rtlphy->txpwr_limit_5g[regulation]
1279 [bw][rate_section][channel][rf_path],
1280 temp_pwrlmt, channel, rf_path, bw40_pwr_base_dbm5G);
1281 }
1282 }
1283 }
1284 }
1285 }
1286 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1287 "<===== _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n");
1288}
1289
1290static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw *hw)
1291{
1292 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 struct rtl_phy *rtlphy = &rtlpriv->phy;
1294 u8 i, j, k, l, m;
1295
1296 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1297 "=====> _rtl8821ae_phy_init_txpower_limit()!\n");
1298
1299 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1300 for (j = 0; j < MAX_2_4G_BANDWITH_NUM; ++j)
1301 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1302 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
1303 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1304 rtlphy->txpwr_limit_2_4g
1305 [i][j][k][m][l]
1306 = MAX_POWER_INDEX;
1307 }
1308 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1309 for (j = 0; j < MAX_5G_BANDWITH_NUM; ++j)
1310 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1311 for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m)
1312 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1313 rtlphy->txpwr_limit_5g
1314 [i][j][k][m][l]
1315 = MAX_POWER_INDEX;
1316 }
1317
1318 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1319 "<===== _rtl8821ae_phy_init_txpower_limit()!\n");
1320}
1321
1322static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
1323{
1324 struct rtl_priv *rtlpriv = rtl_priv(hw);
1325 struct rtl_phy *rtlphy = &rtlpriv->phy;
1326 u8 base = 0, rfPath = 0;
1327
1328 for (rfPath = RF90_PATH_A; rfPath <= RF90_PATH_B; ++rfPath) {
1329 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, CCK);
1330 _phy_convert_txpower_dbm_to_relative_value(
1331 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][0],
1332 0, 3, base);
1333
1334 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, OFDM);
1335 _phy_convert_txpower_dbm_to_relative_value(
1336 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][1],
1337 0, 3, base);
1338 _phy_convert_txpower_dbm_to_relative_value(
1339 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][2],
1340 0, 3, base);
1341
1342 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, HT_MCS0_MCS7);
1343 _phy_convert_txpower_dbm_to_relative_value(
1344 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][3],
1345 0, 3, base);
1346 _phy_convert_txpower_dbm_to_relative_value(
1347 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][4],
1348 0, 3, base);
1349
1350 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, HT_MCS8_MCS15);
1351
1352 _phy_convert_txpower_dbm_to_relative_value(
1353 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][5],
1354 0, 3, base);
1355
1356 _phy_convert_txpower_dbm_to_relative_value(
1357 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][6],
1358 0, 3, base);
1359
1360 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1361 _phy_convert_txpower_dbm_to_relative_value(
1362 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][7],
1363 0, 3, base);
1364 _phy_convert_txpower_dbm_to_relative_value(
1365 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][8],
1366 0, 3, base);
1367 _phy_convert_txpower_dbm_to_relative_value(
1368 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][9],
1369 0, 1, base);
1370
1371 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1372 _phy_convert_txpower_dbm_to_relative_value(
1373 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][9],
1374 2, 3, base);
1375 _phy_convert_txpower_dbm_to_relative_value(
1376 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][10],
1377 0, 3, base);
1378 _phy_convert_txpower_dbm_to_relative_value(
1379 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][11],
1380 0, 3, base);
1381
1382 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, OFDM);
1383 _phy_convert_txpower_dbm_to_relative_value(
1384 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][1],
1385 0, 3, base);
1386 _phy_convert_txpower_dbm_to_relative_value(
1387 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][2],
1388 0, 3, base);
1389
1390 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, HT_MCS0_MCS7);
1391 _phy_convert_txpower_dbm_to_relative_value(
1392 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][3],
1393 0, 3, base);
1394 _phy_convert_txpower_dbm_to_relative_value(
1395 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][4],
1396 0, 3, base);
1397
1398 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, HT_MCS8_MCS15);
1399 _phy_convert_txpower_dbm_to_relative_value(
1400 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][5],
1401 0, 3, base);
1402 _phy_convert_txpower_dbm_to_relative_value(
1403 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][6],
1404 0, 3, base);
1405
1406 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1407 _phy_convert_txpower_dbm_to_relative_value(
1408 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][7],
1409 0, 3, base);
1410 _phy_convert_txpower_dbm_to_relative_value(
1411 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][8],
1412 0, 3, base);
1413 _phy_convert_txpower_dbm_to_relative_value(
1414 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][9],
1415 0, 1, base);
1416
1417 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1418 _phy_convert_txpower_dbm_to_relative_value(
1419 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][9],
1420 2, 3, base);
1421 _phy_convert_txpower_dbm_to_relative_value(
1422 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][10],
1423 0, 3, base);
1424 _phy_convert_txpower_dbm_to_relative_value(
1425 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][11],
1426 0, 3, base);
1427 }
1428
1429 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1430 "<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n");
1431}
1432
1433static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
1434{
1435 _rtl8821ae_phy_store_txpower_by_rate_base(hw);
1436 _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw);
1437}
1438
1439/* string is in decimal */
1440static bool _rtl8812ae_get_integer_from_string(char *str, u8 *pint)
1441{
1442 u16 i = 0;
1443 *pint = 0;
1444
1445 while (str[i] != '\0') {
1446 if (str[i] >= '0' && str[i] <= '9') {
1447 *pint *= 10;
1448 *pint += (str[i] - '0');
1449 } else {
1450 return false;
1451 }
1452 ++i;
1453 }
1454
1455 return true;
1456}
1457
1458static bool _rtl8812ae_eq_n_byte(u8 *str1, u8 *str2, u32 num)
1459{
1460 if (num == 0)
1461 return false;
1462 while (num > 0) {
1463 num--;
1464 if (str1[num] != str2[num])
1465 return false;
1466 }
1467 return true;
1468}
1469
1470static char _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw,
1471 u8 band, u8 channel)
1472{
1473 struct rtl_priv *rtlpriv = rtl_priv(hw);
1474 char channel_index = -1;
1475 u8 channel_5g[CHANNEL_MAX_NUMBER_5G] = {
1476 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
1477 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
1478 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 149,
1479 151, 153, 155, 157, 159, 161, 163, 165, 167, 168, 169, 171,
1480 173, 175, 177};
1481 u8 i = 0;
1482 if (band == BAND_ON_2_4G)
1483 channel_index = channel - 1;
1484 else if (band == BAND_ON_5G) {
1485 for (i = 0; i < sizeof(channel_5g)/sizeof(u8); ++i) {
1486 if (channel_5g[i] == channel)
1487 channel_index = i;
1488 }
1489 } else
1490 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Band %d in %s",
1491 band, __func__);
1492
1493 if (channel_index == -1)
1494 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1495 "Invalid Channel %d of Band %d in %s", channel,
1496 band, __func__);
1497
1498 return channel_index;
1499}
1500
1501static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation,
1502 u8 *pband, u8 *pbandwidth,
1503 u8 *prate_section, u8 *prf_path,
1504 u8 *pchannel, u8 *ppower_limit)
1505{
1506 struct rtl_priv *rtlpriv = rtl_priv(hw);
1507 struct rtl_phy *rtlphy = &rtlpriv->phy;
1508 u8 regulation = 0, bandwidth = 0, rate_section = 0, channel;
1509 u8 channel_index;
1510 char power_limit = 0, prev_power_limit, ret;
1511
1512 if (!_rtl8812ae_get_integer_from_string((char *)pchannel, &channel) ||
1513 !_rtl8812ae_get_integer_from_string((char *)ppower_limit,
1514 &power_limit)) {
1515 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1516 "Illegal index of pwr_lmt table [chnl %d][val %d]\n",
1517 channel, power_limit);
1518 }
1519
1520 power_limit = power_limit > MAX_POWER_INDEX ?
1521 MAX_POWER_INDEX : power_limit;
1522
1523 if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("FCC"), 3))
1524 regulation = 0;
1525 else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("MKK"), 3))
1526 regulation = 1;
1527 else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("ETSI"), 4))
1528 regulation = 2;
1529 else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("WW13"), 4))
1530 regulation = 3;
1531
1532 if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("CCK"), 3))
1533 rate_section = 0;
1534 else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("OFDM"), 4))
1535 rate_section = 1;
1536 else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
1537 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2))
1538 rate_section = 2;
1539 else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
1540 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2))
1541 rate_section = 3;
1542 else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
1543 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2))
1544 rate_section = 4;
1545 else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
1546 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2))
1547 rate_section = 5;
1548
1549 if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("20M"), 3))
1550 bandwidth = 0;
1551 else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("40M"), 3))
1552 bandwidth = 1;
1553 else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("80M"), 3))
1554 bandwidth = 2;
1555 else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("160M"), 4))
1556 bandwidth = 3;
1557
1558 if (_rtl8812ae_eq_n_byte(pband, (u8 *)("2.4G"), 4)) {
1559 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1560 BAND_ON_2_4G,
1561 channel);
1562
1563 if (ret == -1)
1564 return;
1565
1566 channel_index = ret;
1567
1568 prev_power_limit = rtlphy->txpwr_limit_2_4g[regulation]
1569 [bandwidth][rate_section]
1570 [channel_index][RF90_PATH_A];
1571
1572 if (power_limit < prev_power_limit)
1573 rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1574 [rate_section][channel_index][RF90_PATH_A] =
1575 power_limit;
1576
1577 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1578 "2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n",
1579 regulation, bandwidth, rate_section, channel_index,
1580 rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1581 [rate_section][channel_index][RF90_PATH_A]);
1582 } else if (_rtl8812ae_eq_n_byte(pband, (u8 *)("5G"), 2)) {
1583 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1584 BAND_ON_5G,
1585 channel);
1586
1587 if (ret == -1)
1588 return;
1589
1590 channel_index = ret;
1591
1592 prev_power_limit = rtlphy->txpwr_limit_5g[regulation][bandwidth]
1593 [rate_section][channel_index]
1594 [RF90_PATH_A];
1595
1596 if (power_limit < prev_power_limit)
1597 rtlphy->txpwr_limit_5g[regulation][bandwidth]
1598 [rate_section][channel_index][RF90_PATH_A] = power_limit;
1599
1600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1601 "5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n",
1602 regulation, bandwidth, rate_section, channel,
1603 rtlphy->txpwr_limit_5g[regulation][bandwidth]
1604 [rate_section][channel_index][RF90_PATH_A]);
1605 } else {
1606 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1607 "Cannot recognize the band info in %s\n", pband);
1608 return;
1609 }
1610}
1611
1612static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw,
1613 u8 *regulation, u8 *band,
1614 u8 *bandwidth, u8 *rate_section,
1615 u8 *rf_path, u8 *channel,
1616 u8 *power_limit)
1617{
1618 _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth,
1619 rate_section, rf_path, channel,
1620 power_limit);
1621}
1622
1623static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw)
1624{
1625 struct rtl_priv *rtlpriv = rtl_priv(hw);
1626 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1627 u32 i = 0;
1628 u32 array_len;
1629 u8 **array;
1630
1631 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1632 array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN;
1633 array = RTL8812AE_TXPWR_LMT;
1634 } else {
1635 array_len = RTL8821AE_TXPWR_LMT_ARRAY_LEN;
1636 array = RTL8821AE_TXPWR_LMT;
1637 }
1638
1639 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1640 "\n");
1641
1642 for (i = 0; i < array_len; i += 7) {
1643 u8 *regulation = array[i];
1644 u8 *band = array[i+1];
1645 u8 *bandwidth = array[i+2];
1646 u8 *rate = array[i+3];
1647 u8 *rf_path = array[i+4];
1648 u8 *chnl = array[i+5];
1649 u8 *val = array[i+6];
1650
1651 _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band,
1652 bandwidth, rate, rf_path,
1653 chnl, val);
1654 }
1655}
1656
1657static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw)
1658{
1659 struct rtl_priv *rtlpriv = rtl_priv(hw);
1660 struct rtl_phy *rtlphy = &rtlpriv->phy;
1661 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1662 bool rtstatus;
1663
1664 _rtl8821ae_phy_init_txpower_limit(hw);
1665
1666 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1667 if (rtlefuse->eeprom_regulatory != 2)
1668 _rtl8821ae_phy_read_and_config_txpwr_lmt(hw);
1669
1670 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1671 BASEBAND_CONFIG_PHY_REG);
1672 if (rtstatus != true) {
1673 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
1674 return false;
1675 }
1676 _rtl8821ae_phy_init_tx_power_by_rate(hw);
1677 if (rtlefuse->autoload_failflag == false) {
1678 rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw,
1679 BASEBAND_CONFIG_PHY_REG);
1680 }
1681 if (rtstatus != true) {
1682 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
1683 return false;
1684 }
1685
1686 _rtl8821ae_phy_txpower_by_rate_configuration(hw);
1687
1688 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1689 if (rtlefuse->eeprom_regulatory != 2)
1690 _rtl8812ae_phy_convert_txpower_limit_to_power_index(hw);
1691
1692 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1693 BASEBAND_CONFIG_AGC_TAB);
1694
1695 if (rtstatus != true) {
1696 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
1697 return false;
1698 }
1699 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
1700 RFPGA0_XA_HSSIPARAMETER2, 0x200));
1701 return true;
1702}
1703
1704static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1705{
1706 struct rtl_priv *rtlpriv = rtl_priv(hw);
1707 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1708 u32 i, v1, v2;
1709 u32 arraylength;
1710 u32 *ptrarray;
1711
1712 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read MAC_REG_Array\n");
1713 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1714 arraylength = RTL8821AEMAC_1T_ARRAYLEN;
1715 ptrarray = RTL8821AE_MAC_REG_ARRAY;
1716 } else {
1717 arraylength = RTL8812AEMAC_1T_ARRAYLEN;
1718 ptrarray = RTL8812AE_MAC_REG_ARRAY;
1719 }
1720 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1721 "Img: MAC_REG_ARRAY LEN %d\n", arraylength);
1722 for (i = 0; i < arraylength; i += 2) {
1723 v1 = ptrarray[i];
1724 v2 = (u8)ptrarray[i + 1];
1725 if (v1 < 0xCDCDCDCD) {
1726 rtl_write_byte(rtlpriv, v1, (u8)v2);
1727 continue;
1728 } else {
1729 if (!_rtl8821ae_check_condition(hw, v1)) {
1730 /*Discard the following (offset, data) pairs*/
1731 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1732 while (v2 != 0xDEAD &&
1733 v2 != 0xCDEF &&
1734 v2 != 0xCDCD && i < arraylength - 2) {
1735 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1736 }
1737 i -= 2; /* prevent from for-loop += 2*/
1738 } else {/*Configure matched pairs and skip to end of if-else.*/
1739 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1740 while (v2 != 0xDEAD &&
1741 v2 != 0xCDEF &&
1742 v2 != 0xCDCD && i < arraylength - 2) {
1743 rtl_write_byte(rtlpriv, v1, v2);
1744 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1745 }
1746
1747 while (v2 != 0xDEAD && i < arraylength - 2)
1748 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1749 }
1750 }
1751 }
1752 return true;
1753}
1754
1755static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1756 u8 configtype)
1757{
1758 struct rtl_priv *rtlpriv = rtl_priv(hw);
1759 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1760 int i;
1761 u32 *array_table;
1762 u16 arraylen;
1763 u32 v1 = 0, v2 = 0;
1764
1765 if (configtype == BASEBAND_CONFIG_PHY_REG) {
1766 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1767 arraylen = RTL8812AEPHY_REG_1TARRAYLEN;
1768 array_table = RTL8812AE_PHY_REG_ARRAY;
1769 } else {
1770 arraylen = RTL8821AEPHY_REG_1TARRAYLEN;
1771 array_table = RTL8821AE_PHY_REG_ARRAY;
1772 }
1773
1774 for (i = 0; i < arraylen; i += 2) {
1775 v1 = array_table[i];
1776 v2 = array_table[i + 1];
1777 if (v1 < 0xCDCDCDCD) {
1778 _rtl8821ae_config_bb_reg(hw, v1, v2);
1779 continue;
1780 } else {/*This line is the start line of branch.*/
1781 if (!_rtl8821ae_check_condition(hw, v1)) {
1782 /*Discard the following (offset, data) pairs*/
1783 READ_NEXT_PAIR(array_table, v1, v2, i);
1784 while (v2 != 0xDEAD &&
1785 v2 != 0xCDEF &&
1786 v2 != 0xCDCD &&
1787 i < arraylen - 2) {
1788 READ_NEXT_PAIR(array_table, v1,
1789 v2, i);
1790 }
1791
1792 i -= 2; /* prevent from for-loop += 2*/
1793 } else {/*Configure matched pairs and skip to end of if-else.*/
1794 READ_NEXT_PAIR(array_table, v1, v2, i);
1795 while (v2 != 0xDEAD &&
1796 v2 != 0xCDEF &&
1797 v2 != 0xCDCD &&
1798 i < arraylen - 2) {
1799 _rtl8821ae_config_bb_reg(hw, v1,
1800 v2);
1801 READ_NEXT_PAIR(array_table, v1,
1802 v2, i);
1803 }
1804
1805 while (v2 != 0xDEAD &&
1806 i < arraylen - 2) {
1807 READ_NEXT_PAIR(array_table, v1,
1808 v2, i);
1809 }
1810 }
1811 }
1812 }
1813 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1814 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1815 arraylen = RTL8812AEAGCTAB_1TARRAYLEN;
1816 array_table = RTL8812AE_AGC_TAB_ARRAY;
1817 } else {
1818 arraylen = RTL8821AEAGCTAB_1TARRAYLEN;
1819 array_table = RTL8821AE_AGC_TAB_ARRAY;
1820 }
1821
1822 for (i = 0; i < arraylen; i = i + 2) {
1823 v1 = array_table[i];
1824 v2 = array_table[i+1];
1825 if (v1 < 0xCDCDCDCD) {
1826 rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1827 udelay(1);
1828 continue;
1829 } else {/*This line is the start line of branch.*/
1830 if (!_rtl8821ae_check_condition(hw, v1)) {
1831 /*Discard the following (offset, data) pairs*/
1832 READ_NEXT_PAIR(array_table, v1, v2, i);
1833 while (v2 != 0xDEAD &&
1834 v2 != 0xCDEF &&
1835 v2 != 0xCDCD &&
1836 i < arraylen - 2) {
1837 READ_NEXT_PAIR(array_table, v1,
1838 v2, i);
1839 }
1840 i -= 2; /* prevent from for-loop += 2*/
1841 } else {/*Configure matched pairs and skip to end of if-else.*/
1842 READ_NEXT_PAIR(array_table, v1, v2, i);
1843 while (v2 != 0xDEAD &&
1844 v2 != 0xCDEF &&
1845 v2 != 0xCDCD &&
1846 i < arraylen - 2) {
1847 rtl_set_bbreg(hw, v1, MASKDWORD,
1848 v2);
1849 udelay(1);
1850 READ_NEXT_PAIR(array_table, v1,
1851 v2, i);
1852 }
1853
1854 while (v2 != 0xDEAD &&
1855 i < arraylen - 2) {
1856 READ_NEXT_PAIR(array_table, v1,
1857 v2, i);
1858 }
1859 }
1860 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1861 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
1862 array_table[i], array_table[i + 1]);
1863 }
1864 }
1865 }
1866 return true;
1867}
1868
1869static u8 _rtl8821ae_get_rate_section_index(u32 regaddr)
1870{
1871 u8 index = 0;
1872 regaddr &= 0xFFF;
1873 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
1874 index = (u8)((regaddr - 0xC20) / 4);
1875 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
1876 index = (u8)((regaddr - 0xE20) / 4);
1877 else
1878 RT_ASSERT(!COMP_INIT,
1879 "Invalid RegAddr 0x%x\n", regaddr);
1880 return index;
1881}
1882
1883static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw,
1884 u32 band, u32 rfpath,
1885 u32 txnum, u32 regaddr,
1886 u32 bitmask, u32 data)
1887{
1888 struct rtl_priv *rtlpriv = rtl_priv(hw);
1889 struct rtl_phy *rtlphy = &rtlpriv->phy;
1890 u8 rate_section = _rtl8821ae_get_rate_section_index(regaddr);
1891
1892 if (band != BAND_ON_2_4G && band != BAND_ON_5G)
1893 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid Band %d\n", band);
1894
1895 if (rfpath >= MAX_RF_PATH)
1896 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid RfPath %d\n", rfpath);
1897
1898 if (txnum >= MAX_RF_PATH)
1899 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid TxNum %d\n", txnum);
1900
1901 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data;
1902 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1903 "TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n",
1904 band, rfpath, txnum, rate_section,
1905 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]);
1906}
1907
1908static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
1909 u8 configtype)
1910{
1911 struct rtl_priv *rtlpriv = rtl_priv(hw);
1912 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1913 int i;
1914 u32 *array;
1915 u16 arraylen;
1916 u32 v1, v2, v3, v4, v5, v6;
1917
1918 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1919 arraylen = RTL8812AEPHY_REG_ARRAY_PGLEN;
1920 array = RTL8812AE_PHY_REG_ARRAY_PG;
1921 } else {
1922 arraylen = RTL8821AEPHY_REG_ARRAY_PGLEN;
1923 array = RTL8821AE_PHY_REG_ARRAY_PG;
1924 }
1925
1926 if (configtype != BASEBAND_CONFIG_PHY_REG) {
1927 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
1928 "configtype != BaseBand_Config_PHY_REG\n");
1929 return true;
1930 }
1931 for (i = 0; i < arraylen; i += 6) {
1932 v1 = array[i];
1933 v2 = array[i+1];
1934 v3 = array[i+2];
1935 v4 = array[i+3];
1936 v5 = array[i+4];
1937 v6 = array[i+5];
1938
1939 if (v1 < 0xCDCDCDCD) {
1940 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1941 (v4 == 0xfe || v4 == 0xffe)) {
1942 msleep(50);
1943 continue;
1944 }
1945
1946 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1947 if (v4 == 0xfe)
1948 msleep(50);
1949 else if (v4 == 0xfd)
1950 mdelay(5);
1951 else if (v4 == 0xfc)
1952 mdelay(1);
1953 else if (v4 == 0xfb)
1954 udelay(50);
1955 else if (v4 == 0xfa)
1956 udelay(5);
1957 else if (v4 == 0xf9)
1958 udelay(1);
1959 }
1960 _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3,
1961 v4, v5, v6);
1962 continue;
1963 } else {
1964 /*don't need the hw_body*/
1965 if (!_rtl8821ae_check_condition(hw, v1)) {
1966 i += 2; /* skip the pair of expression*/
1967 v1 = array[i];
1968 v2 = array[i+1];
1969 v3 = array[i+2];
1970 while (v2 != 0xDEAD) {
1971 i += 3;
1972 v1 = array[i];
1973 v2 = array[i+1];
1974 v3 = array[i+2];
1975 }
1976 }
1977 }
1978 }
1979
1980 return true;
1981}
1982
1983bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
1984 enum radio_path rfpath)
1985{
1986 int i;
1987 bool rtstatus = true;
1988 u32 *radioa_array_table_a, *radioa_array_table_b;
1989 u16 radioa_arraylen_a, radioa_arraylen_b;
1990 struct rtl_priv *rtlpriv = rtl_priv(hw);
1991 u32 v1 = 0, v2 = 0;
1992
1993 radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN;
1994 radioa_array_table_a = RTL8812AE_RADIOA_ARRAY;
1995 radioa_arraylen_b = RTL8812AE_RADIOB_1TARRAYLEN;
1996 radioa_array_table_b = RTL8812AE_RADIOB_ARRAY;
1997 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1998 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen_a);
1999 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2000 rtstatus = true;
2001 switch (rfpath) {
2002 case RF90_PATH_A:
2003 for (i = 0; i < radioa_arraylen_a; i = i + 2) {
2004 v1 = radioa_array_table_a[i];
2005 v2 = radioa_array_table_a[i+1];
2006 if (v1 < 0xcdcdcdcd) {
2007 _rtl8821ae_config_rf_radio_a(hw, v1, v2);
2008 continue;
2009 } else{/*This line is the start line of branch.*/
2010 if (!_rtl8821ae_check_condition(hw, v1)) {
2011 /*Discard the following (offset, data) pairs*/
2012 READ_NEXT_PAIR(radioa_array_table_a, v1, v2, i);
2013 while (v2 != 0xDEAD &&
2014 v2 != 0xCDEF &&
2015 v2 != 0xCDCD && i < radioa_arraylen_a-2)
2016 READ_NEXT_PAIR(radioa_array_table_a, v1, v2, i);
2017
2018 i -= 2; /* prevent from for-loop += 2*/
2019 } else {/*Configure matched pairs and skip to end of if-else.*/
2020 READ_NEXT_PAIR(radioa_array_table_a, v1, v2, i);
2021 while (v2 != 0xDEAD &&
2022 v2 != 0xCDEF &&
2023 v2 != 0xCDCD && i < radioa_arraylen_a - 2) {
2024 _rtl8821ae_config_rf_radio_a(hw, v1, v2);
2025 READ_NEXT_PAIR(radioa_array_table_a, v1, v2, i);
2026 }
2027
2028 while (v2 != 0xDEAD && i < radioa_arraylen_a-2)
2029 READ_NEXT_PAIR(radioa_array_table_a, v1, v2, i);
2030
2031 }
2032 }
2033 }
2034 break;
2035 case RF90_PATH_B:
2036 for (i = 0; i < radioa_arraylen_b; i = i + 2) {
2037 v1 = radioa_array_table_b[i];
2038 v2 = radioa_array_table_b[i+1];
2039 if (v1 < 0xcdcdcdcd) {
2040 _rtl8821ae_config_rf_radio_b(hw, v1, v2);
2041 continue;
2042 } else{/*This line is the start line of branch.*/
2043 if (!_rtl8821ae_check_condition(hw, v1)) {
2044 /*Discard the following (offset, data) pairs*/
2045 READ_NEXT_PAIR(radioa_array_table_b, v1, v2, i);
2046 while (v2 != 0xDEAD &&
2047 v2 != 0xCDEF &&
2048 v2 != 0xCDCD && i < radioa_arraylen_b-2)
2049 READ_NEXT_PAIR(radioa_array_table_b, v1, v2, i);
2050
2051 i -= 2; /* prevent from for-loop += 2*/
2052 } else {/*Configure matched pairs and skip to end of if-else.*/
2053 READ_NEXT_PAIR(radioa_array_table_b, v1, v2, i);
2054 while (v2 != 0xDEAD &&
2055 v2 != 0xCDEF &&
2056 v2 != 0xCDCD && i < radioa_arraylen_b-2) {
2057 _rtl8821ae_config_rf_radio_b(hw, v1, v2);
2058 READ_NEXT_PAIR(radioa_array_table_b, v1, v2, i);
2059 }
2060
2061 while (v2 != 0xDEAD && i < radioa_arraylen_b-2)
2062 READ_NEXT_PAIR(radioa_array_table_b, v1, v2, i);
2063 }
2064 }
2065 }
2066 break;
2067 case RF90_PATH_C:
2068 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2069 "switch case not process\n");
2070 break;
2071 case RF90_PATH_D:
2072 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2073 "switch case not process\n");
2074 break;
2075 }
2076 return true;
2077}
2078
2079bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
2080 enum radio_path rfpath)
2081{
2082 #define READ_NEXT_RF_PAIR(v1, v2, i) \
2083 do { \
2084 i += 2; \
2085 v1 = radioa_array_table[i]; \
2086 v2 = radioa_array_table[i+1]; \
2087 } \
2088 while (0)
2089
2090 int i;
2091 bool rtstatus = true;
2092 u32 *radioa_array_table;
2093 u16 radioa_arraylen;
2094 struct rtl_priv *rtlpriv = rtl_priv(hw);
2095 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */
2096 u32 v1 = 0, v2 = 0;
2097
2098 radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN;
2099 radioa_array_table = RTL8821AE_RADIOA_ARRAY;
2100 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2101 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen);
2102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2103 rtstatus = true;
2104 switch (rfpath) {
2105 case RF90_PATH_A:
2106 for (i = 0; i < radioa_arraylen; i = i + 2) {
2107 v1 = radioa_array_table[i];
2108 v2 = radioa_array_table[i+1];
2109 if (v1 < 0xcdcdcdcd)
2110 _rtl8821ae_config_rf_radio_a(hw, v1, v2);
2111 else{/*This line is the start line of branch.*/
2112 if (!_rtl8821ae_check_condition(hw, v1)) {
2113 /*Discard the following (offset, data) pairs*/
2114 READ_NEXT_RF_PAIR(v1, v2, i);
2115 while (v2 != 0xDEAD &&
2116 v2 != 0xCDEF &&
2117 v2 != 0xCDCD && i < radioa_arraylen - 2)
2118 READ_NEXT_RF_PAIR(v1, v2, i);
2119
2120 i -= 2; /* prevent from for-loop += 2*/
2121 } else {/*Configure matched pairs and skip to end of if-else.*/
2122 READ_NEXT_RF_PAIR(v1, v2, i);
2123 while (v2 != 0xDEAD &&
2124 v2 != 0xCDEF &&
2125 v2 != 0xCDCD && i < radioa_arraylen - 2) {
2126 _rtl8821ae_config_rf_radio_a(hw, v1, v2);
2127 READ_NEXT_RF_PAIR(v1, v2, i);
2128 }
2129
2130 while (v2 != 0xDEAD && i < radioa_arraylen - 2)
2131 READ_NEXT_RF_PAIR(v1, v2, i);
2132 }
2133 }
2134 }
2135 break;
2136
2137 case RF90_PATH_B:
2138 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2139 "switch case not process\n");
2140 break;
2141 case RF90_PATH_C:
2142 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2143 "switch case not process\n");
2144 break;
2145 case RF90_PATH_D:
2146 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2147 "switch case not process\n");
2148 break;
2149 }
2150 return true;
2151}
2152
2153void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
2154{
2155 struct rtl_priv *rtlpriv = rtl_priv(hw);
2156 struct rtl_phy *rtlphy = &rtlpriv->phy;
2157
2158 rtlphy->default_initialgain[0] =
2159 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
2160 rtlphy->default_initialgain[1] =
2161 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
2162 rtlphy->default_initialgain[2] =
2163 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
2164 rtlphy->default_initialgain[3] =
2165 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
2166
2167 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2168 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
2169 rtlphy->default_initialgain[0],
2170 rtlphy->default_initialgain[1],
2171 rtlphy->default_initialgain[2],
2172 rtlphy->default_initialgain[3]);
2173
2174 rtlphy->framesync = (u8)rtl_get_bbreg(hw,
2175 ROFDM0_RXDETECTOR3, MASKBYTE0);
2176 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
2177 ROFDM0_RXDETECTOR2, MASKDWORD);
2178
2179 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2180 "Default framesync (0x%x) = 0x%x\n",
2181 ROFDM0_RXDETECTOR3, rtlphy->framesync);
2182}
2183
2184static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
2185{
2186 struct rtl_priv *rtlpriv = rtl_priv(hw);
2187 struct rtl_phy *rtlphy = &rtlpriv->phy;
2188
2189 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2190 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2191
2192 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
2193 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
2194
2195 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
2196 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
2197
2198 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A;
2199 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A;
2200
2201 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE;
2202 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE;
2203
2204 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8821A;
2205 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8821A;
2206
2207 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8821A;
2208 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8821A;
2209}
2210
2211void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
2212{
2213 struct rtl_priv *rtlpriv = rtl_priv(hw);
2214 struct rtl_phy *rtlphy = &rtlpriv->phy;
2215 u8 txpwr_level;
2216 long txpwr_dbm;
2217
2218 txpwr_level = rtlphy->cur_cck_txpwridx;
2219 txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2220 WIRELESS_MODE_B, txpwr_level);
2221 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2222 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2223 WIRELESS_MODE_G,
2224 txpwr_level) > txpwr_dbm)
2225 txpwr_dbm =
2226 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
2227 txpwr_level);
2228 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2229 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2230 WIRELESS_MODE_N_24G,
2231 txpwr_level) > txpwr_dbm)
2232 txpwr_dbm =
2233 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
2234 txpwr_level);
2235 *powerlevel = txpwr_dbm;
2236}
2237
2238static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index)
2239{
2240 u8 channel_5g[CHANNEL_MAX_NUMBER_5G] = {
2241 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62,
2242 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118,
2243 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140,
2244 142, 144, 149, 151, 153, 155, 157, 159, 161, 163, 165,
2245 167, 168, 169, 171, 173, 175, 177
2246 };
2247 u8 i = 0;
2248 bool in_24g = true;
2249
2250 if (channel <= 14) {
2251 in_24g = true;
2252 *chnl_index = channel - 1;
2253 } else {
2254 in_24g = false;
2255
2256 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; ++i) {
2257 if (channel_5g[i] == channel) {
2258 *chnl_index = i;
2259 return in_24g;
2260 }
2261 }
2262 }
2263 return in_24g;
2264}
2265
2266static char _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate)
2267{
2268 char rate_section = 0;
2269 switch (rate) {
2270 case DESC_RATE1M:
2271 case DESC_RATE2M:
2272 case DESC_RATE5_5M:
2273 case DESC_RATE11M:
2274 rate_section = 0;
2275 break;
2276 case DESC_RATE6M:
2277 case DESC_RATE9M:
2278 case DESC_RATE12M:
2279 case DESC_RATE18M:
2280 rate_section = 1;
2281 break;
2282 case DESC_RATE24M:
2283 case DESC_RATE36M:
2284 case DESC_RATE48M:
2285 case DESC_RATE54M:
2286 rate_section = 2;
2287 break;
2288 case DESC_RATEMCS0:
2289 case DESC_RATEMCS1:
2290 case DESC_RATEMCS2:
2291 case DESC_RATEMCS3:
2292 rate_section = 3;
2293 break;
2294 case DESC_RATEMCS4:
2295 case DESC_RATEMCS5:
2296 case DESC_RATEMCS6:
2297 case DESC_RATEMCS7:
2298 rate_section = 4;
2299 break;
2300 case DESC_RATEMCS8:
2301 case DESC_RATEMCS9:
2302 case DESC_RATEMCS10:
2303 case DESC_RATEMCS11:
2304 rate_section = 5;
2305 break;
2306 case DESC_RATEMCS12:
2307 case DESC_RATEMCS13:
2308 case DESC_RATEMCS14:
2309 case DESC_RATEMCS15:
2310 rate_section = 6;
2311 break;
2312 case DESC_RATEVHT1SS_MCS0:
2313 case DESC_RATEVHT1SS_MCS1:
2314 case DESC_RATEVHT1SS_MCS2:
2315 case DESC_RATEVHT1SS_MCS3:
2316 rate_section = 7;
2317 break;
2318 case DESC_RATEVHT1SS_MCS4:
2319 case DESC_RATEVHT1SS_MCS5:
2320 case DESC_RATEVHT1SS_MCS6:
2321 case DESC_RATEVHT1SS_MCS7:
2322 rate_section = 8;
2323 break;
2324 case DESC_RATEVHT1SS_MCS8:
2325 case DESC_RATEVHT1SS_MCS9:
2326 case DESC_RATEVHT2SS_MCS0:
2327 case DESC_RATEVHT2SS_MCS1:
2328 rate_section = 9;
2329 break;
2330 case DESC_RATEVHT2SS_MCS2:
2331 case DESC_RATEVHT2SS_MCS3:
2332 case DESC_RATEVHT2SS_MCS4:
2333 case DESC_RATEVHT2SS_MCS5:
2334 rate_section = 10;
2335 break;
2336 case DESC_RATEVHT2SS_MCS6:
2337 case DESC_RATEVHT2SS_MCS7:
2338 case DESC_RATEVHT2SS_MCS8:
2339 case DESC_RATEVHT2SS_MCS9:
2340 rate_section = 11;
2341 break;
2342 default:
2343 RT_ASSERT(true, "Rate_Section is Illegal\n");
2344 break;
2345 }
2346
2347 return rate_section;
2348}
2349
2350static char _rtl8812ae_phy_get_world_wide_limit(char *limit_table)
2351{
2352 char min = limit_table[0];
2353 u8 i = 0;
2354
2355 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
2356 if (limit_table[i] < min)
2357 min = limit_table[i];
2358 }
2359 return min;
2360}
2361
2362static char _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw *hw,
2363 u8 band,
2364 enum ht_channel_width bandwidth,
2365 enum radio_path rf_path,
2366 u8 rate, u8 channel)
2367{
2368 struct rtl_priv *rtlpriv = rtl_priv(hw);
2369 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
2370 struct rtl_phy *rtlphy = &rtlpriv->phy;
2371 short band_temp = -1, regulation = -1, bandwidth_temp = -1,
2372 rate_section = -1, channel_temp = -1;
2373 u16 bd, regu, bdwidth, sec, chnl;
2374 char power_limit = MAX_POWER_INDEX;
2375
2376 if (rtlefuse->eeprom_regulatory == 2)
2377 return MAX_POWER_INDEX;
2378
2379 regulation = TXPWR_LMT_WW;
2380
2381 if (band == BAND_ON_2_4G)
2382 band_temp = 0;
2383 else if (band == BAND_ON_5G)
2384 band_temp = 1;
2385
2386 if (bandwidth == HT_CHANNEL_WIDTH_20)
2387 bandwidth_temp = 0;
2388 else if (bandwidth == HT_CHANNEL_WIDTH_20_40)
2389 bandwidth_temp = 1;
2390 else if (bandwidth == HT_CHANNEL_WIDTH_80)
2391 bandwidth_temp = 2;
2392
2393 switch (rate) {
2394 case DESC_RATE1M:
2395 case DESC_RATE2M:
2396 case DESC_RATE5_5M:
2397 case DESC_RATE11M:
2398 rate_section = 0;
2399 break;
2400 case DESC_RATE6M:
2401 case DESC_RATE9M:
2402 case DESC_RATE12M:
2403 case DESC_RATE18M:
2404 case DESC_RATE24M:
2405 case DESC_RATE36M:
2406 case DESC_RATE48M:
2407 case DESC_RATE54M:
2408 rate_section = 1;
2409 break;
2410 case DESC_RATEMCS0:
2411 case DESC_RATEMCS1:
2412 case DESC_RATEMCS2:
2413 case DESC_RATEMCS3:
2414 case DESC_RATEMCS4:
2415 case DESC_RATEMCS5:
2416 case DESC_RATEMCS6:
2417 case DESC_RATEMCS7:
2418 rate_section = 2;
2419 break;
2420 case DESC_RATEMCS8:
2421 case DESC_RATEMCS9:
2422 case DESC_RATEMCS10:
2423 case DESC_RATEMCS11:
2424 case DESC_RATEMCS12:
2425 case DESC_RATEMCS13:
2426 case DESC_RATEMCS14:
2427 case DESC_RATEMCS15:
2428 rate_section = 3;
2429 break;
2430 case DESC_RATEVHT1SS_MCS0:
2431 case DESC_RATEVHT1SS_MCS1:
2432 case DESC_RATEVHT1SS_MCS2:
2433 case DESC_RATEVHT1SS_MCS3:
2434 case DESC_RATEVHT1SS_MCS4:
2435 case DESC_RATEVHT1SS_MCS5:
2436 case DESC_RATEVHT1SS_MCS6:
2437 case DESC_RATEVHT1SS_MCS7:
2438 case DESC_RATEVHT1SS_MCS8:
2439 case DESC_RATEVHT1SS_MCS9:
2440 rate_section = 4;
2441 break;
2442 case DESC_RATEVHT2SS_MCS0:
2443 case DESC_RATEVHT2SS_MCS1:
2444 case DESC_RATEVHT2SS_MCS2:
2445 case DESC_RATEVHT2SS_MCS3:
2446 case DESC_RATEVHT2SS_MCS4:
2447 case DESC_RATEVHT2SS_MCS5:
2448 case DESC_RATEVHT2SS_MCS6:
2449 case DESC_RATEVHT2SS_MCS7:
2450 case DESC_RATEVHT2SS_MCS8:
2451 case DESC_RATEVHT2SS_MCS9:
2452 rate_section = 5;
2453 break;
2454 default:
2455 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2456 "Wrong rate 0x%x\n", rate);
2457 break;
2458 }
2459
2460 if (band_temp == BAND_ON_5G && rate_section == 0)
2461 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2462 "Wrong rate 0x%x: No CCK in 5G Band\n", rate);
2463
2464 /*workaround for wrong index combination to obtain tx power limit,
2465 OFDM only exists in BW 20M*/
2466 if (rate_section == 1)
2467 bandwidth_temp = 0;
2468
2469 /*workaround for wrong index combination to obtain tx power limit,
2470 *HT on 80M will reference to HT on 40M
2471 */
2472 if ((rate_section == 2 || rate_section == 3) && band == BAND_ON_5G &&
2473 bandwidth_temp == 2)
2474 bandwidth_temp = 1;
2475
2476 if (band == BAND_ON_2_4G)
2477 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2478 BAND_ON_2_4G, channel);
2479 else if (band == BAND_ON_5G)
2480 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2481 BAND_ON_5G, channel);
2482 else if (band == BAND_ON_BOTH)
2483 ;/* BAND_ON_BOTH don't care temporarily */
2484
2485 if (band_temp == -1 || regulation == -1 || bandwidth_temp == -1 ||
2486 rate_section == -1 || channel_temp == -1) {
2487 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2488 "Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n",
2489 band_temp, regulation, bandwidth_temp, rf_path,
2490 rate_section, channel_temp);
2491 return MAX_POWER_INDEX;
2492 }
2493
2494 bd = band_temp;
2495 regu = regulation;
2496 bdwidth = bandwidth_temp;
2497 sec = rate_section;
2498 chnl = channel_temp;
2499
2500 if (band == BAND_ON_2_4G) {
2501 char limits[10] = {0};
2502 u8 i;
2503
2504 for (i = 0; i < 4; ++i)
2505 limits[i] = rtlphy->txpwr_limit_2_4g[i][bdwidth]
2506 [sec][chnl][rf_path];
2507
2508 power_limit = (regulation == TXPWR_LMT_WW) ?
2509 _rtl8812ae_phy_get_world_wide_limit(limits) :
2510 rtlphy->txpwr_limit_2_4g[regu][bdwidth]
2511 [sec][chnl][rf_path];
2512 } else if (band == BAND_ON_5G) {
2513 char limits[10] = {0};
2514 u8 i;
2515
2516 for (i = 0; i < MAX_REGULATION_NUM; ++i)
2517 limits[i] = rtlphy->txpwr_limit_5g[i][bdwidth]
2518 [sec][chnl][rf_path];
2519
2520 power_limit = (regulation == TXPWR_LMT_WW) ?
2521 _rtl8812ae_phy_get_world_wide_limit(limits) :
2522 rtlphy->txpwr_limit_5g[regu][chnl]
2523 [sec][chnl][rf_path];
2524 } else {
2525 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2526 "No power limit table of the specified band\n");
2527 }
2528 return power_limit;
2529}
2530
2531static char _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw,
2532 u8 band, u8 path, u8 rate)
2533{
2534 struct rtl_priv *rtlpriv = rtl_priv(hw);
2535 struct rtl_phy *rtlphy = &rtlpriv->phy;
2536 u8 shift = 0, rate_section, tx_num;
2537 char tx_pwr_diff = 0;
2538 char limit = 0;
2539
2540 rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate);
2541 tx_num = RF_TX_NUM_NONIMPLEMENT;
2542
2543 if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
2544 if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
2545 (rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9))
2546 tx_num = RF_2TX;
2547 else
2548 tx_num = RF_1TX;
2549 }
2550
2551 switch (rate) {
2552 case DESC_RATE1M:
2553 case DESC_RATE6M:
2554 case DESC_RATE24M:
2555 case DESC_RATEMCS0:
2556 case DESC_RATEMCS4:
2557 case DESC_RATEMCS8:
2558 case DESC_RATEMCS12:
2559 case DESC_RATEVHT1SS_MCS0:
2560 case DESC_RATEVHT1SS_MCS4:
2561 case DESC_RATEVHT1SS_MCS8:
2562 case DESC_RATEVHT2SS_MCS2:
2563 case DESC_RATEVHT2SS_MCS6:
2564 shift = 0;
2565 break;
2566 case DESC_RATE2M:
2567 case DESC_RATE9M:
2568 case DESC_RATE36M:
2569 case DESC_RATEMCS1:
2570 case DESC_RATEMCS5:
2571 case DESC_RATEMCS9:
2572 case DESC_RATEMCS13:
2573 case DESC_RATEVHT1SS_MCS1:
2574 case DESC_RATEVHT1SS_MCS5:
2575 case DESC_RATEVHT1SS_MCS9:
2576 case DESC_RATEVHT2SS_MCS3:
2577 case DESC_RATEVHT2SS_MCS7:
2578 shift = 8;
2579 break;
2580 case DESC_RATE5_5M:
2581 case DESC_RATE12M:
2582 case DESC_RATE48M:
2583 case DESC_RATEMCS2:
2584 case DESC_RATEMCS6:
2585 case DESC_RATEMCS10:
2586 case DESC_RATEMCS14:
2587 case DESC_RATEVHT1SS_MCS2:
2588 case DESC_RATEVHT1SS_MCS6:
2589 case DESC_RATEVHT2SS_MCS0:
2590 case DESC_RATEVHT2SS_MCS4:
2591 case DESC_RATEVHT2SS_MCS8:
2592 shift = 16;
2593 break;
2594 case DESC_RATE11M:
2595 case DESC_RATE18M:
2596 case DESC_RATE54M:
2597 case DESC_RATEMCS3:
2598 case DESC_RATEMCS7:
2599 case DESC_RATEMCS11:
2600 case DESC_RATEMCS15:
2601 case DESC_RATEVHT1SS_MCS3:
2602 case DESC_RATEVHT1SS_MCS7:
2603 case DESC_RATEVHT2SS_MCS1:
2604 case DESC_RATEVHT2SS_MCS5:
2605 case DESC_RATEVHT2SS_MCS9:
2606 shift = 24;
2607 break;
2608 default:
2609 RT_ASSERT(true, "Rate_Section is Illegal\n");
2610 break;
2611 }
2612
2613 tx_pwr_diff = (u8)(rtlphy->tx_power_by_rate_offset[band][path]
2614 [tx_num][rate_section] >> shift) & 0xff;
2615
2616 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
2617 if (rtlpriv->efuse.eeprom_regulatory != 2) {
2618 limit = _rtl8812ae_phy_get_txpower_limit(hw, band,
2619 rtlphy->current_chan_bw, path, rate,
2620 rtlphy->current_channel);
2621
2622 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2623 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) {
2624 if (limit < 0) {
2625 if (tx_pwr_diff < (-limit))
2626 tx_pwr_diff = -limit;
2627 }
2628 } else {
2629 if (limit < 0)
2630 tx_pwr_diff = limit;
2631 else
2632 tx_pwr_diff = tx_pwr_diff > limit ? limit : tx_pwr_diff;
2633 }
2634 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2635 "Maximum power by rate %d, final power by rate %d\n",
2636 limit, tx_pwr_diff);
2637 }
2638
2639 return tx_pwr_diff;
2640}
2641
2642static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path,
2643 u8 rate, u8 bandwidth, u8 channel)
2644{
2645 struct rtl_priv *rtlpriv = rtl_priv(hw);
2646 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2647 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2648 u8 index = (channel - 1);
2649 u8 txpower = 0;
2650 bool in_24g = false;
2651 char powerdiff_byrate = 0;
2652
2653 if (((rtlhal->current_bandtype == BAND_ON_2_4G) &&
2654 (channel > 14 || channel < 1)) ||
2655 ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) {
2656 index = 0;
2657 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2658 "Illegal channel!!\n");
2659 }
2660
2661 in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index);
2662 if (in_24g) {
2663 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2664 txpower = rtlefuse->txpwrlevel_cck[path][index];
2665 else if (DESC_RATE6M <= rate)
2666 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
2667 else
2668 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "invalid rate\n");
2669
2670 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2671 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2672 txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S];
2673
2674 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2675 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2676 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2677 txpower += rtlefuse->txpwr_ht20diff[path][TX_1S];
2678 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2679 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2680 txpower += rtlefuse->txpwr_ht20diff[path][TX_2S];
2681 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2682 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2683 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2684 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2685 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2686 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2687 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2688 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2689 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2690 (DESC_RATEVHT1SS_MCS0 <= rate &&
2691 rate <= DESC_RATEVHT2SS_MCS9))
2692 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2693 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2694 (DESC_RATEVHT2SS_MCS0 <= rate &&
2695 rate <= DESC_RATEVHT2SS_MCS9))
2696 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2697 }
2698 } else {
2699 if (DESC_RATE6M <= rate)
2700 txpower = rtlefuse->txpwr_5g_bw40base[path][index];
2701 else
2702 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_WARNING,
2703 "INVALID Rate.\n");
2704
2705 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2706 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2707 txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S];
2708
2709 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2710 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2711 (DESC_RATEVHT1SS_MCS0 <= rate &&
2712 rate <= DESC_RATEVHT2SS_MCS9))
2713 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S];
2714 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2715 (DESC_RATEVHT2SS_MCS0 <= rate &&
2716 rate <= DESC_RATEVHT2SS_MCS9))
2717 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S];
2718 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2719 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2720 (DESC_RATEVHT1SS_MCS0 <= rate &&
2721 rate <= DESC_RATEVHT2SS_MCS9))
2722 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S];
2723 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2724 (DESC_RATEVHT2SS_MCS0 <= rate &&
2725 rate <= DESC_RATEVHT2SS_MCS9))
2726 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S];
2727 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2728 u8 channel_5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2729 42, 58, 106, 122, 138, 155, 171
2730 };
2731 u8 i;
2732
2733 for (i = 0; i < sizeof(channel_5g_80m) / sizeof(u8); ++i)
2734 if (channel_5g_80m[i] == channel)
2735 index = i;
2736
2737 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2738 (DESC_RATEVHT1SS_MCS0 <= rate &&
2739 rate <= DESC_RATEVHT2SS_MCS9))
2740 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2741 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S];
2742 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2743 (DESC_RATEVHT2SS_MCS0 <= rate &&
2744 rate <= DESC_RATEVHT2SS_MCS9))
2745 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2746 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S]
2747 + rtlefuse->txpwr_5g_bw80diff[path][TX_2S];
2748 }
2749 }
2750 if (rtlefuse->eeprom_regulatory != 2)
2751 powerdiff_byrate =
2752 _rtl8821ae_phy_get_txpower_by_rate(hw, (u8)(!in_24g),
2753 path, rate);
2754
2755 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2756 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9)
2757 txpower -= powerdiff_byrate;
2758 else
2759 txpower += powerdiff_byrate;
2760
2761 if (rate > DESC_RATE11M)
2762 txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path];
2763 else
2764 txpower += rtlpriv->dm.remnant_cck_idx;
2765
2766 if (txpower > MAX_POWER_INDEX)
2767 txpower = MAX_POWER_INDEX;
2768
2769 return txpower;
2770}
2771
2772static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw,
2773 u8 power_index, u8 path, u8 rate)
2774{
2775 struct rtl_priv *rtlpriv = rtl_priv(hw);
2776
2777 if (path == RF90_PATH_A) {
2778 switch (rate) {
2779 case DESC_RATE1M:
2780 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2781 MASKBYTE0, power_index);
2782 break;
2783 case DESC_RATE2M:
2784 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2785 MASKBYTE1, power_index);
2786 break;
2787 case DESC_RATE5_5M:
2788 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2789 MASKBYTE2, power_index);
2790 break;
2791 case DESC_RATE11M:
2792 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2793 MASKBYTE3, power_index);
2794 break;
2795 case DESC_RATE6M:
2796 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2797 MASKBYTE0, power_index);
2798 break;
2799 case DESC_RATE9M:
2800 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2801 MASKBYTE1, power_index);
2802 break;
2803 case DESC_RATE12M:
2804 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2805 MASKBYTE2, power_index);
2806 break;
2807 case DESC_RATE18M:
2808 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2809 MASKBYTE3, power_index);
2810 break;
2811 case DESC_RATE24M:
2812 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2813 MASKBYTE0, power_index);
2814 break;
2815 case DESC_RATE36M:
2816 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2817 MASKBYTE1, power_index);
2818 break;
2819 case DESC_RATE48M:
2820 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2821 MASKBYTE2, power_index);
2822 break;
2823 case DESC_RATE54M:
2824 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2825 MASKBYTE3, power_index);
2826 break;
2827 case DESC_RATEMCS0:
2828 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2829 MASKBYTE0, power_index);
2830 break;
2831 case DESC_RATEMCS1:
2832 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2833 MASKBYTE1, power_index);
2834 break;
2835 case DESC_RATEMCS2:
2836 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2837 MASKBYTE2, power_index);
2838 break;
2839 case DESC_RATEMCS3:
2840 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2841 MASKBYTE3, power_index);
2842 break;
2843 case DESC_RATEMCS4:
2844 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2845 MASKBYTE0, power_index);
2846 break;
2847 case DESC_RATEMCS5:
2848 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2849 MASKBYTE1, power_index);
2850 break;
2851 case DESC_RATEMCS6:
2852 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2853 MASKBYTE2, power_index);
2854 break;
2855 case DESC_RATEMCS7:
2856 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2857 MASKBYTE3, power_index);
2858 break;
2859 case DESC_RATEMCS8:
2860 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2861 MASKBYTE0, power_index);
2862 break;
2863 case DESC_RATEMCS9:
2864 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2865 MASKBYTE1, power_index);
2866 break;
2867 case DESC_RATEMCS10:
2868 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2869 MASKBYTE2, power_index);
2870 break;
2871 case DESC_RATEMCS11:
2872 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2873 MASKBYTE3, power_index);
2874 break;
2875 case DESC_RATEMCS12:
2876 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2877 MASKBYTE0, power_index);
2878 break;
2879 case DESC_RATEMCS13:
2880 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2881 MASKBYTE1, power_index);
2882 break;
2883 case DESC_RATEMCS14:
2884 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2885 MASKBYTE2, power_index);
2886 break;
2887 case DESC_RATEMCS15:
2888 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2889 MASKBYTE3, power_index);
2890 break;
2891 case DESC_RATEVHT1SS_MCS0:
2892 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2893 MASKBYTE0, power_index);
2894 break;
2895 case DESC_RATEVHT1SS_MCS1:
2896 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2897 MASKBYTE1, power_index);
2898 break;
2899 case DESC_RATEVHT1SS_MCS2:
2900 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2901 MASKBYTE2, power_index);
2902 break;
2903 case DESC_RATEVHT1SS_MCS3:
2904 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2905 MASKBYTE3, power_index);
2906 break;
2907 case DESC_RATEVHT1SS_MCS4:
2908 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2909 MASKBYTE0, power_index);
2910 break;
2911 case DESC_RATEVHT1SS_MCS5:
2912 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2913 MASKBYTE1, power_index);
2914 break;
2915 case DESC_RATEVHT1SS_MCS6:
2916 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2917 MASKBYTE2, power_index);
2918 break;
2919 case DESC_RATEVHT1SS_MCS7:
2920 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2921 MASKBYTE3, power_index);
2922 break;
2923 case DESC_RATEVHT1SS_MCS8:
2924 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2925 MASKBYTE0, power_index);
2926 break;
2927 case DESC_RATEVHT1SS_MCS9:
2928 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2929 MASKBYTE1, power_index);
2930 break;
2931 case DESC_RATEVHT2SS_MCS0:
2932 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2933 MASKBYTE2, power_index);
2934 break;
2935 case DESC_RATEVHT2SS_MCS1:
2936 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2937 MASKBYTE3, power_index);
2938 break;
2939 case DESC_RATEVHT2SS_MCS2:
2940 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2941 MASKBYTE0, power_index);
2942 break;
2943 case DESC_RATEVHT2SS_MCS3:
2944 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2945 MASKBYTE1, power_index);
2946 break;
2947 case DESC_RATEVHT2SS_MCS4:
2948 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2949 MASKBYTE2, power_index);
2950 break;
2951 case DESC_RATEVHT2SS_MCS5:
2952 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2953 MASKBYTE3, power_index);
2954 break;
2955 case DESC_RATEVHT2SS_MCS6:
2956 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2957 MASKBYTE0, power_index);
2958 break;
2959 case DESC_RATEVHT2SS_MCS7:
2960 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2961 MASKBYTE1, power_index);
2962 break;
2963 case DESC_RATEVHT2SS_MCS8:
2964 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2965 MASKBYTE2, power_index);
2966 break;
2967 case DESC_RATEVHT2SS_MCS9:
2968 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2969 MASKBYTE3, power_index);
2970 break;
2971 default:
2972 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2973 "Invalid Rate!!\n");
2974 break;
2975 }
2976 } else if (path == RF90_PATH_B) {
2977 switch (rate) {
2978 case DESC_RATE1M:
2979 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2980 MASKBYTE0, power_index);
2981 break;
2982 case DESC_RATE2M:
2983 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2984 MASKBYTE1, power_index);
2985 break;
2986 case DESC_RATE5_5M:
2987 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2988 MASKBYTE2, power_index);
2989 break;
2990 case DESC_RATE11M:
2991 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2992 MASKBYTE3, power_index);
2993 break;
2994 case DESC_RATE6M:
2995 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2996 MASKBYTE0, power_index);
2997 break;
2998 case DESC_RATE9M:
2999 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
3000 MASKBYTE1, power_index);
3001 break;
3002 case DESC_RATE12M:
3003 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
3004 MASKBYTE2, power_index);
3005 break;
3006 case DESC_RATE18M:
3007 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
3008 MASKBYTE3, power_index);
3009 break;
3010 case DESC_RATE24M:
3011 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
3012 MASKBYTE0, power_index);
3013 break;
3014 case DESC_RATE36M:
3015 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
3016 MASKBYTE1, power_index);
3017 break;
3018 case DESC_RATE48M:
3019 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
3020 MASKBYTE2, power_index);
3021 break;
3022 case DESC_RATE54M:
3023 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
3024 MASKBYTE3, power_index);
3025 break;
3026 case DESC_RATEMCS0:
3027 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3028 MASKBYTE0, power_index);
3029 break;
3030 case DESC_RATEMCS1:
3031 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3032 MASKBYTE1, power_index);
3033 break;
3034 case DESC_RATEMCS2:
3035 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3036 MASKBYTE2, power_index);
3037 break;
3038 case DESC_RATEMCS3:
3039 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3040 MASKBYTE3, power_index);
3041 break;
3042 case DESC_RATEMCS4:
3043 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3044 MASKBYTE0, power_index);
3045 break;
3046 case DESC_RATEMCS5:
3047 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3048 MASKBYTE1, power_index);
3049 break;
3050 case DESC_RATEMCS6:
3051 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3052 MASKBYTE2, power_index);
3053 break;
3054 case DESC_RATEMCS7:
3055 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3056 MASKBYTE3, power_index);
3057 break;
3058 case DESC_RATEMCS8:
3059 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3060 MASKBYTE0, power_index);
3061 break;
3062 case DESC_RATEMCS9:
3063 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3064 MASKBYTE1, power_index);
3065 break;
3066 case DESC_RATEMCS10:
3067 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3068 MASKBYTE2, power_index);
3069 break;
3070 case DESC_RATEMCS11:
3071 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3072 MASKBYTE3, power_index);
3073 break;
3074 case DESC_RATEMCS12:
3075 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3076 MASKBYTE0, power_index);
3077 break;
3078 case DESC_RATEMCS13:
3079 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3080 MASKBYTE1, power_index);
3081 break;
3082 case DESC_RATEMCS14:
3083 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3084 MASKBYTE2, power_index);
3085 break;
3086 case DESC_RATEMCS15:
3087 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3088 MASKBYTE3, power_index);
3089 break;
3090 case DESC_RATEVHT1SS_MCS0:
3091 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3092 MASKBYTE0, power_index);
3093 break;
3094 case DESC_RATEVHT1SS_MCS1:
3095 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3096 MASKBYTE1, power_index);
3097 break;
3098 case DESC_RATEVHT1SS_MCS2:
3099 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3100 MASKBYTE2, power_index);
3101 break;
3102 case DESC_RATEVHT1SS_MCS3:
3103 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3104 MASKBYTE3, power_index);
3105 break;
3106 case DESC_RATEVHT1SS_MCS4:
3107 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3108 MASKBYTE0, power_index);
3109 break;
3110 case DESC_RATEVHT1SS_MCS5:
3111 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3112 MASKBYTE1, power_index);
3113 break;
3114 case DESC_RATEVHT1SS_MCS6:
3115 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3116 MASKBYTE2, power_index);
3117 break;
3118 case DESC_RATEVHT1SS_MCS7:
3119 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3120 MASKBYTE3, power_index);
3121 break;
3122 case DESC_RATEVHT1SS_MCS8:
3123 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3124 MASKBYTE0, power_index);
3125 break;
3126 case DESC_RATEVHT1SS_MCS9:
3127 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3128 MASKBYTE1, power_index);
3129 break;
3130 case DESC_RATEVHT2SS_MCS0:
3131 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3132 MASKBYTE2, power_index);
3133 break;
3134 case DESC_RATEVHT2SS_MCS1:
3135 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3136 MASKBYTE3, power_index);
3137 break;
3138 case DESC_RATEVHT2SS_MCS2:
3139 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3140 MASKBYTE0, power_index);
3141 break;
3142 case DESC_RATEVHT2SS_MCS3:
3143 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3144 MASKBYTE1, power_index);
3145 break;
3146 case DESC_RATEVHT2SS_MCS4:
3147 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3148 MASKBYTE2, power_index);
3149 break;
3150 case DESC_RATEVHT2SS_MCS5:
3151 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3152 MASKBYTE3, power_index);
3153 break;
3154 case DESC_RATEVHT2SS_MCS6:
3155 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3156 MASKBYTE0, power_index);
3157 break;
3158 case DESC_RATEVHT2SS_MCS7:
3159 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3160 MASKBYTE1, power_index);
3161 break;
3162 case DESC_RATEVHT2SS_MCS8:
3163 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3164 MASKBYTE2, power_index);
3165 break;
3166 case DESC_RATEVHT2SS_MCS9:
3167 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3168 MASKBYTE3, power_index);
3169 break;
3170 default:
3171 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3172 "Invalid Rate!!\n");
3173 break;
3174 }
3175 } else {
3176 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3177 "Invalid RFPath!!\n");
3178 }
3179}
3180
3181static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3182 u8 *array, u8 path,
3183 u8 channel, u8 size)
3184{
3185 struct rtl_priv *rtlpriv = rtl_priv(hw);
3186 struct rtl_phy *rtlphy = &rtlpriv->phy;
3187 u8 i;
3188 u8 power_index;
3189
3190 for (i = 0; i < size; i++) {
3191 power_index =
3192 _rtl8821ae_get_txpower_index(hw, path, array[i],
3193 rtlphy->current_chan_bw,
3194 channel);
3195 _rtl8821ae_phy_set_txpower_index(hw, power_index, path,
3196 array[i]);
3197 }
3198}
3199
3200static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw,
3201 u8 bw, u8 channel, u8 path)
3202{
3203 struct rtl_priv *rtlpriv = rtl_priv(hw);
3204 struct rtl_phy *rtlphy = &rtlpriv->phy;
3205
3206 u8 i;
3207 u32 power_level, data, offset;
3208
3209 if (path >= rtlphy->num_total_rfpath)
3210 return;
3211
3212 data = 0;
3213 if (path == RF90_PATH_A) {
3214 power_level =
3215 _rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
3216 DESC_RATEMCS7, bw, channel);
3217 offset = RA_TXPWRTRAING;
3218 } else {
3219 power_level =
3220 _rtl8821ae_get_txpower_index(hw, RF90_PATH_B,
3221 DESC_RATEMCS7, bw, channel);
3222 offset = RB_TXPWRTRAING;
3223 }
3224
3225 for (i = 0; i < 3; i++) {
3226 if (i == 0)
3227 power_level = power_level - 10;
3228 else if (i == 1)
3229 power_level = power_level - 8;
3230 else
3231 power_level = power_level - 6;
3232
3233 data |= (((power_level > 2) ? (power_level) : 2) << (i * 8));
3234 }
3235 rtl_set_bbreg(hw, offset, 0xffffff, data);
3236}
3237
3238void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3239 u8 channel, u8 path)
3240{
3241 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
3242 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3243 struct rtl_priv *rtlpriv = rtl_priv(hw);
3244 struct rtl_phy *rtlphy = &rtlpriv->phy;
3245 u8 cck_rates[] = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M,
3246 DESC_RATE11M};
3247 u8 sizes_of_cck_retes = 4;
3248 u8 ofdm_rates[] = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
3249 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
3250 DESC_RATE48M, DESC_RATE54M};
3251 u8 sizes_of_ofdm_retes = 8;
3252 u8 ht_rates_1t[] = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
3253 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
3254 DESC_RATEMCS6, DESC_RATEMCS7};
3255 u8 sizes_of_ht_retes_1t = 8;
3256 u8 ht_rates_2t[] = {DESC_RATEMCS8, DESC_RATEMCS9,
3257 DESC_RATEMCS10, DESC_RATEMCS11,
3258 DESC_RATEMCS12, DESC_RATEMCS13,
3259 DESC_RATEMCS14, DESC_RATEMCS15};
3260 u8 sizes_of_ht_retes_2t = 8;
3261 u8 vht_rates_1t[] = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
3262 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
3263 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
3264 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
3265 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
3266 u8 vht_rates_2t[] = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
3267 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
3268 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
3269 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
3270 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
3271 u8 sizes_of_vht_retes = 10;
3272
3273 if (rtlhal->current_bandtype == BAND_ON_2_4G)
3274 _rtl8821ae_phy_set_txpower_level_by_path(hw, cck_rates, path, channel,
3275 sizes_of_cck_retes);
3276
3277 _rtl8821ae_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel,
3278 sizes_of_ofdm_retes);
3279 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel,
3280 sizes_of_ht_retes_1t);
3281 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_1t, path, channel,
3282 sizes_of_vht_retes);
3283
3284 if (rtlphy->num_total_rfpath >= 2) {
3285 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_2t, path,
3286 channel,
3287 sizes_of_ht_retes_2t);
3288 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_2t, path,
3289 channel,
3290 sizes_of_vht_retes);
3291 }
3292
3293 _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw,
3294 channel, path);
3295}
3296
3297/*just in case, write txpower in DW, to reduce time*/
3298void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
3299{
3300 struct rtl_priv *rtlpriv = rtl_priv(hw);
3301 struct rtl_phy *rtlphy = &rtlpriv->phy;
3302 u8 path = 0;
3303
3304 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path)
3305 rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path);
3306}
3307
3308static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
3309 enum wireless_mode wirelessmode,
3310 u8 txpwridx)
3311{
3312 long offset;
3313 long pwrout_dbm;
3314
3315 switch (wirelessmode) {
3316 case WIRELESS_MODE_B:
3317 offset = -7;
3318 break;
3319 case WIRELESS_MODE_G:
3320 case WIRELESS_MODE_N_24G:
3321 offset = -8;
3322 break;
3323 default:
3324 offset = -8;
3325 break;
3326 }
3327 pwrout_dbm = txpwridx / 2 + offset;
3328 return pwrout_dbm;
3329}
3330
3331void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
3332{
3333 struct rtl_priv *rtlpriv = rtl_priv(hw);
3334 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3335 enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3336
3337 if (!is_hal_stop(rtlhal)) {
3338 switch (operation) {
3339 case SCAN_OPT_BACKUP_BAND0:
3340 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3341 rtlpriv->cfg->ops->set_hw_reg(hw,
3342 HW_VAR_IO_CMD,
3343 (u8 *)&iotype);
3344
3345 break;
3346 case SCAN_OPT_BACKUP_BAND1:
3347 iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN;
3348 rtlpriv->cfg->ops->set_hw_reg(hw,
3349 HW_VAR_IO_CMD,
3350 (u8 *)&iotype);
3351
3352 break;
3353 case SCAN_OPT_RESTORE:
3354 iotype = IO_CMD_RESUME_DM_BY_SCAN;
3355 rtlpriv->cfg->ops->set_hw_reg(hw,
3356 HW_VAR_IO_CMD,
3357 (u8 *)&iotype);
3358 break;
3359 default:
3360 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3361 "Unknown Scan Backup operation.\n");
3362 break;
3363 }
3364 }
3365}
3366
3367static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv *rtlpriv, u8 bw)
3368{
3369 u16 reg_rf_mode_bw, tmp = 0;
3370
3371 reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL);
3372 switch (bw) {
3373 case HT_CHANNEL_WIDTH_20:
3374 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F);
3375 break;
3376 case HT_CHANNEL_WIDTH_20_40:
3377 tmp = reg_rf_mode_bw | BIT(7);
3378 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF);
3379 break;
3380 case HT_CHANNEL_WIDTH_80:
3381 tmp = reg_rf_mode_bw | BIT(8);
3382 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F);
3383 break;
3384 default:
3385 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "unknown Bandwidth: 0x%x\n", bw);
3386 break;
3387 }
3388}
3389
3390static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv *rtlpriv)
3391{
3392 struct rtl_phy *rtlphy = &rtlpriv->phy;
3393 struct rtl_mac *mac = rtl_mac(rtlpriv);
3394 u8 sc_set_40 = 0, sc_set_20 = 0;
3395
3396 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3397 if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3398 sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
3399 else if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3400 sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
3401 else
3402 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3403 "SCMapping: Not Correct Primary40MHz Setting\n");
3404
3405 if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3406 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3407 sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
3408 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3409 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3410 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3411 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3412 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3413 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3414 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3415 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3416 sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
3417 else
3418 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3419 "SCMapping: Not Correct Primary40MHz Setting\n");
3420 } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
3421 if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3422 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3423 else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3424 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3425 else
3426 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3427 "SCMapping: Not Correct Primary40MHz Setting\n");
3428 }
3429 return (sc_set_40 << 4) | sc_set_20;
3430}
3431
3432void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
3433{
3434 struct rtl_priv *rtlpriv = rtl_priv(hw);
3435 struct rtl_phy *rtlphy = &rtlpriv->phy;
3436 u8 sub_chnl = 0;
3437 u8 l1pk_val = 0;
3438
3439 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
3440 "Switch to %s bandwidth\n",
3441 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
3442 "20MHz" :
3443 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ?
3444 "40MHz" : "80MHz")));
3445
3446 _rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw);
3447 sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv);
3448 rtl_write_byte(rtlpriv, 0x0483, sub_chnl);
3449
3450 switch (rtlphy->current_chan_bw) {
3451 case HT_CHANNEL_WIDTH_20:
3452 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200);
3453 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3454
3455 if (rtlphy->rf_type == RF_2T2R)
3456 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7);
3457 else
3458 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8);
3459 break;
3460 case HT_CHANNEL_WIDTH_20_40:
3461 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201);
3462 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3463 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3464 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3465
3466 if (rtlphy->reg_837 & BIT(2))
3467 l1pk_val = 6;
3468 else {
3469 if (rtlphy->rf_type == RF_2T2R)
3470 l1pk_val = 7;
3471 else
3472 l1pk_val = 8;
3473 }
3474 /* 0x848[25:22] = 0x6 */
3475 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3476
3477 if (sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ)
3478 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1);
3479 else
3480 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0);
3481 break;
3482
3483 case HT_CHANNEL_WIDTH_80:
3484 /* 0x8ac[21,20,9:6,1,0]=8'b11100010 */
3485 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202);
3486 /* 0x8c4[30] = 1 */
3487 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
3488 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3489 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3490
3491 if (rtlphy->reg_837 & BIT(2))
3492 l1pk_val = 5;
3493 else {
3494 if (rtlphy->rf_type == RF_2T2R)
3495 l1pk_val = 6;
3496 else
3497 l1pk_val = 7;
3498 }
3499 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3500
3501 break;
3502 default:
3503 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3504 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
3505 break;
3506 }
3507
3508 rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel);
3509
3510 rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
3511 rtlphy->set_bwmode_inprogress = false;
3512
3513 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
3514}
3515
3516void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
3517 enum nl80211_channel_type ch_type)
3518{
3519 struct rtl_priv *rtlpriv = rtl_priv(hw);
3520 struct rtl_phy *rtlphy = &rtlpriv->phy;
3521 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3522 u8 tmp_bw = rtlphy->current_chan_bw;
3523
3524 if (rtlphy->set_bwmode_inprogress)
3525 return;
3526 rtlphy->set_bwmode_inprogress = true;
3527 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
3528 rtl8821ae_phy_set_bw_mode_callback(hw);
3529 else {
3530 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3531 "FALSE driver sleep or unload\n");
3532 rtlphy->set_bwmode_inprogress = false;
3533 rtlphy->current_chan_bw = tmp_bw;
3534 }
3535}
3536
3537void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
3538{
3539 struct rtl_priv *rtlpriv = rtl_priv(hw);
3540 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3541 struct rtl_phy *rtlphy = &rtlpriv->phy;
3542 u8 channel = rtlphy->current_channel;
3543 u8 path;
3544 u32 data;
3545
3546 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
3547 "switch to channel%d\n", rtlphy->current_channel);
3548 if (is_hal_stop(rtlhal))
3549 return;
3550
3551 if (36 <= channel && channel <= 48)
3552 data = 0x494;
3553 else if (50 <= channel && channel <= 64)
3554 data = 0x453;
3555 else if (100 <= channel && channel <= 116)
3556 data = 0x452;
3557 else if (118 <= channel)
3558 data = 0x412;
3559 else
3560 data = 0x96a;
3561 rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data);
3562
3563 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++) {
3564 if (36 <= channel && channel <= 64)
3565 data = 0x101;
3566 else if (100 <= channel && channel <= 140)
3567 data = 0x301;
3568 else if (140 < channel)
3569 data = 0x501;
3570 else
3571 data = 0x000;
3572 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3573 BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data);
3574
3575 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3576 BMASKBYTE0, channel);
3577
3578 if (channel > 14) {
3579 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
3580 if (36 <= channel && channel <= 64)
3581 data = 0x114E9;
3582 else if (100 <= channel && channel <= 140)
3583 data = 0x110E9;
3584 else
3585 data = 0x110E9;
3586 rtl8821ae_phy_set_rf_reg(hw, path, RF_APK,
3587 BRFREGOFFSETMASK, data);
3588 }
3589 }
3590 }
3591 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3592}
3593
3594u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw)
3595{
3596 struct rtl_priv *rtlpriv = rtl_priv(hw);
3597 struct rtl_phy *rtlphy = &rtlpriv->phy;
3598 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3599 u32 timeout = 1000, timecount = 0;
3600 u8 channel = rtlphy->current_channel;
3601
3602 if (rtlphy->sw_chnl_inprogress)
3603 return 0;
3604 if (rtlphy->set_bwmode_inprogress)
3605 return 0;
3606
3607 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3608 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
3609 "sw_chnl_inprogress false driver sleep or unload\n");
3610 return 0;
3611 }
3612 while (rtlphy->lck_inprogress && timecount < timeout) {
3613 mdelay(50);
3614 timecount += 50;
3615 }
3616
3617 if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G)
3618 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G);
3619 else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G)
3620 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3621
3622 rtlphy->sw_chnl_inprogress = true;
3623 if (channel == 0)
3624 channel = 1;
3625
3626 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
3627 "switch to channel%d, band type is %d\n",
3628 rtlphy->current_channel, rtlhal->current_bandtype);
3629
3630 rtl8821ae_phy_sw_chnl_callback(hw);
3631
3632 rtl8821ae_dm_clear_txpower_tracking_state(hw);
3633 rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel);
3634
3635 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3636 rtlphy->sw_chnl_inprogress = false;
3637 return 1;
3638}
3639
3640u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl)
3641{
3642 u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] = {
3643 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3644 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
3645 56, 58, 60, 62, 64, 100, 102, 104, 106, 108,
3646 110, 112, 114, 116, 118, 120, 122, 124, 126,
3647 128, 130, 132, 134, 136, 138, 140, 149, 151,
3648 153, 155, 157, 159, 161, 163, 165};
3649 u8 place = chnl;
3650
3651 if (chnl > 14) {
3652 for (place = 14; place < sizeof(channel_all); place++)
3653 if (channel_all[place] == chnl)
3654 return place-13;
3655 }
3656
3657 return 0;
3658}
3659
3660#define MACBB_REG_NUM 10
3661#define AFE_REG_NUM 14
3662#define RF_REG_NUM 3
3663
3664static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw *hw,
3665 u32 *macbb_backup,
3666 u32 *backup_macbb_reg, u32 mac_bb_num)
3667{
3668 struct rtl_priv *rtlpriv = rtl_priv(hw);
3669 u32 i;
3670
3671 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3672 /*save MACBB default value*/
3673 for (i = 0; i < mac_bb_num; i++)
3674 macbb_backup[i] = rtl_read_dword(rtlpriv, backup_macbb_reg[i]);
3675
3676 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "BackupMacBB Success!!!!\n");
3677}
3678
3679static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw *hw, u32 *afe_backup,
3680 u32 *backup_afe_REG, u32 afe_num)
3681{
3682 struct rtl_priv *rtlpriv = rtl_priv(hw);
3683 u32 i;
3684
3685 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3686 /*Save AFE Parameters */
3687 for (i = 0; i < afe_num; i++)
3688 afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
3689 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "BackupAFE Success!!!!\n");
3690}
3691
3692static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw *hw, u32 *rfa_backup,
3693 u32 *rfb_backup, u32 *backup_rf_reg,
3694 u32 rf_num)
3695{
3696 struct rtl_priv *rtlpriv = rtl_priv(hw);
3697 u32 i;
3698
3699 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3700 /*Save RF Parameters*/
3701 for (i = 0; i < rf_num; i++) {
3702 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i],
3703 BMASKDWORD);
3704 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i],
3705 BMASKDWORD);
3706 }
3707 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "BackupRF Success!!!!\n");
3708}
3709
3710static void _rtl8821ae_iqk_configure_mac(
3711 struct ieee80211_hw *hw
3712 )
3713{
3714 struct rtl_priv *rtlpriv = rtl_priv(hw);
3715 /* ========MAC register setting========*/
3716 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3717 rtl_write_byte(rtlpriv, 0x522, 0x3f);
3718 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
3719 rtl_write_byte(rtlpriv, 0x808, 0x00); /*RX ante off*/
3720 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/
3721}
3722
3723static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw *hw,
3724 enum radio_path path, u32 tx_x, u32 tx_y)
3725{
3726 struct rtl_priv *rtlpriv = rtl_priv(hw);
3727 switch (path) {
3728 case RF90_PATH_A:
3729 /* [31] = 1 --> Page C1 */
3730 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1);
3731 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3732 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
3733 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
3734 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
3735 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
3736 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
3737 "TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3738 tx_x, tx_y);
3739 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
3740 "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
3741 rtl_get_bbreg(hw, 0xcd4, 0x000007ff),
3742 rtl_get_bbreg(hw, 0xccc, 0x000007ff));
3743 break;
3744 default:
3745 break;
3746 };
3747}
3748
3749static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw *hw,
3750 enum radio_path path, u32 rx_x, u32 rx_y)
3751{
3752 struct rtl_priv *rtlpriv = rtl_priv(hw);
3753 switch (path) {
3754 case RF90_PATH_A:
3755 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3756 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1);
3757 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1);
3758 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
3759 "rx_x = %x;;rx_y = %x ====>fill to IQC\n",
3760 rx_x>>1, rx_y>>1);
3761 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
3762 "0xc10 = %x ====>fill to IQC\n",
3763 rtl_read_dword(rtlpriv, 0xc10));
3764 break;
3765 default:
3766 break;
3767 };
3768}
3769
3770#define cal_num 10
3771
3772static void _rtl8821ae_iqk_tx(struct ieee80211_hw *hw, enum radio_path path)
3773{
3774 struct rtl_priv *rtlpriv = rtl_priv(hw);
3775 struct rtl_phy *rtlphy = &rtlpriv->phy;
3776 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3777
3778 u32 tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65;
3779 int tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0;
3780 int tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num],
3781 tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num];
3782 bool tx0iqkok = false, rx0iqkok = false;
3783 bool vdf_enable = false;
3784 int i, k, vdf_y[3], vdf_x[3], tx_dt[3], rx_dt[3],
3785 ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0;
3786
3787 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
3788 "BandWidth = %d.\n",
3789 rtlphy->current_chan_bw);
3790 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3791 vdf_enable = true;
3792
3793 while (cal < cal_num) {
3794 switch (path) {
3795 case RF90_PATH_A:
3796 temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff);
3797 /* Path-A LOK */
3798 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3799 /*========Path-A AFE all on========*/
3800 /*Port 0 DAC/ADC on*/
3801 rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
3802 rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
3803 rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
3804 rtl_write_dword(rtlpriv, 0xc6c, 0x19791979);
3805 rtl_write_dword(rtlpriv, 0xc70, 0x19791979);
3806 rtl_write_dword(rtlpriv, 0xc74, 0x19791979);
3807 rtl_write_dword(rtlpriv, 0xc78, 0x19791979);
3808 rtl_write_dword(rtlpriv, 0xc7c, 0x19791979);
3809 rtl_write_dword(rtlpriv, 0xc80, 0x19791979);
3810 rtl_write_dword(rtlpriv, 0xc84, 0x19791979);
3811
3812 rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
3813
3814 /* LOK Setting */
3815 /* ====== LOK ====== */
3816 /*DAC/ADC sampling rate (160 MHz)*/
3817 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3818
3819 /* 2. LoK RF Setting (at BW = 20M) */
3820 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002);
3821 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3); /* BW 20M */
3822 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3823 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3824 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3825 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3826 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3827 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
3828 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3829 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3830 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3831 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3832 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3833 rtl_write_dword(rtlpriv, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
3834
3835 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3836 rtl_write_dword(rtlpriv, 0xc88, 0x821403f4);
3837
3838 if (rtlhal->current_bandtype)
3839 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
3840 else
3841 rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
3842
3843 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3844 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3845 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3846 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3847 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3848
3849 mdelay(10); /* Delay 10ms */
3850 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3851
3852 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3853 rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); /* Load LOK */
3854
3855 switch (rtlphy->current_chan_bw) {
3856 case 1:
3857 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1);
3858 break;
3859 case 2:
3860 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0);
3861 break;
3862 default:
3863 break;
3864 }
3865
3866 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3867
3868 /* 3. TX RF Setting */
3869 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3870 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
3871 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3872 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3873 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3874 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3875 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3876 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
3877 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd); */
3878 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3879 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3880 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3881 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3882 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3883 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
3884
3885 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3886 rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
3887 if (rtlhal->current_bandtype)
3888 rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96);
3889 else
3890 rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96);
3891
3892 if (vdf_enable == 1) {
3893 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "VDF_enable\n");
3894 for (k = 0; k <= 2; k++) {
3895 switch (k) {
3896 case 0:
3897 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3898 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3899 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3900 break;
3901 case 1:
3902 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0);
3903 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0);
3904 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3905 break;
3906 case 2:
3907 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
3908 "vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff);
3909 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
3910 "vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff);
3911 tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
3912 tx_dt[cal] = ((16*tx_dt[cal])*10000/15708);
3913 tx_dt[cal] = (tx_dt[cal] >> 1)+(tx_dt[cal] & BIT(0));
3914 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3915 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3916 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);
3917 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
3918 break;
3919 default:
3920 break;
3921 }
3922 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3923 cal_retry = 0;
3924 while (1) {
3925 /* one shot */
3926 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3927 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3928
3929 mdelay(10); /* Delay 10ms */
3930 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3931 delay_count = 0;
3932 while (1) {
3933 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3934 if ((~iqk_ready) || (delay_count > 20))
3935 break;
3936 else{
3937 mdelay(1);
3938 delay_count++;
3939 }
3940 }
3941
3942 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
3943 /* ============TXIQK Check============== */
3944 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3945
3946 if (~tx_fail) {
3947 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3948 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3949 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3950 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3951 tx0iqkok = true;
3952 break;
3953 } else {
3954 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3955 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3956 tx0iqkok = false;
3957 cal_retry++;
3958 if (cal_retry == 10)
3959 break;
3960 }
3961 } else {
3962 tx0iqkok = false;
3963 cal_retry++;
3964 if (cal_retry == 10)
3965 break;
3966 }
3967 }
3968 }
3969 if (k == 3) {
3970 tx_x0[cal] = vdf_x[k-1];
3971 tx_y0[cal] = vdf_y[k-1];
3972 }
3973 } else {
3974 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3975 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3976 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3977 cal_retry = 0;
3978 while (1) {
3979 /* one shot */
3980 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3981 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3982
3983 mdelay(10); /* Delay 10ms */
3984 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3985 delay_count = 0;
3986 while (1) {
3987 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3988 if ((~iqk_ready) || (delay_count > 20))
3989 break;
3990 else{
3991 mdelay(1);
3992 delay_count++;
3993 }
3994 }
3995
3996 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
3997 /* ============TXIQK Check============== */
3998 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3999
4000 if (~tx_fail) {
4001 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4002 tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4003 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4004 tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4005 tx0iqkok = true;
4006 break;
4007 } else {
4008 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
4009 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
4010 tx0iqkok = false;
4011 cal_retry++;
4012 if (cal_retry == 10)
4013 break;
4014 }
4015 } else {
4016 tx0iqkok = false;
4017 cal_retry++;
4018 if (cal_retry == 10)
4019 break;
4020 }
4021 }
4022 }
4023
4024 if (tx0iqkok == false)
4025 break; /* TXK fail, Don't do RXK */
4026
4027 if (vdf_enable == 1) {
4028 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); /* TX VDF Disable */
4029 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "RXVDF Start\n");
4030 for (k = 0; k <= 2; k++) {
4031 /* ====== RX mode TXK (RXK Step 1) ====== */
4032 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4033 /* 1. TX RF Setting */
4034 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4035 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4036 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4037 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4038 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4039 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4040 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4041
4042 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
4043 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
4044 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
4045 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4046 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4047 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4048 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4049 switch (k) {
4050 case 0:
4051 {
4052 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4053 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4054 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4055 }
4056 break;
4057 case 1:
4058 {
4059 rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4060 rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4061 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4062 }
4063 break;
4064 case 2:
4065 {
4066 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4067 "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n",
4068 vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff);
4069 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4070 "VDF_X[1] = %x;;;VDF_X[0] = %x\n",
4071 vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff);
4072 rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4073 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "Rx_dt = %d\n", rx_dt[cal]);
4074 rx_dt[cal] = ((16*rx_dt[cal])*10000/13823);
4075 rx_dt[cal] = (rx_dt[cal] >> 1)+(rx_dt[cal] & BIT(0));
4076 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4077 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4078 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff);
4079 }
4080 break;
4081 default:
4082 break;
4083 }
4084 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4085 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4086 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4087 cal_retry = 0;
4088 while (1) {
4089 /* one shot */
4090 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4091 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4092
4093 mdelay(10); /* Delay 10ms */
4094 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4095 delay_count = 0;
4096 while (1) {
4097 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4098 if ((~iqk_ready) || (delay_count > 20))
4099 break;
4100 else{
4101 mdelay(1);
4102 delay_count++;
4103 }
4104 }
4105
4106 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4107 /* ============TXIQK Check============== */
4108 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4109
4110 if (~tx_fail) {
4111 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4112 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4113 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4114 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4115 tx0iqkok = true;
4116 break;
4117 } else{
4118 tx0iqkok = false;
4119 cal_retry++;
4120 if (cal_retry == 10)
4121 break;
4122 }
4123 } else {
4124 tx0iqkok = false;
4125 cal_retry++;
4126 if (cal_retry == 10)
4127 break;
4128 }
4129 }
4130
4131 if (tx0iqkok == false) { /* If RX mode TXK fail, then take TXK Result */
4132 tx_x0_rxk[cal] = tx_x0[cal];
4133 tx_y0_rxk[cal] = tx_y0[cal];
4134 tx0iqkok = true;
4135 RT_TRACE(rtlpriv,
4136 COMP_IQK,
4137 DBG_LOUD,
4138 "RXK Step 1 fail\n");
4139 }
4140
4141 /* ====== RX IQK ====== */
4142 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4143 /* 1. RX RF Setting */
4144 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4145 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4146 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4147 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4148 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4149 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4150 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4151
4152 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4153 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4154 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4155 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4156 rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe);
4157 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4158 rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4159
4160 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4161 rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1);
4162 rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0);
4163 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4164
4165 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */
4166
4167 if (k == 2)
4168 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); /* RX VDF Enable */
4169 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4170
4171 cal_retry = 0;
4172 while (1) {
4173 /* one shot */
4174 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4175 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4176
4177 mdelay(10); /* Delay 10ms */
4178 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4179 delay_count = 0;
4180 while (1) {
4181 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4182 if ((~iqk_ready) || (delay_count > 20))
4183 break;
4184 else{
4185 mdelay(1);
4186 delay_count++;
4187 }
4188 }
4189
4190 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4191 /* ============RXIQK Check============== */
4192 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4193 if (rx_fail == 0) {
4194 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4195 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4196 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4197 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4198 rx0iqkok = true;
4199 break;
4200 } else {
4201 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4202 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4203 rx0iqkok = false;
4204 cal_retry++;
4205 if (cal_retry == 10)
4206 break;
4207
4208 }
4209 } else{
4210 rx0iqkok = false;
4211 cal_retry++;
4212 if (cal_retry == 10)
4213 break;
4214 }
4215 }
4216
4217 }
4218 if (k == 3) {
4219 rx_x0[cal] = vdf_x[k-1];
4220 rx_y0[cal] = vdf_y[k-1];
4221 }
4222 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); /* TX VDF Enable */
4223 }
4224
4225 else{
4226 /* ====== RX mode TXK (RXK Step 1) ====== */
4227 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4228 /* 1. TX RF Setting */
4229 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4230 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4231 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4232 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4233 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4234 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4235 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4236 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4237 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4238 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4239
4240 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4241 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4242 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4243 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4244 /* ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); */
4245 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4246 cal_retry = 0;
4247 while (1) {
4248 /* one shot */
4249 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4250 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4251
4252 mdelay(10); /* Delay 10ms */
4253 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4254 delay_count = 0;
4255 while (1) {
4256 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4257 if ((~iqk_ready) || (delay_count > 20))
4258 break;
4259 else{
4260 mdelay(1);
4261 delay_count++;
4262 }
4263 }
4264
4265 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4266 /* ============TXIQK Check============== */
4267 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4268
4269 if (~tx_fail) {
4270 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4271 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4272 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4273 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4274 tx0iqkok = true;
4275 break;
4276 } else {
4277 tx0iqkok = false;
4278 cal_retry++;
4279 if (cal_retry == 10)
4280 break;
4281 }
4282 } else{
4283 tx0iqkok = false;
4284 cal_retry++;
4285 if (cal_retry == 10)
4286 break;
4287 }
4288 }
4289
4290 if (tx0iqkok == false) { /* If RX mode TXK fail, then take TXK Result */
4291 tx_x0_rxk[cal] = tx_x0[cal];
4292 tx_y0_rxk[cal] = tx_y0[cal];
4293 tx0iqkok = true;
4294 RT_TRACE(rtlpriv, COMP_IQK,
4295 DBG_LOUD, "1");
4296 }
4297
4298 /* ====== RX IQK ====== */
4299 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4300 /* 1. RX RF Setting */
4301 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4302 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4303 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4304 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4305 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4306 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4307 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4308
4309 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4310 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4311 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4312 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4313 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe); */
4314 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4315 rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4316
4317 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4318 rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4319 rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4320 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4321
4322 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/
4323
4324 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4325
4326 cal_retry = 0;
4327 while (1) {
4328 /* one shot */
4329 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4330 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4331
4332 mdelay(10); /* Delay 10ms */
4333 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4334 delay_count = 0;
4335 while (1) {
4336 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4337 if ((~iqk_ready) || (delay_count > 20))
4338 break;
4339 else{
4340 mdelay(1);
4341 delay_count++;
4342 }
4343 }
4344
4345 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4346 /* ============RXIQK Check============== */
4347 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4348 if (rx_fail == 0) {
4349 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4350 rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4351 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4352 rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4353 rx0iqkok = true;
4354 break;
4355 } else{
4356 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4357 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4358 rx0iqkok = false;
4359 cal_retry++;
4360 if (cal_retry == 10)
4361 break;
4362
4363 }
4364 } else{
4365 rx0iqkok = false;
4366 cal_retry++;
4367 if (cal_retry == 10)
4368 break;
4369 }
4370 }
4371 }
4372
4373 if (tx0iqkok)
4374 tx_average++;
4375 if (rx0iqkok)
4376 rx_average++;
4377 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4378 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4379 break;
4380 default:
4381 break;
4382 }
4383 cal++;
4384 }
4385
4386 /* FillIQK Result */
4387 switch (path) {
4388 case RF90_PATH_A:
4389 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4390 "========Path_A =======\n");
4391 if (tx_average == 0)
4392 break;
4393
4394 for (i = 0; i < tx_average; i++) {
4395 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4396 "TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i,
4397 (tx_x0_rxk[i])>>21&0x000007ff, i,
4398 (tx_y0_rxk[i])>>21&0x000007ff);
4399 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4400 "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i,
4401 (tx_x0[i])>>21&0x000007ff, i,
4402 (tx_y0[i])>>21&0x000007ff);
4403 }
4404 for (i = 0; i < tx_average; i++) {
4405 for (ii = i+1; ii < tx_average; ii++) {
4406 dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21);
4407 if (dx < 3 && dx > -3) {
4408 dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
4409 if (dy < 3 && dy > -3) {
4410 tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2;
4411 tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2;
4412 tx_finish = 1;
4413 break;
4414 }
4415 }
4416 }
4417 if (tx_finish == 1)
4418 break;
4419 }
4420
4421 if (tx_finish == 1)
4422 _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); /* ? */
4423 else
4424 _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0);
4425
4426 if (rx_average == 0)
4427 break;
4428
4429 for (i = 0; i < rx_average; i++)
4430 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4431 "RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i,
4432 (rx_x0[i])>>21&0x000007ff, i,
4433 (rx_y0[i])>>21&0x000007ff);
4434 for (i = 0; i < rx_average; i++) {
4435 for (ii = i+1; ii < rx_average; ii++) {
4436 dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21);
4437 if (dx < 4 && dx > -4) {
4438 dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21);
4439 if (dy < 4 && dy > -4) {
4440 rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2;
4441 rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2;
4442 rx_finish = 1;
4443 break;
4444 }
4445 }
4446 }
4447 if (rx_finish == 1)
4448 break;
4449 }
4450
4451 if (rx_finish == 1)
4452 _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y);
4453 else
4454 _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0);
4455 break;
4456 default:
4457 break;
4458 }
4459}
4460
4461static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw *hw,
4462 enum radio_path path,
4463 u32 *backup_rf_reg,
4464 u32 *rf_backup, u32 rf_reg_num)
4465{
4466 struct rtl_priv *rtlpriv = rtl_priv(hw);
4467 u32 i;
4468
4469 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4470 for (i = 0; i < RF_REG_NUM; i++)
4471 rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK,
4472 rf_backup[i]);
4473
4474 switch (path) {
4475 case RF90_PATH_A:
4476 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4477 "RestoreRF Path A Success!!!!\n");
4478 break;
4479 default:
4480 break;
4481 }
4482}
4483
4484static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw *hw,
4485 u32 *afe_backup, u32 *backup_afe_reg,
4486 u32 afe_num)
4487{
4488 u32 i;
4489 struct rtl_priv *rtlpriv = rtl_priv(hw);
4490
4491 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4492 /* Reload AFE Parameters */
4493 for (i = 0; i < afe_num; i++)
4494 rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
4495 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4496 rtl_write_dword(rtlpriv, 0xc80, 0x0);
4497 rtl_write_dword(rtlpriv, 0xc84, 0x0);
4498 rtl_write_dword(rtlpriv, 0xc88, 0x0);
4499 rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
4500 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4501 rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4502 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4503 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4504 rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4505 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreAFE Success!!!!\n");
4506}
4507
4508static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw *hw,
4509 u32 *macbb_backup,
4510 u32 *backup_macbb_reg,
4511 u32 macbb_num)
4512{
4513 u32 i;
4514 struct rtl_priv *rtlpriv = rtl_priv(hw);
4515
4516 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4517 /* Reload MacBB Parameters */
4518 for (i = 0; i < macbb_num; i++)
4519 rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);
4520 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreMacBB Success!!!!\n");
4521}
4522
4523#undef MACBB_REG_NUM
4524#undef AFE_REG_NUM
4525#undef RF_REG_NUM
4526
4527#define MACBB_REG_NUM 11
4528#define AFE_REG_NUM 12
4529#define RF_REG_NUM 3
4530
4531static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw)
4532{
4533 u32 macbb_backup[MACBB_REG_NUM];
4534 u32 afe_backup[AFE_REG_NUM];
4535 u32 rfa_backup[RF_REG_NUM];
4536 u32 rfb_backup[RF_REG_NUM];
4537 u32 backup_macbb_reg[MACBB_REG_NUM] = {
4538 0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50,
4539 0xe00, 0xe50, 0x838, 0x82c
4540 };
4541 u32 backup_afe_reg[AFE_REG_NUM] = {
4542 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
4543 0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8
4544 };
4545 u32 backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
4546
4547 _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg,
4548 MACBB_REG_NUM);
4549 _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4550 _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg,
4551 RF_REG_NUM);
4552
4553 _rtl8821ae_iqk_configure_mac(hw);
4554 _rtl8821ae_iqk_tx(hw, RF90_PATH_A);
4555 _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup,
4556 RF_REG_NUM);
4557
4558 _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4559 _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg,
4560 MACBB_REG_NUM);
4561}
4562
4563static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main)
4564{
4565 struct rtl_priv *rtlpriv = rtl_priv(hw);
4566 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */
4567 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
4568 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
4569
4570 if (main)
4571 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1);
4572 else
4573 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2);
4574}
4575
4576#undef IQK_ADDA_REG_NUM
4577#undef IQK_DELAY_TIME
4578
4579void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4580{
4581}
4582
4583void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4584 u8 thermal_value, u8 threshold)
4585{
4586 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
4587
4588 rtldm->thermalvalue_iqk = thermal_value;
4589 rtl8812ae_phy_iq_calibrate(hw, false);
4590}
4591
4592void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4593{
4594 struct rtl_priv *rtlpriv = rtl_priv(hw);
4595 struct rtl_phy *rtlphy = &rtlpriv->phy;
4596
4597 if (!rtlphy->lck_inprogress) {
4598 spin_lock(&rtlpriv->locks.iqk_lock);
4599 rtlphy->lck_inprogress = true;
4600 spin_unlock(&rtlpriv->locks.iqk_lock);
4601
4602 _rtl8821ae_phy_iq_calibrate(hw);
4603
4604 spin_lock(&rtlpriv->locks.iqk_lock);
4605 rtlphy->lck_inprogress = false;
4606 spin_unlock(&rtlpriv->locks.iqk_lock);
4607 }
4608}
4609
4610void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw)
4611{
4612 struct rtl_priv *rtlpriv = rtl_priv(hw);
4613 struct rtl_phy *rtlphy = &rtlpriv->phy;
4614 u8 i;
4615
4616 RT_TRACE(rtlpriv, COMP_IQK, DBG_LOUD,
4617 "rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
4618 (int)(sizeof(rtlphy->iqk_matrix) /
4619 sizeof(struct iqk_matrix_regs)),
4620 IQK_MATRIX_SETTINGS_NUM);
4621
4622 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
4623 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
4624 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
4625 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
4626 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
4627
4628 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
4629 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
4630 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
4631 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
4632
4633 rtlphy->iqk_matrix[i].iqk_done = false;
4634 }
4635}
4636
4637void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4638 u8 thermal_value, u8 threshold)
4639{
4640 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
4641
4642 rtl8821ae_reset_iqk_result(hw);
4643
4644 rtldm->thermalvalue_iqk = thermal_value;
4645 rtl8821ae_phy_iq_calibrate(hw, false);
4646}
4647
4648void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw)
4649{
4650}
4651
4652void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
4653{
4654}
4655
4656void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
4657{
4658 _rtl8821ae_phy_set_rfpath_switch(hw, bmain);
4659}
4660
4661bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
4662{
4663 struct rtl_priv *rtlpriv = rtl_priv(hw);
4664 struct rtl_phy *rtlphy = &rtlpriv->phy;
4665 bool postprocessing = false;
4666
4667 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
4668 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
4669 iotype, rtlphy->set_io_inprogress);
4670 do {
4671 switch (iotype) {
4672 case IO_CMD_RESUME_DM_BY_SCAN:
4673 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
4674 "[IO CMD] Resume DM after scan.\n");
4675 postprocessing = true;
4676 break;
4677 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4678 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4679 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
4680 "[IO CMD] Pause DM before scan.\n");
4681 postprocessing = true;
4682 break;
4683 default:
4684 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
4685 "switch case not process\n");
4686 break;
4687 }
4688 } while (false);
4689 if (postprocessing && !rtlphy->set_io_inprogress) {
4690 rtlphy->set_io_inprogress = true;
4691 rtlphy->current_io_type = iotype;
4692 } else {
4693 return false;
4694 }
4695 rtl8821ae_phy_set_io(hw);
4696 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
4697 return true;
4698}
4699
4700static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw)
4701{
4702 struct rtl_priv *rtlpriv = rtl_priv(hw);
4703 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
4704 struct rtl_phy *rtlphy = &rtlpriv->phy;
4705
4706 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
4707 "--->Cmd(%#x), set_io_inprogress(%d)\n",
4708 rtlphy->current_io_type, rtlphy->set_io_inprogress);
4709 switch (rtlphy->current_io_type) {
4710 case IO_CMD_RESUME_DM_BY_SCAN:
4711 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4712 _rtl8821ae_resume_tx_beacon(hw);
4713 rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
4714 rtl8821ae_dm_write_cck_cca_thres(hw,
4715 rtlphy->initgain_backup.cca);
4716 break;
4717 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4718 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4719 _rtl8821ae_stop_tx_beacon(hw);
4720 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
4721 rtl8821ae_dm_write_dig(hw, 0x17);
4722 rtlphy->initgain_backup.cca = dm_digtable->cur_cck_cca_thres;
4723 rtl8821ae_dm_write_cck_cca_thres(hw, 0x40);
4724 break;
4725 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4726 break;
4727 default:
4728 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
4729 "switch case not process\n");
4730 break;
4731 }
4732 rtlphy->set_io_inprogress = false;
4733 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
4734 "(%#x)\n", rtlphy->current_io_type);
4735}
4736
4737static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw)
4738{
4739 struct rtl_priv *rtlpriv = rtl_priv(hw);
4740
4741 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
4742 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4743 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
4744 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4745 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
4746}
4747
4748static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4749 enum rf_pwrstate rfpwr_state)
4750{
4751 struct rtl_priv *rtlpriv = rtl_priv(hw);
4752 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
4753 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
4754 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4755 bool bresult = true;
4756 u8 i, queue_id;
4757 struct rtl8192_tx_ring *ring = NULL;
4758
4759 switch (rfpwr_state) {
4760 case ERFON:
4761 if ((ppsc->rfpwr_state == ERFOFF) &&
4762 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
4763 bool rtstatus = false;
4764 u32 initializecount = 0;
4765
4766 do {
4767 initializecount++;
4768 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
4769 "IPS Set eRf nic enable\n");
4770 rtstatus = rtl_ps_enable_nic(hw);
4771 } while (!rtstatus && (initializecount < 10));
4772 RT_CLEAR_PS_LEVEL(ppsc,
4773 RT_RF_OFF_LEVL_HALT_NIC);
4774 } else {
4775 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
4776 "Set ERFON sleeped:%d ms\n",
4777 jiffies_to_msecs(jiffies -
4778 ppsc->
4779 last_sleep_jiffies));
4780 ppsc->last_awake_jiffies = jiffies;
4781 rtl8821ae_phy_set_rf_on(hw);
4782 }
4783 if (mac->link_state == MAC80211_LINKED) {
4784 rtlpriv->cfg->ops->led_control(hw,
4785 LED_CTL_LINK);
4786 } else {
4787 rtlpriv->cfg->ops->led_control(hw,
4788 LED_CTL_NO_LINK);
4789 }
4790 break;
4791 case ERFOFF:
4792 for (queue_id = 0, i = 0;
4793 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
4794 ring = &pcipriv->dev.tx_ring[queue_id];
4795 if (queue_id == BEACON_QUEUE ||
4796 skb_queue_len(&ring->queue) == 0) {
4797 queue_id++;
4798 continue;
4799 } else {
4800 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
4801 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
4802 (i + 1), queue_id,
4803 skb_queue_len(&ring->queue));
4804
4805 udelay(10);
4806 i++;
4807 }
4808 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
4809 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
4810 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
4811 MAX_DOZE_WAITING_TIMES_9x,
4812 queue_id,
4813 skb_queue_len(&ring->queue));
4814 break;
4815 }
4816 }
4817
4818 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
4819 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
4820 "IPS Set eRf nic disable\n");
4821 rtl_ps_disable_nic(hw);
4822 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
4823 } else {
4824 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
4825 rtlpriv->cfg->ops->led_control(hw,
4826 LED_CTL_NO_LINK);
4827 } else {
4828 rtlpriv->cfg->ops->led_control(hw,
4829 LED_CTL_POWER_OFF);
4830 }
4831 }
4832 break;
4833 default:
4834 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
4835 "switch case not process\n");
4836 bresult = false;
4837 break;
4838 }
4839 if (bresult)
4840 ppsc->rfpwr_state = rfpwr_state;
4841 return bresult;
4842}
4843
4844bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4845 enum rf_pwrstate rfpwr_state)
4846{
4847 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4848
4849 bool bresult = false;
4850
4851 if (rfpwr_state == ppsc->rfpwr_state)
4852 return bresult;
4853 bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state);
4854 return bresult;
4855}
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/phy.h b/drivers/net/wireless/rtlwifi/rtl8821ae/phy.h
new file mode 100644
index 000000000000..c411f0a95cc4
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/phy.h
@@ -0,0 +1,259 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_PHY_H__
27#define __RTL8821AE_PHY_H__
28
29/* MAX_TX_COUNT must always be set to 4, otherwise read
30 * efuse table sequence will be wrong.
31 */
32#define MAX_TX_COUNT 4
33#define TX_1S 0
34#define TX_2S 1
35#define TX_3S 2
36#define TX_4S 3
37
38#define MAX_POWER_INDEX 0x3F
39
40#define MAX_PRECMD_CNT 16
41#define MAX_RFDEPENDCMD_CNT 16
42#define MAX_POSTCMD_CNT 16
43
44#define MAX_DOZE_WAITING_TIMES_9x 64
45
46#define RT_CANNOT_IO(hw) false
47#define HIGHPOWER_RADIOA_ARRAYLEN 22
48
49#define IQK_ADDA_REG_NUM 16
50#define IQK_BB_REG_NUM 9
51#define MAX_TOLERANCE 5
52#define IQK_DELAY_TIME 10
53#define index_mapping_NUM 15
54
55#define APK_BB_REG_NUM 5
56#define APK_AFE_REG_NUM 16
57#define APK_CURVE_REG_NUM 4
58#define PATH_NUM 2
59
60#define LOOP_LIMIT 5
61#define MAX_STALL_TIME 50
62#define AntennaDiversityValue 0x80
63#define MAX_TXPWR_IDX_NMODE_92S 63
64#define Reset_Cnt_Limit 3
65
66#define IQK_ADDA_REG_NUM 16
67#define IQK_MAC_REG_NUM 4
68
69#define RF6052_MAX_PATH 2
70
71#define CT_OFFSET_MAC_ADDR 0X16
72
73#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
74#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
75#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
76#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
77#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
78
79#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
80#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
81
82#define CT_OFFSET_CHANNEL_PLAH 0x75
83#define CT_OFFSET_THERMAL_METER 0x78
84#define CT_OFFSET_RF_OPTION 0x79
85#define CT_OFFSET_VERSION 0x7E
86#define CT_OFFSET_CUSTOMER_ID 0x7F
87
88#define RTL8821AE_MAX_PATH_NUM 2
89
90#define TARGET_CHNL_NUM_2G_5G_8812 59
91
92enum swchnlcmd_id {
93 CMDID_END,
94 CMDID_SET_TXPOWEROWER_LEVEL,
95 CMDID_BBREGWRITE10,
96 CMDID_WRITEPORT_ULONG,
97 CMDID_WRITEPORT_USHORT,
98 CMDID_WRITEPORT_UCHAR,
99 CMDID_RF_WRITEREG,
100};
101
102struct swchnlcmd {
103 enum swchnlcmd_id cmdid;
104 u32 para1;
105 u32 para2;
106 u32 msdelay;
107};
108
109enum hw90_block_e {
110 HW90_BLOCK_MAC = 0,
111 HW90_BLOCK_PHY0 = 1,
112 HW90_BLOCK_PHY1 = 2,
113 HW90_BLOCK_RF = 3,
114 HW90_BLOCK_MAXIMUM = 4,
115};
116
117enum baseband_config_type {
118 BASEBAND_CONFIG_PHY_REG = 0,
119 BASEBAND_CONFIG_AGC_TAB = 1,
120};
121
122enum ra_offset_area {
123 RA_OFFSET_LEGACY_OFDM1,
124 RA_OFFSET_LEGACY_OFDM2,
125 RA_OFFSET_HT_OFDM1,
126 RA_OFFSET_HT_OFDM2,
127 RA_OFFSET_HT_OFDM3,
128 RA_OFFSET_HT_OFDM4,
129 RA_OFFSET_HT_CCK,
130};
131
132enum antenna_path {
133 ANTENNA_NONE,
134 ANTENNA_D,
135 ANTENNA_C,
136 ANTENNA_CD,
137 ANTENNA_B,
138 ANTENNA_BD,
139 ANTENNA_BC,
140 ANTENNA_BCD,
141 ANTENNA_A,
142 ANTENNA_AD,
143 ANTENNA_AC,
144 ANTENNA_ACD,
145 ANTENNA_AB,
146 ANTENNA_ABD,
147 ANTENNA_ABC,
148 ANTENNA_ABCD
149};
150
151struct r_antenna_select_ofdm {
152 u32 r_tx_antenna:4;
153 u32 r_ant_l:4;
154 u32 r_ant_non_ht:4;
155 u32 r_ant_ht1:4;
156 u32 r_ant_ht2:4;
157 u32 r_ant_ht_s1:4;
158 u32 r_ant_non_ht_s1:4;
159 u32 ofdm_txsc:2;
160 u32 reserved:2;
161};
162
163struct r_antenna_select_cck {
164 u8 r_cckrx_enable_2:2;
165 u8 r_cckrx_enable:2;
166 u8 r_ccktx_enable:4;
167};
168
169struct efuse_contents {
170 u8 mac_addr[ETH_ALEN];
171 u8 cck_tx_power_idx[6];
172 u8 ht40_1s_tx_power_idx[6];
173 u8 ht40_2s_tx_power_idx_diff[3];
174 u8 ht20_tx_power_idx_diff[3];
175 u8 ofdm_tx_power_idx_diff[3];
176 u8 ht40_max_power_offset[3];
177 u8 ht20_max_power_offset[3];
178 u8 channel_plan;
179 u8 thermal_meter;
180 u8 rf_option[5];
181 u8 version;
182 u8 oem_id;
183 u8 regulatory;
184};
185
186struct tx_power_struct {
187 u8 cck[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
188 u8 ht40_1s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
189 u8 ht40_2s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
190 u8 ht20_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
191 u8 legacy_ht_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
192 u8 legacy_ht_txpowerdiff;
193 u8 groupht20[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
194 u8 groupht40[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
195 u8 pwrgroup_cnt;
196 u32 mcs_original_offset[4][16];
197};
198enum _ANT_DIV_TYPE {
199 NO_ANTDIV = 0xFF,
200 CG_TRX_HW_ANTDIV = 0x01,
201 CGCS_RX_HW_ANTDIV = 0x02,
202 FIXED_HW_ANTDIV = 0x03,
203 CG_TRX_SMART_ANTDIV = 0x04,
204 CGCS_RX_SW_ANTDIV = 0x05,
205
206};
207
208u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw,
209 u32 regaddr, u32 bitmask);
210void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
211 u32 regaddr, u32 bitmask, u32 data);
212u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
213 enum radio_path rfpath, u32 regaddr,
214 u32 bitmask);
215void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
216 enum radio_path rfpath, u32 regaddr,
217 u32 bitmask, u32 data);
218bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw);
219bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw);
220bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw);
221void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw,
222 u8 band);
223void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
224void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw,
225 long *powerlevel);
226void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw,
227 u8 channel);
228void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw,
229 u8 operation);
230void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
231void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
232 enum nl80211_channel_type ch_type);
233void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
234u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw);
235void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw,
236 bool b_recovery);
237void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw,
238 bool b_recovery);
239void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
240void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw);
241void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
242bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
243 enum radio_path rfpath);
244bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
245 enum radio_path rfpath);
246bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
247bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
248 enum rf_pwrstate rfpwr_state);
249u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl);
250void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
251 u8 channel, u8 path);
252void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
253 u8 thermal_value, u8 threshold);
254void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
255 u8 thermal_value, u8 threshold);
256void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw);
257u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band, u8 rf_path);
258
259#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.c b/drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.c
new file mode 100644
index 000000000000..9ddf78a187dd
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.c
@@ -0,0 +1,182 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../pwrseqcmd.h"
27#include "pwrseq.h"
28
29/* drivers should parse below arrays and do the corresponding actions */
30/* 3 Power on Array */
31struct wlan_pwr_cfg rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
32 RTL8812_TRANS_END_STEPS] = {
33 RTL8812_TRANS_CARDEMU_TO_ACT
34 RTL8812_TRANS_END
35};
36
37/* 3Radio off GPIO Array */
38struct wlan_pwr_cfg rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
39 RTL8812_TRANS_END_STEPS] = {
40 RTL8812_TRANS_ACT_TO_CARDEMU
41 RTL8812_TRANS_END
42};
43
44/* 3Card Disable Array */
45struct wlan_pwr_cfg rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
46 + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
47 + RTL8812_TRANS_END_STEPS] = {
48 RTL8812_TRANS_ACT_TO_CARDEMU
49 RTL8812_TRANS_CARDEMU_TO_CARDDIS
50 RTL8812_TRANS_END
51};
52
53/* 3 Card Enable Array */
54struct wlan_pwr_cfg rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
55 + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
56 + RTL8812_TRANS_END_STEPS] = {
57 RTL8812_TRANS_CARDDIS_TO_CARDEMU
58 RTL8812_TRANS_CARDEMU_TO_ACT
59 RTL8812_TRANS_END
60};
61
62/* 3Suspend Array */
63struct wlan_pwr_cfg rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
64 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
65 RTL8812_TRANS_END_STEPS] = {
66 RTL8812_TRANS_ACT_TO_CARDEMU
67 RTL8812_TRANS_CARDEMU_TO_SUS
68 RTL8812_TRANS_END
69};
70
71/* 3 Resume Array */
72struct wlan_pwr_cfg rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
73 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
74 RTL8812_TRANS_END_STEPS] = {
75 RTL8812_TRANS_SUS_TO_CARDEMU
76 RTL8812_TRANS_CARDEMU_TO_ACT
77 RTL8812_TRANS_END
78};
79
80/* 3HWPDN Array */
81struct wlan_pwr_cfg rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
82 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
83 RTL8812_TRANS_END_STEPS] = {
84 RTL8812_TRANS_ACT_TO_CARDEMU
85 RTL8812_TRANS_CARDEMU_TO_PDN
86 RTL8812_TRANS_END
87};
88
89/* 3 Enter LPS */
90struct wlan_pwr_cfg rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS +
91 RTL8812_TRANS_END_STEPS] = {
92 /* FW behavior */
93 RTL8812_TRANS_ACT_TO_LPS
94 RTL8812_TRANS_END
95};
96
97/* 3 Leave LPS */
98struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS +
99 RTL8812_TRANS_END_STEPS] = {
100 /* FW behavior */
101 RTL8812_TRANS_LPS_TO_ACT
102 RTL8812_TRANS_END
103};
104
105/* drivers should parse below arrays and do the corresponding actions */
106/*3 Power on Array*/
107struct wlan_pwr_cfg rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
108 + RTL8821A_TRANS_END_STEPS] = {
109 RTL8821A_TRANS_CARDEMU_TO_ACT
110 RTL8821A_TRANS_END
111};
112
113/*3Radio off GPIO Array */
114struct wlan_pwr_cfg rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
115 + RTL8821A_TRANS_END_STEPS] = {
116 RTL8821A_TRANS_ACT_TO_CARDEMU
117 RTL8821A_TRANS_END
118};
119
120/*3Card Disable Array*/
121struct wlan_pwr_cfg rtl8821A_card_disable_flow
122 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
123 + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
124 + RTL8821A_TRANS_END_STEPS] = {
125 RTL8821A_TRANS_ACT_TO_CARDEMU
126 RTL8821A_TRANS_CARDEMU_TO_CARDDIS
127 RTL8821A_TRANS_END
128};
129
130/*3 Card Enable Array*/
131/*RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS*/
132struct wlan_pwr_cfg rtl8821A_card_enable_flow
133 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
134 + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
135 + RTL8821A_TRANS_END_STEPS] = {
136 RTL8821A_TRANS_CARDDIS_TO_CARDEMU
137 RTL8821A_TRANS_CARDEMU_TO_ACT
138 RTL8821A_TRANS_END
139};
140
141/*3Suspend Array*/
142struct wlan_pwr_cfg rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
143 + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
144 + RTL8821A_TRANS_END_STEPS] = {
145 RTL8821A_TRANS_ACT_TO_CARDEMU
146 RTL8821A_TRANS_CARDEMU_TO_SUS
147 RTL8821A_TRANS_END
148};
149
150/*3 Resume Array*/
151struct wlan_pwr_cfg rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
152 + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
153 + RTL8821A_TRANS_END_STEPS] = {
154 RTL8821A_TRANS_SUS_TO_CARDEMU
155 RTL8821A_TRANS_CARDEMU_TO_ACT
156 RTL8821A_TRANS_END
157};
158
159/*3HWPDN Array*/
160struct wlan_pwr_cfg rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
161 + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
162 + RTL8821A_TRANS_END_STEPS] = {
163 RTL8821A_TRANS_ACT_TO_CARDEMU
164 RTL8821A_TRANS_CARDEMU_TO_PDN
165 RTL8821A_TRANS_END
166};
167
168/*3 Enter LPS */
169struct wlan_pwr_cfg rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS
170 + RTL8821A_TRANS_END_STEPS] = {
171 /*FW behavior*/
172 RTL8821A_TRANS_ACT_TO_LPS
173 RTL8821A_TRANS_END
174};
175
176/*3 Leave LPS */
177struct wlan_pwr_cfg rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS
178 + RTL8821A_TRANS_END_STEPS] = {
179 /*FW behavior*/
180 RTL8821A_TRANS_LPS_TO_ACT
181 RTL8821A_TRANS_END
182};
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.h
new file mode 100644
index 000000000000..bf0b0ce9519c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/pwrseq.h
@@ -0,0 +1,738 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_PWRSEQ_H__
27#define __RTL8821AE_PWRSEQ_H__
28
29#include "../pwrseqcmd.h"
30#include "../btcoexist/halbt_precomp.h"
31
32#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
33#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
34#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
35#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
36#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 25
37#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
38#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
39#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
40#define RTL8812_TRANS_END_STEPS 1
41
42/* The following macros have the following format:
43 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
44 * comments },
45 */
46#define RTL8812_TRANS_CARDEMU_TO_ACT \
47 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
48 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
49 /* disable SW LPS 0x04[10]=0*/}, \
50 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
51 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
52 /* wait till 0x04[17] = 1 power ready*/}, \
53 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
54 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
55 /* disable HWPDN 0x04[15]=0*/}, \
56 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
58 /* disable WL suspend*/}, \
59 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
60 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
61 /* polling until return 0*/}, \
62 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
64
65#define RTL8812_TRANS_ACT_TO_CARDEMU \
66 {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
67 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
68 /* 0xc00[7:0] = 4 turn off 3-wire */}, \
69 {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
71 /* 0xe00[7:0] = 4 turn off 3-wire */}, \
72 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
74 /* 0x2[0] = 0 RESET BB, CLOSE RF */}, \
75 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
76 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
77 /*Delay 1us*/}, \
78 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
80 /* Whole BB is reset*/}, \
81 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \
83 /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/}, \
84 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
86 /*0x8[1] = 0 ANA clk =500k */}, \
87 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
89 /*0x04[9] = 1 turn off MAC by HW state machine*/}, \
90 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
92 /*wait till 0x04[9] = 0 polling until return 0 to disable*/},
93
94#define RTL8812_TRANS_CARDEMU_TO_SUS \
95 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
97 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
99 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
100 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
101 /* gpio11 input mode, gpio10~8 output mode */}, \
102 {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
104 /* gpio 0~7 output same value as input ?? */}, \
105 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
107 /* gpio0~7 output mode */}, \
108 {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
110 /* 0x47[7:0] = 00 gpio mode */}, \
111 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
113 /* suspend option all off */}, \
114 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
116 /*0x14[7] = 1 turn on ZCD */}, \
117 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
119 /* 0x15[0] =1 trun on ZCD */}, \
120 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
122 /*0x23[4] = 1 hpon LDO sleep mode */}, \
123 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
124 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
125 /*0x8[1] = 0 ANA clk =500k */}, \
126 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
128 /*0x04[11] = 2b'11 enable WL suspend for PCIe*/},
129
130#define RTL8812_TRANS_SUS_TO_CARDEMU \
131 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
133 /*0x04[11] = 2b'01enable WL suspend*/}, \
134 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
135 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
136 /*0x23[4] = 0 hpon LDO sleep mode leave */}, \
137 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
139 /* 0x15[0] =0 trun off ZCD */}, \
140 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
141 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
142 /*0x14[7] = 0 turn off ZCD */}, \
143 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
144 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
145 /* gpio0~7 input mode */}, \
146 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
147 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
148 /* gpio11 input mode, gpio10~8 input mode */},
149
150#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
151 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
153 /*0x03[2] = 0, reset 8051*/}, \
154 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \
156 /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/}, \
157 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
159 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
160 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
161 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
162 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
163 /* gpio11 input mode, gpio10~8 output mode */}, \
164 {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
165 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
166 /* gpio 0~7 output same value as input ?? */}, \
167 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
168 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
169 /* gpio0~7 output mode */}, \
170 {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
171 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
172 /* 0x47[7:0] = 00 gpio mode */}, \
173 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
174 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
175 /*0x14[7] = 1 turn on ZCD */}, \
176 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
178 /* 0x15[0] =1 trun on ZCD */}, \
179 {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
180 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
181 /*0x12[0] = 0 force PFM mode */}, \
182 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
184 /*0x23[4] = 1 hpon LDO sleep mode */}, \
185 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
186 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
187 /*0x8[1] = 0 ANA clk =500k */}, \
188 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
189 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
190 /*0x07=0x20 , SOP option to disable BG/MB*/}, \
191 {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
192 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
193 /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */}, \
194 {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
196 /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */}, \
197 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
198 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
199 /*0x04[11] = 2b'01 enable WL suspend*/},
200
201#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
202 {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
203 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
204 /*0x12[0] = 1 force PWM mode */}, \
205 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
207 /*0x14[7] = 0 turn off ZCD */}, \
208 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
210 /* 0x15[0] =0 trun off ZCD */}, \
211 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
212 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
213 /*0x23[4] = 0 hpon LDO leave sleep mode */}, \
214 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
215 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
216 /* gpio0~7 input mode */}, \
217 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
219 /* gpio11 input mode, gpio10~8 input mode */}, \
220 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
222 /*0x04[10] = 0, enable SW LPS PCIE only*/}, \
223 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
225 /*0x04[11] = 2b'01enable WL suspend*/}, \
226 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
228 /*0x03[2] = 1, enable 8051*/}, \
229 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
231 /*PCIe DMA start*/},
232
233#define RTL8812_TRANS_CARDEMU_TO_PDN \
234 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
235 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
236 /* 0x04[15] = 1*/},
237
238#define RTL8812_TRANS_PDN_TO_CARDEMU \
239 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
241 /* 0x04[15] = 0*/},
242
243#define RTL8812_TRANS_ACT_TO_LPS \
244 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
245 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
246 /*PCIe DMA stop*/}, \
247 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
249 /*Tx Pause*/}, \
250 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
251 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
252 /*Should be zero if no packet is transmitting*/}, \
253 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
254 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
255 /*Should be zero if no packet is transmitting*/}, \
256 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
257 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
258 /*Should be zero if no packet is transmitting*/}, \
259 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
260 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
261 /*Should be zero if no packet is transmitting*/}, \
262 {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
263 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
264 /* 0xc00[7:0] = 4 turn off 3-wire */}, \
265 {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
267 /* 0xe00[7:0] = 4 turn off 3-wire */}, \
268 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
269 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
270 /*CCK and OFDM are disabled,and clock are gated,and RF closed*/}, \
271 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
272 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
273 /*Delay 1us*/}, \
274 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
275 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
276 /* Whole BB is reset*/}, \
277 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
278 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
279 /*Reset MAC TRX*/}, \
280 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
281 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
282 /*check if removed later*/}, \
283 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
284 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
285 /*Respond TxOK to scheduler*/},
286
287#define RTL8812_TRANS_LPS_TO_ACT \
288 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
289 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
290 /*SDIO RPWM*/}, \
291 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
293 /*USB RPWM*/}, \
294 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
295 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
296 /*PCIe RPWM*/}, \
297 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
298 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
299 /*Delay*/}, \
300 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
302 /*. 0x08[4] = 0 switch TSF to 40M*/}, \
303 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
304 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
305 /*Polling 0x109[7]=0 TSF in 40M*/}, \
306 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
308 /*. 0x29[7:6] = 2b'00 enable BB clock*/}, \
309 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
311 /*. 0x101[1] = 1*/}, \
312 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
313 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
314 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/}, \
315 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
317 /*. 0x02[1:0] = 2b'11 enable BB macro*/}, \
318 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
319 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
320 /*. 0x522 = 0*/},
321
322#define RTL8812_TRANS_END \
323 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
324 0, PWR_CMD_END, 0, 0},
325
326extern struct wlan_pwr_cfg rtl8812_power_on_flow
327 [RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
328 RTL8812_TRANS_END_STEPS];
329extern struct wlan_pwr_cfg rtl8812_radio_off_flow
330 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
331 RTL8812_TRANS_END_STEPS];
332extern struct wlan_pwr_cfg rtl8812_card_disable_flow
333 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
334 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
335 RTL8812_TRANS_END_STEPS];
336extern struct wlan_pwr_cfg rtl8812_card_enable_flow
337 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
338 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
339 RTL8812_TRANS_END_STEPS];
340extern struct wlan_pwr_cfg rtl8812_suspend_flow
341 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
342 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
343 RTL8812_TRANS_END_STEPS];
344extern struct wlan_pwr_cfg rtl8812_resume_flow
345 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
346 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
347 RTL8812_TRANS_END_STEPS];
348extern struct wlan_pwr_cfg rtl8812_hwpdn_flow
349 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
350 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
351 RTL8812_TRANS_END_STEPS];
352extern struct wlan_pwr_cfg rtl8812_enter_lps_flow
353 [RTL8812_TRANS_ACT_TO_LPS_STEPS +
354 RTL8812_TRANS_END_STEPS];
355extern struct wlan_pwr_cfg rtl8812_leave_lps_flow
356 [RTL8812_TRANS_LPS_TO_ACT_STEPS +
357 RTL8812_TRANS_END_STEPS];
358
359/* Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
360 * There are 6 HW Power States:
361 * 0: POFF--Power Off
362 * 1: PDN--Power Down
363 * 2: CARDEMU--Card Emulation
364 * 3: ACT--Active Mode
365 * 4: LPS--Low Power State
366 * 5: SUS--Suspend
367 *
368 * The transision from different states are defined below
369 * TRANS_CARDEMU_TO_ACT
370 * TRANS_ACT_TO_CARDEMU
371 * TRANS_CARDEMU_TO_SUS
372 * TRANS_SUS_TO_CARDEMU
373 * TRANS_CARDEMU_TO_PDN
374 * TRANS_ACT_TO_LPS
375 * TRANS_LPS_TO_ACT
376 *
377 * TRANS_END
378 */
379#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
380#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
381#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
382#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
383#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
384#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
385#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
386#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
387#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
388#define RTL8821A_TRANS_END_STEPS 1
389
390#define RTL8821A_TRANS_CARDEMU_TO_ACT \
391 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
392 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
393 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
394 /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/}, \
395 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
396 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
397 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
398 /*0x67[0] = 0 to disable BT_GPS_SEL pins*/}, \
399 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
400 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
401 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS \
402 /*Delay 1ms*/}, \
403 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
404 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
405 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
406 /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/}, \
407 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
409 /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/}, \
410 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
411 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
412 /* Disable USB suspend */}, \
413 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
414 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
415 /* wait till 0x04[17] = 1 power ready*/}, \
416 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
417 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
418 /* Enable USB suspend */}, \
419 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
420 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
421 /* release WLON reset 0x04[16]=1*/}, \
422 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
423 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
424 /* disable HWPDN 0x04[15]=0*/}, \
425 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
427 /* disable WL suspend*/}, \
428 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
429 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
430 /* polling until return 0*/}, \
431 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
432 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
433 /**/}, \
434 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
435 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
436 /*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */},\
437 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
439 /*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A \
440 from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */},\
441 {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
442 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
443 /*anapar_mac<118> , 0x25[6]=0 by wlan single function*/},\
444 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
445 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
446 /*Enable falling edge triggering interrupt*/},\
447 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
448 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
449 /*Enable GPIO9 interrupt mode*/},\
450 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
451 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
452 /*Enable GPIO9 input mode*/},\
453 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
454 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
455 /*Enable HSISR GPIO[C:0] interrupt*/},\
456 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
457 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
458 /*Enable HSISR GPIO9 interrupt*/},\
459 {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
460 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \
461 /*0x7A = 0x3A start BT*/},\
462 {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
463 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 \
464 /* 0x2C[23:12]=0x820 ; XTAL trim */}, \
465 {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
467 /* 0x10[6]=1 */},
468
469#define RTL8821A_TRANS_ACT_TO_CARDEMU \
470 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
471 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
472 /*0x1F[7:0] = 0 turn off RF*/}, \
473 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
474 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
475 /*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from \
476 register 0x65[2] */},\
477 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
478 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
479 /*Enable rising edge triggering interrupt*/}, \
480 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
481 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
482 /*0x04[9] = 1 turn off MAC by HW state machine*/}, \
483 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
484 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
485 /*wait till 0x04[9] = 0 polling until return 0 to disable*/}, \
486 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
487 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
489 /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/}, \
490 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
491 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
492 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
493 /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/},
494
495#define RTL8821A_TRANS_CARDEMU_TO_SUS \
496 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
498 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/}, \
499 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
500 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
501 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
502 /*0x04[12:11] = 2b'01 enable WL suspend*/}, \
503 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
504 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
505 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \
506 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
507 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
508 /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/}, \
509 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
510 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
511 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/}, \
512 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
513 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
514 /*Set SDIO suspend local register*/}, \
515 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
516 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
517 /*wait power state to suspend*/},
518
519#define RTL8821A_TRANS_SUS_TO_CARDEMU \
520 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
521 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
522 /*clear suspend enable and power down enable*/}, \
523 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
524 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
525 /*Set SDIO suspend local register*/}, \
526 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
527 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
528 /*wait power state to suspend*/},\
529 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
530 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
531 /*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \
532 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
533 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
534 /*0x04[12:11] = 2b'01enable WL suspend*/},
535
536#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
537 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
538 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
539 /*0x07=0x20 , SOP option to disable BG/MB*/}, \
540 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
541 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
542 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
543 /*0x04[12:11] = 2b'01 enable WL suspend*/}, \
544 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
545 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
546 /*0x04[10] = 1, enable SW LPS*/}, \
547 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
548 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
549 /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/}, \
550 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
551 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
552 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \
553 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
554 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
555 /*Set SDIO suspend local register*/}, \
556 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
557 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
558 /*wait power state to suspend*/},
559
560#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
561 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
562 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
563 /*clear suspend enable and power down enable*/}, \
564 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
565 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
566 /*Set SDIO suspend local register*/}, \
567 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
568 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
569 /*wait power state to suspend*/},\
570 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
571 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
572 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/}, \
573 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
574 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
575 /*0x04[12:11] = 2b'01enable WL suspend*/},\
576 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
577 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
578 /*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \
579 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
580 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
581 /*PCIe DMA start*/},
582
583#define RTL8821A_TRANS_CARDEMU_TO_PDN \
584 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
585 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
586 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \
587 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
588 PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,\
589 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
590 /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/}, \
591 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
592 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
593 /* 0x04[16] = 0*/},\
594 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
595 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
596 /* 0x04[15] = 1*/},
597
598#define RTL8821A_TRANS_PDN_TO_CARDEMU \
599 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
600 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
601 /* 0x04[15] = 0*/},
602
603#define RTL8821A_TRANS_ACT_TO_LPS \
604 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
605 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
606 /*PCIe DMA stop*/}, \
607 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
608 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
609 /*Tx Pause*/}, \
610 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
611 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
612 /*Should be zero if no packet is transmitting*/}, \
613 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
614 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
615 /*Should be zero if no packet is transmitting*/}, \
616 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
617 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
618 /*Should be zero if no packet is transmitting*/}, \
619 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
620 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
621 /*Should be zero if no packet is transmitting*/}, \
622 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
623 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
624 /*CCK and OFDM are disabled,and clock are gated*/}, \
625 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
626 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
627 /*Delay 1us*/}, \
628 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
629 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
630 /*Whole BB is reset*/}, \
631 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
632 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
633 /*Reset MAC TRX*/}, \
634 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
635 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
636 /*check if removed later*/}, \
637 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
638 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
639 /*When driver enter Sus/ Disable, enable LOP for BT*/}, \
640 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
641 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
642 /*Respond TxOK to scheduler*/},
643
644#define RTL8821A_TRANS_LPS_TO_ACT \
645 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
646 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
647 /*SDIO RPWM*/},\
648 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
649 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
650 /*USB RPWM*/},\
651 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
652 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
653 /*PCIe RPWM*/},\
654 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
655 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
656 /*Delay*/},\
657 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
658 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
659 /*. 0x08[4] = 0 switch TSF to 40M*/},\
660 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
661 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
662 /*Polling 0x109[7]=0 TSF in 40M*/},\
663 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
664 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
665 /*. 0x29[7:6] = 2b'00 enable BB clock*/},\
666 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
667 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
668 /*. 0x101[1] = 1*/},\
669 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
670 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
671 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/},\
672 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
673 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
674 /*. 0x02[1:0] = 2b'11 enable BB macro*/},\
675 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
676 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
677 /*. 0x522 = 0*/},
678
679#define RTL8821A_TRANS_END \
680 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
681 0, PWR_CMD_END, 0, 0},
682
683extern struct wlan_pwr_cfg rtl8821A_power_on_flow
684 [RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
685 RTL8821A_TRANS_END_STEPS];
686extern struct wlan_pwr_cfg rtl8821A_radio_off_flow
687 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
688 RTL8821A_TRANS_END_STEPS];
689extern struct wlan_pwr_cfg rtl8821A_card_disable_flow
690 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
691 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
692 RTL8821A_TRANS_END_STEPS];
693extern struct wlan_pwr_cfg rtl8821A_card_enable_flow
694 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
695 RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
696 RTL8821A_TRANS_END_STEPS];
697extern struct wlan_pwr_cfg rtl8821A_suspend_flow
698 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
699 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
700 RTL8821A_TRANS_END_STEPS];
701extern struct wlan_pwr_cfg rtl8821A_resume_flow
702 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
703 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
704 RTL8821A_TRANS_END_STEPS];
705extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow
706 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
707 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
708 RTL8821A_TRANS_END_STEPS];
709extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow
710 [RTL8821A_TRANS_ACT_TO_LPS_STEPS +
711 RTL8821A_TRANS_END_STEPS];
712extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow
713 [RTL8821A_TRANS_LPS_TO_ACT_STEPS +
714 RTL8821A_TRANS_END_STEPS];
715
716/*RTL8812 Power Configuration CMDs for PCIe interface*/
717#define RTL8812_NIC_PWR_ON_FLOW rtl8812_power_on_flow
718#define RTL8812_NIC_RF_OFF_FLOW rtl8812_radio_off_flow
719#define RTL8812_NIC_DISABLE_FLOW rtl8812_card_disable_flow
720#define RTL8812_NIC_ENABLE_FLOW rtl8812_card_enable_flow
721#define RTL8812_NIC_SUSPEND_FLOW rtl8812_suspend_flow
722#define RTL8812_NIC_RESUME_FLOW rtl8812_resume_flow
723#define RTL8812_NIC_PDN_FLOW rtl8812_hwpdn_flow
724#define RTL8812_NIC_LPS_ENTER_FLOW rtl8812_enter_lps_flow
725#define RTL8812_NIC_LPS_LEAVE_FLOW rtl8812_leave_lps_flow
726
727/* RTL8821 Power Configuration CMDs for PCIe interface */
728#define RTL8821A_NIC_PWR_ON_FLOW rtl8821A_power_on_flow
729#define RTL8821A_NIC_RF_OFF_FLOW rtl8821A_radio_off_flow
730#define RTL8821A_NIC_DISABLE_FLOW rtl8821A_card_disable_flow
731#define RTL8821A_NIC_ENABLE_FLOW rtl8821A_card_enable_flow
732#define RTL8821A_NIC_SUSPEND_FLOW rtl8821A_suspend_flow
733#define RTL8821A_NIC_RESUME_FLOW rtl8821A_resume_flow
734#define RTL8821A_NIC_PDN_FLOW rtl8821A_hwpdn_flow
735#define RTL8821A_NIC_LPS_ENTER_FLOW rtl8821A_enter_lps_flow
736#define RTL8821A_NIC_LPS_LEAVE_FLOW rtl8821A_leave_lps_flow
737
738#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/reg.h b/drivers/net/wireless/rtlwifi/rtl8821ae/reg.h
new file mode 100644
index 000000000000..53668fc8f23e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/reg.h
@@ -0,0 +1,2464 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_REG_H__
27#define __RTL8821AE_REG_H__
28
29#define TXPKT_BUF_SELECT 0x69
30#define RXPKT_BUF_SELECT 0xA5
31#define DISABLE_TRXPKT_BUF_ACCESS 0x0
32
33#define REG_SYS_ISO_CTRL 0x0000
34#define REG_SYS_FUNC_EN 0x0002
35#define REG_APS_FSMCO 0x0004
36#define REG_SYS_CLKR 0x0008
37#define REG_9346CR 0x000A
38#define REG_EE_VPD 0x000C
39#define REG_AFE_MISC 0x0010
40#define REG_SPS0_CTRL 0x0011
41#define REG_SPS_OCP_CFG 0x0018
42#define REG_RSV_CTRL 0x001C
43#define REG_RF_CTRL 0x001F
44#define REG_LDOA15_CTRL 0x0020
45#define REG_LDOV12D_CTRL 0x0021
46#define REG_LDOHCI12_CTRL 0x0022
47#define REG_LPLDO_CTRL 0x0023
48#define REG_AFE_XTAL_CTRL 0x0024
49 /* 1.5v for 8188EE test chip, 1.4v for MP chip */
50#define REG_AFE_LDO_CTRL 0x0027
51#define REG_AFE_PLL_CTRL 0x0028
52#define REG_MAC_PHY_CTRL 0x002c
53#define REG_EFUSE_CTRL 0x0030
54#define REG_EFUSE_TEST 0x0034
55#define REG_PWR_DATA 0x0038
56#define REG_CAL_TIMER 0x003C
57#define REG_ACLK_MON 0x003E
58#define REG_GPIO_MUXCFG 0x0040
59#define REG_GPIO_IO_SEL 0x0042
60#define REG_MAC_PINMUX_CFG 0x0043
61#define REG_GPIO_PIN_CTRL 0x0044
62#define REG_GPIO_INTM 0x0048
63#define REG_LEDCFG0 0x004C
64#define REG_LEDCFG1 0x004D
65#define REG_LEDCFG2 0x004E
66#define REG_LEDCFG3 0x004F
67#define REG_FSIMR 0x0050
68#define REG_FSISR 0x0054
69#define REG_HSIMR 0x0058
70#define REG_HSISR 0x005c
71#define REG_GPIO_PIN_CTRL_2 0x0060
72#define REG_GPIO_IO_SEL_2 0x0062
73#define REG_MULTI_FUNC_CTRL 0x0068
74#define REG_GPIO_OUTPUT 0x006c
75#define REG_OPT_CTRL 0x0074
76#define REG_AFE_XTAL_CTRL_EXT 0x0078
77#define REG_XCK_OUT_CTRL 0x007c
78#define REG_MCUFWDL 0x0080
79#define REG_WOL_EVENT 0x0081
80#define REG_MCUTSTCFG 0x0084
81
82#define REG_HIMR 0x00B0
83#define REG_HISR 0x00B4
84#define REG_HIMRE 0x00B8
85#define REG_HISRE 0x00BC
86
87#define REG_PMC_DBG_CTRL2 0x00CC
88
89#define REG_EFUSE_ACCESS 0x00CF
90
91#define REG_BIST_SCAN 0x00D0
92#define REG_BIST_RPT 0x00D4
93#define REG_BIST_ROM_RPT 0x00D8
94#define REG_USB_SIE_INTF 0x00E0
95#define REG_PCIE_MIO_INTF 0x00E4
96#define REG_PCIE_MIO_INTD 0x00E8
97#define REG_HPON_FSM 0x00EC
98#define REG_SYS_CFG 0x00F0
99#define REG_GPIO_OUTSTS 0x00F4
100#define REG_MAC_PHY_CTRL_NORMAL 0x00F8
101#define REG_SYS_CFG1 0x00FC
102#define REG_ROM_VERSION 0x00FD
103
104#define REG_CR 0x0100
105#define REG_PBP 0x0104
106#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
107#define REG_TRXDMA_CTRL 0x010C
108#define REG_TRXFF_BNDY 0x0114
109#define REG_TRXFF_STATUS 0x0118
110#define REG_RXFF_PTR 0x011C
111
112#define REG_CPWM 0x012F
113#define REG_FWIMR 0x0130
114#define REG_FWISR 0x0134
115#define REG_FTISR 0x013C
116#define REG_PKTBUF_DBG_CTRL 0x0140
117#define REG_PKTBUF_DBG_DATA_L 0x0144
118#define REG_PKTBUF_DBG_DATA_H 0x0148
119#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)
120
121#define REG_TC0_CTRL 0x0150
122#define REG_TC1_CTRL 0x0154
123#define REG_TC2_CTRL 0x0158
124#define REG_TC3_CTRL 0x015C
125#define REG_TC4_CTRL 0x0160
126#define REG_TCUNIT_BASE 0x0164
127#define REG_MBIST_START 0x0174
128#define REG_MBIST_DONE 0x0178
129#define REG_MBIST_FAIL 0x017C
130#define REG_32K_CTRL 0x0194
131#define REG_C2HEVT_MSG_NORMAL 0x01A0
132#define REG_C2HEVT_CLEAR 0x01AF
133#define REG_C2HEVT_MSG_TEST 0x01B8
134#define REG_MCUTST_1 0x01c0
135#define REG_MCUTST_WOWLAN 0x01C7
136#define REG_FMETHR 0x01C8
137#define REG_HMETFR 0x01CC
138#define REG_HMEBOX_0 0x01D0
139#define REG_HMEBOX_1 0x01D4
140#define REG_HMEBOX_2 0x01D8
141#define REG_HMEBOX_3 0x01DC
142
143#define REG_LLT_INIT 0x01E0
144#define REG_BB_ACCEESS_CTRL 0x01E8
145#define REG_BB_ACCESS_DATA 0x01EC
146
147#define REG_HMEBOX_EXT_0 0x01F0
148#define REG_HMEBOX_EXT_1 0x01F4
149#define REG_HMEBOX_EXT_2 0x01F8
150#define REG_HMEBOX_EXT_3 0x01FC
151
152#define REG_RQPN 0x0200
153#define REG_FIFOPAGE 0x0204
154#define REG_TDECTRL 0x0208
155#define REG_TXDMA_OFFSET_CHK 0x020C
156#define REG_TXDMA_STATUS 0x0210
157#define REG_RQPN_NPQ 0x0214
158
159#define REG_RXDMA_AGG_PG_TH 0x0280
160 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
161#define REG_FW_UPD_RDPTR 0x0284
162 /* Control the RX DMA.*/
163#define REG_RXDMA_CONTROL 0x0286
164/* The number of packets in RXPKTBUF. */
165#define REG_RXPKT_NUM 0x0287
166
167#define REG_PCIE_CTRL_REG 0x0300
168#define REG_INT_MIG 0x0304
169#define REG_BCNQ_DESA 0x0308
170#define REG_HQ_DESA 0x0310
171#define REG_MGQ_DESA 0x0318
172#define REG_VOQ_DESA 0x0320
173#define REG_VIQ_DESA 0x0328
174#define REG_BEQ_DESA 0x0330
175#define REG_BKQ_DESA 0x0338
176#define REG_RX_DESA 0x0340
177
178#define REG_DBI_WDATA 0x0348
179#define REG_DBI_RDATA 0x034C
180#define REG_DBI_CTRL 0x0350
181#define REG_DBI_ADDR 0x0350
182#define REG_DBI_FLAG 0x0352
183#define REG_MDIO_WDATA 0x0354
184#define REG_MDIO_RDATA 0x0356
185#define REG_MDIO_CTL 0x0358
186#define REG_DBG_SEL 0x0360
187#define REG_PCIE_HRPWM 0x0361
188#define REG_PCIE_HCPWM 0x0363
189#define REG_UART_CTRL 0x0364
190#define REG_WATCH_DOG 0x0368
191#define REG_UART_TX_DESA 0x0370
192#define REG_UART_RX_DESA 0x0378
193
194#define REG_HDAQ_DESA_NODEF 0x0000
195#define REG_CMDQ_DESA_NODEF 0x0000
196
197#define REG_VOQ_INFORMATION 0x0400
198#define REG_VIQ_INFORMATION 0x0404
199#define REG_BEQ_INFORMATION 0x0408
200#define REG_BKQ_INFORMATION 0x040C
201#define REG_MGQ_INFORMATION 0x0410
202#define REG_HGQ_INFORMATION 0x0414
203#define REG_BCNQ_INFORMATION 0x0418
204#define REG_TXPKT_EMPTY 0x041A
205
206#define REG_CPU_MGQ_INFORMATION 0x041C
207#define REG_FWHW_TXQ_CTRL 0x0420
208#define REG_HWSEQ_CTRL 0x0423
209#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
210#define REG_TXPKTBUF_MGQ_BDNY 0x0425
211#define REG_MULTI_BCNQ_EN 0x0426
212#define REG_MULTI_BCNQ_OFFSET 0x0427
213#define REG_SPEC_SIFS 0x0428
214#define REG_RL 0x042A
215#define REG_DARFRC 0x0430
216#define REG_RARFRC 0x0438
217#define REG_RRSR 0x0440
218#define REG_ARFR0 0x0444
219#define REG_ARFR1 0x044C
220#define REG_CCK_CHECK 0x0454
221#define REG_AMPDU_MAX_TIME 0x0456
222#define REG_AGGLEN_LMT 0x0458
223#define REG_AMPDU_MIN_SPACE 0x045C
224#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
225#define REG_FAST_EDCA_CTRL 0x0460
226#define REG_RD_RESP_PKT_TH 0x0463
227#define REG_INIRTS_RATE_SEL 0x0480
228#define REG_INIDATA_RATE_SEL 0x0484
229#define REG_ARFR2 0x048C
230#define REG_ARFR3 0x0494
231#define REG_POWER_STATUS 0x04A4
232#define REG_POWER_STAGE1 0x04B4
233#define REG_POWER_STAGE2 0x04B8
234#define REG_PKT_LIFE_TIME 0x04C0
235#define REG_STBC_SETTING 0x04C4
236#define REG_HT_SINGLE_AMPDU 0x04C7
237#define REG_PROT_MODE_CTRL 0x04C8
238#define REG_MAX_AGGR_NUM 0x04CA
239#define REG_BAR_MODE_CTRL 0x04CC
240#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
241#define REG_EARLY_MODE_CONTROL 0x04D0
242#define REG_NQOS_SEQ 0x04DC
243#define REG_QOS_SEQ 0x04DE
244#define REG_NEED_CPU_HANDLE 0x04E0
245#define REG_PKT_LOSE_RPT 0x04E1
246#define REG_PTCL_ERR_STATUS 0x04E2
247#define REG_TX_RPT_CTRL 0x04EC
248#define REG_TX_RPT_TIME 0x04F0
249#define REG_DUMMY 0x04FC
250
251#define REG_EDCA_VO_PARAM 0x0500
252#define REG_EDCA_VI_PARAM 0x0504
253#define REG_EDCA_BE_PARAM 0x0508
254#define REG_EDCA_BK_PARAM 0x050C
255#define REG_BCNTCFG 0x0510
256#define REG_PIFS 0x0512
257#define REG_RDG_PIFS 0x0513
258#define REG_SIFS_CTX 0x0514
259#define REG_SIFS_TRX 0x0516
260#define REG_AGGR_BREAK_TIME 0x051A
261#define REG_SLOT 0x051B
262#define REG_TX_PTCL_CTRL 0x0520
263#define REG_TXPAUSE 0x0522
264#define REG_DIS_TXREQ_CLR 0x0523
265#define REG_RD_CTRL 0x0524
266#define REG_TBTT_PROHIBIT 0x0540
267#define REG_RD_NAV_NXT 0x0544
268#define REG_NAV_PROT_LEN 0x0546
269#define REG_BCN_CTRL 0x0550
270#define REG_USTIME_TSF 0x0551
271#define REG_MBID_NUM 0x0552
272#define REG_DUAL_TSF_RST 0x0553
273#define REG_BCN_INTERVAL 0x0554
274#define REG_MBSSID_BCN_SPACE 0x0554
275#define REG_DRVERLYINT 0x0558
276#define REG_BCNDMATIM 0x0559
277#define REG_ATIMWND 0x055A
278#define REG_BCN_MAX_ERR 0x055D
279#define REG_RXTSF_OFFSET_CCK 0x055E
280#define REG_RXTSF_OFFSET_OFDM 0x055F
281#define REG_TSFTR 0x0560
282#define REG_INIT_TSFTR 0x0564
283#define REG_SECONDARY_CCA_CTRL 0x0577
284#define REG_PSTIMER 0x0580
285#define REG_TIMER0 0x0584
286#define REG_TIMER1 0x0588
287#define REG_ACMHWCTRL 0x05C0
288#define REG_ACMRSTCTRL 0x05C1
289#define REG_ACMAVG 0x05C2
290#define REG_VO_ADMTIME 0x05C4
291#define REG_VI_ADMTIME 0x05C6
292#define REG_BE_ADMTIME 0x05C8
293#define REG_EDCA_RANDOM_GEN 0x05CC
294#define REG_NOA_DESC_SEL 0x05CF
295#define REG_NOA_DESC_DURATION 0x05E0
296#define REG_NOA_DESC_INTERVAL 0x05E4
297#define REG_NOA_DESC_START 0x05E8
298#define REG_NOA_DESC_COUNT 0x05EC
299#define REG_SCH_TXCMD 0x05F8
300
301#define REG_APSD_CTRL 0x0600
302#define REG_BWOPMODE 0x0603
303#define REG_TCR 0x0604
304#define REG_RCR 0x0608
305#define REG_RX_PKT_LIMIT 0x060C
306#define REG_RX_DLK_TIME 0x060D
307#define REG_RX_DRVINFO_SZ 0x060F
308
309#define REG_MACID 0x0610
310#define REG_BSSID 0x0618
311#define REG_MAR 0x0620
312#define REG_MBIDCAMCFG 0x0628
313
314#define REG_USTIME_EDCA 0x0638
315#define REG_MAC_SPEC_SIFS 0x063A
316#define REG_RESP_SIFS_CCK 0x063C
317#define REG_RESP_SIFS_OFDM 0x063E
318#define REG_ACKTO 0x0640
319#define REG_CTS2TO 0x0641
320#define REG_EIFS 0x0642
321
322#define REG_NAV_CTRL 0x0650
323#define REG_NAV_UPPER 0x0652
324#define REG_BACAMCMD 0x0654
325#define REG_BACAMCONTENT 0x0658
326#define REG_LBDLY 0x0660
327#define REG_FWDLY 0x0661
328#define REG_RXERR_RPT 0x0664
329#define REG_TRXPTCL_CTL 0x0668
330
331#define REG_CAMCMD 0x0670
332#define REG_CAMWRITE 0x0674
333#define REG_CAMREAD 0x0678
334#define REG_CAMDBG 0x067C
335#define REG_SECCFG 0x0680
336
337#define REG_WOW_CTRL 0x0690
338#define REG_PSSTATUS 0x0691
339#define REG_PS_RX_INFO 0x0692
340#define REG_UAPSD_TID 0x0693
341#define REG_LPNAV_CTRL 0x0694
342#define REG_WKFMCAM_NUM 0x0698
343#define REG_WKFMCAM_RWD 0x069C
344#define REG_RXFLTMAP0 0x06A0
345#define REG_RXFLTMAP1 0x06A2
346#define REG_RXFLTMAP2 0x06A4
347#define REG_BCN_PSR_RPT 0x06A8
348#define REG_CALB32K_CTRL 0x06AC
349#define REG_PKT_MON_CTRL 0x06B4
350#define REG_BT_COEX_TABLE 0x06C0
351#define REG_WMAC_RESP_TXINFO 0x06D8
352
353#define REG_USB_INFO 0xFE17
354#define REG_USB_SPECIAL_OPTION 0xFE55
355#define REG_USB_DMA_AGG_TO 0xFE5B
356#define REG_USB_AGG_TO 0xFE5C
357#define REG_USB_AGG_TH 0xFE5D
358
359#define REG_TEST_USB_TXQS 0xFE48
360#define REG_TEST_SIE_VID 0xFE60
361#define REG_TEST_SIE_PID 0xFE62
362#define REG_TEST_SIE_OPTIONAL 0xFE64
363#define REG_TEST_SIE_CHIRP_K 0xFE65
364#define REG_TEST_SIE_PHY 0xFE66
365#define REG_TEST_SIE_MAC_ADDR 0xFE70
366#define REG_TEST_SIE_STRING 0xFE80
367
368#define REG_NORMAL_SIE_VID 0xFE60
369#define REG_NORMAL_SIE_PID 0xFE62
370#define REG_NORMAL_SIE_OPTIONAL 0xFE64
371#define REG_NORMAL_SIE_EP 0xFE65
372#define REG_NORMAL_SIE_PHY 0xFE68
373#define REG_NORMAL_SIE_MAC_ADDR 0xFE70
374#define REG_NORMAL_SIE_STRING 0xFE80
375
376#define CR9346 REG_9346CR
377#define MSR (REG_CR + 2)
378#define ISR REG_HISR
379#define TSFR REG_TSFTR
380
381#define MACIDR0 REG_MACID
382#define MACIDR4 (REG_MACID + 4)
383
384#define PBP REG_PBP
385
386#define IDR0 MACIDR0
387#define IDR4 MACIDR4
388
389#define UNUSED_REGISTER 0x1BF
390#define DCAM UNUSED_REGISTER
391#define PSR UNUSED_REGISTER
392#define BBADDR UNUSED_REGISTER
393#define PHYDATAR UNUSED_REGISTER
394
395#define INVALID_BBRF_VALUE 0x12345678
396
397#define MAX_MSS_DENSITY_2T 0x13
398#define MAX_MSS_DENSITY_1T 0x0A
399
400#define CMDEEPROM_EN BIT(5)
401#define CMDEEPROM_SEL BIT(4)
402#define CMD9346CR_9356SEL BIT(4)
403#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)
404#define AUTOLOAD_EFUSE CMDEEPROM_EN
405
406#define GPIOSEL_GPIO 0
407#define GPIOSEL_ENBT BIT(5)
408
409#define GPIO_IN REG_GPIO_PIN_CTRL
410#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)
411#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
412#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
413
414/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
415#define HSIMR_GPIO12_0_INT_EN BIT(0)
416#define HSIMR_SPS_OCP_INT_EN BIT(5)
417#define HSIMR_RON_INT_EN BIT(6)
418#define HSIMR_PDN_INT_EN BIT(7)
419#define HSIMR_GPIO9_INT_EN BIT(25)
420
421/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
422#define HSISR_GPIO12_0_INT BIT(0)
423#define HSISR_SPS_OCP_INT BIT(5)
424#define HSISR_RON_INT_EN BIT(6)
425#define HSISR_PDNINT BIT(7)
426#define HSISR_GPIO9_INT BIT(25)
427
428#define MSR_NOLINK 0x00
429#define MSR_ADHOC 0x01
430#define MSR_INFRA 0x02
431#define MSR_AP 0x03
432
433#define RRSR_RSC_OFFSET 21
434#define RRSR_SHORT_OFFSET 23
435#define RRSR_RSC_BW_40M 0x600000
436#define RRSR_RSC_UPSUBCHNL 0x400000
437#define RRSR_RSC_LOWSUBCHNL 0x200000
438#define RRSR_SHORT 0x800000
439#define RRSR_1M BIT(0)
440#define RRSR_2M BIT(1)
441#define RRSR_5_5M BIT(2)
442#define RRSR_11M BIT(3)
443#define RRSR_6M BIT(4)
444#define RRSR_9M BIT(5)
445#define RRSR_12M BIT(6)
446#define RRSR_18M BIT(7)
447#define RRSR_24M BIT(8)
448#define RRSR_36M BIT(9)
449#define RRSR_48M BIT(10)
450#define RRSR_54M BIT(11)
451#define RRSR_MCS0 BIT(12)
452#define RRSR_MCS1 BIT(13)
453#define RRSR_MCS2 BIT(14)
454#define RRSR_MCS3 BIT(15)
455#define RRSR_MCS4 BIT(16)
456#define RRSR_MCS5 BIT(17)
457#define RRSR_MCS6 BIT(18)
458#define RRSR_MCS7 BIT(19)
459#define BRSR_ACKSHORTPMB BIT(23)
460
461#define RATR_1M 0x00000001
462#define RATR_2M 0x00000002
463#define RATR_55M 0x00000004
464#define RATR_11M 0x00000008
465#define RATR_6M 0x00000010
466#define RATR_9M 0x00000020
467#define RATR_12M 0x00000040
468#define RATR_18M 0x00000080
469#define RATR_24M 0x00000100
470#define RATR_36M 0x00000200
471#define RATR_48M 0x00000400
472#define RATR_54M 0x00000800
473#define RATR_MCS0 0x00001000
474#define RATR_MCS1 0x00002000
475#define RATR_MCS2 0x00004000
476#define RATR_MCS3 0x00008000
477#define RATR_MCS4 0x00010000
478#define RATR_MCS5 0x00020000
479#define RATR_MCS6 0x00040000
480#define RATR_MCS7 0x00080000
481#define RATR_MCS8 0x00100000
482#define RATR_MCS9 0x00200000
483#define RATR_MCS10 0x00400000
484#define RATR_MCS11 0x00800000
485#define RATR_MCS12 0x01000000
486#define RATR_MCS13 0x02000000
487#define RATR_MCS14 0x04000000
488#define RATR_MCS15 0x08000000
489
490#define RATE_1M BIT(0)
491#define RATE_2M BIT(1)
492#define RATE_5_5M BIT(2)
493#define RATE_11M BIT(3)
494#define RATE_6M BIT(4)
495#define RATE_9M BIT(5)
496#define RATE_12M BIT(6)
497#define RATE_18M BIT(7)
498#define RATE_24M BIT(8)
499#define RATE_36M BIT(9)
500#define RATE_48M BIT(10)
501#define RATE_54M BIT(11)
502#define RATE_MCS0 BIT(12)
503#define RATE_MCS1 BIT(13)
504#define RATE_MCS2 BIT(14)
505#define RATE_MCS3 BIT(15)
506#define RATE_MCS4 BIT(16)
507#define RATE_MCS5 BIT(17)
508#define RATE_MCS6 BIT(18)
509#define RATE_MCS7 BIT(19)
510#define RATE_MCS8 BIT(20)
511#define RATE_MCS9 BIT(21)
512#define RATE_MCS10 BIT(22)
513#define RATE_MCS11 BIT(23)
514#define RATE_MCS12 BIT(24)
515#define RATE_MCS13 BIT(25)
516#define RATE_MCS14 BIT(26)
517#define RATE_MCS15 BIT(27)
518
519#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
520#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\
521 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
522#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\
523 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\
524 RATR_MCS6 | RATR_MCS7)
525#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\
526 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\
527 RATR_MCS14 | RATR_MCS15)
528
529#define BW_OPMODE_20MHZ BIT(2)
530#define BW_OPMODE_5G BIT(1)
531#define BW_OPMODE_11J BIT(0)
532
533#define CAM_VALID BIT(15)
534#define CAM_NOTVALID 0x0000
535#define CAM_USEDK BIT(5)
536
537#define CAM_NONE 0x0
538#define CAM_WEP40 0x01
539#define CAM_TKIP 0x02
540#define CAM_AES 0x04
541#define CAM_WEP104 0x05
542
543#define TOTAL_CAM_ENTRY 32
544#define HALF_CAM_ENTRY 16
545
546#define CAM_WRITE BIT(16)
547#define CAM_READ 0x00000000
548#define CAM_POLLINIG BIT(31)
549
550#define SCR_USEDK 0x01
551#define SCR_TXSEC_ENABLE 0x02
552#define SCR_RXSEC_ENABLE 0x04
553
554#define WOW_PMEN BIT(0)
555#define WOW_WOMEN BIT(1)
556#define WOW_MAGIC BIT(2)
557#define WOW_UWF BIT(3)
558
559/*********************************************
560* 8188 IMR/ISR bits
561**********************************************/
562#define IMR_DISABLED 0x0
563/* IMR DW0(0x0060-0063) Bit 0-31 */
564/* TXRPT interrupt when CCX bit of the packet is set */
565#define IMR_TXCCK BIT(30)
566/* Power Save Time Out Interrupt */
567#define IMR_PSTIMEOUT BIT(29)
568/* When GTIMER4 expires, this bit is set to 1 */
569#define IMR_GTINT4 BIT(28)
570/* When GTIMER3 expires, this bit is set to 1 */
571#define IMR_GTINT3 BIT(27)
572/* Transmit Beacon0 Error */
573#define IMR_TBDER BIT(26)
574/* Transmit Beacon0 OK */
575#define IMR_TBDOK BIT(25)
576/* TSF Timer BIT32 toggle indication interrupt */
577#define IMR_TSF_BIT32_TOGGLE BIT(24)
578/* Beacon DMA Interrupt 0 */
579#define IMR_BCNDMAINT0 BIT(20)
580/* Beacon Queue DMA OK0 */
581#define IMR_BCNDOK0 BIT(16)
582/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
583#define IMR_HSISR_IND_ON_INT BIT(15)
584/* Beacon DMA Interrupt Extension for Win7 */
585#define IMR_BCNDMAINT_E BIT(14)
586/* CTWidnow End or ATIM Window End */
587#define IMR_ATIMEND BIT(12)
588/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/
589#define IMR_HISR1_IND_INT BIT(11)
590/* CPU to Host Command INT Status, Write 1 clear */
591#define IMR_C2HCMD BIT(10)
592/* CPU power Mode exchange INT Status, Write 1 clear */
593#define IMR_CPWM2 BIT(9)
594/* CPU power Mode exchange INT Status, Write 1 clear */
595#define IMR_CPWM BIT(8)
596/* High Queue DMA OK */
597#define IMR_HIGHDOK BIT(7)
598/* Management Queue DMA OK */
599#define IMR_MGNTDOK BIT(6)
600/* AC_BK DMA OK */
601#define IMR_BKDOK BIT(5)
602/* AC_BE DMA OK */
603#define IMR_BEDOK BIT(4)
604/* AC_VI DMA OK */
605#define IMR_VIDOK BIT(3)
606/* AC_VO DMA OK */
607#define IMR_VODOK BIT(2)
608/* Rx Descriptor Unavailable */
609#define IMR_RDU BIT(1)
610#define IMR_ROK BIT(0) /* Receive DMA OK */
611
612/* IMR DW1(0x00B4-00B7) Bit 0-31 */
613/* Beacon DMA Interrupt 7 */
614#define IMR_BCNDMAINT7 BIT(27)
615/* Beacon DMA Interrupt 6 */
616#define IMR_BCNDMAINT6 BIT(26)
617/* Beacon DMA Interrupt 5 */
618#define IMR_BCNDMAINT5 BIT(25)
619/* Beacon DMA Interrupt 4 */
620#define IMR_BCNDMAINT4 BIT(24)
621/* Beacon DMA Interrupt 3 */
622#define IMR_BCNDMAINT3 BIT(23)
623/* Beacon DMA Interrupt 2 */
624#define IMR_BCNDMAINT2 BIT(22)
625/* Beacon DMA Interrupt 1 */
626#define IMR_BCNDMAINT1 BIT(21)
627/* Beacon Queue DMA OK Interrup 7 */
628#define IMR_BCNDOK7 BIT(20)
629/* Beacon Queue DMA OK Interrup 6 */
630#define IMR_BCNDOK6 BIT(19)
631/* Beacon Queue DMA OK Interrup 5 */
632#define IMR_BCNDOK5 BIT(18)
633/* Beacon Queue DMA OK Interrup 4 */
634#define IMR_BCNDOK4 BIT(17)
635/* Beacon Queue DMA OK Interrup 3 */
636#define IMR_BCNDOK3 BIT(16)
637/* Beacon Queue DMA OK Interrup 2 */
638#define IMR_BCNDOK2 BIT(15)
639/* Beacon Queue DMA OK Interrup 1 */
640#define IMR_BCNDOK1 BIT(14)
641/* ATIM Window End Extension for Win7 */
642#define IMR_ATIMEND_E BIT(13)
643/* Tx Error Flag Interrupt Status, write 1 clear. */
644#define IMR_TXERR BIT(11)
645/* Rx Error Flag INT Status, Write 1 clear */
646#define IMR_RXERR BIT(10)
647/* Transmit FIFO Overflow */
648#define IMR_TXFOVW BIT(9)
649/* Receive FIFO Overflow */
650#define IMR_RXFOVW BIT(8)
651
652#define HWSET_MAX_SIZE 512
653#define EFUSE_MAX_SECTION 64
654#define EFUSE_REAL_CONTENT_LEN 256
655/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/
656#define EFUSE_OOB_PROTECT_BYTES 18
657
658#define EEPROM_DEFAULT_TSSI 0x0
659#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
660#define EEPROM_DEFAULT_CRYSTALCAP 0x5
661#define EEPROM_DEFAULT_BOARDTYPE 0x02
662#define EEPROM_DEFAULT_TXPOWER 0x1010
663#define EEPROM_DEFAULT_HT2T_TXPWR 0x10
664
665#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
666#define EEPROM_DEFAULT_THERMALMETER 0x18
667#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
668#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
669#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
670#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
671#define EEPROM_DEFAULT_HT20_DIFF 2
672#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
673#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
674#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
675
676#define RF_OPTION1 0x79
677#define RF_OPTION2 0x7A
678#define RF_OPTION3 0x7B
679#define RF_OPTION4 0xC3
680
681#define EEPROM_DEFAULT_PID 0x1234
682#define EEPROM_DEFAULT_VID 0x5678
683#define EEPROM_DEFAULT_CUSTOMERID 0xAB
684#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
685#define EEPROM_DEFAULT_VERSION 0
686
687#define EEPROM_CHANNEL_PLAN_FCC 0x0
688#define EEPROM_CHANNEL_PLAN_IC 0x1
689#define EEPROM_CHANNEL_PLAN_ETSI 0x2
690#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
691#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
692#define EEPROM_CHANNEL_PLAN_MKK 0x5
693#define EEPROM_CHANNEL_PLAN_MKK1 0x6
694#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
695#define EEPROM_CHANNEL_PLAN_TELEC 0x8
696#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
697#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
698#define EEPROM_CHANNEL_PLAN_NCC 0xB
699#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
700
701#define EEPROM_CID_DEFAULT 0x0
702#define EEPROM_CID_TOSHIBA 0x4
703#define EEPROM_CID_CCX 0x10
704#define EEPROM_CID_QMI 0x0D
705#define EEPROM_CID_WHQL 0xFE
706
707#define RTL_EEPROM_ID 0x8129
708
709#define EEPROM_HPON 0x02
710#define EEPROM_CLK 0x06
711#define EEPROM_TESTR 0x08
712
713#define EEPROM_TXPOWERCCK 0x10
714#define EEPROM_TXPOWERHT40_1S 0x16
715#define EEPROM_TXPOWERHT20DIFF 0x1B
716#define EEPROM_TXPOWER_OFDMDIFF 0x1B
717
718#define EEPROM_TX_PWR_INX 0x10
719
720#define EEPROM_CHANNELPLAN 0xB8
721#define EEPROM_XTAL_8821AE 0xB9
722#define EEPROM_THERMAL_METER 0xBA
723#define EEPROM_IQK_LCK_88E 0xBB
724
725#define EEPROM_RF_BOARD_OPTION 0xC1
726#define EEPROM_RF_FEATURE_OPTION_88E 0xC2
727#define EEPROM_RF_BT_SETTING 0xC3
728#define EEPROM_VERSION 0xC4
729#define EEPROM_CUSTOMER_ID 0xC5
730#define EEPROM_RF_ANTENNA_OPT_88E 0xC9
731#define EEPROM_RFE_OPTION 0xCA
732
733#define EEPROM_MAC_ADDR 0xD0
734#define EEPROM_VID 0xD6
735#define EEPROM_DID 0xD8
736#define EEPROM_SVID 0xDA
737#define EEPROM_SMID 0xDC
738
739#define STOPBECON BIT(6)
740#define STOPHIGHT BIT(5)
741#define STOPMGT BIT(4)
742#define STOPVO BIT(3)
743#define STOPVI BIT(2)
744#define STOPBE BIT(1)
745#define STOPBK BIT(0)
746
747#define RCR_APPFCS BIT(31)
748#define RCR_APP_MIC BIT(30)
749#define RCR_APP_ICV BIT(29)
750#define RCR_APP_PHYST_RXFF BIT(28)
751#define RCR_APP_BA_SSN BIT(27)
752#define RCR_NONQOS_VHT BIT(26)
753#define RCR_ENMBID BIT(24)
754#define RCR_LSIGEN BIT(23)
755#define RCR_MFBEN BIT(22)
756#define RCR_HTC_LOC_CTRL BIT(14)
757#define RCR_AMF BIT(13)
758#define RCR_ACF BIT(12)
759#define RCR_ADF BIT(11)
760#define RCR_AICV BIT(9)
761#define RCR_ACRC32 BIT(8)
762#define RCR_CBSSID_BCN BIT(7)
763#define RCR_CBSSID_DATA BIT(6)
764#define RCR_CBSSID RCR_CBSSID_DATA
765#define RCR_APWRMGT BIT(5)
766#define RCR_ADD3 BIT(4)
767#define RCR_AB BIT(3)
768#define RCR_AM BIT(2)
769#define RCR_APM BIT(1)
770#define RCR_AAP BIT(0)
771#define RCR_MXDMA_OFFSET 8
772#define RCR_FIFO_OFFSET 13
773
774#define RSV_CTRL 0x001C
775#define RD_CTRL 0x0524
776
777#define REG_USB_INFO 0xFE17
778#define REG_USB_SPECIAL_OPTION 0xFE55
779#define REG_USB_DMA_AGG_TO 0xFE5B
780#define REG_USB_AGG_TO 0xFE5C
781#define REG_USB_AGG_TH 0xFE5D
782
783#define REG_USB_VID 0xFE60
784#define REG_USB_PID 0xFE62
785#define REG_USB_OPTIONAL 0xFE64
786#define REG_USB_CHIRP_K 0xFE65
787#define REG_USB_PHY 0xFE66
788#define REG_USB_MAC_ADDR 0xFE70
789#define REG_USB_HRPWM 0xFE58
790#define REG_USB_HCPWM 0xFE57
791
792#define SW18_FPWM BIT(3)
793
794#define ISO_MD2PP BIT(0)
795#define ISO_UA2USB BIT(1)
796#define ISO_UD2CORE BIT(2)
797#define ISO_PA2PCIE BIT(3)
798#define ISO_PD2CORE BIT(4)
799#define ISO_IP2MAC BIT(5)
800#define ISO_DIOP BIT(6)
801#define ISO_DIOE BIT(7)
802#define ISO_EB2CORE BIT(8)
803#define ISO_DIOR BIT(9)
804
805#define PWC_EV25V BIT(14)
806#define PWC_EV12V BIT(15)
807
808#define FEN_BBRSTB BIT(0)
809#define FEN_BB_GLB_RSTN BIT(1)
810#define FEN_USBA BIT(2)
811#define FEN_UPLL BIT(3)
812#define FEN_USBD BIT(4)
813#define FEN_DIO_PCIE BIT(5)
814#define FEN_PCIEA BIT(6)
815#define FEN_PPLL BIT(7)
816#define FEN_PCIED BIT(8)
817#define FEN_DIOE BIT(9)
818#define FEN_CPUEN BIT(10)
819#define FEN_DCORE BIT(11)
820#define FEN_ELDR BIT(12)
821#define FEN_DIO_RF BIT(13)
822#define FEN_HWPDN BIT(14)
823#define FEN_MREGEN BIT(15)
824
825#define PFM_LDALL BIT(0)
826#define PFM_ALDN BIT(1)
827#define PFM_LDKP BIT(2)
828#define PFM_WOWL BIT(3)
829#define ENPDN BIT(4)
830#define PDN_PL BIT(5)
831#define APFM_ONMAC BIT(8)
832#define APFM_OFF BIT(9)
833#define APFM_RSM BIT(10)
834#define AFSM_HSUS BIT(11)
835#define AFSM_PCIE BIT(12)
836#define APDM_MAC BIT(13)
837#define APDM_HOST BIT(14)
838#define APDM_HPDN BIT(15)
839#define RDY_MACON BIT(16)
840#define SUS_HOST BIT(17)
841#define ROP_ALD BIT(20)
842#define ROP_PWR BIT(21)
843#define ROP_SPS BIT(22)
844#define SOP_MRST BIT(25)
845#define SOP_FUSE BIT(26)
846#define SOP_ABG BIT(27)
847#define SOP_AMB BIT(28)
848#define SOP_RCK BIT(29)
849#define SOP_A8M BIT(30)
850#define XOP_BTCK BIT(31)
851
852#define ANAD16V_EN BIT(0)
853#define ANA8M BIT(1)
854#define MACSLP BIT(4)
855#define LOADER_CLK_EN BIT(5)
856#define _80M_SSC_DIS BIT(7)
857#define _80M_SSC_EN_HO BIT(8)
858#define PHY_SSC_RSTB BIT(9)
859#define SEC_CLK_EN BIT(10)
860#define MAC_CLK_EN BIT(11)
861#define SYS_CLK_EN BIT(12)
862#define RING_CLK_EN BIT(13)
863
864#define BOOT_FROM_EEPROM BIT(4)
865#define EEPROM_EN BIT(5)
866
867#define AFE_BGEN BIT(0)
868#define AFE_MBEN BIT(1)
869#define MAC_ID_EN BIT(7)
870
871#define WLOCK_ALL BIT(0)
872#define WLOCK_00 BIT(1)
873#define WLOCK_04 BIT(2)
874#define WLOCK_08 BIT(3)
875#define WLOCK_40 BIT(4)
876#define R_DIS_PRST_0 BIT(5)
877#define R_DIS_PRST_1 BIT(6)
878#define LOCK_ALL_EN BIT(7)
879
880#define RF_EN BIT(0)
881#define RF_RSTB BIT(1)
882#define RF_SDMRSTB BIT(2)
883
884#define LDA15_EN BIT(0)
885#define LDA15_STBY BIT(1)
886#define LDA15_OBUF BIT(2)
887#define LDA15_REG_VOS BIT(3)
888#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
889
890#define LDV12_EN BIT(0)
891#define LDV12_SDBY BIT(1)
892#define LPLDO_HSM BIT(2)
893#define LPLDO_LSM_DIS BIT(3)
894#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
895
896#define XTAL_EN BIT(0)
897#define XTAL_BSEL BIT(1)
898#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
899#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
900#define XTAL_GATE_USB BIT(8)
901#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
902#define XTAL_GATE_AFE BIT(11)
903#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
904#define XTAL_RF_GATE BIT(14)
905#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
906#define XTAL_GATE_DIG BIT(17)
907#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
908#define XTAL_BT_GATE BIT(20)
909#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
910#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
911
912#define CKDLY_AFE BIT(26)
913#define CKDLY_USB BIT(27)
914#define CKDLY_DIG BIT(28)
915#define CKDLY_BT BIT(29)
916
917#define APLL_EN BIT(0)
918#define APLL_320_EN BIT(1)
919#define APLL_FREF_SEL BIT(2)
920#define APLL_EDGE_SEL BIT(3)
921#define APLL_WDOGB BIT(4)
922#define APLL_LPFEN BIT(5)
923
924#define APLL_REF_CLK_13MHZ 0x1
925#define APLL_REF_CLK_19_2MHZ 0x2
926#define APLL_REF_CLK_20MHZ 0x3
927#define APLL_REF_CLK_25MHZ 0x4
928#define APLL_REF_CLK_26MHZ 0x5
929#define APLL_REF_CLK_38_4MHZ 0x6
930#define APLL_REF_CLK_40MHZ 0x7
931
932#define APLL_320EN BIT(14)
933#define APLL_80EN BIT(15)
934#define APLL_1MEN BIT(24)
935
936#define ALD_EN BIT(18)
937#define EF_PD BIT(19)
938#define EF_FLAG BIT(31)
939
940#define EF_TRPT BIT(7)
941#define LDOE25_EN BIT(31)
942
943#define RSM_EN BIT(0)
944#define TIMER_EN BIT(4)
945
946#define TRSW0EN BIT(2)
947#define TRSW1EN BIT(3)
948#define EROM_EN BIT(4)
949#define ENBT BIT(5)
950#define ENUART BIT(8)
951#define UART_910 BIT(9)
952#define ENPMAC BIT(10)
953#define SIC_SWRST BIT(11)
954#define ENSIC BIT(12)
955#define SIC_23 BIT(13)
956#define ENHDP BIT(14)
957#define SIC_LBK BIT(15)
958
959#define LED0PL BIT(4)
960#define LED1PL BIT(12)
961#define LED0DIS BIT(7)
962
963#define MCUFWDL_EN BIT(0)
964#define MCUFWDL_RDY BIT(1)
965#define FWDL_CHKSUM_RPT BIT(2)
966#define MACINI_RDY BIT(3)
967#define BBINI_RDY BIT(4)
968#define RFINI_RDY BIT(5)
969#define WINTINI_RDY BIT(6)
970#define CPRST BIT(23)
971
972#define XCLK_VLD BIT(0)
973#define ACLK_VLD BIT(1)
974#define UCLK_VLD BIT(2)
975#define PCLK_VLD BIT(3)
976#define PCIRSTB BIT(4)
977#define V15_VLD BIT(5)
978#define TRP_B15V_EN BIT(7)
979#define SIC_IDLE BIT(8)
980#define BD_MAC2 BIT(9)
981#define BD_MAC1 BIT(10)
982#define IC_MACPHY_MODE BIT(11)
983#define VENDOR_ID BIT(19)
984#define PAD_HWPD_IDN BIT(22)
985#define TRP_VAUX_EN BIT(23)
986#define TRP_BT_EN BIT(24)
987#define BD_PKG_SEL BIT(25)
988#define BD_HCI_SEL BIT(26)
989#define TYPE_ID BIT(27)
990
991#define CHIP_VER_RTL_MASK 0xF000
992#define CHIP_VER_RTL_SHIFT 12
993
994#define REG_LBMODE (REG_CR + 3)
995
996#define HCI_TXDMA_EN BIT(0)
997#define HCI_RXDMA_EN BIT(1)
998#define TXDMA_EN BIT(2)
999#define RXDMA_EN BIT(3)
1000#define PROTOCOL_EN BIT(4)
1001#define SCHEDULE_EN BIT(5)
1002#define MACTXEN BIT(6)
1003#define MACRXEN BIT(7)
1004#define ENSWBCN BIT(8)
1005#define ENSEC BIT(9)
1006
1007#define _NETTYPE(x) (((x) & 0x3) << 16)
1008#define MASK_NETTYPE 0x30000
1009#define NT_NO_LINK 0x0
1010#define NT_LINK_AD_HOC 0x1
1011#define NT_LINK_AP 0x2
1012#define NT_AS_AP 0x3
1013
1014#define _LBMODE(x) (((x) & 0xF) << 24)
1015#define MASK_LBMODE 0xF000000
1016#define LOOPBACK_NORMAL 0x0
1017#define LOOPBACK_IMMEDIATELY 0xB
1018#define LOOPBACK_MAC_DELAY 0x3
1019#define LOOPBACK_PHY 0x1
1020#define LOOPBACK_DMA 0x7
1021
1022#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
1023#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
1024#define _PSRX_MASK 0xF
1025#define _PSTX_MASK 0xF0
1026#define _PSRX(x) (x)
1027#define _PSTX(x) ((x) << 4)
1028
1029#define PBP_64 0x0
1030#define PBP_128 0x1
1031#define PBP_256 0x2
1032#define PBP_512 0x3
1033#define PBP_1024 0x4
1034
1035#define RXDMA_ARBBW_EN BIT(0)
1036#define RXSHFT_EN BIT(1)
1037#define RXDMA_AGG_EN BIT(2)
1038#define QS_VO_QUEUE BIT(8)
1039#define QS_VI_QUEUE BIT(9)
1040#define QS_BE_QUEUE BIT(10)
1041#define QS_BK_QUEUE BIT(11)
1042#define QS_MANAGER_QUEUE BIT(12)
1043#define QS_HIGH_QUEUE BIT(13)
1044
1045#define HQSEL_VOQ BIT(0)
1046#define HQSEL_VIQ BIT(1)
1047#define HQSEL_BEQ BIT(2)
1048#define HQSEL_BKQ BIT(3)
1049#define HQSEL_MGTQ BIT(4)
1050#define HQSEL_HIQ BIT(5)
1051
1052#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
1053#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
1054#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
1055#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
1056#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
1057#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
1058
1059#define QUEUE_LOW 1
1060#define QUEUE_NORMAL 2
1061#define QUEUE_HIGH 3
1062
1063#define _LLT_NO_ACTIVE 0x0
1064#define _LLT_WRITE_ACCESS 0x1
1065#define _LLT_READ_ACCESS 0x2
1066
1067#define _LLT_INIT_DATA(x) ((x) & 0xFF)
1068#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
1069#define _LLT_OP(x) (((x) & 0x3) << 30)
1070#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
1071
1072#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
1073#define BB_WRITE_EN BIT(30)
1074#define BB_READ_EN BIT(31)
1075
1076#define _HPQ(x) ((x) & 0xFF)
1077#define _LPQ(x) (((x) & 0xFF) << 8)
1078#define _PUBQ(x) (((x) & 0xFF) << 16)
1079#define _NPQ(x) ((x) & 0xFF)
1080
1081#define HPQ_PUBLIC_DIS BIT(24)
1082#define LPQ_PUBLIC_DIS BIT(25)
1083#define LD_RQPN BIT(31)
1084
1085#define BCN_VALID BIT(16)
1086#define BCN_HEAD(x) (((x) & 0xFF) << 8)
1087#define BCN_HEAD_MASK 0xFF00
1088
1089#define BLK_DESC_NUM_SHIFT 4
1090#define BLK_DESC_NUM_MASK 0xF
1091
1092#define DROP_DATA_EN BIT(9)
1093
1094#define EN_AMPDU_RTY_NEW BIT(7)
1095
1096#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1097
1098#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1099#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1100
1101#define RATE_REG_BITMAP_ALL 0xFFFFF
1102
1103#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1104
1105#define _RRSR_RSC(x) (((x) & 0x3) << 21)
1106#define RRSR_RSC_RESERVED 0x0
1107#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1108#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1109#define RRSR_RSC_DUPLICATE_MODE 0x3
1110
1111#define USE_SHORT_G1 BIT(20)
1112
1113#define _AGGLMT_MCS0(x) ((x) & 0xF)
1114#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1115#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1116#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1117#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1118#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1119#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1120#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1121
1122#define RETRY_LIMIT_SHORT_SHIFT 8
1123#define RETRY_LIMIT_LONG_SHIFT 0
1124
1125#define _DARF_RC1(x) ((x) & 0x1F)
1126#define _DARF_RC2(x) (((x) & 0x1F) << 8)
1127#define _DARF_RC3(x) (((x) & 0x1F) << 16)
1128#define _DARF_RC4(x) (((x) & 0x1F) << 24)
1129#define _DARF_RC5(x) ((x) & 0x1F)
1130#define _DARF_RC6(x) (((x) & 0x1F) << 8)
1131#define _DARF_RC7(x) (((x) & 0x1F) << 16)
1132#define _DARF_RC8(x) (((x) & 0x1F) << 24)
1133
1134#define _RARF_RC1(x) ((x) & 0x1F)
1135#define _RARF_RC2(x) (((x) & 0x1F) << 8)
1136#define _RARF_RC3(x) (((x) & 0x1F) << 16)
1137#define _RARF_RC4(x) (((x) & 0x1F) << 24)
1138#define _RARF_RC5(x) ((x) & 0x1F)
1139#define _RARF_RC6(x) (((x) & 0x1F) << 8)
1140#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1141#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1142
1143#define AC_PARAM_TXOP_LIMIT_OFFSET 16
1144#define AC_PARAM_ECW_MAX_OFFSET 12
1145#define AC_PARAM_ECW_MIN_OFFSET 8
1146#define AC_PARAM_AIFS_OFFSET 0
1147
1148#define _AIFS(x) (x)
1149#define _ECW_MAX_MIN(x) ((x) << 8)
1150#define _TXOP_LIMIT(x) ((x) << 16)
1151
1152#define _BCNIFS(x) ((x) & 0xFF)
1153#define _BCNECW(x) ((((x) & 0xF)) << 8)
1154
1155#define _LRL(x) ((x) & 0x3F)
1156#define _SRL(x) (((x) & 0x3F) << 8)
1157
1158#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1159#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)
1160
1161#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1162#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)
1163
1164#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1165
1166#define DIS_EDCA_CNT_DWN BIT(11)
1167
1168#define EN_MBSSID BIT(1)
1169#define EN_TXBCN_RPT BIT(2)
1170#define EN_BCN_FUNCTION BIT(3)
1171
1172#define TSFTR_RST BIT(0)
1173#define TSFTR1_RST BIT(1)
1174
1175#define STOP_BCNQ BIT(6)
1176
1177#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1178#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1179
1180#define ACMHW_HWEN BIT(0)
1181#define ACMHW_BEQEN BIT(1)
1182#define ACMHW_VIQEN BIT(2)
1183#define ACMHW_VOQEN BIT(3)
1184#define ACMHW_BEQSTATUS BIT(4)
1185#define ACMHW_VIQSTATUS BIT(5)
1186#define ACMHW_VOQSTATUS BIT(6)
1187
1188#define APSDOFF BIT(6)
1189#define APSDOFF_STATUS BIT(7)
1190
1191#define BW_20MHZ BIT(2)
1192
1193#define RATE_BITMAP_ALL 0xFFFFF
1194
1195#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1196
1197#define TSFRST BIT(0)
1198#define DIS_GCLK BIT(1)
1199#define PAD_SEL BIT(2)
1200#define PWR_ST BIT(6)
1201#define PWRBIT_OW_EN BIT(7)
1202#define ACRC BIT(8)
1203#define CFENDFORM BIT(9)
1204#define ICV BIT(10)
1205
1206#define AAP BIT(0)
1207#define APM BIT(1)
1208#define AM BIT(2)
1209#define AB BIT(3)
1210#define ADD3 BIT(4)
1211#define APWRMGT BIT(5)
1212#define CBSSID BIT(6)
1213#define CBSSID_DATA BIT(6)
1214#define CBSSID_BCN BIT(7)
1215#define ACRC32 BIT(8)
1216#define AICV BIT(9)
1217#define ADF BIT(11)
1218#define ACF BIT(12)
1219#define AMF BIT(13)
1220#define HTC_LOC_CTRL BIT(14)
1221#define UC_DATA_EN BIT(16)
1222#define BM_DATA_EN BIT(17)
1223#define MFBEN BIT(22)
1224#define LSIGEN BIT(23)
1225#define ENMBID BIT(24)
1226#define APP_BASSN BIT(27)
1227#define APP_PHYSTS BIT(28)
1228#define APP_ICV BIT(29)
1229#define APP_MIC BIT(30)
1230#define APP_FCS BIT(31)
1231
1232#define _MIN_SPACE(x) ((x) & 0x7)
1233#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1234
1235#define RXERR_TYPE_OFDM_PPDU 0
1236#define RXERR_TYPE_OFDM_FALSE_ALARM 1
1237#define RXERR_TYPE_OFDM_MPDU_OK 2
1238#define RXERR_TYPE_OFDM_MPDU_FAIL 3
1239#define RXERR_TYPE_CCK_PPDU 4
1240#define RXERR_TYPE_CCK_FALSE_ALARM 5
1241#define RXERR_TYPE_CCK_MPDU_OK 6
1242#define RXERR_TYPE_CCK_MPDU_FAIL 7
1243#define RXERR_TYPE_HT_PPDU 8
1244#define RXERR_TYPE_HT_FALSE_ALARM 9
1245#define RXERR_TYPE_HT_MPDU_TOTAL 10
1246#define RXERR_TYPE_HT_MPDU_OK 11
1247#define RXERR_TYPE_HT_MPDU_FAIL 12
1248#define RXERR_TYPE_RX_FULL_DROP 15
1249
1250#define RXERR_COUNTER_MASK 0xFFFFF
1251#define RXERR_RPT_RST BIT(27)
1252#define _RXERR_RPT_SEL(type) ((type) << 28)
1253
1254#define SCR_TXUSEDK BIT(0)
1255#define SCR_RXUSEDK BIT(1)
1256#define SCR_TXENCENABLE BIT(2)
1257#define SCR_RXDECENABLE BIT(3)
1258#define SCR_SKBYA2 BIT(4)
1259#define SCR_NOSKMC BIT(5)
1260#define SCR_TXBCUSEDK BIT(6)
1261#define SCR_RXBCUSEDK BIT(7)
1262
1263#define XCLK_VLD BIT(0)
1264#define ACLK_VLD BIT(1)
1265#define UCLK_VLD BIT(2)
1266#define PCLK_VLD BIT(3)
1267#define PCIRSTB BIT(4)
1268#define V15_VLD BIT(5)
1269#define TRP_B15V_EN BIT(7)
1270#define SIC_IDLE BIT(8)
1271#define BD_MAC2 BIT(9)
1272#define BD_MAC1 BIT(10)
1273#define IC_MACPHY_MODE BIT(11)
1274#define BT_FUNC BIT(16)
1275#define VENDOR_ID BIT(19)
1276#define PAD_HWPD_IDN BIT(22)
1277#define TRP_VAUX_EN BIT(23)
1278#define TRP_BT_EN BIT(24)
1279#define BD_PKG_SEL BIT(25)
1280#define BD_HCI_SEL BIT(26)
1281#define TYPE_ID BIT(27)
1282
1283#define USB_IS_HIGH_SPEED 0
1284#define USB_IS_FULL_SPEED 1
1285#define USB_SPEED_MASK BIT(5)
1286
1287#define USB_NORMAL_SIE_EP_MASK 0xF
1288#define USB_NORMAL_SIE_EP_SHIFT 4
1289
1290#define USB_TEST_EP_MASK 0x30
1291#define USB_TEST_EP_SHIFT 4
1292
1293#define USB_AGG_EN BIT(3)
1294
1295#define MAC_ADDR_LEN 6
1296#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
1297
1298#define POLLING_LLT_THRESHOLD 20
1299#define POLLING_READY_TIMEOUT_COUNT 3000
1300
1301#define MAX_MSS_DENSITY_2T 0x13
1302#define MAX_MSS_DENSITY_1T 0x0A
1303
1304#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
1305#define EPROM_CMD_CONFIG 0x3
1306#define EPROM_CMD_LOAD 1
1307
1308#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1309
1310#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1311
1312#define RA_LSSIWRITE_8821A 0xc90
1313#define RB_LSSIWRITE_8821A 0xe90
1314
1315#define RA_PIREAD_8821A 0xd04
1316#define RB_PIREAD_8821A 0xd44
1317#define RA_SIREAD_8821A 0xd08
1318#define RB_SIREAD_8821A 0xd48
1319
1320#define RPMAC_RESET 0x100
1321#define RPMAC_TXSTART 0x104
1322#define RPMAC_TXLEGACYSIG 0x108
1323#define RPMAC_TXHTSIG1 0x10c
1324#define RPMAC_TXHTSIG2 0x110
1325#define RPMAC_PHYDEBUG 0x114
1326#define RPMAC_TXPACKETNUM 0x118
1327#define RPMAC_TXIDLE 0x11c
1328#define RPMAC_TXMACHEADER0 0x120
1329#define RPMAC_TXMACHEADER1 0x124
1330#define RPMAC_TXMACHEADER2 0x128
1331#define RPMAC_TXMACHEADER3 0x12c
1332#define RPMAC_TXMACHEADER4 0x130
1333#define RPMAC_TXMACHEADER5 0x134
1334#define RPMAC_TXDADATYPE 0x138
1335#define RPMAC_TXRANDOMSEED 0x13c
1336#define RPMAC_CCKPLCPPREAMBLE 0x140
1337#define RPMAC_CCKPLCPHEADER 0x144
1338#define RPMAC_CCKCRC16 0x148
1339#define RPMAC_OFDMRXCRC32OK 0x170
1340#define RPMAC_OFDMRXCRC32ER 0x174
1341#define RPMAC_OFDMRXPARITYER 0x178
1342#define RPMAC_OFDMRXCRC8ER 0x17c
1343#define RPMAC_CCKCRXRC16ER 0x180
1344#define RPMAC_CCKCRXRC32ER 0x184
1345#define RPMAC_CCKCRXRC32OK 0x188
1346#define RPMAC_TXSTATUS 0x18c
1347
1348#define RFPGA0_RFMOD 0x800
1349
1350#define RFPGA0_TXINFO 0x804
1351#define RFPGA0_PSDFUNCTION 0x808
1352
1353#define RFPGA0_TXGAINSTAGE 0x80c
1354
1355#define RFPGA0_RFTIMING1 0x810
1356#define RFPGA0_RFTIMING2 0x814
1357
1358#define RFPGA0_XA_HSSIPARAMETER1 0x820
1359#define RFPGA0_XA_HSSIPARAMETER2 0x824
1360#define RFPGA0_XB_HSSIPARAMETER1 0x828
1361#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1362#define RCCAONSEC 0x838
1363
1364#define RFPGA0_XA_LSSIPARAMETER 0x840
1365#define RFPGA0_XB_LSSIPARAMETER 0x844
1366#define RL1PEAKTH 0x848
1367
1368#define RFPGA0_RFWAKEUPPARAMETER 0x850
1369#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1370
1371#define RFPGA0_XAB_SWITCHCONTROL 0x858
1372#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1373
1374#define RFPGA0_XA_RFINTERFACEOE 0x860
1375#define RFC_AREA 0x860
1376#define RFPGA0_XB_RFINTERFACEOE 0x864
1377
1378#define RFPGA0_XAB_RFINTERFACESW 0x870
1379#define RFPGA0_XCD_RFINTERFACESW 0x874
1380
1381#define RFPGA0_XAB_RFPARAMETER 0x878
1382#define RFPGA0_XCD_RFPARAMETER 0x87c
1383
1384#define RFPGA0_ANALOGPARAMETER1 0x880
1385#define RFPGA0_ANALOGPARAMETER2 0x884
1386#define RFPGA0_ANALOGPARAMETER3 0x888
1387#define RFPGA0_ANALOGPARAMETER4 0x88c
1388
1389#define RFPGA0_XA_LSSIREADBACK 0x8a0
1390#define RFPGA0_XB_LSSIREADBACK 0x8a4
1391#define RFPGA0_XC_LSSIREADBACK 0x8a8
1392#define RRFMOD 0x8ac
1393#define RHSSIREAD_8821AE 0x8b0
1394
1395#define RFPGA0_PSDREPORT 0x8b4
1396#define TRANSCEIVEA_HSPI_READBACK 0x8b8
1397#define TRANSCEIVEB_HSPI_READBACK 0x8bc
1398#define RADC_BUF_CLK 0x8c4
1399#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1400#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1401
1402#define RFPGA1_RFMOD 0x900
1403
1404#define RFPGA1_TXBLOCK 0x904
1405#define RFPGA1_DEBUGSELECT 0x908
1406#define RFPGA1_TXINFO 0x90c
1407
1408#define RCCK_SYSTEM 0xa00
1409#define BCCK_SYSTEM 0x10
1410
1411#define RCCK0_AFESETTING 0xa04
1412#define RCCK0_CCA 0xa08
1413
1414#define RCCK0_RXAGC1 0xa0c
1415#define RCCK0_RXAGC2 0xa10
1416
1417#define RCCK0_RXHP 0xa14
1418
1419#define RCCK0_DSPPARAMETER1 0xa18
1420#define RCCK0_DSPPARAMETER2 0xa1c
1421
1422#define RCCK0_TXFILTER1 0xa20
1423#define RCCK0_TXFILTER2 0xa24
1424#define RCCK0_DEBUGPORT 0xa28
1425#define RCCK0_FALSEALARMREPORT 0xa2c
1426#define RCCK0_TRSSIREPORT 0xa50
1427#define RCCK0_RXREPORT 0xa54
1428#define RCCK0_FACOUNTERLOWER 0xa5c
1429#define RCCK0_FACOUNTERUPPER 0xa58
1430#define RCCK0_CCA_CNT 0xa60
1431
1432/* PageB(0xB00) */
1433#define RPDP_ANTA 0xb00
1434#define RPDP_ANTA_4 0xb04
1435#define RPDP_ANTA_8 0xb08
1436#define RPDP_ANTA_C 0xb0c
1437#define RPDP_ANTA_10 0xb10
1438#define RPDP_ANTA_14 0xb14
1439#define RPDP_ANTA_18 0xb18
1440#define RPDP_ANTA_1C 0xb1c
1441#define RPDP_ANTA_20 0xb20
1442#define RPDP_ANTA_24 0xb24
1443
1444#define RCONFIG_PMPD_ANTA 0xb28
1445#define RCONFIG_RAM64x16 0xb2c
1446
1447#define RBNDA 0xb30
1448#define RHSSIPAR 0xb34
1449
1450#define RCONFIG_ANTA 0xb68
1451#define RCONFIG_ANTB 0xb6c
1452
1453#define RPDP_ANTB 0xb70
1454#define RPDP_ANTB_4 0xb74
1455#define RPDP_ANTB_8 0xb78
1456#define RPDP_ANTB_C 0xb7c
1457#define RPDP_ANTB_10 0xb80
1458#define RPDP_ANTB_14 0xb84
1459#define RPDP_ANTB_18 0xb88
1460#define RPDP_ANTB_1C 0xb8c
1461#define RPDP_ANTB_20 0xb90
1462#define RPDP_ANTB_24 0xb94
1463
1464#define RCONFIG_PMPD_ANTB 0xb98
1465
1466#define RBNDB 0xba0
1467
1468#define RAPK 0xbd8
1469#define RPM_RX0_ANTA 0xbdc
1470#define RPM_RX1_ANTA 0xbe0
1471#define RPM_RX2_ANTA 0xbe4
1472#define RPM_RX3_ANTA 0xbe8
1473#define RPM_RX0_ANTB 0xbec
1474#define RPM_RX1_ANTB 0xbf0
1475#define RPM_RX2_ANTB 0xbf4
1476#define RPM_RX3_ANTB 0xbf8
1477
1478/*RSSI Dump*/
1479#define RA_RSSI_DUMP 0xBF0
1480#define RB_RSSI_DUMP 0xBF1
1481#define RS1_RX_EVM_DUMP 0xBF4
1482#define RS2_RX_EVM_DUMP 0xBF5
1483#define RA_RX_SNR_DUMP 0xBF6
1484#define RB_RX_SNR_DUMP 0xBF7
1485#define RA_CFO_SHORT_DUMP 0xBF8
1486#define RB_CFO_SHORT_DUMP 0xBFA
1487#define RA_CFO_LONG_DUMP 0xBEC
1488#define RB_CFO_LONG_DUMP 0xBEE
1489
1490/*Page C*/
1491#define ROFDM0_LSTF 0xc00
1492
1493#define ROFDM0_TRXPATHENABLE 0xc04
1494#define ROFDM0_TRMUXPAR 0xc08
1495#define ROFDM0_TRSWISOLATION 0xc0c
1496
1497#define ROFDM0_XARXAFE 0xc10
1498#define ROFDM0_XARXIQIMBALANCE 0xc14
1499#define ROFDM0_XBRXAFE 0xc18
1500#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1501#define ROFDM0_XCRXAFE 0xc20
1502#define ROFDM0_XCRXIQIMBANLANCE 0xc24
1503#define ROFDM0_XDRXAFE 0xc28
1504#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1505
1506#define ROFDM0_RXDETECTOR1 0xc30
1507#define ROFDM0_RXDETECTOR2 0xc34
1508#define ROFDM0_RXDETECTOR3 0xc38
1509#define ROFDM0_RXDETECTOR4 0xc3c
1510
1511#define ROFDM0_RXDSP 0xc40
1512#define ROFDM0_CFOANDDAGC 0xc44
1513#define ROFDM0_CCADROPTHRESHOLD 0xc48
1514#define ROFDM0_ECCATHRESHOLD 0xc4c
1515
1516#define ROFDM0_XAAGCCORE1 0xc50
1517#define ROFDM0_XAAGCCORE2 0xc54
1518#define ROFDM0_XBAGCCORE1 0xc58
1519#define ROFDM0_XBAGCCORE2 0xc5c
1520#define ROFDM0_XCAGCCORE1 0xc60
1521#define ROFDM0_XCAGCCORE2 0xc64
1522#define ROFDM0_XDAGCCORE1 0xc68
1523#define ROFDM0_XDAGCCORE2 0xc6c
1524
1525#define ROFDM0_AGCPARAMETER1 0xc70
1526#define ROFDM0_AGCPARAMETER2 0xc74
1527#define ROFDM0_AGCRSSITABLE 0xc78
1528#define ROFDM0_HTSTFAGC 0xc7c
1529
1530#define ROFDM0_XATXIQIMBALANCE 0xc80
1531#define ROFDM0_XATXAFE 0xc84
1532#define ROFDM0_XBTXIQIMBALANCE 0xc88
1533#define ROFDM0_XBTXAFE 0xc8c
1534#define ROFDM0_XCTXIQIMBALANCE 0xc90
1535#define ROFDM0_XCTXAFE 0xc94
1536#define ROFDM0_XDTXIQIMBALANCE 0xc98
1537#define ROFDM0_XDTXAFE 0xc9c
1538
1539#define ROFDM0_RXIQEXTANTA 0xca0
1540#define ROFDM0_TXCOEFF1 0xca4
1541#define ROFDM0_TXCOEFF2 0xca8
1542#define ROFDM0_TXCOEFF3 0xcac
1543#define ROFDM0_TXCOEFF4 0xcb0
1544#define ROFDM0_TXCOEFF5 0xcb4
1545#define ROFDM0_TXCOEFF6 0xcb8
1546
1547/*Path_A RFE cotrol */
1548#define RA_RFE_CTRL_8812 0xcb8
1549/*Path_B RFE control*/
1550#define RB_RFE_CTRL_8812 0xeb8
1551
1552#define ROFDM0_RXHPPARAMETER 0xce0
1553#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1554#define ROFDM0_FRAMESYNC 0xcf0
1555#define ROFDM0_DFSREPORT 0xcf4
1556
1557#define ROFDM1_LSTF 0xd00
1558#define ROFDM1_TRXPATHENABLE 0xd04
1559
1560#define ROFDM1_CF0 0xd08
1561#define ROFDM1_CSI1 0xd10
1562#define ROFDM1_SBD 0xd14
1563#define ROFDM1_CSI2 0xd18
1564#define ROFDM1_CFOTRACKING 0xd2c
1565#define ROFDM1_TRXMESAURE1 0xd34
1566#define ROFDM1_INTFDET 0xd3c
1567#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1568#define ROFDM1_PSEUDONOISESTATECD 0xd54
1569#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1570
1571#define ROFDM_PHYCOUNTER1 0xda0
1572#define ROFDM_PHYCOUNTER2 0xda4
1573#define ROFDM_PHYCOUNTER3 0xda8
1574
1575#define ROFDM_SHORTCFOAB 0xdac
1576#define ROFDM_SHORTCFOCD 0xdb0
1577#define ROFDM_LONGCFOAB 0xdb4
1578#define ROFDM_LONGCFOCD 0xdb8
1579#define ROFDM_TAILCF0AB 0xdbc
1580#define ROFDM_TAILCF0CD 0xdc0
1581#define ROFDM_PWMEASURE1 0xdc4
1582#define ROFDM_PWMEASURE2 0xdc8
1583#define ROFDM_BWREPORT 0xdcc
1584#define ROFDM_AGCREPORT 0xdd0
1585#define ROFDM_RXSNR 0xdd4
1586#define ROFDM_RXEVMCSI 0xdd8
1587#define ROFDM_SIGREPORT 0xddc
1588
1589#define RTXAGC_A_CCK11_CCK1 0xc20
1590#define RTXAGC_A_OFDM18_OFDM6 0xc24
1591#define RTXAGC_A_OFDM54_OFDM24 0xc28
1592#define RTXAGC_A_MCS03_MCS00 0xc2c
1593#define RTXAGC_A_MCS07_MCS04 0xc30
1594#define RTXAGC_A_MCS11_MCS08 0xc34
1595#define RTXAGC_A_MCS15_MCS12 0xc38
1596#define RTXAGC_A_NSS1INDEX3_NSS1INDEX0 0xc3c
1597#define RTXAGC_A_NSS1INDEX7_NSS1INDEX4 0xc40
1598#define RTXAGC_A_NSS2INDEX1_NSS1INDEX8 0xc44
1599#define RTXAGC_A_NSS2INDEX5_NSS2INDEX2 0xc48
1600#define RTXAGC_A_NSS2INDEX9_NSS2INDEX6 0xc4c
1601#define RTXAGC_B_CCK11_CCK1 0xe20
1602#define RTXAGC_B_OFDM18_OFDM6 0xe24
1603#define RTXAGC_B_OFDM54_OFDM24 0xe28
1604#define RTXAGC_B_MCS03_MCS00 0xe2c
1605#define RTXAGC_B_MCS07_MCS04 0xe30
1606#define RTXAGC_B_MCS11_MCS08 0xe34
1607#define RTXAGC_B_MCS15_MCS12 0xe38
1608#define RTXAGC_B_NSS1INDEX3_NSS1INDEX0 0xe3c
1609#define RTXAGC_B_NSS1INDEX7_NSS1INDEX4 0xe40
1610#define RTXAGC_B_NSS2INDEX1_NSS1INDEX8 0xe44
1611#define RTXAGC_B_NSS2INDEX5_NSS2INDEX2 0xe48
1612#define RTXAGC_B_NSS2INDEX9_NSS2INDEX6 0xe4c
1613
1614#define RA_TXPWRTRAING 0xc54
1615#define RB_TXPWRTRAING 0xe54
1616
1617#define RFPGA0_IQK 0xe28
1618#define RTX_IQK_TONE_A 0xe30
1619#define RRX_IQK_TONE_A 0xe34
1620#define RTX_IQK_PI_A 0xe38
1621#define RRX_IQK_PI_A 0xe3c
1622
1623#define RTX_IQK 0xe40
1624#define RRX_IQK 0xe44
1625#define RIQK_AGC_PTS 0xe48
1626#define RIQK_AGC_RSP 0xe4c
1627#define RTX_IQK_TONE_B 0xe50
1628#define RRX_IQK_TONE_B 0xe54
1629#define RTX_IQK_PI_B 0xe58
1630#define RRX_IQK_PI_B 0xe5c
1631#define RIQK_AGC_CONT 0xe60
1632
1633#define RBLUE_TOOTH 0xe6c
1634#define RRX_WAIT_CCA 0xe70
1635#define RTX_CCK_RFON 0xe74
1636#define RTX_CCK_BBON 0xe78
1637#define RTX_OFDM_RFON 0xe7c
1638#define RTX_OFDM_BBON 0xe80
1639#define RTX_TO_RX 0xe84
1640#define RTX_TO_TX 0xe88
1641#define RRX_CCK 0xe8c
1642
1643#define RTX_POWER_BEFORE_IQK_A 0xe94
1644#define RTX_POWER_AFTER_IQK_A 0xe9c
1645
1646#define RRX_POWER_BEFORE_IQK_A 0xea0
1647#define RRX_POWER_BEFORE_IQK_A_2 0xea4
1648#define RRX_POWER_AFTER_IQK_A 0xea8
1649#define RRX_POWER_AFTER_IQK_A_2 0xeac
1650
1651#define RTX_POWER_BEFORE_IQK_B 0xeb4
1652#define RTX_POWER_AFTER_IQK_B 0xebc
1653
1654#define RRX_POER_BEFORE_IQK_B 0xec0
1655#define RRX_POER_BEFORE_IQK_B_2 0xec4
1656#define RRX_POWER_AFTER_IQK_B 0xec8
1657#define RRX_POWER_AFTER_IQK_B_2 0xecc
1658
1659#define RRX_OFDM 0xed0
1660#define RRX_WAIT_RIFS 0xed4
1661#define RRX_TO_RX 0xed8
1662#define RSTANDBY 0xedc
1663#define RSLEEP 0xee0
1664#define RPMPD_ANAEN 0xeec
1665
1666#define RZEBRA1_HSSIENABLE 0x0
1667#define RZEBRA1_TRXENABLE1 0x1
1668#define RZEBRA1_TRXENABLE2 0x2
1669#define RZEBRA1_AGC 0x4
1670#define RZEBRA1_CHARGEPUMP 0x5
1671#define RZEBRA1_CHANNEL 0x7
1672
1673#define RZEBRA1_TXGAIN 0x8
1674#define RZEBRA1_TXLPF 0x9
1675#define RZEBRA1_RXLPF 0xb
1676#define RZEBRA1_RXHPFCORNER 0xc
1677
1678#define RGLOBALCTRL 0
1679#define RRTL8256_TXLPF 19
1680#define RRTL8256_RXLPF 11
1681#define RRTL8258_TXLPF 0x11
1682#define RRTL8258_RXLPF 0x13
1683#define RRTL8258_RSSILPF 0xa
1684
1685#define RF_AC 0x00
1686
1687#define RF_IQADJ_G1 0x01
1688#define RF_IQADJ_G2 0x02
1689#define RF_POW_TRSW 0x05
1690
1691#define RF_GAIN_RX 0x06
1692#define RF_GAIN_TX 0x07
1693
1694#define RF_TXM_IDAC 0x08
1695#define RF_BS_IQGEN 0x0F
1696
1697#define RF_MODE1 0x10
1698#define RF_MODE2 0x11
1699
1700#define RF_RX_AGC_HP 0x12
1701#define RF_TX_AGC 0x13
1702#define RF_BIAS 0x14
1703#define RF_IPA 0x15
1704#define RF_POW_ABILITY 0x17
1705#define RF_MODE_AG 0x18
1706#define RRFCHANNEL 0x18
1707#define RF_CHNLBW 0x18
1708#define RF_TOP 0x19
1709
1710#define RF_RX_G1 0x1A
1711#define RF_RX_G2 0x1B
1712
1713#define RF_RX_BB2 0x1C
1714#define RF_RX_BB1 0x1D
1715
1716#define RF_RCK1 0x1E
1717#define RF_RCK2 0x1F
1718
1719#define RF_TX_G1 0x20
1720#define RF_TX_G2 0x21
1721#define RF_TX_G3 0x22
1722
1723#define RF_TX_BB1 0x23
1724#define RF_T_METER 0x24
1725#define RF_T_METER_88E 0x42
1726#define RF_T_METER_8812A 0x42
1727
1728#define RF_SYN_G1 0x25
1729#define RF_SYN_G2 0x26
1730#define RF_SYN_G3 0x27
1731#define RF_SYN_G4 0x28
1732#define RF_SYN_G5 0x29
1733#define RF_SYN_G6 0x2A
1734#define RF_SYN_G7 0x2B
1735#define RF_SYN_G8 0x2C
1736
1737#define RF_RCK_OS 0x30
1738#define RF_TXPA_G1 0x31
1739#define RF_TXPA_G2 0x32
1740#define RF_TXPA_G3 0x33
1741
1742#define RF_TX_BIAS_A 0x35
1743#define RF_TX_BIAS_D 0x36
1744#define RF_LOBF_9 0x38
1745#define RF_RXRF_A3 0x3C
1746#define RF_TRSW 0x3F
1747
1748#define RF_TXRF_A2 0x41
1749#define RF_TXPA_G4 0x46
1750#define RF_TXPA_A4 0x4B
1751
1752#define RF_APK 0x63
1753
1754#define RF_WE_LUT 0xEF
1755
1756#define BBBRESETB 0x100
1757#define BGLOBALRESETB 0x200
1758#define BOFDMTXSTART 0x4
1759#define BCCKTXSTART 0x8
1760#define BCRC32DEBUG 0x100
1761#define BPMACLOOPBACK 0x10
1762#define BTXLSIG 0xffffff
1763#define BOFDMTXRATE 0xf
1764#define BOFDMTXRESERVED 0x10
1765#define BOFDMTXLENGTH 0x1ffe0
1766#define BOFDMTXPARITY 0x20000
1767#define BTXHTSIG1 0xffffff
1768#define BTXHTMCSRATE 0x7f
1769#define BTXHTBW 0x80
1770#define BTXHTLENGTH 0xffff00
1771#define BTXHTSIG2 0xffffff
1772#define BTXHTSMOOTHING 0x1
1773#define BTXHTSOUNDING 0x2
1774#define BTXHTRESERVED 0x4
1775#define BTXHTAGGREATION 0x8
1776#define BTXHTSTBC 0x30
1777#define BTXHTADVANCECODING 0x40
1778#define BTXHTSHORTGI 0x80
1779#define BTXHTNUMBERHT_LTF 0x300
1780#define BTXHTCRC8 0x3fc00
1781#define BCOUNTERRESET 0x10000
1782#define BNUMOFOFDMTX 0xffff
1783#define BNUMOFCCKTX 0xffff0000
1784#define BTXIDLEINTERVAL 0xffff
1785#define BOFDMSERVICE 0xffff0000
1786#define BTXMACHEADER 0xffffffff
1787#define BTXDATAINIT 0xff
1788#define BTXHTMODE 0x100
1789#define BTXDATATYPE 0x30000
1790#define BTXRANDOMSEED 0xffffffff
1791#define BCCKTXPREAMBLE 0x1
1792#define BCCKTXSFD 0xffff0000
1793#define BCCKTXSIG 0xff
1794#define BCCKTXSERVICE 0xff00
1795#define BCCKLENGTHEXT 0x8000
1796#define BCCKTXLENGHT 0xffff0000
1797#define BCCKTXCRC16 0xffff
1798#define BCCKTXSTATUS 0x1
1799#define BOFDMTXSTATUS 0x2
1800#define IS_BB_REG_OFFSET_92S(__offset) \
1801 ((__offset >= 0x800) && (__offset <= 0xfff))
1802
1803#define BRFMOD 0x1
1804#define BJAPANMODE 0x2
1805#define BCCKTXSC 0x30
1806/* Block & Path enable*/
1807#define ROFDMCCKEN 0x808
1808#define BCCKEN 0x10000000
1809#define BOFDMEN 0x20000000
1810/* Rx antenna*/
1811#define RRXPATH 0x808
1812#define BRXPATH 0xff
1813/* Tx antenna*/
1814#define RTXPATH 0x80c
1815#define BTXPATH 0x0fffffff
1816/* for cck rx path selection*/
1817#define RCCK_RX 0xa04
1818#define BCCK_RX 0x0c000000
1819/* Use LSIG for VHT length*/
1820#define RVHTLEN_USE_LSIG 0x8c3
1821
1822#define BOFDMRXADCPHASE 0x10000
1823#define BOFDMTXDACPHASE 0x40000
1824#define BXATXAGC 0x3f
1825
1826#define BXBTXAGC 0xf00
1827#define BXCTXAGC 0xf000
1828#define BXDTXAGC 0xf0000
1829
1830#define BPASTART 0xf0000000
1831#define BTRSTART 0x00f00000
1832#define BRFSTART 0x0000f000
1833#define BBBSTART 0x000000f0
1834#define BBBCCKSTART 0x0000000f
1835#define BPAEND 0xf
1836#define BTREND 0x0f000000
1837#define BRFEND 0x000f0000
1838#define BCCAMASK 0x000000f0
1839#define BR2RCCAMASK 0x00000f00
1840#define BHSSI_R2TDELAY 0xf8000000
1841#define BHSSI_T2RDELAY 0xf80000
1842#define BCONTXHSSI 0x400
1843#define BIGFROMCCK 0x200
1844#define BAGCADDRESS 0x3f
1845#define BRXHPTX 0x7000
1846#define BRXHP2RX 0x38000
1847#define BRXHPCCKINI 0xc0000
1848#define BAGCTXCODE 0xc00000
1849#define BAGCRXCODE 0x300000
1850
1851#define B3WIREDATALENGTH 0x800
1852#define B3WIREADDREAALENGTH 0x400
1853
1854#define B3WIRERFPOWERDOWN 0x1
1855#define B5GPAPEPOLARITY 0x40000000
1856#define B2GPAPEPOLARITY 0x80000000
1857#define BRFSW_TXDEFAULTANT 0x3
1858#define BRFSW_TXOPTIONANT 0x30
1859#define BRFSW_RXDEFAULTANT 0x300
1860#define BRFSW_RXOPTIONANT 0x3000
1861#define BRFSI_3WIREDATA 0x1
1862#define BRFSI_3WIRECLOCK 0x2
1863#define BRFSI_3WIRELOAD 0x4
1864#define BRFSI_3WIRERW 0x8
1865#define BRFSI_3WIRE 0xf
1866
1867#define BRFSI_RFENV 0x10
1868
1869#define BRFSI_TRSW 0x20
1870#define BRFSI_TRSWB 0x40
1871#define BRFSI_ANTSW 0x100
1872#define BRFSI_ANTSWB 0x200
1873#define BRFSI_PAPE 0x400
1874#define BRFSI_PAPE5G 0x800
1875#define BBANDSELECT 0x1
1876#define BHTSIG2_GI 0x80
1877#define BHTSIG2_SMOOTHING 0x01
1878#define BHTSIG2_SOUNDING 0x02
1879#define BHTSIG2_AGGREATON 0x08
1880#define BHTSIG2_STBC 0x30
1881#define BHTSIG2_ADVCODING 0x40
1882#define BHTSIG2_NUMOFHTLTF 0x300
1883#define BHTSIG2_CRC8 0x3fc
1884#define BHTSIG1_MCS 0x7f
1885#define BHTSIG1_BANDWIDTH 0x80
1886#define BHTSIG1_HTLENGTH 0xffff
1887#define BLSIG_RATE 0xf
1888#define BLSIG_RESERVED 0x10
1889#define BLSIG_LENGTH 0x1fffe
1890#define BLSIG_PARITY 0x20
1891#define BCCKRXPHASE 0x4
1892
1893#define BLSSIREADADDRESS 0x7f800000
1894#define BLSSIREADEDGE 0x80000000
1895
1896#define BLSSIREADBACKDATA 0xfffff
1897
1898#define BLSSIREADOKFLAG 0x1000
1899#define BCCKSAMPLERATE 0x8
1900#define BREGULATOR0STANDBY 0x1
1901#define BREGULATORPLLSTANDBY 0x2
1902#define BREGULATOR1STANDBY 0x4
1903#define BPLLPOWERUP 0x8
1904#define BDPLLPOWERUP 0x10
1905#define BDA10POWERUP 0x20
1906#define BAD7POWERUP 0x200
1907#define BDA6POWERUP 0x2000
1908#define BXTALPOWERUP 0x4000
1909#define B40MDCLKPOWERUP 0x8000
1910#define BDA6DEBUGMODE 0x20000
1911#define BDA6SWING 0x380000
1912
1913#define BADCLKPHASE 0x4000000
1914#define B80MCLKDELAY 0x18000000
1915#define BAFEWATCHDOGENABLE 0x20000000
1916
1917#define BXTALCAP01 0xc0000000
1918#define BXTALCAP23 0x3
1919#define BXTALCAP92X 0x0f000000
1920#define BXTALCAP 0x0f000000
1921
1922#define BINTDIFCLKENABLE 0x400
1923#define BEXTSIGCLKENABLE 0x800
1924#define BBANDGAP_MBIAS_POWERUP 0x10000
1925#define BAD11SH_GAIN 0xc0000
1926#define BAD11NPUT_RANGE 0x700000
1927#define BAD110P_CURRENT 0x3800000
1928#define BLPATH_LOOPBACK 0x4000000
1929#define BQPATH_LOOPBACK 0x8000000
1930#define BAFE_LOOPBACK 0x10000000
1931#define BDA10_SWING 0x7e0
1932#define BDA10_REVERSE 0x800
1933#define BDA_CLK_SOURCE 0x1000
1934#define BDA7INPUT_RANGE 0x6000
1935#define BDA7_GAIN 0x38000
1936#define BDA7OUTPUT_CM_MODE 0x40000
1937#define BDA7INPUT_CM_MODE 0x380000
1938#define BDA7CURRENT 0xc00000
1939#define BREGULATOR_ADJUST 0x7000000
1940#define BAD11POWERUP_ATTX 0x1
1941#define BDA10PS_ATTX 0x10
1942#define BAD11POWERUP_ATRX 0x100
1943#define BDA10PS_ATRX 0x1000
1944#define BCCKRX_AGC_FORMAT 0x200
1945#define BPSDFFT_SAMPLE_POINT 0xc000
1946#define BPSD_AVERAGE_NUM 0x3000
1947#define BIQPATH_CONTROL 0xc00
1948#define BPSD_FREQ 0x3ff
1949#define BPSD_ANTENNA_PATH 0x30
1950#define BPSD_IQ_SWITCH 0x40
1951#define BPSD_RX_TRIGGER 0x400000
1952#define BPSD_TX_TRIGGER 0x80000000
1953#define BPSD_SINE_TONE_SCALE 0x7f000000
1954#define BPSD_REPORT 0xffff
1955
1956#define BOFDM_TXSC 0x30000000
1957#define BCCK_TXON 0x1
1958#define BOFDM_TXON 0x2
1959#define BDEBUG_PAGE 0xfff
1960#define BDEBUG_ITEM 0xff
1961#define BANTL 0x10
1962#define BANT_NONHT 0x100
1963#define BANT_HT1 0x1000
1964#define BANT_HT2 0x10000
1965#define BANT_HT1S1 0x100000
1966#define BANT_NONHTS1 0x1000000
1967
1968#define BCCK_BBMODE 0x3
1969#define BCCK_TXPOWERSAVING 0x80
1970#define BCCK_RXPOWERSAVING 0x40
1971
1972#define BCCK_SIDEBAND 0x10
1973
1974#define BCCK_SCRAMBLE 0x8
1975#define BCCK_ANTDIVERSITY 0x8000
1976#define BCCK_CARRIER_RECOVERY 0x4000
1977#define BCCK_TXRATE 0x3000
1978#define BCCK_DCCANCEL 0x0800
1979#define BCCK_ISICANCEL 0x0400
1980#define BCCK_MATCH_FILTER 0x0200
1981#define BCCK_EQUALIZER 0x0100
1982#define BCCK_PREAMBLE_DETECT 0x800000
1983#define BCCK_FAST_FALSECCA 0x400000
1984#define BCCK_CH_ESTSTART 0x300000
1985#define BCCK_CCA_COUNT 0x080000
1986#define BCCK_CS_LIM 0x070000
1987#define BCCK_BIST_MODE 0x80000000
1988#define BCCK_CCAMASK 0x40000000
1989#define BCCK_TX_DAC_PHASE 0x4
1990#define BCCK_RX_ADC_PHASE 0x20000000
1991#define BCCKR_CP_MODE 0x0100
1992#define BCCK_TXDC_OFFSET 0xf0
1993#define BCCK_RXDC_OFFSET 0xf
1994#define BCCK_CCA_MODE 0xc000
1995#define BCCK_FALSECS_LIM 0x3f00
1996#define BCCK_CS_RATIO 0xc00000
1997#define BCCK_CORGBIT_SEL 0x300000
1998#define BCCK_PD_LIM 0x0f0000
1999#define BCCK_NEWCCA 0x80000000
2000#define BCCK_RXHP_OF_IG 0x8000
2001#define BCCK_RXIG 0x7f00
2002#define BCCK_LNA_POLARITY 0x800000
2003#define BCCK_RX1ST_BAIN 0x7f0000
2004#define BCCK_RF_EXTEND 0x20000000
2005#define BCCK_RXAGC_SATLEVEL 0x1f000000
2006#define BCCK_RXAGC_SATCOUNT 0xe0
2007#define BCCKRXRFSETTLE 0x1f
2008#define BCCK_FIXED_RXAGC 0x8000
2009#define BCCK_ANTENNA_POLARITY 0x2000
2010#define BCCK_TXFILTER_TYPE 0x0c00
2011#define BCCK_RXAGC_REPORTTYPE 0x0300
2012#define BCCK_RXDAGC_EN 0x80000000
2013#define BCCK_RXDAGC_PERIOD 0x20000000
2014#define BCCK_RXDAGC_SATLEVEL 0x1f000000
2015#define BCCK_TIMING_RECOVERY 0x800000
2016#define BCCK_TXC0 0x3f0000
2017#define BCCK_TXC1 0x3f000000
2018#define BCCK_TXC2 0x3f
2019#define BCCK_TXC3 0x3f00
2020#define BCCK_TXC4 0x3f0000
2021#define BCCK_TXC5 0x3f000000
2022#define BCCK_TXC6 0x3f
2023#define BCCK_TXC7 0x3f00
2024#define BCCK_DEBUGPORT 0xff0000
2025#define BCCK_DAC_DEBUG 0x0f000000
2026#define BCCK_FALSEALARM_ENABLE 0x8000
2027#define BCCK_FALSEALARM_READ 0x4000
2028#define BCCK_TRSSI 0x7f
2029#define BCCK_RXAGC_REPORT 0xfe
2030#define BCCK_RXREPORT_ANTSEL 0x80000000
2031#define BCCK_RXREPORT_MFOFF 0x40000000
2032#define BCCK_RXREPORT_SQLOSS 0x20000000
2033#define BCCK_RXREPORT_PKTLOSS 0x10000000
2034#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
2035#define BCCK_RXREPORT_RATEERROR 0x04000000
2036#define BCCK_RXREPORT_RXRATE 0x03000000
2037#define BCCK_RXFA_COUNTER_LOWER 0xff
2038#define BCCK_RXFA_COUNTER_UPPER 0xff000000
2039#define BCCK_RXHPAGC_START 0xe000
2040#define BCCK_RXHPAGC_FINAL 0x1c00
2041#define BCCK_RXFALSEALARM_ENABLE 0x8000
2042#define BCCK_FACOUNTER_FREEZE 0x4000
2043#define BCCK_TXPATH_SEL 0x10000000
2044#define BCCK_DEFAULT_RXPATH 0xc000000
2045#define BCCK_OPTION_RXPATH 0x3000000
2046
2047#define BNUM_OFSTF 0x3
2048#define BSHIFT_L 0xc0
2049#define BGI_TH 0xc
2050#define BRXPATH_A 0x1
2051#define BRXPATH_B 0x2
2052#define BRXPATH_C 0x4
2053#define BRXPATH_D 0x8
2054#define BTXPATH_A 0x1
2055#define BTXPATH_B 0x2
2056#define BTXPATH_C 0x4
2057#define BTXPATH_D 0x8
2058#define BTRSSI_FREQ 0x200
2059#define BADC_BACKOFF 0x3000
2060#define BDFIR_BACKOFF 0xc000
2061#define BTRSSI_LATCH_PHASE 0x10000
2062#define BRX_LDC_OFFSET 0xff
2063#define BRX_QDC_OFFSET 0xff00
2064#define BRX_DFIR_MODE 0x1800000
2065#define BRX_DCNF_TYPE 0xe000000
2066#define BRXIQIMB_A 0x3ff
2067#define BRXIQIMB_B 0xfc00
2068#define BRXIQIMB_C 0x3f0000
2069#define BRXIQIMB_D 0xffc00000
2070#define BDC_DC_NOTCH 0x60000
2071#define BRXNB_NOTCH 0x1f000000
2072#define BPD_TH 0xf
2073#define BPD_TH_OPT2 0xc000
2074#define BPWED_TH 0x700
2075#define BIFMF_WIN_L 0x800
2076#define BPD_OPTION 0x1000
2077#define BMF_WIN_L 0xe000
2078#define BBW_SEARCH_L 0x30000
2079#define BWIN_ENH_L 0xc0000
2080#define BBW_TH 0x700000
2081#define BED_TH2 0x3800000
2082#define BBW_OPTION 0x4000000
2083#define BRADIO_TH 0x18000000
2084#define BWINDOW_L 0xe0000000
2085#define BSBD_OPTION 0x1
2086#define BFRAME_TH 0x1c
2087#define BFS_OPTION 0x60
2088#define BDC_SLOPE_CHECK 0x80
2089#define BFGUARD_COUNTER_DC_L 0xe00
2090#define BFRAME_WEIGHT_SHORT 0x7000
2091#define BSUB_TUNE 0xe00000
2092#define BFRAME_DC_LENGTH 0xe000000
2093#define BSBD_START_OFFSET 0x30000000
2094#define BFRAME_TH_2 0x7
2095#define BFRAME_GI2_TH 0x38
2096#define BGI2_SYNC_EN 0x40
2097#define BSARCH_SHORT_EARLY 0x300
2098#define BSARCH_SHORT_LATE 0xc00
2099#define BSARCH_GI2_LATE 0x70000
2100#define BCFOANTSUM 0x1
2101#define BCFOACC 0x2
2102#define BCFOSTARTOFFSET 0xc
2103#define BCFOLOOPBACK 0x70
2104#define BCFOSUMWEIGHT 0x80
2105#define BDAGCENABLE 0x10000
2106#define BTXIQIMB_A 0x3ff
2107#define BTXIQIMB_b 0xfc00
2108#define BTXIQIMB_C 0x3f0000
2109#define BTXIQIMB_D 0xffc00000
2110#define BTXIDCOFFSET 0xff
2111#define BTXIQDCOFFSET 0xff00
2112#define BTXDFIRMODE 0x10000
2113#define BTXPESUDO_NOISEON 0x4000000
2114#define BTXPESUDO_NOISE_A 0xff
2115#define BTXPESUDO_NOISE_B 0xff00
2116#define BTXPESUDO_NOISE_C 0xff0000
2117#define BTXPESUDO_NOISE_D 0xff000000
2118#define BCCA_DROPOPTION 0x20000
2119#define BCCA_DROPTHRES 0xfff00000
2120#define BEDCCA_H 0xf
2121#define BEDCCA_L 0xf0
2122#define BLAMBDA_ED 0x300
2123#define BRX_INITIALGAIN 0x7f
2124#define BRX_ANTDIV_EN 0x80
2125#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
2126#define BRX_HIGHPOWER_FLOW 0x8000
2127#define BRX_AGC_FREEZE_THRES 0xc0000
2128#define BRX_FREEZESTEP_AGC1 0x300000
2129#define BRX_FREEZESTEP_AGC2 0xc00000
2130#define BRX_FREEZESTEP_AGC3 0x3000000
2131#define BRX_FREEZESTEP_AGC0 0xc000000
2132#define BRXRSSI_CMP_EN 0x10000000
2133#define BRXQUICK_AGCEN 0x20000000
2134#define BRXAGC_FREEZE_THRES_MODE 0x40000000
2135#define BRX_OVERFLOW_CHECKTYPE 0x80000000
2136#define BRX_AGCSHIFT 0x7f
2137#define BTRSW_TRI_ONLY 0x80
2138#define BPOWER_THRES 0x300
2139#define BRXAGC_EN 0x1
2140#define BRXAGC_TOGETHER_EN 0x2
2141#define BRXAGC_MIN 0x4
2142#define BRXHP_INI 0x7
2143#define BRXHP_TRLNA 0x70
2144#define BRXHP_RSSI 0x700
2145#define BRXHP_BBP1 0x7000
2146#define BRXHP_BBP2 0x70000
2147#define BRXHP_BBP3 0x700000
2148#define BRSSI_H 0x7f0000
2149#define BRSSI_GEN 0x7f000000
2150#define BRXSETTLE_TRSW 0x7
2151#define BRXSETTLE_LNA 0x38
2152#define BRXSETTLE_RSSI 0x1c0
2153#define BRXSETTLE_BBP 0xe00
2154#define BRXSETTLE_RXHP 0x7000
2155#define BRXSETTLE_ANTSW_RSSI 0x38000
2156#define BRXSETTLE_ANTSW 0xc0000
2157#define BRXPROCESS_TIME_DAGC 0x300000
2158#define BRXSETTLE_HSSI 0x400000
2159#define BRXPROCESS_TIME_BBPPW 0x800000
2160#define BRXANTENNA_POWER_SHIFT 0x3000000
2161#define BRSSI_TABLE_SELECT 0xc000000
2162#define BRXHP_FINAL 0x7000000
2163#define BRXHPSETTLE_BBP 0x7
2164#define BRXHTSETTLE_HSSI 0x8
2165#define BRXHTSETTLE_RXHP 0x70
2166#define BRXHTSETTLE_BBPPW 0x80
2167#define BRXHTSETTLE_IDLE 0x300
2168#define BRXHTSETTLE_RESERVED 0x1c00
2169#define BRXHT_RXHP_EN 0x8000
2170#define BRXAGC_FREEZE_THRES 0x30000
2171#define BRXAGC_TOGETHEREN 0x40000
2172#define BRXHTAGC_MIN 0x80000
2173#define BRXHTAGC_EN 0x100000
2174#define BRXHTDAGC_EN 0x200000
2175#define BRXHT_RXHP_BBP 0x1c00000
2176#define BRXHT_RXHP_FINAL 0xe0000000
2177#define BRXPW_RADIO_TH 0x3
2178#define BRXPW_RADIO_EN 0x4
2179#define BRXMF_HOLD 0x3800
2180#define BRXPD_DELAY_TH1 0x38
2181#define BRXPD_DELAY_TH2 0x1c0
2182#define BRXPD_DC_COUNT_MAX 0x600
2183#define BRXPD_DELAY_TH 0x8000
2184#define BRXPROCESS_DELAY 0xf0000
2185#define BRXSEARCHRANGE_GI2_EARLY 0x700000
2186#define BRXFRAME_FUARD_COUNTER_L 0x3800000
2187#define BRXSGI_GUARD_L 0xc000000
2188#define BRXSGI_SEARCH_L 0x30000000
2189#define BRXSGI_TH 0xc0000000
2190#define BDFSCNT0 0xff
2191#define BDFSCNT1 0xff00
2192#define BDFSFLAG 0xf0000
2193#define BMF_WEIGHT_SUM 0x300000
2194#define BMINIDX_TH 0x7f000000
2195#define BDAFORMAT 0x40000
2196#define BTXCH_EMU_ENABLE 0x01000000
2197#define BTRSW_ISOLATION_A 0x7f
2198#define BTRSW_ISOLATION_B 0x7f00
2199#define BTRSW_ISOLATION_C 0x7f0000
2200#define BTRSW_ISOLATION_D 0x7f000000
2201#define BEXT_LNA_GAIN 0x7c00
2202
2203#define BSTBC_EN 0x4
2204#define BANTENNA_MAPPING 0x10
2205#define BNSS 0x20
2206#define BCFO_ANTSUM_ID 0x200
2207#define BPHY_COUNTER_RESET 0x8000000
2208#define BCFO_REPORT_GET 0x4000000
2209#define BOFDM_CONTINUE_TX 0x10000000
2210#define BOFDM_SINGLE_CARRIER 0x20000000
2211#define BOFDM_SINGLE_TONE 0x40000000
2212#define BHT_DETECT 0x100
2213#define BCFOEN 0x10000
2214#define BCFOVALUE 0xfff00000
2215#define BSIGTONE_RE 0x3f
2216#define BSIGTONE_IM 0x7f00
2217#define BCOUNTER_CCA 0xffff
2218#define BCOUNTER_PARITYFAIL 0xffff0000
2219#define BCOUNTER_RATEILLEGAL 0xffff
2220#define BCOUNTER_CRC8FAIL 0xffff0000
2221#define BCOUNTER_MCSNOSUPPORT 0xffff
2222#define BCOUNTER_FASTSYNC 0xffff
2223#define BSHORTCFO 0xfff
2224#define BSHORTCFOT_LENGTH 12
2225#define BSHORTCFOF_LENGTH 11
2226#define BLONGCFO 0x7ff
2227#define BLONGCFOT_LENGTH 11
2228#define BLONGCFOF_LENGTH 11
2229#define BTAILCFO 0x1fff
2230#define BTAILCFOT_LENGTH 13
2231#define BTAILCFOF_LENGTH 12
2232#define BNOISE_EN_PWDB 0xffff
2233#define BCC_POWER_DB 0xffff0000
2234#define BMOISE_PWDB 0xffff
2235#define BPOWERMEAST_LENGTH 10
2236#define BPOWERMEASF_LENGTH 3
2237#define BRX_HT_BW 0x1
2238#define BRXSC 0x6
2239#define BRX_HT 0x8
2240#define BNB_INTF_DET_ON 0x1
2241#define BINTF_WIN_LEN_CFG 0x30
2242#define BNB_INTF_TH_CFG 0x1c0
2243#define BRFGAIN 0x3f
2244#define BTABLESEL 0x40
2245#define BTRSW 0x80
2246#define BRXSNR_A 0xff
2247#define BRXSNR_B 0xff00
2248#define BRXSNR_C 0xff0000
2249#define BRXSNR_D 0xff000000
2250#define BSNR_EVMT_LENGTH 8
2251#define BSNR_EVMF_LENGTH 1
2252#define BCSI1ST 0xff
2253#define BCSI2ND 0xff00
2254#define BRXEVM1ST 0xff0000
2255#define BRXEVM2ND 0xff000000
2256#define BSIGEVM 0xff
2257#define BPWDB 0xff00
2258#define BSGIEN 0x10000
2259
2260#define BSFACTOR_QMA1 0xf
2261#define BSFACTOR_QMA2 0xf0
2262#define BSFACTOR_QMA3 0xf00
2263#define BSFACTOR_QMA4 0xf000
2264#define BSFACTOR_QMA5 0xf0000
2265#define BSFACTOR_QMA6 0xf0000
2266#define BSFACTOR_QMA7 0xf00000
2267#define BSFACTOR_QMA8 0xf000000
2268#define BSFACTOR_QMA9 0xf0000000
2269#define BCSI_SCHEME 0x100000
2270
2271#define BNOISE_LVL_TOP_SET 0x3
2272#define BCHSMOOTH 0x4
2273#define BCHSMOOTH_CFG1 0x38
2274#define BCHSMOOTH_CFG2 0x1c0
2275#define BCHSMOOTH_CFG3 0xe00
2276#define BCHSMOOTH_CFG4 0x7000
2277#define BMRCMODE 0x800000
2278#define BTHEVMCFG 0x7000000
2279
2280#define BLOOP_FIT_TYPE 0x1
2281#define BUPD_CFO 0x40
2282#define BUPD_CFO_OFFDATA 0x80
2283#define BADV_UPD_CFO 0x100
2284#define BADV_TIME_CTRL 0x800
2285#define BUPD_CLKO 0x1000
2286#define BFC 0x6000
2287#define BTRACKING_MODE 0x8000
2288#define BPHCMP_ENABLE 0x10000
2289#define BUPD_CLKO_LTF 0x20000
2290#define BCOM_CH_CFO 0x40000
2291#define BCSI_ESTI_MODE 0x80000
2292#define BADV_UPD_EQZ 0x100000
2293#define BUCHCFG 0x7000000
2294#define BUPDEQZ 0x8000000
2295
2296#define BRX_PESUDO_NOISE_ON 0x20000000
2297#define BRX_PESUDO_NOISE_A 0xff
2298#define BRX_PESUDO_NOISE_B 0xff00
2299#define BRX_PESUDO_NOISE_C 0xff0000
2300#define BRX_PESUDO_NOISE_D 0xff000000
2301#define BRX_PESUDO_NOISESTATE_A 0xffff
2302#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2303#define BRX_PESUDO_NOISESTATE_C 0xffff
2304#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2305
2306#define BZEBRA1_HSSIENABLE 0x8
2307#define BZEBRA1_TRXCONTROL 0xc00
2308#define BZEBRA1_TRXGAINSETTING 0x07f
2309#define BZEBRA1_RXCOUNTER 0xc00
2310#define BZEBRA1_TXCHANGEPUMP 0x38
2311#define BZEBRA1_RXCHANGEPUMP 0x7
2312#define BZEBRA1_CHANNEL_NUM 0xf80
2313#define BZEBRA1_TXLPFBW 0x400
2314#define BZEBRA1_RXLPFBW 0x600
2315
2316#define BRTL8256REG_MODE_CTRL1 0x100
2317#define BRTL8256REG_MODE_CTRL0 0x40
2318#define BRTL8256REG_TXLPFBW 0x18
2319#define BRTL8256REG_RXLPFBW 0x600
2320
2321#define BRTL8258_TXLPFBW 0xc
2322#define BRTL8258_RXLPFBW 0xc00
2323#define BRTL8258_RSSILPFBW 0xc0
2324
2325#define BBYTE0 0x1
2326#define BBYTE1 0x2
2327#define BBYTE2 0x4
2328#define BBYTE3 0x8
2329#define BWORD0 0x3
2330#define BWORD1 0xc
2331#define BWORD 0xf
2332
2333#define MASKBYTE0 0xff
2334#define MASKBYTE1 0xff00
2335#define MASKBYTE2 0xff0000
2336#define MASKBYTE3 0xff000000
2337#define MASKHWORD 0xffff0000
2338#define MASKLWORD 0x0000ffff
2339#define MASKDWORD 0xffffffff
2340#define MASK12BITS 0xfff
2341#define MASKH4BITS 0xf0000000
2342#define MASKOFDM_D 0xffc00000
2343#define MASKCCK 0x3f3f3f3f
2344
2345#define MASK4BITS 0x0f
2346#define MASK20BITS 0xfffff
2347#define RFREG_OFFSET_MASK 0xfffff
2348
2349#define BENABLE 0x1
2350#define BDISABLE 0x0
2351
2352#define LEFT_ANTENNA 0x0
2353#define RIGHT_ANTENNA 0x1
2354
2355#define TCHECK_TXSTATUS 500
2356#define TUPDATE_RXCOUNTER 100
2357
2358#define REG_UN_used_register 0x01bf
2359
2360/* Path_A RFE cotrol pinmux*/
2361#define RA_RFE_PINMUX 0xcb0
2362/* Path_B RFE control pinmux*/
2363#define RB_RFE_PINMUX 0xeb0
2364
2365#define RA_RFE_INV 0xcb4
2366#define RB_RFE_INV 0xeb4
2367
2368/* RXIQC */
2369/*RxIQ imblance matrix coeff. A & B*/
2370#define RA_RXIQC_AB 0xc10
2371/*RxIQ imblance matrix coeff. C & D*/
2372#define RA_RXIQC_CD 0xc14
2373/* Pah_A TX scaling factor*/
2374#define RA_TXSCALE 0xc1c
2375/* Path_B TX scaling factor*/
2376#define RB_TXSCALE 0xe1c
2377/*RxIQ imblance matrix coeff. A & B*/
2378#define RB_RXIQC_AB 0xe10
2379/*RxIQ imblance matrix coeff. C & D*/
2380#define RB_RXIQC_CD 0xe14
2381/*bit mask for IQC matrix element A & C*/
2382#define RXIQC_AC 0x02ff
2383 /*bit mask for IQC matrix element A & C*/
2384#define RXIQC_BD 0x02ff0000
2385
2386/* 2 EFUSE_TEST (For RTL8723 partially) */
2387#define EFUSE_SEL(x) (((x) & 0x3) << 8)
2388#define EFUSE_SEL_MASK 0x300
2389#define EFUSE_WIFI_SEL_0 0x0
2390
2391/*REG_MULTI_FUNC_CTRL(For RTL8723 Only)*/
2392/* Enable GPIO[9] as WiFi HW PDn source*/
2393#define WL_HWPDN_EN BIT(0)
2394/* WiFi HW PDn polarity control*/
2395#define WL_HWPDN_SL BIT(1)
2396/* WiFi function enable */
2397#define WL_FUNC_EN BIT(2)
2398/* Enable GPIO[9] as WiFi RF HW PDn source */
2399#define WL_HWROF_EN BIT(3)
2400/* Enable GPIO[11] as BT HW PDn source */
2401#define BT_HWPDN_EN BIT(16)
2402/* BT HW PDn polarity control */
2403#define BT_HWPDN_SL BIT(17)
2404/* BT function enable */
2405#define BT_FUNC_EN BIT(18)
2406/* Enable GPIO[11] as BT/GPS RF HW PDn source */
2407#define BT_HWROF_EN BIT(19)
2408/* Enable GPIO[10] as GPS HW PDn source */
2409#define GPS_HWPDN_EN BIT(20)
2410/* GPS HW PDn polarity control */
2411#define GPS_HWPDN_SL BIT(21)
2412/* GPS function enable */
2413#define GPS_FUNC_EN BIT(22)
2414
2415#define BMASKBYTE0 0xff
2416#define BMASKBYTE1 0xff00
2417#define BMASKBYTE2 0xff0000
2418#define BMASKBYTE3 0xff000000
2419#define BMASKHWORD 0xffff0000
2420#define BMASKLWORD 0x0000ffff
2421#define BMASKDWORD 0xffffffff
2422#define BMASK12BITS 0xfff
2423#define BMASKH4BITS 0xf0000000
2424#define BMASKOFDM_D 0xffc00000
2425#define BMASKCCK 0x3f3f3f3f
2426
2427#define BRFREGOFFSETMASK 0xfffff
2428
2429#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
2430#define ODM_REG_BB_RX_PATH_11AC 0x808
2431/*PAGE 9*/
2432#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
2433/*PAGE A*/
2434#define ODM_REG_CCK_CCA_11AC 0xA0A
2435#define ODM_REG_CCK_FA_RST_11AC 0xA2C
2436#define ODM_REG_CCK_FA_11AC 0xA5C
2437/*PAGE C*/
2438#define ODM_REG_IGI_A_11AC 0xC50
2439/*PAGE E*/
2440#define ODM_REG_IGI_B_11AC 0xE50
2441/*PAGE F*/
2442#define ODM_REG_OFDM_FA_11AC 0xF48
2443
2444/* 2 MAC REG LIST */
2445
2446/* DIG Related */
2447#define ODM_BIT_IGI_11AC 0xFFFFFFFF
2448#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
2449#define ODM_BIT_BB_RX_PATH_11AC 0xF
2450
2451enum AGGRE_SIZE {
2452 HT_AGG_SIZE_8K = 0,
2453 HT_AGG_SIZE_16K = 1,
2454 HT_AGG_SIZE_32K = 2,
2455 HT_AGG_SIZE_64K = 3,
2456 VHT_AGG_SIZE_128K = 4,
2457 VHT_AGG_SIZE_256K = 5,
2458 VHT_AGG_SIZE_512K = 6,
2459 VHT_AGG_SIZE_1024K = 7,
2460};
2461
2462#define REG_AMPDU_MAX_LENGTH_8812 0x0458
2463
2464#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/rf.c b/drivers/net/wireless/rtlwifi/rtl8821ae/rf.c
new file mode 100644
index 000000000000..2922538160e5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/rf.c
@@ -0,0 +1,465 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "reg.h"
28#include "def.h"
29#include "phy.h"
30#include "rf.h"
31#include "dm.h"
32
33static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
34
35void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
36{
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38
39 switch (bandwidth) {
40 case HT_CHANNEL_WIDTH_20:
41 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
42 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
43 break;
44 case HT_CHANNEL_WIDTH_20_40:
45 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
47 break;
48 case HT_CHANNEL_WIDTH_80:
49 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
50 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
51 break;
52 default:
53 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
54 "unknown bandwidth: %#X\n", bandwidth);
55 break;
56 }
57}
58
59void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
60 u8 *ppowerlevel)
61{
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_phy *rtlphy = &rtlpriv->phy;
64 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
65 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
66 u32 tx_agc[2] = {0, 0}, tmpval;
67 bool turbo_scanoff = false;
68 u8 idx1, idx2;
69 u8 *ptr;
70 u8 direction;
71 u32 pwrtrac_value;
72
73 if (rtlefuse->eeprom_regulatory != 0)
74 turbo_scanoff = true;
75
76 if (mac->act_scanning) {
77 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
78 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
79
80 if (turbo_scanoff) {
81 for (idx1 = RF90_PATH_A;
82 idx1 <= RF90_PATH_B;
83 idx1++) {
84 tx_agc[idx1] = ppowerlevel[idx1] |
85 (ppowerlevel[idx1] << 8) |
86 (ppowerlevel[idx1] << 16) |
87 (ppowerlevel[idx1] << 24);
88 }
89 }
90 } else {
91 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
92 tx_agc[idx1] = ppowerlevel[idx1] |
93 (ppowerlevel[idx1] << 8) |
94 (ppowerlevel[idx1] << 16) |
95 (ppowerlevel[idx1] << 24);
96 }
97
98 if (rtlefuse->eeprom_regulatory == 0) {
99 tmpval =
100 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
101 (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
102 8);
103 tx_agc[RF90_PATH_A] += tmpval;
104
105 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
106 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
107 24);
108 tx_agc[RF90_PATH_B] += tmpval;
109 }
110 }
111
112 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
113 ptr = (u8 *)(&tx_agc[idx1]);
114 for (idx2 = 0; idx2 < 4; idx2++) {
115 if (*ptr > RF6052_MAX_TX_PWR)
116 *ptr = RF6052_MAX_TX_PWR;
117 ptr++;
118 }
119 }
120 rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
121 if (direction == 1) {
122 tx_agc[0] += pwrtrac_value;
123 tx_agc[1] += pwrtrac_value;
124 } else if (direction == 2) {
125 tx_agc[0] -= pwrtrac_value;
126 tx_agc[1] -= pwrtrac_value;
127 }
128 tmpval = tx_agc[RF90_PATH_A];
129 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval);
130
131 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
132 "CCK PWR 1~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
133 RTXAGC_A_CCK11_CCK1);
134
135 tmpval = tx_agc[RF90_PATH_B];
136 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval);
137
138 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
139 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
140 RTXAGC_B_CCK11_CCK1);
141}
142
143static void rtl8821ae_phy_get_power_base(struct ieee80211_hw *hw,
144 u8 *ppowerlevel_ofdm,
145 u8 *ppowerlevel_bw20,
146 u8 *ppowerlevel_bw40, u8 channel,
147 u32 *ofdmbase, u32 *mcsbase)
148{
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 struct rtl_phy *rtlphy = &rtlpriv->phy;
151 u32 powerbase0, powerbase1;
152 u8 i, powerlevel[2];
153
154 for (i = 0; i < 2; i++) {
155 powerbase0 = ppowerlevel_ofdm[i];
156
157 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
158 (powerbase0 << 8) | powerbase0;
159 *(ofdmbase + i) = powerbase0;
160 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
161 " [OFDM power base index rf(%c) = 0x%x]\n",
162 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
163 }
164
165 for (i = 0; i < 2; i++) {
166 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
167 powerlevel[i] = ppowerlevel_bw20[i];
168 else
169 powerlevel[i] = ppowerlevel_bw40[i];
170
171 powerbase1 = powerlevel[i];
172 powerbase1 = (powerbase1 << 24) |
173 (powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
174
175 *(mcsbase + i) = powerbase1;
176
177 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
178 " [MCS power base index rf(%c) = 0x%x]\n",
179 ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
180 }
181}
182
183static void get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
184 u8 channel, u8 index,
185 u32 *powerbase0,
186 u32 *powerbase1,
187 u32 *p_outwriteval)
188{
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_phy *rtlphy = &rtlpriv->phy;
191 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
192 u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
193 u32 writeval, customer_limit, rf;
194
195 for (rf = 0; rf < 2; rf++) {
196 switch (rtlefuse->eeprom_regulatory) {
197 case 0:
198 chnlgroup = 0;
199
200 writeval =
201 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
202 (rf ? 8 : 0)]
203 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
204
205 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
206 "RTK better performance, writeval(%c) = 0x%x\n",
207 ((rf == 0) ? 'A' : 'B'), writeval);
208 break;
209 case 1:
210 if (rtlphy->pwrgroup_cnt == 1) {
211 chnlgroup = 0;
212 } else {
213 if (channel < 3)
214 chnlgroup = 0;
215 else if (channel < 6)
216 chnlgroup = 1;
217 else if (channel < 9)
218 chnlgroup = 2;
219 else if (channel < 12)
220 chnlgroup = 3;
221 else if (channel < 14)
222 chnlgroup = 4;
223 else if (channel == 14)
224 chnlgroup = 5;
225 }
226
227 writeval =
228 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
229 [index + (rf ? 8 : 0)] + ((index < 2) ?
230 powerbase0[rf] :
231 powerbase1[rf]);
232
233 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
234 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
235 ((rf == 0) ? 'A' : 'B'), writeval);
236
237 break;
238 case 2:
239 writeval =
240 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
241
242 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
243 "Better regulatory, writeval(%c) = 0x%x\n",
244 ((rf == 0) ? 'A' : 'B'), writeval);
245 break;
246 case 3:
247 chnlgroup = 0;
248
249 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
250 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
251 "customer's limit, 40MHz rf(%c) = 0x%x\n",
252 ((rf == 0) ? 'A' : 'B'),
253 rtlefuse->pwrgroup_ht40[rf][channel -
254 1]);
255 } else {
256 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
257 "customer's limit, 20MHz rf(%c) = 0x%x\n",
258 ((rf == 0) ? 'A' : 'B'),
259 rtlefuse->pwrgroup_ht20[rf][channel -
260 1]);
261 }
262
263 if (index < 2)
264 pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
265 else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
266 pwr_diff =
267 rtlefuse->txpwr_ht20diff[rf][channel-1];
268
269 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
270 customer_pwr_diff =
271 rtlefuse->pwrgroup_ht40[rf][channel-1];
272 else
273 customer_pwr_diff =
274 rtlefuse->pwrgroup_ht20[rf][channel-1];
275
276 if (pwr_diff > customer_pwr_diff)
277 pwr_diff = 0;
278 else
279 pwr_diff = customer_pwr_diff - pwr_diff;
280
281 for (i = 0; i < 4; i++) {
282 pwr_diff_limit[i] =
283 (u8)((rtlphy->mcs_txpwrlevel_origoffset
284 [chnlgroup][index + (rf ? 8 : 0)] &
285 (0x7f << (i * 8))) >> (i * 8));
286
287 if (pwr_diff_limit[i] > pwr_diff)
288 pwr_diff_limit[i] = pwr_diff;
289 }
290
291 customer_limit = (pwr_diff_limit[3] << 24) |
292 (pwr_diff_limit[2] << 16) |
293 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
294
295 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
296 "Customer's limit rf(%c) = 0x%x\n",
297 ((rf == 0) ? 'A' : 'B'), customer_limit);
298
299 writeval = customer_limit +
300 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
301
302 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
303 "Customer, writeval rf(%c)= 0x%x\n",
304 ((rf == 0) ? 'A' : 'B'), writeval);
305 break;
306 default:
307 chnlgroup = 0;
308 writeval =
309 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
310 [index + (rf ? 8 : 0)]
311 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
312
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
314 "RTK better performance, writeval rf(%c) = 0x%x\n",
315 ((rf == 0) ? 'A' : 'B'), writeval);
316 break;
317 }
318
319 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
320 writeval = writeval - 0x06060606;
321 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
322 TXHIGHPWRLEVEL_BT2)
323 writeval = writeval - 0x0c0c0c0c;
324 *(p_outwriteval + rf) = writeval;
325 }
326}
327
328static void _rtl8821ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
329 u8 index, u32 *pvalue)
330{
331 struct rtl_priv *rtlpriv = rtl_priv(hw);
332 u16 regoffset_a[6] = {
333 RTXAGC_A_OFDM18_OFDM6, RTXAGC_A_OFDM54_OFDM24,
334 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
335 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
336 };
337 u16 regoffset_b[6] = {
338 RTXAGC_B_OFDM18_OFDM6, RTXAGC_B_OFDM54_OFDM24,
339 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
340 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
341 };
342 u8 i, rf, pwr_val[4];
343 u32 writeval;
344 u16 regoffset;
345
346 for (rf = 0; rf < 2; rf++) {
347 writeval = pvalue[rf];
348 for (i = 0; i < 4; i++) {
349 pwr_val[i] = (u8)((writeval & (0x7f <<
350 (i * 8))) >> (i * 8));
351
352 if (pwr_val[i] > RF6052_MAX_TX_PWR)
353 pwr_val[i] = RF6052_MAX_TX_PWR;
354 }
355 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
356 (pwr_val[1] << 8) | pwr_val[0];
357
358 if (rf == 0)
359 regoffset = regoffset_a[index];
360 else
361 regoffset = regoffset_b[index];
362 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
363
364 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
365 "Set 0x%x = %08x\n", regoffset, writeval);
366 }
367}
368
369void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
370 u8 *ppowerlevel_ofdm,
371 u8 *ppowerlevel_bw20,
372 u8 *ppowerlevel_bw40,
373 u8 channel)
374{
375 u32 writeval[2], powerbase0[2], powerbase1[2];
376 u8 index;
377 u8 direction;
378 u32 pwrtrac_value;
379
380 rtl8821ae_phy_get_power_base(hw, ppowerlevel_ofdm,
381 ppowerlevel_bw20,
382 ppowerlevel_bw40,
383 channel,
384 &powerbase0[0],
385 &powerbase1[0]);
386
387 rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
388
389 for (index = 0; index < 6; index++) {
390 get_txpower_writeval_by_regulatory(hw, channel, index,
391 &powerbase0[0],
392 &powerbase1[0],
393 &writeval[0]);
394 if (direction == 1) {
395 writeval[0] += pwrtrac_value;
396 writeval[1] += pwrtrac_value;
397 } else if (direction == 2) {
398 writeval[0] -= pwrtrac_value;
399 writeval[1] -= pwrtrac_value;
400 }
401 _rtl8821ae_write_ofdm_power_reg(hw, index, &writeval[0]);
402 }
403}
404
405bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw)
406{
407 struct rtl_priv *rtlpriv = rtl_priv(hw);
408 struct rtl_phy *rtlphy = &rtlpriv->phy;
409
410 if (rtlphy->rf_type == RF_1T1R)
411 rtlphy->num_total_rfpath = 1;
412 else
413 rtlphy->num_total_rfpath = 2;
414
415 return _rtl8821ae_phy_rf6052_config_parafile(hw);
416}
417
418static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
419{
420 struct rtl_priv *rtlpriv = rtl_priv(hw);
421 struct rtl_phy *rtlphy = &rtlpriv->phy;
422 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
423 u8 rfpath;
424 bool rtstatus = true;
425
426 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
427 switch (rfpath) {
428 case RF90_PATH_A: {
429 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
430 rtstatus =
431 rtl8812ae_phy_config_rf_with_headerfile(hw,
432 (enum radio_path)rfpath);
433 else
434 rtstatus =
435 rtl8821ae_phy_config_rf_with_headerfile(hw,
436 (enum radio_path)rfpath);
437 break;
438 }
439 case RF90_PATH_B:
440 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
441 rtstatus =
442 rtl8812ae_phy_config_rf_with_headerfile(hw,
443 (enum radio_path)rfpath);
444 else
445 rtstatus =
446 rtl8821ae_phy_config_rf_with_headerfile(hw,
447 (enum radio_path)rfpath);
448 break;
449 case RF90_PATH_C:
450 break;
451 case RF90_PATH_D:
452 break;
453 }
454
455 if (!rtstatus) {
456 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
457 "Radio[%d] Fail!!", rfpath);
458 return false;
459 }
460 }
461
462 /*put arrays in dm.c*/
463 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
464 return rtstatus;
465}
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/rf.h b/drivers/net/wireless/rtlwifi/rtl8821ae/rf.h
new file mode 100644
index 000000000000..d9582ee1c335
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/rf.h
@@ -0,0 +1,43 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_RF_H__
27#define __RTL8821AE_RF_H__
28
29#define RF6052_MAX_TX_PWR 0x3F
30#define RF6052_MAX_REG 0x3F
31
32void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
33 u8 bandwidth);
34void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
35 u8 *ppowerlevel);
36void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
37 u8 *ppowerlevel_ofdm,
38 u8 *ppowerlevel_bw20,
39 u8 *ppowerlevel_bw40,
40 u8 channel);
41bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw);
42
43#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/sw.c b/drivers/net/wireless/rtlwifi/rtl8821ae/sw.c
new file mode 100644
index 000000000000..3cf7557b7786
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/sw.c
@@ -0,0 +1,484 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../core.h"
28#include "../pci.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "dm.h"
33#include "hw.h"
34#include "fw.h"
35#include "sw.h"
36#include "trx.h"
37#include "led.h"
38#include "table.h"
39#include "../btcoexist/rtl_btc.h"
40
41#include <linux/vmalloc.h>
42#include <linux/module.h>
43
44static void rtl8821ae_init_aspm_vars(struct ieee80211_hw *hw)
45{
46 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
47
48 /*close ASPM for AMD defaultly */
49 rtlpci->const_amdpci_aspm = 0;
50
51 /**
52 * ASPM PS mode.
53 * 0 - Disable ASPM,
54 * 1 - Enable ASPM without Clock Req,
55 * 2 - Enable ASPM with Clock Req,
56 * 3 - Alwyas Enable ASPM with Clock Req,
57 * 4 - Always Enable ASPM without Clock Req.
58 * set defult to RTL8192CE:3 RTL8192E:2
59 */
60 rtlpci->const_pci_aspm = 3;
61
62 /*Setting for PCI-E device */
63 rtlpci->const_devicepci_aspm_setting = 0x03;
64
65 /*Setting for PCI-E bridge */
66 rtlpci->const_hostpci_aspm_setting = 0x02;
67
68 /**
69 * In Hw/Sw Radio Off situation.
70 * 0 - Default,
71 * 1 - From ASPM setting without low Mac Pwr,
72 * 2 - From ASPM setting with low Mac Pwr,
73 * 3 - Bus D3
74 * set default to RTL8192CE:0 RTL8192SE:2
75 */
76 rtlpci->const_hwsw_rfoff_d3 = 0;
77
78 /**
79 * This setting works for those device with
80 * backdoor ASPM setting such as EPHY setting.
81 * 0 - Not support ASPM,
82 * 1 - Support ASPM,
83 * 2 - According to chipset.
84 */
85 rtlpci->const_support_pciaspm = 1;
86}
87
88static void load_wowlan_fw(struct rtl_priv *rtlpriv)
89{
90 /* callback routine to load wowlan firmware after main fw has
91 * been loaded
92 */
93 const struct firmware *wowlan_firmware;
94 char *fw_name = NULL;
95 int err;
96
97 /* for wowlan firmware buf */
98 rtlpriv->rtlhal.wowlan_firmware = vmalloc(0x8000);
99 if (!rtlpriv->rtlhal.wowlan_firmware) {
100 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
101 "Can't alloc buffer for wowlan fw.\n");
102 return;
103 }
104
105 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8821AE)
106 fw_name = "rtlwifi/rtl8821aefw_wowlan.bin";
107 else
108 fw_name = "rtlwifi/rtl8812aefw_wowlan.bin";
109 err = request_firmware(&wowlan_firmware, fw_name, rtlpriv->io.dev);
110 if (err) {
111 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
112 "Failed to request wowlan firmware!\n");
113 goto error;
114 }
115
116 if (wowlan_firmware->size > 0x8000) {
117 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
118 "Wowlan Firmware is too big!\n");
119 goto error;
120 }
121
122 memcpy(rtlpriv->rtlhal.wowlan_firmware, wowlan_firmware->data,
123 wowlan_firmware->size);
124 rtlpriv->rtlhal.wowlan_fwsize = wowlan_firmware->size;
125 release_firmware(wowlan_firmware);
126
127 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "WOWLAN FirmwareDownload OK\n");
128 return;
129error:
130 release_firmware(wowlan_firmware);
131 vfree(rtlpriv->rtlhal.wowlan_firmware);
132}
133
134/*InitializeVariables8812E*/
135int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw)
136{
137 int err = 0;
138 struct rtl_priv *rtlpriv = rtl_priv(hw);
139 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
140 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
141 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
142
143 rtl8821ae_bt_reg_init(hw);
144 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
145 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
146
147 rtlpriv->dm.dm_initialgain_enable = 1;
148 rtlpriv->dm.dm_flag = 0;
149 rtlpriv->dm.disable_framebursting = 0;
150 rtlpriv->dm.thermalvalue = 0;
151 rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
152
153 mac->ht_enable = true;
154 mac->ht_cur_stbc = 0;
155 mac->ht_stbc_cap = 0;
156 mac->vht_cur_ldpc = 0;
157 mac->vht_ldpc_cap = 0;
158 mac->vht_cur_stbc = 0;
159 mac->vht_stbc_cap = 0;
160
161 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
162 /*following 2 is for register 5G band, refer to _rtl_init_mac80211()*/
163 rtlpriv->rtlhal.bandset = BAND_ON_BOTH;
164 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
165
166 rtlpci->receive_config = (RCR_APPFCS |
167 RCR_APP_MIC |
168 RCR_APP_ICV |
169 RCR_APP_PHYST_RXFF |
170 RCR_NONQOS_VHT |
171 RCR_HTC_LOC_CTRL |
172 RCR_AMF |
173 RCR_ACF |
174 /*This bit controls the PS-Poll packet filter.*/
175 RCR_ADF |
176 RCR_AICV |
177 RCR_ACRC32 |
178 RCR_AB |
179 RCR_AM |
180 RCR_APM |
181 0);
182
183 rtlpci->irq_mask[0] =
184 (u32)(IMR_PSTIMEOUT |
185 IMR_GTINT3 |
186 IMR_HSISR_IND_ON_INT |
187 IMR_C2HCMD |
188 IMR_HIGHDOK |
189 IMR_MGNTDOK |
190 IMR_BKDOK |
191 IMR_BEDOK |
192 IMR_VIDOK |
193 IMR_VODOK |
194 IMR_RDU |
195 IMR_ROK |
196 0);
197
198 rtlpci->irq_mask[1] =
199 (u32)(IMR_RXFOVW |
200 IMR_TXFOVW |
201 0);
202 rtlpci->sys_irq_mask = (u32)(HSIMR_PDN_INT_EN |
203 HSIMR_RON_INT_EN |
204 0);
205 /* for WOWLAN */
206 rtlpriv->psc.wo_wlan_mode = WAKE_ON_MAGIC_PACKET |
207 WAKE_ON_PATTERN_MATCH;
208
209 /* for debug level */
210 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
211 /* for LPS & IPS */
212 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
213 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
214 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
215 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
216 if (rtlpriv->cfg->mod_params->disable_watchdog)
217 pr_info("watchdog disabled\n");
218 rtlpriv->psc.reg_fwctrl_lps = 3;
219 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
220 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
221
222 /* for ASPM, you can close aspm through
223 * set const_support_pciaspm = 0
224 */
225 rtl8821ae_init_aspm_vars(hw);
226
227 if (rtlpriv->psc.reg_fwctrl_lps == 1)
228 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
229 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
230 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
231 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
232 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
233
234 rtlpriv->rtl_fw_second_cb = load_wowlan_fw;
235 /* for firmware buf */
236 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
237 if (!rtlpriv->rtlhal.pfirmware) {
238 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
239 "Can't alloc buffer for fw.\n");
240 return 1;
241 }
242
243 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
244 rtlpriv->cfg->fw_name = "rtlwifi/rtl8812aefw.bin";
245 else
246 rtlpriv->cfg->fw_name = "rtlwifi/rtl8821aefw.bin";
247
248 rtlpriv->max_fw_size = 0x8000;
249 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
250 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
251 rtlpriv->io.dev, GFP_KERNEL, hw,
252 rtl_fw_cb);
253 if (err) {
254 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
255 "Failed to request firmware!\n");
256 return 1;
257 }
258 return 0;
259}
260
261void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw)
262{
263 struct rtl_priv *rtlpriv = rtl_priv(hw);
264
265 if (rtlpriv->rtlhal.pfirmware) {
266 vfree(rtlpriv->rtlhal.pfirmware);
267 rtlpriv->rtlhal.pfirmware = NULL;
268 }
269#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
270 if (rtlpriv->rtlhal.wowlan_firmware) {
271 vfree(rtlpriv->rtlhal.wowlan_firmware);
272 rtlpriv->rtlhal.wowlan_firmware = NULL;
273 }
274#endif
275}
276
277/* get bt coexist status */
278bool rtl8821ae_get_btc_status(void)
279{
280 return true;
281}
282
283static struct rtl_hal_ops rtl8821ae_hal_ops = {
284 .init_sw_vars = rtl8821ae_init_sw_vars,
285 .deinit_sw_vars = rtl8821ae_deinit_sw_vars,
286 .read_eeprom_info = rtl8821ae_read_eeprom_info,
287 .interrupt_recognized = rtl8821ae_interrupt_recognized,
288 .hw_init = rtl8821ae_hw_init,
289 .hw_disable = rtl8821ae_card_disable,
290 .hw_suspend = rtl8821ae_suspend,
291 .hw_resume = rtl8821ae_resume,
292 .enable_interrupt = rtl8821ae_enable_interrupt,
293 .disable_interrupt = rtl8821ae_disable_interrupt,
294 .set_network_type = rtl8821ae_set_network_type,
295 .set_chk_bssid = rtl8821ae_set_check_bssid,
296 .set_qos = rtl8821ae_set_qos,
297 .set_bcn_reg = rtl8821ae_set_beacon_related_registers,
298 .set_bcn_intv = rtl8821ae_set_beacon_interval,
299 .update_interrupt_mask = rtl8821ae_update_interrupt_mask,
300 .get_hw_reg = rtl8821ae_get_hw_reg,
301 .set_hw_reg = rtl8821ae_set_hw_reg,
302 .update_rate_tbl = rtl8821ae_update_hal_rate_tbl,
303 .fill_tx_desc = rtl8821ae_tx_fill_desc,
304 .fill_tx_cmddesc = rtl8821ae_tx_fill_cmddesc,
305 .query_rx_desc = rtl8821ae_rx_query_desc,
306 .set_channel_access = rtl8821ae_update_channel_access_setting,
307 .radio_onoff_checking = rtl8821ae_gpio_radio_on_off_checking,
308 .set_bw_mode = rtl8821ae_phy_set_bw_mode,
309 .switch_channel = rtl8821ae_phy_sw_chnl,
310 .dm_watchdog = rtl8821ae_dm_watchdog,
311 .scan_operation_backup = rtl8821ae_phy_scan_operation_backup,
312 .set_rf_power_state = rtl8821ae_phy_set_rf_power_state,
313 .led_control = rtl8821ae_led_control,
314 .set_desc = rtl8821ae_set_desc,
315 .get_desc = rtl8821ae_get_desc,
316 .is_tx_desc_closed = rtl8821ae_is_tx_desc_closed,
317 .tx_polling = rtl8821ae_tx_polling,
318 .enable_hw_sec = rtl8821ae_enable_hw_security_config,
319 .set_key = rtl8821ae_set_key,
320 .init_sw_leds = rtl8821ae_init_sw_leds,
321 .get_bbreg = rtl8821ae_phy_query_bb_reg,
322 .set_bbreg = rtl8821ae_phy_set_bb_reg,
323 .get_rfreg = rtl8821ae_phy_query_rf_reg,
324 .set_rfreg = rtl8821ae_phy_set_rf_reg,
325 .fill_h2c_cmd = rtl8821ae_fill_h2c_cmd,
326 .get_btc_status = rtl8821ae_get_btc_status,
327 .rx_command_packet = rtl8821ae_rx_command_packet,
328 .add_wowlan_pattern = rtl8821ae_add_wowlan_pattern,
329};
330
331static struct rtl_mod_params rtl8821ae_mod_params = {
332 .sw_crypto = false,
333 .inactiveps = true,
334 .swctrl_lps = false,
335 .fwctrl_lps = true,
336 .msi_support = true,
337 .debug = DBG_EMERG,
338 .disable_watchdog = 0,
339};
340
341static struct rtl_hal_cfg rtl8821ae_hal_cfg = {
342 .bar_id = 2,
343 .write_readback = true,
344 .name = "rtl8821ae_pci",
345 .fw_name = "rtlwifi/rtl8821aefw.bin",
346 .ops = &rtl8821ae_hal_ops,
347 .mod_params = &rtl8821ae_mod_params,
348 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
349 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
350 .maps[SYS_CLK] = REG_SYS_CLKR,
351 .maps[MAC_RCR_AM] = AM,
352 .maps[MAC_RCR_AB] = AB,
353 .maps[MAC_RCR_ACRC32] = ACRC32,
354 .maps[MAC_RCR_ACF] = ACF,
355 .maps[MAC_RCR_AAP] = AAP,
356 .maps[MAC_HIMR] = REG_HIMR,
357 .maps[MAC_HIMRE] = REG_HIMRE,
358
359 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
360
361 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
362 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
363 .maps[EFUSE_CLK] = 0,
364 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
365 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
366 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
367 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
368 .maps[EFUSE_ANA8M] = ANA8M,
369 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
370 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
371 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
372 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
373
374 .maps[RWCAM] = REG_CAMCMD,
375 .maps[WCAMI] = REG_CAMWRITE,
376 .maps[RCAMO] = REG_CAMREAD,
377 .maps[CAMDBG] = REG_CAMDBG,
378 .maps[SECR] = REG_SECCFG,
379 .maps[SEC_CAM_NONE] = CAM_NONE,
380 .maps[SEC_CAM_WEP40] = CAM_WEP40,
381 .maps[SEC_CAM_TKIP] = CAM_TKIP,
382 .maps[SEC_CAM_AES] = CAM_AES,
383 .maps[SEC_CAM_WEP104] = CAM_WEP104,
384
385 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
386 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
387 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
388 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
389 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
390 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
391/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
392 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
393 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
394 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
395 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
396 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
397 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
398 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
399/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
400/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
401
402 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
403 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
404 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
405 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
406 .maps[RTL_IMR_RDU] = IMR_RDU,
407 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
408 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
409 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
410 .maps[RTL_IMR_TBDER] = IMR_TBDER,
411 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
412 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
413 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
414 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
415 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
416 .maps[RTL_IMR_VODOK] = IMR_VODOK,
417 .maps[RTL_IMR_ROK] = IMR_ROK,
418 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
419
420 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
421 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
422 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
423 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
424 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
425 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
426 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
427 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
428 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
429 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
430 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
431 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
432
433 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
434 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
435
436 /*VHT hightest rate*/
437 .maps[RTL_RC_VHT_RATE_1SS_MCS7] = DESC_RATEVHT1SS_MCS7,
438 .maps[RTL_RC_VHT_RATE_1SS_MCS8] = DESC_RATEVHT1SS_MCS8,
439 .maps[RTL_RC_VHT_RATE_1SS_MCS9] = DESC_RATEVHT1SS_MCS9,
440 .maps[RTL_RC_VHT_RATE_2SS_MCS7] = DESC_RATEVHT2SS_MCS7,
441 .maps[RTL_RC_VHT_RATE_2SS_MCS8] = DESC_RATEVHT2SS_MCS8,
442 .maps[RTL_RC_VHT_RATE_2SS_MCS9] = DESC_RATEVHT2SS_MCS9,
443};
444
445static struct pci_device_id rtl8821ae_pci_ids[] = {
446 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8812, rtl8821ae_hal_cfg)},
447 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8821, rtl8821ae_hal_cfg)},
448 {},
449};
450
451MODULE_DEVICE_TABLE(pci, rtl8821ae_pci_ids);
452
453MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
454MODULE_LICENSE("GPL");
455MODULE_DESCRIPTION("Realtek 8821ae 802.11ac PCI wireless");
456MODULE_FIRMWARE("rtlwifi/rtl8821aefw.bin");
457
458module_param_named(swenc, rtl8821ae_mod_params.sw_crypto, bool, 0444);
459module_param_named(debug, rtl8821ae_mod_params.debug, int, 0444);
460module_param_named(ips, rtl8821ae_mod_params.inactiveps, bool, 0444);
461module_param_named(swlps, rtl8821ae_mod_params.swctrl_lps, bool, 0444);
462module_param_named(fwlps, rtl8821ae_mod_params.fwctrl_lps, bool, 0444);
463module_param_named(msi, rtl8821ae_mod_params.msi_support, bool, 0444);
464module_param_named(disable_watchdog, rtl8821ae_mod_params.disable_watchdog,
465 bool, 0444);
466MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
467MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
468MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
469MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
470MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
471MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
472MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
473
474static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
475
476static struct pci_driver rtl8821ae_driver = {
477 .name = KBUILD_MODNAME,
478 .id_table = rtl8821ae_pci_ids,
479 .probe = rtl_pci_probe,
480 .remove = rtl_pci_disconnect,
481 .driver.pm = &rtlwifi_pm_ops,
482};
483
484module_pci_driver(rtl8821ae_driver);
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/sw.h b/drivers/net/wireless/rtlwifi/rtl8821ae/sw.h
new file mode 100644
index 000000000000..d001e7ce3052
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/sw.h
@@ -0,0 +1,34 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_SW_H__
27#define __RTL8821AE_SW_H__
28
29int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw);
30void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw);
31void rtl8821ae_init_var_map(struct ieee80211_hw *hw);
32bool rtl8821ae_get_btc_status(void);
33
34#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/table.c b/drivers/net/wireless/rtlwifi/rtl8821ae/table.c
new file mode 100644
index 000000000000..62a0fb76f080
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/table.c
@@ -0,0 +1,4572 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Created on 2010/ 5/18, 1:41
23 *
24 * Larry Finger <Larry.Finger@lwfinger.net>
25 *
26 *****************************************************************************/
27
28#include "table.h"
29u32 RTL8812AE_PHY_REG_ARRAY[] = {
30 0x800, 0x8020D010,
31 0x804, 0x080112E0,
32 0x808, 0x0E028233,
33 0x80C, 0x12131113,
34 0x810, 0x20101263,
35 0x814, 0x020C3D10,
36 0x818, 0x03A00385,
37 0x820, 0x00000000,
38 0x824, 0x00030FE0,
39 0x828, 0x00000000,
40 0x82C, 0x002083DD,
41 0x830, 0x2AAA6C86,
42 0x834, 0x0037A706,
43 0x838, 0x06C89B44,
44 0x83C, 0x0000095B,
45 0x840, 0xC0000001,
46 0x844, 0x40003CDE,
47 0x848, 0x6210FF8B,
48 0x84C, 0x6CFDFFB8,
49 0x850, 0x28874706,
50 0x854, 0x0001520C,
51 0x858, 0x8060E000,
52 0x85C, 0x74210168,
53 0x860, 0x6929C321,
54 0x864, 0x79727432,
55 0x868, 0x8CA7A314,
56 0x86C, 0x338C2878,
57 0x870, 0x03333333,
58 0x874, 0x31602C2E,
59 0x878, 0x00003152,
60 0x87C, 0x000FC000,
61 0x8A0, 0x00000013,
62 0x8A4, 0x7F7F7F7F,
63 0x8A8, 0xA202033E,
64 0x8AC, 0x0FF0FA0A,
65 0x8B0, 0x00000600,
66 0x8B4, 0x000FC080,
67 0x8B8, 0x6C0057FF,
68 0x8BC, 0x4CA520A3,
69 0x8C0, 0x27F00020,
70 0x8C4, 0x00000000,
71 0x8C8, 0x00013169,
72 0x8CC, 0x08248492,
73 0x8D0, 0x0000B800,
74 0x8DC, 0x00000000,
75 0x8D4, 0x940008A0,
76 0x8D8, 0x290B5612,
77 0x8F8, 0x400002C0,
78 0x8FC, 0x00000000,
79 0xFF0F07D8, 0xABCD,
80 0x900, 0x00000701,
81 0xFF0F07D0, 0xCDEF,
82 0x900, 0x00000701,
83 0xCDCDCDCD, 0xCDCD,
84 0x900, 0x00000700,
85 0xFF0F07D8, 0xDEAD,
86 0x90C, 0x00000000,
87 0x910, 0x0000FC00,
88 0x914, 0x00000404,
89 0x918, 0x1C1028C0,
90 0x91C, 0x64B11A1C,
91 0x920, 0xE0767233,
92 0x924, 0x055AA500,
93 0x928, 0x00000004,
94 0x92C, 0xFFFE0000,
95 0x930, 0xFFFFFFFE,
96 0x934, 0x001FFFFF,
97 0x960, 0x00000000,
98 0x964, 0x00000000,
99 0x968, 0x00000000,
100 0x96C, 0x00000000,
101 0x970, 0x801FFFFF,
102 0x978, 0x00000000,
103 0x97C, 0x00000000,
104 0x980, 0x00000000,
105 0x984, 0x00000000,
106 0x988, 0x00000000,
107 0x990, 0x27100000,
108 0x994, 0xFFFF0100,
109 0x998, 0xFFFFFF5C,
110 0x99C, 0xFFFFFFFF,
111 0x9A0, 0x000000FF,
112 0x9A4, 0x00080080,
113 0x9A8, 0x00000000,
114 0x9AC, 0x00000000,
115 0x9B0, 0x81081008,
116 0x9B4, 0x00000000,
117 0x9B8, 0x01081008,
118 0x9BC, 0x01081008,
119 0x9D0, 0x00000000,
120 0x9D4, 0x00000000,
121 0x9D8, 0x00000000,
122 0x9DC, 0x00000000,
123 0x9E4, 0x00000002,
124 0x9E8, 0x000002D5,
125 0xA00, 0x00D047C8,
126 0xA04, 0x01FF000C,
127 0xA08, 0x8C838300,
128 0xA0C, 0x2E7F000F,
129 0xA10, 0x9500BB78,
130 0xA14, 0x11144028,
131 0xA18, 0x00881117,
132 0xA1C, 0x89140F00,
133 0xA20, 0x1A1B0000,
134 0xA24, 0x090E1317,
135 0xA28, 0x00000204,
136 0xA2C, 0x00900000,
137 0xA70, 0x101FFF00,
138 0xA74, 0x00000008,
139 0xA78, 0x00000900,
140 0xA7C, 0x225B0606,
141 0xA80, 0x218075B2,
142 0xA84, 0x001F8C80,
143 0xB00, 0x03100000,
144 0xB04, 0x0000B000,
145 0xB08, 0xAE0201EB,
146 0xB0C, 0x01003207,
147 0xB10, 0x00009807,
148 0xB14, 0x01000000,
149 0xB18, 0x00000002,
150 0xB1C, 0x00000002,
151 0xB20, 0x0000001F,
152 0xB24, 0x03020100,
153 0xB28, 0x07060504,
154 0xB2C, 0x0B0A0908,
155 0xB30, 0x0F0E0D0C,
156 0xB34, 0x13121110,
157 0xB38, 0x17161514,
158 0xB3C, 0x0000003A,
159 0xB40, 0x00000000,
160 0xB44, 0x00000000,
161 0xB48, 0x13000032,
162 0xB4C, 0x48080000,
163 0xB50, 0x00000000,
164 0xB54, 0x00000000,
165 0xB58, 0x00000000,
166 0xB5C, 0x00000000,
167 0xC00, 0x00000007,
168 0xC04, 0x00042020,
169 0xC08, 0x80410231,
170 0xC0C, 0x00000000,
171 0xC10, 0x00000100,
172 0xC14, 0x01000000,
173 0xC1C, 0x40000003,
174 0xC20, 0x12121212,
175 0xC24, 0x12121212,
176 0xC28, 0x12121212,
177 0xC2C, 0x12121212,
178 0xC30, 0x12121212,
179 0xC34, 0x12121212,
180 0xC38, 0x12121212,
181 0xC3C, 0x12121212,
182 0xC40, 0x12121212,
183 0xC44, 0x12121212,
184 0xC48, 0x12121212,
185 0xC4C, 0x12121212,
186 0xC50, 0x00000020,
187 0xC54, 0x0008121C,
188 0xC58, 0x30000C1C,
189 0xC5C, 0x00000058,
190 0xC60, 0x34344443,
191 0xC64, 0x07003333,
192 0xC68, 0x59791979,
193 0xC6C, 0x59795979,
194 0xC70, 0x19795979,
195 0xC74, 0x19795979,
196 0xC78, 0x19791979,
197 0xC7C, 0x19791979,
198 0xC80, 0x19791979,
199 0xC84, 0x19791979,
200 0xC94, 0x0100005C,
201 0xC98, 0x00000000,
202 0xC9C, 0x00000000,
203 0xCA0, 0x00000029,
204 0xCA4, 0x08040201,
205 0xCA8, 0x80402010,
206 0xFF0F0740, 0xABCD,
207 0xCB0, 0x77547717,
208 0xFF0F01C0, 0xCDEF,
209 0xCB0, 0x77547717,
210 0xFF0F02C0, 0xCDEF,
211 0xCB0, 0x77547717,
212 0xFF0F07D8, 0xCDEF,
213 0xCB0, 0x54547710,
214 0xFF0F07D0, 0xCDEF,
215 0xCB0, 0x54547710,
216 0xCDCDCDCD, 0xCDCD,
217 0xCB0, 0x77547777,
218 0xFF0F0740, 0xDEAD,
219 0xCB4, 0x00000077,
220 0xCB8, 0x00508242,
221 0xE00, 0x00000007,
222 0xE04, 0x00042020,
223 0xE08, 0x80410231,
224 0xE0C, 0x00000000,
225 0xE10, 0x00000100,
226 0xE14, 0x01000000,
227 0xE1C, 0x40000003,
228 0xE20, 0x12121212,
229 0xE24, 0x12121212,
230 0xE28, 0x12121212,
231 0xE2C, 0x12121212,
232 0xE30, 0x12121212,
233 0xE34, 0x12121212,
234 0xE38, 0x12121212,
235 0xE3C, 0x12121212,
236 0xE40, 0x12121212,
237 0xE44, 0x12121212,
238 0xE48, 0x12121212,
239 0xE4C, 0x12121212,
240 0xE50, 0x00000020,
241 0xE54, 0x0008121C,
242 0xE58, 0x30000C1C,
243 0xE5C, 0x00000058,
244 0xE60, 0x34344443,
245 0xE64, 0x07003333,
246 0xE68, 0x59791979,
247 0xE6C, 0x59795979,
248 0xE70, 0x19795979,
249 0xE74, 0x19795979,
250 0xE78, 0x19791979,
251 0xE7C, 0x19791979,
252 0xE80, 0x19791979,
253 0xE84, 0x19791979,
254 0xE94, 0x0100005C,
255 0xE98, 0x00000000,
256 0xE9C, 0x00000000,
257 0xEA0, 0x00000029,
258 0xEA4, 0x08040201,
259 0xEA8, 0x80402010,
260 0xFF0F0740, 0xABCD,
261 0xEB0, 0x77547717,
262 0xFF0F01C0, 0xCDEF,
263 0xEB0, 0x77547717,
264 0xFF0F02C0, 0xCDEF,
265 0xEB0, 0x77547717,
266 0xFF0F07D8, 0xCDEF,
267 0xEB0, 0x54547710,
268 0xFF0F07D0, 0xCDEF,
269 0xEB0, 0x54547710,
270 0xCDCDCDCD, 0xCDCD,
271 0xEB0, 0x77547777,
272 0xFF0F0740, 0xDEAD,
273 0xEB4, 0x00000077,
274 0xEB8, 0x00508242,
275};
276
277u32 RTL8821AE_PHY_REG_ARRAY[] = {
278 0x800, 0x0020D090,
279 0x804, 0x080112E0,
280 0x808, 0x0E028211,
281 0x80C, 0x92131111,
282 0x810, 0x20101261,
283 0x814, 0x020C3D10,
284 0x818, 0x03A00385,
285 0x820, 0x00000000,
286 0x824, 0x00030FE0,
287 0x828, 0x00000000,
288 0x82C, 0x002081DD,
289 0x830, 0x2AAA8E24,
290 0x834, 0x0037A706,
291 0x838, 0x06489B44,
292 0x83C, 0x0000095B,
293 0x840, 0xC0000001,
294 0x844, 0x40003CDE,
295 0x848, 0x62103F8B,
296 0x84C, 0x6CFDFFB8,
297 0x850, 0x28874706,
298 0x854, 0x0001520C,
299 0x858, 0x8060E000,
300 0x85C, 0x74210168,
301 0x860, 0x6929C321,
302 0x864, 0x79727432,
303 0x868, 0x8CA7A314,
304 0x86C, 0x888C2878,
305 0x870, 0x08888888,
306 0x874, 0x31612C2E,
307 0x878, 0x00000152,
308 0x87C, 0x000FD000,
309 0x8A0, 0x00000013,
310 0x8A4, 0x7F7F7F7F,
311 0x8A8, 0xA2000338,
312 0x8AC, 0x0FF0FA0A,
313 0x8B4, 0x000FC080,
314 0x8B8, 0x6C10D7FF,
315 0x8BC, 0x0CA52090,
316 0x8C0, 0x1BF00020,
317 0x8C4, 0x00000000,
318 0x8C8, 0x00013169,
319 0x8CC, 0x08248492,
320 0x8D4, 0x940008A0,
321 0x8D8, 0x290B5612,
322 0x8F8, 0x400002C0,
323 0x8FC, 0x00000000,
324 0x900, 0x00000700,
325 0x90C, 0x00000000,
326 0x910, 0x0000FC00,
327 0x914, 0x00000404,
328 0x918, 0x1C1028C0,
329 0x91C, 0x64B11A1C,
330 0x920, 0xE0767233,
331 0x924, 0x055AA500,
332 0x928, 0x00000004,
333 0x92C, 0xFFFE0000,
334 0x930, 0xFFFFFFFE,
335 0x934, 0x001FFFFF,
336 0x960, 0x00000000,
337 0x964, 0x00000000,
338 0x968, 0x00000000,
339 0x96C, 0x00000000,
340 0x970, 0x801FFFFF,
341 0x974, 0x000003FF,
342 0x978, 0x00000000,
343 0x97C, 0x00000000,
344 0x980, 0x00000000,
345 0x984, 0x00000000,
346 0x988, 0x00000000,
347 0x990, 0x27100000,
348 0x994, 0xFFFF0100,
349 0x998, 0xFFFFFF5C,
350 0x99C, 0xFFFFFFFF,
351 0x9A0, 0x000000FF,
352 0x9A4, 0x00480080,
353 0x9A8, 0x00000000,
354 0x9AC, 0x00000000,
355 0x9B0, 0x81081008,
356 0x9B4, 0x01081008,
357 0x9B8, 0x01081008,
358 0x9BC, 0x01081008,
359 0x9D0, 0x00000000,
360 0x9D4, 0x00000000,
361 0x9D8, 0x00000000,
362 0x9DC, 0x00000000,
363 0x9E0, 0x00005D00,
364 0x9E4, 0x00000002,
365 0x9E8, 0x00000001,
366 0xA00, 0x00D047C8,
367 0xA04, 0x01FF000C,
368 0xA08, 0x8C8A8300,
369 0xA0C, 0x2E68000F,
370 0xA10, 0x9500BB78,
371 0xA14, 0x11144028,
372 0xA18, 0x00881117,
373 0xA1C, 0x89140F00,
374 0xA20, 0x1A1B0000,
375 0xA24, 0x090E1317,
376 0xA28, 0x00000204,
377 0xA2C, 0x00900000,
378 0xA70, 0x101FFF00,
379 0xA74, 0x00000008,
380 0xA78, 0x00000900,
381 0xA7C, 0x225B0606,
382 0xA80, 0x21805490,
383 0xA84, 0x001F0000,
384 0xB00, 0x03100040,
385 0xB04, 0x0000B000,
386 0xB08, 0xAE0201EB,
387 0xB0C, 0x01003207,
388 0xB10, 0x00009807,
389 0xB14, 0x01000000,
390 0xB18, 0x00000002,
391 0xB1C, 0x00000002,
392 0xB20, 0x0000001F,
393 0xB24, 0x03020100,
394 0xB28, 0x07060504,
395 0xB2C, 0x0B0A0908,
396 0xB30, 0x0F0E0D0C,
397 0xB34, 0x13121110,
398 0xB38, 0x17161514,
399 0xB3C, 0x0000003A,
400 0xB40, 0x00000000,
401 0xB44, 0x00000000,
402 0xB48, 0x13000032,
403 0xB4C, 0x48080000,
404 0xB50, 0x00000000,
405 0xB54, 0x00000000,
406 0xB58, 0x00000000,
407 0xB5C, 0x00000000,
408 0xC00, 0x00000007,
409 0xC04, 0x00042020,
410 0xC08, 0x80410231,
411 0xC0C, 0x00000000,
412 0xC10, 0x00000100,
413 0xC14, 0x01000000,
414 0xC1C, 0x40000003,
415 0xC20, 0x2C2C2C2C,
416 0xC24, 0x30303030,
417 0xC28, 0x30303030,
418 0xC2C, 0x2C2C2C2C,
419 0xC30, 0x2C2C2C2C,
420 0xC34, 0x2C2C2C2C,
421 0xC38, 0x2C2C2C2C,
422 0xC3C, 0x2A2A2A2A,
423 0xC40, 0x2A2A2A2A,
424 0xC44, 0x2A2A2A2A,
425 0xC48, 0x2A2A2A2A,
426 0xC4C, 0x2A2A2A2A,
427 0xC50, 0x00000020,
428 0xC54, 0x001C1208,
429 0xC58, 0x30000C1C,
430 0xC5C, 0x00000058,
431 0xC60, 0x34344443,
432 0xC64, 0x07003333,
433 0xC68, 0x19791979,
434 0xC6C, 0x19791979,
435 0xC70, 0x19791979,
436 0xC74, 0x19791979,
437 0xC78, 0x19791979,
438 0xC7C, 0x19791979,
439 0xC80, 0x19791979,
440 0xC84, 0x19791979,
441 0xC94, 0x0100005C,
442 0xC98, 0x00000000,
443 0xC9C, 0x00000000,
444 0xCA0, 0x00000029,
445 0xCA4, 0x08040201,
446 0xCA8, 0x80402010,
447 0xCB0, 0x77775747,
448 0xCB4, 0x10000077,
449 0xCB8, 0x00508240,
450};
451
452u32 RTL8812AE_PHY_REG_ARRAY_PG[] = {
453 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840,
454 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
455 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638,
456 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
457 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
458 0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
459 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
460 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
461 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
462 0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
463 0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
464 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
465 0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840,
466 0, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
467 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638,
468 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
469 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
470 0, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
471 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
472 0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
473 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
474 0, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
475 0, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
476 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628,
477 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
478 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640,
479 1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
480 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
481 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
482 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
483 1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
484 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
485 1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
486 1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
487 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
488 1, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
489 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323640,
490 1, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
491 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
492 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
493 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
494 1, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
495 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
496 1, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
497 1, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
498 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628
499};
500
501u32 RTL8821AE_PHY_REG_ARRAY_PG[] = {
502 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
503 0, 0, 0, 0x00000c24, 0xffffffff, 0x36363838,
504 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
505 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363838,
506 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
507 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
508 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
509 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022,
510 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343636,
511 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032,
512 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343636,
513 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830,
514 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
515 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
516 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022
517};
518
519u32 RTL8812AE_RADIOA_ARRAY[] = {
520 0x000, 0x00010000,
521 0x018, 0x0001712A,
522 0x056, 0x00051CF2,
523 0x066, 0x00040000,
524 0x01E, 0x00080000,
525 0x089, 0x00000080,
526 0xFF0F0740, 0xABCD,
527 0x086, 0x00014B38,
528 0xFF0F02C0, 0xCDEF,
529 0x086, 0x00014B38,
530 0xFF0F01C0, 0xCDEF,
531 0x086, 0x00014B38,
532 0xFF0F07D8, 0xCDEF,
533 0x086, 0x00014B3A,
534 0xFF0F07D0, 0xCDEF,
535 0x086, 0x00014B3A,
536 0xCDCDCDCD, 0xCDCD,
537 0x086, 0x00014B38,
538 0xFF0F0740, 0xDEAD,
539 0x0B1, 0x0001FC1A,
540 0x0B3, 0x000F0810,
541 0x0B4, 0x0001A78D,
542 0x0BA, 0x00086180,
543 0x018, 0x00000006,
544 0x0EF, 0x00002000,
545 0xFF0F07D8, 0xABCD,
546 0x03B, 0x0003F218,
547 0x03B, 0x00030A58,
548 0x03B, 0x0002FA58,
549 0x03B, 0x00022590,
550 0x03B, 0x0001FA50,
551 0x03B, 0x00010248,
552 0x03B, 0x00008240,
553 0xFF0F07D0, 0xCDEF,
554 0x03B, 0x0003F218,
555 0x03B, 0x00030A58,
556 0x03B, 0x0002FA58,
557 0x03B, 0x00022590,
558 0x03B, 0x0001FA50,
559 0x03B, 0x00010248,
560 0x03B, 0x00008240,
561 0xCDCDCDCD, 0xCDCD,
562 0x03B, 0x00038A58,
563 0x03B, 0x00037A58,
564 0x03B, 0x0002A590,
565 0x03B, 0x00027A50,
566 0x03B, 0x00018248,
567 0x03B, 0x00010240,
568 0x03B, 0x00008240,
569 0xFF0F07D8, 0xDEAD,
570 0x0EF, 0x00000100,
571 0xFF0F07D8, 0xABCD,
572 0x034, 0x0000A4EE,
573 0x034, 0x00009076,
574 0x034, 0x00008073,
575 0x034, 0x00007070,
576 0x034, 0x0000606D,
577 0x034, 0x0000506A,
578 0x034, 0x00004049,
579 0x034, 0x00003046,
580 0x034, 0x00002028,
581 0x034, 0x00001025,
582 0x034, 0x00000022,
583 0xCDCDCDCD, 0xCDCD,
584 0x034, 0x0000ADF4,
585 0x034, 0x00009DF1,
586 0x034, 0x00008DEE,
587 0x034, 0x00007DEB,
588 0x034, 0x00006DE8,
589 0x034, 0x00005CEC,
590 0x034, 0x00004CE9,
591 0x034, 0x000034EA,
592 0x034, 0x000024E7,
593 0x034, 0x0000146B,
594 0x034, 0x0000006D,
595 0xFF0F07D8, 0xDEAD,
596 0x0EF, 0x00000000,
597 0x0EF, 0x000020A2,
598 0x0DF, 0x00000080,
599 0x035, 0x00000192,
600 0x035, 0x00008192,
601 0x035, 0x00010192,
602 0x036, 0x00000024,
603 0x036, 0x00008024,
604 0x036, 0x00010024,
605 0x036, 0x00018024,
606 0x0EF, 0x00000000,
607 0x051, 0x00000C21,
608 0x052, 0x000006D9,
609 0x053, 0x000FC649,
610 0x054, 0x0000017E,
611 0x0EF, 0x00000002,
612 0x008, 0x00008400,
613 0x018, 0x0001712A,
614 0x0EF, 0x00001000,
615 0x03A, 0x00000080,
616 0x03B, 0x0003A02C,
617 0x03C, 0x00004000,
618 0x03A, 0x00000400,
619 0x03B, 0x0003202C,
620 0x03C, 0x00010000,
621 0x03A, 0x000000A0,
622 0x03B, 0x0002B064,
623 0x03C, 0x00004000,
624 0x03A, 0x000000D8,
625 0x03B, 0x00023070,
626 0x03C, 0x00004000,
627 0x03A, 0x00000468,
628 0x03B, 0x0001B870,
629 0x03C, 0x00010000,
630 0x03A, 0x00000098,
631 0x03B, 0x00012085,
632 0x03C, 0x000E4000,
633 0x03A, 0x00000418,
634 0x03B, 0x0000A080,
635 0x03C, 0x000F0000,
636 0x03A, 0x00000418,
637 0x03B, 0x00002080,
638 0x03C, 0x00010000,
639 0x03A, 0x00000080,
640 0x03B, 0x0007A02C,
641 0x03C, 0x00004000,
642 0x03A, 0x00000400,
643 0x03B, 0x0007202C,
644 0x03C, 0x00010000,
645 0x03A, 0x000000A0,
646 0x03B, 0x0006B064,
647 0x03C, 0x00004000,
648 0x03A, 0x000000D8,
649 0x03B, 0x00023070,
650 0x03C, 0x00004000,
651 0x03A, 0x00000468,
652 0x03B, 0x0005B870,
653 0x03C, 0x00010000,
654 0x03A, 0x00000098,
655 0x03B, 0x00052085,
656 0x03C, 0x000E4000,
657 0x03A, 0x00000418,
658 0x03B, 0x0004A080,
659 0x03C, 0x000F0000,
660 0x03A, 0x00000418,
661 0x03B, 0x00042080,
662 0x03C, 0x00010000,
663 0x03A, 0x00000080,
664 0x03B, 0x000BA02C,
665 0x03C, 0x00004000,
666 0x03A, 0x00000400,
667 0x03B, 0x000B202C,
668 0x03C, 0x00010000,
669 0x03A, 0x000000A0,
670 0x03B, 0x000AB064,
671 0x03C, 0x00004000,
672 0x03A, 0x000000D8,
673 0x03B, 0x000A3070,
674 0x03C, 0x00004000,
675 0x03A, 0x00000468,
676 0x03B, 0x0009B870,
677 0x03C, 0x00010000,
678 0x03A, 0x00000098,
679 0x03B, 0x00092085,
680 0x03C, 0x000E4000,
681 0x03A, 0x00000418,
682 0x03B, 0x0008A080,
683 0x03C, 0x000F0000,
684 0x03A, 0x00000418,
685 0x03B, 0x00082080,
686 0x03C, 0x00010000,
687 0x0EF, 0x00001100,
688 0xFF0F0740, 0xABCD,
689 0x034, 0x0004A0B2,
690 0x034, 0x000490AF,
691 0x034, 0x00048070,
692 0x034, 0x0004706D,
693 0x034, 0x00046050,
694 0x034, 0x0004504D,
695 0x034, 0x0004404A,
696 0x034, 0x00043047,
697 0x034, 0x0004200A,
698 0x034, 0x00041007,
699 0x034, 0x00040004,
700 0xFF0F02C0, 0xCDEF,
701 0x034, 0x0004A0B2,
702 0x034, 0x000490AF,
703 0x034, 0x00048070,
704 0x034, 0x0004706D,
705 0x034, 0x00046050,
706 0x034, 0x0004504D,
707 0x034, 0x0004404A,
708 0x034, 0x00043047,
709 0x034, 0x0004200A,
710 0x034, 0x00041007,
711 0x034, 0x00040004,
712 0xFF0F01C0, 0xCDEF,
713 0x034, 0x0004A0B2,
714 0x034, 0x000490AF,
715 0x034, 0x00048070,
716 0x034, 0x0004706D,
717 0x034, 0x00046050,
718 0x034, 0x0004504D,
719 0x034, 0x0004404A,
720 0x034, 0x00043047,
721 0x034, 0x0004200A,
722 0x034, 0x00041007,
723 0x034, 0x00040004,
724 0xFF0F07D8, 0xCDEF,
725 0x034, 0x0004A0B2,
726 0x034, 0x000490AF,
727 0x034, 0x00048070,
728 0x034, 0x0004706D,
729 0x034, 0x00046050,
730 0x034, 0x0004504D,
731 0x034, 0x0004404A,
732 0x034, 0x00043047,
733 0x034, 0x0004200A,
734 0x034, 0x00041007,
735 0x034, 0x00040004,
736 0xFF0F07D0, 0xCDEF,
737 0x034, 0x0004A0B2,
738 0x034, 0x000490AF,
739 0x034, 0x00048070,
740 0x034, 0x0004706D,
741 0x034, 0x00046050,
742 0x034, 0x0004504D,
743 0x034, 0x0004404A,
744 0x034, 0x00043047,
745 0x034, 0x0004200A,
746 0x034, 0x00041007,
747 0x034, 0x00040004,
748 0xCDCDCDCD, 0xCDCD,
749 0x034, 0x0004ADF5,
750 0x034, 0x00049DF2,
751 0x034, 0x00048DEF,
752 0x034, 0x00047DEC,
753 0x034, 0x00046DE9,
754 0x034, 0x00045DC9,
755 0x034, 0x00044CE8,
756 0x034, 0x000438CA,
757 0x034, 0x00042889,
758 0x034, 0x0004184A,
759 0x034, 0x0004044A,
760 0xFF0F0740, 0xDEAD,
761 0xFF0F0740, 0xABCD,
762 0x034, 0x0002A0B2,
763 0x034, 0x000290AF,
764 0x034, 0x00028070,
765 0x034, 0x0002706D,
766 0x034, 0x00026050,
767 0x034, 0x0002504D,
768 0x034, 0x0002404A,
769 0x034, 0x00023047,
770 0x034, 0x0002200A,
771 0x034, 0x00021007,
772 0x034, 0x00020004,
773 0xFF0F02C0, 0xCDEF,
774 0x034, 0x0002A0B2,
775 0x034, 0x000290AF,
776 0x034, 0x00028070,
777 0x034, 0x0002706D,
778 0x034, 0x00026050,
779 0x034, 0x0002504D,
780 0x034, 0x0002404A,
781 0x034, 0x00023047,
782 0x034, 0x0002200A,
783 0x034, 0x00021007,
784 0x034, 0x00020004,
785 0xFF0F01C0, 0xCDEF,
786 0x034, 0x0002A0B2,
787 0x034, 0x000290AF,
788 0x034, 0x00028070,
789 0x034, 0x0002706D,
790 0x034, 0x00026050,
791 0x034, 0x0002504D,
792 0x034, 0x0002404A,
793 0x034, 0x00023047,
794 0x034, 0x0002200A,
795 0x034, 0x00021007,
796 0x034, 0x00020004,
797 0xFF0F07D8, 0xCDEF,
798 0x034, 0x0002A0B2,
799 0x034, 0x000290AF,
800 0x034, 0x00028070,
801 0x034, 0x0002706D,
802 0x034, 0x00026050,
803 0x034, 0x0002504D,
804 0x034, 0x0002404A,
805 0x034, 0x00023047,
806 0x034, 0x0002200A,
807 0x034, 0x00021007,
808 0x034, 0x00020004,
809 0xFF0F07D0, 0xCDEF,
810 0x034, 0x0002A0B2,
811 0x034, 0x000290AF,
812 0x034, 0x00028070,
813 0x034, 0x0002706D,
814 0x034, 0x00026050,
815 0x034, 0x0002504D,
816 0x034, 0x0002404A,
817 0x034, 0x00023047,
818 0x034, 0x0002200A,
819 0x034, 0x00021007,
820 0x034, 0x00020004,
821 0xCDCDCDCD, 0xCDCD,
822 0x034, 0x0002ADF5,
823 0x034, 0x00029DF2,
824 0x034, 0x00028DEF,
825 0x034, 0x00027DEC,
826 0x034, 0x00026DE9,
827 0x034, 0x00025DC9,
828 0x034, 0x00024CE8,
829 0x034, 0x000238CA,
830 0x034, 0x00022889,
831 0x034, 0x0002184A,
832 0x034, 0x0002044A,
833 0xFF0F0740, 0xDEAD,
834 0xFF0F0740, 0xABCD,
835 0x034, 0x0000A0B2,
836 0x034, 0x000090AF,
837 0x034, 0x00008070,
838 0x034, 0x0000706D,
839 0x034, 0x00006050,
840 0x034, 0x0000504D,
841 0x034, 0x0000404A,
842 0x034, 0x00003047,
843 0x034, 0x0000200A,
844 0x034, 0x00001007,
845 0x034, 0x00000004,
846 0xFF0F02C0, 0xCDEF,
847 0x034, 0x0000A0B2,
848 0x034, 0x000090AF,
849 0x034, 0x00008070,
850 0x034, 0x0000706D,
851 0x034, 0x00006050,
852 0x034, 0x0000504D,
853 0x034, 0x0000404A,
854 0x034, 0x00003047,
855 0x034, 0x0000200A,
856 0x034, 0x00001007,
857 0x034, 0x00000004,
858 0xFF0F01C0, 0xCDEF,
859 0x034, 0x0000A0B2,
860 0x034, 0x000090AF,
861 0x034, 0x00008070,
862 0x034, 0x0000706D,
863 0x034, 0x00006050,
864 0x034, 0x0000504D,
865 0x034, 0x0000404A,
866 0x034, 0x00003047,
867 0x034, 0x0000200A,
868 0x034, 0x00001007,
869 0x034, 0x00000004,
870 0xFF0F07D8, 0xCDEF,
871 0x034, 0x0000A0B2,
872 0x034, 0x000090AF,
873 0x034, 0x00008070,
874 0x034, 0x0000706D,
875 0x034, 0x00006050,
876 0x034, 0x0000504D,
877 0x034, 0x0000404A,
878 0x034, 0x00003047,
879 0x034, 0x0000200A,
880 0x034, 0x00001007,
881 0x034, 0x00000004,
882 0xFF0F07D0, 0xCDEF,
883 0x034, 0x0000A0B2,
884 0x034, 0x000090AF,
885 0x034, 0x00008070,
886 0x034, 0x0000706D,
887 0x034, 0x00006050,
888 0x034, 0x0000504D,
889 0x034, 0x0000404A,
890 0x034, 0x00003047,
891 0x034, 0x0000200A,
892 0x034, 0x00001007,
893 0x034, 0x00000004,
894 0xCDCDCDCD, 0xCDCD,
895 0x034, 0x0000AFF7,
896 0x034, 0x00009DF7,
897 0x034, 0x00008DF4,
898 0x034, 0x00007DF1,
899 0x034, 0x00006DEE,
900 0x034, 0x00005DCD,
901 0x034, 0x00004CEB,
902 0x034, 0x000038CC,
903 0x034, 0x0000288B,
904 0x034, 0x0000184C,
905 0x034, 0x0000044C,
906 0xFF0F0740, 0xDEAD,
907 0x0EF, 0x00000000,
908 0xFF0F0740, 0xABCD,
909 0x018, 0x0001712A,
910 0x0EF, 0x00000040,
911 0x035, 0x000001D4,
912 0x035, 0x000081D4,
913 0x035, 0x000101D4,
914 0x035, 0x000201B4,
915 0x035, 0x000281B4,
916 0x035, 0x000301B4,
917 0x035, 0x000401B4,
918 0x035, 0x000481B4,
919 0x035, 0x000501B4,
920 0xFF0F02C0, 0xCDEF,
921 0x018, 0x0001712A,
922 0x0EF, 0x00000040,
923 0x035, 0x000001D4,
924 0x035, 0x000081D4,
925 0x035, 0x000101D4,
926 0x035, 0x000201B4,
927 0x035, 0x000281B4,
928 0x035, 0x000301B4,
929 0x035, 0x000401B4,
930 0x035, 0x000481B4,
931 0x035, 0x000501B4,
932 0xFF0F01C0, 0xCDEF,
933 0x018, 0x0001712A,
934 0x0EF, 0x00000040,
935 0x035, 0x000001D4,
936 0x035, 0x000081D4,
937 0x035, 0x000101D4,
938 0x035, 0x000201B4,
939 0x035, 0x000281B4,
940 0x035, 0x000301B4,
941 0x035, 0x000401B4,
942 0x035, 0x000481B4,
943 0x035, 0x000501B4,
944 0xFF0F07D8, 0xCDEF,
945 0x018, 0x0001712A,
946 0x0EF, 0x00000040,
947 0x035, 0x000001D4,
948 0x035, 0x000081D4,
949 0x035, 0x000101D4,
950 0x035, 0x000201B4,
951 0x035, 0x000281B4,
952 0x035, 0x000301B4,
953 0x035, 0x000401B4,
954 0x035, 0x000481B4,
955 0x035, 0x000501B4,
956 0xFF0F07D0, 0xCDEF,
957 0x018, 0x0001712A,
958 0x0EF, 0x00000040,
959 0x035, 0x000001D4,
960 0x035, 0x000081D4,
961 0x035, 0x000101D4,
962 0x035, 0x000201B4,
963 0x035, 0x000281B4,
964 0x035, 0x000301B4,
965 0x035, 0x000401B4,
966 0x035, 0x000481B4,
967 0x035, 0x000501B4,
968 0xCDCDCDCD, 0xCDCD,
969 0x018, 0x0001712A,
970 0x0EF, 0x00000040,
971 0x035, 0x00000188,
972 0x035, 0x00008147,
973 0x035, 0x00010147,
974 0x035, 0x000201D7,
975 0x035, 0x000281D7,
976 0x035, 0x000301D7,
977 0x035, 0x000401D8,
978 0x035, 0x000481D8,
979 0x035, 0x000501D8,
980 0xFF0F0740, 0xDEAD,
981 0x0EF, 0x00000000,
982 0xFF0F0740, 0xABCD,
983 0x018, 0x0001712A,
984 0x0EF, 0x00000010,
985 0x036, 0x00004BFB,
986 0x036, 0x0000CBFB,
987 0x036, 0x00014BFB,
988 0x036, 0x0001CBFB,
989 0x036, 0x00024F4B,
990 0x036, 0x0002CF4B,
991 0x036, 0x00034F4B,
992 0x036, 0x0003CF4B,
993 0x036, 0x00044F4B,
994 0x036, 0x0004CF4B,
995 0x036, 0x00054F4B,
996 0x036, 0x0005CF4B,
997 0xFF0F02C0, 0xCDEF,
998 0x018, 0x0001712A,
999 0x0EF, 0x00000010,
1000 0x036, 0x00004BFB,
1001 0x036, 0x0000CBFB,
1002 0x036, 0x00014BFB,
1003 0x036, 0x0001CBFB,
1004 0x036, 0x00024F4B,
1005 0x036, 0x0002CF4B,
1006 0x036, 0x00034F4B,
1007 0x036, 0x0003CF4B,
1008 0x036, 0x00044F4B,
1009 0x036, 0x0004CF4B,
1010 0x036, 0x00054F4B,
1011 0x036, 0x0005CF4B,
1012 0xFF0F01C0, 0xCDEF,
1013 0x018, 0x0001712A,
1014 0x0EF, 0x00000010,
1015 0x036, 0x00004BFB,
1016 0x036, 0x0000CBFB,
1017 0x036, 0x00014BFB,
1018 0x036, 0x0001CBFB,
1019 0x036, 0x00024F4B,
1020 0x036, 0x0002CF4B,
1021 0x036, 0x00034F4B,
1022 0x036, 0x0003CF4B,
1023 0x036, 0x00044F4B,
1024 0x036, 0x0004CF4B,
1025 0x036, 0x00054F4B,
1026 0x036, 0x0005CF4B,
1027 0xFF0F07D8, 0xCDEF,
1028 0x018, 0x0001712A,
1029 0x0EF, 0x00000010,
1030 0x036, 0x00004BFB,
1031 0x036, 0x0000CBFB,
1032 0x036, 0x00014BFB,
1033 0x036, 0x0001CBFB,
1034 0x036, 0x00024F4B,
1035 0x036, 0x0002CF4B,
1036 0x036, 0x00034F4B,
1037 0x036, 0x0003CF4B,
1038 0x036, 0x00044F4B,
1039 0x036, 0x0004CF4B,
1040 0x036, 0x00054F4B,
1041 0x036, 0x0005CF4B,
1042 0xFF0F07D0, 0xCDEF,
1043 0x018, 0x0001712A,
1044 0x0EF, 0x00000010,
1045 0x036, 0x00004BFB,
1046 0x036, 0x0000CBFB,
1047 0x036, 0x00014BFB,
1048 0x036, 0x0001CBFB,
1049 0x036, 0x00024F4B,
1050 0x036, 0x0002CF4B,
1051 0x036, 0x00034F4B,
1052 0x036, 0x0003CF4B,
1053 0x036, 0x00044F4B,
1054 0x036, 0x0004CF4B,
1055 0x036, 0x00054F4B,
1056 0x036, 0x0005CF4B,
1057 0xCDCDCDCD, 0xCDCD,
1058 0x018, 0x0001712A,
1059 0x0EF, 0x00000010,
1060 0x036, 0x00084EB4,
1061 0x036, 0x0008CC35,
1062 0x036, 0x00094C35,
1063 0x036, 0x0009CC35,
1064 0x036, 0x000A4935,
1065 0x036, 0x000ACC35,
1066 0x036, 0x000B4C35,
1067 0x036, 0x000BCC35,
1068 0x036, 0x000C4EB4,
1069 0x036, 0x000CCEB5,
1070 0x036, 0x000D4EB5,
1071 0x036, 0x000DCEB5,
1072 0xFF0F0740, 0xDEAD,
1073 0x0EF, 0x00000000,
1074 0x0EF, 0x00000008,
1075 0xFF0F0740, 0xABCD,
1076 0x03C, 0x000002CC,
1077 0x03C, 0x00000522,
1078 0x03C, 0x00000902,
1079 0xFF0F02C0, 0xCDEF,
1080 0x03C, 0x000002CC,
1081 0x03C, 0x00000522,
1082 0x03C, 0x00000902,
1083 0xFF0F01C0, 0xCDEF,
1084 0x03C, 0x000002CC,
1085 0x03C, 0x00000522,
1086 0x03C, 0x00000902,
1087 0xFF0F07D8, 0xCDEF,
1088 0x03C, 0x000002CC,
1089 0x03C, 0x00000522,
1090 0x03C, 0x00000902,
1091 0xFF0F07D0, 0xCDEF,
1092 0x03C, 0x000002CC,
1093 0x03C, 0x00000522,
1094 0x03C, 0x00000902,
1095 0xCDCDCDCD, 0xCDCD,
1096 0x03C, 0x000002A8,
1097 0x03C, 0x000005A2,
1098 0x03C, 0x00000880,
1099 0xFF0F0740, 0xDEAD,
1100 0x0EF, 0x00000000,
1101 0x018, 0x0001712A,
1102 0x0EF, 0x00000002,
1103 0x0DF, 0x00000080,
1104 0x01F, 0x00040064,
1105 0xFF0F0740, 0xABCD,
1106 0x061, 0x000FDD43,
1107 0x062, 0x00038F4B,
1108 0x063, 0x00032117,
1109 0x064, 0x000194AC,
1110 0x065, 0x000931D1,
1111 0xFF0F02C0, 0xCDEF,
1112 0x061, 0x000FDD43,
1113 0x062, 0x00038F4B,
1114 0x063, 0x00032117,
1115 0x064, 0x000194AC,
1116 0x065, 0x000931D1,
1117 0xFF0F01C0, 0xCDEF,
1118 0x061, 0x000FDD43,
1119 0x062, 0x00038F4B,
1120 0x063, 0x00032117,
1121 0x064, 0x000194AC,
1122 0x065, 0x000931D1,
1123 0xFF0F07D8, 0xCDEF,
1124 0x061, 0x000FDD43,
1125 0x062, 0x00038F4B,
1126 0x063, 0x00032117,
1127 0x064, 0x000194AC,
1128 0x065, 0x000931D1,
1129 0xFF0F07D0, 0xCDEF,
1130 0x061, 0x000FDD43,
1131 0x062, 0x00038F4B,
1132 0x063, 0x00032117,
1133 0x064, 0x000194AC,
1134 0x065, 0x000931D1,
1135 0xCDCDCDCD, 0xCDCD,
1136 0x061, 0x000E5D53,
1137 0x062, 0x00038FCD,
1138 0x063, 0x000314EB,
1139 0x064, 0x000196AC,
1140 0x065, 0x000911D7,
1141 0xFF0F0740, 0xDEAD,
1142 0x008, 0x00008400,
1143 0x01C, 0x000739D2,
1144 0x0B4, 0x0001E78D,
1145 0x018, 0x0001F12A,
1146 0x0FE, 0x00000000,
1147 0x0FE, 0x00000000,
1148 0x0FE, 0x00000000,
1149 0x0FE, 0x00000000,
1150 0x0B4, 0x0001A78D,
1151 0x018, 0x0001712A,
1152
1153};
1154
1155u32 RTL8812AE_RADIOB_ARRAY[] = {
1156 0x056, 0x00051CF2,
1157 0x066, 0x00040000,
1158 0x089, 0x00000080,
1159 0xFF0F0740, 0xABCD,
1160 0x086, 0x00014B38,
1161 0xFF0F01C0, 0xCDEF,
1162 0x086, 0x00014B38,
1163 0xFF0F02C0, 0xCDEF,
1164 0x086, 0x00014B38,
1165 0xFF0F07D8, 0xCDEF,
1166 0x086, 0x00014B3A,
1167 0xFF0F07D0, 0xCDEF,
1168 0x086, 0x00014B3A,
1169 0xCDCDCDCD, 0xCDCD,
1170 0x086, 0x00014B38,
1171 0xFF0F0740, 0xDEAD,
1172 0x018, 0x00000006,
1173 0x0EF, 0x00002000,
1174 0xFF0F07D8, 0xABCD,
1175 0x03B, 0x0003F218,
1176 0x03B, 0x00030A58,
1177 0x03B, 0x0002FA58,
1178 0x03B, 0x00022590,
1179 0x03B, 0x0001FA50,
1180 0x03B, 0x00010248,
1181 0x03B, 0x00008240,
1182 0xFF0F07D0, 0xCDEF,
1183 0x03B, 0x0003F218,
1184 0x03B, 0x00030A58,
1185 0x03B, 0x0002FA58,
1186 0x03B, 0x00022590,
1187 0x03B, 0x0001FA50,
1188 0x03B, 0x00010248,
1189 0x03B, 0x00008240,
1190 0xCDCDCDCD, 0xCDCD,
1191 0x03B, 0x00038A58,
1192 0x03B, 0x00037A58,
1193 0x03B, 0x0002A590,
1194 0x03B, 0x00027A50,
1195 0x03B, 0x00018248,
1196 0x03B, 0x00010240,
1197 0x03B, 0x00008240,
1198 0xFF0F07D8, 0xDEAD,
1199 0x0EF, 0x00000100,
1200 0xFF0F07D8, 0xABCD,
1201 0x034, 0x0000A4EE,
1202 0x034, 0x00009076,
1203 0x034, 0x00008073,
1204 0x034, 0x00007070,
1205 0x034, 0x0000606D,
1206 0x034, 0x0000506A,
1207 0x034, 0x00004049,
1208 0x034, 0x00003046,
1209 0x034, 0x00002028,
1210 0x034, 0x00001025,
1211 0x034, 0x00000022,
1212 0xCDCDCDCD, 0xCDCD,
1213 0x034, 0x0000ADF4,
1214 0x034, 0x00009DF1,
1215 0x034, 0x00008DEE,
1216 0x034, 0x00007DEB,
1217 0x034, 0x00006DE8,
1218 0x034, 0x00005CEC,
1219 0x034, 0x00004CE9,
1220 0x034, 0x000034EA,
1221 0x034, 0x000024E7,
1222 0x034, 0x0000146B,
1223 0x034, 0x0000006D,
1224 0xFF0F07D8, 0xDEAD,
1225 0x0EF, 0x00000000,
1226 0x0EF, 0x000020A2,
1227 0x0DF, 0x00000080,
1228 0x035, 0x00000192,
1229 0x035, 0x00008192,
1230 0x035, 0x00010192,
1231 0x036, 0x00000024,
1232 0x036, 0x00008024,
1233 0x036, 0x00010024,
1234 0x036, 0x00018024,
1235 0x0EF, 0x00000000,
1236 0x051, 0x00000C21,
1237 0x052, 0x000006D9,
1238 0x053, 0x000FC649,
1239 0x054, 0x0000017E,
1240 0x0EF, 0x00000002,
1241 0x008, 0x00008400,
1242 0x018, 0x0001712A,
1243 0x0EF, 0x00001000,
1244 0x03A, 0x00000080,
1245 0x03B, 0x0003A02C,
1246 0x03C, 0x00004000,
1247 0x03A, 0x00000400,
1248 0x03B, 0x0003202C,
1249 0x03C, 0x00010000,
1250 0x03A, 0x000000A0,
1251 0x03B, 0x0002B064,
1252 0x03C, 0x00004000,
1253 0x03A, 0x000000D8,
1254 0x03B, 0x00023070,
1255 0x03C, 0x00004000,
1256 0x03A, 0x00000468,
1257 0x03B, 0x0001B870,
1258 0x03C, 0x00010000,
1259 0x03A, 0x00000098,
1260 0x03B, 0x00012085,
1261 0x03C, 0x000E4000,
1262 0x03A, 0x00000418,
1263 0x03B, 0x0000A080,
1264 0x03C, 0x000F0000,
1265 0x03A, 0x00000418,
1266 0x03B, 0x00002080,
1267 0x03C, 0x00010000,
1268 0x03A, 0x00000080,
1269 0x03B, 0x0007A02C,
1270 0x03C, 0x00004000,
1271 0x03A, 0x00000400,
1272 0x03B, 0x0007202C,
1273 0x03C, 0x00010000,
1274 0x03A, 0x000000A0,
1275 0x03B, 0x0006B064,
1276 0x03C, 0x00004000,
1277 0x03A, 0x000000D8,
1278 0x03B, 0x00063070,
1279 0x03C, 0x00004000,
1280 0x03A, 0x00000468,
1281 0x03B, 0x0005B870,
1282 0x03C, 0x00010000,
1283 0x03A, 0x00000098,
1284 0x03B, 0x00052085,
1285 0x03C, 0x000E4000,
1286 0x03A, 0x00000418,
1287 0x03B, 0x0004A080,
1288 0x03C, 0x000F0000,
1289 0x03A, 0x00000418,
1290 0x03B, 0x00042080,
1291 0x03C, 0x00010000,
1292 0x03A, 0x00000080,
1293 0x03B, 0x000BA02C,
1294 0x03C, 0x00004000,
1295 0x03A, 0x00000400,
1296 0x03B, 0x000B202C,
1297 0x03C, 0x00010000,
1298 0x03A, 0x000000A0,
1299 0x03B, 0x000AB064,
1300 0x03C, 0x00004000,
1301 0x03A, 0x000000D8,
1302 0x03B, 0x000A3070,
1303 0x03C, 0x00004000,
1304 0x03A, 0x00000468,
1305 0x03B, 0x0009B870,
1306 0x03C, 0x00010000,
1307 0x03A, 0x00000098,
1308 0x03B, 0x00092085,
1309 0x03C, 0x000E4000,
1310 0x03A, 0x00000418,
1311 0x03B, 0x0008A080,
1312 0x03C, 0x000F0000,
1313 0x03A, 0x00000418,
1314 0x03B, 0x00082080,
1315 0x03C, 0x00010000,
1316 0x0EF, 0x00001100,
1317 0xFF0F0740, 0xABCD,
1318 0x034, 0x0004A0B2,
1319 0x034, 0x000490AF,
1320 0x034, 0x00048070,
1321 0x034, 0x0004706D,
1322 0x034, 0x00046050,
1323 0x034, 0x0004504D,
1324 0x034, 0x0004404A,
1325 0x034, 0x00043047,
1326 0x034, 0x0004200A,
1327 0x034, 0x00041007,
1328 0x034, 0x00040004,
1329 0xFF0F01C0, 0xCDEF,
1330 0x034, 0x0004A0B2,
1331 0x034, 0x000490AF,
1332 0x034, 0x00048070,
1333 0x034, 0x0004706D,
1334 0x034, 0x00046050,
1335 0x034, 0x0004504D,
1336 0x034, 0x0004404A,
1337 0x034, 0x00043047,
1338 0x034, 0x0004200A,
1339 0x034, 0x00041007,
1340 0x034, 0x00040004,
1341 0xFF0F02C0, 0xCDEF,
1342 0x034, 0x0004A0B2,
1343 0x034, 0x000490AF,
1344 0x034, 0x00048070,
1345 0x034, 0x0004706D,
1346 0x034, 0x00046050,
1347 0x034, 0x0004504D,
1348 0x034, 0x0004404A,
1349 0x034, 0x00043047,
1350 0x034, 0x0004200A,
1351 0x034, 0x00041007,
1352 0x034, 0x00040004,
1353 0xFF0F07D8, 0xCDEF,
1354 0x034, 0x0004A0B2,
1355 0x034, 0x000490AF,
1356 0x034, 0x00048070,
1357 0x034, 0x0004706D,
1358 0x034, 0x00046050,
1359 0x034, 0x0004504D,
1360 0x034, 0x0004404A,
1361 0x034, 0x00043047,
1362 0x034, 0x0004200A,
1363 0x034, 0x00041007,
1364 0x034, 0x00040004,
1365 0xFF0F07D0, 0xCDEF,
1366 0x034, 0x0004A0B2,
1367 0x034, 0x000490AF,
1368 0x034, 0x00048070,
1369 0x034, 0x0004706D,
1370 0x034, 0x00046050,
1371 0x034, 0x0004504D,
1372 0x034, 0x0004404A,
1373 0x034, 0x00043047,
1374 0x034, 0x0004200A,
1375 0x034, 0x00041007,
1376 0x034, 0x00040004,
1377 0xCDCDCDCD, 0xCDCD,
1378 0x034, 0x0004ADF5,
1379 0x034, 0x00049DF2,
1380 0x034, 0x00048DEF,
1381 0x034, 0x00047DEC,
1382 0x034, 0x00046DE9,
1383 0x034, 0x00045DC9,
1384 0x034, 0x00044CE8,
1385 0x034, 0x000438CA,
1386 0x034, 0x00042889,
1387 0x034, 0x0004184A,
1388 0x034, 0x0004044A,
1389 0xFF0F0740, 0xDEAD,
1390 0xFF0F0740, 0xABCD,
1391 0x034, 0x0002A0B2,
1392 0x034, 0x000290AF,
1393 0x034, 0x00028070,
1394 0x034, 0x0002706D,
1395 0x034, 0x00026050,
1396 0x034, 0x0002504D,
1397 0x034, 0x0002404A,
1398 0x034, 0x00023047,
1399 0x034, 0x0002200A,
1400 0x034, 0x00021007,
1401 0x034, 0x00020004,
1402 0xFF0F01C0, 0xCDEF,
1403 0x034, 0x0002A0B2,
1404 0x034, 0x000290AF,
1405 0x034, 0x00028070,
1406 0x034, 0x0002706D,
1407 0x034, 0x00026050,
1408 0x034, 0x0002504D,
1409 0x034, 0x0002404A,
1410 0x034, 0x00023047,
1411 0x034, 0x0002200A,
1412 0x034, 0x00021007,
1413 0x034, 0x00020004,
1414 0xFF0F02C0, 0xCDEF,
1415 0x034, 0x0002A0B2,
1416 0x034, 0x000290AF,
1417 0x034, 0x00028070,
1418 0x034, 0x0002706D,
1419 0x034, 0x00026050,
1420 0x034, 0x0002504D,
1421 0x034, 0x0002404A,
1422 0x034, 0x00023047,
1423 0x034, 0x0002200A,
1424 0x034, 0x00021007,
1425 0x034, 0x00020004,
1426 0xFF0F07D8, 0xCDEF,
1427 0x034, 0x0002A0B2,
1428 0x034, 0x000290AF,
1429 0x034, 0x00028070,
1430 0x034, 0x0002706D,
1431 0x034, 0x00026050,
1432 0x034, 0x0002504D,
1433 0x034, 0x0002404A,
1434 0x034, 0x00023047,
1435 0x034, 0x0002200A,
1436 0x034, 0x00021007,
1437 0x034, 0x00020004,
1438 0xFF0F07D0, 0xCDEF,
1439 0x034, 0x0002A0B2,
1440 0x034, 0x000290AF,
1441 0x034, 0x00028070,
1442 0x034, 0x0002706D,
1443 0x034, 0x00026050,
1444 0x034, 0x0002504D,
1445 0x034, 0x0002404A,
1446 0x034, 0x00023047,
1447 0x034, 0x0002200A,
1448 0x034, 0x00021007,
1449 0x034, 0x00020004,
1450 0xCDCDCDCD, 0xCDCD,
1451 0x034, 0x0002ADF5,
1452 0x034, 0x00029DF2,
1453 0x034, 0x00028DEF,
1454 0x034, 0x00027DEC,
1455 0x034, 0x00026DE9,
1456 0x034, 0x00025DC9,
1457 0x034, 0x00024CE8,
1458 0x034, 0x000238CA,
1459 0x034, 0x00022889,
1460 0x034, 0x0002184A,
1461 0x034, 0x0002044A,
1462 0xFF0F0740, 0xDEAD,
1463 0xFF0F0740, 0xABCD,
1464 0x034, 0x0000A0B2,
1465 0x034, 0x000090AF,
1466 0x034, 0x00008070,
1467 0x034, 0x0000706D,
1468 0x034, 0x00006050,
1469 0x034, 0x0000504D,
1470 0x034, 0x0000404A,
1471 0x034, 0x00003047,
1472 0x034, 0x0000200A,
1473 0x034, 0x00001007,
1474 0x034, 0x00000004,
1475 0xFF0F01C0, 0xCDEF,
1476 0x034, 0x0000A0B2,
1477 0x034, 0x000090AF,
1478 0x034, 0x00008070,
1479 0x034, 0x0000706D,
1480 0x034, 0x00006050,
1481 0x034, 0x0000504D,
1482 0x034, 0x0000404A,
1483 0x034, 0x00003047,
1484 0x034, 0x0000200A,
1485 0x034, 0x00001007,
1486 0x034, 0x00000004,
1487 0xFF0F02C0, 0xCDEF,
1488 0x034, 0x0000A0B2,
1489 0x034, 0x000090AF,
1490 0x034, 0x00008070,
1491 0x034, 0x0000706D,
1492 0x034, 0x00006050,
1493 0x034, 0x0000504D,
1494 0x034, 0x0000404A,
1495 0x034, 0x00003047,
1496 0x034, 0x0000200A,
1497 0x034, 0x00001007,
1498 0x034, 0x00000004,
1499 0xFF0F07D8, 0xCDEF,
1500 0x034, 0x0000A0B2,
1501 0x034, 0x000090AF,
1502 0x034, 0x00008070,
1503 0x034, 0x0000706D,
1504 0x034, 0x00006050,
1505 0x034, 0x0000504D,
1506 0x034, 0x0000404A,
1507 0x034, 0x00003047,
1508 0x034, 0x0000200A,
1509 0x034, 0x00001007,
1510 0x034, 0x00000004,
1511 0xFF0F07D0, 0xCDEF,
1512 0x034, 0x0000A0B2,
1513 0x034, 0x000090AF,
1514 0x034, 0x00008070,
1515 0x034, 0x0000706D,
1516 0x034, 0x00006050,
1517 0x034, 0x0000504D,
1518 0x034, 0x0000404A,
1519 0x034, 0x00003047,
1520 0x034, 0x0000200A,
1521 0x034, 0x00001007,
1522 0x034, 0x00000004,
1523 0xCDCDCDCD, 0xCDCD,
1524 0x034, 0x0000AFF7,
1525 0x034, 0x00009DF7,
1526 0x034, 0x00008DF4,
1527 0x034, 0x00007DF1,
1528 0x034, 0x00006DEE,
1529 0x034, 0x00005DCD,
1530 0x034, 0x00004CEB,
1531 0x034, 0x000038CC,
1532 0x034, 0x0000288B,
1533 0x034, 0x0000184C,
1534 0x034, 0x0000044C,
1535 0xFF0F0740, 0xDEAD,
1536 0x0EF, 0x00000000,
1537 0xFF0F0740, 0xABCD,
1538 0x018, 0x0001712A,
1539 0x0EF, 0x00000040,
1540 0x035, 0x000001C5,
1541 0x035, 0x000081C5,
1542 0x035, 0x000101C5,
1543 0x035, 0x00020174,
1544 0x035, 0x00028174,
1545 0x035, 0x00030174,
1546 0x035, 0x00040185,
1547 0x035, 0x00048185,
1548 0x035, 0x00050185,
1549 0x0EF, 0x00000000,
1550 0xFF0F01C0, 0xCDEF,
1551 0x018, 0x0001712A,
1552 0x0EF, 0x00000040,
1553 0x035, 0x000001C5,
1554 0x035, 0x000081C5,
1555 0x035, 0x000101C5,
1556 0x035, 0x00020174,
1557 0x035, 0x00028174,
1558 0x035, 0x00030174,
1559 0x035, 0x00040185,
1560 0x035, 0x00048185,
1561 0x035, 0x00050185,
1562 0x0EF, 0x00000000,
1563 0xFF0F02C0, 0xCDEF,
1564 0x018, 0x0001712A,
1565 0x0EF, 0x00000040,
1566 0x035, 0x000001C5,
1567 0x035, 0x000081C5,
1568 0x035, 0x000101C5,
1569 0x035, 0x00020174,
1570 0x035, 0x00028174,
1571 0x035, 0x00030174,
1572 0x035, 0x00040185,
1573 0x035, 0x00048185,
1574 0x035, 0x00050185,
1575 0x0EF, 0x00000000,
1576 0xFF0F07D8, 0xCDEF,
1577 0x018, 0x0001712A,
1578 0x0EF, 0x00000040,
1579 0x035, 0x000001C5,
1580 0x035, 0x000081C5,
1581 0x035, 0x000101C5,
1582 0x035, 0x00020174,
1583 0x035, 0x00028174,
1584 0x035, 0x00030174,
1585 0x035, 0x00040185,
1586 0x035, 0x00048185,
1587 0x035, 0x00050185,
1588 0x0EF, 0x00000000,
1589 0xFF0F07D0, 0xCDEF,
1590 0x018, 0x0001712A,
1591 0x0EF, 0x00000040,
1592 0x035, 0x000001C5,
1593 0x035, 0x000081C5,
1594 0x035, 0x000101C5,
1595 0x035, 0x00020174,
1596 0x035, 0x00028174,
1597 0x035, 0x00030174,
1598 0x035, 0x00040185,
1599 0x035, 0x00048185,
1600 0x035, 0x00050185,
1601 0x0EF, 0x00000000,
1602 0xCDCDCDCD, 0xCDCD,
1603 0x018, 0x0001712A,
1604 0x0EF, 0x00000040,
1605 0x035, 0x00000186,
1606 0x035, 0x00008186,
1607 0x035, 0x00010185,
1608 0x035, 0x000201D5,
1609 0x035, 0x000281D5,
1610 0x035, 0x000301D5,
1611 0x035, 0x000401D5,
1612 0x035, 0x000481D5,
1613 0x035, 0x000501D5,
1614 0x0EF, 0x00000000,
1615 0xFF0F0740, 0xDEAD,
1616 0xFF0F0740, 0xABCD,
1617 0x018, 0x0001712A,
1618 0x0EF, 0x00000010,
1619 0x036, 0x00005B8B,
1620 0x036, 0x0000DB8B,
1621 0x036, 0x00015B8B,
1622 0x036, 0x0001DB8B,
1623 0x036, 0x000262DB,
1624 0x036, 0x0002E2DB,
1625 0x036, 0x000362DB,
1626 0x036, 0x0003E2DB,
1627 0x036, 0x0004553B,
1628 0x036, 0x0004D53B,
1629 0x036, 0x0005553B,
1630 0x036, 0x0005D53B,
1631 0xFF0F01C0, 0xCDEF,
1632 0x018, 0x0001712A,
1633 0x0EF, 0x00000010,
1634 0x036, 0x00005B8B,
1635 0x036, 0x0000DB8B,
1636 0x036, 0x00015B8B,
1637 0x036, 0x0001DB8B,
1638 0x036, 0x000262DB,
1639 0x036, 0x0002E2DB,
1640 0x036, 0x000362DB,
1641 0x036, 0x0003E2DB,
1642 0x036, 0x0004553B,
1643 0x036, 0x0004D53B,
1644 0x036, 0x0005553B,
1645 0x036, 0x0005D53B,
1646 0xFF0F02C0, 0xCDEF,
1647 0x018, 0x0001712A,
1648 0x0EF, 0x00000010,
1649 0x036, 0x00005B8B,
1650 0x036, 0x0000DB8B,
1651 0x036, 0x00015B8B,
1652 0x036, 0x0001DB8B,
1653 0x036, 0x000262DB,
1654 0x036, 0x0002E2DB,
1655 0x036, 0x000362DB,
1656 0x036, 0x0003E2DB,
1657 0x036, 0x0004553B,
1658 0x036, 0x0004D53B,
1659 0x036, 0x0005553B,
1660 0x036, 0x0005D53B,
1661 0xFF0F07D8, 0xCDEF,
1662 0x018, 0x0001712A,
1663 0x0EF, 0x00000010,
1664 0x036, 0x00005B8B,
1665 0x036, 0x0000DB8B,
1666 0x036, 0x00015B8B,
1667 0x036, 0x0001DB8B,
1668 0x036, 0x000262DB,
1669 0x036, 0x0002E2DB,
1670 0x036, 0x000362DB,
1671 0x036, 0x0003E2DB,
1672 0x036, 0x0004553B,
1673 0x036, 0x0004D53B,
1674 0x036, 0x0005553B,
1675 0x036, 0x0005D53B,
1676 0xFF0F07D0, 0xCDEF,
1677 0x018, 0x0001712A,
1678 0x0EF, 0x00000010,
1679 0x036, 0x00005B8B,
1680 0x036, 0x0000DB8B,
1681 0x036, 0x00015B8B,
1682 0x036, 0x0001DB8B,
1683 0x036, 0x000262DB,
1684 0x036, 0x0002E2DB,
1685 0x036, 0x000362DB,
1686 0x036, 0x0003E2DB,
1687 0x036, 0x0004553B,
1688 0x036, 0x0004D53B,
1689 0x036, 0x0005553B,
1690 0x036, 0x0005D53B,
1691 0xCDCDCDCD, 0xCDCD,
1692 0x018, 0x0001712A,
1693 0x0EF, 0x00000010,
1694 0x036, 0x00084EB4,
1695 0x036, 0x0008C9B4,
1696 0x036, 0x000949B4,
1697 0x036, 0x0009C9B4,
1698 0x036, 0x000A4935,
1699 0x036, 0x000AC935,
1700 0x036, 0x000B4935,
1701 0x036, 0x000BC935,
1702 0x036, 0x000C4EB4,
1703 0x036, 0x000CCEB4,
1704 0x036, 0x000D4EB4,
1705 0x036, 0x000DCEB4,
1706 0xFF0F0740, 0xDEAD,
1707 0x0EF, 0x00000000,
1708 0x0EF, 0x00000008,
1709 0xFF0F0740, 0xABCD,
1710 0x03C, 0x000002DC,
1711 0x03C, 0x00000524,
1712 0x03C, 0x00000902,
1713 0xFF0F01C0, 0xCDEF,
1714 0x03C, 0x000002DC,
1715 0x03C, 0x00000524,
1716 0x03C, 0x00000902,
1717 0xFF0F02C0, 0xCDEF,
1718 0x03C, 0x000002DC,
1719 0x03C, 0x00000524,
1720 0x03C, 0x00000902,
1721 0xFF0F07D8, 0xCDEF,
1722 0x03C, 0x000002DC,
1723 0x03C, 0x00000524,
1724 0x03C, 0x00000902,
1725 0xFF0F07D0, 0xCDEF,
1726 0x03C, 0x000002DC,
1727 0x03C, 0x00000524,
1728 0x03C, 0x00000902,
1729 0xCDCDCDCD, 0xCDCD,
1730 0x03C, 0x000002AA,
1731 0x03C, 0x000005A2,
1732 0x03C, 0x00000880,
1733 0xFF0F0740, 0xDEAD,
1734 0x0EF, 0x00000000,
1735 0x018, 0x0001712A,
1736 0x0EF, 0x00000002,
1737 0x0DF, 0x00000080,
1738 0xFF0F0740, 0xABCD,
1739 0x061, 0x000EAC43,
1740 0x062, 0x00038F47,
1741 0x063, 0x00031157,
1742 0x064, 0x0001C4AC,
1743 0x065, 0x000931D1,
1744 0xFF0F01C0, 0xCDEF,
1745 0x061, 0x000EAC43,
1746 0x062, 0x00038F47,
1747 0x063, 0x00031157,
1748 0x064, 0x0001C4AC,
1749 0x065, 0x000931D1,
1750 0xFF0F02C0, 0xCDEF,
1751 0x061, 0x000EAC43,
1752 0x062, 0x00038F47,
1753 0x063, 0x00031157,
1754 0x064, 0x0001C4AC,
1755 0x065, 0x000931D1,
1756 0xFF0F07D8, 0xCDEF,
1757 0x061, 0x000EAC43,
1758 0x062, 0x00038F47,
1759 0x063, 0x00031157,
1760 0x064, 0x0001C4AC,
1761 0x065, 0x000931D1,
1762 0xFF0F07D0, 0xCDEF,
1763 0x061, 0x000EAC43,
1764 0x062, 0x00038F47,
1765 0x063, 0x00031157,
1766 0x064, 0x0001C4AC,
1767 0x065, 0x000931D1,
1768 0xCDCDCDCD, 0xCDCD,
1769 0x061, 0x000E5D53,
1770 0x062, 0x00038FCD,
1771 0x063, 0x000314EB,
1772 0x064, 0x000196AC,
1773 0x065, 0x000931D7,
1774 0xFF0F0740, 0xDEAD,
1775 0x008, 0x00008400,
1776
1777};
1778
1779u32 RTL8821AE_RADIOA_ARRAY[] = {
1780 0x018, 0x0001712A,
1781 0x056, 0x00051CF2,
1782 0x066, 0x00040000,
1783 0x000, 0x00010000,
1784 0x01E, 0x00080000,
1785 0x082, 0x00000830,
1786 0x083, 0x00021800,
1787 0x084, 0x00028000,
1788 0x085, 0x00048000,
1789 0x086, 0x00094838,
1790 0x087, 0x00044980,
1791 0x088, 0x00048000,
1792 0x089, 0x0000D480,
1793 0x08A, 0x00042240,
1794 0x08B, 0x000F0380,
1795 0x08C, 0x00090000,
1796 0x08D, 0x00022852,
1797 0x08E, 0x00065540,
1798 0x08F, 0x00088001,
1799 0x0EF, 0x00020000,
1800 0x03E, 0x00000380,
1801 0x03F, 0x00090018,
1802 0x03E, 0x00020380,
1803 0x03F, 0x000A0018,
1804 0x03E, 0x00040308,
1805 0x03F, 0x000A0018,
1806 0x03E, 0x00060018,
1807 0x03F, 0x000A0018,
1808 0x0EF, 0x00000000,
1809 0x018, 0x0001712A,
1810 0x089, 0x00000080,
1811 0x08B, 0x00080180,
1812 0x0EF, 0x00001000,
1813 0x03A, 0x00000244,
1814 0x03B, 0x00038027,
1815 0x03C, 0x00082000,
1816 0x03A, 0x00000244,
1817 0x03B, 0x00030113,
1818 0x03C, 0x00082000,
1819 0x03A, 0x0000014C,
1820 0x03B, 0x00028027,
1821 0x03C, 0x00082000,
1822 0x03A, 0x000000CC,
1823 0x03B, 0x00027027,
1824 0x03C, 0x00042000,
1825 0x03A, 0x0000014C,
1826 0x03B, 0x0001F913,
1827 0x03C, 0x00042000,
1828 0x03A, 0x0000010C,
1829 0x03B, 0x00017F10,
1830 0x03C, 0x00012000,
1831 0x03A, 0x000000D0,
1832 0x03B, 0x00008027,
1833 0x03C, 0x000CA000,
1834 0x03A, 0x00000244,
1835 0x03B, 0x00078027,
1836 0x03C, 0x00082000,
1837 0x03A, 0x00000244,
1838 0x03B, 0x00070113,
1839 0x03C, 0x00082000,
1840 0x03A, 0x0000014C,
1841 0x03B, 0x00068027,
1842 0x03C, 0x00082000,
1843 0x03A, 0x000000CC,
1844 0x03B, 0x00067027,
1845 0x03C, 0x00042000,
1846 0x03A, 0x0000014C,
1847 0x03B, 0x0005F913,
1848 0x03C, 0x00042000,
1849 0x03A, 0x0000010C,
1850 0x03B, 0x00057F10,
1851 0x03C, 0x00012000,
1852 0x03A, 0x000000D0,
1853 0x03B, 0x00048027,
1854 0x03C, 0x000CA000,
1855 0x03A, 0x00000244,
1856 0x03B, 0x000B8027,
1857 0x03C, 0x00082000,
1858 0x03A, 0x00000244,
1859 0x03B, 0x000B0113,
1860 0x03C, 0x00082000,
1861 0x03A, 0x0000014C,
1862 0x03B, 0x000A8027,
1863 0x03C, 0x00082000,
1864 0x03A, 0x000000CC,
1865 0x03B, 0x000A7027,
1866 0x03C, 0x00042000,
1867 0x03A, 0x0000014C,
1868 0x03B, 0x0009F913,
1869 0x03C, 0x00042000,
1870 0x03A, 0x0000010C,
1871 0x03B, 0x00097F10,
1872 0x03C, 0x00012000,
1873 0x03A, 0x000000D0,
1874 0x03B, 0x00088027,
1875 0x03C, 0x000CA000,
1876 0x0EF, 0x00000000,
1877 0x0EF, 0x00001100,
1878 0xFF0F0104, 0xABCD,
1879 0x034, 0x0004ADF3,
1880 0x034, 0x00049DF0,
1881 0xFF0F0204, 0xCDEF,
1882 0x034, 0x0004ADF3,
1883 0x034, 0x00049DF0,
1884 0xFF0F0404, 0xCDEF,
1885 0x034, 0x0004ADF3,
1886 0x034, 0x00049DF0,
1887 0xFF0F0200, 0xCDEF,
1888 0x034, 0x0004ADF5,
1889 0x034, 0x00049DF2,
1890 0xFF0F02C0, 0xCDEF,
1891 0x034, 0x0004A0F3,
1892 0x034, 0x000490B1,
1893 0xCDCDCDCD, 0xCDCD,
1894 0x034, 0x0004ADF7,
1895 0x034, 0x00049DF3,
1896 0xFF0F0104, 0xDEAD,
1897 0xFF0F0104, 0xABCD,
1898 0x034, 0x00048DED,
1899 0x034, 0x00047DEA,
1900 0x034, 0x00046DE7,
1901 0x034, 0x00045CE9,
1902 0x034, 0x00044CE6,
1903 0x034, 0x000438C6,
1904 0x034, 0x00042886,
1905 0x034, 0x00041486,
1906 0x034, 0x00040447,
1907 0xFF0F0204, 0xCDEF,
1908 0x034, 0x00048DED,
1909 0x034, 0x00047DEA,
1910 0x034, 0x00046DE7,
1911 0x034, 0x00045CE9,
1912 0x034, 0x00044CE6,
1913 0x034, 0x000438C6,
1914 0x034, 0x00042886,
1915 0x034, 0x00041486,
1916 0x034, 0x00040447,
1917 0xFF0F0404, 0xCDEF,
1918 0x034, 0x00048DED,
1919 0x034, 0x00047DEA,
1920 0x034, 0x00046DE7,
1921 0x034, 0x00045CE9,
1922 0x034, 0x00044CE6,
1923 0x034, 0x000438C6,
1924 0x034, 0x00042886,
1925 0x034, 0x00041486,
1926 0x034, 0x00040447,
1927 0xFF0F02C0, 0xCDEF,
1928 0x034, 0x000480AE,
1929 0x034, 0x000470AB,
1930 0x034, 0x0004608B,
1931 0x034, 0x00045069,
1932 0x034, 0x00044048,
1933 0x034, 0x00043045,
1934 0x034, 0x00042026,
1935 0x034, 0x00041023,
1936 0x034, 0x00040002,
1937 0xCDCDCDCD, 0xCDCD,
1938 0x034, 0x00048DEF,
1939 0x034, 0x00047DEC,
1940 0x034, 0x00046DE9,
1941 0x034, 0x00045CCB,
1942 0x034, 0x0004488D,
1943 0x034, 0x0004348D,
1944 0x034, 0x0004248A,
1945 0x034, 0x0004108D,
1946 0x034, 0x0004008A,
1947 0xFF0F0104, 0xDEAD,
1948 0xFF0F0200, 0xABCD,
1949 0x034, 0x0002ADF4,
1950 0xFF0F02C0, 0xCDEF,
1951 0x034, 0x0002A0F3,
1952 0xCDCDCDCD, 0xCDCD,
1953 0x034, 0x0002ADF7,
1954 0xFF0F0200, 0xDEAD,
1955 0xFF0F0104, 0xABCD,
1956 0x034, 0x00029DF4,
1957 0xFF0F0204, 0xCDEF,
1958 0x034, 0x00029DF4,
1959 0xFF0F0404, 0xCDEF,
1960 0x034, 0x00029DF4,
1961 0xFF0F0200, 0xCDEF,
1962 0x034, 0x00029DF1,
1963 0xFF0F02C0, 0xCDEF,
1964 0x034, 0x000290F0,
1965 0xCDCDCDCD, 0xCDCD,
1966 0x034, 0x00029DF2,
1967 0xFF0F0104, 0xDEAD,
1968 0xFF0F0104, 0xABCD,
1969 0x034, 0x00028DF1,
1970 0x034, 0x00027DEE,
1971 0x034, 0x00026DEB,
1972 0x034, 0x00025CEC,
1973 0x034, 0x00024CE9,
1974 0x034, 0x000238CA,
1975 0x034, 0x00022889,
1976 0x034, 0x00021489,
1977 0x034, 0x0002044A,
1978 0xFF0F0204, 0xCDEF,
1979 0x034, 0x00028DF1,
1980 0x034, 0x00027DEE,
1981 0x034, 0x00026DEB,
1982 0x034, 0x00025CEC,
1983 0x034, 0x00024CE9,
1984 0x034, 0x000238CA,
1985 0x034, 0x00022889,
1986 0x034, 0x00021489,
1987 0x034, 0x0002044A,
1988 0xFF0F0404, 0xCDEF,
1989 0x034, 0x00028DF1,
1990 0x034, 0x00027DEE,
1991 0x034, 0x00026DEB,
1992 0x034, 0x00025CEC,
1993 0x034, 0x00024CE9,
1994 0x034, 0x000238CA,
1995 0x034, 0x00022889,
1996 0x034, 0x00021489,
1997 0x034, 0x0002044A,
1998 0xFF0F02C0, 0xCDEF,
1999 0x034, 0x000280AF,
2000 0x034, 0x000270AC,
2001 0x034, 0x0002608B,
2002 0x034, 0x00025069,
2003 0x034, 0x00024048,
2004 0x034, 0x00023045,
2005 0x034, 0x00022026,
2006 0x034, 0x00021023,
2007 0x034, 0x00020002,
2008 0xCDCDCDCD, 0xCDCD,
2009 0x034, 0x00028DEE,
2010 0x034, 0x00027DEB,
2011 0x034, 0x00026CCD,
2012 0x034, 0x00025CCA,
2013 0x034, 0x0002488C,
2014 0x034, 0x0002384C,
2015 0x034, 0x00022849,
2016 0x034, 0x00021449,
2017 0x034, 0x0002004D,
2018 0xFF0F0104, 0xDEAD,
2019 0xFF0F02C0, 0xABCD,
2020 0x034, 0x0000A0D7,
2021 0x034, 0x000090D3,
2022 0x034, 0x000080B1,
2023 0x034, 0x000070AE,
2024 0xCDCDCDCD, 0xCDCD,
2025 0x034, 0x0000ADF7,
2026 0x034, 0x00009DF4,
2027 0x034, 0x00008DF1,
2028 0x034, 0x00007DEE,
2029 0xFF0F02C0, 0xDEAD,
2030 0xFF0F0104, 0xABCD,
2031 0x034, 0x00006DEB,
2032 0x034, 0x00005CEC,
2033 0x034, 0x00004CE9,
2034 0x034, 0x000038CA,
2035 0x034, 0x00002889,
2036 0x034, 0x00001489,
2037 0x034, 0x0000044A,
2038 0xFF0F0204, 0xCDEF,
2039 0x034, 0x00006DEB,
2040 0x034, 0x00005CEC,
2041 0x034, 0x00004CE9,
2042 0x034, 0x000038CA,
2043 0x034, 0x00002889,
2044 0x034, 0x00001489,
2045 0x034, 0x0000044A,
2046 0xFF0F0404, 0xCDEF,
2047 0x034, 0x00006DEB,
2048 0x034, 0x00005CEC,
2049 0x034, 0x00004CE9,
2050 0x034, 0x000038CA,
2051 0x034, 0x00002889,
2052 0x034, 0x00001489,
2053 0x034, 0x0000044A,
2054 0xFF0F02C0, 0xCDEF,
2055 0x034, 0x0000608D,
2056 0x034, 0x0000506B,
2057 0x034, 0x0000404A,
2058 0x034, 0x00003047,
2059 0x034, 0x00002044,
2060 0x034, 0x00001025,
2061 0x034, 0x00000004,
2062 0xCDCDCDCD, 0xCDCD,
2063 0x034, 0x00006DCD,
2064 0x034, 0x00005CCD,
2065 0x034, 0x00004CCA,
2066 0x034, 0x0000388C,
2067 0x034, 0x00002888,
2068 0x034, 0x00001488,
2069 0x034, 0x00000486,
2070 0xFF0F0104, 0xDEAD,
2071 0x0EF, 0x00000000,
2072 0x018, 0x0001712A,
2073 0x0EF, 0x00000040,
2074 0xFF0F0104, 0xABCD,
2075 0x035, 0x00000187,
2076 0x035, 0x00008187,
2077 0x035, 0x00010187,
2078 0x035, 0x00020188,
2079 0x035, 0x00028188,
2080 0x035, 0x00030188,
2081 0x035, 0x00040188,
2082 0x035, 0x00048188,
2083 0x035, 0x00050188,
2084 0xFF0F0204, 0xCDEF,
2085 0x035, 0x00000187,
2086 0x035, 0x00008187,
2087 0x035, 0x00010187,
2088 0x035, 0x00020188,
2089 0x035, 0x00028188,
2090 0x035, 0x00030188,
2091 0x035, 0x00040188,
2092 0x035, 0x00048188,
2093 0x035, 0x00050188,
2094 0xFF0F0404, 0xCDEF,
2095 0x035, 0x00000187,
2096 0x035, 0x00008187,
2097 0x035, 0x00010187,
2098 0x035, 0x00020188,
2099 0x035, 0x00028188,
2100 0x035, 0x00030188,
2101 0x035, 0x00040188,
2102 0x035, 0x00048188,
2103 0x035, 0x00050188,
2104 0xCDCDCDCD, 0xCDCD,
2105 0x035, 0x00000145,
2106 0x035, 0x00008145,
2107 0x035, 0x00010145,
2108 0x035, 0x00020196,
2109 0x035, 0x00028196,
2110 0x035, 0x00030196,
2111 0x035, 0x000401C7,
2112 0x035, 0x000481C7,
2113 0x035, 0x000501C7,
2114 0xFF0F0104, 0xDEAD,
2115 0x0EF, 0x00000000,
2116 0x018, 0x0001712A,
2117 0x0EF, 0x00000010,
2118 0xFF0F0104, 0xABCD,
2119 0x036, 0x00085733,
2120 0x036, 0x0008D733,
2121 0x036, 0x00095733,
2122 0x036, 0x0009D733,
2123 0x036, 0x000A64B4,
2124 0x036, 0x000AE4B4,
2125 0x036, 0x000B64B4,
2126 0x036, 0x000BE4B4,
2127 0x036, 0x000C64B4,
2128 0x036, 0x000CE4B4,
2129 0x036, 0x000D64B4,
2130 0x036, 0x000DE4B4,
2131 0xFF0F0204, 0xCDEF,
2132 0x036, 0x00085733,
2133 0x036, 0x0008D733,
2134 0x036, 0x00095733,
2135 0x036, 0x0009D733,
2136 0x036, 0x000A64B4,
2137 0x036, 0x000AE4B4,
2138 0x036, 0x000B64B4,
2139 0x036, 0x000BE4B4,
2140 0x036, 0x000C64B4,
2141 0x036, 0x000CE4B4,
2142 0x036, 0x000D64B4,
2143 0x036, 0x000DE4B4,
2144 0xFF0F0404, 0xCDEF,
2145 0x036, 0x00085733,
2146 0x036, 0x0008D733,
2147 0x036, 0x00095733,
2148 0x036, 0x0009D733,
2149 0x036, 0x000A64B4,
2150 0x036, 0x000AE4B4,
2151 0x036, 0x000B64B4,
2152 0x036, 0x000BE4B4,
2153 0x036, 0x000C64B4,
2154 0x036, 0x000CE4B4,
2155 0x036, 0x000D64B4,
2156 0x036, 0x000DE4B4,
2157 0xCDCDCDCD, 0xCDCD,
2158 0x036, 0x000056B3,
2159 0x036, 0x0000D6B3,
2160 0x036, 0x000156B3,
2161 0x036, 0x0001D6B3,
2162 0x036, 0x00026634,
2163 0x036, 0x0002E634,
2164 0x036, 0x00036634,
2165 0x036, 0x0003E634,
2166 0x036, 0x000467B4,
2167 0x036, 0x0004E7B4,
2168 0x036, 0x000567B4,
2169 0x036, 0x0005E7B4,
2170 0xFF0F0104, 0xDEAD,
2171 0x0EF, 0x00000000,
2172 0x0EF, 0x00000008,
2173 0xFF0F0104, 0xABCD,
2174 0x03C, 0x000001C8,
2175 0x03C, 0x00000492,
2176 0xFF0F0204, 0xCDEF,
2177 0x03C, 0x000001C8,
2178 0x03C, 0x00000492,
2179 0xFF0F0404, 0xCDEF,
2180 0x03C, 0x000001C8,
2181 0x03C, 0x00000492,
2182 0xCDCDCDCD, 0xCDCD,
2183 0x03C, 0x0000022A,
2184 0x03C, 0x00000594,
2185 0xFF0F0104, 0xDEAD,
2186 0xFF0F0104, 0xABCD,
2187 0x03C, 0x00000800,
2188 0xFF0F0204, 0xCDEF,
2189 0x03C, 0x00000800,
2190 0xFF0F0404, 0xCDEF,
2191 0x03C, 0x00000800,
2192 0xFF0F02C0, 0xCDEF,
2193 0x03C, 0x00000820,
2194 0xCDCDCDCD, 0xCDCD,
2195 0x03C, 0x00000900,
2196 0xFF0F0104, 0xDEAD,
2197 0x0EF, 0x00000000,
2198 0x018, 0x0001712A,
2199 0x0EF, 0x00000002,
2200 0xFF0F0104, 0xABCD,
2201 0x008, 0x0004E400,
2202 0xFF0F0204, 0xCDEF,
2203 0x008, 0x0004E400,
2204 0xFF0F0404, 0xCDEF,
2205 0x008, 0x0004E400,
2206 0xCDCDCDCD, 0xCDCD,
2207 0x008, 0x00002000,
2208 0xFF0F0104, 0xDEAD,
2209 0x0EF, 0x00000000,
2210 0x0DF, 0x000000C0,
2211 0x01F, 0x00040064,
2212 0xFF0F0104, 0xABCD,
2213 0x058, 0x000A7284,
2214 0x059, 0x000600EC,
2215 0xFF0F0204, 0xCDEF,
2216 0x058, 0x000A7284,
2217 0x059, 0x000600EC,
2218 0xFF0F0404, 0xCDEF,
2219 0x058, 0x000A7284,
2220 0x059, 0x000600EC,
2221 0xCDCDCDCD, 0xCDCD,
2222 0x058, 0x00081184,
2223 0x059, 0x0006016C,
2224 0xFF0F0104, 0xDEAD,
2225 0xFF0F0104, 0xABCD,
2226 0x061, 0x000E8D73,
2227 0x062, 0x00093FC5,
2228 0xFF0F0204, 0xCDEF,
2229 0x061, 0x000E8D73,
2230 0x062, 0x00093FC5,
2231 0xFF0F0404, 0xCDEF,
2232 0x061, 0x000E8D73,
2233 0x062, 0x00093FC5,
2234 0xCDCDCDCD, 0xCDCD,
2235 0x061, 0x000EAD53,
2236 0x062, 0x00093BC4,
2237 0xFF0F0104, 0xDEAD,
2238 0xFF0F0104, 0xABCD,
2239 0x063, 0x000110E9,
2240 0xFF0F0204, 0xCDEF,
2241 0x063, 0x000110E9,
2242 0xFF0F0404, 0xCDEF,
2243 0x063, 0x000110E9,
2244 0xFF0F0200, 0xCDEF,
2245 0x063, 0x000710E9,
2246 0xFF0F02C0, 0xCDEF,
2247 0x063, 0x000110E9,
2248 0xCDCDCDCD, 0xCDCD,
2249 0x063, 0x000714E9,
2250 0xFF0F0104, 0xDEAD,
2251 0xFF0F0104, 0xABCD,
2252 0x064, 0x0001C27C,
2253 0xFF0F0204, 0xCDEF,
2254 0x064, 0x0001C27C,
2255 0xFF0F0404, 0xCDEF,
2256 0x064, 0x0001C27C,
2257 0xCDCDCDCD, 0xCDCD,
2258 0x064, 0x0001C67C,
2259 0xFF0F0104, 0xDEAD,
2260 0xFF0F0200, 0xABCD,
2261 0x065, 0x00093016,
2262 0xFF0F02C0, 0xCDEF,
2263 0x065, 0x00093015,
2264 0xCDCDCDCD, 0xCDCD,
2265 0x065, 0x00091016,
2266 0xFF0F0200, 0xDEAD,
2267 0x018, 0x00000006,
2268 0x0EF, 0x00002000,
2269 0x03B, 0x0003824B,
2270 0x03B, 0x0003024B,
2271 0x03B, 0x0002844B,
2272 0x03B, 0x00020F4B,
2273 0x03B, 0x00018F4B,
2274 0x03B, 0x000104B2,
2275 0x03B, 0x00008049,
2276 0x03B, 0x00000148,
2277 0x03B, 0x0007824B,
2278 0x03B, 0x0007024B,
2279 0x03B, 0x0006824B,
2280 0x03B, 0x00060F4B,
2281 0x03B, 0x00058F4B,
2282 0x03B, 0x000504B2,
2283 0x03B, 0x00048049,
2284 0x03B, 0x00040148,
2285 0x0EF, 0x00000000,
2286 0x0EF, 0x00000100,
2287 0x034, 0x0000ADF3,
2288 0x034, 0x00009DEF,
2289 0x034, 0x00008DEC,
2290 0x034, 0x00007DE9,
2291 0x034, 0x00006CED,
2292 0x034, 0x00005CE9,
2293 0x034, 0x000044E9,
2294 0x034, 0x000034E6,
2295 0x034, 0x0000246A,
2296 0x034, 0x00001467,
2297 0x034, 0x00000068,
2298 0x0EF, 0x00000000,
2299 0x0ED, 0x00000010,
2300 0x044, 0x0000ADF2,
2301 0x044, 0x00009DEF,
2302 0x044, 0x00008DEC,
2303 0x044, 0x00007DE9,
2304 0x044, 0x00006CEC,
2305 0x044, 0x00005CE9,
2306 0x044, 0x000044EC,
2307 0x044, 0x000034E9,
2308 0x044, 0x0000246C,
2309 0x044, 0x00001469,
2310 0x044, 0x0000006C,
2311 0x0ED, 0x00000000,
2312 0x0ED, 0x00000001,
2313 0x040, 0x00038DA7,
2314 0x040, 0x000300C2,
2315 0x040, 0x000288E2,
2316 0x040, 0x000200B8,
2317 0x040, 0x000188A5,
2318 0x040, 0x00010FBC,
2319 0x040, 0x00008F71,
2320 0x040, 0x00000240,
2321 0x0ED, 0x00000000,
2322 0x0EF, 0x000020A2,
2323 0x0DF, 0x00000080,
2324 0x035, 0x00000120,
2325 0x035, 0x00008120,
2326 0x035, 0x00010120,
2327 0x036, 0x00000085,
2328 0x036, 0x00008085,
2329 0x036, 0x00010085,
2330 0x036, 0x00018085,
2331 0x0EF, 0x00000000,
2332 0x051, 0x00000C31,
2333 0x052, 0x00000622,
2334 0x053, 0x000FC70B,
2335 0x054, 0x0000017E,
2336 0x056, 0x00051DF3,
2337 0x051, 0x00000C01,
2338 0x052, 0x000006D6,
2339 0x053, 0x000FC649,
2340 0x070, 0x00049661,
2341 0x071, 0x0007843E,
2342 0x072, 0x00000382,
2343 0x074, 0x00051400,
2344 0x035, 0x00000160,
2345 0x035, 0x00008160,
2346 0x035, 0x00010160,
2347 0x036, 0x00000124,
2348 0x036, 0x00008124,
2349 0x036, 0x00010124,
2350 0x036, 0x00018124,
2351 0x0ED, 0x0000000C,
2352 0x045, 0x00000140,
2353 0x045, 0x00008140,
2354 0x045, 0x00010140,
2355 0x046, 0x00000124,
2356 0x046, 0x00008124,
2357 0x046, 0x00010124,
2358 0x046, 0x00018124,
2359 0x0DF, 0x00000088,
2360 0x0B3, 0x000F0E18,
2361 0x0B4, 0x0001214C,
2362 0x0B7, 0x0003000C,
2363 0x01C, 0x000539D2,
2364 0x018, 0x0001F12A,
2365 0x0FE, 0x00000000,
2366 0x0FE, 0x00000000,
2367 0x018, 0x0001712A,
2368};
2369
2370u32 RTL8812AE_MAC_REG_ARRAY[] = {
2371 0x010, 0x0000000C,
2372 0xFF0F0180, 0xABCD,
2373 0x025, 0x0000000F,
2374 0xFF0F01C0, 0xCDEF,
2375 0x025, 0x0000000F,
2376 0xCDCDCDCD, 0xCDCD,
2377 0x025, 0x0000006F,
2378 0xFF0F0180, 0xDEAD,
2379 0x072, 0x00000000,
2380 0x428, 0x0000000A,
2381 0x429, 0x00000010,
2382 0x430, 0x00000000,
2383 0x431, 0x00000000,
2384 0x432, 0x00000000,
2385 0x433, 0x00000001,
2386 0x434, 0x00000004,
2387 0x435, 0x00000005,
2388 0x436, 0x00000007,
2389 0x437, 0x00000008,
2390 0x43C, 0x00000004,
2391 0x43D, 0x00000005,
2392 0x43E, 0x00000007,
2393 0x43F, 0x00000008,
2394 0x440, 0x0000005D,
2395 0x441, 0x00000001,
2396 0x442, 0x00000000,
2397 0x444, 0x00000010,
2398 0x445, 0x00000000,
2399 0x446, 0x00000000,
2400 0x447, 0x00000000,
2401 0x448, 0x00000000,
2402 0x449, 0x000000F0,
2403 0x44A, 0x0000000F,
2404 0x44B, 0x0000003E,
2405 0x44C, 0x00000010,
2406 0x44D, 0x00000000,
2407 0x44E, 0x00000000,
2408 0x44F, 0x00000000,
2409 0x450, 0x00000000,
2410 0x451, 0x000000F0,
2411 0x452, 0x0000000F,
2412 0x453, 0x00000000,
2413 0x45B, 0x00000080,
2414 0x460, 0x00000066,
2415 0x461, 0x00000066,
2416 0x4C8, 0x000000FF,
2417 0x4C9, 0x00000008,
2418 0x4CC, 0x000000FF,
2419 0x4CD, 0x000000FF,
2420 0x4CE, 0x00000001,
2421 0x500, 0x00000026,
2422 0x501, 0x000000A2,
2423 0x502, 0x0000002F,
2424 0x503, 0x00000000,
2425 0x504, 0x00000028,
2426 0x505, 0x000000A3,
2427 0x506, 0x0000005E,
2428 0x507, 0x00000000,
2429 0x508, 0x0000002B,
2430 0x509, 0x000000A4,
2431 0x50A, 0x0000005E,
2432 0x50B, 0x00000000,
2433 0x50C, 0x0000004F,
2434 0x50D, 0x000000A4,
2435 0x50E, 0x00000000,
2436 0x50F, 0x00000000,
2437 0x512, 0x0000001C,
2438 0x514, 0x0000000A,
2439 0x516, 0x0000000A,
2440 0x525, 0x0000004F,
2441 0x550, 0x00000010,
2442 0x551, 0x00000010,
2443 0x559, 0x00000002,
2444 0x55C, 0x00000050,
2445 0x55D, 0x000000FF,
2446 0x604, 0x00000001,
2447 0x605, 0x00000030,
2448 0x607, 0x00000003,
2449 0x608, 0x0000000E,
2450 0x609, 0x0000002A,
2451 0x620, 0x000000FF,
2452 0x621, 0x000000FF,
2453 0x622, 0x000000FF,
2454 0x623, 0x000000FF,
2455 0x624, 0x000000FF,
2456 0x625, 0x000000FF,
2457 0x626, 0x000000FF,
2458 0x627, 0x000000FF,
2459 0x638, 0x00000050,
2460 0x63C, 0x0000000A,
2461 0x63D, 0x0000000A,
2462 0x63E, 0x0000000E,
2463 0x63F, 0x0000000E,
2464 0x640, 0x00000080,
2465 0x642, 0x00000040,
2466 0x643, 0x00000000,
2467 0x652, 0x000000C8,
2468 0x66E, 0x00000005,
2469 0x700, 0x00000021,
2470 0x701, 0x00000043,
2471 0x702, 0x00000065,
2472 0x703, 0x00000087,
2473 0x708, 0x00000021,
2474 0x709, 0x00000043,
2475 0x70A, 0x00000065,
2476 0x70B, 0x00000087,
2477 0x718, 0x00000040,
2478
2479};
2480
2481u32 RTL8821AE_MAC_REG_ARRAY[] = {
2482 0x428, 0x0000000A,
2483 0x429, 0x00000010,
2484 0x430, 0x00000000,
2485 0x431, 0x00000000,
2486 0x432, 0x00000000,
2487 0x433, 0x00000001,
2488 0x434, 0x00000004,
2489 0x435, 0x00000005,
2490 0x436, 0x00000007,
2491 0x437, 0x00000008,
2492 0x43C, 0x00000004,
2493 0x43D, 0x00000005,
2494 0x43E, 0x00000007,
2495 0x43F, 0x00000008,
2496 0x440, 0x0000005D,
2497 0x441, 0x00000001,
2498 0x442, 0x00000000,
2499 0x444, 0x00000010,
2500 0x445, 0x00000000,
2501 0x446, 0x00000000,
2502 0x447, 0x00000000,
2503 0x448, 0x00000000,
2504 0x449, 0x000000F0,
2505 0x44A, 0x0000000F,
2506 0x44B, 0x0000003E,
2507 0x44C, 0x00000010,
2508 0x44D, 0x00000000,
2509 0x44E, 0x00000000,
2510 0x44F, 0x00000000,
2511 0x450, 0x00000000,
2512 0x451, 0x000000F0,
2513 0x452, 0x0000000F,
2514 0x453, 0x00000000,
2515 0x456, 0x0000005E,
2516 0x460, 0x00000066,
2517 0x461, 0x00000066,
2518 0x4C8, 0x0000003F,
2519 0x4C9, 0x000000FF,
2520 0x4CC, 0x000000FF,
2521 0x4CD, 0x000000FF,
2522 0x4CE, 0x00000001,
2523 0x500, 0x00000026,
2524 0x501, 0x000000A2,
2525 0x502, 0x0000002F,
2526 0x503, 0x00000000,
2527 0x504, 0x00000028,
2528 0x505, 0x000000A3,
2529 0x506, 0x0000005E,
2530 0x507, 0x00000000,
2531 0x508, 0x0000002B,
2532 0x509, 0x000000A4,
2533 0x50A, 0x0000005E,
2534 0x50B, 0x00000000,
2535 0x50C, 0x0000004F,
2536 0x50D, 0x000000A4,
2537 0x50E, 0x00000000,
2538 0x50F, 0x00000000,
2539 0x512, 0x0000001C,
2540 0x514, 0x0000000A,
2541 0x516, 0x0000000A,
2542 0x525, 0x0000004F,
2543 0x550, 0x00000010,
2544 0x551, 0x00000010,
2545 0x559, 0x00000002,
2546 0x55C, 0x00000050,
2547 0x55D, 0x000000FF,
2548 0x605, 0x00000030,
2549 0x607, 0x00000007,
2550 0x608, 0x0000000E,
2551 0x609, 0x0000002A,
2552 0x620, 0x000000FF,
2553 0x621, 0x000000FF,
2554 0x622, 0x000000FF,
2555 0x623, 0x000000FF,
2556 0x624, 0x000000FF,
2557 0x625, 0x000000FF,
2558 0x626, 0x000000FF,
2559 0x627, 0x000000FF,
2560 0x638, 0x00000050,
2561 0x63C, 0x0000000A,
2562 0x63D, 0x0000000A,
2563 0x63E, 0x0000000E,
2564 0x63F, 0x0000000E,
2565 0x640, 0x00000040,
2566 0x642, 0x00000040,
2567 0x643, 0x00000000,
2568 0x652, 0x000000C8,
2569 0x66E, 0x00000005,
2570 0x700, 0x00000021,
2571 0x701, 0x00000043,
2572 0x702, 0x00000065,
2573 0x703, 0x00000087,
2574 0x708, 0x00000021,
2575 0x709, 0x00000043,
2576 0x70A, 0x00000065,
2577 0x70B, 0x00000087,
2578 0x718, 0x00000040,
2579};
2580
2581u32 RTL8812AE_AGC_TAB_ARRAY[] = {
2582 0xFF0F07D8, 0xABCD,
2583 0x81C, 0xFC000001,
2584 0x81C, 0xFB020001,
2585 0x81C, 0xFA040001,
2586 0x81C, 0xF9060001,
2587 0x81C, 0xF8080001,
2588 0x81C, 0xF70A0001,
2589 0x81C, 0xF60C0001,
2590 0x81C, 0xF50E0001,
2591 0x81C, 0xF4100001,
2592 0x81C, 0xF3120001,
2593 0x81C, 0xF2140001,
2594 0x81C, 0xF1160001,
2595 0x81C, 0xF0180001,
2596 0x81C, 0xEF1A0001,
2597 0x81C, 0xEE1C0001,
2598 0x81C, 0xED1E0001,
2599 0x81C, 0xEC200001,
2600 0x81C, 0xEB220001,
2601 0x81C, 0xEA240001,
2602 0x81C, 0xCD260001,
2603 0x81C, 0xCC280001,
2604 0x81C, 0xCB2A0001,
2605 0x81C, 0xCA2C0001,
2606 0x81C, 0xC92E0001,
2607 0x81C, 0xC8300001,
2608 0x81C, 0xA6320001,
2609 0x81C, 0xA5340001,
2610 0x81C, 0xA4360001,
2611 0x81C, 0xA3380001,
2612 0x81C, 0xA23A0001,
2613 0x81C, 0x883C0001,
2614 0x81C, 0x873E0001,
2615 0x81C, 0x86400001,
2616 0x81C, 0x85420001,
2617 0x81C, 0x84440001,
2618 0x81C, 0x83460001,
2619 0x81C, 0x82480001,
2620 0x81C, 0x814A0001,
2621 0x81C, 0x484C0001,
2622 0x81C, 0x474E0001,
2623 0x81C, 0x46500001,
2624 0x81C, 0x45520001,
2625 0x81C, 0x44540001,
2626 0x81C, 0x43560001,
2627 0x81C, 0x42580001,
2628 0x81C, 0x415A0001,
2629 0x81C, 0x255C0001,
2630 0x81C, 0x245E0001,
2631 0x81C, 0x23600001,
2632 0x81C, 0x22620001,
2633 0x81C, 0x21640001,
2634 0x81C, 0x21660001,
2635 0x81C, 0x21680001,
2636 0x81C, 0x216A0001,
2637 0x81C, 0x216C0001,
2638 0x81C, 0x216E0001,
2639 0x81C, 0x21700001,
2640 0x81C, 0x21720001,
2641 0x81C, 0x21740001,
2642 0x81C, 0x21760001,
2643 0x81C, 0x21780001,
2644 0x81C, 0x217A0001,
2645 0x81C, 0x217C0001,
2646 0x81C, 0x217E0001,
2647 0xFF0F07D0, 0xCDEF,
2648 0x81C, 0xF9000001,
2649 0x81C, 0xF8020001,
2650 0x81C, 0xF7040001,
2651 0x81C, 0xF6060001,
2652 0x81C, 0xF5080001,
2653 0x81C, 0xF40A0001,
2654 0x81C, 0xF30C0001,
2655 0x81C, 0xF20E0001,
2656 0x81C, 0xF1100001,
2657 0x81C, 0xF0120001,
2658 0x81C, 0xEF140001,
2659 0x81C, 0xEE160001,
2660 0x81C, 0xED180001,
2661 0x81C, 0xEC1A0001,
2662 0x81C, 0xEB1C0001,
2663 0x81C, 0xEA1E0001,
2664 0x81C, 0xCD200001,
2665 0x81C, 0xCC220001,
2666 0x81C, 0xCB240001,
2667 0x81C, 0xCA260001,
2668 0x81C, 0xC9280001,
2669 0x81C, 0xC82A0001,
2670 0x81C, 0xC72C0001,
2671 0x81C, 0xC62E0001,
2672 0x81C, 0xA5300001,
2673 0x81C, 0xA4320001,
2674 0x81C, 0xA3340001,
2675 0x81C, 0xA2360001,
2676 0x81C, 0x88380001,
2677 0x81C, 0x873A0001,
2678 0x81C, 0x863C0001,
2679 0x81C, 0x853E0001,
2680 0x81C, 0x84400001,
2681 0x81C, 0x83420001,
2682 0x81C, 0x82440001,
2683 0x81C, 0x81460001,
2684 0x81C, 0x48480001,
2685 0x81C, 0x474A0001,
2686 0x81C, 0x464C0001,
2687 0x81C, 0x454E0001,
2688 0x81C, 0x44500001,
2689 0x81C, 0x43520001,
2690 0x81C, 0x42540001,
2691 0x81C, 0x41560001,
2692 0x81C, 0x25580001,
2693 0x81C, 0x245A0001,
2694 0x81C, 0x235C0001,
2695 0x81C, 0x225E0001,
2696 0x81C, 0x21600001,
2697 0x81C, 0x21620001,
2698 0x81C, 0x21640001,
2699 0x81C, 0x21660001,
2700 0x81C, 0x21680001,
2701 0x81C, 0x216A0001,
2702 0x81C, 0x236C0001,
2703 0x81C, 0x226E0001,
2704 0x81C, 0x21700001,
2705 0x81C, 0x21720001,
2706 0x81C, 0x21740001,
2707 0x81C, 0x21760001,
2708 0x81C, 0x21780001,
2709 0x81C, 0x217A0001,
2710 0x81C, 0x217C0001,
2711 0x81C, 0x217E0001,
2712 0xCDCDCDCD, 0xCDCD,
2713 0x81C, 0xFF000001,
2714 0x81C, 0xFF020001,
2715 0x81C, 0xFF040001,
2716 0x81C, 0xFF060001,
2717 0x81C, 0xFF080001,
2718 0x81C, 0xFE0A0001,
2719 0x81C, 0xFD0C0001,
2720 0x81C, 0xFC0E0001,
2721 0x81C, 0xFB100001,
2722 0x81C, 0xFA120001,
2723 0x81C, 0xF9140001,
2724 0x81C, 0xF8160001,
2725 0x81C, 0xF7180001,
2726 0x81C, 0xF61A0001,
2727 0x81C, 0xF51C0001,
2728 0x81C, 0xF41E0001,
2729 0x81C, 0xF3200001,
2730 0x81C, 0xF2220001,
2731 0x81C, 0xF1240001,
2732 0x81C, 0xF0260001,
2733 0x81C, 0xEF280001,
2734 0x81C, 0xEE2A0001,
2735 0x81C, 0xED2C0001,
2736 0x81C, 0xEC2E0001,
2737 0x81C, 0xEB300001,
2738 0x81C, 0xEA320001,
2739 0x81C, 0xE9340001,
2740 0x81C, 0xE8360001,
2741 0x81C, 0xE7380001,
2742 0x81C, 0xE63A0001,
2743 0x81C, 0xE53C0001,
2744 0x81C, 0xC73E0001,
2745 0x81C, 0xC6400001,
2746 0x81C, 0xC5420001,
2747 0x81C, 0xC4440001,
2748 0x81C, 0xC3460001,
2749 0x81C, 0xC2480001,
2750 0x81C, 0xC14A0001,
2751 0x81C, 0xA74C0001,
2752 0x81C, 0xA64E0001,
2753 0x81C, 0xA5500001,
2754 0x81C, 0xA4520001,
2755 0x81C, 0xA3540001,
2756 0x81C, 0xA2560001,
2757 0x81C, 0xA1580001,
2758 0x81C, 0x675A0001,
2759 0x81C, 0x665C0001,
2760 0x81C, 0x655E0001,
2761 0x81C, 0x64600001,
2762 0x81C, 0x63620001,
2763 0x81C, 0x48640001,
2764 0x81C, 0x47660001,
2765 0x81C, 0x46680001,
2766 0x81C, 0x456A0001,
2767 0x81C, 0x446C0001,
2768 0x81C, 0x436E0001,
2769 0x81C, 0x42700001,
2770 0x81C, 0x41720001,
2771 0x81C, 0x41740001,
2772 0x81C, 0x41760001,
2773 0x81C, 0x41780001,
2774 0x81C, 0x417A0001,
2775 0x81C, 0x417C0001,
2776 0x81C, 0x417E0001,
2777 0xFF0F07D8, 0xDEAD,
2778 0xFF0F0180, 0xABCD,
2779 0x81C, 0xFC800001,
2780 0x81C, 0xFB820001,
2781 0x81C, 0xFA840001,
2782 0x81C, 0xF9860001,
2783 0x81C, 0xF8880001,
2784 0x81C, 0xF78A0001,
2785 0x81C, 0xF68C0001,
2786 0x81C, 0xF58E0001,
2787 0x81C, 0xF4900001,
2788 0x81C, 0xF3920001,
2789 0x81C, 0xF2940001,
2790 0x81C, 0xF1960001,
2791 0x81C, 0xF0980001,
2792 0x81C, 0xEF9A0001,
2793 0x81C, 0xEE9C0001,
2794 0x81C, 0xED9E0001,
2795 0x81C, 0xECA00001,
2796 0x81C, 0xEBA20001,
2797 0x81C, 0xEAA40001,
2798 0x81C, 0xE9A60001,
2799 0x81C, 0xE8A80001,
2800 0x81C, 0xE7AA0001,
2801 0x81C, 0xE6AC0001,
2802 0x81C, 0xE5AE0001,
2803 0x81C, 0xE4B00001,
2804 0x81C, 0xE3B20001,
2805 0x81C, 0xA8B40001,
2806 0x81C, 0xA7B60001,
2807 0x81C, 0xA6B80001,
2808 0x81C, 0xA5BA0001,
2809 0x81C, 0xA4BC0001,
2810 0x81C, 0xA3BE0001,
2811 0x81C, 0xA2C00001,
2812 0x81C, 0xA1C20001,
2813 0x81C, 0x68C40001,
2814 0x81C, 0x67C60001,
2815 0x81C, 0x66C80001,
2816 0x81C, 0x65CA0001,
2817 0x81C, 0x64CC0001,
2818 0x81C, 0x47CE0001,
2819 0x81C, 0x46D00001,
2820 0x81C, 0x45D20001,
2821 0x81C, 0x44D40001,
2822 0x81C, 0x43D60001,
2823 0x81C, 0x42D80001,
2824 0x81C, 0x08DA0001,
2825 0x81C, 0x07DC0001,
2826 0x81C, 0x06DE0001,
2827 0x81C, 0x05E00001,
2828 0x81C, 0x04E20001,
2829 0x81C, 0x03E40001,
2830 0x81C, 0x02E60001,
2831 0x81C, 0x01E80001,
2832 0x81C, 0x01EA0001,
2833 0x81C, 0x01EC0001,
2834 0x81C, 0x01EE0001,
2835 0x81C, 0x01F00001,
2836 0x81C, 0x01F20001,
2837 0x81C, 0x01F40001,
2838 0x81C, 0x01F60001,
2839 0x81C, 0x01F80001,
2840 0x81C, 0x01FA0001,
2841 0x81C, 0x01FC0001,
2842 0x81C, 0x01FE0001,
2843 0xFF0F0280, 0xCDEF,
2844 0x81C, 0xFC800001,
2845 0x81C, 0xFB820001,
2846 0x81C, 0xFA840001,
2847 0x81C, 0xF9860001,
2848 0x81C, 0xF8880001,
2849 0x81C, 0xF78A0001,
2850 0x81C, 0xF68C0001,
2851 0x81C, 0xF58E0001,
2852 0x81C, 0xF4900001,
2853 0x81C, 0xF3920001,
2854 0x81C, 0xF2940001,
2855 0x81C, 0xF1960001,
2856 0x81C, 0xF0980001,
2857 0x81C, 0xEF9A0001,
2858 0x81C, 0xEE9C0001,
2859 0x81C, 0xED9E0001,
2860 0x81C, 0xECA00001,
2861 0x81C, 0xEBA20001,
2862 0x81C, 0xEAA40001,
2863 0x81C, 0xE9A60001,
2864 0x81C, 0xE8A80001,
2865 0x81C, 0xE7AA0001,
2866 0x81C, 0xE6AC0001,
2867 0x81C, 0xE5AE0001,
2868 0x81C, 0xE4B00001,
2869 0x81C, 0xE3B20001,
2870 0x81C, 0xA8B40001,
2871 0x81C, 0xA7B60001,
2872 0x81C, 0xA6B80001,
2873 0x81C, 0xA5BA0001,
2874 0x81C, 0xA4BC0001,
2875 0x81C, 0xA3BE0001,
2876 0x81C, 0xA2C00001,
2877 0x81C, 0xA1C20001,
2878 0x81C, 0x68C40001,
2879 0x81C, 0x67C60001,
2880 0x81C, 0x66C80001,
2881 0x81C, 0x65CA0001,
2882 0x81C, 0x64CC0001,
2883 0x81C, 0x47CE0001,
2884 0x81C, 0x46D00001,
2885 0x81C, 0x45D20001,
2886 0x81C, 0x44D40001,
2887 0x81C, 0x43D60001,
2888 0x81C, 0x42D80001,
2889 0x81C, 0x08DA0001,
2890 0x81C, 0x07DC0001,
2891 0x81C, 0x06DE0001,
2892 0x81C, 0x05E00001,
2893 0x81C, 0x04E20001,
2894 0x81C, 0x03E40001,
2895 0x81C, 0x02E60001,
2896 0x81C, 0x01E80001,
2897 0x81C, 0x01EA0001,
2898 0x81C, 0x01EC0001,
2899 0x81C, 0x01EE0001,
2900 0x81C, 0x01F00001,
2901 0x81C, 0x01F20001,
2902 0x81C, 0x01F40001,
2903 0x81C, 0x01F60001,
2904 0x81C, 0x01F80001,
2905 0x81C, 0x01FA0001,
2906 0x81C, 0x01FC0001,
2907 0x81C, 0x01FE0001,
2908 0xFF0F01C0, 0xCDEF,
2909 0x81C, 0xFC800001,
2910 0x81C, 0xFB820001,
2911 0x81C, 0xFA840001,
2912 0x81C, 0xF9860001,
2913 0x81C, 0xF8880001,
2914 0x81C, 0xF78A0001,
2915 0x81C, 0xF68C0001,
2916 0x81C, 0xF58E0001,
2917 0x81C, 0xF4900001,
2918 0x81C, 0xF3920001,
2919 0x81C, 0xF2940001,
2920 0x81C, 0xF1960001,
2921 0x81C, 0xF0980001,
2922 0x81C, 0xEF9A0001,
2923 0x81C, 0xEE9C0001,
2924 0x81C, 0xED9E0001,
2925 0x81C, 0xECA00001,
2926 0x81C, 0xEBA20001,
2927 0x81C, 0xEAA40001,
2928 0x81C, 0xE9A60001,
2929 0x81C, 0xE8A80001,
2930 0x81C, 0xE7AA0001,
2931 0x81C, 0xE6AC0001,
2932 0x81C, 0xE5AE0001,
2933 0x81C, 0xE4B00001,
2934 0x81C, 0xE3B20001,
2935 0x81C, 0xA8B40001,
2936 0x81C, 0xA7B60001,
2937 0x81C, 0xA6B80001,
2938 0x81C, 0xA5BA0001,
2939 0x81C, 0xA4BC0001,
2940 0x81C, 0xA3BE0001,
2941 0x81C, 0xA2C00001,
2942 0x81C, 0xA1C20001,
2943 0x81C, 0x68C40001,
2944 0x81C, 0x67C60001,
2945 0x81C, 0x66C80001,
2946 0x81C, 0x65CA0001,
2947 0x81C, 0x64CC0001,
2948 0x81C, 0x47CE0001,
2949 0x81C, 0x46D00001,
2950 0x81C, 0x45D20001,
2951 0x81C, 0x44D40001,
2952 0x81C, 0x43D60001,
2953 0x81C, 0x42D80001,
2954 0x81C, 0x08DA0001,
2955 0x81C, 0x07DC0001,
2956 0x81C, 0x06DE0001,
2957 0x81C, 0x05E00001,
2958 0x81C, 0x04E20001,
2959 0x81C, 0x03E40001,
2960 0x81C, 0x02E60001,
2961 0x81C, 0x01E80001,
2962 0x81C, 0x01EA0001,
2963 0x81C, 0x01EC0001,
2964 0x81C, 0x01EE0001,
2965 0x81C, 0x01F00001,
2966 0x81C, 0x01F20001,
2967 0x81C, 0x01F40001,
2968 0x81C, 0x01F60001,
2969 0x81C, 0x01F80001,
2970 0x81C, 0x01FA0001,
2971 0x81C, 0x01FC0001,
2972 0x81C, 0x01FE0001,
2973 0xFF0F02C0, 0xCDEF,
2974 0x81C, 0xFC800001,
2975 0x81C, 0xFB820001,
2976 0x81C, 0xFA840001,
2977 0x81C, 0xF9860001,
2978 0x81C, 0xF8880001,
2979 0x81C, 0xF78A0001,
2980 0x81C, 0xF68C0001,
2981 0x81C, 0xF58E0001,
2982 0x81C, 0xF4900001,
2983 0x81C, 0xF3920001,
2984 0x81C, 0xF2940001,
2985 0x81C, 0xF1960001,
2986 0x81C, 0xF0980001,
2987 0x81C, 0xEF9A0001,
2988 0x81C, 0xEE9C0001,
2989 0x81C, 0xED9E0001,
2990 0x81C, 0xECA00001,
2991 0x81C, 0xEBA20001,
2992 0x81C, 0xEAA40001,
2993 0x81C, 0xE9A60001,
2994 0x81C, 0xE8A80001,
2995 0x81C, 0xE7AA0001,
2996 0x81C, 0xE6AC0001,
2997 0x81C, 0xE5AE0001,
2998 0x81C, 0xE4B00001,
2999 0x81C, 0xE3B20001,
3000 0x81C, 0xA8B40001,
3001 0x81C, 0xA7B60001,
3002 0x81C, 0xA6B80001,
3003 0x81C, 0xA5BA0001,
3004 0x81C, 0xA4BC0001,
3005 0x81C, 0xA3BE0001,
3006 0x81C, 0xA2C00001,
3007 0x81C, 0xA1C20001,
3008 0x81C, 0x68C40001,
3009 0x81C, 0x67C60001,
3010 0x81C, 0x66C80001,
3011 0x81C, 0x65CA0001,
3012 0x81C, 0x64CC0001,
3013 0x81C, 0x47CE0001,
3014 0x81C, 0x46D00001,
3015 0x81C, 0x45D20001,
3016 0x81C, 0x44D40001,
3017 0x81C, 0x43D60001,
3018 0x81C, 0x42D80001,
3019 0x81C, 0x08DA0001,
3020 0x81C, 0x07DC0001,
3021 0x81C, 0x06DE0001,
3022 0x81C, 0x05E00001,
3023 0x81C, 0x04E20001,
3024 0x81C, 0x03E40001,
3025 0x81C, 0x02E60001,
3026 0x81C, 0x01E80001,
3027 0x81C, 0x01EA0001,
3028 0x81C, 0x01EC0001,
3029 0x81C, 0x01EE0001,
3030 0x81C, 0x01F00001,
3031 0x81C, 0x01F20001,
3032 0x81C, 0x01F40001,
3033 0x81C, 0x01F60001,
3034 0x81C, 0x01F80001,
3035 0x81C, 0x01FA0001,
3036 0x81C, 0x01FC0001,
3037 0x81C, 0x01FE0001,
3038 0xFF0F07D8, 0xCDEF,
3039 0x81C, 0xFC800001,
3040 0x81C, 0xFB820001,
3041 0x81C, 0xFA840001,
3042 0x81C, 0xF9860001,
3043 0x81C, 0xF8880001,
3044 0x81C, 0xF78A0001,
3045 0x81C, 0xF68C0001,
3046 0x81C, 0xF58E0001,
3047 0x81C, 0xF4900001,
3048 0x81C, 0xF3920001,
3049 0x81C, 0xF2940001,
3050 0x81C, 0xF1960001,
3051 0x81C, 0xF0980001,
3052 0x81C, 0xEF9A0001,
3053 0x81C, 0xEE9C0001,
3054 0x81C, 0xED9E0001,
3055 0x81C, 0xECA00001,
3056 0x81C, 0xEBA20001,
3057 0x81C, 0xEAA40001,
3058 0x81C, 0xE9A60001,
3059 0x81C, 0xE8A80001,
3060 0x81C, 0xE7AA0001,
3061 0x81C, 0xE6AC0001,
3062 0x81C, 0xE5AE0001,
3063 0x81C, 0xE4B00001,
3064 0x81C, 0xE3B20001,
3065 0x81C, 0xA8B40001,
3066 0x81C, 0xA7B60001,
3067 0x81C, 0xA6B80001,
3068 0x81C, 0xA5BA0001,
3069 0x81C, 0xA4BC0001,
3070 0x81C, 0xA3BE0001,
3071 0x81C, 0xA2C00001,
3072 0x81C, 0xA1C20001,
3073 0x81C, 0x68C40001,
3074 0x81C, 0x67C60001,
3075 0x81C, 0x66C80001,
3076 0x81C, 0x65CA0001,
3077 0x81C, 0x64CC0001,
3078 0x81C, 0x47CE0001,
3079 0x81C, 0x46D00001,
3080 0x81C, 0x45D20001,
3081 0x81C, 0x44D40001,
3082 0x81C, 0x43D60001,
3083 0x81C, 0x42D80001,
3084 0x81C, 0x08DA0001,
3085 0x81C, 0x07DC0001,
3086 0x81C, 0x06DE0001,
3087 0x81C, 0x05E00001,
3088 0x81C, 0x04E20001,
3089 0x81C, 0x03E40001,
3090 0x81C, 0x02E60001,
3091 0x81C, 0x01E80001,
3092 0x81C, 0x01EA0001,
3093 0x81C, 0x01EC0001,
3094 0x81C, 0x01EE0001,
3095 0x81C, 0x01F00001,
3096 0x81C, 0x01F20001,
3097 0x81C, 0x01F40001,
3098 0x81C, 0x01F60001,
3099 0x81C, 0x01F80001,
3100 0x81C, 0x01FA0001,
3101 0x81C, 0x01FC0001,
3102 0x81C, 0x01FE0001,
3103 0xFF0F07D0, 0xCDEF,
3104 0x81C, 0xFC800001,
3105 0x81C, 0xFB820001,
3106 0x81C, 0xFA840001,
3107 0x81C, 0xF9860001,
3108 0x81C, 0xF8880001,
3109 0x81C, 0xF78A0001,
3110 0x81C, 0xF68C0001,
3111 0x81C, 0xF58E0001,
3112 0x81C, 0xF4900001,
3113 0x81C, 0xF3920001,
3114 0x81C, 0xF2940001,
3115 0x81C, 0xF1960001,
3116 0x81C, 0xF0980001,
3117 0x81C, 0xEF9A0001,
3118 0x81C, 0xEE9C0001,
3119 0x81C, 0xED9E0001,
3120 0x81C, 0xECA00001,
3121 0x81C, 0xEBA20001,
3122 0x81C, 0xEAA40001,
3123 0x81C, 0xE9A60001,
3124 0x81C, 0xE8A80001,
3125 0x81C, 0xE7AA0001,
3126 0x81C, 0xE6AC0001,
3127 0x81C, 0xE5AE0001,
3128 0x81C, 0xE4B00001,
3129 0x81C, 0xE3B20001,
3130 0x81C, 0xA8B40001,
3131 0x81C, 0xA7B60001,
3132 0x81C, 0xA6B80001,
3133 0x81C, 0xA5BA0001,
3134 0x81C, 0xA4BC0001,
3135 0x81C, 0xA3BE0001,
3136 0x81C, 0xA2C00001,
3137 0x81C, 0xA1C20001,
3138 0x81C, 0x68C40001,
3139 0x81C, 0x67C60001,
3140 0x81C, 0x66C80001,
3141 0x81C, 0x65CA0001,
3142 0x81C, 0x64CC0001,
3143 0x81C, 0x47CE0001,
3144 0x81C, 0x46D00001,
3145 0x81C, 0x45D20001,
3146 0x81C, 0x44D40001,
3147 0x81C, 0x43D60001,
3148 0x81C, 0x42D80001,
3149 0x81C, 0x08DA0001,
3150 0x81C, 0x07DC0001,
3151 0x81C, 0x06DE0001,
3152 0x81C, 0x05E00001,
3153 0x81C, 0x04E20001,
3154 0x81C, 0x03E40001,
3155 0x81C, 0x02E60001,
3156 0x81C, 0x01E80001,
3157 0x81C, 0x01EA0001,
3158 0x81C, 0x01EC0001,
3159 0x81C, 0x01EE0001,
3160 0x81C, 0x01F00001,
3161 0x81C, 0x01F20001,
3162 0x81C, 0x01F40001,
3163 0x81C, 0x01F60001,
3164 0x81C, 0x01F80001,
3165 0x81C, 0x01FA0001,
3166 0x81C, 0x01FC0001,
3167 0x81C, 0x01FE0001,
3168 0xCDCDCDCD, 0xCDCD,
3169 0x81C, 0xFF800001,
3170 0x81C, 0xFF820001,
3171 0x81C, 0xFF840001,
3172 0x81C, 0xFE860001,
3173 0x81C, 0xFD880001,
3174 0x81C, 0xFC8A0001,
3175 0x81C, 0xFB8C0001,
3176 0x81C, 0xFA8E0001,
3177 0x81C, 0xF9900001,
3178 0x81C, 0xF8920001,
3179 0x81C, 0xF7940001,
3180 0x81C, 0xF6960001,
3181 0x81C, 0xF5980001,
3182 0x81C, 0xF49A0001,
3183 0x81C, 0xF39C0001,
3184 0x81C, 0xF29E0001,
3185 0x81C, 0xF1A00001,
3186 0x81C, 0xF0A20001,
3187 0x81C, 0xEFA40001,
3188 0x81C, 0xEEA60001,
3189 0x81C, 0xEDA80001,
3190 0x81C, 0xECAA0001,
3191 0x81C, 0xEBAC0001,
3192 0x81C, 0xEAAE0001,
3193 0x81C, 0xE9B00001,
3194 0x81C, 0xE8B20001,
3195 0x81C, 0xE7B40001,
3196 0x81C, 0xE6B60001,
3197 0x81C, 0xE5B80001,
3198 0x81C, 0xE4BA0001,
3199 0x81C, 0xE3BC0001,
3200 0x81C, 0xA8BE0001,
3201 0x81C, 0xA7C00001,
3202 0x81C, 0xA6C20001,
3203 0x81C, 0xA5C40001,
3204 0x81C, 0xA4C60001,
3205 0x81C, 0xA3C80001,
3206 0x81C, 0xA2CA0001,
3207 0x81C, 0xA1CC0001,
3208 0x81C, 0x68CE0001,
3209 0x81C, 0x67D00001,
3210 0x81C, 0x66D20001,
3211 0x81C, 0x65D40001,
3212 0x81C, 0x64D60001,
3213 0x81C, 0x47D80001,
3214 0x81C, 0x46DA0001,
3215 0x81C, 0x45DC0001,
3216 0x81C, 0x44DE0001,
3217 0x81C, 0x43E00001,
3218 0x81C, 0x42E20001,
3219 0x81C, 0x08E40001,
3220 0x81C, 0x07E60001,
3221 0x81C, 0x06E80001,
3222 0x81C, 0x05EA0001,
3223 0x81C, 0x04EC0001,
3224 0x81C, 0x03EE0001,
3225 0x81C, 0x02F00001,
3226 0x81C, 0x01F20001,
3227 0x81C, 0x01F40001,
3228 0x81C, 0x01F60001,
3229 0x81C, 0x01F80001,
3230 0x81C, 0x01FA0001,
3231 0x81C, 0x01FC0001,
3232 0x81C, 0x01FE0001,
3233 0xFF0F0180, 0xDEAD,
3234 0xC50, 0x00000022,
3235 0xC50, 0x00000020,
3236 0xE50, 0x00000022,
3237 0xE50, 0x00000020,
3238
3239};
3240
3241u32 RTL8821AE_AGC_TAB_ARRAY[] = {
3242 0x81C, 0xBF000001,
3243 0x81C, 0xBF020001,
3244 0x81C, 0xBF040001,
3245 0x81C, 0xBF060001,
3246 0x81C, 0xBE080001,
3247 0x81C, 0xBD0A0001,
3248 0x81C, 0xBC0C0001,
3249 0x81C, 0xBA0E0001,
3250 0x81C, 0xB9100001,
3251 0x81C, 0xB8120001,
3252 0x81C, 0xB7140001,
3253 0x81C, 0xB6160001,
3254 0x81C, 0xB5180001,
3255 0x81C, 0xB41A0001,
3256 0x81C, 0xB31C0001,
3257 0x81C, 0xB21E0001,
3258 0x81C, 0xB1200001,
3259 0x81C, 0xB0220001,
3260 0x81C, 0xAF240001,
3261 0x81C, 0xAE260001,
3262 0x81C, 0xAD280001,
3263 0x81C, 0xAC2A0001,
3264 0x81C, 0xAB2C0001,
3265 0x81C, 0xAA2E0001,
3266 0x81C, 0xA9300001,
3267 0x81C, 0xA8320001,
3268 0x81C, 0xA7340001,
3269 0x81C, 0xA6360001,
3270 0x81C, 0xA5380001,
3271 0x81C, 0xA43A0001,
3272 0x81C, 0xA33C0001,
3273 0x81C, 0x673E0001,
3274 0x81C, 0x66400001,
3275 0x81C, 0x65420001,
3276 0x81C, 0x64440001,
3277 0x81C, 0x63460001,
3278 0x81C, 0x62480001,
3279 0x81C, 0x614A0001,
3280 0x81C, 0x474C0001,
3281 0x81C, 0x464E0001,
3282 0x81C, 0x45500001,
3283 0x81C, 0x44520001,
3284 0x81C, 0x43540001,
3285 0x81C, 0x42560001,
3286 0x81C, 0x41580001,
3287 0x81C, 0x285A0001,
3288 0x81C, 0x275C0001,
3289 0x81C, 0x265E0001,
3290 0x81C, 0x25600001,
3291 0x81C, 0x24620001,
3292 0x81C, 0x0A640001,
3293 0x81C, 0x09660001,
3294 0x81C, 0x08680001,
3295 0x81C, 0x076A0001,
3296 0x81C, 0x066C0001,
3297 0x81C, 0x056E0001,
3298 0x81C, 0x04700001,
3299 0x81C, 0x03720001,
3300 0x81C, 0x02740001,
3301 0x81C, 0x01760001,
3302 0x81C, 0x01780001,
3303 0x81C, 0x017A0001,
3304 0x81C, 0x017C0001,
3305 0x81C, 0x017E0001,
3306 0xFF0F02C0, 0xABCD,
3307 0x81C, 0xFB000101,
3308 0x81C, 0xFA020101,
3309 0x81C, 0xF9040101,
3310 0x81C, 0xF8060101,
3311 0x81C, 0xF7080101,
3312 0x81C, 0xF60A0101,
3313 0x81C, 0xF50C0101,
3314 0x81C, 0xF40E0101,
3315 0x81C, 0xF3100101,
3316 0x81C, 0xF2120101,
3317 0x81C, 0xF1140101,
3318 0x81C, 0xF0160101,
3319 0x81C, 0xEF180101,
3320 0x81C, 0xEE1A0101,
3321 0x81C, 0xED1C0101,
3322 0x81C, 0xEC1E0101,
3323 0x81C, 0xEB200101,
3324 0x81C, 0xEA220101,
3325 0x81C, 0xE9240101,
3326 0x81C, 0xE8260101,
3327 0x81C, 0xE7280101,
3328 0x81C, 0xE62A0101,
3329 0x81C, 0xE52C0101,
3330 0x81C, 0xE42E0101,
3331 0x81C, 0xE3300101,
3332 0x81C, 0xA5320101,
3333 0x81C, 0xA4340101,
3334 0x81C, 0xA3360101,
3335 0x81C, 0x87380101,
3336 0x81C, 0x863A0101,
3337 0x81C, 0x853C0101,
3338 0x81C, 0x843E0101,
3339 0x81C, 0x69400101,
3340 0x81C, 0x68420101,
3341 0x81C, 0x67440101,
3342 0x81C, 0x66460101,
3343 0x81C, 0x49480101,
3344 0x81C, 0x484A0101,
3345 0x81C, 0x474C0101,
3346 0x81C, 0x2A4E0101,
3347 0x81C, 0x29500101,
3348 0x81C, 0x28520101,
3349 0x81C, 0x27540101,
3350 0x81C, 0x26560101,
3351 0x81C, 0x25580101,
3352 0x81C, 0x245A0101,
3353 0x81C, 0x235C0101,
3354 0x81C, 0x055E0101,
3355 0x81C, 0x04600101,
3356 0x81C, 0x03620101,
3357 0x81C, 0x02640101,
3358 0x81C, 0x01660101,
3359 0x81C, 0x01680101,
3360 0x81C, 0x016A0101,
3361 0x81C, 0x016C0101,
3362 0x81C, 0x016E0101,
3363 0x81C, 0x01700101,
3364 0x81C, 0x01720101,
3365 0xCDCDCDCD, 0xCDCD,
3366 0x81C, 0xFF000101,
3367 0x81C, 0xFF020101,
3368 0x81C, 0xFE040101,
3369 0x81C, 0xFD060101,
3370 0x81C, 0xFC080101,
3371 0x81C, 0xFD0A0101,
3372 0x81C, 0xFC0C0101,
3373 0x81C, 0xFB0E0101,
3374 0x81C, 0xFA100101,
3375 0x81C, 0xF9120101,
3376 0x81C, 0xF8140101,
3377 0x81C, 0xF7160101,
3378 0x81C, 0xF6180101,
3379 0x81C, 0xF51A0101,
3380 0x81C, 0xF41C0101,
3381 0x81C, 0xF31E0101,
3382 0x81C, 0xF2200101,
3383 0x81C, 0xF1220101,
3384 0x81C, 0xF0240101,
3385 0x81C, 0xEF260101,
3386 0x81C, 0xEE280101,
3387 0x81C, 0xED2A0101,
3388 0x81C, 0xEC2C0101,
3389 0x81C, 0xEB2E0101,
3390 0x81C, 0xEA300101,
3391 0x81C, 0xE9320101,
3392 0x81C, 0xE8340101,
3393 0x81C, 0xE7360101,
3394 0x81C, 0xE6380101,
3395 0x81C, 0xE53A0101,
3396 0x81C, 0xE43C0101,
3397 0x81C, 0xE33E0101,
3398 0x81C, 0xA5400101,
3399 0x81C, 0xA4420101,
3400 0x81C, 0xA3440101,
3401 0x81C, 0x87460101,
3402 0x81C, 0x86480101,
3403 0x81C, 0x854A0101,
3404 0x81C, 0x844C0101,
3405 0x81C, 0x694E0101,
3406 0x81C, 0x68500101,
3407 0x81C, 0x67520101,
3408 0x81C, 0x66540101,
3409 0x81C, 0x49560101,
3410 0x81C, 0x48580101,
3411 0x81C, 0x475A0101,
3412 0x81C, 0x2A5C0101,
3413 0x81C, 0x295E0101,
3414 0x81C, 0x28600101,
3415 0x81C, 0x27620101,
3416 0x81C, 0x26640101,
3417 0x81C, 0x25660101,
3418 0x81C, 0x24680101,
3419 0x81C, 0x236A0101,
3420 0x81C, 0x056C0101,
3421 0x81C, 0x046E0101,
3422 0x81C, 0x03700101,
3423 0x81C, 0x02720101,
3424 0xFF0F02C0, 0xDEAD,
3425 0x81C, 0x01740101,
3426 0x81C, 0x01760101,
3427 0x81C, 0x01780101,
3428 0x81C, 0x017A0101,
3429 0x81C, 0x017C0101,
3430 0x81C, 0x017E0101,
3431 0xC50, 0x00000022,
3432 0xC50, 0x00000020,
3433
3434};
3435
3436/******************************************************************************
3437* TXPWR_LMT.TXT
3438******************************************************************************/
3439
3440u8 *RTL8812AE_TXPWR_LMT[] = {
3441 "FCC", "2.4G", "20M", "CCK", "1T", "01", "36",
3442 "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
3443 "MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
3444 "FCC", "2.4G", "20M", "CCK", "1T", "02", "36",
3445 "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
3446 "MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
3447 "FCC", "2.4G", "20M", "CCK", "1T", "03", "36",
3448 "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
3449 "MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
3450 "FCC", "2.4G", "20M", "CCK", "1T", "04", "36",
3451 "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
3452 "MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
3453 "FCC", "2.4G", "20M", "CCK", "1T", "05", "36",
3454 "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32",
3455 "MKK", "2.4G", "20M", "CCK", "1T", "05", "32",
3456 "FCC", "2.4G", "20M", "CCK", "1T", "06", "36",
3457 "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32",
3458 "MKK", "2.4G", "20M", "CCK", "1T", "06", "32",
3459 "FCC", "2.4G", "20M", "CCK", "1T", "07", "36",
3460 "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32",
3461 "MKK", "2.4G", "20M", "CCK", "1T", "07", "32",
3462 "FCC", "2.4G", "20M", "CCK", "1T", "08", "36",
3463 "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32",
3464 "MKK", "2.4G", "20M", "CCK", "1T", "08", "32",
3465 "FCC", "2.4G", "20M", "CCK", "1T", "09", "36",
3466 "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32",
3467 "MKK", "2.4G", "20M", "CCK", "1T", "09", "32",
3468 "FCC", "2.4G", "20M", "CCK", "1T", "10", "36",
3469 "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32",
3470 "MKK", "2.4G", "20M", "CCK", "1T", "10", "32",
3471 "FCC", "2.4G", "20M", "CCK", "1T", "11", "36",
3472 "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32",
3473 "MKK", "2.4G", "20M", "CCK", "1T", "11", "32",
3474 "FCC", "2.4G", "20M", "CCK", "1T", "12", "63",
3475 "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32",
3476 "MKK", "2.4G", "20M", "CCK", "1T", "12", "32",
3477 "FCC", "2.4G", "20M", "CCK", "1T", "13", "63",
3478 "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32",
3479 "MKK", "2.4G", "20M", "CCK", "1T", "13", "32",
3480 "FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
3481 "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
3482 "MKK", "2.4G", "20M", "CCK", "1T", "14", "32",
3483 "FCC", "2.4G", "20M", "OFDM", "1T", "01", "34",
3484 "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32",
3485 "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32",
3486 "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36",
3487 "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32",
3488 "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32",
3489 "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36",
3490 "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32",
3491 "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32",
3492 "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36",
3493 "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32",
3494 "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32",
3495 "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36",
3496 "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32",
3497 "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32",
3498 "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36",
3499 "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32",
3500 "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32",
3501 "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36",
3502 "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32",
3503 "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32",
3504 "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36",
3505 "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32",
3506 "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32",
3507 "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36",
3508 "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32",
3509 "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32",
3510 "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36",
3511 "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32",
3512 "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32",
3513 "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32",
3514 "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32",
3515 "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32",
3516 "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63",
3517 "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32",
3518 "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32",
3519 "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63",
3520 "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32",
3521 "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32",
3522 "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
3523 "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
3524 "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
3525 "FCC", "2.4G", "20M", "HT", "1T", "01", "34",
3526 "ETSI", "2.4G", "20M", "HT", "1T", "01", "32",
3527 "MKK", "2.4G", "20M", "HT", "1T", "01", "32",
3528 "FCC", "2.4G", "20M", "HT", "1T", "02", "36",
3529 "ETSI", "2.4G", "20M", "HT", "1T", "02", "32",
3530 "MKK", "2.4G", "20M", "HT", "1T", "02", "32",
3531 "FCC", "2.4G", "20M", "HT", "1T", "03", "36",
3532 "ETSI", "2.4G", "20M", "HT", "1T", "03", "32",
3533 "MKK", "2.4G", "20M", "HT", "1T", "03", "32",
3534 "FCC", "2.4G", "20M", "HT", "1T", "04", "36",
3535 "ETSI", "2.4G", "20M", "HT", "1T", "04", "32",
3536 "MKK", "2.4G", "20M", "HT", "1T", "04", "32",
3537 "FCC", "2.4G", "20M", "HT", "1T", "05", "36",
3538 "ETSI", "2.4G", "20M", "HT", "1T", "05", "32",
3539 "MKK", "2.4G", "20M", "HT", "1T", "05", "32",
3540 "FCC", "2.4G", "20M", "HT", "1T", "06", "36",
3541 "ETSI", "2.4G", "20M", "HT", "1T", "06", "32",
3542 "MKK", "2.4G", "20M", "HT", "1T", "06", "32",
3543 "FCC", "2.4G", "20M", "HT", "1T", "07", "36",
3544 "ETSI", "2.4G", "20M", "HT", "1T", "07", "32",
3545 "MKK", "2.4G", "20M", "HT", "1T", "07", "32",
3546 "FCC", "2.4G", "20M", "HT", "1T", "08", "36",
3547 "ETSI", "2.4G", "20M", "HT", "1T", "08", "32",
3548 "MKK", "2.4G", "20M", "HT", "1T", "08", "32",
3549 "FCC", "2.4G", "20M", "HT", "1T", "09", "36",
3550 "ETSI", "2.4G", "20M", "HT", "1T", "09", "32",
3551 "MKK", "2.4G", "20M", "HT", "1T", "09", "32",
3552 "FCC", "2.4G", "20M", "HT", "1T", "10", "36",
3553 "ETSI", "2.4G", "20M", "HT", "1T", "10", "32",
3554 "MKK", "2.4G", "20M", "HT", "1T", "10", "32",
3555 "FCC", "2.4G", "20M", "HT", "1T", "11", "32",
3556 "ETSI", "2.4G", "20M", "HT", "1T", "11", "32",
3557 "MKK", "2.4G", "20M", "HT", "1T", "11", "32",
3558 "FCC", "2.4G", "20M", "HT", "1T", "12", "63",
3559 "ETSI", "2.4G", "20M", "HT", "1T", "12", "32",
3560 "MKK", "2.4G", "20M", "HT", "1T", "12", "32",
3561 "FCC", "2.4G", "20M", "HT", "1T", "13", "63",
3562 "ETSI", "2.4G", "20M", "HT", "1T", "13", "32",
3563 "MKK", "2.4G", "20M", "HT", "1T", "13", "32",
3564 "FCC", "2.4G", "20M", "HT", "1T", "14", "63",
3565 "ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
3566 "MKK", "2.4G", "20M", "HT", "1T", "14", "63",
3567 "FCC", "2.4G", "20M", "HT", "2T", "01", "32",
3568 "ETSI", "2.4G", "20M", "HT", "2T", "01", "32",
3569 "MKK", "2.4G", "20M", "HT", "2T", "01", "32",
3570 "FCC", "2.4G", "20M", "HT", "2T", "02", "34",
3571 "ETSI", "2.4G", "20M", "HT", "2T", "02", "32",
3572 "MKK", "2.4G", "20M", "HT", "2T", "02", "32",
3573 "FCC", "2.4G", "20M", "HT", "2T", "03", "34",
3574 "ETSI", "2.4G", "20M", "HT", "2T", "03", "32",
3575 "MKK", "2.4G", "20M", "HT", "2T", "03", "32",
3576 "FCC", "2.4G", "20M", "HT", "2T", "04", "34",
3577 "ETSI", "2.4G", "20M", "HT", "2T", "04", "32",
3578 "MKK", "2.4G", "20M", "HT", "2T", "04", "32",
3579 "FCC", "2.4G", "20M", "HT", "2T", "05", "34",
3580 "ETSI", "2.4G", "20M", "HT", "2T", "05", "32",
3581 "MKK", "2.4G", "20M", "HT", "2T", "05", "32",
3582 "FCC", "2.4G", "20M", "HT", "2T", "06", "34",
3583 "ETSI", "2.4G", "20M", "HT", "2T", "06", "32",
3584 "MKK", "2.4G", "20M", "HT", "2T", "06", "32",
3585 "FCC", "2.4G", "20M", "HT", "2T", "07", "34",
3586 "ETSI", "2.4G", "20M", "HT", "2T", "07", "32",
3587 "MKK", "2.4G", "20M", "HT", "2T", "07", "32",
3588 "FCC", "2.4G", "20M", "HT", "2T", "08", "34",
3589 "ETSI", "2.4G", "20M", "HT", "2T", "08", "32",
3590 "MKK", "2.4G", "20M", "HT", "2T", "08", "32",
3591 "FCC", "2.4G", "20M", "HT", "2T", "09", "34",
3592 "ETSI", "2.4G", "20M", "HT", "2T", "09", "32",
3593 "MKK", "2.4G", "20M", "HT", "2T", "09", "32",
3594 "FCC", "2.4G", "20M", "HT", "2T", "10", "34",
3595 "ETSI", "2.4G", "20M", "HT", "2T", "10", "32",
3596 "MKK", "2.4G", "20M", "HT", "2T", "10", "32",
3597 "FCC", "2.4G", "20M", "HT", "2T", "11", "30",
3598 "ETSI", "2.4G", "20M", "HT", "2T", "11", "32",
3599 "MKK", "2.4G", "20M", "HT", "2T", "11", "32",
3600 "FCC", "2.4G", "20M", "HT", "2T", "12", "63",
3601 "ETSI", "2.4G", "20M", "HT", "2T", "12", "32",
3602 "MKK", "2.4G", "20M", "HT", "2T", "12", "32",
3603 "FCC", "2.4G", "20M", "HT", "2T", "13", "63",
3604 "ETSI", "2.4G", "20M", "HT", "2T", "13", "32",
3605 "MKK", "2.4G", "20M", "HT", "2T", "13", "32",
3606 "FCC", "2.4G", "20M", "HT", "2T", "14", "63",
3607 "ETSI", "2.4G", "20M", "HT", "2T", "14", "63",
3608 "MKK", "2.4G", "20M", "HT", "2T", "14", "63",
3609 "FCC", "2.4G", "40M", "HT", "1T", "01", "63",
3610 "ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
3611 "MKK", "2.4G", "40M", "HT", "1T", "01", "63",
3612 "FCC", "2.4G", "40M", "HT", "1T", "02", "63",
3613 "ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
3614 "MKK", "2.4G", "40M", "HT", "1T", "02", "63",
3615 "FCC", "2.4G", "40M", "HT", "1T", "03", "32",
3616 "ETSI", "2.4G", "40M", "HT", "1T", "03", "32",
3617 "MKK", "2.4G", "40M", "HT", "1T", "03", "32",
3618 "FCC", "2.4G", "40M", "HT", "1T", "04", "36",
3619 "ETSI", "2.4G", "40M", "HT", "1T", "04", "32",
3620 "MKK", "2.4G", "40M", "HT", "1T", "04", "32",
3621 "FCC", "2.4G", "40M", "HT", "1T", "05", "36",
3622 "ETSI", "2.4G", "40M", "HT", "1T", "05", "32",
3623 "MKK", "2.4G", "40M", "HT", "1T", "05", "32",
3624 "FCC", "2.4G", "40M", "HT", "1T", "06", "36",
3625 "ETSI", "2.4G", "40M", "HT", "1T", "06", "32",
3626 "MKK", "2.4G", "40M", "HT", "1T", "06", "32",
3627 "FCC", "2.4G", "40M", "HT", "1T", "07", "36",
3628 "ETSI", "2.4G", "40M", "HT", "1T", "07", "32",
3629 "MKK", "2.4G", "40M", "HT", "1T", "07", "32",
3630 "FCC", "2.4G", "40M", "HT", "1T", "08", "36",
3631 "ETSI", "2.4G", "40M", "HT", "1T", "08", "32",
3632 "MKK", "2.4G", "40M", "HT", "1T", "08", "32",
3633 "FCC", "2.4G", "40M", "HT", "1T", "09", "36",
3634 "ETSI", "2.4G", "40M", "HT", "1T", "09", "32",
3635 "MKK", "2.4G", "40M", "HT", "1T", "09", "32",
3636 "FCC", "2.4G", "40M", "HT", "1T", "10", "36",
3637 "ETSI", "2.4G", "40M", "HT", "1T", "10", "32",
3638 "MKK", "2.4G", "40M", "HT", "1T", "10", "32",
3639 "FCC", "2.4G", "40M", "HT", "1T", "11", "32",
3640 "ETSI", "2.4G", "40M", "HT", "1T", "11", "32",
3641 "MKK", "2.4G", "40M", "HT", "1T", "11", "32",
3642 "FCC", "2.4G", "40M", "HT", "1T", "12", "63",
3643 "ETSI", "2.4G", "40M", "HT", "1T", "12", "32",
3644 "MKK", "2.4G", "40M", "HT", "1T", "12", "32",
3645 "FCC", "2.4G", "40M", "HT", "1T", "13", "63",
3646 "ETSI", "2.4G", "40M", "HT", "1T", "13", "32",
3647 "MKK", "2.4G", "40M", "HT", "1T", "13", "32",
3648 "FCC", "2.4G", "40M", "HT", "1T", "14", "63",
3649 "ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
3650 "MKK", "2.4G", "40M", "HT", "1T", "14", "63",
3651 "FCC", "2.4G", "40M", "HT", "2T", "01", "63",
3652 "ETSI", "2.4G", "40M", "HT", "2T", "01", "63",
3653 "MKK", "2.4G", "40M", "HT", "2T", "01", "63",
3654 "FCC", "2.4G", "40M", "HT", "2T", "02", "63",
3655 "ETSI", "2.4G", "40M", "HT", "2T", "02", "63",
3656 "MKK", "2.4G", "40M", "HT", "2T", "02", "63",
3657 "FCC", "2.4G", "40M", "HT", "2T", "03", "30",
3658 "ETSI", "2.4G", "40M", "HT", "2T", "03", "30",
3659 "MKK", "2.4G", "40M", "HT", "2T", "03", "30",
3660 "FCC", "2.4G", "40M", "HT", "2T", "04", "34",
3661 "ETSI", "2.4G", "40M", "HT", "2T", "04", "30",
3662 "MKK", "2.4G", "40M", "HT", "2T", "04", "30",
3663 "FCC", "2.4G", "40M", "HT", "2T", "05", "34",
3664 "ETSI", "2.4G", "40M", "HT", "2T", "05", "30",
3665 "MKK", "2.4G", "40M", "HT", "2T", "05", "30",
3666 "FCC", "2.4G", "40M", "HT", "2T", "06", "34",
3667 "ETSI", "2.4G", "40M", "HT", "2T", "06", "30",
3668 "MKK", "2.4G", "40M", "HT", "2T", "06", "30",
3669 "FCC", "2.4G", "40M", "HT", "2T", "07", "34",
3670 "ETSI", "2.4G", "40M", "HT", "2T", "07", "30",
3671 "MKK", "2.4G", "40M", "HT", "2T", "07", "30",
3672 "FCC", "2.4G", "40M", "HT", "2T", "08", "34",
3673 "ETSI", "2.4G", "40M", "HT", "2T", "08", "30",
3674 "MKK", "2.4G", "40M", "HT", "2T", "08", "30",
3675 "FCC", "2.4G", "40M", "HT", "2T", "09", "34",
3676 "ETSI", "2.4G", "40M", "HT", "2T", "09", "30",
3677 "MKK", "2.4G", "40M", "HT", "2T", "09", "30",
3678 "FCC", "2.4G", "40M", "HT", "2T", "10", "34",
3679 "ETSI", "2.4G", "40M", "HT", "2T", "10", "30",
3680 "MKK", "2.4G", "40M", "HT", "2T", "10", "30",
3681 "FCC", "2.4G", "40M", "HT", "2T", "11", "30",
3682 "ETSI", "2.4G", "40M", "HT", "2T", "11", "30",
3683 "MKK", "2.4G", "40M", "HT", "2T", "11", "30",
3684 "FCC", "2.4G", "40M", "HT", "2T", "12", "63",
3685 "ETSI", "2.4G", "40M", "HT", "2T", "12", "32",
3686 "MKK", "2.4G", "40M", "HT", "2T", "12", "32",
3687 "FCC", "2.4G", "40M", "HT", "2T", "13", "63",
3688 "ETSI", "2.4G", "40M", "HT", "2T", "13", "32",
3689 "MKK", "2.4G", "40M", "HT", "2T", "13", "32",
3690 "FCC", "2.4G", "40M", "HT", "2T", "14", "63",
3691 "ETSI", "2.4G", "40M", "HT", "2T", "14", "63",
3692 "MKK", "2.4G", "40M", "HT", "2T", "14", "63",
3693 "FCC", "5G", "20M", "OFDM", "1T", "36", "30",
3694 "ETSI", "5G", "20M", "OFDM", "1T", "36", "32",
3695 "MKK", "5G", "20M", "OFDM", "1T", "36", "32",
3696 "FCC", "5G", "20M", "OFDM", "1T", "40", "30",
3697 "ETSI", "5G", "20M", "OFDM", "1T", "40", "32",
3698 "MKK", "5G", "20M", "OFDM", "1T", "40", "32",
3699 "FCC", "5G", "20M", "OFDM", "1T", "44", "30",
3700 "ETSI", "5G", "20M", "OFDM", "1T", "44", "32",
3701 "MKK", "5G", "20M", "OFDM", "1T", "44", "32",
3702 "FCC", "5G", "20M", "OFDM", "1T", "48", "30",
3703 "ETSI", "5G", "20M", "OFDM", "1T", "48", "32",
3704 "MKK", "5G", "20M", "OFDM", "1T", "48", "32",
3705 "FCC", "5G", "20M", "OFDM", "1T", "52", "36",
3706 "ETSI", "5G", "20M", "OFDM", "1T", "52", "32",
3707 "MKK", "5G", "20M", "OFDM", "1T", "52", "32",
3708 "FCC", "5G", "20M", "OFDM", "1T", "56", "34",
3709 "ETSI", "5G", "20M", "OFDM", "1T", "56", "32",
3710 "MKK", "5G", "20M", "OFDM", "1T", "56", "32",
3711 "FCC", "5G", "20M", "OFDM", "1T", "60", "32",
3712 "ETSI", "5G", "20M", "OFDM", "1T", "60", "32",
3713 "MKK", "5G", "20M", "OFDM", "1T", "60", "32",
3714 "FCC", "5G", "20M", "OFDM", "1T", "64", "28",
3715 "ETSI", "5G", "20M", "OFDM", "1T", "64", "32",
3716 "MKK", "5G", "20M", "OFDM", "1T", "64", "32",
3717 "FCC", "5G", "20M", "OFDM", "1T", "100", "30",
3718 "ETSI", "5G", "20M", "OFDM", "1T", "100", "32",
3719 "MKK", "5G", "20M", "OFDM", "1T", "100", "32",
3720 "FCC", "5G", "20M", "OFDM", "1T", "114", "30",
3721 "ETSI", "5G", "20M", "OFDM", "1T", "114", "32",
3722 "MKK", "5G", "20M", "OFDM", "1T", "114", "32",
3723 "FCC", "5G", "20M", "OFDM", "1T", "108", "32",
3724 "ETSI", "5G", "20M", "OFDM", "1T", "108", "32",
3725 "MKK", "5G", "20M", "OFDM", "1T", "108", "32",
3726 "FCC", "5G", "20M", "OFDM", "1T", "112", "34",
3727 "ETSI", "5G", "20M", "OFDM", "1T", "112", "32",
3728 "MKK", "5G", "20M", "OFDM", "1T", "112", "32",
3729 "FCC", "5G", "20M", "OFDM", "1T", "116", "34",
3730 "ETSI", "5G", "20M", "OFDM", "1T", "116", "32",
3731 "MKK", "5G", "20M", "OFDM", "1T", "116", "32",
3732 "FCC", "5G", "20M", "OFDM", "1T", "120", "36",
3733 "ETSI", "5G", "20M", "OFDM", "1T", "120", "32",
3734 "MKK", "5G", "20M", "OFDM", "1T", "120", "32",
3735 "FCC", "5G", "20M", "OFDM", "1T", "124", "34",
3736 "ETSI", "5G", "20M", "OFDM", "1T", "124", "32",
3737 "MKK", "5G", "20M", "OFDM", "1T", "124", "32",
3738 "FCC", "5G", "20M", "OFDM", "1T", "128", "32",
3739 "ETSI", "5G", "20M", "OFDM", "1T", "128", "32",
3740 "MKK", "5G", "20M", "OFDM", "1T", "128", "32",
3741 "FCC", "5G", "20M", "OFDM", "1T", "132", "30",
3742 "ETSI", "5G", "20M", "OFDM", "1T", "132", "32",
3743 "MKK", "5G", "20M", "OFDM", "1T", "132", "32",
3744 "FCC", "5G", "20M", "OFDM", "1T", "136", "30",
3745 "ETSI", "5G", "20M", "OFDM", "1T", "136", "32",
3746 "MKK", "5G", "20M", "OFDM", "1T", "136", "32",
3747 "FCC", "5G", "20M", "OFDM", "1T", "140", "28",
3748 "ETSI", "5G", "20M", "OFDM", "1T", "140", "32",
3749 "MKK", "5G", "20M", "OFDM", "1T", "140", "32",
3750 "FCC", "5G", "20M", "OFDM", "1T", "149", "36",
3751 "ETSI", "5G", "20M", "OFDM", "1T", "149", "32",
3752 "MKK", "5G", "20M", "OFDM", "1T", "149", "63",
3753 "FCC", "5G", "20M", "OFDM", "1T", "153", "36",
3754 "ETSI", "5G", "20M", "OFDM", "1T", "153", "32",
3755 "MKK", "5G", "20M", "OFDM", "1T", "153", "63",
3756 "FCC", "5G", "20M", "OFDM", "1T", "157", "36",
3757 "ETSI", "5G", "20M", "OFDM", "1T", "157", "32",
3758 "MKK", "5G", "20M", "OFDM", "1T", "157", "63",
3759 "FCC", "5G", "20M", "OFDM", "1T", "161", "36",
3760 "ETSI", "5G", "20M", "OFDM", "1T", "161", "32",
3761 "MKK", "5G", "20M", "OFDM", "1T", "161", "63",
3762 "FCC", "5G", "20M", "OFDM", "1T", "165", "36",
3763 "ETSI", "5G", "20M", "OFDM", "1T", "165", "32",
3764 "MKK", "5G", "20M", "OFDM", "1T", "165", "63",
3765 "FCC", "5G", "20M", "HT", "1T", "36", "30",
3766 "ETSI", "5G", "20M", "HT", "1T", "36", "32",
3767 "MKK", "5G", "20M", "HT", "1T", "36", "32",
3768 "FCC", "5G", "20M", "HT", "1T", "40", "30",
3769 "ETSI", "5G", "20M", "HT", "1T", "40", "32",
3770 "MKK", "5G", "20M", "HT", "1T", "40", "32",
3771 "FCC", "5G", "20M", "HT", "1T", "44", "30",
3772 "ETSI", "5G", "20M", "HT", "1T", "44", "32",
3773 "MKK", "5G", "20M", "HT", "1T", "44", "32",
3774 "FCC", "5G", "20M", "HT", "1T", "48", "30",
3775 "ETSI", "5G", "20M", "HT", "1T", "48", "32",
3776 "MKK", "5G", "20M", "HT", "1T", "48", "32",
3777 "FCC", "5G", "20M", "HT", "1T", "52", "36",
3778 "ETSI", "5G", "20M", "HT", "1T", "52", "32",
3779 "MKK", "5G", "20M", "HT", "1T", "52", "32",
3780 "FCC", "5G", "20M", "HT", "1T", "56", "34",
3781 "ETSI", "5G", "20M", "HT", "1T", "56", "32",
3782 "MKK", "5G", "20M", "HT", "1T", "56", "32",
3783 "FCC", "5G", "20M", "HT", "1T", "60", "32",
3784 "ETSI", "5G", "20M", "HT", "1T", "60", "32",
3785 "MKK", "5G", "20M", "HT", "1T", "60", "32",
3786 "FCC", "5G", "20M", "HT", "1T", "64", "28",
3787 "ETSI", "5G", "20M", "HT", "1T", "64", "32",
3788 "MKK", "5G", "20M", "HT", "1T", "64", "32",
3789 "FCC", "5G", "20M", "HT", "1T", "100", "30",
3790 "ETSI", "5G", "20M", "HT", "1T", "100", "32",
3791 "MKK", "5G", "20M", "HT", "1T", "100", "32",
3792 "FCC", "5G", "20M", "HT", "1T", "114", "30",
3793 "ETSI", "5G", "20M", "HT", "1T", "114", "32",
3794 "MKK", "5G", "20M", "HT", "1T", "114", "32",
3795 "FCC", "5G", "20M", "HT", "1T", "108", "32",
3796 "ETSI", "5G", "20M", "HT", "1T", "108", "32",
3797 "MKK", "5G", "20M", "HT", "1T", "108", "32",
3798 "FCC", "5G", "20M", "HT", "1T", "112", "34",
3799 "ETSI", "5G", "20M", "HT", "1T", "112", "32",
3800 "MKK", "5G", "20M", "HT", "1T", "112", "32",
3801 "FCC", "5G", "20M", "HT", "1T", "116", "34",
3802 "ETSI", "5G", "20M", "HT", "1T", "116", "32",
3803 "MKK", "5G", "20M", "HT", "1T", "116", "32",
3804 "FCC", "5G", "20M", "HT", "1T", "120", "36",
3805 "ETSI", "5G", "20M", "HT", "1T", "120", "32",
3806 "MKK", "5G", "20M", "HT", "1T", "120", "32",
3807 "FCC", "5G", "20M", "HT", "1T", "124", "34",
3808 "ETSI", "5G", "20M", "HT", "1T", "124", "32",
3809 "MKK", "5G", "20M", "HT", "1T", "124", "32",
3810 "FCC", "5G", "20M", "HT", "1T", "128", "32",
3811 "ETSI", "5G", "20M", "HT", "1T", "128", "32",
3812 "MKK", "5G", "20M", "HT", "1T", "128", "32",
3813 "FCC", "5G", "20M", "HT", "1T", "132", "30",
3814 "ETSI", "5G", "20M", "HT", "1T", "132", "32",
3815 "MKK", "5G", "20M", "HT", "1T", "132", "32",
3816 "FCC", "5G", "20M", "HT", "1T", "136", "30",
3817 "ETSI", "5G", "20M", "HT", "1T", "136", "32",
3818 "MKK", "5G", "20M", "HT", "1T", "136", "32",
3819 "FCC", "5G", "20M", "HT", "1T", "140", "28",
3820 "ETSI", "5G", "20M", "HT", "1T", "140", "32",
3821 "MKK", "5G", "20M", "HT", "1T", "140", "32",
3822 "FCC", "5G", "20M", "HT", "1T", "149", "36",
3823 "ETSI", "5G", "20M", "HT", "1T", "149", "32",
3824 "MKK", "5G", "20M", "HT", "1T", "149", "63",
3825 "FCC", "5G", "20M", "HT", "1T", "153", "36",
3826 "ETSI", "5G", "20M", "HT", "1T", "153", "32",
3827 "MKK", "5G", "20M", "HT", "1T", "153", "63",
3828 "FCC", "5G", "20M", "HT", "1T", "157", "36",
3829 "ETSI", "5G", "20M", "HT", "1T", "157", "32",
3830 "MKK", "5G", "20M", "HT", "1T", "157", "63",
3831 "FCC", "5G", "20M", "HT", "1T", "161", "36",
3832 "ETSI", "5G", "20M", "HT", "1T", "161", "32",
3833 "MKK", "5G", "20M", "HT", "1T", "161", "63",
3834 "FCC", "5G", "20M", "HT", "1T", "165", "36",
3835 "ETSI", "5G", "20M", "HT", "1T", "165", "32",
3836 "MKK", "5G", "20M", "HT", "1T", "165", "63",
3837 "FCC", "5G", "20M", "HT", "2T", "36", "28",
3838 "ETSI", "5G", "20M", "HT", "2T", "36", "30",
3839 "MKK", "5G", "20M", "HT", "2T", "36", "30",
3840 "FCC", "5G", "20M", "HT", "2T", "40", "28",
3841 "ETSI", "5G", "20M", "HT", "2T", "40", "30",
3842 "MKK", "5G", "20M", "HT", "2T", "40", "30",
3843 "FCC", "5G", "20M", "HT", "2T", "44", "28",
3844 "ETSI", "5G", "20M", "HT", "2T", "44", "30",
3845 "MKK", "5G", "20M", "HT", "2T", "44", "30",
3846 "FCC", "5G", "20M", "HT", "2T", "48", "28",
3847 "ETSI", "5G", "20M", "HT", "2T", "48", "30",
3848 "MKK", "5G", "20M", "HT", "2T", "48", "30",
3849 "FCC", "5G", "20M", "HT", "2T", "52", "34",
3850 "ETSI", "5G", "20M", "HT", "2T", "52", "30",
3851 "MKK", "5G", "20M", "HT", "2T", "52", "30",
3852 "FCC", "5G", "20M", "HT", "2T", "56", "32",
3853 "ETSI", "5G", "20M", "HT", "2T", "56", "30",
3854 "MKK", "5G", "20M", "HT", "2T", "56", "30",
3855 "FCC", "5G", "20M", "HT", "2T", "60", "30",
3856 "ETSI", "5G", "20M", "HT", "2T", "60", "30",
3857 "MKK", "5G", "20M", "HT", "2T", "60", "30",
3858 "FCC", "5G", "20M", "HT", "2T", "64", "26",
3859 "ETSI", "5G", "20M", "HT", "2T", "64", "30",
3860 "MKK", "5G", "20M", "HT", "2T", "64", "30",
3861 "FCC", "5G", "20M", "HT", "2T", "100", "28",
3862 "ETSI", "5G", "20M", "HT", "2T", "100", "30",
3863 "MKK", "5G", "20M", "HT", "2T", "100", "30",
3864 "FCC", "5G", "20M", "HT", "2T", "114", "28",
3865 "ETSI", "5G", "20M", "HT", "2T", "114", "30",
3866 "MKK", "5G", "20M", "HT", "2T", "114", "30",
3867 "FCC", "5G", "20M", "HT", "2T", "108", "30",
3868 "ETSI", "5G", "20M", "HT", "2T", "108", "30",
3869 "MKK", "5G", "20M", "HT", "2T", "108", "30",
3870 "FCC", "5G", "20M", "HT", "2T", "112", "32",
3871 "ETSI", "5G", "20M", "HT", "2T", "112", "30",
3872 "MKK", "5G", "20M", "HT", "2T", "112", "30",
3873 "FCC", "5G", "20M", "HT", "2T", "116", "32",
3874 "ETSI", "5G", "20M", "HT", "2T", "116", "30",
3875 "MKK", "5G", "20M", "HT", "2T", "116", "30",
3876 "FCC", "5G", "20M", "HT", "2T", "120", "34",
3877 "ETSI", "5G", "20M", "HT", "2T", "120", "30",
3878 "MKK", "5G", "20M", "HT", "2T", "120", "30",
3879 "FCC", "5G", "20M", "HT", "2T", "124", "32",
3880 "ETSI", "5G", "20M", "HT", "2T", "124", "30",
3881 "MKK", "5G", "20M", "HT", "2T", "124", "30",
3882 "FCC", "5G", "20M", "HT", "2T", "128", "30",
3883 "ETSI", "5G", "20M", "HT", "2T", "128", "30",
3884 "MKK", "5G", "20M", "HT", "2T", "128", "30",
3885 "FCC", "5G", "20M", "HT", "2T", "132", "28",
3886 "ETSI", "5G", "20M", "HT", "2T", "132", "30",
3887 "MKK", "5G", "20M", "HT", "2T", "132", "30",
3888 "FCC", "5G", "20M", "HT", "2T", "136", "28",
3889 "ETSI", "5G", "20M", "HT", "2T", "136", "30",
3890 "MKK", "5G", "20M", "HT", "2T", "136", "30",
3891 "FCC", "5G", "20M", "HT", "2T", "140", "26",
3892 "ETSI", "5G", "20M", "HT", "2T", "140", "30",
3893 "MKK", "5G", "20M", "HT", "2T", "140", "30",
3894 "FCC", "5G", "20M", "HT", "2T", "149", "34",
3895 "ETSI", "5G", "20M", "HT", "2T", "149", "30",
3896 "MKK", "5G", "20M", "HT", "2T", "149", "63",
3897 "FCC", "5G", "20M", "HT", "2T", "153", "34",
3898 "ETSI", "5G", "20M", "HT", "2T", "153", "30",
3899 "MKK", "5G", "20M", "HT", "2T", "153", "63",
3900 "FCC", "5G", "20M", "HT", "2T", "157", "34",
3901 "ETSI", "5G", "20M", "HT", "2T", "157", "30",
3902 "MKK", "5G", "20M", "HT", "2T", "157", "63",
3903 "FCC", "5G", "20M", "HT", "2T", "161", "34",
3904 "ETSI", "5G", "20M", "HT", "2T", "161", "30",
3905 "MKK", "5G", "20M", "HT", "2T", "161", "63",
3906 "FCC", "5G", "20M", "HT", "2T", "165", "34",
3907 "ETSI", "5G", "20M", "HT", "2T", "165", "30",
3908 "MKK", "5G", "20M", "HT", "2T", "165", "63",
3909 "FCC", "5G", "40M", "HT", "1T", "38", "30",
3910 "ETSI", "5G", "40M", "HT", "1T", "38", "32",
3911 "MKK", "5G", "40M", "HT", "1T", "38", "32",
3912 "FCC", "5G", "40M", "HT", "1T", "46", "30",
3913 "ETSI", "5G", "40M", "HT", "1T", "46", "32",
3914 "MKK", "5G", "40M", "HT", "1T", "46", "32",
3915 "FCC", "5G", "40M", "HT", "1T", "54", "32",
3916 "ETSI", "5G", "40M", "HT", "1T", "54", "32",
3917 "MKK", "5G", "40M", "HT", "1T", "54", "32",
3918 "FCC", "5G", "40M", "HT", "1T", "62", "32",
3919 "ETSI", "5G", "40M", "HT", "1T", "62", "32",
3920 "MKK", "5G", "40M", "HT", "1T", "62", "32",
3921 "FCC", "5G", "40M", "HT", "1T", "102", "28",
3922 "ETSI", "5G", "40M", "HT", "1T", "102", "32",
3923 "MKK", "5G", "40M", "HT", "1T", "102", "32",
3924 "FCC", "5G", "40M", "HT", "1T", "110", "32",
3925 "ETSI", "5G", "40M", "HT", "1T", "110", "32",
3926 "MKK", "5G", "40M", "HT", "1T", "110", "32",
3927 "FCC", "5G", "40M", "HT", "1T", "118", "36",
3928 "ETSI", "5G", "40M", "HT", "1T", "118", "32",
3929 "MKK", "5G", "40M", "HT", "1T", "118", "32",
3930 "FCC", "5G", "40M", "HT", "1T", "126", "34",
3931 "ETSI", "5G", "40M", "HT", "1T", "126", "32",
3932 "MKK", "5G", "40M", "HT", "1T", "126", "32",
3933 "FCC", "5G", "40M", "HT", "1T", "134", "32",
3934 "ETSI", "5G", "40M", "HT", "1T", "134", "32",
3935 "MKK", "5G", "40M", "HT", "1T", "134", "32",
3936 "FCC", "5G", "40M", "HT", "1T", "151", "36",
3937 "ETSI", "5G", "40M", "HT", "1T", "151", "32",
3938 "MKK", "5G", "40M", "HT", "1T", "151", "63",
3939 "FCC", "5G", "40M", "HT", "1T", "159", "36",
3940 "ETSI", "5G", "40M", "HT", "1T", "159", "32",
3941 "MKK", "5G", "40M", "HT", "1T", "159", "63",
3942 "FCC", "5G", "40M", "HT", "2T", "38", "28",
3943 "ETSI", "5G", "40M", "HT", "2T", "38", "30",
3944 "MKK", "5G", "40M", "HT", "2T", "38", "30",
3945 "FCC", "5G", "40M", "HT", "2T", "46", "28",
3946 "ETSI", "5G", "40M", "HT", "2T", "46", "30",
3947 "MKK", "5G", "40M", "HT", "2T", "46", "30",
3948 "FCC", "5G", "40M", "HT", "2T", "54", "30",
3949 "ETSI", "5G", "40M", "HT", "2T", "54", "30",
3950 "MKK", "5G", "40M", "HT", "2T", "54", "30",
3951 "FCC", "5G", "40M", "HT", "2T", "62", "30",
3952 "ETSI", "5G", "40M", "HT", "2T", "62", "30",
3953 "MKK", "5G", "40M", "HT", "2T", "62", "30",
3954 "FCC", "5G", "40M", "HT", "2T", "102", "26",
3955 "ETSI", "5G", "40M", "HT", "2T", "102", "30",
3956 "MKK", "5G", "40M", "HT", "2T", "102", "30",
3957 "FCC", "5G", "40M", "HT", "2T", "110", "30",
3958 "ETSI", "5G", "40M", "HT", "2T", "110", "30",
3959 "MKK", "5G", "40M", "HT", "2T", "110", "30",
3960 "FCC", "5G", "40M", "HT", "2T", "118", "34",
3961 "ETSI", "5G", "40M", "HT", "2T", "118", "30",
3962 "MKK", "5G", "40M", "HT", "2T", "118", "30",
3963 "FCC", "5G", "40M", "HT", "2T", "126", "32",
3964 "ETSI", "5G", "40M", "HT", "2T", "126", "30",
3965 "MKK", "5G", "40M", "HT", "2T", "126", "30",
3966 "FCC", "5G", "40M", "HT", "2T", "134", "30",
3967 "ETSI", "5G", "40M", "HT", "2T", "134", "30",
3968 "MKK", "5G", "40M", "HT", "2T", "134", "30",
3969 "FCC", "5G", "40M", "HT", "2T", "151", "34",
3970 "ETSI", "5G", "40M", "HT", "2T", "151", "30",
3971 "MKK", "5G", "40M", "HT", "2T", "151", "63",
3972 "FCC", "5G", "40M", "HT", "2T", "159", "34",
3973 "ETSI", "5G", "40M", "HT", "2T", "159", "30",
3974 "MKK", "5G", "40M", "HT", "2T", "159", "63",
3975 "FCC", "5G", "80M", "VHT", "1T", "42", "30",
3976 "ETSI", "5G", "80M", "VHT", "1T", "42", "32",
3977 "MKK", "5G", "80M", "VHT", "1T", "42", "32",
3978 "FCC", "5G", "80M", "VHT", "1T", "58", "28",
3979 "ETSI", "5G", "80M", "VHT", "1T", "58", "32",
3980 "MKK", "5G", "80M", "VHT", "1T", "58", "32",
3981 "FCC", "5G", "80M", "VHT", "1T", "106", "30",
3982 "ETSI", "5G", "80M", "VHT", "1T", "106", "32",
3983 "MKK", "5G", "80M", "VHT", "1T", "106", "32",
3984 "FCC", "5G", "80M", "VHT", "1T", "122", "34",
3985 "ETSI", "5G", "80M", "VHT", "1T", "122", "32",
3986 "MKK", "5G", "80M", "VHT", "1T", "122", "32",
3987 "FCC", "5G", "80M", "VHT", "1T", "155", "36",
3988 "ETSI", "5G", "80M", "VHT", "1T", "155", "32",
3989 "MKK", "5G", "80M", "VHT", "1T", "155", "63",
3990 "FCC", "5G", "80M", "VHT", "2T", "42", "28",
3991 "ETSI", "5G", "80M", "VHT", "2T", "42", "30",
3992 "MKK", "5G", "80M", "VHT", "2T", "42", "30",
3993 "FCC", "5G", "80M", "VHT", "2T", "58", "26",
3994 "ETSI", "5G", "80M", "VHT", "2T", "58", "30",
3995 "MKK", "5G", "80M", "VHT", "2T", "58", "30",
3996 "FCC", "5G", "80M", "VHT", "2T", "106", "28",
3997 "ETSI", "5G", "80M", "VHT", "2T", "106", "30",
3998 "MKK", "5G", "80M", "VHT", "2T", "106", "30",
3999 "FCC", "5G", "80M", "VHT", "2T", "122", "32",
4000 "ETSI", "5G", "80M", "VHT", "2T", "122", "30",
4001 "MKK", "5G", "80M", "VHT", "2T", "122", "30",
4002 "FCC", "5G", "80M", "VHT", "2T", "155", "34",
4003 "ETSI", "5G", "80M", "VHT", "2T", "155", "30",
4004 "MKK", "5G", "80M", "VHT", "2T", "155", "63"
4005};
4006
4007u8 *RTL8821AE_TXPWR_LMT[] = {
4008 "FCC", "2.4G", "20M", "CCK", "1T", "01", "32",
4009 "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
4010 "MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
4011 "FCC", "2.4G", "20M", "CCK", "1T", "02", "32",
4012 "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
4013 "MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
4014 "FCC", "2.4G", "20M", "CCK", "1T", "03", "36",
4015 "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
4016 "MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
4017 "FCC", "2.4G", "20M", "CCK", "1T", "04", "36",
4018 "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
4019 "MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
4020 "FCC", "2.4G", "20M", "CCK", "1T", "05", "36",
4021 "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32",
4022 "MKK", "2.4G", "20M", "CCK", "1T", "05", "32",
4023 "FCC", "2.4G", "20M", "CCK", "1T", "06", "36",
4024 "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32",
4025 "MKK", "2.4G", "20M", "CCK", "1T", "06", "32",
4026 "FCC", "2.4G", "20M", "CCK", "1T", "07", "36",
4027 "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32",
4028 "MKK", "2.4G", "20M", "CCK", "1T", "07", "32",
4029 "FCC", "2.4G", "20M", "CCK", "1T", "08", "36",
4030 "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32",
4031 "MKK", "2.4G", "20M", "CCK", "1T", "08", "32",
4032 "FCC", "2.4G", "20M", "CCK", "1T", "09", "32",
4033 "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32",
4034 "MKK", "2.4G", "20M", "CCK", "1T", "09", "32",
4035 "FCC", "2.4G", "20M", "CCK", "1T", "10", "32",
4036 "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32",
4037 "MKK", "2.4G", "20M", "CCK", "1T", "10", "32",
4038 "FCC", "2.4G", "20M", "CCK", "1T", "11", "32",
4039 "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32",
4040 "MKK", "2.4G", "20M", "CCK", "1T", "11", "32",
4041 "FCC", "2.4G", "20M", "CCK", "1T", "12", "63",
4042 "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32",
4043 "MKK", "2.4G", "20M", "CCK", "1T", "12", "32",
4044 "FCC", "2.4G", "20M", "CCK", "1T", "13", "63",
4045 "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32",
4046 "MKK", "2.4G", "20M", "CCK", "1T", "13", "32",
4047 "FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
4048 "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
4049 "MKK", "2.4G", "20M", "CCK", "1T", "14", "32",
4050 "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30",
4051 "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32",
4052 "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32",
4053 "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30",
4054 "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32",
4055 "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32",
4056 "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32",
4057 "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32",
4058 "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32",
4059 "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32",
4060 "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32",
4061 "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32",
4062 "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32",
4063 "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32",
4064 "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32",
4065 "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32",
4066 "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32",
4067 "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32",
4068 "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32",
4069 "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32",
4070 "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32",
4071 "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32",
4072 "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32",
4073 "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32",
4074 "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30",
4075 "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32",
4076 "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32",
4077 "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30",
4078 "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32",
4079 "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32",
4080 "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30",
4081 "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32",
4082 "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32",
4083 "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63",
4084 "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32",
4085 "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32",
4086 "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63",
4087 "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32",
4088 "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32",
4089 "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
4090 "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
4091 "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
4092 "FCC", "2.4G", "20M", "HT", "1T", "01", "26",
4093 "ETSI", "2.4G", "20M", "HT", "1T", "01", "32",
4094 "MKK", "2.4G", "20M", "HT", "1T", "01", "32",
4095 "FCC", "2.4G", "20M", "HT", "1T", "02", "26",
4096 "ETSI", "2.4G", "20M", "HT", "1T", "02", "32",
4097 "MKK", "2.4G", "20M", "HT", "1T", "02", "32",
4098 "FCC", "2.4G", "20M", "HT", "1T", "03", "32",
4099 "ETSI", "2.4G", "20M", "HT", "1T", "03", "32",
4100 "MKK", "2.4G", "20M", "HT", "1T", "03", "32",
4101 "FCC", "2.4G", "20M", "HT", "1T", "04", "32",
4102 "ETSI", "2.4G", "20M", "HT", "1T", "04", "32",
4103 "MKK", "2.4G", "20M", "HT", "1T", "04", "32",
4104 "FCC", "2.4G", "20M", "HT", "1T", "05", "32",
4105 "ETSI", "2.4G", "20M", "HT", "1T", "05", "32",
4106 "MKK", "2.4G", "20M", "HT", "1T", "05", "32",
4107 "FCC", "2.4G", "20M", "HT", "1T", "06", "32",
4108 "ETSI", "2.4G", "20M", "HT", "1T", "06", "32",
4109 "MKK", "2.4G", "20M", "HT", "1T", "06", "32",
4110 "FCC", "2.4G", "20M", "HT", "1T", "07", "32",
4111 "ETSI", "2.4G", "20M", "HT", "1T", "07", "32",
4112 "MKK", "2.4G", "20M", "HT", "1T", "07", "32",
4113 "FCC", "2.4G", "20M", "HT", "1T", "08", "32",
4114 "ETSI", "2.4G", "20M", "HT", "1T", "08", "32",
4115 "MKK", "2.4G", "20M", "HT", "1T", "08", "32",
4116 "FCC", "2.4G", "20M", "HT", "1T", "09", "26",
4117 "ETSI", "2.4G", "20M", "HT", "1T", "09", "32",
4118 "MKK", "2.4G", "20M", "HT", "1T", "09", "32",
4119 "FCC", "2.4G", "20M", "HT", "1T", "10", "26",
4120 "ETSI", "2.4G", "20M", "HT", "1T", "10", "32",
4121 "MKK", "2.4G", "20M", "HT", "1T", "10", "32",
4122 "FCC", "2.4G", "20M", "HT", "1T", "11", "26",
4123 "ETSI", "2.4G", "20M", "HT", "1T", "11", "32",
4124 "MKK", "2.4G", "20M", "HT", "1T", "11", "32",
4125 "FCC", "2.4G", "20M", "HT", "1T", "12", "63",
4126 "ETSI", "2.4G", "20M", "HT", "1T", "12", "32",
4127 "MKK", "2.4G", "20M", "HT", "1T", "12", "32",
4128 "FCC", "2.4G", "20M", "HT", "1T", "13", "63",
4129 "ETSI", "2.4G", "20M", "HT", "1T", "13", "32",
4130 "MKK", "2.4G", "20M", "HT", "1T", "13", "32",
4131 "FCC", "2.4G", "20M", "HT", "1T", "14", "63",
4132 "ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
4133 "MKK", "2.4G", "20M", "HT", "1T", "14", "63",
4134 "FCC", "2.4G", "20M", "HT", "2T", "01", "30",
4135 "ETSI", "2.4G", "20M", "HT", "2T", "01", "32",
4136 "MKK", "2.4G", "20M", "HT", "2T", "01", "32",
4137 "FCC", "2.4G", "20M", "HT", "2T", "02", "32",
4138 "ETSI", "2.4G", "20M", "HT", "2T", "02", "32",
4139 "MKK", "2.4G", "20M", "HT", "2T", "02", "32",
4140 "FCC", "2.4G", "20M", "HT", "2T", "03", "32",
4141 "ETSI", "2.4G", "20M", "HT", "2T", "03", "32",
4142 "MKK", "2.4G", "20M", "HT", "2T", "03", "32",
4143 "FCC", "2.4G", "20M", "HT", "2T", "04", "32",
4144 "ETSI", "2.4G", "20M", "HT", "2T", "04", "32",
4145 "MKK", "2.4G", "20M", "HT", "2T", "04", "32",
4146 "FCC", "2.4G", "20M", "HT", "2T", "05", "32",
4147 "ETSI", "2.4G", "20M", "HT", "2T", "05", "32",
4148 "MKK", "2.4G", "20M", "HT", "2T", "05", "32",
4149 "FCC", "2.4G", "20M", "HT", "2T", "06", "32",
4150 "ETSI", "2.4G", "20M", "HT", "2T", "06", "32",
4151 "MKK", "2.4G", "20M", "HT", "2T", "06", "32",
4152 "FCC", "2.4G", "20M", "HT", "2T", "07", "32",
4153 "ETSI", "2.4G", "20M", "HT", "2T", "07", "32",
4154 "MKK", "2.4G", "20M", "HT", "2T", "07", "32",
4155 "FCC", "2.4G", "20M", "HT", "2T", "08", "32",
4156 "ETSI", "2.4G", "20M", "HT", "2T", "08", "32",
4157 "MKK", "2.4G", "20M", "HT", "2T", "08", "32",
4158 "FCC", "2.4G", "20M", "HT", "2T", "09", "32",
4159 "ETSI", "2.4G", "20M", "HT", "2T", "09", "32",
4160 "MKK", "2.4G", "20M", "HT", "2T", "09", "32",
4161 "FCC", "2.4G", "20M", "HT", "2T", "10", "32",
4162 "ETSI", "2.4G", "20M", "HT", "2T", "10", "32",
4163 "MKK", "2.4G", "20M", "HT", "2T", "10", "32",
4164 "FCC", "2.4G", "20M", "HT", "2T", "11", "30",
4165 "ETSI", "2.4G", "20M", "HT", "2T", "11", "32",
4166 "MKK", "2.4G", "20M", "HT", "2T", "11", "32",
4167 "FCC", "2.4G", "20M", "HT", "2T", "12", "63",
4168 "ETSI", "2.4G", "20M", "HT", "2T", "12", "32",
4169 "MKK", "2.4G", "20M", "HT", "2T", "12", "32",
4170 "FCC", "2.4G", "20M", "HT", "2T", "13", "63",
4171 "ETSI", "2.4G", "20M", "HT", "2T", "13", "32",
4172 "MKK", "2.4G", "20M", "HT", "2T", "13", "32",
4173 "FCC", "2.4G", "20M", "HT", "2T", "14", "63",
4174 "ETSI", "2.4G", "20M", "HT", "2T", "14", "63",
4175 "MKK", "2.4G", "20M", "HT", "2T", "14", "63",
4176 "FCC", "2.4G", "40M", "HT", "1T", "01", "63",
4177 "ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
4178 "MKK", "2.4G", "40M", "HT", "1T", "01", "63",
4179 "FCC", "2.4G", "40M", "HT", "1T", "02", "63",
4180 "ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
4181 "MKK", "2.4G", "40M", "HT", "1T", "02", "63",
4182 "FCC", "2.4G", "40M", "HT", "1T", "03", "26",
4183 "ETSI", "2.4G", "40M", "HT", "1T", "03", "32",
4184 "MKK", "2.4G", "40M", "HT", "1T", "03", "32",
4185 "FCC", "2.4G", "40M", "HT", "1T", "04", "26",
4186 "ETSI", "2.4G", "40M", "HT", "1T", "04", "32",
4187 "MKK", "2.4G", "40M", "HT", "1T", "04", "32",
4188 "FCC", "2.4G", "40M", "HT", "1T", "05", "26",
4189 "ETSI", "2.4G", "40M", "HT", "1T", "05", "32",
4190 "MKK", "2.4G", "40M", "HT", "1T", "05", "32",
4191 "FCC", "2.4G", "40M", "HT", "1T", "06", "32",
4192 "ETSI", "2.4G", "40M", "HT", "1T", "06", "32",
4193 "MKK", "2.4G", "40M", "HT", "1T", "06", "32",
4194 "FCC", "2.4G", "40M", "HT", "1T", "07", "32",
4195 "ETSI", "2.4G", "40M", "HT", "1T", "07", "32",
4196 "MKK", "2.4G", "40M", "HT", "1T", "07", "32",
4197 "FCC", "2.4G", "40M", "HT", "1T", "08", "32",
4198 "ETSI", "2.4G", "40M", "HT", "1T", "08", "32",
4199 "MKK", "2.4G", "40M", "HT", "1T", "08", "32",
4200 "FCC", "2.4G", "40M", "HT", "1T", "09", "26",
4201 "ETSI", "2.4G", "40M", "HT", "1T", "09", "32",
4202 "MKK", "2.4G", "40M", "HT", "1T", "09", "32",
4203 "FCC", "2.4G", "40M", "HT", "1T", "10", "26",
4204 "ETSI", "2.4G", "40M", "HT", "1T", "10", "32",
4205 "MKK", "2.4G", "40M", "HT", "1T", "10", "32",
4206 "FCC", "2.4G", "40M", "HT", "1T", "11", "26",
4207 "ETSI", "2.4G", "40M", "HT", "1T", "11", "32",
4208 "MKK", "2.4G", "40M", "HT", "1T", "11", "32",
4209 "FCC", "2.4G", "40M", "HT", "1T", "12", "63",
4210 "ETSI", "2.4G", "40M", "HT", "1T", "12", "32",
4211 "MKK", "2.4G", "40M", "HT", "1T", "12", "32",
4212 "FCC", "2.4G", "40M", "HT", "1T", "13", "63",
4213 "ETSI", "2.4G", "40M", "HT", "1T", "13", "32",
4214 "MKK", "2.4G", "40M", "HT", "1T", "13", "32",
4215 "FCC", "2.4G", "40M", "HT", "1T", "14", "63",
4216 "ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
4217 "MKK", "2.4G", "40M", "HT", "1T", "14", "63",
4218 "FCC", "2.4G", "40M", "HT", "2T", "01", "63",
4219 "ETSI", "2.4G", "40M", "HT", "2T", "01", "63",
4220 "MKK", "2.4G", "40M", "HT", "2T", "01", "63",
4221 "FCC", "2.4G", "40M", "HT", "2T", "02", "63",
4222 "ETSI", "2.4G", "40M", "HT", "2T", "02", "63",
4223 "MKK", "2.4G", "40M", "HT", "2T", "02", "63",
4224 "FCC", "2.4G", "40M", "HT", "2T", "03", "30",
4225 "ETSI", "2.4G", "40M", "HT", "2T", "03", "30",
4226 "MKK", "2.4G", "40M", "HT", "2T", "03", "30",
4227 "FCC", "2.4G", "40M", "HT", "2T", "04", "32",
4228 "ETSI", "2.4G", "40M", "HT", "2T", "04", "30",
4229 "MKK", "2.4G", "40M", "HT", "2T", "04", "30",
4230 "FCC", "2.4G", "40M", "HT", "2T", "05", "32",
4231 "ETSI", "2.4G", "40M", "HT", "2T", "05", "30",
4232 "MKK", "2.4G", "40M", "HT", "2T", "05", "30",
4233 "FCC", "2.4G", "40M", "HT", "2T", "06", "32",
4234 "ETSI", "2.4G", "40M", "HT", "2T", "06", "30",
4235 "MKK", "2.4G", "40M", "HT", "2T", "06", "30",
4236 "FCC", "2.4G", "40M", "HT", "2T", "07", "32",
4237 "ETSI", "2.4G", "40M", "HT", "2T", "07", "30",
4238 "MKK", "2.4G", "40M", "HT", "2T", "07", "30",
4239 "FCC", "2.4G", "40M", "HT", "2T", "08", "32",
4240 "ETSI", "2.4G", "40M", "HT", "2T", "08", "30",
4241 "MKK", "2.4G", "40M", "HT", "2T", "08", "30",
4242 "FCC", "2.4G", "40M", "HT", "2T", "09", "32",
4243 "ETSI", "2.4G", "40M", "HT", "2T", "09", "30",
4244 "MKK", "2.4G", "40M", "HT", "2T", "09", "30",
4245 "FCC", "2.4G", "40M", "HT", "2T", "10", "32",
4246 "ETSI", "2.4G", "40M", "HT", "2T", "10", "30",
4247 "MKK", "2.4G", "40M", "HT", "2T", "10", "30",
4248 "FCC", "2.4G", "40M", "HT", "2T", "11", "30",
4249 "ETSI", "2.4G", "40M", "HT", "2T", "11", "30",
4250 "MKK", "2.4G", "40M", "HT", "2T", "11", "30",
4251 "FCC", "2.4G", "40M", "HT", "2T", "12", "63",
4252 "ETSI", "2.4G", "40M", "HT", "2T", "12", "32",
4253 "MKK", "2.4G", "40M", "HT", "2T", "12", "32",
4254 "FCC", "2.4G", "40M", "HT", "2T", "13", "63",
4255 "ETSI", "2.4G", "40M", "HT", "2T", "13", "32",
4256 "MKK", "2.4G", "40M", "HT", "2T", "13", "32",
4257 "FCC", "2.4G", "40M", "HT", "2T", "14", "63",
4258 "ETSI", "2.4G", "40M", "HT", "2T", "14", "63",
4259 "MKK", "2.4G", "40M", "HT", "2T", "14", "63",
4260 "FCC", "5G", "20M", "OFDM", "1T", "36", "32",
4261 "ETSI", "5G", "20M", "OFDM", "1T", "36", "30",
4262 "MKK", "5G", "20M", "OFDM", "1T", "36", "30",
4263 "FCC", "5G", "20M", "OFDM", "1T", "40", "32",
4264 "ETSI", "5G", "20M", "OFDM", "1T", "40", "30",
4265 "MKK", "5G", "20M", "OFDM", "1T", "40", "30",
4266 "FCC", "5G", "20M", "OFDM", "1T", "44", "32",
4267 "ETSI", "5G", "20M", "OFDM", "1T", "44", "30",
4268 "MKK", "5G", "20M", "OFDM", "1T", "44", "30",
4269 "FCC", "5G", "20M", "OFDM", "1T", "48", "32",
4270 "ETSI", "5G", "20M", "OFDM", "1T", "48", "30",
4271 "MKK", "5G", "20M", "OFDM", "1T", "48", "30",
4272 "FCC", "5G", "20M", "OFDM", "1T", "52", "32",
4273 "ETSI", "5G", "20M", "OFDM", "1T", "52", "30",
4274 "MKK", "5G", "20M", "OFDM", "1T", "52", "30",
4275 "FCC", "5G", "20M", "OFDM", "1T", "56", "32",
4276 "ETSI", "5G", "20M", "OFDM", "1T", "56", "30",
4277 "MKK", "5G", "20M", "OFDM", "1T", "56", "30",
4278 "FCC", "5G", "20M", "OFDM", "1T", "60", "32",
4279 "ETSI", "5G", "20M", "OFDM", "1T", "60", "30",
4280 "MKK", "5G", "20M", "OFDM", "1T", "60", "30",
4281 "FCC", "5G", "20M", "OFDM", "1T", "64", "32",
4282 "ETSI", "5G", "20M", "OFDM", "1T", "64", "30",
4283 "MKK", "5G", "20M", "OFDM", "1T", "64", "30",
4284 "FCC", "5G", "20M", "OFDM", "1T", "100", "32",
4285 "ETSI", "5G", "20M", "OFDM", "1T", "100", "30",
4286 "MKK", "5G", "20M", "OFDM", "1T", "100", "30",
4287 "FCC", "5G", "20M", "OFDM", "1T", "114", "32",
4288 "ETSI", "5G", "20M", "OFDM", "1T", "114", "30",
4289 "MKK", "5G", "20M", "OFDM", "1T", "114", "30",
4290 "FCC", "5G", "20M", "OFDM", "1T", "108", "32",
4291 "ETSI", "5G", "20M", "OFDM", "1T", "108", "30",
4292 "MKK", "5G", "20M", "OFDM", "1T", "108", "30",
4293 "FCC", "5G", "20M", "OFDM", "1T", "112", "32",
4294 "ETSI", "5G", "20M", "OFDM", "1T", "112", "30",
4295 "MKK", "5G", "20M", "OFDM", "1T", "112", "30",
4296 "FCC", "5G", "20M", "OFDM", "1T", "116", "32",
4297 "ETSI", "5G", "20M", "OFDM", "1T", "116", "30",
4298 "MKK", "5G", "20M", "OFDM", "1T", "116", "30",
4299 "FCC", "5G", "20M", "OFDM", "1T", "120", "32",
4300 "ETSI", "5G", "20M", "OFDM", "1T", "120", "30",
4301 "MKK", "5G", "20M", "OFDM", "1T", "120", "30",
4302 "FCC", "5G", "20M", "OFDM", "1T", "124", "32",
4303 "ETSI", "5G", "20M", "OFDM", "1T", "124", "30",
4304 "MKK", "5G", "20M", "OFDM", "1T", "124", "30",
4305 "FCC", "5G", "20M", "OFDM", "1T", "128", "32",
4306 "ETSI", "5G", "20M", "OFDM", "1T", "128", "30",
4307 "MKK", "5G", "20M", "OFDM", "1T", "128", "30",
4308 "FCC", "5G", "20M", "OFDM", "1T", "132", "32",
4309 "ETSI", "5G", "20M", "OFDM", "1T", "132", "30",
4310 "MKK", "5G", "20M", "OFDM", "1T", "132", "30",
4311 "FCC", "5G", "20M", "OFDM", "1T", "136", "32",
4312 "ETSI", "5G", "20M", "OFDM", "1T", "136", "30",
4313 "MKK", "5G", "20M", "OFDM", "1T", "136", "30",
4314 "FCC", "5G", "20M", "OFDM", "1T", "140", "32",
4315 "ETSI", "5G", "20M", "OFDM", "1T", "140", "30",
4316 "MKK", "5G", "20M", "OFDM", "1T", "140", "30",
4317 "FCC", "5G", "20M", "OFDM", "1T", "149", "32",
4318 "ETSI", "5G", "20M", "OFDM", "1T", "149", "30",
4319 "MKK", "5G", "20M", "OFDM", "1T", "149", "63",
4320 "FCC", "5G", "20M", "OFDM", "1T", "153", "32",
4321 "ETSI", "5G", "20M", "OFDM", "1T", "153", "30",
4322 "MKK", "5G", "20M", "OFDM", "1T", "153", "63",
4323 "FCC", "5G", "20M", "OFDM", "1T", "157", "32",
4324 "ETSI", "5G", "20M", "OFDM", "1T", "157", "30",
4325 "MKK", "5G", "20M", "OFDM", "1T", "157", "63",
4326 "FCC", "5G", "20M", "OFDM", "1T", "161", "32",
4327 "ETSI", "5G", "20M", "OFDM", "1T", "161", "30",
4328 "MKK", "5G", "20M", "OFDM", "1T", "161", "63",
4329 "FCC", "5G", "20M", "OFDM", "1T", "165", "32",
4330 "ETSI", "5G", "20M", "OFDM", "1T", "165", "30",
4331 "MKK", "5G", "20M", "OFDM", "1T", "165", "63",
4332 "FCC", "5G", "20M", "HT", "1T", "36", "32",
4333 "ETSI", "5G", "20M", "HT", "1T", "36", "30",
4334 "MKK", "5G", "20M", "HT", "1T", "36", "30",
4335 "FCC", "5G", "20M", "HT", "1T", "40", "32",
4336 "ETSI", "5G", "20M", "HT", "1T", "40", "30",
4337 "MKK", "5G", "20M", "HT", "1T", "40", "30",
4338 "FCC", "5G", "20M", "HT", "1T", "44", "32",
4339 "ETSI", "5G", "20M", "HT", "1T", "44", "30",
4340 "MKK", "5G", "20M", "HT", "1T", "44", "30",
4341 "FCC", "5G", "20M", "HT", "1T", "48", "32",
4342 "ETSI", "5G", "20M", "HT", "1T", "48", "30",
4343 "MKK", "5G", "20M", "HT", "1T", "48", "30",
4344 "FCC", "5G", "20M", "HT", "1T", "52", "32",
4345 "ETSI", "5G", "20M", "HT", "1T", "52", "30",
4346 "MKK", "5G", "20M", "HT", "1T", "52", "30",
4347 "FCC", "5G", "20M", "HT", "1T", "56", "32",
4348 "ETSI", "5G", "20M", "HT", "1T", "56", "30",
4349 "MKK", "5G", "20M", "HT", "1T", "56", "30",
4350 "FCC", "5G", "20M", "HT", "1T", "60", "32",
4351 "ETSI", "5G", "20M", "HT", "1T", "60", "30",
4352 "MKK", "5G", "20M", "HT", "1T", "60", "30",
4353 "FCC", "5G", "20M", "HT", "1T", "64", "32",
4354 "ETSI", "5G", "20M", "HT", "1T", "64", "30",
4355 "MKK", "5G", "20M", "HT", "1T", "64", "30",
4356 "FCC", "5G", "20M", "HT", "1T", "100", "32",
4357 "ETSI", "5G", "20M", "HT", "1T", "100", "30",
4358 "MKK", "5G", "20M", "HT", "1T", "100", "30",
4359 "FCC", "5G", "20M", "HT", "1T", "114", "32",
4360 "ETSI", "5G", "20M", "HT", "1T", "114", "30",
4361 "MKK", "5G", "20M", "HT", "1T", "114", "30",
4362 "FCC", "5G", "20M", "HT", "1T", "108", "32",
4363 "ETSI", "5G", "20M", "HT", "1T", "108", "30",
4364 "MKK", "5G", "20M", "HT", "1T", "108", "30",
4365 "FCC", "5G", "20M", "HT", "1T", "112", "32",
4366 "ETSI", "5G", "20M", "HT", "1T", "112", "30",
4367 "MKK", "5G", "20M", "HT", "1T", "112", "30",
4368 "FCC", "5G", "20M", "HT", "1T", "116", "32",
4369 "ETSI", "5G", "20M", "HT", "1T", "116", "30",
4370 "MKK", "5G", "20M", "HT", "1T", "116", "30",
4371 "FCC", "5G", "20M", "HT", "1T", "120", "32",
4372 "ETSI", "5G", "20M", "HT", "1T", "120", "30",
4373 "MKK", "5G", "20M", "HT", "1T", "120", "30",
4374 "FCC", "5G", "20M", "HT", "1T", "124", "32",
4375 "ETSI", "5G", "20M", "HT", "1T", "124", "30",
4376 "MKK", "5G", "20M", "HT", "1T", "124", "30",
4377 "FCC", "5G", "20M", "HT", "1T", "128", "32",
4378 "ETSI", "5G", "20M", "HT", "1T", "128", "30",
4379 "MKK", "5G", "20M", "HT", "1T", "128", "30",
4380 "FCC", "5G", "20M", "HT", "1T", "132", "32",
4381 "ETSI", "5G", "20M", "HT", "1T", "132", "30",
4382 "MKK", "5G", "20M", "HT", "1T", "132", "30",
4383 "FCC", "5G", "20M", "HT", "1T", "136", "32",
4384 "ETSI", "5G", "20M", "HT", "1T", "136", "30",
4385 "MKK", "5G", "20M", "HT", "1T", "136", "30",
4386 "FCC", "5G", "20M", "HT", "1T", "140", "32",
4387 "ETSI", "5G", "20M", "HT", "1T", "140", "30",
4388 "MKK", "5G", "20M", "HT", "1T", "140", "30",
4389 "FCC", "5G", "20M", "HT", "1T", "149", "32",
4390 "ETSI", "5G", "20M", "HT", "1T", "149", "30",
4391 "MKK", "5G", "20M", "HT", "1T", "149", "63",
4392 "FCC", "5G", "20M", "HT", "1T", "153", "32",
4393 "ETSI", "5G", "20M", "HT", "1T", "153", "30",
4394 "MKK", "5G", "20M", "HT", "1T", "153", "63",
4395 "FCC", "5G", "20M", "HT", "1T", "157", "32",
4396 "ETSI", "5G", "20M", "HT", "1T", "157", "30",
4397 "MKK", "5G", "20M", "HT", "1T", "157", "63",
4398 "FCC", "5G", "20M", "HT", "1T", "161", "32",
4399 "ETSI", "5G", "20M", "HT", "1T", "161", "30",
4400 "MKK", "5G", "20M", "HT", "1T", "161", "63",
4401 "FCC", "5G", "20M", "HT", "1T", "165", "32",
4402 "ETSI", "5G", "20M", "HT", "1T", "165", "30",
4403 "MKK", "5G", "20M", "HT", "1T", "165", "63",
4404 "FCC", "5G", "20M", "HT", "2T", "36", "28",
4405 "ETSI", "5G", "20M", "HT", "2T", "36", "30",
4406 "MKK", "5G", "20M", "HT", "2T", "36", "30",
4407 "FCC", "5G", "20M", "HT", "2T", "40", "28",
4408 "ETSI", "5G", "20M", "HT", "2T", "40", "30",
4409 "MKK", "5G", "20M", "HT", "2T", "40", "30",
4410 "FCC", "5G", "20M", "HT", "2T", "44", "28",
4411 "ETSI", "5G", "20M", "HT", "2T", "44", "30",
4412 "MKK", "5G", "20M", "HT", "2T", "44", "30",
4413 "FCC", "5G", "20M", "HT", "2T", "48", "28",
4414 "ETSI", "5G", "20M", "HT", "2T", "48", "30",
4415 "MKK", "5G", "20M", "HT", "2T", "48", "30",
4416 "FCC", "5G", "20M", "HT", "2T", "52", "34",
4417 "ETSI", "5G", "20M", "HT", "2T", "52", "30",
4418 "MKK", "5G", "20M", "HT", "2T", "52", "30",
4419 "FCC", "5G", "20M", "HT", "2T", "56", "32",
4420 "ETSI", "5G", "20M", "HT", "2T", "56", "30",
4421 "MKK", "5G", "20M", "HT", "2T", "56", "30",
4422 "FCC", "5G", "20M", "HT", "2T", "60", "30",
4423 "ETSI", "5G", "20M", "HT", "2T", "60", "30",
4424 "MKK", "5G", "20M", "HT", "2T", "60", "30",
4425 "FCC", "5G", "20M", "HT", "2T", "64", "26",
4426 "ETSI", "5G", "20M", "HT", "2T", "64", "30",
4427 "MKK", "5G", "20M", "HT", "2T", "64", "30",
4428 "FCC", "5G", "20M", "HT", "2T", "100", "28",
4429 "ETSI", "5G", "20M", "HT", "2T", "100", "30",
4430 "MKK", "5G", "20M", "HT", "2T", "100", "30",
4431 "FCC", "5G", "20M", "HT", "2T", "114", "28",
4432 "ETSI", "5G", "20M", "HT", "2T", "114", "30",
4433 "MKK", "5G", "20M", "HT", "2T", "114", "30",
4434 "FCC", "5G", "20M", "HT", "2T", "108", "30",
4435 "ETSI", "5G", "20M", "HT", "2T", "108", "30",
4436 "MKK", "5G", "20M", "HT", "2T", "108", "30",
4437 "FCC", "5G", "20M", "HT", "2T", "112", "32",
4438 "ETSI", "5G", "20M", "HT", "2T", "112", "30",
4439 "MKK", "5G", "20M", "HT", "2T", "112", "30",
4440 "FCC", "5G", "20M", "HT", "2T", "116", "32",
4441 "ETSI", "5G", "20M", "HT", "2T", "116", "30",
4442 "MKK", "5G", "20M", "HT", "2T", "116", "30",
4443 "FCC", "5G", "20M", "HT", "2T", "120", "34",
4444 "ETSI", "5G", "20M", "HT", "2T", "120", "30",
4445 "MKK", "5G", "20M", "HT", "2T", "120", "30",
4446 "FCC", "5G", "20M", "HT", "2T", "124", "32",
4447 "ETSI", "5G", "20M", "HT", "2T", "124", "30",
4448 "MKK", "5G", "20M", "HT", "2T", "124", "30",
4449 "FCC", "5G", "20M", "HT", "2T", "128", "30",
4450 "ETSI", "5G", "20M", "HT", "2T", "128", "30",
4451 "MKK", "5G", "20M", "HT", "2T", "128", "30",
4452 "FCC", "5G", "20M", "HT", "2T", "132", "28",
4453 "ETSI", "5G", "20M", "HT", "2T", "132", "30",
4454 "MKK", "5G", "20M", "HT", "2T", "132", "30",
4455 "FCC", "5G", "20M", "HT", "2T", "136", "28",
4456 "ETSI", "5G", "20M", "HT", "2T", "136", "30",
4457 "MKK", "5G", "20M", "HT", "2T", "136", "30",
4458 "FCC", "5G", "20M", "HT", "2T", "140", "26",
4459 "ETSI", "5G", "20M", "HT", "2T", "140", "30",
4460 "MKK", "5G", "20M", "HT", "2T", "140", "30",
4461 "FCC", "5G", "20M", "HT", "2T", "149", "34",
4462 "ETSI", "5G", "20M", "HT", "2T", "149", "30",
4463 "MKK", "5G", "20M", "HT", "2T", "149", "63",
4464 "FCC", "5G", "20M", "HT", "2T", "153", "34",
4465 "ETSI", "5G", "20M", "HT", "2T", "153", "30",
4466 "MKK", "5G", "20M", "HT", "2T", "153", "63",
4467 "FCC", "5G", "20M", "HT", "2T", "157", "34",
4468 "ETSI", "5G", "20M", "HT", "2T", "157", "30",
4469 "MKK", "5G", "20M", "HT", "2T", "157", "63",
4470 "FCC", "5G", "20M", "HT", "2T", "161", "34",
4471 "ETSI", "5G", "20M", "HT", "2T", "161", "30",
4472 "MKK", "5G", "20M", "HT", "2T", "161", "63",
4473 "FCC", "5G", "20M", "HT", "2T", "165", "34",
4474 "ETSI", "5G", "20M", "HT", "2T", "165", "30",
4475 "MKK", "5G", "20M", "HT", "2T", "165", "63",
4476 "FCC", "5G", "40M", "HT", "1T", "38", "26",
4477 "ETSI", "5G", "40M", "HT", "1T", "38", "30",
4478 "MKK", "5G", "40M", "HT", "1T", "38", "30",
4479 "FCC", "5G", "40M", "HT", "1T", "46", "32",
4480 "ETSI", "5G", "40M", "HT", "1T", "46", "30",
4481 "MKK", "5G", "40M", "HT", "1T", "46", "30",
4482 "FCC", "5G", "40M", "HT", "1T", "54", "32",
4483 "ETSI", "5G", "40M", "HT", "1T", "54", "30",
4484 "MKK", "5G", "40M", "HT", "1T", "54", "30",
4485 "FCC", "5G", "40M", "HT", "1T", "62", "24",
4486 "ETSI", "5G", "40M", "HT", "1T", "62", "30",
4487 "MKK", "5G", "40M", "HT", "1T", "62", "30",
4488 "FCC", "5G", "40M", "HT", "1T", "102", "24",
4489 "ETSI", "5G", "40M", "HT", "1T", "102", "30",
4490 "MKK", "5G", "40M", "HT", "1T", "102", "30",
4491 "FCC", "5G", "40M", "HT", "1T", "110", "32",
4492 "ETSI", "5G", "40M", "HT", "1T", "110", "30",
4493 "MKK", "5G", "40M", "HT", "1T", "110", "30",
4494 "FCC", "5G", "40M", "HT", "1T", "118", "32",
4495 "ETSI", "5G", "40M", "HT", "1T", "118", "30",
4496 "MKK", "5G", "40M", "HT", "1T", "118", "30",
4497 "FCC", "5G", "40M", "HT", "1T", "126", "32",
4498 "ETSI", "5G", "40M", "HT", "1T", "126", "30",
4499 "MKK", "5G", "40M", "HT", "1T", "126", "30",
4500 "FCC", "5G", "40M", "HT", "1T", "134", "32",
4501 "ETSI", "5G", "40M", "HT", "1T", "134", "30",
4502 "MKK", "5G", "40M", "HT", "1T", "134", "30",
4503 "FCC", "5G", "40M", "HT", "1T", "151", "30",
4504 "ETSI", "5G", "40M", "HT", "1T", "151", "30",
4505 "MKK", "5G", "40M", "HT", "1T", "151", "63",
4506 "FCC", "5G", "40M", "HT", "1T", "159", "32",
4507 "ETSI", "5G", "40M", "HT", "1T", "159", "30",
4508 "MKK", "5G", "40M", "HT", "1T", "159", "63",
4509 "FCC", "5G", "40M", "HT", "2T", "38", "28",
4510 "ETSI", "5G", "40M", "HT", "2T", "38", "30",
4511 "MKK", "5G", "40M", "HT", "2T", "38", "30",
4512 "FCC", "5G", "40M", "HT", "2T", "46", "28",
4513 "ETSI", "5G", "40M", "HT", "2T", "46", "30",
4514 "MKK", "5G", "40M", "HT", "2T", "46", "30",
4515 "FCC", "5G", "40M", "HT", "2T", "54", "30",
4516 "ETSI", "5G", "40M", "HT", "2T", "54", "30",
4517 "MKK", "5G", "40M", "HT", "2T", "54", "30",
4518 "FCC", "5G", "40M", "HT", "2T", "62", "30",
4519 "ETSI", "5G", "40M", "HT", "2T", "62", "30",
4520 "MKK", "5G", "40M", "HT", "2T", "62", "30",
4521 "FCC", "5G", "40M", "HT", "2T", "102", "26",
4522 "ETSI", "5G", "40M", "HT", "2T", "102", "30",
4523 "MKK", "5G", "40M", "HT", "2T", "102", "30",
4524 "FCC", "5G", "40M", "HT", "2T", "110", "30",
4525 "ETSI", "5G", "40M", "HT", "2T", "110", "30",
4526 "MKK", "5G", "40M", "HT", "2T", "110", "30",
4527 "FCC", "5G", "40M", "HT", "2T", "118", "34",
4528 "ETSI", "5G", "40M", "HT", "2T", "118", "30",
4529 "MKK", "5G", "40M", "HT", "2T", "118", "30",
4530 "FCC", "5G", "40M", "HT", "2T", "126", "32",
4531 "ETSI", "5G", "40M", "HT", "2T", "126", "30",
4532 "MKK", "5G", "40M", "HT", "2T", "126", "30",
4533 "FCC", "5G", "40M", "HT", "2T", "134", "30",
4534 "ETSI", "5G", "40M", "HT", "2T", "134", "30",
4535 "MKK", "5G", "40M", "HT", "2T", "134", "30",
4536 "FCC", "5G", "40M", "HT", "2T", "151", "34",
4537 "ETSI", "5G", "40M", "HT", "2T", "151", "30",
4538 "MKK", "5G", "40M", "HT", "2T", "151", "63",
4539 "FCC", "5G", "40M", "HT", "2T", "159", "34",
4540 "ETSI", "5G", "40M", "HT", "2T", "159", "30",
4541 "MKK", "5G", "40M", "HT", "2T", "159", "63",
4542 "FCC", "5G", "80M", "VHT", "1T", "42", "22",
4543 "ETSI", "5G", "80M", "VHT", "1T", "42", "30",
4544 "MKK", "5G", "80M", "VHT", "1T", "42", "30",
4545 "FCC", "5G", "80M", "VHT", "1T", "58", "20",
4546 "ETSI", "5G", "80M", "VHT", "1T", "58", "30",
4547 "MKK", "5G", "80M", "VHT", "1T", "58", "30",
4548 "FCC", "5G", "80M", "VHT", "1T", "106", "20",
4549 "ETSI", "5G", "80M", "VHT", "1T", "106", "30",
4550 "MKK", "5G", "80M", "VHT", "1T", "106", "30",
4551 "FCC", "5G", "80M", "VHT", "1T", "122", "20",
4552 "ETSI", "5G", "80M", "VHT", "1T", "122", "30",
4553 "MKK", "5G", "80M", "VHT", "1T", "122", "30",
4554 "FCC", "5G", "80M", "VHT", "1T", "155", "28",
4555 "ETSI", "5G", "80M", "VHT", "1T", "155", "30",
4556 "MKK", "5G", "80M", "VHT", "1T", "155", "63",
4557 "FCC", "5G", "80M", "VHT", "2T", "42", "28",
4558 "ETSI", "5G", "80M", "VHT", "2T", "42", "30",
4559 "MKK", "5G", "80M", "VHT", "2T", "42", "30",
4560 "FCC", "5G", "80M", "VHT", "2T", "58", "26",
4561 "ETSI", "5G", "80M", "VHT", "2T", "58", "30",
4562 "MKK", "5G", "80M", "VHT", "2T", "58", "30",
4563 "FCC", "5G", "80M", "VHT", "2T", "106", "28",
4564 "ETSI", "5G", "80M", "VHT", "2T", "106", "30",
4565 "MKK", "5G", "80M", "VHT", "2T", "106", "30",
4566 "FCC", "5G", "80M", "VHT", "2T", "122", "32",
4567 "ETSI", "5G", "80M", "VHT", "2T", "122", "30",
4568 "MKK", "5G", "80M", "VHT", "2T", "122", "30",
4569 "FCC", "5G", "80M", "VHT", "2T", "155", "34",
4570 "ETSI", "5G", "80M", "VHT", "2T", "155", "30",
4571 "MKK", "5G", "80M", "VHT", "2T", "155", "63"
4572};
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/table.h b/drivers/net/wireless/rtlwifi/rtl8821ae/table.h
new file mode 100644
index 000000000000..24bcff6bc507
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/table.h
@@ -0,0 +1,60 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Created on 2010/ 5/18, 1:41
23 *
24 * Larry Finger <Larry.Finger@lwfinger.net>
25 *
26 *****************************************************************************/
27
28#ifndef __RTL8821AE_TABLE__H_
29#define __RTL8821AE_TABLE__H_
30
31#include <linux/types.h>
32#define RTL8821AEPHY_REG_1TARRAYLEN 344
33extern u32 RTL8821AE_PHY_REG_ARRAY[];
34#define RTL8812AEPHY_REG_1TARRAYLEN 490
35extern u32 RTL8812AE_PHY_REG_ARRAY[];
36#define RTL8821AEPHY_REG_ARRAY_PGLEN 90
37extern u32 RTL8821AE_PHY_REG_ARRAY_PG[];
38#define RTL8812AEPHY_REG_ARRAY_PGLEN 276
39extern u32 RTL8812AE_PHY_REG_ARRAY_PG[];
40/* #define RTL8723BE_RADIOA_1TARRAYLEN 206 */
41/* extern u8 *RTL8821AE_TXPWR_LMT_ARRAY[]; */
42#define RTL8812AE_RADIOA_1TARRAYLEN 1264
43extern u32 RTL8812AE_RADIOA_ARRAY[];
44#define RTL8812AE_RADIOB_1TARRAYLEN 1240
45extern u32 RTL8812AE_RADIOB_ARRAY[];
46#define RTL8821AE_RADIOA_1TARRAYLEN 1176
47extern u32 RTL8821AE_RADIOA_ARRAY[];
48#define RTL8821AEMAC_1T_ARRAYLEN 194
49extern u32 RTL8821AE_MAC_REG_ARRAY[];
50#define RTL8812AEMAC_1T_ARRAYLEN 214
51extern u32 RTL8812AE_MAC_REG_ARRAY[];
52#define RTL8821AEAGCTAB_1TARRAYLEN 382
53extern u32 RTL8821AE_AGC_TAB_ARRAY[];
54#define RTL8812AEAGCTAB_1TARRAYLEN 1312
55extern u32 RTL8812AE_AGC_TAB_ARRAY[];
56#define RTL8812AE_TXPWR_LMT_ARRAY_LEN 3948
57extern u8 *RTL8812AE_TXPWR_LMT[];
58#define RTL8821AE_TXPWR_LMT_ARRAY_LEN 3948
59extern u8 *RTL8821AE_TXPWR_LMT[];
60#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/trx.c b/drivers/net/wireless/rtlwifi/rtl8821ae/trx.c
new file mode 100644
index 000000000000..7ece0efc6d3b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/trx.c
@@ -0,0 +1,1243 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "../base.h"
29#include "../stats.h"
30#include "reg.h"
31#include "def.h"
32#include "phy.h"
33#include "trx.h"
34#include "led.h"
35#include "dm.h"
36#include "phy.h"
37#include "fw.h"
38
39static u8 _rtl8821ae_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
40{
41 __le16 fc = rtl_get_fc(skb);
42
43 if (unlikely(ieee80211_is_beacon(fc)))
44 return QSLT_BEACON;
45 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
46 return QSLT_MGNT;
47
48 return skb->priority;
49}
50
51/* mac80211's rate_idx is like this:
52 *
53 * 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
54 *
55 * B/G rate:
56 * (rx_status->flag & RX_FLAG_HT) = 0,
57 * DESC_RATE1M-->DESC_RATE54M ==> idx is 0-->11,
58 *
59 * N rate:
60 * (rx_status->flag & RX_FLAG_HT) = 1,
61 * DESC_RATEMCS0-->DESC_RATEMCS15 ==> idx is 0-->15
62 *
63 * 5G band:rx_status->band == IEEE80211_BAND_5GHZ
64 * A rate:
65 * (rx_status->flag & RX_FLAG_HT) = 0,
66 * DESC_RATE6M-->DESC_RATE54M ==> idx is 0-->7,
67 *
68 * N rate:
69 * (rx_status->flag & RX_FLAG_HT) = 1,
70 * DESC_RATEMCS0-->DESC_RATEMCS15 ==> idx is 0-->15
71 */
72static int _rtl8821ae_rate_mapping(struct ieee80211_hw *hw,
73 bool isht, bool isvht, u8 desc_rate)
74{
75 int rate_idx;
76
77 if (!isht) {
78 if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
79 switch (desc_rate) {
80 case DESC_RATE1M:
81 rate_idx = 0;
82 break;
83 case DESC_RATE2M:
84 rate_idx = 1;
85 break;
86 case DESC_RATE5_5M:
87 rate_idx = 2;
88 break;
89 case DESC_RATE11M:
90 rate_idx = 3;
91 break;
92 case DESC_RATE6M:
93 rate_idx = 4;
94 break;
95 case DESC_RATE9M:
96 rate_idx = 5;
97 break;
98 case DESC_RATE12M:
99 rate_idx = 6;
100 break;
101 case DESC_RATE18M:
102 rate_idx = 7;
103 break;
104 case DESC_RATE24M:
105 rate_idx = 8;
106 break;
107 case DESC_RATE36M:
108 rate_idx = 9;
109 break;
110 case DESC_RATE48M:
111 rate_idx = 10;
112 break;
113 case DESC_RATE54M:
114 rate_idx = 11;
115 break;
116 default:
117 rate_idx = 0;
118 break;
119 }
120 } else {
121 switch (desc_rate) {
122 case DESC_RATE6M:
123 rate_idx = 0;
124 break;
125 case DESC_RATE9M:
126 rate_idx = 1;
127 break;
128 case DESC_RATE12M:
129 rate_idx = 2;
130 break;
131 case DESC_RATE18M:
132 rate_idx = 3;
133 break;
134 case DESC_RATE24M:
135 rate_idx = 4;
136 break;
137 case DESC_RATE36M:
138 rate_idx = 5;
139 break;
140 case DESC_RATE48M:
141 rate_idx = 6;
142 break;
143 case DESC_RATE54M:
144 rate_idx = 7;
145 break;
146 default:
147 rate_idx = 0;
148 break;
149 }
150 }
151 } else {
152 switch (desc_rate) {
153 case DESC_RATEMCS0:
154 rate_idx = 0;
155 break;
156 case DESC_RATEMCS1:
157 rate_idx = 1;
158 break;
159 case DESC_RATEMCS2:
160 rate_idx = 2;
161 break;
162 case DESC_RATEMCS3:
163 rate_idx = 3;
164 break;
165 case DESC_RATEMCS4:
166 rate_idx = 4;
167 break;
168 case DESC_RATEMCS5:
169 rate_idx = 5;
170 break;
171 case DESC_RATEMCS6:
172 rate_idx = 6;
173 break;
174 case DESC_RATEMCS7:
175 rate_idx = 7;
176 break;
177 case DESC_RATEMCS8:
178 rate_idx = 8;
179 break;
180 case DESC_RATEMCS9:
181 rate_idx = 9;
182 break;
183 case DESC_RATEMCS10:
184 rate_idx = 10;
185 break;
186 case DESC_RATEMCS11:
187 rate_idx = 11;
188 break;
189 case DESC_RATEMCS12:
190 rate_idx = 12;
191 break;
192 case DESC_RATEMCS13:
193 rate_idx = 13;
194 break;
195 case DESC_RATEMCS14:
196 rate_idx = 14;
197 break;
198 case DESC_RATEMCS15:
199 rate_idx = 15;
200 break;
201 default:
202 rate_idx = 0;
203 break;
204 }
205 }
206
207 if (isvht) {
208 switch (desc_rate) {
209 case DESC_RATEVHT1SS_MCS0:
210 rate_idx = 0;
211 break;
212 case DESC_RATEVHT1SS_MCS1:
213 rate_idx = 1;
214 break;
215 case DESC_RATEVHT1SS_MCS2:
216 rate_idx = 2;
217 break;
218 case DESC_RATEVHT1SS_MCS3:
219 rate_idx = 3;
220 break;
221 case DESC_RATEVHT1SS_MCS4:
222 rate_idx = 4;
223 break;
224 case DESC_RATEVHT1SS_MCS5:
225 rate_idx = 5;
226 break;
227 case DESC_RATEVHT1SS_MCS6:
228 rate_idx = 6;
229 break;
230 case DESC_RATEVHT1SS_MCS7:
231 rate_idx = 7;
232 break;
233 case DESC_RATEVHT1SS_MCS8:
234 rate_idx = 8;
235 break;
236 case DESC_RATEVHT1SS_MCS9:
237 rate_idx = 9;
238 break;
239 case DESC_RATEVHT2SS_MCS0:
240 rate_idx = 0;
241 break;
242 case DESC_RATEVHT2SS_MCS1:
243 rate_idx = 1;
244 break;
245 case DESC_RATEVHT2SS_MCS2:
246 rate_idx = 2;
247 break;
248 case DESC_RATEVHT2SS_MCS3:
249 rate_idx = 3;
250 break;
251 case DESC_RATEVHT2SS_MCS4:
252 rate_idx = 4;
253 break;
254 case DESC_RATEVHT2SS_MCS5:
255 rate_idx = 5;
256 break;
257 case DESC_RATEVHT2SS_MCS6:
258 rate_idx = 6;
259 break;
260 case DESC_RATEVHT2SS_MCS7:
261 rate_idx = 7;
262 break;
263 case DESC_RATEVHT2SS_MCS8:
264 rate_idx = 8;
265 break;
266 case DESC_RATEVHT2SS_MCS9:
267 rate_idx = 9;
268 break;
269 default:
270 rate_idx = 0;
271 break;
272 }
273 }
274 return rate_idx;
275}
276
277static u16 odm_cfo(char value)
278{
279 int ret_val;
280
281 if (value < 0) {
282 ret_val = 0 - value;
283 ret_val = (ret_val << 1) + (ret_val >> 1);
284 /* set bit12 as 1 for negative cfo */
285 ret_val = ret_val | BIT(12);
286 } else {
287 ret_val = value;
288 ret_val = (ret_val << 1) + (ret_val >> 1);
289 }
290 return ret_val;
291}
292
293static void query_rxphystatus(struct ieee80211_hw *hw,
294 struct rtl_stats *pstatus, u8 *pdesc,
295 struct rx_fwinfo_8821ae *p_drvinfo,
296 bool bpacket_match_bssid,
297 bool bpacket_toself, bool packet_beacon)
298{
299 struct rtl_priv *rtlpriv = rtl_priv(hw);
300 struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
301 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
302 struct rtl_phy *rtlphy = &rtlpriv->phy;
303 char rx_pwr_all = 0, rx_pwr[4];
304 u8 rf_rx_num = 0, evm, evmdbm, pwdb_all;
305 u8 i, max_spatial_stream;
306 u32 rssi, total_rssi = 0;
307 bool is_cck = pstatus->is_cck;
308 u8 lan_idx, vga_idx;
309
310 /* Record it for next packet processing */
311 pstatus->packet_matchbssid = bpacket_match_bssid;
312 pstatus->packet_toself = bpacket_toself;
313 pstatus->packet_beacon = packet_beacon;
314 pstatus->rx_mimo_signalquality[0] = -1;
315 pstatus->rx_mimo_signalquality[1] = -1;
316
317 if (is_cck) {
318 u8 cck_highpwr;
319 u8 cck_agc_rpt;
320
321 cck_agc_rpt = p_phystrpt->cfosho[0];
322
323 /* (1)Hardware does not provide RSSI for CCK
324 * (2)PWDB, Average PWDB cacluated by
325 * hardware (for rate adaptive)
326 */
327 cck_highpwr = (u8)rtlphy->cck_high_power;
328
329 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
330 vga_idx = (cck_agc_rpt & 0x1f);
331 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
332 switch (lan_idx) {
333 case 7:
334 if (vga_idx <= 27)
335 /*VGA_idx = 27~2*/
336 rx_pwr_all = -100 + 2*(27-vga_idx);
337 else
338 rx_pwr_all = -100;
339 break;
340 case 6:
341 /*VGA_idx = 2~0*/
342 rx_pwr_all = -48 + 2*(2-vga_idx);
343 break;
344 case 5:
345 /*VGA_idx = 7~5*/
346 rx_pwr_all = -42 + 2*(7-vga_idx);
347 break;
348 case 4:
349 /*VGA_idx = 7~4*/
350 rx_pwr_all = -36 + 2*(7-vga_idx);
351 break;
352 case 3:
353 /*VGA_idx = 7~0*/
354 rx_pwr_all = -24 + 2*(7-vga_idx);
355 break;
356 case 2:
357 if (cck_highpwr)
358 /*VGA_idx = 5~0*/
359 rx_pwr_all = -12 + 2*(5-vga_idx);
360 else
361 rx_pwr_all = -6 + 2*(5-vga_idx);
362 break;
363 case 1:
364 rx_pwr_all = 8-2*vga_idx;
365 break;
366 case 0:
367 rx_pwr_all = 14-2*vga_idx;
368 break;
369 default:
370 break;
371 }
372 rx_pwr_all += 6;
373 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
374 if (!cck_highpwr) {
375 if (pwdb_all >= 80)
376 pwdb_all =
377 ((pwdb_all - 80)<<1) +
378 ((pwdb_all - 80)>>1) + 80;
379 else if ((pwdb_all <= 78) && (pwdb_all >= 20))
380 pwdb_all += 3;
381 if (pwdb_all > 100)
382 pwdb_all = 100;
383 }
384 } else { /* 8821 */
385 char pout = -6;
386
387 switch (lan_idx) {
388 case 5:
389 rx_pwr_all = pout - 32 - (2*vga_idx);
390 break;
391 case 4:
392 rx_pwr_all = pout - 24 - (2*vga_idx);
393 break;
394 case 2:
395 rx_pwr_all = pout - 11 - (2*vga_idx);
396 break;
397 case 1:
398 rx_pwr_all = pout + 5 - (2*vga_idx);
399 break;
400 case 0:
401 rx_pwr_all = pout + 21 - (2*vga_idx);
402 break;
403 }
404 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
405 }
406
407 pstatus->rx_pwdb_all = pwdb_all;
408 pstatus->recvsignalpower = rx_pwr_all;
409
410 /* (3) Get Signal Quality (EVM) */
411 if (bpacket_match_bssid) {
412 u8 sq;
413
414 if (pstatus->rx_pwdb_all > 40) {
415 sq = 100;
416 } else {
417 sq = p_phystrpt->pwdb_all;
418 if (sq > 64)
419 sq = 0;
420 else if (sq < 20)
421 sq = 100;
422 else
423 sq = ((64 - sq) * 100) / 44;
424 }
425
426 pstatus->signalquality = sq;
427 pstatus->rx_mimo_signalquality[0] = sq;
428 pstatus->rx_mimo_signalquality[1] = -1;
429 }
430 } else {
431 /* (1)Get RSSI for HT rate */
432 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
433 /* we will judge RF RX path now. */
434 if (rtlpriv->dm.rfpath_rxenable[i])
435 rf_rx_num++;
436
437 rx_pwr[i] = (p_phystrpt->gain_trsw[i] & 0x7f) - 110;
438
439 /* Translate DBM to percentage. */
440 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
441 total_rssi += rssi;
442
443 /* Get Rx snr value in DB */
444 pstatus->rx_snr[i] = p_phystrpt->rxsnr[i] / 2;
445 rtlpriv->stats.rx_snr_db[i] = p_phystrpt->rxsnr[i] / 2;
446
447 pstatus->cfo_short[i] = odm_cfo(p_phystrpt->cfosho[i]);
448 pstatus->cfo_tail[i] = odm_cfo(p_phystrpt->cfotail[i]);
449 /* Record Signal Strength for next packet */
450 pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
451 }
452
453 /* (2)PWDB, Average PWDB cacluated by
454 * hardware (for rate adaptive)
455 */
456 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
457
458 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
459 pstatus->rx_pwdb_all = pwdb_all;
460 pstatus->rxpower = rx_pwr_all;
461 pstatus->recvsignalpower = rx_pwr_all;
462
463 /* (3)EVM of HT rate */
464 if ((pstatus->is_ht && pstatus->rate >= DESC_RATEMCS8 &&
465 pstatus->rate <= DESC_RATEMCS15) ||
466 (pstatus->is_vht &&
467 pstatus->rate >= DESC_RATEVHT2SS_MCS0 &&
468 pstatus->rate <= DESC_RATEVHT2SS_MCS9))
469 max_spatial_stream = 2;
470 else
471 max_spatial_stream = 1;
472
473 for (i = 0; i < max_spatial_stream; i++) {
474 evm = rtl_evm_db_to_percentage(p_phystrpt->rxevm[i]);
475 evmdbm = rtl_evm_dbm_jaguar(p_phystrpt->rxevm[i]);
476
477 if (bpacket_match_bssid) {
478 /* Fill value in RFD, Get the first
479 * spatial stream only
480 */
481 if (i == 0)
482 pstatus->signalquality = evm;
483 pstatus->rx_mimo_signalquality[i] = evm;
484 pstatus->rx_mimo_evm_dbm[i] = evmdbm;
485 }
486 }
487 if (bpacket_match_bssid) {
488 for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
489 rtl_priv(hw)->dm.cfo_tail[i] =
490 (char)p_phystrpt->cfotail[i];
491
492 rtl_priv(hw)->dm.packet_count++;
493 }
494 }
495
496 /* UI BSS List signal strength(in percentage),
497 * make it good looking, from 0~100.
498 */
499 if (is_cck)
500 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
501 pwdb_all));
502 else if (rf_rx_num != 0)
503 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
504 total_rssi /= rf_rx_num));
505 /*HW antenna diversity*/
506 rtldm->fat_table.antsel_rx_keep_0 = p_phystrpt->antidx_anta;
507 rtldm->fat_table.antsel_rx_keep_1 = p_phystrpt->antidx_antb;
508}
509
510static void translate_rx_signal_stuff(struct ieee80211_hw *hw,
511 struct sk_buff *skb,
512 struct rtl_stats *pstatus, u8 *pdesc,
513 struct rx_fwinfo_8821ae *p_drvinfo)
514{
515 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
516 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
517 struct ieee80211_hdr *hdr;
518 u8 *tmp_buf;
519 u8 *praddr;
520 u8 *psaddr;
521 __le16 fc;
522 u16 type;
523 bool packet_matchbssid, packet_toself, packet_beacon;
524
525 tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift;
526
527 hdr = (struct ieee80211_hdr *)tmp_buf;
528 fc = hdr->frame_control;
529 type = WLAN_FC_GET_TYPE(hdr->frame_control);
530 praddr = hdr->addr1;
531 psaddr = ieee80211_get_SA(hdr);
532 ether_addr_copy(pstatus->psaddr, psaddr);
533
534 packet_matchbssid = (!ieee80211_is_ctl(fc) &&
535 (ether_addr_equal(mac->bssid,
536 ieee80211_has_tods(fc) ?
537 hdr->addr1 :
538 ieee80211_has_fromds(fc) ?
539 hdr->addr2 : hdr->addr3)) &&
540 (!pstatus->hwerror) &&
541 (!pstatus->crc) && (!pstatus->icv));
542
543 packet_toself = packet_matchbssid &&
544 (ether_addr_equal(praddr, rtlefuse->dev_addr));
545
546 if (ieee80211_is_beacon(hdr->frame_control))
547 packet_beacon = true;
548 else
549 packet_beacon = false;
550
551 if (packet_beacon && packet_matchbssid)
552 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
553
554 if (packet_matchbssid &&
555 ieee80211_is_data_qos(hdr->frame_control) &&
556 !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
557 struct ieee80211_qos_hdr *hdr_qos =
558 (struct ieee80211_qos_hdr *)tmp_buf;
559 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
560
561 if (tid != 0 && tid != 3)
562 rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
563 }
564
565 query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
566 packet_matchbssid, packet_toself,
567 packet_beacon);
568 /*_rtl8821ae_smart_antenna(hw, pstatus); */
569 rtl_process_phyinfo(hw, tmp_buf, pstatus);
570}
571
572static void _rtl8821ae_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
573 u8 *virtualaddress)
574{
575 u32 dwtmp = 0;
576
577 memset(virtualaddress, 0, 8);
578
579 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
580 if (ptcb_desc->empkt_num == 1) {
581 dwtmp = ptcb_desc->empkt_len[0];
582 } else {
583 dwtmp = ptcb_desc->empkt_len[0];
584 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0)+4;
585 dwtmp += ptcb_desc->empkt_len[1];
586 }
587 SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
588
589 if (ptcb_desc->empkt_num <= 3) {
590 dwtmp = ptcb_desc->empkt_len[2];
591 } else {
592 dwtmp = ptcb_desc->empkt_len[2];
593 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0)+4;
594 dwtmp += ptcb_desc->empkt_len[3];
595 }
596 SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
597 if (ptcb_desc->empkt_num <= 5) {
598 dwtmp = ptcb_desc->empkt_len[4];
599 } else {
600 dwtmp = ptcb_desc->empkt_len[4];
601 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0)+4;
602 dwtmp += ptcb_desc->empkt_len[5];
603 }
604 SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
605 SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
606 if (ptcb_desc->empkt_num <= 7) {
607 dwtmp = ptcb_desc->empkt_len[6];
608 } else {
609 dwtmp = ptcb_desc->empkt_len[6];
610 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0)+4;
611 dwtmp += ptcb_desc->empkt_len[7];
612 }
613 SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
614 if (ptcb_desc->empkt_num <= 9) {
615 dwtmp = ptcb_desc->empkt_len[8];
616 } else {
617 dwtmp = ptcb_desc->empkt_len[8];
618 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0)+4;
619 dwtmp += ptcb_desc->empkt_len[9];
620 }
621 SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
622}
623
624static bool rtl8821ae_get_rxdesc_is_ht(struct ieee80211_hw *hw, u8 *pdesc)
625{
626 struct rtl_priv *rtlpriv = rtl_priv(hw);
627 u8 rx_rate = 0;
628
629 rx_rate = GET_RX_DESC_RXMCS(pdesc);
630
631 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD, "rx_rate=0x%02x.\n", rx_rate);
632
633 if ((rx_rate >= DESC_RATEMCS0) && (rx_rate <= DESC_RATEMCS15))
634 return true;
635 return false;
636}
637
638static bool rtl8821ae_get_rxdesc_is_vht(struct ieee80211_hw *hw, u8 *pdesc)
639{
640 struct rtl_priv *rtlpriv = rtl_priv(hw);
641 u8 rx_rate = 0;
642
643 rx_rate = GET_RX_DESC_RXMCS(pdesc);
644
645 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD, "rx_rate=0x%02x.\n", rx_rate);
646
647 if (rx_rate >= DESC_RATEVHT1SS_MCS0)
648 return true;
649 return false;
650}
651
652static u8 rtl8821ae_get_rx_vht_nss(struct ieee80211_hw *hw, u8 *pdesc)
653{
654 u8 rx_rate = 0;
655 u8 vht_nss = 0;
656
657 rx_rate = GET_RX_DESC_RXMCS(pdesc);
658 if ((rx_rate >= DESC_RATEVHT1SS_MCS0) &&
659 (rx_rate <= DESC_RATEVHT1SS_MCS9))
660 vht_nss = 1;
661 else if ((rx_rate >= DESC_RATEVHT2SS_MCS0) &&
662 (rx_rate <= DESC_RATEVHT2SS_MCS9))
663 vht_nss = 2;
664
665 return vht_nss;
666}
667
668bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
669 struct rtl_stats *status,
670 struct ieee80211_rx_status *rx_status,
671 u8 *pdesc, struct sk_buff *skb)
672{
673 struct rtl_priv *rtlpriv = rtl_priv(hw);
674 struct rx_fwinfo_8821ae *p_drvinfo;
675 struct ieee80211_hdr *hdr;
676
677 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
678
679 status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
680 status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
681 RX_DRV_INFO_SIZE_UNIT;
682 status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
683 status->icv = (u16)GET_RX_DESC_ICV(pdesc);
684 status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
685 status->hwerror = (status->crc | status->icv);
686 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
687 status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
688 status->shortpreamble = (u16)GET_RX_DESC_SPLCP(pdesc);
689 status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
690 status->isfirst_ampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
691 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
692 status->rx_packet_bw = GET_RX_DESC_BW(pdesc);
693 status->macid = GET_RX_DESC_MACID(pdesc);
694 status->is_short_gi = !(bool)GET_RX_DESC_SPLCP(pdesc);
695 status->is_ht = rtl8821ae_get_rxdesc_is_ht(hw, pdesc);
696 status->is_vht = rtl8821ae_get_rxdesc_is_vht(hw, pdesc);
697 status->vht_nss = rtl8821ae_get_rx_vht_nss(hw, pdesc);
698 status->is_cck = RTL8821AE_RX_HAL_IS_CCK_RATE(status->rate);
699
700 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
701 "rx_packet_bw=%s,is_ht %d, is_vht %d, vht_nss=%d,is_short_gi %d.\n",
702 (status->rx_packet_bw == 2) ? "80M" :
703 (status->rx_packet_bw == 1) ? "40M" : "20M",
704 status->is_ht, status->is_vht, status->vht_nss,
705 status->is_short_gi);
706
707 if (GET_RX_STATUS_DESC_RPT_SEL(pdesc))
708 status->packet_report_type = C2H_PACKET;
709 else
710 status->packet_report_type = NORMAL_RX;
711
712 if (GET_RX_STATUS_DESC_PATTERN_MATCH(pdesc))
713 status->wake_match = BIT(2);
714 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
715 status->wake_match = BIT(1);
716 else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
717 status->wake_match = BIT(0);
718 else
719 status->wake_match = 0;
720
721 if (status->wake_match)
722 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
723 "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
724 status->wake_match);
725 rx_status->freq = hw->conf.chandef.chan->center_freq;
726 rx_status->band = hw->conf.chandef.chan->band;
727
728 hdr = (struct ieee80211_hdr *)(skb->data +
729 status->rx_drvinfo_size + status->rx_bufshift);
730
731 if (status->crc)
732 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
733
734 if (status->rx_packet_bw == HT_CHANNEL_WIDTH_20_40)
735 rx_status->flag |= RX_FLAG_40MHZ;
736 else if (status->rx_packet_bw == HT_CHANNEL_WIDTH_80)
737 rx_status->vht_flag |= RX_VHT_FLAG_80MHZ;
738 if (status->is_ht)
739 rx_status->flag |= RX_FLAG_HT;
740 if (status->is_vht)
741 rx_status->flag |= RX_FLAG_VHT;
742
743 if (status->is_short_gi)
744 rx_status->flag |= RX_FLAG_SHORT_GI;
745
746 rx_status->vht_nss = status->vht_nss;
747 rx_status->flag |= RX_FLAG_MACTIME_START;
748
749 /* hw will set status->decrypted true, if it finds the
750 * frame is open data frame or mgmt frame.
751 * So hw will not decryption robust managment frame
752 * for IEEE80211w but still set status->decrypted
753 * true, so here we should set it back to undecrypted
754 * for IEEE80211w frame, and mac80211 sw will help
755 * to decrypt it
756 */
757 if (status->decrypted) {
758 if (!hdr) {
759 WARN_ON_ONCE(true);
760 pr_err("decrypted is true but hdr NULL, from skb %p\n",
761 rtl_get_hdr(skb));
762 return false;
763 }
764
765 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
766 (ieee80211_has_protected(hdr->frame_control)))
767 rx_status->flag |= RX_FLAG_DECRYPTED;
768 else
769 rx_status->flag &= ~RX_FLAG_DECRYPTED;
770 }
771
772 /* rate_idx: index of data rate into band's
773 * supported rates or MCS index if HT rates
774 * are use (RX_FLAG_HT)
775 */
776 rx_status->rate_idx =
777 _rtl8821ae_rate_mapping(hw, status->is_ht,
778 status->is_vht, status->rate);
779
780 rx_status->mactime = status->timestamp_low;
781 if (phystatus) {
782 p_drvinfo = (struct rx_fwinfo_8821ae *)(skb->data +
783 status->rx_bufshift);
784
785 translate_rx_signal_stuff(hw, skb, status, pdesc, p_drvinfo);
786 }
787 rx_status->signal = status->recvsignalpower + 10;
788 if (status->packet_report_type == TX_REPORT2) {
789 status->macid_valid_entry[0] =
790 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
791 status->macid_valid_entry[1] =
792 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
793 }
794 return true;
795}
796
797static u8 rtl8821ae_bw_mapping(struct ieee80211_hw *hw,
798 struct rtl_tcb_desc *ptcb_desc)
799{
800 struct rtl_priv *rtlpriv = rtl_priv(hw);
801 struct rtl_phy *rtlphy = &rtlpriv->phy;
802 u8 bw_setting_of_desc = 0;
803
804 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
805 "rtl8821ae_bw_mapping, current_chan_bw %d, packet_bw %d\n",
806 rtlphy->current_chan_bw, ptcb_desc->packet_bw);
807
808 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
809 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_80)
810 bw_setting_of_desc = 2;
811 else if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40)
812 bw_setting_of_desc = 1;
813 else
814 bw_setting_of_desc = 0;
815 } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
816 if ((ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) ||
817 (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_80))
818 bw_setting_of_desc = 1;
819 else
820 bw_setting_of_desc = 0;
821 } else {
822 bw_setting_of_desc = 0;
823 }
824 return bw_setting_of_desc;
825}
826
827static u8 rtl8821ae_sc_mapping(struct ieee80211_hw *hw,
828 struct rtl_tcb_desc *ptcb_desc)
829{
830 struct rtl_priv *rtlpriv = rtl_priv(hw);
831 struct rtl_phy *rtlphy = &rtlpriv->phy;
832 struct rtl_mac *mac = rtl_mac(rtlpriv);
833 u8 sc_setting_of_desc = 0;
834
835 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
836 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_80) {
837 sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
838 } else if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
839 if (mac->cur_80_prime_sc ==
840 HAL_PRIME_CHNL_OFFSET_LOWER)
841 sc_setting_of_desc =
842 VHT_DATA_SC_40_LOWER_OF_80MHZ;
843 else if (mac->cur_80_prime_sc ==
844 HAL_PRIME_CHNL_OFFSET_UPPER)
845 sc_setting_of_desc =
846 VHT_DATA_SC_40_UPPER_OF_80MHZ;
847 else
848 RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD,
849 "rtl8821ae_sc_mapping: Not Correct Primary40MHz Setting\n");
850 } else {
851 if ((mac->cur_40_prime_sc ==
852 HAL_PRIME_CHNL_OFFSET_LOWER) &&
853 (mac->cur_80_prime_sc ==
854 HAL_PRIME_CHNL_OFFSET_LOWER))
855 sc_setting_of_desc =
856 VHT_DATA_SC_20_LOWEST_OF_80MHZ;
857 else if ((mac->cur_40_prime_sc ==
858 HAL_PRIME_CHNL_OFFSET_UPPER) &&
859 (mac->cur_80_prime_sc ==
860 HAL_PRIME_CHNL_OFFSET_LOWER))
861 sc_setting_of_desc =
862 VHT_DATA_SC_20_LOWER_OF_80MHZ;
863 else if ((mac->cur_40_prime_sc ==
864 HAL_PRIME_CHNL_OFFSET_LOWER) &&
865 (mac->cur_80_prime_sc ==
866 HAL_PRIME_CHNL_OFFSET_UPPER))
867 sc_setting_of_desc =
868 VHT_DATA_SC_20_UPPER_OF_80MHZ;
869 else if ((mac->cur_40_prime_sc ==
870 HAL_PRIME_CHNL_OFFSET_UPPER) &&
871 (mac->cur_80_prime_sc ==
872 HAL_PRIME_CHNL_OFFSET_UPPER))
873 sc_setting_of_desc =
874 VHT_DATA_SC_20_UPPERST_OF_80MHZ;
875 else
876 RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD,
877 "rtl8821ae_sc_mapping: Not Correct Primary40MHz Setting\n");
878 }
879 } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
880 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
881 sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
882 } else if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20) {
883 if (mac->cur_40_prime_sc ==
884 HAL_PRIME_CHNL_OFFSET_UPPER) {
885 sc_setting_of_desc =
886 VHT_DATA_SC_20_UPPER_OF_80MHZ;
887 } else if (mac->cur_40_prime_sc ==
888 HAL_PRIME_CHNL_OFFSET_LOWER){
889 sc_setting_of_desc =
890 VHT_DATA_SC_20_LOWER_OF_80MHZ;
891 } else {
892 sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
893 }
894 }
895 } else {
896 sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
897 }
898
899 return sc_setting_of_desc;
900}
901
902void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
903 struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
904 struct ieee80211_tx_info *info,
905 struct ieee80211_sta *sta,
906 struct sk_buff *skb,
907 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
908{
909 struct rtl_priv *rtlpriv = rtl_priv(hw);
910 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
911 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
912 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
913 u8 *pdesc = (u8 *)pdesc_tx;
914 u16 seq_number;
915 __le16 fc = hdr->frame_control;
916 unsigned int buf_len = 0;
917 unsigned int skb_len = skb->len;
918 u8 fw_qsel = _rtl8821ae_map_hwqueue_to_fwqueue(skb, hw_queue);
919 bool firstseg = ((hdr->seq_ctrl &
920 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
921 bool lastseg = ((hdr->frame_control &
922 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
923 dma_addr_t mapping;
924 u8 short_gi = 0;
925
926 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
927 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
928 /* reserve 8 byte for AMPDU early mode */
929 if (rtlhal->earlymode_enable) {
930 skb_push(skb, EM_HDR_LEN);
931 memset(skb->data, 0, EM_HDR_LEN);
932 }
933 buf_len = skb->len;
934 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
935 PCI_DMA_TODEVICE);
936 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
937 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
938 "DMA mapping error");
939 return;
940 }
941 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_8821ae));
942 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
943 firstseg = true;
944 lastseg = true;
945 }
946 if (firstseg) {
947 if (rtlhal->earlymode_enable) {
948 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
949 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
950 EM_HDR_LEN);
951 if (ptcb_desc->empkt_num) {
952 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
953 "Insert 8 byte.pTcb->EMPktNum:%d\n",
954 ptcb_desc->empkt_num);
955 _rtl8821ae_insert_emcontent(ptcb_desc,
956 (u8 *)(skb->data));
957 }
958 } else {
959 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
960 }
961
962 /* ptcb_desc->use_driver_rate = true; */
963 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
964 if (ptcb_desc->hw_rate > DESC_RATEMCS0)
965 short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
966 else
967 short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
968
969 SET_TX_DESC_DATA_SHORTGI(pdesc, short_gi);
970
971 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
972 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
973 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x1f);
974 }
975 SET_TX_DESC_SEQ(pdesc, seq_number);
976 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
977 !ptcb_desc->cts_enable) ? 1 : 0));
978 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
979 SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
980
981 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
982 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
983 SET_TX_DESC_RTS_SHORT(pdesc,
984 ((ptcb_desc->rts_rate <= DESC_RATE54M) ?
985 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
986 (ptcb_desc->rts_use_shortgi ? 1 : 0)));
987
988 if (ptcb_desc->tx_enable_sw_calc_duration)
989 SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
990
991 SET_TX_DESC_DATA_BW(pdesc,
992 rtl8821ae_bw_mapping(hw, ptcb_desc));
993
994 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
995 rtl8821ae_sc_mapping(hw, ptcb_desc));
996
997 SET_TX_DESC_LINIP(pdesc, 0);
998 SET_TX_DESC_PKT_SIZE(pdesc, (u16)skb_len);
999 if (sta) {
1000 u8 ampdu_density = sta->ht_cap.ampdu_density;
1001
1002 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
1003 }
1004 if (info->control.hw_key) {
1005 struct ieee80211_key_conf *keyconf =
1006 info->control.hw_key;
1007 switch (keyconf->cipher) {
1008 case WLAN_CIPHER_SUITE_WEP40:
1009 case WLAN_CIPHER_SUITE_WEP104:
1010 case WLAN_CIPHER_SUITE_TKIP:
1011 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
1012 break;
1013 case WLAN_CIPHER_SUITE_CCMP:
1014 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
1015 break;
1016 default:
1017 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
1018 break;
1019 }
1020 }
1021
1022 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
1023 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
1024 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
1025 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
1026 1 : 0);
1027 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
1028
1029 if (ieee80211_is_data_qos(fc)) {
1030 if (mac->rdg_en) {
1031 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
1032 "Enable RDG function.\n");
1033 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
1034 SET_TX_DESC_HTC(pdesc, 1);
1035 }
1036 }
1037 }
1038
1039 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
1040 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
1041 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)buf_len);
1042 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1043 /* if (rtlpriv->dm.useramask) { */
1044 if (1) {
1045 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
1046 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
1047 } else {
1048 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
1049 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
1050 }
1051 if (!ieee80211_is_data_qos(fc)) {
1052 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
1053 SET_TX_DESC_HWSEQ_SEL(pdesc, 0);
1054 }
1055 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
1056 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
1057 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
1058 SET_TX_DESC_BMC(pdesc, 1);
1059 }
1060
1061 rtl8821ae_dm_set_tx_ant_by_tx_info(hw, pdesc, ptcb_desc->mac_id);
1062 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
1063}
1064
1065void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
1066 u8 *pdesc, bool firstseg,
1067 bool lastseg, struct sk_buff *skb)
1068{
1069 struct rtl_priv *rtlpriv = rtl_priv(hw);
1070 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1071 u8 fw_queue = QSLT_BEACON;
1072
1073 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
1074 skb->data, skb->len,
1075 PCI_DMA_TODEVICE);
1076
1077 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
1078 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
1079 "DMA mapping error");
1080 return;
1081 }
1082 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
1083
1084 SET_TX_DESC_FIRST_SEG(pdesc, 1);
1085 SET_TX_DESC_LAST_SEG(pdesc, 1);
1086
1087 SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
1088
1089 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
1090
1091 SET_TX_DESC_USE_RATE(pdesc, 1);
1092 SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M);
1093 SET_TX_DESC_DISABLE_FB(pdesc, 1);
1094
1095 SET_TX_DESC_DATA_BW(pdesc, 0);
1096
1097 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
1098
1099 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
1100
1101 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
1102
1103 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1104
1105 SET_TX_DESC_MACID(pdesc, 0);
1106
1107 SET_TX_DESC_OWN(pdesc, 1);
1108
1109 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1110 "H2C Tx Cmd Content\n",
1111 pdesc, TX_DESC_SIZE);
1112}
1113
1114void rtl8821ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
1115 bool istx, u8 desc_name, u8 *val)
1116{
1117 if (istx) {
1118 switch (desc_name) {
1119 case HW_DESC_OWN:
1120 SET_TX_DESC_OWN(pdesc, 1);
1121 break;
1122 case HW_DESC_TX_NEXTDESC_ADDR:
1123 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
1124 break;
1125 default:
1126 RT_ASSERT(false,
1127 "ERR txdesc :%d not process\n", desc_name);
1128 break;
1129 }
1130 } else {
1131 switch (desc_name) {
1132 case HW_DESC_RXOWN:
1133 SET_RX_DESC_OWN(pdesc, 1);
1134 break;
1135 case HW_DESC_RXBUFF_ADDR:
1136 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *)val);
1137 break;
1138 case HW_DESC_RXPKT_LEN:
1139 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *)val);
1140 break;
1141 case HW_DESC_RXERO:
1142 SET_RX_DESC_EOR(pdesc, 1);
1143 break;
1144 default:
1145 RT_ASSERT(false,
1146 "ERR rxdesc :%d not process\n", desc_name);
1147 break;
1148 }
1149 }
1150}
1151
1152u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
1153{
1154 u32 ret = 0;
1155
1156 if (istx) {
1157 switch (desc_name) {
1158 case HW_DESC_OWN:
1159 ret = GET_TX_DESC_OWN(pdesc);
1160 break;
1161 case HW_DESC_TXBUFF_ADDR:
1162 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc);
1163 break;
1164 default:
1165 RT_ASSERT(false,
1166 "ERR txdesc :%d not process\n", desc_name);
1167 break;
1168 }
1169 } else {
1170 switch (desc_name) {
1171 case HW_DESC_OWN:
1172 ret = GET_RX_DESC_OWN(pdesc);
1173 break;
1174 case HW_DESC_RXPKT_LEN:
1175 ret = GET_RX_DESC_PKT_LEN(pdesc);
1176 break;
1177 case HW_DESC_RXBUFF_ADDR:
1178 ret = GET_RX_DESC_BUFF_ADDR(pdesc);
1179 break;
1180 default:
1181 RT_ASSERT(false,
1182 "ERR rxdesc :%d not process\n", desc_name);
1183 break;
1184 }
1185 }
1186 return ret;
1187}
1188
1189bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
1190 u8 hw_queue, u16 index)
1191{
1192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1193 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
1194 u8 *entry = (u8 *)(&ring->desc[ring->idx]);
1195 u8 own = (u8)rtl8821ae_get_desc(entry, true, HW_DESC_OWN);
1196
1197 /**
1198 *beacon packet will only use the first
1199 *descriptor defautly,and the own may not
1200 *be cleared by the hardware
1201 */
1202 if (own)
1203 return false;
1204 return true;
1205}
1206
1207void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
1208{
1209 struct rtl_priv *rtlpriv = rtl_priv(hw);
1210
1211 if (hw_queue == BEACON_QUEUE) {
1212 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
1213 } else {
1214 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
1215 BIT(0) << (hw_queue));
1216 }
1217}
1218
1219u32 rtl8821ae_rx_command_packet(struct ieee80211_hw *hw,
1220 struct rtl_stats status,
1221 struct sk_buff *skb)
1222{
1223 u32 result = 0;
1224 struct rtl_priv *rtlpriv = rtl_priv(hw);
1225
1226 switch (status.packet_report_type) {
1227 case NORMAL_RX:
1228 result = 0;
1229 break;
1230 case C2H_PACKET:
1231 rtl8821ae_c2h_packet_handler(hw, skb->data, (u8)skb->len);
1232 result = 1;
1233 RT_TRACE(rtlpriv, COMP_RECV, DBG_LOUD,
1234 "skb->len=%d\n\n", skb->len);
1235 break;
1236 default:
1237 RT_TRACE(rtlpriv, COMP_RECV, DBG_LOUD,
1238 "No this packet type!!\n");
1239 break;
1240 }
1241
1242 return result;
1243}
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/trx.h b/drivers/net/wireless/rtlwifi/rtl8821ae/trx.h
new file mode 100644
index 000000000000..31409042d8dd
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/trx.h
@@ -0,0 +1,620 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8821AE_TRX_H__
27#define __RTL8821AE_TRX_H__
28
29#define TX_DESC_SIZE 40
30#define TX_DESC_AGGR_SUBFRAME_SIZE 32
31
32#define RX_DESC_SIZE 32
33#define RX_DRV_INFO_SIZE_UNIT 8
34
35#define TX_DESC_NEXT_DESC_OFFSET 40
36#define USB_HWDESC_HEADER_LEN 40
37#define CRCLENGTH 4
38
39#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
40 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
41#define SET_TX_DESC_OFFSET(__pdesc, __val) \
42 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
43#define SET_TX_DESC_BMC(__pdesc, __val) \
44 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
45#define SET_TX_DESC_HTC(__pdesc, __val) \
46 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
47#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
48 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
49#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
50 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
51#define SET_TX_DESC_LINIP(__pdesc, __val) \
52 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
53#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
54 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
55#define SET_TX_DESC_GF(__pdesc, __val) \
56 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
57#define SET_TX_DESC_OWN(__pdesc, __val) \
58 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
59
60#define GET_TX_DESC_PKT_SIZE(__pdesc) \
61 LE_BITS_TO_4BYTE(__pdesc, 0, 16)
62#define GET_TX_DESC_OFFSET(__pdesc) \
63 LE_BITS_TO_4BYTE(__pdesc, 16, 8)
64#define GET_TX_DESC_BMC(__pdesc) \
65 LE_BITS_TO_4BYTE(__pdesc, 24, 1)
66#define GET_TX_DESC_HTC(__pdesc) \
67 LE_BITS_TO_4BYTE(__pdesc, 25, 1)
68#define GET_TX_DESC_LAST_SEG(__pdesc) \
69 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
70#define GET_TX_DESC_FIRST_SEG(__pdesc) \
71 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
72#define GET_TX_DESC_LINIP(__pdesc) \
73 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
74#define GET_TX_DESC_NO_ACM(__pdesc) \
75 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
76#define GET_TX_DESC_GF(__pdesc) \
77 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
78#define GET_TX_DESC_OWN(__pdesc) \
79 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
80
81#define SET_TX_DESC_MACID(__pdesc, __val) \
82 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
83#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
84 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
85#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
86 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
87#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
88 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
89#define SET_TX_DESC_PIFS(__pdesc, __val) \
90 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
91#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
92 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
93#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
94 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
95#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
96 SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
97#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
98 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
99
100#define SET_TX_DESC_PAID(__pdesc, __val) \
101 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
102#define SET_TX_DESC_CCA_RTS(__pdesc, __val) \
103 SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
104#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
105 SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
106#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
107 SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
108#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
109 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
110#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
111 SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
112#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
113 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
114#define SET_TX_DESC_RAW(__pdesc, __val) \
115 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
116#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
117 SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
118#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
119 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
120#define SET_TX_DESC_BT_INT(__pdesc, __val) \
121 SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
122#define SET_TX_DESC_GID(__pdesc, __val) \
123 SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
124
125#define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \
126 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
127#define SET_TX_DESC_CHK_EN(__pdesc, __val) \
128 SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
129#define SET_TX_DESC_EARLY_MODE(__pdesc, __val) \
130 SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
131#define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \
132 SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
133#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
134 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
135#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
136 SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
137#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
138 SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
139#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
140 SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
141#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
142 SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
143#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
144 SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
145#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
146 SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
147#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
148 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
149#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
150 SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
151#define SET_TX_DESC_NDPA(__pdesc, __val) \
152 SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
153#define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \
154 SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
155#define SET_TX_DESC_TX_ANT(__pdesc, __val) \
156 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
157
158#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
159 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
160#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
161 SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
162#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
163 SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
164#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
165 SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
166#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
167 SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
168#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
169 SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
170
171#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
172 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
173#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
174 SET_BITS_TO_LE_1BYTE(__pdesc+20, 4, 1, __val)
175#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
176 SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
177#define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \
178 SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
179#define SET_TX_DESC_DATA_STBC(__pdesc, __val) \
180 SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
181#define SET_TX_DESC_CTROL_STBC(__pdesc, __val) \
182 SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
183#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
184 SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
185#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
186 SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
187
188#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
189 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
190
191#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
192 LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
193
194#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
195 SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val)
196
197#define SET_TX_DESC_SEQ(__pdesc, __val) \
198 SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val)
199
200#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
201 SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
202
203#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
204 LE_BITS_TO_4BYTE(__pdesc+40, 0, 32)
205
206#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
207 SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val)
208
209#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
210 LE_BITS_TO_4BYTE(__pdesc+48, 0, 32)
211
212#define GET_RX_DESC_PKT_LEN(__pdesc) \
213 LE_BITS_TO_4BYTE(__pdesc, 0, 14)
214#define GET_RX_DESC_CRC32(__pdesc) \
215 LE_BITS_TO_4BYTE(__pdesc, 14, 1)
216#define GET_RX_DESC_ICV(__pdesc) \
217 LE_BITS_TO_4BYTE(__pdesc, 15, 1)
218#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
219 LE_BITS_TO_4BYTE(__pdesc, 16, 4)
220#define GET_RX_DESC_SECURITY(__pdesc) \
221 LE_BITS_TO_4BYTE(__pdesc, 20, 3)
222#define GET_RX_DESC_QOS(__pdesc) \
223 LE_BITS_TO_4BYTE(__pdesc, 23, 1)
224#define GET_RX_DESC_SHIFT(__pdesc) \
225 LE_BITS_TO_4BYTE(__pdesc, 24, 2)
226#define GET_RX_DESC_PHYST(__pdesc) \
227 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
228#define GET_RX_DESC_SWDEC(__pdesc) \
229 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
230#define GET_RX_DESC_LS(__pdesc) \
231 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
232#define GET_RX_DESC_FS(__pdesc) \
233 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
234#define GET_RX_DESC_EOR(__pdesc) \
235 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
236#define GET_RX_DESC_OWN(__pdesc) \
237 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
238
239#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
240 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
241#define SET_RX_DESC_EOR(__pdesc, __val) \
242 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
243#define SET_RX_DESC_OWN(__pdesc, __val) \
244 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
245
246#define GET_RX_DESC_MACID(__pdesc) \
247 LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
248#define GET_RX_DESC_TID(__pdesc) \
249 LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
250#define GET_RX_DESC_AMSDU(__pdesc) \
251 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
252#define GET_RX_STATUS_DESC_RXID_MATCH(__pdesc) \
253 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
254#define GET_RX_DESC_PAGGR(__pdesc) \
255 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
256#define GET_RX_DESC_A1_FIT(__pdesc) \
257 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
258#define GET_RX_DESC_CHKERR(__pdesc) \
259 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
260#define GET_RX_DESC_IPVER(__pdesc) \
261 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
262#define GET_RX_STATUS_DESC_IS_TCPUDP(__pdesc) \
263 LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
264#define GET_RX_STATUS_DESC_CHK_VLD(__pdesc) \
265 LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
266#define GET_RX_DESC_PAM(__pdesc) \
267 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
268#define GET_RX_DESC_PWR(__pdesc) \
269 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
270#define GET_RX_DESC_MD(__pdesc) \
271 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
272#define GET_RX_DESC_MF(__pdesc) \
273 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
274#define GET_RX_DESC_TYPE(__pdesc) \
275 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
276#define GET_RX_DESC_MC(__pdesc) \
277 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
278#define GET_RX_DESC_BC(__pdesc) \
279 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
280
281#define GET_RX_DESC_SEQ(__pdesc) \
282 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
283#define GET_RX_DESC_FRAG(__pdesc) \
284 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
285#define GET_RX_STATUS_DESC_RX_IS_QOS(__pdesc) \
286 LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
287#define GET_RX_STATUS_DESC_WLANHD_IV_LEN(__pdesc) \
288 LE_BITS_TO_4BYTE(__pdesc+8, 18, 6)
289#define GET_RX_STATUS_DESC_RPT_SEL(__pdesc) \
290 LE_BITS_TO_4BYTE(__pdesc+8, 28, 1)
291
292#define GET_RX_DESC_RXMCS(__pdesc) \
293 LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
294#define GET_RX_DESC_HTC(__pdesc) \
295 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
296#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
297 LE_BITS_TO_4BYTE(__pdesc+12, 11, 1)
298#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
299 LE_BITS_TO_4BYTE(__pdesc+12, 12, 2)
300
301#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
302 LE_BITS_TO_4BYTE(__pdesc+12, 29, 1)
303#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
304 LE_BITS_TO_4BYTE(__pdesc+12, 30, 1)
305#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
306 LE_BITS_TO_4BYTE(__pdesc+12, 31, 1)
307
308#define GET_RX_DESC_SPLCP(__pdesc) \
309 LE_BITS_TO_4BYTE(__pdesc+16, 0, 1)
310#define GET_RX_STATUS_DESC_LDPC(__pdesc) \
311 LE_BITS_TO_4BYTE(__pdesc+16, 1, 1)
312#define GET_RX_STATUS_DESC_STBC(__pdesc) \
313 LE_BITS_TO_4BYTE(__pdesc+16, 2, 1)
314#define GET_RX_DESC_BW(__pdesc) \
315 LE_BITS_TO_4BYTE(__pdesc+16, 4, 2)
316
317#define GET_RX_DESC_TSFL(__pdesc) \
318 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
319
320#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
321 LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
322#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
323 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
324
325#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
326 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
327#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
328 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
329
330/* TX report 2 format in Rx desc*/
331
332#define GET_RX_RPT2_DESC_PKT_LEN(__status) \
333 LE_BITS_TO_4BYTE(__status, 0, 9)
334#define GET_RX_RPT2_DESC_MACID_VALID_1(__status) \
335 LE_BITS_TO_4BYTE(__status+16, 0, 32)
336#define GET_RX_RPT2_DESC_MACID_VALID_2(__status) \
337 LE_BITS_TO_4BYTE(__status+20, 0, 32)
338
339#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
340 SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __value)
341#define SET_EARLYMODE_LEN0(__paddr, __value) \
342 SET_BITS_TO_LE_4BYTE(__paddr, 4, 12, __value)
343#define SET_EARLYMODE_LEN1(__paddr, __value) \
344 SET_BITS_TO_LE_4BYTE(__paddr, 16, 12, __value)
345#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
346 SET_BITS_TO_LE_4BYTE(__paddr, 28, 4, __value)
347#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
348 SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __value)
349#define SET_EARLYMODE_LEN3(__paddr, __value) \
350 SET_BITS_TO_LE_4BYTE(__paddr+4, 8, 12, __value)
351#define SET_EARLYMODE_LEN4(__paddr, __value) \
352 SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __value)
353
354#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
355do { \
356 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
357 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
358 else \
359 memset(__pdesc, 0, _size); \
360} while (0)
361
362#define RTL8821AE_RX_HAL_IS_CCK_RATE(rxmcs)\
363 (rxmcs == DESC_RATE1M ||\
364 rxmcs == DESC_RATE2M ||\
365 rxmcs == DESC_RATE5_5M ||\
366 rxmcs == DESC_RATE11M)
367
368struct phy_rx_agc_info_t {
369 #ifdef __LITTLE_ENDIAN
370 u8 gain:7, trsw:1;
371 #else
372 u8 trsw:1, gain:7;
373 #endif
374};
375
376struct phy_status_rpt {
377 /* DWORD 0 */
378 u8 gain_trsw[2];
379#ifdef __LITTLE_ENDIAN
380 u16 chl_num:10;
381 u16 sub_chnl:4;
382 u16 r_rfmod:2;
383#else /* _BIG_ENDIAN_ */
384 u16 r_rfmod:2;
385 u16 sub_chnl:4;
386 u16 chl_num:10;
387#endif
388 /* DWORD 1 */
389 u8 pwdb_all;
390 u8 cfosho[4]; /* DW 1 byte 1 DW 2 byte 0 */
391
392 /* DWORD 2 */
393 char cfotail[4]; /* DW 2 byte 1 DW 3 byte 0 */
394
395 /* DWORD 3 */
396 char rxevm[2]; /* DW 3 byte 1 DW 3 byte 2 */
397 char rxsnr[2]; /* DW 3 byte 3 DW 4 byte 0 */
398
399 /* DWORD 4 */
400 u8 pcts_msk_rpt[2];
401 u8 pdsnr[2]; /* DW 4 byte 3 DW 5 Byte 0 */
402
403 /* DWORD 5 */
404 u8 csi_current[2];
405 u8 rx_gain_c;
406
407 /* DWORD 6 */
408 u8 rx_gain_d;
409 u8 sigevm;
410 u8 resvd_0;
411 u8 antidx_anta:3;
412 u8 antidx_antb:3;
413 u8 resvd_1:2;
414} __packed;
415
416struct rx_fwinfo_8821ae {
417 u8 gain_trsw[4];
418 u8 pwdb_all;
419 u8 cfosho[4];
420 u8 cfotail[4];
421 char rxevm[2];
422 char rxsnr[4];
423 u8 pdsnr[2];
424 u8 csi_current[2];
425 u8 csi_target[2];
426 u8 sigevm;
427 u8 max_ex_pwr;
428 u8 ex_intf_flag:1;
429 u8 sgi_en:1;
430 u8 rxsc:2;
431 u8 reserve:4;
432} __packed;
433
434struct tx_desc_8821ae {
435 u32 pktsize:16;
436 u32 offset:8;
437 u32 bmc:1;
438 u32 htc:1;
439 u32 lastseg:1;
440 u32 firstseg:1;
441 u32 linip:1;
442 u32 noacm:1;
443 u32 gf:1;
444 u32 own:1;
445
446 u32 macid:6;
447 u32 rsvd0:2;
448 u32 queuesel:5;
449 u32 rd_nav_ext:1;
450 u32 lsig_txop_en:1;
451 u32 pifs:1;
452 u32 rateid:4;
453 u32 nav_usehdr:1;
454 u32 en_descid:1;
455 u32 sectype:2;
456 u32 pktoffset:8;
457
458 u32 rts_rc:6;
459 u32 data_rc:6;
460 u32 agg_en:1;
461 u32 rdg_en:1;
462 u32 bar_retryht:2;
463 u32 agg_break:1;
464 u32 morefrag:1;
465 u32 raw:1;
466 u32 ccx:1;
467 u32 ampdudensity:3;
468 u32 bt_int:1;
469 u32 ant_sela:1;
470 u32 ant_selb:1;
471 u32 txant_cck:2;
472 u32 txant_l:2;
473 u32 txant_ht:2;
474
475 u32 nextheadpage:8;
476 u32 tailpage:8;
477 u32 seq:12;
478 u32 cpu_handle:1;
479 u32 tag1:1;
480 u32 trigger_int:1;
481 u32 hwseq_en:1;
482
483 u32 rtsrate:5;
484 u32 apdcfe:1;
485 u32 qos:1;
486 u32 hwseq_ssn:1;
487 u32 userrate:1;
488 u32 dis_rtsfb:1;
489 u32 dis_datafb:1;
490 u32 cts2self:1;
491 u32 rts_en:1;
492 u32 hwrts_en:1;
493 u32 portid:1;
494 u32 pwr_status:3;
495 u32 waitdcts:1;
496 u32 cts2ap_en:1;
497 u32 txsc:2;
498 u32 stbc:2;
499 u32 txshort:1;
500 u32 txbw:1;
501 u32 rtsshort:1;
502 u32 rtsbw:1;
503 u32 rtssc:2;
504 u32 rtsstbc:2;
505
506 u32 txrate:6;
507 u32 shortgi:1;
508 u32 ccxt:1;
509 u32 txrate_fb_lmt:5;
510 u32 rtsrate_fb_lmt:4;
511 u32 retrylmt_en:1;
512 u32 txretrylmt:6;
513 u32 usb_txaggnum:8;
514
515 u32 txagca:5;
516 u32 txagcb:5;
517 u32 usemaxlen:1;
518 u32 maxaggnum:5;
519 u32 mcsg1maxlen:4;
520 u32 mcsg2maxlen:4;
521 u32 mcsg3maxlen:4;
522 u32 mcs7sgimaxlen:4;
523
524 u32 txbuffersize:16;
525 u32 sw_offset30:8;
526 u32 sw_offset31:4;
527 u32 rsvd1:1;
528 u32 antsel_c:1;
529 u32 null_0:1;
530 u32 null_1:1;
531
532 u32 txbuffaddr;
533 u32 txbufferaddr64;
534 u32 nextdescaddress;
535 u32 nextdescaddress64;
536
537 u32 reserve_pass_pcie_mm_limit[4];
538} __packed;
539
540struct rx_desc_8821ae {
541 u32 length:14;
542 u32 crc32:1;
543 u32 icverror:1;
544 u32 drv_infosize:4;
545 u32 security:3;
546 u32 qos:1;
547 u32 shift:2;
548 u32 phystatus:1;
549 u32 swdec:1;
550 u32 lastseg:1;
551 u32 firstseg:1;
552 u32 eor:1;
553 u32 own:1;
554
555 u32 macid:6;
556 u32 tid:4;
557 u32 hwrsvd:5;
558 u32 paggr:1;
559 u32 faggr:1;
560 u32 a1_fit:4;
561 u32 a2_fit:4;
562 u32 pam:1;
563 u32 pwr:1;
564 u32 moredata:1;
565 u32 morefrag:1;
566 u32 type:2;
567 u32 mc:1;
568 u32 bc:1;
569
570 u32 seq:12;
571 u32 frag:4;
572 u32 nextpktlen:14;
573 u32 nextind:1;
574 u32 rsvd:1;
575
576 u32 rxmcs:6;
577 u32 rxht:1;
578 u32 amsdu:1;
579 u32 splcp:1;
580 u32 bandwidth:1;
581 u32 htc:1;
582 u32 tcpchk_rpt:1;
583 u32 ipcchk_rpt:1;
584 u32 tcpchk_valid:1;
585 u32 hwpcerr:1;
586 u32 hwpcind:1;
587 u32 iv0:16;
588
589 u32 iv1;
590
591 u32 tsfl;
592
593 u32 bufferaddress;
594 u32 bufferaddress64;
595
596} __packed;
597
598void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
599 struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
600 struct ieee80211_tx_info *info,
601 struct ieee80211_sta *sta,
602 struct sk_buff *skb,
603 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
604bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
605 struct rtl_stats *status,
606 struct ieee80211_rx_status *rx_status,
607 u8 *pdesc, struct sk_buff *skb);
608void rtl8821ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
609 bool istx, u8 desc_name, u8 *val);
610u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name);
611bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
612 u8 hw_queue, u16 index);
613void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
614void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
615 bool firstseg, bool lastseg,
616 struct sk_buff *skb);
617u32 rtl8821ae_rx_command_packet(struct ieee80211_hw *hw,
618 struct rtl_stats status,
619 struct sk_buff *skb);
620#endif
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 06b5741401a7..b2a2f5110efe 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -148,6 +144,11 @@
148#define EM_HDR_LEN 8 144#define EM_HDR_LEN 8
149 145
150#define MAX_TX_COUNT 4 146#define MAX_TX_COUNT 4
147#define MAX_REGULATION_NUM 4
148#define MAX_RF_PATH_NUM 4
149#define MAX_RATE_SECTION_NUM 6
150#define MAX_2_4G_BANDWITH_NUM 4
151#define MAX_5G_BANDWITH_NUM 4
151#define MAX_RF_PATH 4 152#define MAX_RF_PATH 4
152#define MAX_CHNL_GROUP_24G 6 153#define MAX_CHNL_GROUP_24G 6
153#define MAX_CHNL_GROUP_5G 14 154#define MAX_CHNL_GROUP_5G 14
@@ -249,6 +250,15 @@ enum radio_path {
249 RF90_PATH_D = 3, 250 RF90_PATH_D = 3,
250}; 251};
251 252
253enum regulation_txpwr_lmt {
254 TXPWR_LMT_FCC = 0,
255 TXPWR_LMT_MKK = 1,
256 TXPWR_LMT_ETSI = 2,
257 TXPWR_LMT_WW = 3,
258
259 TXPWR_LMT_MAX_REGULATION_NUM = 4
260};
261
252enum rt_eeprom_type { 262enum rt_eeprom_type {
253 EEPROM_93C46, 263 EEPROM_93C46,
254 EEPROM_93C56, 264 EEPROM_93C56,
@@ -376,6 +386,7 @@ enum hw_variables {
376 HW_VAR_DEFAULTKEY2, 386 HW_VAR_DEFAULTKEY2,
377 HW_VAR_DEFAULTKEY3, 387 HW_VAR_DEFAULTKEY3,
378 HW_VAR_SIFS, 388 HW_VAR_SIFS,
389 HW_VAR_R2T_SIFS,
379 HW_VAR_DIFS, 390 HW_VAR_DIFS,
380 HW_VAR_EIFS, 391 HW_VAR_EIFS,
381 HW_VAR_SLOT_TIME, 392 HW_VAR_SLOT_TIME,
@@ -427,6 +438,7 @@ enum hw_variables {
427 HW_VAR_H2C_FW_MEDIASTATUSRPT, 438 HW_VAR_H2C_FW_MEDIASTATUSRPT,
428 HW_VAR_H2C_FW_P2P_PS_OFFLOAD, 439 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
429 HW_VAR_FW_PSMODE_STATUS, 440 HW_VAR_FW_PSMODE_STATUS,
441 HW_VAR_INIT_RTS_RATE,
430 HW_VAR_RESUME_CLK_ON, 442 HW_VAR_RESUME_CLK_ON,
431 HW_VAR_FW_LPS_ACTION, 443 HW_VAR_FW_LPS_ACTION,
432 HW_VAR_1X1_RECV_COMBINE, 444 HW_VAR_1X1_RECV_COMBINE,
@@ -789,7 +801,9 @@ enum wireless_mode {
789 WIRELESS_MODE_N_24G = 0x10, 801 WIRELESS_MODE_N_24G = 0x10,
790 WIRELESS_MODE_N_5G = 0x20, 802 WIRELESS_MODE_N_5G = 0x20,
791 WIRELESS_MODE_AC_5G = 0x40, 803 WIRELESS_MODE_AC_5G = 0x40,
792 WIRELESS_MODE_AC_24G = 0x80 804 WIRELESS_MODE_AC_24G = 0x80,
805 WIRELESS_MODE_AC_ONLY = 0x100,
806 WIRELESS_MODE_MAX = 0x800
793}; 807};
794 808
795#define IS_WIRELESS_MODE_A(wirelessmode) \ 809#define IS_WIRELESS_MODE_A(wirelessmode) \
@@ -843,6 +857,22 @@ enum rt_polarity_ctl {
843 RT_POLARITY_HIGH_ACT = 1, 857 RT_POLARITY_HIGH_ACT = 1,
844}; 858};
845 859
860/* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
861enum fw_wow_reason_v2 {
862 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
863 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
864 FW_WOW_V2_DISASSOC_EVENT = 0x04,
865 FW_WOW_V2_DEAUTH_EVENT = 0x08,
866 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
867 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
868 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
869 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
870 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
871 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
872 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
873 FW_WOW_V2_REASON_MAX = 0xff,
874};
875
846enum wolpattern_type { 876enum wolpattern_type {
847 UNICAST_PATTERN = 0, 877 UNICAST_PATTERN = 0,
848 MULTICAST_PATTERN = 1, 878 MULTICAST_PATTERN = 1,
@@ -1182,6 +1212,17 @@ struct rtl_phy {
1182 u8 cur_bw20_txpwridx; 1212 u8 cur_bw20_txpwridx;
1183 u8 cur_bw40_txpwridx; 1213 u8 cur_bw40_txpwridx;
1184 1214
1215 char txpwr_limit_2_4g[MAX_REGULATION_NUM]
1216 [MAX_2_4G_BANDWITH_NUM]
1217 [MAX_RATE_SECTION_NUM]
1218 [CHANNEL_MAX_NUMBER_2G]
1219 [MAX_RF_PATH_NUM];
1220 char txpwr_limit_5g[MAX_REGULATION_NUM]
1221 [MAX_5G_BANDWITH_NUM]
1222 [MAX_RATE_SECTION_NUM]
1223 [CHANNEL_MAX_NUMBER_5G]
1224 [MAX_RF_PATH_NUM];
1225
1185 u32 rfreg_chnlval[2]; 1226 u32 rfreg_chnlval[2];
1186 bool apk_done; 1227 bool apk_done;
1187 u32 reg_rf3c[2]; /* pathA / pathB */ 1228 u32 reg_rf3c[2]; /* pathA / pathB */
@@ -1425,6 +1466,18 @@ struct rtl_hal {
1425 u32 version; /*version of chip */ 1466 u32 version; /*version of chip */
1426 u8 state; /*stop 0, start 1 */ 1467 u8 state; /*stop 0, start 1 */
1427 u8 board_type; 1468 u8 board_type;
1469 u8 external_pa;
1470
1471 u8 pa_mode;
1472 u8 pa_type_2g;
1473 u8 pa_type_5g;
1474 u8 lna_type_2g;
1475 u8 lna_type_5g;
1476 u8 external_pa_2g;
1477 u8 external_lna_2g;
1478 u8 external_pa_5g;
1479 u8 external_lna_5g;
1480 u8 rfe_type;
1428 1481
1429 /*firmware */ 1482 /*firmware */
1430 u32 fwsize; 1483 u32 fwsize;
@@ -1884,12 +1937,14 @@ struct rtl_stats {
1884 u16 wakeup:1; 1937 u16 wakeup:1;
1885 u32 timestamp_low; 1938 u32 timestamp_low;
1886 u32 timestamp_high; 1939 u32 timestamp_high;
1940 bool shift;
1887 1941
1888 u8 rx_drvinfo_size; 1942 u8 rx_drvinfo_size;
1889 u8 rx_bufshift; 1943 u8 rx_bufshift;
1890 bool isampdu; 1944 bool isampdu;
1891 bool isfirst_ampdu; 1945 bool isfirst_ampdu;
1892 bool rx_is40Mhzpacket; 1946 bool rx_is40Mhzpacket;
1947 u8 rx_packet_bw;
1893 u32 rx_pwdb_all; 1948 u32 rx_pwdb_all;
1894 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 1949 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1895 s8 rx_mimo_signalquality[4]; 1950 s8 rx_mimo_signalquality[4];
@@ -1900,6 +1955,8 @@ struct rtl_stats {
1900 s8 rx_mimo_sig_qual[4]; 1955 s8 rx_mimo_sig_qual[4];
1901 u8 rx_pwr[4]; /* per-path's pwdb */ 1956 u8 rx_pwr[4]; /* per-path's pwdb */
1902 u8 rx_snr[4]; /* per-path's SNR */ 1957 u8 rx_snr[4]; /* per-path's SNR */
1958 u8 bandwidth;
1959 u8 bt_coex_pwr_adjust;
1903 bool packet_matchbssid; 1960 bool packet_matchbssid;
1904 bool is_cck; 1961 bool is_cck;
1905 bool is_ht; 1962 bool is_ht;
@@ -1907,6 +1964,10 @@ struct rtl_stats {
1907 bool packet_beacon; /*for rssi */ 1964 bool packet_beacon; /*for rssi */
1908 char cck_adc_pwdb[4]; /*for rx path selection */ 1965 char cck_adc_pwdb[4]; /*for rx path selection */
1909 1966
1967 bool is_vht;
1968 bool is_short_gi;
1969 u8 vht_nss;
1970
1910 u8 packet_report_type; 1971 u8 packet_report_type;
1911 1972
1912 u32 macid; 1973 u32 macid;
@@ -2447,6 +2508,8 @@ struct proxim {
2447 2508
2448struct rtl_priv { 2509struct rtl_priv {
2449 struct ieee80211_hw *hw; 2510 struct ieee80211_hw *hw;
2511 /* Used to load a second firmware */
2512 void (*rtl_fw_second_cb)(struct rtl_priv *rtlpriv);
2450 struct completion firmware_loading_complete; 2513 struct completion firmware_loading_complete;
2451 struct list_head list; 2514 struct list_head list;
2452 struct rtl_priv *buddy_priv; 2515 struct rtl_priv *buddy_priv;
@@ -2773,6 +2836,26 @@ value to host byte ordering.*/
2773 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 2836 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2774 (des)[4] = (src)[4], (des)[5] = (src)[5]) 2837 (des)[4] = (src)[4], (des)[5] = (src)[5])
2775 2838
2839#define LDPC_HT_ENABLE_RX BIT(0)
2840#define LDPC_HT_ENABLE_TX BIT(1)
2841#define LDPC_HT_TEST_TX_ENABLE BIT(2)
2842#define LDPC_HT_CAP_TX BIT(3)
2843
2844#define STBC_HT_ENABLE_RX BIT(0)
2845#define STBC_HT_ENABLE_TX BIT(1)
2846#define STBC_HT_TEST_TX_ENABLE BIT(2)
2847#define STBC_HT_CAP_TX BIT(3)
2848
2849#define LDPC_VHT_ENABLE_RX BIT(0)
2850#define LDPC_VHT_ENABLE_TX BIT(1)
2851#define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2852#define LDPC_VHT_CAP_TX BIT(3)
2853
2854#define STBC_VHT_ENABLE_RX BIT(0)
2855#define STBC_VHT_ENABLE_TX BIT(1)
2856#define STBC_VHT_TEST_TX_ENABLE BIT(2)
2857#define STBC_VHT_CAP_TX BIT(3)
2858
2776static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 2859static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2777{ 2860{
2778 return rtlpriv->io.read8_sync(rtlpriv, addr); 2861 return rtlpriv->io.read8_sync(rtlpriv, addr);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 18:28:22 -0500