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-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/acenic.c1
-rw-r--r--drivers/net/arm/ixp4xx_eth.c6
-rw-r--r--drivers/net/atl1e/atl1e_ethtool.c2
-rw-r--r--drivers/net/au1000_eth.c2
-rw-r--r--drivers/net/ax88796.c4
-rw-r--r--drivers/net/bnx2.c47
-rw-r--r--drivers/net/bnx2x.h87
-rw-r--r--drivers/net/bnx2x_fw_defs.h160
-rw-r--r--drivers/net/bnx2x_hsi.h16
-rw-r--r--drivers/net/bnx2x_init.h26
-rw-r--r--drivers/net/bnx2x_init_values.h533
-rw-r--r--drivers/net/bnx2x_link.c1259
-rw-r--r--drivers/net/bnx2x_link.h11
-rw-r--r--drivers/net/bnx2x_main.c1213
-rw-r--r--drivers/net/bnx2x_reg.h210
-rw-r--r--drivers/net/cpmac.c1
-rw-r--r--drivers/net/e1000e/defines.h2
-rw-r--r--drivers/net/e1000e/e1000.h1
-rw-r--r--drivers/net/e1000e/ethtool.c2
-rw-r--r--drivers/net/e1000e/netdev.c185
-rw-r--r--drivers/net/e1000e/param.c25
-rw-r--r--drivers/net/gianfar.c6
-rw-r--r--drivers/net/gianfar_sysfs.c1
-rw-r--r--drivers/net/ipg.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c1
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c4
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h1
-rw-r--r--drivers/net/loopback.c67
-rw-r--r--drivers/net/myri10ge/myri10ge.c7
-rw-r--r--drivers/net/ne.c4
-rw-r--r--drivers/net/netxen/netxen_nic.h8
-rw-r--r--drivers/net/netxen/netxen_nic_ethtool.c1
-rw-r--r--drivers/net/netxen/netxen_nic_hdr.h2
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c59
-rw-r--r--drivers/net/netxen/netxen_nic_init.c28
-rw-r--r--drivers/net/netxen/netxen_nic_main.c210
-rw-r--r--drivers/net/netxen/netxen_nic_phan_reg.h2
-rw-r--r--drivers/net/ppp_mppe.c1
-rw-r--r--drivers/net/pppol2tp.c1
-rw-r--r--drivers/net/r6040.c1
-rw-r--r--drivers/net/sh_eth.c1
-rw-r--r--drivers/net/sky2.c8
-rw-r--r--drivers/net/tehuti.h1
-rw-r--r--drivers/net/tg3.c101
-rw-r--r--drivers/net/tg3.h6
-rw-r--r--drivers/net/tlan.c8
-rw-r--r--drivers/net/tokenring/lanstreamer.c1
-rw-r--r--drivers/net/tokenring/lanstreamer.h2
-rw-r--r--drivers/net/tun.c105
-rw-r--r--drivers/net/typhoon.c1
-rw-r--r--drivers/net/usb/Kconfig21
-rw-r--r--drivers/net/usb/hso.c53
-rw-r--r--drivers/net/wireless/ath5k/base.c9
-rw-r--r--drivers/net/wireless/ath9k/hw.c6
-rw-r--r--drivers/net/wireless/b43/main.c3
-rw-r--r--drivers/net/wireless/b43legacy/main.c1
-rw-r--r--drivers/net/wireless/ipw2100.c1
-rw-r--r--drivers/net/wireless/ipw2200.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-led.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c7
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-hcmd.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-led.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-power.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rfkill.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sta.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-tx.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c7
-rw-r--r--drivers/net/wireless/p54/p54common.c51
-rw-r--r--drivers/net/wireless/p54/p54common.h18
-rw-r--r--drivers/net/wireless/p54/p54usb.c10
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h8
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c1
-rw-r--r--drivers/net/wireless/rtl8187_dev.c1
79 files changed, 2747 insertions, 1906 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4b4cb2bf4f11..a5c141cecd4e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1172,7 +1172,7 @@ config ETH16I
1172 1172
1173config NE2000 1173config NE2000
1174 tristate "NE2000/NE1000 support" 1174 tristate "NE2000/NE1000 support"
1175 depends on NET_ISA || (Q40 && m) || M32R || TOSHIBA_RBTX4927 || TOSHIBA_RBTX4938 1175 depends on NET_ISA || (Q40 && m) || M32R || MACH_TX49XX
1176 select CRC32 1176 select CRC32
1177 ---help--- 1177 ---help---
1178 If you have a network (Ethernet) card of this type, say Y and read 1178 If you have a network (Ethernet) card of this type, say Y and read
diff --git a/drivers/net/acenic.c b/drivers/net/acenic.c
index e4483de84e7f..66de80b64b92 100644
--- a/drivers/net/acenic.c
+++ b/drivers/net/acenic.c
@@ -52,7 +52,6 @@
52 52
53#include <linux/module.h> 53#include <linux/module.h>
54#include <linux/moduleparam.h> 54#include <linux/moduleparam.h>
55#include <linux/version.h>
56#include <linux/types.h> 55#include <linux/types.h>
57#include <linux/errno.h> 56#include <linux/errno.h>
58#include <linux/ioport.h> 57#include <linux/ioport.h>
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 020771bfb603..e2d702b8b2e4 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -551,7 +551,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
551 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { 551 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
552 phys = dma_map_single(&dev->dev, skb->data, 552 phys = dma_map_single(&dev->dev, skb->data,
553 RX_BUFF_SIZE, DMA_FROM_DEVICE); 553 RX_BUFF_SIZE, DMA_FROM_DEVICE);
554 if (dma_mapping_error(phys)) { 554 if (dma_mapping_error(&dev->dev, phys)) {
555 dev_kfree_skb(skb); 555 dev_kfree_skb(skb);
556 skb = NULL; 556 skb = NULL;
557 } 557 }
@@ -698,7 +698,7 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
698#endif 698#endif
699 699
700 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 700 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
701 if (dma_mapping_error(phys)) { 701 if (dma_mapping_error(&dev->dev, phys)) {
702#ifdef __ARMEB__ 702#ifdef __ARMEB__
703 dev_kfree_skb(skb); 703 dev_kfree_skb(skb);
704#else 704#else
@@ -883,7 +883,7 @@ static int init_queues(struct port *port)
883 desc->buf_len = MAX_MRU; 883 desc->buf_len = MAX_MRU;
884 desc->data = dma_map_single(&port->netdev->dev, data, 884 desc->data = dma_map_single(&port->netdev->dev, data,
885 RX_BUFF_SIZE, DMA_FROM_DEVICE); 885 RX_BUFF_SIZE, DMA_FROM_DEVICE);
886 if (dma_mapping_error(desc->data)) { 886 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
887 free_buffer(buff); 887 free_buffer(buff);
888 return -EIO; 888 return -EIO;
889 } 889 }
diff --git a/drivers/net/atl1e/atl1e_ethtool.c b/drivers/net/atl1e/atl1e_ethtool.c
index cdc3b85b10b9..619c6583e1aa 100644
--- a/drivers/net/atl1e/atl1e_ethtool.c
+++ b/drivers/net/atl1e/atl1e_ethtool.c
@@ -355,7 +355,7 @@ static int atl1e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
355 struct atl1e_adapter *adapter = netdev_priv(netdev); 355 struct atl1e_adapter *adapter = netdev_priv(netdev);
356 356
357 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | 357 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
358 WAKE_MCAST | WAKE_BCAST | WAKE_MCAST)) 358 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
359 return -EOPNOTSUPP; 359 return -EOPNOTSUPP;
360 /* these settings will always override what we currently have */ 360 /* these settings will always override what we currently have */
361 adapter->wol = 0; 361 adapter->wol = 0;
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index cb8be490e5ae..5ee1b0557a02 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -807,7 +807,7 @@ err_out:
807static int au1000_init(struct net_device *dev) 807static int au1000_init(struct net_device *dev)
808{ 808{
809 struct au1000_private *aup = (struct au1000_private *) dev->priv; 809 struct au1000_private *aup = (struct au1000_private *) dev->priv;
810 u32 flags; 810 unsigned long flags;
811 int i; 811 int i;
812 u32 control; 812 u32 control;
813 813
diff --git a/drivers/net/ax88796.c b/drivers/net/ax88796.c
index 0b4adf4a0f7d..a886a4b9f7e5 100644
--- a/drivers/net/ax88796.c
+++ b/drivers/net/ax88796.c
@@ -554,7 +554,7 @@ static int ax_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
554 554
555 spin_lock_irqsave(&ax->mii_lock, flags); 555 spin_lock_irqsave(&ax->mii_lock, flags);
556 mii_ethtool_gset(&ax->mii, cmd); 556 mii_ethtool_gset(&ax->mii, cmd);
557 spin_lock_irqsave(&ax->mii_lock, flags); 557 spin_unlock_irqrestore(&ax->mii_lock, flags);
558 558
559 return 0; 559 return 0;
560} 560}
@@ -567,7 +567,7 @@ static int ax_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
567 567
568 spin_lock_irqsave(&ax->mii_lock, flags); 568 spin_lock_irqsave(&ax->mii_lock, flags);
569 rc = mii_ethtool_sset(&ax->mii, cmd); 569 rc = mii_ethtool_sset(&ax->mii, cmd);
570 spin_lock_irqsave(&ax->mii_lock, flags); 570 spin_unlock_irqrestore(&ax->mii_lock, flags);
571 571
572 return rc; 572 return rc;
573} 573}
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 5ebde67d4297..2486a656f12d 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -35,8 +35,8 @@
35#include <linux/time.h> 35#include <linux/time.h>
36#include <linux/ethtool.h> 36#include <linux/ethtool.h>
37#include <linux/mii.h> 37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h> 38#include <linux/if_vlan.h>
39#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40#define BCM_VLAN 1 40#define BCM_VLAN 1
41#endif 41#endif
42#include <net/ip.h> 42#include <net/ip.h>
@@ -57,8 +57,8 @@
57 57
58#define DRV_MODULE_NAME "bnx2" 58#define DRV_MODULE_NAME "bnx2"
59#define PFX DRV_MODULE_NAME ": " 59#define PFX DRV_MODULE_NAME ": "
60#define DRV_MODULE_VERSION "1.7.9" 60#define DRV_MODULE_VERSION "1.8.0"
61#define DRV_MODULE_RELDATE "July 18, 2008" 61#define DRV_MODULE_RELDATE "Aug 14, 2008"
62 62
63#define RUN_AT(x) (jiffies + (x)) 63#define RUN_AT(x) (jiffies + (x))
64 64
@@ -2876,6 +2876,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2876 struct sw_bd *rx_buf; 2876 struct sw_bd *rx_buf;
2877 struct sk_buff *skb; 2877 struct sk_buff *skb;
2878 dma_addr_t dma_addr; 2878 dma_addr_t dma_addr;
2879 u16 vtag = 0;
2880 int hw_vlan __maybe_unused = 0;
2879 2881
2880 sw_ring_cons = RX_RING_IDX(sw_cons); 2882 sw_ring_cons = RX_RING_IDX(sw_cons);
2881 sw_ring_prod = RX_RING_IDX(sw_prod); 2883 sw_ring_prod = RX_RING_IDX(sw_prod);
@@ -2919,7 +2921,7 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2919 if (len <= bp->rx_copy_thresh) { 2921 if (len <= bp->rx_copy_thresh) {
2920 struct sk_buff *new_skb; 2922 struct sk_buff *new_skb;
2921 2923
2922 new_skb = netdev_alloc_skb(bp->dev, len + 2); 2924 new_skb = netdev_alloc_skb(bp->dev, len + 6);
2923 if (new_skb == NULL) { 2925 if (new_skb == NULL) {
2924 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, 2926 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2925 sw_ring_prod); 2927 sw_ring_prod);
@@ -2928,9 +2930,9 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2928 2930
2929 /* aligned copy */ 2931 /* aligned copy */
2930 skb_copy_from_linear_data_offset(skb, 2932 skb_copy_from_linear_data_offset(skb,
2931 BNX2_RX_OFFSET - 2, 2933 BNX2_RX_OFFSET - 6,
2932 new_skb->data, len + 2); 2934 new_skb->data, len + 6);
2933 skb_reserve(new_skb, 2); 2935 skb_reserve(new_skb, 6);
2934 skb_put(new_skb, len); 2936 skb_put(new_skb, len);
2935 2937
2936 bnx2_reuse_rx_skb(bp, rxr, skb, 2938 bnx2_reuse_rx_skb(bp, rxr, skb,
@@ -2941,6 +2943,25 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2941 dma_addr, (sw_ring_cons << 16) | sw_ring_prod))) 2943 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2942 goto next_rx; 2944 goto next_rx;
2943 2945
2946 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2947 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2948 vtag = rx_hdr->l2_fhdr_vlan_tag;
2949#ifdef BCM_VLAN
2950 if (bp->vlgrp)
2951 hw_vlan = 1;
2952 else
2953#endif
2954 {
2955 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2956 __skb_push(skb, 4);
2957
2958 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2959 ve->h_vlan_proto = htons(ETH_P_8021Q);
2960 ve->h_vlan_TCI = htons(vtag);
2961 len += 4;
2962 }
2963 }
2964
2944 skb->protocol = eth_type_trans(skb, bp->dev); 2965 skb->protocol = eth_type_trans(skb, bp->dev);
2945 2966
2946 if ((len > (bp->dev->mtu + ETH_HLEN)) && 2967 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
@@ -2962,10 +2983,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2962 } 2983 }
2963 2984
2964#ifdef BCM_VLAN 2985#ifdef BCM_VLAN
2965 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) { 2986 if (hw_vlan)
2966 vlan_hwaccel_receive_skb(skb, bp->vlgrp, 2987 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
2967 rx_hdr->l2_fhdr_vlan_tag);
2968 }
2969 else 2988 else
2970#endif 2989#endif
2971 netif_receive_skb(skb); 2990 netif_receive_skb(skb);
@@ -3237,10 +3256,10 @@ bnx2_set_rx_mode(struct net_device *dev)
3237 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); 3256 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3238 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; 3257 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3239#ifdef BCM_VLAN 3258#ifdef BCM_VLAN
3240 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE)) 3259 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3241 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 3260 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3242#else 3261#else
3243 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) 3262 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3244 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 3263 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3245#endif 3264#endif
3246 if (dev->flags & IFF_PROMISC) { 3265 if (dev->flags & IFF_PROMISC) {
@@ -5963,10 +5982,12 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5963 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5982 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5964 } 5983 }
5965 5984
5985#ifdef BCM_VLAN
5966 if (bp->vlgrp && vlan_tx_tag_present(skb)) { 5986 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5967 vlan_tag_flags |= 5987 vlan_tag_flags |=
5968 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); 5988 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5969 } 5989 }
5990#endif
5970 if ((mss = skb_shinfo(skb)->gso_size)) { 5991 if ((mss = skb_shinfo(skb)->gso_size)) {
5971 u32 tcp_opt_len, ip_tcp_len; 5992 u32 tcp_opt_len, ip_tcp_len;
5972 struct iphdr *iph; 5993 struct iphdr *iph;
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 4bf4f7b205f2..b468f904c7f8 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -40,20 +40,20 @@
40#define DP(__mask, __fmt, __args...) do { \ 40#define DP(__mask, __fmt, __args...) do { \
41 if (bp->msglevel & (__mask)) \ 41 if (bp->msglevel & (__mask)) \
42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
43 bp->dev?(bp->dev->name):"?", ##__args); \ 43 bp->dev ? (bp->dev->name) : "?", ##__args); \
44 } while (0) 44 } while (0)
45 45
46/* errors debug print */ 46/* errors debug print */
47#define BNX2X_DBG_ERR(__fmt, __args...) do { \ 47#define BNX2X_DBG_ERR(__fmt, __args...) do { \
48 if (bp->msglevel & NETIF_MSG_PROBE) \ 48 if (bp->msglevel & NETIF_MSG_PROBE) \
49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
50 bp->dev?(bp->dev->name):"?", ##__args); \ 50 bp->dev ? (bp->dev->name) : "?", ##__args); \
51 } while (0) 51 } while (0)
52 52
53/* for errors (never masked) */ 53/* for errors (never masked) */
54#define BNX2X_ERR(__fmt, __args...) do { \ 54#define BNX2X_ERR(__fmt, __args...) do { \
55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
56 bp->dev?(bp->dev->name):"?", ##__args); \ 56 bp->dev ? (bp->dev->name) : "?", ##__args); \
57 } while (0) 57 } while (0)
58 58
59/* before we have a dev->name use dev_info() */ 59/* before we have a dev->name use dev_info() */
@@ -120,16 +120,8 @@
120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
122 122
123#define NIG_WR(reg, val) REG_WR(bp, reg, val) 123#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
124#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) 124#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
125#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
126
127
128#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
129
130#define for_each_nondefault_queue(bp, var) \
131 for (var = 1; var < bp->num_queues; var++)
132#define is_multi(bp) (bp->num_queues > 1)
133 125
134 126
135/* fast path */ 127/* fast path */
@@ -163,7 +155,7 @@ struct sw_rx_page {
163#define NUM_RX_SGE_PAGES 2 155#define NUM_RX_SGE_PAGES 2
164#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 156#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
165#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) 157#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
166/* RX_SGE_CNT is promissed to be a power of 2 */ 158/* RX_SGE_CNT is promised to be a power of 2 */
167#define RX_SGE_MASK (RX_SGE_CNT - 1) 159#define RX_SGE_MASK (RX_SGE_CNT - 1)
168#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 160#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
169#define MAX_RX_SGE (NUM_RX_SGE - 1) 161#define MAX_RX_SGE (NUM_RX_SGE - 1)
@@ -258,8 +250,7 @@ struct bnx2x_fastpath {
258 250
259 unsigned long tx_pkt, 251 unsigned long tx_pkt,
260 rx_pkt, 252 rx_pkt,
261 rx_calls, 253 rx_calls;
262 rx_alloc_failed;
263 /* TPA related */ 254 /* TPA related */
264 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; 255 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
265 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; 256 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
@@ -275,6 +266,15 @@ struct bnx2x_fastpath {
275 266
276#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 267#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
277 268
269#define BNX2X_HAS_TX_WORK(fp) \
270 ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
271 (fp->tx_pkt_prod != fp->tx_pkt_cons))
272
273#define BNX2X_HAS_RX_WORK(fp) \
274 (fp->rx_comp_cons != le16_to_cpu(*fp->rx_cons_sb))
275
276#define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
277
278 278
279/* MC hsi */ 279/* MC hsi */
280#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 280#define MAX_FETCH_BD 13 /* HW max BDs per packet */
@@ -317,7 +317,7 @@ struct bnx2x_fastpath {
317#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 317#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
318 318
319 319
320/* This is needed for determening of last_max */ 320/* This is needed for determining of last_max */
321#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 321#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
322 322
323#define __SGE_MASK_SET_BIT(el, bit) \ 323#define __SGE_MASK_SET_BIT(el, bit) \
@@ -386,20 +386,28 @@ struct bnx2x_fastpath {
386#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ 386#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
387 (TPA_TYPE_START | TPA_TYPE_END)) 387 (TPA_TYPE_START | TPA_TYPE_END))
388 388
389#define BNX2X_RX_SUM_OK(cqe) \ 389#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
390 (!(cqe->fast_path_cqe.status_flags & \ 390
391 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ 391#define BNX2X_IP_CSUM_ERR(cqe) \
392 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) 392 (!((cqe)->fast_path_cqe.status_flags & \
393 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
394 ((cqe)->fast_path_cqe.type_error_flags & \
395 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
396
397#define BNX2X_L4_CSUM_ERR(cqe) \
398 (!((cqe)->fast_path_cqe.status_flags & \
399 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
400 ((cqe)->fast_path_cqe.type_error_flags & \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
402
403#define BNX2X_RX_CSUM_OK(cqe) \
404 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
393 405
394#define BNX2X_RX_SUM_FIX(cqe) \ 406#define BNX2X_RX_SUM_FIX(cqe) \
395 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ 407 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
396 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ 408 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
397 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) 409 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
398 410
399#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
400 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
402
403 411
404#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) 412#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
405#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) 413#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
@@ -647,6 +655,8 @@ struct bnx2x_eth_stats {
647 655
648 u32 brb_drop_hi; 656 u32 brb_drop_hi;
649 u32 brb_drop_lo; 657 u32 brb_drop_lo;
658 u32 brb_truncate_hi;
659 u32 brb_truncate_lo;
650 660
651 u32 jabber_packets_received; 661 u32 jabber_packets_received;
652 662
@@ -663,6 +673,9 @@ struct bnx2x_eth_stats {
663 u32 mac_discard; 673 u32 mac_discard;
664 674
665 u32 driver_xoff; 675 u32 driver_xoff;
676 u32 rx_err_discard_pkt;
677 u32 rx_skb_alloc_failed;
678 u32 hw_csum_err;
666}; 679};
667 680
668#define STATS_OFFSET32(stat_name) \ 681#define STATS_OFFSET32(stat_name) \
@@ -753,7 +766,6 @@ struct bnx2x {
753 u16 def_att_idx; 766 u16 def_att_idx;
754 u32 attn_state; 767 u32 attn_state;
755 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 768 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
756 u32 aeu_mask;
757 u32 nig_mask; 769 u32 nig_mask;
758 770
759 /* slow path ring */ 771 /* slow path ring */
@@ -772,7 +784,7 @@ struct bnx2x {
772 u8 stats_pending; 784 u8 stats_pending;
773 u8 set_mac_pending; 785 u8 set_mac_pending;
774 786
775 /* End of fileds used in the performance code paths */ 787 /* End of fields used in the performance code paths */
776 788
777 int panic; 789 int panic;
778 int msglevel; 790 int msglevel;
@@ -794,9 +806,6 @@ struct bnx2x {
794#define BP_FUNC(bp) (bp->func) 806#define BP_FUNC(bp) (bp->func)
795#define BP_E1HVN(bp) (bp->func >> 1) 807#define BP_E1HVN(bp) (bp->func >> 1)
796#define BP_L_ID(bp) (BP_E1HVN(bp) << 2) 808#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
797/* assorted E1HVN */
798#define IS_E1HMF(bp) (bp->e1hmf != 0)
799#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
800 809
801 int pm_cap; 810 int pm_cap;
802 int pcie_cap; 811 int pcie_cap;
@@ -821,6 +830,7 @@ struct bnx2x {
821 u32 mf_config; 830 u32 mf_config;
822 u16 e1hov; 831 u16 e1hov;
823 u8 e1hmf; 832 u8 e1hmf;
833#define IS_E1HMF(bp) (bp->e1hmf != 0)
824 834
825 u8 wol; 835 u8 wol;
826 836
@@ -836,7 +846,6 @@ struct bnx2x {
836 u16 rx_ticks_int; 846 u16 rx_ticks_int;
837 u16 rx_ticks; 847 u16 rx_ticks;
838 848
839 u32 stats_ticks;
840 u32 lin_cnt; 849 u32 lin_cnt;
841 850
842 int state; 851 int state;
@@ -852,6 +861,7 @@ struct bnx2x {
852#define BNX2X_STATE_ERROR 0xf000 861#define BNX2X_STATE_ERROR 0xf000
853 862
854 int num_queues; 863 int num_queues;
864#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
855 865
856 u32 rx_mode; 866 u32 rx_mode;
857#define BNX2X_RX_MODE_NONE 0 867#define BNX2X_RX_MODE_NONE 0
@@ -902,10 +912,17 @@ struct bnx2x {
902}; 912};
903 913
904 914
915#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
916
917#define for_each_nondefault_queue(bp, var) \
918 for (var = 1; var < bp->num_queues; var++)
919#define is_multi(bp) (bp->num_queues > 1)
920
921
905void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 922void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
906void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 923void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
907 u32 len32); 924 u32 len32);
908int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); 925int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
909 926
910static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 927static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
911 int wait) 928 int wait)
@@ -976,7 +993,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
976#define PCICFG_LINK_SPEED_SHIFT 16 993#define PCICFG_LINK_SPEED_SHIFT 16
977 994
978 995
979#define BNX2X_NUM_STATS 39 996#define BNX2X_NUM_STATS 42
980#define BNX2X_NUM_TESTS 8 997#define BNX2X_NUM_TESTS 8
981 998
982#define BNX2X_MAC_LOOPBACK 0 999#define BNX2X_MAC_LOOPBACK 0
@@ -1007,10 +1024,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1007/* resolution of the rate shaping timer - 100 usec */ 1024/* resolution of the rate shaping timer - 100 usec */
1008#define RS_PERIODIC_TIMEOUT_USEC 100 1025#define RS_PERIODIC_TIMEOUT_USEC 100
1009/* resolution of fairness algorithm in usecs - 1026/* resolution of fairness algorithm in usecs -
1010 coefficient for clauclating the actuall t fair */ 1027 coefficient for calculating the actual t fair */
1011#define T_FAIR_COEF 10000000 1028#define T_FAIR_COEF 10000000
1012/* number of bytes in single QM arbitration cycle - 1029/* number of bytes in single QM arbitration cycle -
1013 coeffiecnt for calculating the fairness timer */ 1030 coefficient for calculating the fairness timer */
1014#define QM_ARB_BYTES 40000 1031#define QM_ARB_BYTES 40000
1015#define FAIR_MEM 2 1032#define FAIR_MEM 2
1016 1033
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
index e3da7f69d27b..192fa981b930 100644
--- a/drivers/net/bnx2x_fw_defs.h
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -9,165 +9,171 @@
9 9
10 10
11#define CSTORM_ASSERT_LIST_INDEX_OFFSET \ 11#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
12 (IS_E1H_OFFSET? 0x7000 : 0x1000) 12 (IS_E1H_OFFSET ? 0x7000 : 0x1000)
13#define CSTORM_ASSERT_LIST_OFFSET(idx) \ 13#define CSTORM_ASSERT_LIST_OFFSET(idx) \
14 (IS_E1H_OFFSET? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 14 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
16 (IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \ 16 (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
17 * 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \ 17 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
18 * 0x4))) 18 0x40) + (index * 0x4)))
19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
20 (IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \ 20 (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
21 * 0x100)) : (0x1900 + (function * 0x40))) 21 ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
23 (IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \ 23 (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
24 * 0x100)) : (0x1908 + (function * 0x40))) 24 ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
25#define CSTORM_FUNCTION_MODE_OFFSET \ 25#define CSTORM_FUNCTION_MODE_OFFSET \
26 (IS_E1H_OFFSET? 0x11e8 : 0xffffffff) 26 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
27#define CSTORM_HC_BTR_OFFSET(port) \ 27#define CSTORM_HC_BTR_OFFSET(port) \
28 (IS_E1H_OFFSET? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) 28 (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ 29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
30 (IS_E1H_OFFSET? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ 30 (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ 31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
32 (index * 0x4))) 32 (index * 0x4)))
33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ 33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
34 (IS_E1H_OFFSET? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ 34 (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ 35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
36 (index * 0x4))) 36 (index * 0x4)))
37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ 37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
38 (IS_E1H_OFFSET? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ 38 (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
39 (0x1400 + (port * 0x280) + (cpu_id * 0x28))) 39 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ 40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
41 (IS_E1H_OFFSET? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ 41 (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
42 (0x1408 + (port * 0x280) + (cpu_id * 0x28))) 42 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
43#define CSTORM_STATS_FLAGS_OFFSET(function) \ 43#define CSTORM_STATS_FLAGS_OFFSET(function) \
44 (IS_E1H_OFFSET? (0x1108 + (function * 0x8)) : (0x5108 + \ 44 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
45 (function * 0x8))) 45 (function * 0x8)))
46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ 46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47 (IS_E1H_OFFSET? (0x31c0 + (function * 0x20)) : 0xffffffff) 47 (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \ 48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49 (IS_E1H_OFFSET? 0xa000 : 0x1000) 49 (IS_E1H_OFFSET ? 0xa000 : 0x1000)
50#define TSTORM_ASSERT_LIST_OFFSET(idx) \ 50#define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (IS_E1H_OFFSET? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 51 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ 52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \ 53 (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \
54 (0x9c8 + (port * 0x2f8) + (client_id * 0x28))) 54 : (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
55#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 55#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
56 (IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \ 56 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
57 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \ 57 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
58 0x4))) 58 0x28) + (index * 0x4)))
59#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 59#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
60 (IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \ 60 (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
61 * 0xa0)) : (0x1400 + (function * 0x28))) 61 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
62#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 62#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
63 (IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \ 63 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
64 * 0xa0)) : (0x1408 + (function * 0x28))) 64 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
65#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 65#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
66 (IS_E1H_OFFSET? (0x2b80 + (function * 0x8)) : (0x4b68 + \ 66 (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
67 (function * 0x8))) 67 (function * 0x8)))
68#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ 68#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
69 (IS_E1H_OFFSET? (0x3000 + (function * 0x38)) : (0x1500 + \ 69 (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
70 (function * 0x38))) 70 (function * 0x38)))
71#define TSTORM_FUNCTION_MODE_OFFSET \ 71#define TSTORM_FUNCTION_MODE_OFFSET \
72 (IS_E1H_OFFSET? 0x1ad0 : 0xffffffff) 72 (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
73#define TSTORM_HC_BTR_OFFSET(port) \ 73#define TSTORM_HC_BTR_OFFSET(port) \
74 (IS_E1H_OFFSET? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) 74 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
75#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ 75#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
76 (IS_E1H_OFFSET? (0x12c8 + (function * 0x80)) : (0x22c8 + \ 76 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
77 (function * 0x80))) 77 (function * 0x80)))
78#define TSTORM_INDIRECTION_TABLE_SIZE 0x80 78#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
79#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ 79#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
80 (IS_E1H_OFFSET? (0x3008 + (function * 0x38)) : (0x1508 + \ 80 (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
81 (function * 0x38))) 81 (function * 0x38)))
82#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
83 (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
84 0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))
82#define TSTORM_RX_PRODS_OFFSET(port, client_id) \ 85#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
83 (IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \ 86 (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \
84 (0x9c0 + (port * 0x2f8) + (client_id * 0x28))) 87 : (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
85#define TSTORM_STATS_FLAGS_OFFSET(function) \ 88#define TSTORM_STATS_FLAGS_OFFSET(function) \
86 (IS_E1H_OFFSET? (0x2c00 + (function * 0x8)) : (0x4b88 + \ 89 (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
87 (function * 0x8))) 90 (function * 0x8)))
88#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET? 0x3b30 : 0x1c20) 91#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20)
89#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET? 0xa040 : 0x2c10) 92#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
90#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET? 0x2440 : 0x1200) 93#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
91#define USTORM_ASSERT_LIST_INDEX_OFFSET \ 94#define USTORM_ASSERT_LIST_INDEX_OFFSET \
92 (IS_E1H_OFFSET? 0x8000 : 0x1000) 95 (IS_E1H_OFFSET ? 0x8000 : 0x1000)
93#define USTORM_ASSERT_LIST_OFFSET(idx) \ 96#define USTORM_ASSERT_LIST_OFFSET(idx) \
94 (IS_E1H_OFFSET? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 97 (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
95#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ 98#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
96 (IS_E1H_OFFSET? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \ 99 (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
97 (0x5450 + (port * 0x1c8) + (clientId * 0x18))) 100 (0x5450 + (port * 0x1c8) + (clientId * 0x18)))
98#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 101#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
99 (IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \ 102 (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \
100 * 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \ 103 ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \
101 0x4))) 104 0x28) + (index * 0x4)))
102#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 105#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
103 (IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \ 106 (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \
104 * 0xa0)) : (0x1900 + (function * 0x28))) 107 ((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))
105#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 108#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
106 (IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \ 109 (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \
107 * 0xa0)) : (0x1908 + (function * 0x28))) 110 ((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))
108#define USTORM_FUNCTION_MODE_OFFSET \ 111#define USTORM_FUNCTION_MODE_OFFSET \
109 (IS_E1H_OFFSET? 0x2448 : 0xffffffff) 112 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
110#define USTORM_HC_BTR_OFFSET(port) \ 113#define USTORM_HC_BTR_OFFSET(port) \
111 (IS_E1H_OFFSET? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8))) 114 (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
112#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ 115#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
113 (IS_E1H_OFFSET? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \ 116 (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
114 (0x5448 + (port * 0x1c8) + (clientId * 0x18))) 117 (0x5448 + (port * 0x1c8) + (clientId * 0x18)))
115#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ 118#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
116 (IS_E1H_OFFSET? (0x2408 + (function * 0x8)) : (0x5408 + \ 119 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \
117 (function * 0x8))) 120 (function * 0x8)))
118#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ 121#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
119 (IS_E1H_OFFSET? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ 122 (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
120 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ 123 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
121 (index * 0x4))) 124 (index * 0x4)))
122#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ 125#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
123 (IS_E1H_OFFSET? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \ 126 (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
124 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ 127 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
125 (index * 0x4))) 128 (index * 0x4)))
126#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ 129#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
127 (IS_E1H_OFFSET? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \ 130 (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
128 (0x1400 + (port * 0x280) + (cpu_id * 0x28))) 131 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
129#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ 132#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
130 (IS_E1H_OFFSET? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \ 133 (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
131 (0x1408 + (port * 0x280) + (cpu_id * 0x28))) 134 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
132#define XSTORM_ASSERT_LIST_INDEX_OFFSET \ 135#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
133 (IS_E1H_OFFSET? 0x9000 : 0x1000) 136 (IS_E1H_OFFSET ? 0x9000 : 0x1000)
134#define XSTORM_ASSERT_LIST_OFFSET(idx) \ 137#define XSTORM_ASSERT_LIST_OFFSET(idx) \
135 (IS_E1H_OFFSET? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 138 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
136#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ 139#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
137 (IS_E1H_OFFSET? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40))) 140 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
138#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 141#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
139 (IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \ 142 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
140 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \ 143 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
141 0x4))) 144 0x28) + (index * 0x4)))
142#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 145#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
143 (IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \ 146 (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
144 * 0xa0)) : (0x1400 + (function * 0x28))) 147 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
145#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 148#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
146 (IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \ 149 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
147 * 0xa0)) : (0x1408 + (function * 0x28))) 150 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
148#define XSTORM_E1HOV_OFFSET(function) \ 151#define XSTORM_E1HOV_OFFSET(function) \
149 (IS_E1H_OFFSET? (0x2ab8 + (function * 0x2)) : 0xffffffff) 152 (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)
150#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 153#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
151 (IS_E1H_OFFSET? (0x2418 + (function * 0x8)) : (0x3b70 + \ 154 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
152 (function * 0x8))) 155 (function * 0x8)))
153#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ 156#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
154 (IS_E1H_OFFSET? (0x2568 + (function * 0x70)) : (0x3c60 + \ 157 (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \
155 (function * 0x70))) 158 (function * 0x70)))
156#define XSTORM_FUNCTION_MODE_OFFSET \ 159#define XSTORM_FUNCTION_MODE_OFFSET \
157 (IS_E1H_OFFSET? 0x2ac8 : 0xffffffff) 160 (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)
158#define XSTORM_HC_BTR_OFFSET(port) \ 161#define XSTORM_HC_BTR_OFFSET(port) \
159 (IS_E1H_OFFSET? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) 162 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
163#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
164 (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
165 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
160#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ 166#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
161 (IS_E1H_OFFSET? (0x2528 + (function * 0x70)) : (0x3c20 + \ 167 (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \
162 (function * 0x70))) 168 (function * 0x70)))
163#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ 169#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
164 (IS_E1H_OFFSET? (0x2000 + (function * 0x10)) : (0x3328 + \ 170 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
165 (function * 0x10))) 171 (function * 0x10)))
166#define XSTORM_SPQ_PROD_OFFSET(function) \ 172#define XSTORM_SPQ_PROD_OFFSET(function) \
167 (IS_E1H_OFFSET? (0x2008 + (function * 0x10)) : (0x3330 + \ 173 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
168 (function * 0x10))) 174 (function * 0x10)))
169#define XSTORM_STATS_FLAGS_OFFSET(function) \ 175#define XSTORM_STATS_FLAGS_OFFSET(function) \
170 (IS_E1H_OFFSET? (0x23d8 + (function * 0x8)) : (0x3b60 + \ 176 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
171 (function * 0x8))) 177 (function * 0x8)))
172#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 178#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
173 179
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index d3e8198d7dba..efd764427fa1 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -1268,7 +1268,7 @@ struct doorbell {
1268 1268
1269 1269
1270/* 1270/*
1271 * IGU driver acknowlegement register 1271 * IGU driver acknowledgement register
1272 */ 1272 */
1273struct igu_ack_register { 1273struct igu_ack_register {
1274#if defined(__BIG_ENDIAN) 1274#if defined(__BIG_ENDIAN)
@@ -1882,7 +1882,7 @@ struct timers_block_context {
1882}; 1882};
1883 1883
1884/* 1884/*
1885 * structure for easy accessability to assembler 1885 * structure for easy accessibility to assembler
1886 */ 1886 */
1887struct eth_tx_bd_flags { 1887struct eth_tx_bd_flags {
1888 u8 as_bitfield; 1888 u8 as_bitfield;
@@ -2044,7 +2044,7 @@ struct eth_context {
2044 2044
2045 2045
2046/* 2046/*
2047 * ethernet doorbell 2047 * Ethernet doorbell
2048 */ 2048 */
2049struct eth_tx_doorbell { 2049struct eth_tx_doorbell {
2050#if defined(__BIG_ENDIAN) 2050#if defined(__BIG_ENDIAN)
@@ -2256,7 +2256,7 @@ struct ramrod_data {
2256}; 2256};
2257 2257
2258/* 2258/*
2259 * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits) 2259 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2260 */ 2260 */
2261union eth_ramrod_data { 2261union eth_ramrod_data {
2262 struct ramrod_data general; 2262 struct ramrod_data general;
@@ -2330,7 +2330,7 @@ struct spe_hdr {
2330}; 2330};
2331 2331
2332/* 2332/*
2333 * ethernet slow path element 2333 * Ethernet slow path element
2334 */ 2334 */
2335union eth_specific_data { 2335union eth_specific_data {
2336 u8 protocol_data[8]; 2336 u8 protocol_data[8];
@@ -2343,7 +2343,7 @@ union eth_specific_data {
2343}; 2343};
2344 2344
2345/* 2345/*
2346 * ethernet slow path element 2346 * Ethernet slow path element
2347 */ 2347 */
2348struct eth_spe { 2348struct eth_spe {
2349 struct spe_hdr hdr; 2349 struct spe_hdr hdr;
@@ -2615,7 +2615,7 @@ struct tstorm_eth_rx_producers {
2615 2615
2616 2616
2617/* 2617/*
2618 * common flag to indicate existance of TPA. 2618 * common flag to indicate existence of TPA.
2619 */ 2619 */
2620struct tstorm_eth_tpa_exist { 2620struct tstorm_eth_tpa_exist {
2621#if defined(__BIG_ENDIAN) 2621#if defined(__BIG_ENDIAN)
@@ -2765,7 +2765,7 @@ struct tstorm_common_stats {
2765}; 2765};
2766 2766
2767/* 2767/*
2768 * Eth statistics query sturcture for the eth_stats_quesry ramrod 2768 * Eth statistics query structure for the eth_stats_query ramrod
2769 */ 2769 */
2770struct eth_stats_query { 2770struct eth_stats_query {
2771 struct xstorm_common_stats xstorm_common; 2771 struct xstorm_common_stats xstorm_common;
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 4c7750789b62..130927cfc75b 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -72,26 +72,26 @@
72 72
73 73
74struct raw_op { 74struct raw_op {
75 u32 op :8; 75 u32 op:8;
76 u32 offset :24; 76 u32 offset:24;
77 u32 raw_data; 77 u32 raw_data;
78}; 78};
79 79
80struct op_read { 80struct op_read {
81 u32 op :8; 81 u32 op:8;
82 u32 offset :24; 82 u32 offset:24;
83 u32 pad; 83 u32 pad;
84}; 84};
85 85
86struct op_write { 86struct op_write {
87 u32 op :8; 87 u32 op:8;
88 u32 offset :24; 88 u32 offset:24;
89 u32 val; 89 u32 val;
90}; 90};
91 91
92struct op_string_write { 92struct op_string_write {
93 u32 op :8; 93 u32 op:8;
94 u32 offset :24; 94 u32 offset:24;
95#ifdef __LITTLE_ENDIAN 95#ifdef __LITTLE_ENDIAN
96 u16 data_off; 96 u16 data_off;
97 u16 data_len; 97 u16 data_len;
@@ -102,8 +102,8 @@ struct op_string_write {
102}; 102};
103 103
104struct op_zero { 104struct op_zero {
105 u32 op :8; 105 u32 op:8;
106 u32 offset :24; 106 u32 offset:24;
107 u32 len; 107 u32 len;
108}; 108};
109 109
@@ -208,7 +208,7 @@ static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
208/********************************************************* 208/*********************************************************
209 There are different blobs for each PRAM section. 209 There are different blobs for each PRAM section.
210 In addition, each blob write operation is divided into a few operations 210 In addition, each blob write operation is divided into a few operations
211 in order to decrease the amount of phys. contigious buffer needed. 211 in order to decrease the amount of phys. contiguous buffer needed.
212 Thus, when we select a blob the address may be with some offset 212 Thus, when we select a blob the address may be with some offset
213 from the beginning of PRAM section. 213 from the beginning of PRAM section.
214 The same holds for the INT_TABLE sections. 214 The same holds for the INT_TABLE sections.
@@ -336,7 +336,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
336 len = op->str_wr.data_len; 336 len = op->str_wr.data_len;
337 data = data_base + op->str_wr.data_off; 337 data = data_base + op->str_wr.data_off;
338 338
339 /* carefull! it must be in order */ 339 /* careful! it must be in order */
340 if (unlikely(op_type > OP_WB)) { 340 if (unlikely(op_type > OP_WB)) {
341 341
342 /* If E1 only */ 342 /* If E1 only */
@@ -740,7 +740,7 @@ static u8 calc_crc8(u32 data, u8 crc)
740 return crc_res; 740 return crc_res;
741} 741}
742 742
743/* regiesers addresses are not in order 743/* registers addresses are not in order
744 so these arrays help simplify the code */ 744 so these arrays help simplify the code */
745static const int cm_start[E1H_FUNC_MAX][9] = { 745static const int cm_start[E1H_FUNC_MAX][9] = {
746 {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START, 746 {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h
index 63019055e4bb..9755bf6b08dd 100644
--- a/drivers/net/bnx2x_init_values.h
+++ b/drivers/net/bnx2x_init_values.h
@@ -901,31 +901,28 @@ static const struct raw_op init_ops[] = {
901 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4}, 901 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4},
902 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42}, 902 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42},
903 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9}, 903 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9},
904 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400}, 904 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
905 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293}, 905 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293},
906 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2}, 906 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x20278},
907 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42}, 907 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42},
908 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278}, 908 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
909 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400}, 909 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
910 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, 910 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027a},
911 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2}, 911 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
912 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a},
913 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294}, 912 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294},
914 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
915 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2}, 913 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
916 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c},
917 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296}, 914 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296},
918 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2}, 915 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
919 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298}, 916 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298},
920 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 917 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
921 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e}, 918 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027c},
922 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a}, 919 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a},
923 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, 920 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
924 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028e}, 921 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028c},
925 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa}, 922 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa},
926 {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000}, 923 {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000},
927 {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000}, 924 {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000},
928 {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e}, 925 {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029c},
929 {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba}, 926 {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba},
930 {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000}, 927 {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000},
931 {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000}, 928 {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000},
@@ -933,11 +930,11 @@ static const struct raw_op init_ops[] = {
933 {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42}, 930 {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42},
934 {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919}, 931 {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919},
935 {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906}, 932 {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906},
936 {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x500402a0}, 933 {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x5004029e},
937 {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d}, 934 {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d},
938 {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc}, 935 {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc},
939#define USEM_COMMON_END 790 936#define USEM_COMMON_END 787
940#define USEM_PORT0_START 790 937#define USEM_PORT0_START 787
941 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 938 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
942 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0}, 939 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0},
943 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, 940 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa},
@@ -950,44 +947,27 @@ static const struct raw_op init_ops[] = {
950 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96}, 947 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96},
951 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72}, 948 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72},
952 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20}, 949 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
953 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x20}, 950 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
954 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20}, 951 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
955 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3100, 0x20}, 952 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
956 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20}, 953 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
957 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3200, 0x20},
958 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20}, 954 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
959 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3300, 0x20},
960 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20}, 955 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
961 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3400, 0x20},
962 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20}, 956 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
963 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3500, 0x20},
964 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20}, 957 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
965 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3600, 0x20},
966 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20}, 958 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
967 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3700, 0x20},
968 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20}, 959 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
969 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3800, 0x20},
970 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20}, 960 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
971 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3900, 0x20},
972 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20}, 961 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
973 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a00, 0x20},
974 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20}, 962 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
975 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b00, 0x20},
976 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20}, 963 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
977 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c00, 0x20},
978 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20}, 964 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
979 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
980 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20}, 965 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
981 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e00, 0x20},
982 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20}, 966 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
983 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f00, 0x20},
984 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52}, 967 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
985 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c10, 0x2},
986 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc}, 968 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
987 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, 969#define USEM_PORT0_END 818
988 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, 970#define USEM_PORT1_START 818
989#define USEM_PORT0_END 838
990#define USEM_PORT1_START 838
991 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 971 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
992 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0}, 972 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0},
993 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, 973 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa},
@@ -1000,76 +980,59 @@ static const struct raw_op init_ops[] = {
1000 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96}, 980 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96},
1001 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72}, 981 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72},
1002 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20}, 982 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
1003 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3080, 0x20}, 983 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
1004 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20}, 984 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
1005 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3180, 0x20}, 985 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
1006 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20}, 986 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
1007 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3280, 0x20},
1008 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20}, 987 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
1009 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3380, 0x20},
1010 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20}, 988 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
1011 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3480, 0x20},
1012 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20}, 989 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
1013 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3580, 0x20},
1014 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20}, 990 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
1015 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3680, 0x20},
1016 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20}, 991 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
1017 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3780, 0x20},
1018 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20}, 992 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
1019 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3880, 0x20},
1020 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20}, 993 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
1021 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3980, 0x20},
1022 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20}, 994 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
1023 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a80, 0x20},
1024 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20}, 995 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
1025 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b80, 0x20},
1026 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20}, 996 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
1027 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c80, 0x20},
1028 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20}, 997 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
1029 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d80, 0x20},
1030 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20}, 998 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
1031 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e80, 0x20},
1032 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20}, 999 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
1033 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f80, 0x20},
1034 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52}, 1000 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
1035 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c20, 0x2},
1036 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc}, 1001 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
1037 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, 1002#define USEM_PORT1_END 849
1038 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, 1003#define USEM_FUNC0_START 849
1039#define USEM_PORT1_END 886
1040#define USEM_FUNC0_START 886
1041 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4}, 1004 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4},
1042 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2}, 1005 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
1043#define USEM_FUNC0_END 888 1006#define USEM_FUNC0_END 851
1044#define USEM_FUNC1_START 888 1007#define USEM_FUNC1_START 851
1045 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4}, 1008 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4},
1046 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2}, 1009 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
1047#define USEM_FUNC1_END 890 1010#define USEM_FUNC1_END 853
1048#define USEM_FUNC2_START 890 1011#define USEM_FUNC2_START 853
1049 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4}, 1012 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4},
1050 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2}, 1013 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
1051#define USEM_FUNC2_END 892 1014#define USEM_FUNC2_END 855
1052#define USEM_FUNC3_START 892 1015#define USEM_FUNC3_START 855
1053 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4}, 1016 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4},
1054 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2}, 1017 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
1055#define USEM_FUNC3_END 894 1018#define USEM_FUNC3_END 857
1056#define USEM_FUNC4_START 894 1019#define USEM_FUNC4_START 857
1057 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4}, 1020 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4},
1058 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2}, 1021 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
1059#define USEM_FUNC4_END 896 1022#define USEM_FUNC4_END 859
1060#define USEM_FUNC5_START 896 1023#define USEM_FUNC5_START 859
1061 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4}, 1024 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4},
1062 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2}, 1025 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
1063#define USEM_FUNC5_END 898 1026#define USEM_FUNC5_END 861
1064#define USEM_FUNC6_START 898 1027#define USEM_FUNC6_START 861
1065 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4}, 1028 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4},
1066 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2}, 1029 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
1067#define USEM_FUNC6_END 900 1030#define USEM_FUNC6_END 863
1068#define USEM_FUNC7_START 900 1031#define USEM_FUNC7_START 863
1069 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4}, 1032 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4},
1070 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2}, 1033 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
1071#define USEM_FUNC7_END 902 1034#define USEM_FUNC7_END 865
1072#define CSEM_COMMON_START 902 1035#define CSEM_COMMON_START 865
1073 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, 1036 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
1074 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, 1037 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
1075 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, 1038 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1128,29 +1091,29 @@ static const struct raw_op init_ops[] = {
1128 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0}, 1091 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
1129 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240}, 1092 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
1130 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0}, 1093 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
1131 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a2}, 1094 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a0},
1132 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80}, 1095 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
1133 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4}, 1096 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
1134 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240}, 1097 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240},
1135 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be}, 1098 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be},
1136 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, 1099 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
1137 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002aa}, 1100 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002a8},
1138 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de}, 1101 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de},
1139 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1102 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1140 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ba}, 1103 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002b8},
1141 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee}, 1104 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee},
1142 {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000}, 1105 {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000},
1143 {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000}, 1106 {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000},
1144 {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca}, 1107 {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002c8},
1145 {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe}, 1108 {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe},
1146 {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000}, 1109 {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000},
1147 {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000}, 1110 {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000},
1148 {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96}, 1111 {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96},
1149 {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f}, 1112 {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f},
1150 {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc}, 1113 {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402ca},
1151 {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300}, 1114 {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300},
1152#define CSEM_COMMON_END 981 1115#define CSEM_COMMON_END 944
1153#define CSEM_PORT0_START 981 1116#define CSEM_PORT0_START 944
1154 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 1117 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
1155 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0}, 1118 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0},
1156 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10}, 1119 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
@@ -1163,8 +1126,8 @@ static const struct raw_op init_ops[] = {
1163 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30}, 1126 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
1164 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6}, 1127 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
1165 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, 1128 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
1166#define CSEM_PORT0_END 993 1129#define CSEM_PORT0_END 956
1167#define CSEM_PORT1_START 993 1130#define CSEM_PORT1_START 956
1168 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 1131 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
1169 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0}, 1132 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0},
1170 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10}, 1133 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
@@ -1177,43 +1140,43 @@ static const struct raw_op init_ops[] = {
1177 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30}, 1140 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
1178 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6}, 1141 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
1179 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, 1142 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
1180#define CSEM_PORT1_END 1005 1143#define CSEM_PORT1_END 968
1181#define CSEM_FUNC0_START 1005 1144#define CSEM_FUNC0_START 968
1182 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0}, 1145 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
1183 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2}, 1146 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
1184#define CSEM_FUNC0_END 1007 1147#define CSEM_FUNC0_END 970
1185#define CSEM_FUNC1_START 1007 1148#define CSEM_FUNC1_START 970
1186 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0}, 1149 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
1187 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2}, 1150 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
1188#define CSEM_FUNC1_END 1009 1151#define CSEM_FUNC1_END 972
1189#define CSEM_FUNC2_START 1009 1152#define CSEM_FUNC2_START 972
1190 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0}, 1153 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
1191 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2}, 1154 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
1192#define CSEM_FUNC2_END 1011 1155#define CSEM_FUNC2_END 974
1193#define CSEM_FUNC3_START 1011 1156#define CSEM_FUNC3_START 974
1194 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0}, 1157 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
1195 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2}, 1158 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
1196#define CSEM_FUNC3_END 1013 1159#define CSEM_FUNC3_END 976
1197#define CSEM_FUNC4_START 1013 1160#define CSEM_FUNC4_START 976
1198 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0}, 1161 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
1199 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2}, 1162 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
1200#define CSEM_FUNC4_END 1015 1163#define CSEM_FUNC4_END 978
1201#define CSEM_FUNC5_START 1015 1164#define CSEM_FUNC5_START 978
1202 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0}, 1165 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
1203 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2}, 1166 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
1204#define CSEM_FUNC5_END 1017 1167#define CSEM_FUNC5_END 980
1205#define CSEM_FUNC6_START 1017 1168#define CSEM_FUNC6_START 980
1206 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0}, 1169 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
1207 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2}, 1170 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
1208#define CSEM_FUNC6_END 1019 1171#define CSEM_FUNC6_END 982
1209#define CSEM_FUNC7_START 1019 1172#define CSEM_FUNC7_START 982
1210 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0}, 1173 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
1211 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2}, 1174 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
1212#define CSEM_FUNC7_END 1021 1175#define CSEM_FUNC7_END 984
1213#define XPB_COMMON_START 1021 1176#define XPB_COMMON_START 984
1214 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20}, 1177 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
1215#define XPB_COMMON_END 1022 1178#define XPB_COMMON_END 985
1216#define DQ_COMMON_START 1022 1179#define DQ_COMMON_START 985
1217 {OP_WR, DORQ_REG_MODE_ACT, 0x2}, 1180 {OP_WR, DORQ_REG_MODE_ACT, 0x2},
1218 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, 1181 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
1219 {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, 1182 {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
@@ -1232,8 +1195,8 @@ static const struct raw_op init_ops[] = {
1232 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, 1195 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
1233 {OP_WR, DORQ_REG_REGN, 0x7c1004}, 1196 {OP_WR, DORQ_REG_REGN, 0x7c1004},
1234 {OP_WR, DORQ_REG_IF_EN, 0xf}, 1197 {OP_WR, DORQ_REG_IF_EN, 0xf},
1235#define DQ_COMMON_END 1040 1198#define DQ_COMMON_END 1003
1236#define TIMERS_COMMON_START 1040 1199#define TIMERS_COMMON_START 1003
1237 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, 1200 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
1238 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, 1201 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
1239 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, 1202 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
@@ -1256,14 +1219,14 @@ static const struct raw_op init_ops[] = {
1256 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, 1219 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
1257 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, 1220 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
1258 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, 1221 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
1259#define TIMERS_COMMON_END 1062 1222#define TIMERS_COMMON_END 1025
1260#define TIMERS_PORT0_START 1062 1223#define TIMERS_PORT0_START 1025
1261 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, 1224 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
1262#define TIMERS_PORT0_END 1063 1225#define TIMERS_PORT0_END 1026
1263#define TIMERS_PORT1_START 1063 1226#define TIMERS_PORT1_START 1026
1264 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, 1227 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
1265#define TIMERS_PORT1_END 1064 1228#define TIMERS_PORT1_END 1027
1266#define XSDM_COMMON_START 1064 1229#define XSDM_COMMON_START 1027
1267 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614}, 1230 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
1268 {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424}, 1231 {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
1269 {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600}, 1232 {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
@@ -1311,8 +1274,8 @@ static const struct raw_op init_ops[] = {
1311 {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8}, 1274 {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
1312 {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1}, 1275 {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
1313 {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa}, 1276 {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
1314#define XSDM_COMMON_END 1111 1277#define XSDM_COMMON_END 1074
1315#define QM_COMMON_START 1111 1278#define QM_COMMON_START 1074
1316 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, 1279 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
1317 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, 1280 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
1318 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, 1281 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
@@ -1613,8 +1576,8 @@ static const struct raw_op init_ops[] = {
1613 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5}, 1576 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5},
1614 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7}, 1577 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7},
1615 {OP_WR, QM_REG_CMINTEN, 0xff}, 1578 {OP_WR, QM_REG_CMINTEN, 0xff},
1616#define QM_COMMON_END 1411 1579#define QM_COMMON_END 1374
1617#define PBF_COMMON_START 1411 1580#define PBF_COMMON_START 1374
1618 {OP_WR, PBF_REG_INIT, 0x1}, 1581 {OP_WR, PBF_REG_INIT, 0x1},
1619 {OP_WR, PBF_REG_INIT_P4, 0x1}, 1582 {OP_WR, PBF_REG_INIT_P4, 0x1},
1620 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, 1583 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
@@ -1622,20 +1585,20 @@ static const struct raw_op init_ops[] = {
1622 {OP_WR, PBF_REG_INIT_P4, 0x0}, 1585 {OP_WR, PBF_REG_INIT_P4, 0x0},
1623 {OP_WR, PBF_REG_INIT, 0x0}, 1586 {OP_WR, PBF_REG_INIT, 0x0},
1624 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, 1587 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
1625#define PBF_COMMON_END 1418 1588#define PBF_COMMON_END 1381
1626#define PBF_PORT0_START 1418 1589#define PBF_PORT0_START 1381
1627 {OP_WR, PBF_REG_INIT_P0, 0x1}, 1590 {OP_WR, PBF_REG_INIT_P0, 0x1},
1628 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, 1591 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
1629 {OP_WR, PBF_REG_INIT_P0, 0x0}, 1592 {OP_WR, PBF_REG_INIT_P0, 0x0},
1630 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, 1593 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
1631#define PBF_PORT0_END 1422 1594#define PBF_PORT0_END 1385
1632#define PBF_PORT1_START 1422 1595#define PBF_PORT1_START 1385
1633 {OP_WR, PBF_REG_INIT_P1, 0x1}, 1596 {OP_WR, PBF_REG_INIT_P1, 0x1},
1634 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, 1597 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
1635 {OP_WR, PBF_REG_INIT_P1, 0x0}, 1598 {OP_WR, PBF_REG_INIT_P1, 0x0},
1636 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, 1599 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
1637#define PBF_PORT1_END 1426 1600#define PBF_PORT1_END 1389
1638#define XCM_COMMON_START 1426 1601#define XCM_COMMON_START 1389
1639 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, 1602 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
1640 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, 1603 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
1641 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, 1604 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
@@ -1670,7 +1633,7 @@ static const struct raw_op init_ops[] = {
1670 {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f}, 1633 {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f},
1671 {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20}, 1634 {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20},
1672 {OP_ZR, XCM_REG_XX_TABLE, 0x12}, 1635 {OP_ZR, XCM_REG_XX_TABLE, 0x12},
1673 {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02ce}, 1636 {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02cc},
1674 {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302}, 1637 {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302},
1675 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, 1638 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
1676 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, 1639 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
@@ -1700,8 +1663,8 @@ static const struct raw_op init_ops[] = {
1700 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, 1663 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
1701 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, 1664 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
1702 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, 1665 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
1703#define XCM_COMMON_END 1490 1666#define XCM_COMMON_END 1453
1704#define XCM_PORT0_START 1490 1667#define XCM_PORT0_START 1453
1705 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1668 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1706 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1669 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1707 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1670 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1710,8 +1673,8 @@ static const struct raw_op init_ops[] = {
1710 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2}, 1673 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1711 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1674 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1712 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1675 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1713#define XCM_PORT0_END 1498 1676#define XCM_PORT0_END 1461
1714#define XCM_PORT1_START 1498 1677#define XCM_PORT1_START 1461
1715 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1678 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1716 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1679 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1717 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1680 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1720,8 +1683,8 @@ static const struct raw_op init_ops[] = {
1720 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2}, 1683 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1721 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1684 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1722 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1685 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1723#define XCM_PORT1_END 1506 1686#define XCM_PORT1_END 1469
1724#define XCM_FUNC0_START 1506 1687#define XCM_FUNC0_START 1469
1725 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1688 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1726 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1689 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1727 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1690 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1731,8 +1694,8 @@ static const struct raw_op init_ops[] = {
1731 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1694 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1732 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1695 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1733 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1696 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1734#define XCM_FUNC0_END 1515 1697#define XCM_FUNC0_END 1478
1735#define XCM_FUNC1_START 1515 1698#define XCM_FUNC1_START 1478
1736 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1699 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1737 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1700 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1738 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1701 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1742,8 +1705,8 @@ static const struct raw_op init_ops[] = {
1742 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1705 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1743 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1706 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1744 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1707 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1745#define XCM_FUNC1_END 1524 1708#define XCM_FUNC1_END 1487
1746#define XCM_FUNC2_START 1524 1709#define XCM_FUNC2_START 1487
1747 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1710 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1748 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1711 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1749 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1712 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1753,8 +1716,8 @@ static const struct raw_op init_ops[] = {
1753 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1716 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1754 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1717 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1755 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1718 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1756#define XCM_FUNC2_END 1533 1719#define XCM_FUNC2_END 1496
1757#define XCM_FUNC3_START 1533 1720#define XCM_FUNC3_START 1496
1758 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1721 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1759 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1722 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1760 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1723 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1764,8 +1727,8 @@ static const struct raw_op init_ops[] = {
1764 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1727 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1765 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1728 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1766 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1729 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1767#define XCM_FUNC3_END 1542 1730#define XCM_FUNC3_END 1505
1768#define XCM_FUNC4_START 1542 1731#define XCM_FUNC4_START 1505
1769 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1732 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1770 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1733 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1771 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1734 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1775,8 +1738,8 @@ static const struct raw_op init_ops[] = {
1775 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1738 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1776 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1739 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1777 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1740 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1778#define XCM_FUNC4_END 1551 1741#define XCM_FUNC4_END 1514
1779#define XCM_FUNC5_START 1551 1742#define XCM_FUNC5_START 1514
1780 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1743 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1781 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1744 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1782 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1745 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1786,8 +1749,8 @@ static const struct raw_op init_ops[] = {
1786 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1749 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1787 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1750 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1788 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1751 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1789#define XCM_FUNC5_END 1560 1752#define XCM_FUNC5_END 1523
1790#define XCM_FUNC6_START 1560 1753#define XCM_FUNC6_START 1523
1791 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1754 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1792 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1755 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1793 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1756 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1797,8 +1760,8 @@ static const struct raw_op init_ops[] = {
1797 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1760 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1798 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1761 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1799 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1762 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1800#define XCM_FUNC6_END 1569 1763#define XCM_FUNC6_END 1532
1801#define XCM_FUNC7_START 1569 1764#define XCM_FUNC7_START 1532
1802 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1765 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1803 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1766 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1804 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1767 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1808,8 +1771,8 @@ static const struct raw_op init_ops[] = {
1808 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1771 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1809 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1772 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1810 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1773 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1811#define XCM_FUNC7_END 1578 1774#define XCM_FUNC7_END 1541
1812#define XSEM_COMMON_START 1578 1775#define XSEM_COMMON_START 1541
1813 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, 1776 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
1814 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, 1777 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
1815 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, 1778 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1876,9 +1839,9 @@ static const struct raw_op init_ops[] = {
1876 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2}, 1839 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
1877 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0}, 1840 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
1878 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86}, 1841 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
1879 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202ed}, 1842 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202eb},
1880 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20}, 1843 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
1881 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ef}, 1844 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ed},
1882 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0}, 1845 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
1883 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1}, 1846 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
1884 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321}, 1847 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321},
@@ -1886,29 +1849,29 @@ static const struct raw_op init_ops[] = {
1886 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323}, 1849 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323},
1887 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0}, 1850 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
1888 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0}, 1851 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0},
1889 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f3}, 1852 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f1},
1890 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0}, 1853 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0},
1891 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2}, 1854 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
1892 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1}, 1855 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1},
1893 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4}, 1856 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
1894 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10}, 1857 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
1895 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f5}, 1858 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f3},
1896 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327}, 1859 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327},
1897 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2}, 1860 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
1898 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4}, 1861 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
1899 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337}, 1862 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337},
1900 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1863 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1901 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f7}, 1864 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f5},
1902 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339}, 1865 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339},
1903 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 1866 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
1904 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80307}, 1867 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80305},
1905 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349}, 1868 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349},
1906 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, 1869 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
1907 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f}, 1870 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030d},
1908 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351}, 1871 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351},
1909 {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000}, 1872 {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000},
1910 {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000}, 1873 {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000},
1911 {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317}, 1874 {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130315},
1912 {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359}, 1875 {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359},
1913 {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000}, 1876 {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000},
1914 {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000}, 1877 {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000},
@@ -1918,10 +1881,10 @@ static const struct raw_op init_ops[] = {
1918 {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22}, 1881 {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22},
1919 {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2}, 1882 {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2},
1920 {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8}, 1883 {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8},
1921 {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60319}, 1884 {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60317},
1922 {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b}, 1885 {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b},
1923#define XSEM_COMMON_END 1688 1886#define XSEM_COMMON_END 1651
1924#define XSEM_PORT0_START 1688 1887#define XSEM_PORT0_START 1651
1925 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10}, 1888 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10},
1926 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc}, 1889 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc},
1927 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c}, 1890 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c},
@@ -1934,7 +1897,7 @@ static const struct raw_op init_ops[] = {
1934 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c}, 1897 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c},
1935 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0}, 1898 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0},
1936 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c}, 1899 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c},
1937 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x10031b}, 1900 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x100319},
1938 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28}, 1901 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
1939 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0}, 1902 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
1940 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc}, 1903 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
@@ -1950,12 +1913,12 @@ static const struct raw_op init_ops[] = {
1950 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d}, 1913 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d},
1951 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1}, 1914 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
1952 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42}, 1915 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
1953 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2032b}, 1916 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x20329},
1954 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4}, 1917 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
1955 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42}, 1918 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
1956 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4}, 1919 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
1957#define XSEM_PORT0_END 1720 1920#define XSEM_PORT0_END 1683
1958#define XSEM_PORT1_START 1720 1921#define XSEM_PORT1_START 1683
1959 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10}, 1922 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10},
1960 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc}, 1923 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc},
1961 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c}, 1924 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c},
@@ -1968,7 +1931,7 @@ static const struct raw_op init_ops[] = {
1968 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c}, 1931 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c},
1969 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0}, 1932 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0},
1970 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c}, 1933 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c},
1971 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032d}, 1934 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032b},
1972 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28}, 1935 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
1973 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0}, 1936 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
1974 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc}, 1937 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
@@ -1984,65 +1947,65 @@ static const struct raw_op init_ops[] = {
1984 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f}, 1947 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f},
1985 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1}, 1948 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
1986 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42}, 1949 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
1987 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033d}, 1950 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033b},
1988 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4}, 1951 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
1989 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42}, 1952 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
1990 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4}, 1953 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
1991#define XSEM_PORT1_END 1752 1954#define XSEM_PORT1_END 1715
1992#define XSEM_FUNC0_START 1752 1955#define XSEM_FUNC0_START 1715
1993 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0}, 1956 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0},
1994 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361}, 1957 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361},
1995 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, 1958 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1996#define XSEM_FUNC0_END 1755 1959#define XSEM_FUNC0_END 1718
1997#define XSEM_FUNC1_START 1755 1960#define XSEM_FUNC1_START 1718
1998 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0}, 1961 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0},
1999 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371}, 1962 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371},
2000 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, 1963 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
2001#define XSEM_FUNC1_END 1758 1964#define XSEM_FUNC1_END 1721
2002#define XSEM_FUNC2_START 1758 1965#define XSEM_FUNC2_START 1721
2003 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0}, 1966 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0},
2004 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381}, 1967 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381},
2005 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe}, 1968 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
2006#define XSEM_FUNC2_END 1761 1969#define XSEM_FUNC2_END 1724
2007#define XSEM_FUNC3_START 1761 1970#define XSEM_FUNC3_START 1724
2008 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0}, 1971 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0},
2009 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391}, 1972 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391},
2010 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe}, 1973 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
2011#define XSEM_FUNC3_END 1764 1974#define XSEM_FUNC3_END 1727
2012#define XSEM_FUNC4_START 1764 1975#define XSEM_FUNC4_START 1727
2013 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0}, 1976 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0},
2014 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1}, 1977 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1},
2015 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe}, 1978 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
2016#define XSEM_FUNC4_END 1767 1979#define XSEM_FUNC4_END 1730
2017#define XSEM_FUNC5_START 1767 1980#define XSEM_FUNC5_START 1730
2018 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0}, 1981 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0},
2019 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1}, 1982 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1},
2020 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe}, 1983 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
2021#define XSEM_FUNC5_END 1770 1984#define XSEM_FUNC5_END 1733
2022#define XSEM_FUNC6_START 1770 1985#define XSEM_FUNC6_START 1733
2023 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0}, 1986 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0},
2024 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1}, 1987 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1},
2025 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe}, 1988 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
2026#define XSEM_FUNC6_END 1773 1989#define XSEM_FUNC6_END 1736
2027#define XSEM_FUNC7_START 1773 1990#define XSEM_FUNC7_START 1736
2028 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0}, 1991 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0},
2029 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1}, 1992 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1},
2030 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe}, 1993 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
2031#define XSEM_FUNC7_END 1776 1994#define XSEM_FUNC7_END 1739
2032#define CDU_COMMON_START 1776 1995#define CDU_COMMON_START 1739
2033 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, 1996 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
2034 {OP_WR_E1H, CDU_REG_MF_MODE, 0x1}, 1997 {OP_WR_E1H, CDU_REG_MF_MODE, 0x1},
2035 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, 1998 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
2036 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, 1999 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
2037 {OP_WB_E1, CDU_REG_L1TT, 0x200033f}, 2000 {OP_WB_E1, CDU_REG_L1TT, 0x200033d},
2038 {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1}, 2001 {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1},
2039 {OP_WB_E1, CDU_REG_MATT, 0x20053f}, 2002 {OP_WB_E1, CDU_REG_MATT, 0x20053d},
2040 {OP_WB_E1H, CDU_REG_MATT, 0x2805e1}, 2003 {OP_WB_E1H, CDU_REG_MATT, 0x2805e1},
2041 {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2}, 2004 {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2},
2042 {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055f}, 2005 {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055d},
2043 {OP_ZR, CDU_REG_MATT + 0xa0, 0x18}, 2006 {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
2044#define CDU_COMMON_END 1787 2007#define CDU_COMMON_END 1750
2045#define DMAE_COMMON_START 1787 2008#define DMAE_COMMON_START 1750
2046 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0}, 2009 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
2047 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, 2010 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
2048 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, 2011 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
@@ -2050,24 +2013,24 @@ static const struct raw_op init_ops[] = {
2050 {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2}, 2013 {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
2051 {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, 2014 {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
2052 {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, 2015 {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
2053#define DMAE_COMMON_END 1794 2016#define DMAE_COMMON_END 1757
2054#define PXP_COMMON_START 1794 2017#define PXP_COMMON_START 1757
2055 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50565}, 2018 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50563},
2056 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609}, 2019 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609},
2057 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x5056a}, 2020 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x50568},
2058 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e}, 2021 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e},
2059 {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056f}, 2022 {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056d},
2060#define PXP_COMMON_END 1799 2023#define PXP_COMMON_END 1762
2061#define CFC_COMMON_START 1799 2024#define CFC_COMMON_START 1762
2062 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100}, 2025 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100},
2063 {OP_WR, CFC_REG_CONTROL0, 0x10}, 2026 {OP_WR, CFC_REG_CONTROL0, 0x10},
2064 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, 2027 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
2065 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, 2028 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
2066#define CFC_COMMON_END 1803 2029#define CFC_COMMON_END 1766
2067#define HC_COMMON_START 1803 2030#define HC_COMMON_START 1766
2068 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4}, 2031 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
2069#define HC_COMMON_END 1804 2032#define HC_COMMON_END 1767
2070#define HC_PORT0_START 1804 2033#define HC_PORT0_START 1767
2071 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080}, 2034 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
2072 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2}, 2035 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
2073 {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10}, 2036 {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2086,8 +2049,8 @@ static const struct raw_op init_ops[] = {
2086 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2049 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2087 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2050 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2088 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2051 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2089#define HC_PORT0_END 1822 2052#define HC_PORT0_END 1785
2090#define HC_PORT1_START 1822 2053#define HC_PORT1_START 1785
2091 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080}, 2054 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
2092 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2}, 2055 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
2093 {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10}, 2056 {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2106,8 +2069,8 @@ static const struct raw_op init_ops[] = {
2106 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2069 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2107 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2070 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2108 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2071 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2109#define HC_PORT1_END 1840 2072#define HC_PORT1_END 1803
2110#define HC_FUNC0_START 1840 2073#define HC_FUNC0_START 1803
2111 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2074 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2112 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0}, 2075 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
2113 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2076 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2123,8 +2086,8 @@ static const struct raw_op init_ops[] = {
2123 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2086 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2124 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2087 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2125 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2088 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2126#define HC_FUNC0_END 1855 2089#define HC_FUNC0_END 1818
2127#define HC_FUNC1_START 1855 2090#define HC_FUNC1_START 1818
2128 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2091 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2129 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1}, 2092 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
2130 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2093 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2140,8 +2103,8 @@ static const struct raw_op init_ops[] = {
2140 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2103 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2141 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2104 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2142 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2105 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2143#define HC_FUNC1_END 1870 2106#define HC_FUNC1_END 1833
2144#define HC_FUNC2_START 1870 2107#define HC_FUNC2_START 1833
2145 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2108 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2146 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2}, 2109 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
2147 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2110 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2157,8 +2120,8 @@ static const struct raw_op init_ops[] = {
2157 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2120 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2158 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2121 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2159 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2122 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2160#define HC_FUNC2_END 1885 2123#define HC_FUNC2_END 1848
2161#define HC_FUNC3_START 1885 2124#define HC_FUNC3_START 1848
2162 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2125 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2163 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3}, 2126 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
2164 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2127 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2174,8 +2137,8 @@ static const struct raw_op init_ops[] = {
2174 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2137 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2175 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2138 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2176 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2139 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2177#define HC_FUNC3_END 1900 2140#define HC_FUNC3_END 1863
2178#define HC_FUNC4_START 1900 2141#define HC_FUNC4_START 1863
2179 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2142 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2180 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4}, 2143 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
2181 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2144 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2191,8 +2154,8 @@ static const struct raw_op init_ops[] = {
2191 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2154 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2192 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2155 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2193 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2156 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2194#define HC_FUNC4_END 1915 2157#define HC_FUNC4_END 1878
2195#define HC_FUNC5_START 1915 2158#define HC_FUNC5_START 1878
2196 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2159 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2197 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5}, 2160 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
2198 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2161 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2208,8 +2171,8 @@ static const struct raw_op init_ops[] = {
2208 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2171 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2209 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2172 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2210 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2173 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2211#define HC_FUNC5_END 1930 2174#define HC_FUNC5_END 1893
2212#define HC_FUNC6_START 1930 2175#define HC_FUNC6_START 1893
2213 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2176 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2214 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6}, 2177 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
2215 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2178 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2225,8 +2188,8 @@ static const struct raw_op init_ops[] = {
2225 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2188 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2226 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2189 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2227 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2190 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2228#define HC_FUNC6_END 1945 2191#define HC_FUNC6_END 1908
2229#define HC_FUNC7_START 1945 2192#define HC_FUNC7_START 1908
2230 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2193 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2231 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7}, 2194 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
2232 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2195 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2242,8 +2205,8 @@ static const struct raw_op init_ops[] = {
2242 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2205 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2243 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2206 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2244 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2207 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2245#define HC_FUNC7_END 1960 2208#define HC_FUNC7_END 1923
2246#define PXP2_COMMON_START 1960 2209#define PXP2_COMMON_START 1923
2247 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340}, 2210 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340},
2248 {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1}, 2211 {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
2249 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, 2212 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
@@ -2361,8 +2324,8 @@ static const struct raw_op init_ops[] = {
2361 {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1}, 2324 {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1},
2362 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, 2325 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
2363 {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340}, 2326 {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340},
2364#define PXP2_COMMON_END 2077 2327#define PXP2_COMMON_END 2040
2365#define MISC_AEU_COMMON_START 2077 2328#define MISC_AEU_COMMON_START 2040
2366 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, 2329 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
2367 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, 2330 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
2368 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, 2331 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
@@ -2382,8 +2345,8 @@ static const struct raw_op init_ops[] = {
2382 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, 2345 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2383 {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00}, 2346 {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
2384 {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3}, 2347 {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3},
2385#define MISC_AEU_COMMON_END 2096 2348#define MISC_AEU_COMMON_END 2059
2386#define MISC_AEU_PORT0_START 2096 2349#define MISC_AEU_PORT0_START 2059
2387 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000}, 2350 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
2388 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000}, 2351 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
2389 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef}, 2352 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
@@ -2416,8 +2379,8 @@ static const struct raw_op init_ops[] = {
2416 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0}, 2379 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
2417 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3}, 2380 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
2418 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7}, 2381 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
2419#define MISC_AEU_PORT0_END 2128 2382#define MISC_AEU_PORT0_END 2091
2420#define MISC_AEU_PORT1_START 2128 2383#define MISC_AEU_PORT1_START 2091
2421 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000}, 2384 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
2422 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000}, 2385 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
2423 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef}, 2386 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
@@ -2450,7 +2413,7 @@ static const struct raw_op init_ops[] = {
2450 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0}, 2413 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
2451 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3}, 2414 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
2452 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7}, 2415 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
2453#define MISC_AEU_PORT1_END 2160 2416#define MISC_AEU_PORT1_END 2123
2454 2417
2455}; 2418};
2456 2419
@@ -2560,103 +2523,92 @@ static const u32 init_data_e1[] = {
2560 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 2523 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80,
2561 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 2524 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280,
2562 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 2525 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780,
2563 0x000ddb00, 0x00001900, 0x00000028, 0x00000000, 0x00100000, 0x00000000, 2526 0x000ddb00, 0x00001900, 0x00100000, 0x00000000, 0x00000000, 0xffffffff,
2564 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2565 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2527 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2566 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2528 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2567 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2529 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2568 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2530 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2569 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
2570 0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2571 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000,
2572 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2531 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2532 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500,
2533 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2534 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2573 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2535 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2574 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2536 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2575 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2537 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2576 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2538 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2577 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0x00001000, 0x00002080, 2539 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
2578 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380, 2540 0x00000000, 0x00003500, 0x00001000, 0x00002080, 0x00003100, 0x00004180,
2579 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 2541 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480,
2580 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980, 2542 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780,
2581 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 2543 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80,
2582 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 2544 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80,
2583 0x00010001, 0x00000604, 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, 2545 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001, 0x00000604,
2584 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 2546 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc, 0x00000000,
2547 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2585 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2548 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2586 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2549 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2587 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2550 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2588 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2551 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2589 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 2552 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000,
2590 0x00007ff8, 0x00000000, 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, 2553 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2591 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2554 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2555 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000,
2592 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2556 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2593 0x00000000, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2594 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2557 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2595 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2558 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000,
2596 0x00000000, 0x00100000, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 2559 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2597 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 2560 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c,
2598 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
2599 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2600 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
2601 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
2602 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
2603 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2604 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c,
2605 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
2606 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
2607 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2608 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
2609 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 2561 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
2610 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 2562 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
2611 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 2563 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
2612 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 2564 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
2613 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 2565 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
2614 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 2566 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
2615 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2567 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2616 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 2568 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c,
2617 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 2569 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
2618 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 2570 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
2619 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2571 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2620 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 2572 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
2621 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 2573 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
2622 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 2574 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
2623 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2575 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2624 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 2576 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
2625 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 2577 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7,
2626 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 2578 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c,
2627 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2579 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2628 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 2580 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c,
2629 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 2581 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
2630 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 2582 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
2631 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2583 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2632 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 2584 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
2633 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 2585 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
2634 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 2586 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
2635 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 2587 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2636 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 2588 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c,
2637 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 2589 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
2638 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 2590 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
2639 0xcdcdcdcd, 0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2591 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2640 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 2592 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
2641 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 2593 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
2642 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 2594 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
2643 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 2595 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
2644 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 2596 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
2645 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 2597 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a,
2646 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 2598 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c,
2647 0xcdcdcdcd, 0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 2599 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
2648 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 2600 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c,
2649 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 2601 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
2650 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 2602 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
2651 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2603 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2652 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2604 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
2653 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 2605 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
2654 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 2606 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
2655 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2607 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2656 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2608 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
2657 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 2609 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
2658 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 2610 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
2659 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2611 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2660 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2612 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2661 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 2613 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
2662 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 2614 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
@@ -2678,16 +2630,27 @@ static const u32 init_data_e1[] = {
2678 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 2630 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
2679 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2631 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2680 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2632 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2681 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 2633 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
2682 0x00070100, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 2634 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
2683 0x00010370, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 2635 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2684 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 2636 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2685 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 2637 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
2686 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 2638 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
2687 0x00080380, 0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 2639 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2688 0x00000118, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 2640 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2689 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 2641 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
2690 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000 2642 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
2643 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2644 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170,
2645 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 0x00010370, 0x00080000,
2646 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210,
2647 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250,
2648 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180,
2649 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x00028000,
2650 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118, 0xcccccccc,
2651 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc,
2652 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc,
2653 0xcccccccc, 0x00002000
2691}; 2654};
2692 2655
2693static const u32 init_data_e1h[] = { 2656static const u32 init_data_e1h[] = {
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index ff2743db10d9..4ce7fe9c5251 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -21,7 +21,6 @@
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/ethtool.h> 22#include <linux/ethtool.h>
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <linux/version.h>
25 24
26#include "bnx2x_reg.h" 25#include "bnx2x_reg.h"
27#include "bnx2x_fw_defs.h" 26#include "bnx2x_fw_defs.h"
@@ -31,17 +30,16 @@
31 30
32/********************************************************/ 31/********************************************************/
33#define SUPPORT_CL73 0 /* Currently no */ 32#define SUPPORT_CL73 0 /* Currently no */
34#define ETH_HLEN 14 33#define ETH_HLEN 14
35#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/ 34#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
36#define ETH_MIN_PACKET_SIZE 60 35#define ETH_MIN_PACKET_SIZE 60
37#define ETH_MAX_PACKET_SIZE 1500 36#define ETH_MAX_PACKET_SIZE 1500
38#define ETH_MAX_JUMBO_PACKET_SIZE 9600 37#define ETH_MAX_JUMBO_PACKET_SIZE 9600
39#define MDIO_ACCESS_TIMEOUT 1000 38#define MDIO_ACCESS_TIMEOUT 1000
40#define BMAC_CONTROL_RX_ENABLE 2 39#define BMAC_CONTROL_RX_ENABLE 2
41#define MAX_MTU_SIZE 5000
42 40
43/***********************************************************/ 41/***********************************************************/
44/* Shortcut definitions */ 42/* Shortcut definitions */
45/***********************************************************/ 43/***********************************************************/
46 44
47#define NIG_STATUS_XGXS0_LINK10G \ 45#define NIG_STATUS_XGXS0_LINK10G \
@@ -80,12 +78,12 @@
80 78
81#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 79#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
82#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 80#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
83#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 81#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
84#define AUTONEG_PARALLEL \ 82#define AUTONEG_PARALLEL \
85 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 83 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
86#define AUTONEG_SGMII_FIBER_AUTODET \ 84#define AUTONEG_SGMII_FIBER_AUTODET \
87 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 85 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
88#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 86#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
89 87
90#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 88#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
91 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 89 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
@@ -202,11 +200,10 @@ static void bnx2x_emac_init(struct link_params *params,
202 /* init emac - use read-modify-write */ 200 /* init emac - use read-modify-write */
203 /* self clear reset */ 201 /* self clear reset */
204 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 202 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
205 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 203 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
206 204
207 timeout = 200; 205 timeout = 200;
208 do 206 do {
209 {
210 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 207 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
211 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 208 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
212 if (!timeout) { 209 if (!timeout) {
@@ -214,18 +211,18 @@ static void bnx2x_emac_init(struct link_params *params,
214 return; 211 return;
215 } 212 }
216 timeout--; 213 timeout--;
217 }while (val & EMAC_MODE_RESET); 214 } while (val & EMAC_MODE_RESET);
218 215
219 /* Set mac address */ 216 /* Set mac address */
220 val = ((params->mac_addr[0] << 8) | 217 val = ((params->mac_addr[0] << 8) |
221 params->mac_addr[1]); 218 params->mac_addr[1]);
222 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val); 219 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
223 220
224 val = ((params->mac_addr[2] << 24) | 221 val = ((params->mac_addr[2] << 24) |
225 (params->mac_addr[3] << 16) | 222 (params->mac_addr[3] << 16) |
226 (params->mac_addr[4] << 8) | 223 (params->mac_addr[4] << 8) |
227 params->mac_addr[5]); 224 params->mac_addr[5]);
228 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val); 225 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
229} 226}
230 227
231static u8 bnx2x_emac_enable(struct link_params *params, 228static u8 bnx2x_emac_enable(struct link_params *params,
@@ -286,7 +283,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
286 if (CHIP_REV_IS_SLOW(bp)) { 283 if (CHIP_REV_IS_SLOW(bp)) {
287 /* config GMII mode */ 284 /* config GMII mode */
288 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 285 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
289 EMAC_WR(EMAC_REG_EMAC_MODE, 286 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
290 (val | EMAC_MODE_PORT_GMII)); 287 (val | EMAC_MODE_PORT_GMII));
291 } else { /* ASIC */ 288 } else { /* ASIC */
292 /* pause enable/disable */ 289 /* pause enable/disable */
@@ -298,17 +295,19 @@ static u8 bnx2x_emac_enable(struct link_params *params,
298 EMAC_RX_MODE_FLOW_EN); 295 EMAC_RX_MODE_FLOW_EN);
299 296
300 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 297 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
301 EMAC_TX_MODE_EXT_PAUSE_EN); 298 (EMAC_TX_MODE_EXT_PAUSE_EN |
299 EMAC_TX_MODE_FLOW_EN));
302 if (vars->flow_ctrl & FLOW_CTRL_TX) 300 if (vars->flow_ctrl & FLOW_CTRL_TX)
303 bnx2x_bits_en(bp, emac_base + 301 bnx2x_bits_en(bp, emac_base +
304 EMAC_REG_EMAC_TX_MODE, 302 EMAC_REG_EMAC_TX_MODE,
305 EMAC_TX_MODE_EXT_PAUSE_EN); 303 (EMAC_TX_MODE_EXT_PAUSE_EN |
304 EMAC_TX_MODE_FLOW_EN));
306 } 305 }
307 306
308 /* KEEP_VLAN_TAG, promiscuous */ 307 /* KEEP_VLAN_TAG, promiscuous */
309 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 308 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
310 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 309 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
311 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val); 310 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
312 311
313 /* Set Loopback */ 312 /* Set Loopback */
314 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 313 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
@@ -316,10 +315,10 @@ static u8 bnx2x_emac_enable(struct link_params *params,
316 val |= 0x810; 315 val |= 0x810;
317 else 316 else
318 val &= ~0x810; 317 val &= ~0x810;
319 EMAC_WR(EMAC_REG_EMAC_MODE, val); 318 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
320 319
321 /* enable emac for jumbo packets */ 320 /* enable emac for jumbo packets */
322 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE, 321 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
323 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 322 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
324 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 323 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
325 324
@@ -591,9 +590,9 @@ void bnx2x_link_status_update(struct link_params *params,
591 vars->flow_ctrl &= ~FLOW_CTRL_RX; 590 vars->flow_ctrl &= ~FLOW_CTRL_RX;
592 591
593 if (vars->phy_flags & PHY_XGXS_FLAG) { 592 if (vars->phy_flags & PHY_XGXS_FLAG) {
594 if (params->req_line_speed && 593 if (vars->line_speed &&
595 ((params->req_line_speed == SPEED_10) || 594 ((vars->line_speed == SPEED_10) ||
596 (params->req_line_speed == SPEED_100))) { 595 (vars->line_speed == SPEED_100))) {
597 vars->phy_flags |= PHY_SGMII_FLAG; 596 vars->phy_flags |= PHY_SGMII_FLAG;
598 } else { 597 } else {
599 vars->phy_flags &= ~PHY_SGMII_FLAG; 598 vars->phy_flags &= ~PHY_SGMII_FLAG;
@@ -645,7 +644,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
645 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 644 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
646 NIG_REG_INGRESS_BMAC0_MEM; 645 NIG_REG_INGRESS_BMAC0_MEM;
647 u32 wb_data[2]; 646 u32 wb_data[2];
648 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 647 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
649 648
650 /* Only if the bmac is out of reset */ 649 /* Only if the bmac is out of reset */
651 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 650 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
@@ -670,7 +669,6 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
670 u8 port = params->port; 669 u8 port = params->port;
671 u32 init_crd, crd; 670 u32 init_crd, crd;
672 u32 count = 1000; 671 u32 count = 1000;
673 u32 pause = 0;
674 672
675 /* disable port */ 673 /* disable port */
676 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 674 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
@@ -693,33 +691,25 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
693 return -EINVAL; 691 return -EINVAL;
694 } 692 }
695 693
696 if (flow_ctrl & FLOW_CTRL_RX) 694 if (flow_ctrl & FLOW_CTRL_RX ||
697 pause = 1; 695 line_speed == SPEED_10 ||
698 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause); 696 line_speed == SPEED_100 ||
699 if (pause) { 697 line_speed == SPEED_1000 ||
698 line_speed == SPEED_2500) {
699 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
700 /* update threshold */ 700 /* update threshold */
701 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 701 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
702 /* update init credit */ 702 /* update init credit */
703 init_crd = 778; /* (800-18-4) */ 703 init_crd = 778; /* (800-18-4) */
704 704
705 } else { 705 } else {
706 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 706 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
707 ETH_OVREHEAD)/16; 707 ETH_OVREHEAD)/16;
708 708 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
709 /* update threshold */ 709 /* update threshold */
710 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 710 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
711 /* update init credit */ 711 /* update init credit */
712 switch (line_speed) { 712 switch (line_speed) {
713 case SPEED_10:
714 case SPEED_100:
715 case SPEED_1000:
716 init_crd = thresh + 55 - 22;
717 break;
718
719 case SPEED_2500:
720 init_crd = thresh + 138 - 22;
721 break;
722
723 case SPEED_10000: 713 case SPEED_10000:
724 init_crd = thresh + 553 - 22; 714 init_crd = thresh + 553 - 22;
725 break; 715 break;
@@ -764,10 +754,10 @@ static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port)
764 emac_base = GRCBASE_EMAC0; 754 emac_base = GRCBASE_EMAC0;
765 break; 755 break;
766 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 756 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
767 emac_base = (port) ? GRCBASE_EMAC0: GRCBASE_EMAC1; 757 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
768 break; 758 break;
769 default: 759 default:
770 emac_base = (port) ? GRCBASE_EMAC1: GRCBASE_EMAC0; 760 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
771 break; 761 break;
772 } 762 }
773 return emac_base; 763 return emac_base;
@@ -1044,7 +1034,7 @@ static void bnx2x_set_swap_lanes(struct link_params *params)
1044} 1034}
1045 1035
1046static void bnx2x_set_parallel_detection(struct link_params *params, 1036static void bnx2x_set_parallel_detection(struct link_params *params,
1047 u8 phy_flags) 1037 u8 phy_flags)
1048{ 1038{
1049 struct bnx2x *bp = params->bp; 1039 struct bnx2x *bp = params->bp;
1050 u16 control2; 1040 u16 control2;
@@ -1114,7 +1104,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1114 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); 1104 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1115 1105
1116 /* CL37 Autoneg Enabled */ 1106 /* CL37 Autoneg Enabled */
1117 if (params->req_line_speed == SPEED_AUTO_NEG) 1107 if (vars->line_speed == SPEED_AUTO_NEG)
1118 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 1108 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1119 else /* CL37 Autoneg Disabled */ 1109 else /* CL37 Autoneg Disabled */
1120 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 1110 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
@@ -1132,7 +1122,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1132 MDIO_REG_BANK_SERDES_DIGITAL, 1122 MDIO_REG_BANK_SERDES_DIGITAL,
1133 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val); 1123 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1134 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN; 1124 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
1135 if (params->req_line_speed == SPEED_AUTO_NEG) 1125 if (vars->line_speed == SPEED_AUTO_NEG)
1136 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 1126 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1137 else 1127 else
1138 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 1128 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
@@ -1148,7 +1138,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1148 MDIO_REG_BANK_BAM_NEXT_PAGE, 1138 MDIO_REG_BANK_BAM_NEXT_PAGE,
1149 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 1139 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1150 &reg_val); 1140 &reg_val);
1151 if (params->req_line_speed == SPEED_AUTO_NEG) { 1141 if (vars->line_speed == SPEED_AUTO_NEG) {
1152 /* Enable BAM aneg Mode and TetonII aneg Mode */ 1142 /* Enable BAM aneg Mode and TetonII aneg Mode */
1153 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 1143 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1154 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 1144 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
@@ -1164,7 +1154,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1164 reg_val); 1154 reg_val);
1165 1155
1166 /* Enable Clause 73 Aneg */ 1156 /* Enable Clause 73 Aneg */
1167 if ((params->req_line_speed == SPEED_AUTO_NEG) && 1157 if ((vars->line_speed == SPEED_AUTO_NEG) &&
1168 (SUPPORT_CL73)) { 1158 (SUPPORT_CL73)) {
1169 /* Enable BAM Station Manager */ 1159 /* Enable BAM Station Manager */
1170 1160
@@ -1226,7 +1216,8 @@ static void bnx2x_set_autoneg(struct link_params *params,
1226} 1216}
1227 1217
1228/* program SerDes, forced speed */ 1218/* program SerDes, forced speed */
1229static void bnx2x_program_serdes(struct link_params *params) 1219static void bnx2x_program_serdes(struct link_params *params,
1220 struct link_vars *vars)
1230{ 1221{
1231 struct bnx2x *bp = params->bp; 1222 struct bnx2x *bp = params->bp;
1232 u16 reg_val; 1223 u16 reg_val;
@@ -1248,28 +1239,35 @@ static void bnx2x_program_serdes(struct link_params *params)
1248 1239
1249 /* program speed 1240 /* program speed
1250 - needed only if the speed is greater than 1G (2.5G or 10G) */ 1241 - needed only if the speed is greater than 1G (2.5G or 10G) */
1251 if (!((params->req_line_speed == SPEED_1000) || 1242 CL45_RD_OVER_CL22(bp, params->port,
1252 (params->req_line_speed == SPEED_100) ||
1253 (params->req_line_speed == SPEED_10))) {
1254 CL45_RD_OVER_CL22(bp, params->port,
1255 params->phy_addr, 1243 params->phy_addr,
1256 MDIO_REG_BANK_SERDES_DIGITAL, 1244 MDIO_REG_BANK_SERDES_DIGITAL,
1257 MDIO_SERDES_DIGITAL_MISC1, &reg_val); 1245 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
1258 /* clearing the speed value before setting the right speed */ 1246 /* clearing the speed value before setting the right speed */
1259 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK; 1247 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1248
1249 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1250 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1251
1252 if (!((vars->line_speed == SPEED_1000) ||
1253 (vars->line_speed == SPEED_100) ||
1254 (vars->line_speed == SPEED_10))) {
1255
1260 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 1256 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1261 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 1257 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1262 if (params->req_line_speed == SPEED_10000) 1258 if (vars->line_speed == SPEED_10000)
1263 reg_val |= 1259 reg_val |=
1264 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 1260 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1265 if (params->req_line_speed == SPEED_13000) 1261 if (vars->line_speed == SPEED_13000)
1266 reg_val |= 1262 reg_val |=
1267 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G; 1263 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1268 CL45_WR_OVER_CL22(bp, params->port, 1264 }
1265
1266 CL45_WR_OVER_CL22(bp, params->port,
1269 params->phy_addr, 1267 params->phy_addr,
1270 MDIO_REG_BANK_SERDES_DIGITAL, 1268 MDIO_REG_BANK_SERDES_DIGITAL,
1271 MDIO_SERDES_DIGITAL_MISC1, reg_val); 1269 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1272 } 1270
1273} 1271}
1274 1272
1275static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params) 1273static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
@@ -1295,48 +1293,49 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1295 MDIO_OVER_1G_UP3, 0); 1293 MDIO_OVER_1G_UP3, 0);
1296} 1294}
1297 1295
1298static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, 1296static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
1299 u32 *ieee_fc)
1300{ 1297{
1301 struct bnx2x *bp = params->bp; 1298 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1302 /* for AN, we are always publishing full duplex */
1303 u16 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1304
1305 /* resolve pause mode and advertisement 1299 /* resolve pause mode and advertisement
1306 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ 1300 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1307 1301
1308 switch (params->req_flow_ctrl) { 1302 switch (params->req_flow_ctrl) {
1309 case FLOW_CTRL_AUTO: 1303 case FLOW_CTRL_AUTO:
1310 if (params->mtu <= MAX_MTU_SIZE) { 1304 if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) {
1311 an_adv |= 1305 *ieee_fc |=
1312 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 1306 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1313 } else { 1307 } else {
1314 an_adv |= 1308 *ieee_fc |=
1315 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 1309 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1316 } 1310 }
1317 break; 1311 break;
1318 case FLOW_CTRL_TX: 1312 case FLOW_CTRL_TX:
1319 an_adv |= 1313 *ieee_fc |=
1320 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 1314 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1321 break; 1315 break;
1322 1316
1323 case FLOW_CTRL_RX: 1317 case FLOW_CTRL_RX:
1324 case FLOW_CTRL_BOTH: 1318 case FLOW_CTRL_BOTH:
1325 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 1319 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1326 break; 1320 break;
1327 1321
1328 case FLOW_CTRL_NONE: 1322 case FLOW_CTRL_NONE:
1329 default: 1323 default:
1330 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 1324 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1331 break; 1325 break;
1332 } 1326 }
1327}
1333 1328
1334 *ieee_fc = an_adv; 1329static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1330 u32 ieee_fc)
1331{
1332 struct bnx2x *bp = params->bp;
1333 /* for AN, we are always publishing full duplex */
1335 1334
1336 CL45_WR_OVER_CL22(bp, params->port, 1335 CL45_WR_OVER_CL22(bp, params->port,
1337 params->phy_addr, 1336 params->phy_addr,
1338 MDIO_REG_BANK_COMBO_IEEE0, 1337 MDIO_REG_BANK_COMBO_IEEE0,
1339 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv); 1338 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
1340} 1339}
1341 1340
1342static void bnx2x_restart_autoneg(struct link_params *params) 1341static void bnx2x_restart_autoneg(struct link_params *params)
@@ -1382,7 +1381,8 @@ static void bnx2x_restart_autoneg(struct link_params *params)
1382 } 1381 }
1383} 1382}
1384 1383
1385static void bnx2x_initialize_sgmii_process(struct link_params *params) 1384static void bnx2x_initialize_sgmii_process(struct link_params *params,
1385 struct link_vars *vars)
1386{ 1386{
1387 struct bnx2x *bp = params->bp; 1387 struct bnx2x *bp = params->bp;
1388 u16 control1; 1388 u16 control1;
@@ -1406,7 +1406,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1406 control1); 1406 control1);
1407 1407
1408 /* if forced speed */ 1408 /* if forced speed */
1409 if (!(params->req_line_speed == SPEED_AUTO_NEG)) { 1409 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
1410 /* set speed, disable autoneg */ 1410 /* set speed, disable autoneg */
1411 u16 mii_control; 1411 u16 mii_control;
1412 1412
@@ -1419,7 +1419,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1419 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 1419 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1420 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 1420 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1421 1421
1422 switch (params->req_line_speed) { 1422 switch (vars->line_speed) {
1423 case SPEED_100: 1423 case SPEED_100:
1424 mii_control |= 1424 mii_control |=
1425 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 1425 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
@@ -1433,8 +1433,8 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1433 break; 1433 break;
1434 default: 1434 default:
1435 /* invalid speed for SGMII */ 1435 /* invalid speed for SGMII */
1436 DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n", 1436 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1437 params->req_line_speed); 1437 vars->line_speed);
1438 break; 1438 break;
1439 } 1439 }
1440 1440
@@ -1460,20 +1460,20 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1460 */ 1460 */
1461 1461
1462static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 1462static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1463{ 1463{ /* LD LP */
1464 switch (pause_result) { /* ASYM P ASYM P */ 1464 switch (pause_result) { /* ASYM P ASYM P */
1465 case 0xb: /* 1 0 1 1 */ 1465 case 0xb: /* 1 0 1 1 */
1466 vars->flow_ctrl = FLOW_CTRL_TX; 1466 vars->flow_ctrl = FLOW_CTRL_TX;
1467 break; 1467 break;
1468 1468
1469 case 0xe: /* 1 1 1 0 */ 1469 case 0xe: /* 1 1 1 0 */
1470 vars->flow_ctrl = FLOW_CTRL_RX; 1470 vars->flow_ctrl = FLOW_CTRL_RX;
1471 break; 1471 break;
1472 1472
1473 case 0x5: /* 0 1 0 1 */ 1473 case 0x5: /* 0 1 0 1 */
1474 case 0x7: /* 0 1 1 1 */ 1474 case 0x7: /* 0 1 1 1 */
1475 case 0xd: /* 1 1 0 1 */ 1475 case 0xd: /* 1 1 0 1 */
1476 case 0xf: /* 1 1 1 1 */ 1476 case 0xf: /* 1 1 1 1 */
1477 vars->flow_ctrl = FLOW_CTRL_BOTH; 1477 vars->flow_ctrl = FLOW_CTRL_BOTH;
1478 break; 1478 break;
1479 1479
@@ -1531,6 +1531,28 @@ static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1531 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n", 1531 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1532 pause_result); 1532 pause_result);
1533 bnx2x_pause_resolve(vars, pause_result); 1533 bnx2x_pause_resolve(vars, pause_result);
1534 if (vars->flow_ctrl == FLOW_CTRL_NONE &&
1535 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1536 bnx2x_cl45_read(bp, port,
1537 ext_phy_type,
1538 ext_phy_addr,
1539 MDIO_AN_DEVAD,
1540 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1541
1542 bnx2x_cl45_read(bp, port,
1543 ext_phy_type,
1544 ext_phy_addr,
1545 MDIO_AN_DEVAD,
1546 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1547 pause_result = (ld_pause &
1548 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1549 pause_result |= (lp_pause &
1550 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1551
1552 bnx2x_pause_resolve(vars, pause_result);
1553 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1554 pause_result);
1555 }
1534 } 1556 }
1535 return ret; 1557 return ret;
1536} 1558}
@@ -1541,8 +1563,8 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1541 u32 gp_status) 1563 u32 gp_status)
1542{ 1564{
1543 struct bnx2x *bp = params->bp; 1565 struct bnx2x *bp = params->bp;
1544 u16 ld_pause; /* local driver */ 1566 u16 ld_pause; /* local driver */
1545 u16 lp_pause; /* link partner */ 1567 u16 lp_pause; /* link partner */
1546 u16 pause_result; 1568 u16 pause_result;
1547 1569
1548 vars->flow_ctrl = FLOW_CTRL_NONE; 1570 vars->flow_ctrl = FLOW_CTRL_NONE;
@@ -1573,13 +1595,10 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1573 (bnx2x_ext_phy_resove_fc(params, vars))) { 1595 (bnx2x_ext_phy_resove_fc(params, vars))) {
1574 return; 1596 return;
1575 } else { 1597 } else {
1576 vars->flow_ctrl = params->req_flow_ctrl; 1598 if (params->req_flow_ctrl == FLOW_CTRL_AUTO)
1577 if (vars->flow_ctrl == FLOW_CTRL_AUTO) { 1599 vars->flow_ctrl = params->req_fc_auto_adv;
1578 if (params->mtu <= MAX_MTU_SIZE) 1600 else
1579 vars->flow_ctrl = FLOW_CTRL_BOTH; 1601 vars->flow_ctrl = params->req_flow_ctrl;
1580 else
1581 vars->flow_ctrl = FLOW_CTRL_TX;
1582 }
1583 } 1602 }
1584 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 1603 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1585} 1604}
@@ -1590,6 +1609,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1590 u32 gp_status) 1609 u32 gp_status)
1591{ 1610{
1592 struct bnx2x *bp = params->bp; 1611 struct bnx2x *bp = params->bp;
1612
1593 u8 rc = 0; 1613 u8 rc = 0;
1594 vars->link_status = 0; 1614 vars->link_status = 0;
1595 1615
@@ -1690,7 +1710,11 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1690 1710
1691 vars->link_status |= LINK_STATUS_SERDES_LINK; 1711 vars->link_status |= LINK_STATUS_SERDES_LINK;
1692 1712
1693 if (params->req_line_speed == SPEED_AUTO_NEG) { 1713 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1714 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1715 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1716 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1717 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705))) {
1694 vars->autoneg = AUTO_NEG_ENABLED; 1718 vars->autoneg = AUTO_NEG_ENABLED;
1695 1719
1696 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 1720 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
@@ -1705,18 +1729,18 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1705 1729
1706 } 1730 }
1707 if (vars->flow_ctrl & FLOW_CTRL_TX) 1731 if (vars->flow_ctrl & FLOW_CTRL_TX)
1708 vars->link_status |= 1732 vars->link_status |=
1709 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 1733 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1710 1734
1711 if (vars->flow_ctrl & FLOW_CTRL_RX) 1735 if (vars->flow_ctrl & FLOW_CTRL_RX)
1712 vars->link_status |= 1736 vars->link_status |=
1713 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 1737 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1714 1738
1715 } else { /* link_down */ 1739 } else { /* link_down */
1716 DP(NETIF_MSG_LINK, "phy link down\n"); 1740 DP(NETIF_MSG_LINK, "phy link down\n");
1717 1741
1718 vars->phy_link_up = 0; 1742 vars->phy_link_up = 0;
1719 vars->line_speed = 0; 1743
1720 vars->duplex = DUPLEX_FULL; 1744 vars->duplex = DUPLEX_FULL;
1721 vars->flow_ctrl = FLOW_CTRL_NONE; 1745 vars->flow_ctrl = FLOW_CTRL_NONE;
1722 vars->autoneg = AUTO_NEG_DISABLED; 1746 vars->autoneg = AUTO_NEG_DISABLED;
@@ -1817,15 +1841,15 @@ static u8 bnx2x_emac_program(struct link_params *params,
1817} 1841}
1818 1842
1819/*****************************************************************************/ 1843/*****************************************************************************/
1820/* External Phy section */ 1844/* External Phy section */
1821/*****************************************************************************/ 1845/*****************************************************************************/
1822static void bnx2x_hw_reset(struct bnx2x *bp) 1846static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
1823{ 1847{
1824 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1848 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1825 MISC_REGISTERS_GPIO_OUTPUT_LOW); 1849 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
1826 msleep(1); 1850 msleep(1);
1827 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1851 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1828 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1852 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
1829} 1853}
1830 1854
1831static void bnx2x_ext_phy_reset(struct link_params *params, 1855static void bnx2x_ext_phy_reset(struct link_params *params,
@@ -1854,10 +1878,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1854 1878
1855 /* Restore normal power mode*/ 1879 /* Restore normal power mode*/
1856 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1880 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1857 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1881 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1882 params->port);
1858 1883
1859 /* HW reset */ 1884 /* HW reset */
1860 bnx2x_hw_reset(bp); 1885 bnx2x_hw_reset(bp, params->port);
1861 1886
1862 bnx2x_cl45_write(bp, params->port, 1887 bnx2x_cl45_write(bp, params->port,
1863 ext_phy_type, 1888 ext_phy_type,
@@ -1869,7 +1894,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1869 /* Unset Low Power Mode and SW reset */ 1894 /* Unset Low Power Mode and SW reset */
1870 /* Restore normal power mode*/ 1895 /* Restore normal power mode*/
1871 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1896 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1872 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1897 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1898 params->port);
1873 1899
1874 DP(NETIF_MSG_LINK, "XGXS 8072\n"); 1900 DP(NETIF_MSG_LINK, "XGXS 8072\n");
1875 bnx2x_cl45_write(bp, params->port, 1901 bnx2x_cl45_write(bp, params->port,
@@ -1887,19 +1913,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1887 1913
1888 /* Restore normal power mode*/ 1914 /* Restore normal power mode*/
1889 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1915 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1890 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1916 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1917 params->port);
1891 1918
1892 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1919 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1893 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1920 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1921 params->port);
1894 1922
1895 DP(NETIF_MSG_LINK, "XGXS 8073\n"); 1923 DP(NETIF_MSG_LINK, "XGXS 8073\n");
1896 bnx2x_cl45_write(bp,
1897 params->port,
1898 ext_phy_type,
1899 ext_phy_addr,
1900 MDIO_PMA_DEVAD,
1901 MDIO_PMA_REG_CTRL,
1902 1<<15);
1903 } 1924 }
1904 break; 1925 break;
1905 1926
@@ -1908,10 +1929,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1908 1929
1909 /* Restore normal power mode*/ 1930 /* Restore normal power mode*/
1910 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1931 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1911 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1932 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1933 params->port);
1912 1934
1913 /* HW reset */ 1935 /* HW reset */
1914 bnx2x_hw_reset(bp); 1936 bnx2x_hw_reset(bp, params->port);
1915 1937
1916 break; 1938 break;
1917 1939
@@ -1934,7 +1956,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1934 1956
1935 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: 1957 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
1936 DP(NETIF_MSG_LINK, "SerDes 5482\n"); 1958 DP(NETIF_MSG_LINK, "SerDes 5482\n");
1937 bnx2x_hw_reset(bp); 1959 bnx2x_hw_reset(bp, params->port);
1938 break; 1960 break;
1939 1961
1940 default: 1962 default:
@@ -2098,42 +2120,45 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2098 2120
2099} 2121}
2100 2122
2101static void bnx2x_bcm8073_external_rom_boot(struct link_params *params) 2123static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2124 u8 ext_phy_addr)
2102{ 2125{
2103 struct bnx2x *bp = params->bp; 2126 u16 fw_ver1, fw_ver2;
2104 u8 port = params->port; 2127 /* Boot port from external ROM */
2105 u8 ext_phy_addr = ((params->ext_phy_config &
2106 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2107 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2108 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2109 u16 fw_ver1, fw_ver2, val;
2110 /* Need to wait 100ms after reset */
2111 msleep(100);
2112 /* Boot port from external ROM */
2113 /* EDC grst */ 2128 /* EDC grst */
2114 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2129 bnx2x_cl45_write(bp, port,
2130 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2131 ext_phy_addr,
2115 MDIO_PMA_DEVAD, 2132 MDIO_PMA_DEVAD,
2116 MDIO_PMA_REG_GEN_CTRL, 2133 MDIO_PMA_REG_GEN_CTRL,
2117 0x0001); 2134 0x0001);
2118 2135
2119 /* ucode reboot and rst */ 2136 /* ucode reboot and rst */
2120 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2137 bnx2x_cl45_write(bp, port,
2138 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2139 ext_phy_addr,
2121 MDIO_PMA_DEVAD, 2140 MDIO_PMA_DEVAD,
2122 MDIO_PMA_REG_GEN_CTRL, 2141 MDIO_PMA_REG_GEN_CTRL,
2123 0x008c); 2142 0x008c);
2124 2143
2125 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2144 bnx2x_cl45_write(bp, port,
2145 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2146 ext_phy_addr,
2126 MDIO_PMA_DEVAD, 2147 MDIO_PMA_DEVAD,
2127 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 2148 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2128 2149
2129 /* Reset internal microprocessor */ 2150 /* Reset internal microprocessor */
2130 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2151 bnx2x_cl45_write(bp, port,
2152 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2153 ext_phy_addr,
2131 MDIO_PMA_DEVAD, 2154 MDIO_PMA_DEVAD,
2132 MDIO_PMA_REG_GEN_CTRL, 2155 MDIO_PMA_REG_GEN_CTRL,
2133 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 2156 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2134 2157
2135 /* Release srst bit */ 2158 /* Release srst bit */
2136 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2159 bnx2x_cl45_write(bp, port,
2160 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2161 ext_phy_addr,
2137 MDIO_PMA_DEVAD, 2162 MDIO_PMA_DEVAD,
2138 MDIO_PMA_REG_GEN_CTRL, 2163 MDIO_PMA_REG_GEN_CTRL,
2139 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2164 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
@@ -2142,35 +2167,52 @@ static void bnx2x_bcm8073_external_rom_boot(struct link_params *params)
2142 msleep(100); 2167 msleep(100);
2143 2168
2144 /* Clear ser_boot_ctl bit */ 2169 /* Clear ser_boot_ctl bit */
2145 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2170 bnx2x_cl45_write(bp, port,
2171 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2172 ext_phy_addr,
2146 MDIO_PMA_DEVAD, 2173 MDIO_PMA_DEVAD,
2147 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 2174 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2148 2175
2149 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, 2176 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2150 MDIO_PMA_DEVAD, 2177 ext_phy_addr,
2151 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 2178 MDIO_PMA_DEVAD,
2152 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, 2179 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2153 MDIO_PMA_DEVAD, 2180 bnx2x_cl45_read(bp, port,
2154 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 2181 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2182 ext_phy_addr,
2183 MDIO_PMA_DEVAD,
2184 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2155 DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2); 2185 DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
2156 2186
2157 /* Only set bit 10 = 1 (Tx power down) */ 2187}
2158 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2159 MDIO_PMA_DEVAD,
2160 MDIO_PMA_REG_TX_POWER_DOWN, &val);
2161 2188
2189static void bnx2x_bcm807x_force_10G(struct link_params *params)
2190{
2191 struct bnx2x *bp = params->bp;
2192 u8 port = params->port;
2193 u8 ext_phy_addr = ((params->ext_phy_config &
2194 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2195 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2196 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2197
2198 /* Force KR or KX */
2162 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2199 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2163 MDIO_PMA_DEVAD, 2200 MDIO_PMA_DEVAD,
2164 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1<<10)); 2201 MDIO_PMA_REG_CTRL,
2165 2202 0x2040);
2166 msleep(600);
2167 /* Release bit 10 (Release Tx power down) */
2168 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2203 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2169 MDIO_PMA_DEVAD, 2204 MDIO_PMA_DEVAD,
2170 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 2205 MDIO_PMA_REG_10G_CTRL2,
2171 2206 0x000b);
2207 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2208 MDIO_PMA_DEVAD,
2209 MDIO_PMA_REG_BCM_CTRL,
2210 0x0000);
2211 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2212 MDIO_AN_DEVAD,
2213 MDIO_AN_REG_CTRL,
2214 0x0000);
2172} 2215}
2173
2174static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params) 2216static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
2175{ 2217{
2176 struct bnx2x *bp = params->bp; 2218 struct bnx2x *bp = params->bp;
@@ -2236,32 +2278,51 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
2236 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2278 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2237 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); 2279 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
2238} 2280}
2239static void bnx2x_bcm807x_force_10G(struct link_params *params) 2281
2282static void bnx2x_8073_set_pause_cl37(struct link_params *params,
2283 struct link_vars *vars)
2240{ 2284{
2285
2241 struct bnx2x *bp = params->bp; 2286 struct bnx2x *bp = params->bp;
2242 u8 port = params->port; 2287 u16 cl37_val;
2243 u8 ext_phy_addr = ((params->ext_phy_config & 2288 u8 ext_phy_addr = ((params->ext_phy_config &
2244 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> 2289 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2245 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); 2290 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2246 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 2291 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2247 2292
2248 /* Force KR or KX */ 2293 bnx2x_cl45_read(bp, params->port,
2249 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2294 ext_phy_type,
2250 MDIO_PMA_DEVAD, 2295 ext_phy_addr,
2251 MDIO_PMA_REG_CTRL, 2296 MDIO_AN_DEVAD,
2252 0x2040); 2297 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
2253 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2298
2254 MDIO_PMA_DEVAD, 2299 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2255 MDIO_PMA_REG_10G_CTRL2, 2300 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
2256 0x000b); 2301
2257 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2302 if ((vars->ieee_fc &
2258 MDIO_PMA_DEVAD, 2303 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
2259 MDIO_PMA_REG_BCM_CTRL, 2304 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
2260 0x0000); 2305 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
2261 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2306 }
2307 if ((vars->ieee_fc &
2308 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
2309 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2310 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2311 }
2312 if ((vars->ieee_fc &
2313 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
2314 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2315 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2316 }
2317 DP(NETIF_MSG_LINK,
2318 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
2319
2320 bnx2x_cl45_write(bp, params->port,
2321 ext_phy_type,
2322 ext_phy_addr,
2262 MDIO_AN_DEVAD, 2323 MDIO_AN_DEVAD,
2263 MDIO_AN_REG_CTRL, 2324 MDIO_AN_REG_CL37_FC_LD, cl37_val);
2264 0x0000); 2325 msleep(500);
2265} 2326}
2266 2327
2267static void bnx2x_ext_phy_set_pause(struct link_params *params, 2328static void bnx2x_ext_phy_set_pause(struct link_params *params,
@@ -2282,13 +2343,16 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
2282 MDIO_AN_REG_ADV_PAUSE, &val); 2343 MDIO_AN_REG_ADV_PAUSE, &val);
2283 2344
2284 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 2345 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
2346
2285 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 2347 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
2286 2348
2287 if (vars->ieee_fc & 2349 if ((vars->ieee_fc &
2350 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
2288 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 2351 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2289 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 2352 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
2290 } 2353 }
2291 if (vars->ieee_fc & 2354 if ((vars->ieee_fc &
2355 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
2292 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 2356 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2293 val |= 2357 val |=
2294 MDIO_AN_REG_ADV_PAUSE_PAUSE; 2358 MDIO_AN_REG_ADV_PAUSE_PAUSE;
@@ -2302,6 +2366,65 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
2302 MDIO_AN_REG_ADV_PAUSE, val); 2366 MDIO_AN_REG_ADV_PAUSE, val);
2303} 2367}
2304 2368
2369
2370static void bnx2x_init_internal_phy(struct link_params *params,
2371 struct link_vars *vars)
2372{
2373 struct bnx2x *bp = params->bp;
2374 u8 port = params->port;
2375 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2376 u16 bank, rx_eq;
2377
2378 rx_eq = ((params->serdes_config &
2379 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
2380 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
2381
2382 DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
2383 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
2384 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
2385 CL45_WR_OVER_CL22(bp, port,
2386 params->phy_addr,
2387 bank ,
2388 MDIO_RX0_RX_EQ_BOOST,
2389 ((rx_eq &
2390 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
2391 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
2392 }
2393
2394 /* forced speed requested? */
2395 if (vars->line_speed != SPEED_AUTO_NEG) {
2396 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2397
2398 /* disable autoneg */
2399 bnx2x_set_autoneg(params, vars);
2400
2401 /* program speed and duplex */
2402 bnx2x_program_serdes(params, vars);
2403
2404 } else { /* AN_mode */
2405 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2406
2407 /* AN enabled */
2408 bnx2x_set_brcm_cl37_advertisment(params);
2409
2410 /* program duplex & pause advertisement (for aneg) */
2411 bnx2x_set_ieee_aneg_advertisment(params,
2412 vars->ieee_fc);
2413
2414 /* enable autoneg */
2415 bnx2x_set_autoneg(params, vars);
2416
2417 /* enable and restart AN */
2418 bnx2x_restart_autoneg(params);
2419 }
2420
2421 } else { /* SGMII mode */
2422 DP(NETIF_MSG_LINK, "SGMII\n");
2423
2424 bnx2x_initialize_sgmii_process(params, vars);
2425 }
2426}
2427
2305static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) 2428static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2306{ 2429{
2307 struct bnx2x *bp = params->bp; 2430 struct bnx2x *bp = params->bp;
@@ -2343,7 +2466,6 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2343 2466
2344 switch (ext_phy_type) { 2467 switch (ext_phy_type) {
2345 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 2468 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2346 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2347 break; 2469 break;
2348 2470
2349 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 2471 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
@@ -2419,7 +2541,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2419 ext_phy_type, 2541 ext_phy_type,
2420 ext_phy_addr, 2542 ext_phy_addr,
2421 MDIO_AN_DEVAD, 2543 MDIO_AN_DEVAD,
2422 MDIO_AN_REG_CL37_FD, 2544 MDIO_AN_REG_CL37_FC_LP,
2423 0x0020); 2545 0x0020);
2424 /* Enable CL37 AN */ 2546 /* Enable CL37 AN */
2425 bnx2x_cl45_write(bp, params->port, 2547 bnx2x_cl45_write(bp, params->port,
@@ -2458,54 +2580,43 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2458 rx_alarm_ctrl_val = 0x400; 2580 rx_alarm_ctrl_val = 0x400;
2459 lasi_ctrl_val = 0x0004; 2581 lasi_ctrl_val = 0x0004;
2460 } else { 2582 } else {
2461 /* In 8073, port1 is directed through emac0 and
2462 * port0 is directed through emac1
2463 */
2464 rx_alarm_ctrl_val = (1<<2); 2583 rx_alarm_ctrl_val = (1<<2);
2465 /*lasi_ctrl_val = 0x0005;*/
2466 lasi_ctrl_val = 0x0004; 2584 lasi_ctrl_val = 0x0004;
2467 } 2585 }
2468 2586
2469 /* Wait for soft reset to get cleared upto 1 sec */ 2587 /* enable LASI */
2470 for (cnt = 0; cnt < 1000; cnt++) { 2588 bnx2x_cl45_write(bp, params->port,
2471 bnx2x_cl45_read(bp, params->port, 2589 ext_phy_type,
2472 ext_phy_type, 2590 ext_phy_addr,
2473 ext_phy_addr, 2591 MDIO_PMA_DEVAD,
2474 MDIO_PMA_DEVAD, 2592 MDIO_PMA_REG_RX_ALARM_CTRL,
2475 MDIO_PMA_REG_CTRL, 2593 rx_alarm_ctrl_val);
2476 &ctrl); 2594
2477 if (!(ctrl & (1<<15))) 2595 bnx2x_cl45_write(bp, params->port,
2478 break; 2596 ext_phy_type,
2479 msleep(1); 2597 ext_phy_addr,
2480 } 2598 MDIO_PMA_DEVAD,
2481 DP(NETIF_MSG_LINK, 2599 MDIO_PMA_REG_LASI_CTRL,
2482 "807x control reg 0x%x (after %d ms)\n", 2600 lasi_ctrl_val);
2483 ctrl, cnt); 2601
2602 bnx2x_8073_set_pause_cl37(params, vars);
2484 2603
2485 if (ext_phy_type == 2604 if (ext_phy_type ==
2486 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){ 2605 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
2487 bnx2x_bcm8072_external_rom_boot(params); 2606 bnx2x_bcm8072_external_rom_boot(params);
2488 } else { 2607 } else {
2489 bnx2x_bcm8073_external_rom_boot(params); 2608
2490 /* In case of 8073 with long xaui lines, 2609 /* In case of 8073 with long xaui lines,
2491 don't set the 8073 xaui low power*/ 2610 don't set the 8073 xaui low power*/
2492 bnx2x_bcm8073_set_xaui_low_power_mode(params); 2611 bnx2x_bcm8073_set_xaui_low_power_mode(params);
2493 } 2612 }
2494 2613
2495 /* enable LASI */ 2614 bnx2x_cl45_read(bp, params->port,
2496 bnx2x_cl45_write(bp, params->port, 2615 ext_phy_type,
2497 ext_phy_type, 2616 ext_phy_addr,
2498 ext_phy_addr, 2617 MDIO_PMA_DEVAD,
2499 MDIO_PMA_DEVAD, 2618 0xca13,
2500 MDIO_PMA_REG_RX_ALARM_CTRL, 2619 &tmp1);
2501 rx_alarm_ctrl_val);
2502
2503 bnx2x_cl45_write(bp, params->port,
2504 ext_phy_type,
2505 ext_phy_addr,
2506 MDIO_PMA_DEVAD,
2507 MDIO_PMA_REG_LASI_CTRL,
2508 lasi_ctrl_val);
2509 2620
2510 bnx2x_cl45_read(bp, params->port, 2621 bnx2x_cl45_read(bp, params->port,
2511 ext_phy_type, 2622 ext_phy_type,
@@ -2519,12 +2630,21 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2519 /* If this is forced speed, set to KR or KX 2630 /* If this is forced speed, set to KR or KX
2520 * (all other are not supported) 2631 * (all other are not supported)
2521 */ 2632 */
2522 if (!(params->req_line_speed == SPEED_AUTO_NEG)) { 2633 if (params->loopback_mode == LOOPBACK_EXT) {
2523 if (params->req_line_speed == SPEED_10000) { 2634 bnx2x_bcm807x_force_10G(params);
2524 bnx2x_bcm807x_force_10G(params); 2635 DP(NETIF_MSG_LINK,
2525 DP(NETIF_MSG_LINK, 2636 "Forced speed 10G on 807X\n");
2526 "Forced speed 10G on 807X\n"); 2637 break;
2527 break; 2638 } else {
2639 bnx2x_cl45_write(bp, params->port,
2640 ext_phy_type, ext_phy_addr,
2641 MDIO_PMA_DEVAD,
2642 MDIO_PMA_REG_BCM_CTRL,
2643 0x0002);
2644 }
2645 if (params->req_line_speed != SPEED_AUTO_NEG) {
2646 if (params->req_line_speed == SPEED_10000) {
2647 val = (1<<7);
2528 } else if (params->req_line_speed == 2648 } else if (params->req_line_speed ==
2529 SPEED_2500) { 2649 SPEED_2500) {
2530 val = (1<<5); 2650 val = (1<<5);
@@ -2539,11 +2659,14 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2659 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2540 val |= (1<<7); 2660 val |= (1<<7);
2541 2661
2662 /* Note that 2.5G works only when
2663 used with 1G advertisment */
2542 if (params->speed_cap_mask & 2664 if (params->speed_cap_mask &
2543 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 2665 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
2666 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
2544 val |= (1<<5); 2667 val |= (1<<5);
2545 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 2668 DP(NETIF_MSG_LINK,
2546 /*val = ((1<<5)|(1<<7));*/ 2669 "807x autoneg val = 0x%x\n", val);
2547 } 2670 }
2548 2671
2549 bnx2x_cl45_write(bp, params->port, 2672 bnx2x_cl45_write(bp, params->port,
@@ -2554,20 +2677,19 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2554 2677
2555 if (ext_phy_type == 2678 if (ext_phy_type ==
2556 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 2679 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2557 /* Disable 2.5Ghz */ 2680
2558 bnx2x_cl45_read(bp, params->port, 2681 bnx2x_cl45_read(bp, params->port,
2559 ext_phy_type, 2682 ext_phy_type,
2560 ext_phy_addr, 2683 ext_phy_addr,
2561 MDIO_AN_DEVAD, 2684 MDIO_AN_DEVAD,
2562 0x8329, &tmp1); 2685 0x8329, &tmp1);
2563/* SUPPORT_SPEED_CAPABILITY 2686
2564 (Due to the nature of the link order, its not 2687 if (((params->speed_cap_mask &
2565 possible to enable 2.5G within the autoneg 2688 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
2566 capabilities) 2689 (params->req_line_speed ==
2567 if (params->speed_cap_mask & 2690 SPEED_AUTO_NEG)) ||
2568 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 2691 (params->req_line_speed ==
2569*/ 2692 SPEED_2500)) {
2570 if (params->req_line_speed == SPEED_2500) {
2571 u16 phy_ver; 2693 u16 phy_ver;
2572 /* Allow 2.5G for A1 and above */ 2694 /* Allow 2.5G for A1 and above */
2573 bnx2x_cl45_read(bp, params->port, 2695 bnx2x_cl45_read(bp, params->port,
@@ -2575,49 +2697,53 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2575 ext_phy_addr, 2697 ext_phy_addr,
2576 MDIO_PMA_DEVAD, 2698 MDIO_PMA_DEVAD,
2577 0xc801, &phy_ver); 2699 0xc801, &phy_ver);
2578 2700 DP(NETIF_MSG_LINK, "Add 2.5G\n");
2579 if (phy_ver > 0) 2701 if (phy_ver > 0)
2580 tmp1 |= 1; 2702 tmp1 |= 1;
2581 else 2703 else
2582 tmp1 &= 0xfffe; 2704 tmp1 &= 0xfffe;
2583 } 2705 } else {
2584 else 2706 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
2585 tmp1 &= 0xfffe; 2707 tmp1 &= 0xfffe;
2708 }
2586 2709
2587 bnx2x_cl45_write(bp, params->port, 2710 bnx2x_cl45_write(bp, params->port,
2588 ext_phy_type, 2711 ext_phy_type,
2589 ext_phy_addr, 2712 ext_phy_addr,
2590 MDIO_AN_DEVAD, 2713 MDIO_AN_DEVAD,
2591 0x8329, tmp1); 2714 0x8329, tmp1);
2592 } 2715 }
2593 /* Add support for CL37 (passive mode) I */ 2716
2594 bnx2x_cl45_write(bp, params->port, 2717 /* Add support for CL37 (passive mode) II */
2718
2719 bnx2x_cl45_read(bp, params->port,
2595 ext_phy_type, 2720 ext_phy_type,
2596 ext_phy_addr, 2721 ext_phy_addr,
2597 MDIO_AN_DEVAD, 2722 MDIO_AN_DEVAD,
2598 MDIO_AN_REG_CL37_CL73, 0x040c); 2723 MDIO_AN_REG_CL37_FC_LD,
2599 /* Add support for CL37 (passive mode) II */ 2724 &tmp1);
2725
2600 bnx2x_cl45_write(bp, params->port, 2726 bnx2x_cl45_write(bp, params->port,
2601 ext_phy_type, 2727 ext_phy_type,
2602 ext_phy_addr, 2728 ext_phy_addr,
2603 MDIO_AN_DEVAD, 2729 MDIO_AN_DEVAD,
2604 MDIO_AN_REG_CL37_FD, 0x20); 2730 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
2731 ((params->req_duplex == DUPLEX_FULL) ?
2732 0x20 : 0x40)));
2733
2605 /* Add support for CL37 (passive mode) III */ 2734 /* Add support for CL37 (passive mode) III */
2606 bnx2x_cl45_write(bp, params->port, 2735 bnx2x_cl45_write(bp, params->port,
2607 ext_phy_type, 2736 ext_phy_type,
2608 ext_phy_addr, 2737 ext_phy_addr,
2609 MDIO_AN_DEVAD, 2738 MDIO_AN_DEVAD,
2610 MDIO_AN_REG_CL37_AN, 0x1000); 2739 MDIO_AN_REG_CL37_AN, 0x1000);
2611 /* Restart autoneg */
2612 msleep(500);
2613 2740
2614 if (ext_phy_type == 2741 if (ext_phy_type ==
2615 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 2742 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2616 2743 /* The SNR will improve about 2db by changing
2617 /* The SNR will improve about 2db by changing the
2618 BW and FEE main tap. Rest commands are executed 2744 BW and FEE main tap. Rest commands are executed
2619 after link is up*/ 2745 after link is up*/
2620 /* Change FFE main cursor to 5 in EDC register */ 2746 /*Change FFE main cursor to 5 in EDC register*/
2621 if (bnx2x_8073_is_snr_needed(params)) 2747 if (bnx2x_8073_is_snr_needed(params))
2622 bnx2x_cl45_write(bp, params->port, 2748 bnx2x_cl45_write(bp, params->port,
2623 ext_phy_type, 2749 ext_phy_type,
@@ -2626,25 +2752,28 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2626 MDIO_PMA_REG_EDC_FFE_MAIN, 2752 MDIO_PMA_REG_EDC_FFE_MAIN,
2627 0xFB0C); 2753 0xFB0C);
2628 2754
2629 /* Enable FEC (Forware Error Correction) 2755 /* Enable FEC (Forware Error Correction)
2630 Request in the AN */ 2756 Request in the AN */
2631 bnx2x_cl45_read(bp, params->port, 2757 bnx2x_cl45_read(bp, params->port,
2632 ext_phy_type, 2758 ext_phy_type,
2633 ext_phy_addr, 2759 ext_phy_addr,
2634 MDIO_AN_DEVAD, 2760 MDIO_AN_DEVAD,
2635 MDIO_AN_REG_ADV2, &tmp1); 2761 MDIO_AN_REG_ADV2, &tmp1);
2636 2762
2637 tmp1 |= (1<<15); 2763 tmp1 |= (1<<15);
2764
2765 bnx2x_cl45_write(bp, params->port,
2766 ext_phy_type,
2767 ext_phy_addr,
2768 MDIO_AN_DEVAD,
2769 MDIO_AN_REG_ADV2, tmp1);
2638 2770
2639 bnx2x_cl45_write(bp, params->port,
2640 ext_phy_type,
2641 ext_phy_addr,
2642 MDIO_AN_DEVAD,
2643 MDIO_AN_REG_ADV2, tmp1);
2644 } 2771 }
2645 2772
2646 bnx2x_ext_phy_set_pause(params, vars); 2773 bnx2x_ext_phy_set_pause(params, vars);
2647 2774
2775 /* Restart autoneg */
2776 msleep(500);
2648 bnx2x_cl45_write(bp, params->port, 2777 bnx2x_cl45_write(bp, params->port,
2649 ext_phy_type, 2778 ext_phy_type,
2650 ext_phy_addr, 2779 ext_phy_addr,
@@ -2701,10 +2830,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2701 } 2830 }
2702 2831
2703 } else { /* SerDes */ 2832 } else { /* SerDes */
2704/* ext_phy_addr = ((bp->ext_phy_config & 2833
2705 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
2706 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
2707*/
2708 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config); 2834 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2709 switch (ext_phy_type) { 2835 switch (ext_phy_type) {
2710 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT: 2836 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
@@ -2726,7 +2852,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2726 2852
2727 2853
2728static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, 2854static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2729 struct link_vars *vars) 2855 struct link_vars *vars)
2730{ 2856{
2731 struct bnx2x *bp = params->bp; 2857 struct bnx2x *bp = params->bp;
2732 u32 ext_phy_type; 2858 u32 ext_phy_type;
@@ -2767,6 +2893,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2767 MDIO_PMA_REG_RX_SD, &rx_sd); 2893 MDIO_PMA_REG_RX_SD, &rx_sd);
2768 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd); 2894 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2769 ext_phy_link_up = (rx_sd & 0x1); 2895 ext_phy_link_up = (rx_sd & 0x1);
2896 if (ext_phy_link_up)
2897 vars->line_speed = SPEED_10000;
2770 break; 2898 break;
2771 2899
2772 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 2900 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
@@ -2810,6 +2938,13 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2810 */ 2938 */
2811 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) || 2939 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
2812 (val2 & (1<<1))); 2940 (val2 & (1<<1)));
2941 if (ext_phy_link_up) {
2942 if (val2 & (1<<1))
2943 vars->line_speed = SPEED_1000;
2944 else
2945 vars->line_speed = SPEED_10000;
2946 }
2947
2813 /* clear LASI indication*/ 2948 /* clear LASI indication*/
2814 bnx2x_cl45_read(bp, params->port, ext_phy_type, 2949 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2815 ext_phy_addr, 2950 ext_phy_addr,
@@ -2820,6 +2955,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2820 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 2955 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2821 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 2956 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2822 { 2957 {
2958 u16 link_status = 0;
2959 u16 an1000_status = 0;
2823 if (ext_phy_type == 2960 if (ext_phy_type ==
2824 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) { 2961 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
2825 bnx2x_cl45_read(bp, params->port, 2962 bnx2x_cl45_read(bp, params->port,
@@ -2846,14 +2983,9 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2846 MDIO_PMA_DEVAD, 2983 MDIO_PMA_DEVAD,
2847 MDIO_PMA_REG_LASI_STATUS, &val1); 2984 MDIO_PMA_REG_LASI_STATUS, &val1);
2848 2985
2849 bnx2x_cl45_read(bp, params->port,
2850 ext_phy_type,
2851 ext_phy_addr,
2852 MDIO_PMA_DEVAD,
2853 MDIO_PMA_REG_LASI_STATUS, &val2);
2854 DP(NETIF_MSG_LINK, 2986 DP(NETIF_MSG_LINK,
2855 "8703 LASI status 0x%x->0x%x\n", 2987 "8703 LASI status 0x%x\n",
2856 val1, val2); 2988 val1);
2857 } 2989 }
2858 2990
2859 /* clear the interrupt LASI status register */ 2991 /* clear the interrupt LASI status register */
@@ -2869,20 +3001,23 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2869 MDIO_PCS_REG_STATUS, &val1); 3001 MDIO_PCS_REG_STATUS, &val1);
2870 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", 3002 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
2871 val2, val1); 3003 val2, val1);
2872 /* Check the LASI */ 3004 /* Clear MSG-OUT */
2873 bnx2x_cl45_read(bp, params->port, 3005 bnx2x_cl45_read(bp, params->port,
2874 ext_phy_type, 3006 ext_phy_type,
2875 ext_phy_addr, 3007 ext_phy_addr,
2876 MDIO_PMA_DEVAD, 3008 MDIO_PMA_DEVAD,
2877 MDIO_PMA_REG_RX_ALARM, &val2); 3009 0xca13,
3010 &val1);
3011
3012 /* Check the LASI */
2878 bnx2x_cl45_read(bp, params->port, 3013 bnx2x_cl45_read(bp, params->port,
2879 ext_phy_type, 3014 ext_phy_type,
2880 ext_phy_addr, 3015 ext_phy_addr,
2881 MDIO_PMA_DEVAD, 3016 MDIO_PMA_DEVAD,
2882 MDIO_PMA_REG_RX_ALARM, 3017 MDIO_PMA_REG_RX_ALARM, &val2);
2883 &val1); 3018
2884 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n", 3019 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
2885 val2, val1); 3020
2886 /* Check the link status */ 3021 /* Check the link status */
2887 bnx2x_cl45_read(bp, params->port, 3022 bnx2x_cl45_read(bp, params->port,
2888 ext_phy_type, 3023 ext_phy_type,
@@ -2905,29 +3040,29 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2905 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 3040 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
2906 if (ext_phy_type == 3041 if (ext_phy_type ==
2907 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 3042 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2908 u16 an1000_status = 0; 3043
2909 if (ext_phy_link_up && 3044 if (ext_phy_link_up &&
2910 ( 3045 ((params->req_line_speed !=
2911 (params->req_line_speed != SPEED_10000) 3046 SPEED_10000))) {
2912 )) {
2913 if (bnx2x_bcm8073_xaui_wa(params) 3047 if (bnx2x_bcm8073_xaui_wa(params)
2914 != 0) { 3048 != 0) {
2915 ext_phy_link_up = 0; 3049 ext_phy_link_up = 0;
2916 break; 3050 break;
2917 } 3051 }
2918 bnx2x_cl45_read(bp, params->port, 3052 }
3053 bnx2x_cl45_read(bp, params->port,
2919 ext_phy_type, 3054 ext_phy_type,
2920 ext_phy_addr, 3055 ext_phy_addr,
2921 MDIO_XS_DEVAD, 3056 MDIO_AN_DEVAD,
2922 0x8304, 3057 0x8304,
2923 &an1000_status); 3058 &an1000_status);
2924 bnx2x_cl45_read(bp, params->port, 3059 bnx2x_cl45_read(bp, params->port,
2925 ext_phy_type, 3060 ext_phy_type,
2926 ext_phy_addr, 3061 ext_phy_addr,
2927 MDIO_XS_DEVAD, 3062 MDIO_AN_DEVAD,
2928 0x8304, 3063 0x8304,
2929 &an1000_status); 3064 &an1000_status);
2930 } 3065
2931 /* Check the link status on 1.1.2 */ 3066 /* Check the link status on 1.1.2 */
2932 bnx2x_cl45_read(bp, params->port, 3067 bnx2x_cl45_read(bp, params->port,
2933 ext_phy_type, 3068 ext_phy_type,
@@ -2943,8 +3078,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2943 "an_link_status=0x%x\n", 3078 "an_link_status=0x%x\n",
2944 val2, val1, an1000_status); 3079 val2, val1, an1000_status);
2945 3080
2946 ext_phy_link_up = (((val1 & 4) == 4) || 3081 ext_phy_link_up = (((val1 & 4) == 4) ||
2947 (an1000_status & (1<<1))); 3082 (an1000_status & (1<<1)));
2948 if (ext_phy_link_up && 3083 if (ext_phy_link_up &&
2949 bnx2x_8073_is_snr_needed(params)) { 3084 bnx2x_8073_is_snr_needed(params)) {
2950 /* The SNR will improve about 2dbby 3085 /* The SNR will improve about 2dbby
@@ -2968,8 +3103,74 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2968 MDIO_PMA_REG_CDR_BANDWIDTH, 3103 MDIO_PMA_REG_CDR_BANDWIDTH,
2969 0x0333); 3104 0x0333);
2970 3105
3106
3107 }
3108 bnx2x_cl45_read(bp, params->port,
3109 ext_phy_type,
3110 ext_phy_addr,
3111 MDIO_PMA_DEVAD,
3112 0xc820,
3113 &link_status);
3114
3115 /* Bits 0..2 --> speed detected,
3116 bits 13..15--> link is down */
3117 if ((link_status & (1<<2)) &&
3118 (!(link_status & (1<<15)))) {
3119 ext_phy_link_up = 1;
3120 vars->line_speed = SPEED_10000;
3121 DP(NETIF_MSG_LINK,
3122 "port %x: External link"
3123 " up in 10G\n", params->port);
3124 } else if ((link_status & (1<<1)) &&
3125 (!(link_status & (1<<14)))) {
3126 ext_phy_link_up = 1;
3127 vars->line_speed = SPEED_2500;
3128 DP(NETIF_MSG_LINK,
3129 "port %x: External link"
3130 " up in 2.5G\n", params->port);
3131 } else if ((link_status & (1<<0)) &&
3132 (!(link_status & (1<<13)))) {
3133 ext_phy_link_up = 1;
3134 vars->line_speed = SPEED_1000;
3135 DP(NETIF_MSG_LINK,
3136 "port %x: External link"
3137 " up in 1G\n", params->port);
3138 } else {
3139 ext_phy_link_up = 0;
3140 DP(NETIF_MSG_LINK,
3141 "port %x: External link"
3142 " is down\n", params->port);
3143 }
3144 } else {
3145 /* See if 1G link is up for the 8072 */
3146 bnx2x_cl45_read(bp, params->port,
3147 ext_phy_type,
3148 ext_phy_addr,
3149 MDIO_AN_DEVAD,
3150 0x8304,
3151 &an1000_status);
3152 bnx2x_cl45_read(bp, params->port,
3153 ext_phy_type,
3154 ext_phy_addr,
3155 MDIO_AN_DEVAD,
3156 0x8304,
3157 &an1000_status);
3158 if (an1000_status & (1<<1)) {
3159 ext_phy_link_up = 1;
3160 vars->line_speed = SPEED_1000;
3161 DP(NETIF_MSG_LINK,
3162 "port %x: External link"
3163 " up in 1G\n", params->port);
3164 } else if (ext_phy_link_up) {
3165 ext_phy_link_up = 1;
3166 vars->line_speed = SPEED_10000;
3167 DP(NETIF_MSG_LINK,
3168 "port %x: External link"
3169 " up in 10G\n", params->port);
2971 } 3170 }
2972 } 3171 }
3172
3173
2973 break; 3174 break;
2974 } 3175 }
2975 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 3176 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
@@ -3006,6 +3207,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
3006 MDIO_AN_DEVAD, 3207 MDIO_AN_DEVAD,
3007 MDIO_AN_REG_MASTER_STATUS, 3208 MDIO_AN_REG_MASTER_STATUS,
3008 &val2); 3209 &val2);
3210 vars->line_speed = SPEED_10000;
3009 DP(NETIF_MSG_LINK, 3211 DP(NETIF_MSG_LINK,
3010 "SFX7101 AN status 0x%x->Master=%x\n", 3212 "SFX7101 AN status 0x%x->Master=%x\n",
3011 val2, 3213 val2,
@@ -3100,7 +3302,7 @@ static void bnx2x_link_int_enable(struct link_params *params)
3100 * link management 3302 * link management
3101 */ 3303 */
3102static void bnx2x_link_int_ack(struct link_params *params, 3304static void bnx2x_link_int_ack(struct link_params *params,
3103 struct link_vars *vars, u16 is_10g) 3305 struct link_vars *vars, u8 is_10g)
3104{ 3306{
3105 struct bnx2x *bp = params->bp; 3307 struct bnx2x *bp = params->bp;
3106 u8 port = params->port; 3308 u8 port = params->port;
@@ -3181,7 +3383,8 @@ static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
3181} 3383}
3182 3384
3183 3385
3184static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr) 3386static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
3387 u32 ext_phy_type)
3185{ 3388{
3186 u32 cnt = 0; 3389 u32 cnt = 0;
3187 u16 ctrl = 0; 3390 u16 ctrl = 0;
@@ -3192,12 +3395,14 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
3192 3395
3193 /* take ext phy out of reset */ 3396 /* take ext phy out of reset */
3194 bnx2x_set_gpio(bp, 3397 bnx2x_set_gpio(bp,
3195 MISC_REGISTERS_GPIO_2, 3398 MISC_REGISTERS_GPIO_2,
3196 MISC_REGISTERS_GPIO_HIGH); 3399 MISC_REGISTERS_GPIO_HIGH,
3400 port);
3197 3401
3198 bnx2x_set_gpio(bp, 3402 bnx2x_set_gpio(bp,
3199 MISC_REGISTERS_GPIO_1, 3403 MISC_REGISTERS_GPIO_1,
3200 MISC_REGISTERS_GPIO_HIGH); 3404 MISC_REGISTERS_GPIO_HIGH,
3405 port);
3201 3406
3202 /* wait for 5ms */ 3407 /* wait for 5ms */
3203 msleep(5); 3408 msleep(5);
@@ -3205,7 +3410,7 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
3205 for (cnt = 0; cnt < 1000; cnt++) { 3410 for (cnt = 0; cnt < 1000; cnt++) {
3206 msleep(1); 3411 msleep(1);
3207 bnx2x_cl45_read(bp, port, 3412 bnx2x_cl45_read(bp, port,
3208 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 3413 ext_phy_type,
3209 ext_phy_addr, 3414 ext_phy_addr,
3210 MDIO_PMA_DEVAD, 3415 MDIO_PMA_DEVAD,
3211 MDIO_PMA_REG_CTRL, 3416 MDIO_PMA_REG_CTRL,
@@ -3217,13 +3422,17 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
3217 } 3422 }
3218} 3423}
3219 3424
3220static void bnx2x_turn_off_sf(struct bnx2x *bp) 3425static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
3221{ 3426{
3222 /* put sf to reset */ 3427 /* put sf to reset */
3223 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW);
3224 bnx2x_set_gpio(bp, 3428 bnx2x_set_gpio(bp,
3225 MISC_REGISTERS_GPIO_2, 3429 MISC_REGISTERS_GPIO_1,
3226 MISC_REGISTERS_GPIO_LOW); 3430 MISC_REGISTERS_GPIO_LOW,
3431 port);
3432 bnx2x_set_gpio(bp,
3433 MISC_REGISTERS_GPIO_2,
3434 MISC_REGISTERS_GPIO_LOW,
3435 port);
3227} 3436}
3228 3437
3229u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, 3438u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
@@ -3253,7 +3462,8 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3253 3462
3254 /* Take ext phy out of reset */ 3463 /* Take ext phy out of reset */
3255 if (!driver_loaded) 3464 if (!driver_loaded)
3256 bnx2x_turn_on_sf(bp, params->port, ext_phy_addr); 3465 bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
3466 ext_phy_type);
3257 3467
3258 /* wait for 1ms */ 3468 /* wait for 1ms */
3259 msleep(1); 3469 msleep(1);
@@ -3276,11 +3486,16 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3276 version[4] = '\0'; 3486 version[4] = '\0';
3277 3487
3278 if (!driver_loaded) 3488 if (!driver_loaded)
3279 bnx2x_turn_off_sf(bp); 3489 bnx2x_turn_off_sf(bp, params->port);
3280 break; 3490 break;
3281 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 3491 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3282 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 3492 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3283 { 3493 {
3494 /* Take ext phy out of reset */
3495 if (!driver_loaded)
3496 bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
3497 ext_phy_type);
3498
3284 bnx2x_cl45_read(bp, params->port, ext_phy_type, 3499 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3285 ext_phy_addr, 3500 ext_phy_addr,
3286 MDIO_PMA_DEVAD, 3501 MDIO_PMA_DEVAD,
@@ -3333,7 +3548,7 @@ static void bnx2x_set_xgxs_loopback(struct link_params *params,
3333 struct bnx2x *bp = params->bp; 3548 struct bnx2x *bp = params->bp;
3334 3549
3335 if (is_10g) { 3550 if (is_10g) {
3336 u32 md_devad; 3551 u32 md_devad;
3337 3552
3338 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 3553 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3339 3554
@@ -3553,6 +3768,8 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3553 u16 hw_led_mode, u32 chip_id) 3768 u16 hw_led_mode, u32 chip_id)
3554{ 3769{
3555 u8 rc = 0; 3770 u8 rc = 0;
3771 u32 tmp;
3772 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3556 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 3773 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3557 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 3774 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3558 speed, hw_led_mode); 3775 speed, hw_led_mode);
@@ -3561,6 +3778,9 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3561 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 3778 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3562 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 3779 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3563 SHARED_HW_CFG_LED_MAC1); 3780 SHARED_HW_CFG_LED_MAC1);
3781
3782 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3783 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3564 break; 3784 break;
3565 3785
3566 case LED_MODE_OPER: 3786 case LED_MODE_OPER:
@@ -3572,6 +3792,10 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3572 LED_BLINK_RATE_VAL); 3792 LED_BLINK_RATE_VAL);
3573 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 3793 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3574 port*4, 1); 3794 port*4, 1);
3795 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3796 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3797 (tmp & (~EMAC_LED_OVERRIDE)));
3798
3575 if (!CHIP_IS_E1H(bp) && 3799 if (!CHIP_IS_E1H(bp) &&
3576 ((speed == SPEED_2500) || 3800 ((speed == SPEED_2500) ||
3577 (speed == SPEED_1000) || 3801 (speed == SPEED_1000) ||
@@ -3622,7 +3846,8 @@ static u8 bnx2x_link_initialize(struct link_params *params,
3622 struct bnx2x *bp = params->bp; 3846 struct bnx2x *bp = params->bp;
3623 u8 port = params->port; 3847 u8 port = params->port;
3624 u8 rc = 0; 3848 u8 rc = 0;
3625 3849 u8 non_ext_phy;
3850 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3626 /* Activate the external PHY */ 3851 /* Activate the external PHY */
3627 bnx2x_ext_phy_reset(params, vars); 3852 bnx2x_ext_phy_reset(params, vars);
3628 3853
@@ -3644,10 +3869,6 @@ static u8 bnx2x_link_initialize(struct link_params *params,
3644 bnx2x_set_swap_lanes(params); 3869 bnx2x_set_swap_lanes(params);
3645 } 3870 }
3646 3871
3647 /* Set Parallel Detect */
3648 if (params->req_line_speed == SPEED_AUTO_NEG)
3649 bnx2x_set_parallel_detection(params, vars->phy_flags);
3650
3651 if (vars->phy_flags & PHY_XGXS_FLAG) { 3872 if (vars->phy_flags & PHY_XGXS_FLAG) {
3652 if (params->req_line_speed && 3873 if (params->req_line_speed &&
3653 ((params->req_line_speed == SPEED_100) || 3874 ((params->req_line_speed == SPEED_100) ||
@@ -3657,68 +3878,33 @@ static u8 bnx2x_link_initialize(struct link_params *params,
3657 vars->phy_flags &= ~PHY_SGMII_FLAG; 3878 vars->phy_flags &= ~PHY_SGMII_FLAG;
3658 } 3879 }
3659 } 3880 }
3881 /* In case of external phy existance, the line speed would be the
3882 line speed linked up by the external phy. In case it is direct only,
3883 then the line_speed during initialization will be equal to the
3884 req_line_speed*/
3885 vars->line_speed = params->req_line_speed;
3660 3886
3661 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 3887 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
3662 u16 bank, rx_eq;
3663
3664 rx_eq = ((params->serdes_config &
3665 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
3666 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
3667 3888
3668 DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq); 3889 /* init ext phy and enable link state int */
3669 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL; 3890 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
3670 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) { 3891 (params->loopback_mode == LOOPBACK_XGXS_10) ||
3671 CL45_WR_OVER_CL22(bp, port, 3892 (params->loopback_mode == LOOPBACK_EXT_PHY));
3672 params->phy_addr, 3893
3673 bank , 3894 if (non_ext_phy ||
3674 MDIO_RX0_RX_EQ_BOOST, 3895 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705)) {
3675 ((rx_eq & 3896 if (params->req_line_speed == SPEED_AUTO_NEG)
3676 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) | 3897 bnx2x_set_parallel_detection(params, vars->phy_flags);
3677 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL)); 3898 bnx2x_init_internal_phy(params, vars);
3678 }
3679
3680 /* forced speed requested? */
3681 if (params->req_line_speed != SPEED_AUTO_NEG) {
3682 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3683
3684 /* disable autoneg */
3685 bnx2x_set_autoneg(params, vars);
3686
3687 /* program speed and duplex */
3688 bnx2x_program_serdes(params);
3689 vars->ieee_fc =
3690 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3691
3692 } else { /* AN_mode */
3693 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3694
3695 /* AN enabled */
3696 bnx2x_set_brcm_cl37_advertisment(params);
3697
3698 /* program duplex & pause advertisement (for aneg) */
3699 bnx2x_set_ieee_aneg_advertisment(params,
3700 &vars->ieee_fc);
3701
3702 /* enable autoneg */
3703 bnx2x_set_autoneg(params, vars);
3704
3705 /* enable and restart AN */
3706 bnx2x_restart_autoneg(params);
3707 }
3708
3709 } else { /* SGMII mode */
3710 DP(NETIF_MSG_LINK, "SGMII\n");
3711
3712 bnx2x_initialize_sgmii_process(params);
3713 } 3899 }
3714 3900
3715 /* init ext phy and enable link state int */ 3901 if (!non_ext_phy)
3716 rc |= bnx2x_ext_phy_init(params, vars); 3902 rc |= bnx2x_ext_phy_init(params, vars);
3717 3903
3718 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 3904 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3719 (NIG_STATUS_XGXS0_LINK10G | 3905 (NIG_STATUS_XGXS0_LINK10G |
3720 NIG_STATUS_XGXS0_LINK_STATUS | 3906 NIG_STATUS_XGXS0_LINK_STATUS |
3721 NIG_STATUS_SERDES0_LINK_STATUS)); 3907 NIG_STATUS_SERDES0_LINK_STATUS));
3722 3908
3723 return rc; 3909 return rc;
3724 3910
@@ -3730,15 +3916,23 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
3730 struct bnx2x *bp = params->bp; 3916 struct bnx2x *bp = params->bp;
3731 3917
3732 u32 val; 3918 u32 val;
3733 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 3919 DP(NETIF_MSG_LINK, "Phy Initialization started \n");
3734 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n", 3920 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
3735 params->req_line_speed, params->req_flow_ctrl); 3921 params->req_line_speed, params->req_flow_ctrl);
3736 vars->link_status = 0; 3922 vars->link_status = 0;
3923 vars->phy_link_up = 0;
3924 vars->link_up = 0;
3925 vars->line_speed = 0;
3926 vars->duplex = DUPLEX_FULL;
3927 vars->flow_ctrl = FLOW_CTRL_NONE;
3928 vars->mac_type = MAC_TYPE_NONE;
3929
3737 if (params->switch_cfg == SWITCH_CFG_1G) 3930 if (params->switch_cfg == SWITCH_CFG_1G)
3738 vars->phy_flags = PHY_SERDES_FLAG; 3931 vars->phy_flags = PHY_SERDES_FLAG;
3739 else 3932 else
3740 vars->phy_flags = PHY_XGXS_FLAG; 3933 vars->phy_flags = PHY_XGXS_FLAG;
3741 3934
3935
3742 /* disable attentions */ 3936 /* disable attentions */
3743 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 3937 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
3744 (NIG_MASK_XGXS0_LINK_STATUS | 3938 (NIG_MASK_XGXS0_LINK_STATUS |
@@ -3894,6 +4088,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
3894 } 4088 }
3895 4089
3896 bnx2x_link_initialize(params, vars); 4090 bnx2x_link_initialize(params, vars);
4091 msleep(30);
3897 bnx2x_link_int_enable(params); 4092 bnx2x_link_int_enable(params);
3898 } 4093 }
3899 return 0; 4094 return 0;
@@ -3943,39 +4138,22 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
3943 /* HW reset */ 4138 /* HW reset */
3944 4139
3945 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 4140 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3946 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4141 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4142 port);
3947 4143
3948 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4144 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3949 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4145 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4146 port);
3950 4147
3951 DP(NETIF_MSG_LINK, "reset external PHY\n"); 4148 DP(NETIF_MSG_LINK, "reset external PHY\n");
3952 } else { 4149 } else if (ext_phy_type ==
3953 4150 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3954 u8 ext_phy_addr = ((ext_phy_config & 4151 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
3955 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3956 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3957
3958 /* SW reset */
3959 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3960 MDIO_PMA_DEVAD,
3961 MDIO_PMA_REG_CTRL,
3962 1<<15);
3963
3964 /* Set Low Power Mode */
3965 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3966 MDIO_PMA_DEVAD,
3967 MDIO_PMA_REG_CTRL,
3968 1<<11);
3969
3970
3971 if (ext_phy_type ==
3972 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3973 DP(NETIF_MSG_LINK, "Setting 8073 port %d into"
3974 "low power mode\n", 4152 "low power mode\n",
3975 port); 4153 port);
3976 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4154 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3977 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4155 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3978 } 4156 port);
3979 } 4157 }
3980 } 4158 }
3981 /* reset the SerDes/XGXS */ 4159 /* reset the SerDes/XGXS */
@@ -3995,6 +4173,73 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
3995 return 0; 4173 return 0;
3996} 4174}
3997 4175
4176static u8 bnx2x_update_link_down(struct link_params *params,
4177 struct link_vars *vars)
4178{
4179 struct bnx2x *bp = params->bp;
4180 u8 port = params->port;
4181 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
4182 bnx2x_set_led(bp, port, LED_MODE_OFF,
4183 0, params->hw_led_mode,
4184 params->chip_id);
4185
4186 /* indicate no mac active */
4187 vars->mac_type = MAC_TYPE_NONE;
4188
4189 /* update shared memory */
4190 vars->link_status = 0;
4191 vars->line_speed = 0;
4192 bnx2x_update_mng(params, vars->link_status);
4193
4194 /* activate nig drain */
4195 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4196
4197 /* reset BigMac */
4198 bnx2x_bmac_rx_disable(bp, params->port);
4199 REG_WR(bp, GRCBASE_MISC +
4200 MISC_REGISTERS_RESET_REG_2_CLEAR,
4201 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4202 return 0;
4203}
4204
4205static u8 bnx2x_update_link_up(struct link_params *params,
4206 struct link_vars *vars,
4207 u8 link_10g, u32 gp_status)
4208{
4209 struct bnx2x *bp = params->bp;
4210 u8 port = params->port;
4211 u8 rc = 0;
4212 vars->link_status |= LINK_STATUS_LINK_UP;
4213 if (link_10g) {
4214 bnx2x_bmac_enable(params, vars, 0);
4215 bnx2x_set_led(bp, port, LED_MODE_OPER,
4216 SPEED_10000, params->hw_led_mode,
4217 params->chip_id);
4218
4219 } else {
4220 bnx2x_emac_enable(params, vars, 0);
4221 rc = bnx2x_emac_program(params, vars->line_speed,
4222 vars->duplex);
4223
4224 /* AN complete? */
4225 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
4226 if (!(vars->phy_flags &
4227 PHY_SGMII_FLAG))
4228 bnx2x_set_sgmii_tx_driver(params);
4229 }
4230 }
4231
4232 /* PBF - link up */
4233 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
4234 vars->line_speed);
4235
4236 /* disable drain */
4237 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
4238
4239 /* update shared memory */
4240 bnx2x_update_mng(params, vars->link_status);
4241 return rc;
4242}
3998/* This function should called upon link interrupt */ 4243/* This function should called upon link interrupt */
3999/* In case vars->link_up, driver needs to 4244/* In case vars->link_up, driver needs to
4000 1. Update the pbf 4245 1. Update the pbf
@@ -4012,10 +4257,10 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4012{ 4257{
4013 struct bnx2x *bp = params->bp; 4258 struct bnx2x *bp = params->bp;
4014 u8 port = params->port; 4259 u8 port = params->port;
4015 u16 i;
4016 u16 gp_status; 4260 u16 gp_status;
4017 u16 link_10g; 4261 u8 link_10g;
4018 u8 rc = 0; 4262 u8 ext_phy_link_up, rc = 0;
4263 u32 ext_phy_type;
4019 4264
4020 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 4265 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
4021 port, 4266 port,
@@ -4031,15 +4276,16 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4031 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 4276 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
4032 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 4277 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4033 4278
4279 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4034 4280
4035 /* avoid fast toggling */ 4281 /* Check external link change only for non-direct */
4036 for (i = 0; i < 10; i++) { 4282 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars);
4037 msleep(10); 4283
4038 CL45_RD_OVER_CL22(bp, port, params->phy_addr, 4284 /* Read gp_status */
4039 MDIO_REG_BANK_GP_STATUS, 4285 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
4040 MDIO_GP_STATUS_TOP_AN_STATUS1, 4286 MDIO_REG_BANK_GP_STATUS,
4041 &gp_status); 4287 MDIO_GP_STATUS_TOP_AN_STATUS1,
4042 } 4288 &gp_status);
4043 4289
4044 rc = bnx2x_link_settings_status(params, vars, gp_status); 4290 rc = bnx2x_link_settings_status(params, vars, gp_status);
4045 if (rc != 0) 4291 if (rc != 0)
@@ -4055,73 +4301,177 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4055 4301
4056 bnx2x_link_int_ack(params, vars, link_10g); 4302 bnx2x_link_int_ack(params, vars, link_10g);
4057 4303
4304 /* In case external phy link is up, and internal link is down
4305 ( not initialized yet probably after link initialization, it needs
4306 to be initialized.
4307 Note that after link down-up as result of cable plug,
4308 the xgxs link would probably become up again without the need to
4309 initialize it*/
4310
4311 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
4312 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
4313 (ext_phy_link_up && !vars->phy_link_up))
4314 bnx2x_init_internal_phy(params, vars);
4315
4058 /* link is up only if both local phy and external phy are up */ 4316 /* link is up only if both local phy and external phy are up */
4059 vars->link_up = (vars->phy_link_up && 4317 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
4060 bnx2x_ext_phy_is_link_up(params, vars));
4061 4318
4062 if (!vars->phy_link_up && 4319 if (vars->link_up)
4063 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18)) { 4320 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
4064 bnx2x_ext_phy_is_link_up(params, vars); /* Clear interrupt */ 4321 else
4322 rc = bnx2x_update_link_down(params, vars);
4323
4324 return rc;
4325}
4326
4327static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
4328{
4329 u8 ext_phy_addr[PORT_MAX];
4330 u16 val;
4331 s8 port;
4332
4333 /* PART1 - Reset both phys */
4334 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4335 /* Extract the ext phy address for the port */
4336 u32 ext_phy_config = REG_RD(bp, shmem_base +
4337 offsetof(struct shmem_region,
4338 dev_info.port_hw_config[port].external_phy_config));
4339
4340 /* disable attentions */
4341 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
4342 (NIG_MASK_XGXS0_LINK_STATUS |
4343 NIG_MASK_XGXS0_LINK10G |
4344 NIG_MASK_SERDES0_LINK_STATUS |
4345 NIG_MASK_MI_INT));
4346
4347 ext_phy_addr[port] =
4348 ((ext_phy_config &
4349 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4350 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4351
4352 /* Need to take the phy out of low power mode in order
4353 to write to access its registers */
4354 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4355 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
4356
4357 /* Reset the phy */
4358 bnx2x_cl45_write(bp, port,
4359 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4360 ext_phy_addr[port],
4361 MDIO_PMA_DEVAD,
4362 MDIO_PMA_REG_CTRL,
4363 1<<15);
4065 } 4364 }
4066 4365
4067 if (vars->link_up) { 4366 /* Add delay of 150ms after reset */
4068 vars->link_status |= LINK_STATUS_LINK_UP; 4367 msleep(150);
4069 if (link_10g) {
4070 bnx2x_bmac_enable(params, vars, 0);
4071 bnx2x_set_led(bp, port, LED_MODE_OPER,
4072 SPEED_10000, params->hw_led_mode,
4073 params->chip_id);
4074 4368
4075 } else { 4369 /* PART2 - Download firmware to both phys */
4076 bnx2x_emac_enable(params, vars, 0); 4370 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4077 rc = bnx2x_emac_program(params, vars->line_speed, 4371 u16 fw_ver1;
4078 vars->duplex);
4079 4372
4080 /* AN complete? */ 4373 bnx2x_bcm8073_external_rom_boot(bp, port,
4081 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 4374 ext_phy_addr[port]);
4082 if (!(vars->phy_flags & 4375
4083 PHY_SGMII_FLAG)) 4376 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4084 bnx2x_set_sgmii_tx_driver(params); 4377 ext_phy_addr[port],
4085 } 4378 MDIO_PMA_DEVAD,
4379 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
4380 if (fw_ver1 == 0) {
4381 DP(NETIF_MSG_LINK,
4382 "bnx2x_8073_common_init_phy port %x "
4383 "fw Download failed\n", port);
4384 return -EINVAL;
4086 } 4385 }
4087 4386
4088 /* PBF - link up */ 4387 /* Only set bit 10 = 1 (Tx power down) */
4089 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 4388 bnx2x_cl45_read(bp, port,
4090 vars->line_speed); 4389 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4390 ext_phy_addr[port],
4391 MDIO_PMA_DEVAD,
4392 MDIO_PMA_REG_TX_POWER_DOWN, &val);
4091 4393
4092 /* disable drain */ 4394 /* Phase1 of TX_POWER_DOWN reset */
4093 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 4395 bnx2x_cl45_write(bp, port,
4396 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4397 ext_phy_addr[port],
4398 MDIO_PMA_DEVAD,
4399 MDIO_PMA_REG_TX_POWER_DOWN,
4400 (val | 1<<10));
4401 }
4094 4402
4095 /* update shared memory */ 4403 /* Toggle Transmitter: Power down and then up with 600ms
4096 bnx2x_update_mng(params, vars->link_status); 4404 delay between */
4405 msleep(600);
4097 4406
4098 } else { /* link down */ 4407 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
4099 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", params->port); 4408 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4100 bnx2x_set_led(bp, port, LED_MODE_OFF, 4409 /* Phase2 of POWER_DOWN_RESET*/
4101 0, params->hw_led_mode, 4410 /* Release bit 10 (Release Tx power down) */
4102 params->chip_id); 4411 bnx2x_cl45_read(bp, port,
4412 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4413 ext_phy_addr[port],
4414 MDIO_PMA_DEVAD,
4415 MDIO_PMA_REG_TX_POWER_DOWN, &val);
4103 4416
4104 /* indicate no mac active */ 4417 bnx2x_cl45_write(bp, port,
4105 vars->mac_type = MAC_TYPE_NONE; 4418 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4419 ext_phy_addr[port],
4420 MDIO_PMA_DEVAD,
4421 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
4422 msleep(15);
4106 4423
4107 /* update shared memory */ 4424 /* Read modify write the SPI-ROM version select register */
4108 vars->link_status = 0; 4425 bnx2x_cl45_read(bp, port,
4109 bnx2x_update_mng(params, vars->link_status); 4426 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4427 ext_phy_addr[port],
4428 MDIO_PMA_DEVAD,
4429 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
4430 bnx2x_cl45_write(bp, port,
4431 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4432 ext_phy_addr[port],
4433 MDIO_PMA_DEVAD,
4434 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
4110 4435
4111 /* activate nig drain */ 4436 /* set GPIO2 back to LOW */
4112 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 4437 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4438 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
4439 }
4440 return 0;
4113 4441
4114 /* reset BigMac */ 4442}
4115 bnx2x_bmac_rx_disable(bp, params->port);
4116 REG_WR(bp, GRCBASE_MISC +
4117 MISC_REGISTERS_RESET_REG_2_CLEAR,
4118 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4119 4443
4444u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
4445{
4446 u8 rc = 0;
4447 u32 ext_phy_type;
4448
4449 DP(NETIF_MSG_LINK, "bnx2x_common_init_phy\n");
4450
4451 /* Read the ext_phy_type for arbitrary port(0) */
4452 ext_phy_type = XGXS_EXT_PHY_TYPE(
4453 REG_RD(bp, shmem_base +
4454 offsetof(struct shmem_region,
4455 dev_info.port_hw_config[0].external_phy_config)));
4456
4457 switch (ext_phy_type) {
4458 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4459 {
4460 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
4461 break;
4462 }
4463 default:
4464 DP(NETIF_MSG_LINK,
4465 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
4466 ext_phy_type);
4467 break;
4120 } 4468 }
4121 4469
4122 return rc; 4470 return rc;
4123} 4471}
4124 4472
4473
4474
4125static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr) 4475static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
4126{ 4476{
4127 u16 val, cnt; 4477 u16 val, cnt;
@@ -4154,7 +4504,7 @@ static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
4154} 4504}
4155#define RESERVED_SIZE 256 4505#define RESERVED_SIZE 256
4156/* max application is 160K bytes - data at end of RAM */ 4506/* max application is 160K bytes - data at end of RAM */
4157#define MAX_APP_SIZE 160*1024 - RESERVED_SIZE 4507#define MAX_APP_SIZE (160*1024 - RESERVED_SIZE)
4158 4508
4159/* Header is 14 bytes */ 4509/* Header is 14 bytes */
4160#define HEADER_SIZE 14 4510#define HEADER_SIZE 14
@@ -4192,12 +4542,12 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4192 size = MAX_APP_SIZE+HEADER_SIZE; 4542 size = MAX_APP_SIZE+HEADER_SIZE;
4193 } 4543 }
4194 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]); 4544 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
4195 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]); 4545 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
4196 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1 4546 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
4197 and issuing a reset.*/ 4547 and issuing a reset.*/
4198 4548
4199 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 4549 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4200 MISC_REGISTERS_GPIO_HIGH); 4550 MISC_REGISTERS_GPIO_HIGH, port);
4201 4551
4202 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); 4552 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4203 4553
@@ -4429,7 +4779,8 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4429 } 4779 }
4430 4780
4431 /* DSP Remove Download Mode */ 4781 /* DSP Remove Download Mode */
4432 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW); 4782 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4783 MISC_REGISTERS_GPIO_LOW, port);
4433 4784
4434 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); 4785 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4435 4786
@@ -4437,7 +4788,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4437 for (cnt = 0; cnt < 100; cnt++) 4788 for (cnt = 0; cnt < 100; cnt++)
4438 msleep(5); 4789 msleep(5);
4439 4790
4440 bnx2x_hw_reset(bp); 4791 bnx2x_hw_reset(bp, port);
4441 4792
4442 for (cnt = 0; cnt < 100; cnt++) 4793 for (cnt = 0; cnt < 100; cnt++)
4443 msleep(5); 4794 msleep(5);
@@ -4473,7 +4824,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4473 MDIO_PMA_REG_7101_VER2, 4824 MDIO_PMA_REG_7101_VER2,
4474 &image_revision2); 4825 &image_revision2);
4475 4826
4476 if (data[0x14e] != (image_revision2&0xFF) || 4827 if (data[0x14e] != (image_revision2&0xFF) ||
4477 data[0x14f] != ((image_revision2&0xFF00)>>8) || 4828 data[0x14f] != ((image_revision2&0xFF00)>>8) ||
4478 data[0x150] != (image_revision1&0xFF) || 4829 data[0x150] != (image_revision1&0xFF) ||
4479 data[0x151] != ((image_revision1&0xFF00)>>8)) { 4830 data[0x151] != ((image_revision1&0xFF00)>>8)) {
@@ -4508,11 +4859,11 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
4508 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 4859 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4509 /* Take ext phy out of reset */ 4860 /* Take ext phy out of reset */
4510 if (!driver_loaded) 4861 if (!driver_loaded)
4511 bnx2x_turn_on_sf(bp, port, ext_phy_addr); 4862 bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
4512 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr, 4863 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
4513 data, size); 4864 data, size);
4514 if (!driver_loaded) 4865 if (!driver_loaded)
4515 bnx2x_turn_off_sf(bp); 4866 bnx2x_turn_off_sf(bp, port);
4516 break; 4867 break;
4517 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 4868 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 4869 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
diff --git a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h
index 714d37ac95de..86d54a17b411 100644
--- a/drivers/net/bnx2x_link.h
+++ b/drivers/net/bnx2x_link.h
@@ -55,14 +55,17 @@ struct link_params {
55#define LOOPBACK_BMAC 2 55#define LOOPBACK_BMAC 2
56#define LOOPBACK_XGXS_10 3 56#define LOOPBACK_XGXS_10 3
57#define LOOPBACK_EXT_PHY 4 57#define LOOPBACK_EXT_PHY 4
58#define LOOPBACK_EXT 5
58 59
59 u16 req_duplex; 60 u16 req_duplex;
60 u16 req_flow_ctrl; 61 u16 req_flow_ctrl;
62 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
63 req_flow_ctrl is set to AUTO */
61 u16 req_line_speed; /* Also determine AutoNeg */ 64 u16 req_line_speed; /* Also determine AutoNeg */
62 65
63 /* Device parameters */ 66 /* Device parameters */
64 u8 mac_addr[6]; 67 u8 mac_addr[6];
65 u16 mtu; 68
66 69
67 70
68 /* shmem parameters */ 71 /* shmem parameters */
@@ -140,7 +143,7 @@ u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
140 u8 phy_addr, u8 devad, u16 reg, u16 val); 143 u8 phy_addr, u8 devad, u16 reg, u16 val);
141 144
142/* Reads the link_status from the shmem, 145/* Reads the link_status from the shmem,
143 and update the link vars accordinaly */ 146 and update the link vars accordingly */
144void bnx2x_link_status_update(struct link_params *input, 147void bnx2x_link_status_update(struct link_params *input,
145 struct link_vars *output); 148 struct link_vars *output);
146/* returns string representing the fw_version of the external phy */ 149/* returns string representing the fw_version of the external phy */
@@ -149,7 +152,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
149 152
150/* Set/Unset the led 153/* Set/Unset the led
151 Basically, the CLC takes care of the led for the link, but in case one needs 154 Basically, the CLC takes care of the led for the link, but in case one needs
152 to set/unset the led unnatually, set the "mode" to LED_MODE_OPER to 155 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
153 blink the led, and LED_MODE_OFF to set the led off.*/ 156 blink the led, and LED_MODE_OFF to set the led off.*/
154u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, 157u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
155 u16 hw_led_mode, u32 chip_id); 158 u16 hw_led_mode, u32 chip_id);
@@ -164,5 +167,7 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
164 otherwise link is down*/ 167 otherwise link is down*/
165u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); 168u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
166 169
170/* One-time initialization for external phy after power up */
171u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
167 172
168#endif /* BNX2X_LINK_H */ 173#endif /* BNX2X_LINK_H */
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 272a4bd25953..971576b43687 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -44,7 +44,6 @@
44#include <net/ip.h> 44#include <net/ip.h>
45#include <net/tcp.h> 45#include <net/tcp.h>
46#include <net/checksum.h> 46#include <net/checksum.h>
47#include <linux/version.h>
48#include <net/ip6_checksum.h> 47#include <net/ip6_checksum.h>
49#include <linux/workqueue.h> 48#include <linux/workqueue.h>
50#include <linux/crc32.h> 49#include <linux/crc32.h>
@@ -60,8 +59,8 @@
60#include "bnx2x.h" 59#include "bnx2x.h"
61#include "bnx2x_init.h" 60#include "bnx2x_init.h"
62 61
63#define DRV_MODULE_VERSION "1.45.6" 62#define DRV_MODULE_VERSION "1.45.17"
64#define DRV_MODULE_RELDATE "2008/06/23" 63#define DRV_MODULE_RELDATE "2008/08/13"
65#define BNX2X_BC_VER 0x040200 64#define BNX2X_BC_VER 0x040200
66 65
67/* Time in jiffies before concluding the transmitter is hung */ 66/* Time in jiffies before concluding the transmitter is hung */
@@ -76,23 +75,21 @@ MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
76MODULE_LICENSE("GPL"); 75MODULE_LICENSE("GPL");
77MODULE_VERSION(DRV_MODULE_VERSION); 76MODULE_VERSION(DRV_MODULE_VERSION);
78 77
78static int disable_tpa;
79static int use_inta; 79static int use_inta;
80static int poll; 80static int poll;
81static int debug; 81static int debug;
82static int disable_tpa;
83static int nomcp;
84static int load_count[3]; /* 0-common, 1-port0, 2-port1 */ 82static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
85static int use_multi; 83static int use_multi;
86 84
85module_param(disable_tpa, int, 0);
87module_param(use_inta, int, 0); 86module_param(use_inta, int, 0);
88module_param(poll, int, 0); 87module_param(poll, int, 0);
89module_param(debug, int, 0); 88module_param(debug, int, 0);
90module_param(disable_tpa, int, 0); 89MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
91module_param(nomcp, int, 0);
92MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); 90MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
93MODULE_PARM_DESC(poll, "use polling (for debug)"); 91MODULE_PARM_DESC(poll, "use polling (for debug)");
94MODULE_PARM_DESC(debug, "default debug msglevel"); 92MODULE_PARM_DESC(debug, "default debug msglevel");
95MODULE_PARM_DESC(nomcp, "ignore management CPU");
96 93
97#ifdef BNX2X_MULTI 94#ifdef BNX2X_MULTI
98module_param(use_multi, int, 0); 95module_param(use_multi, int, 0);
@@ -237,17 +234,16 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
237 while (*wb_comp != DMAE_COMP_VAL) { 234 while (*wb_comp != DMAE_COMP_VAL) {
238 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 235 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
239 236
240 /* adjust delay for emulation/FPGA */
241 if (CHIP_REV_IS_SLOW(bp))
242 msleep(100);
243 else
244 udelay(5);
245
246 if (!cnt) { 237 if (!cnt) {
247 BNX2X_ERR("dmae timeout!\n"); 238 BNX2X_ERR("dmae timeout!\n");
248 break; 239 break;
249 } 240 }
250 cnt--; 241 cnt--;
242 /* adjust delay for emulation/FPGA */
243 if (CHIP_REV_IS_SLOW(bp))
244 msleep(100);
245 else
246 udelay(5);
251 } 247 }
252 248
253 mutex_unlock(&bp->dmae_mutex); 249 mutex_unlock(&bp->dmae_mutex);
@@ -310,17 +306,16 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
310 306
311 while (*wb_comp != DMAE_COMP_VAL) { 307 while (*wb_comp != DMAE_COMP_VAL) {
312 308
313 /* adjust delay for emulation/FPGA */
314 if (CHIP_REV_IS_SLOW(bp))
315 msleep(100);
316 else
317 udelay(5);
318
319 if (!cnt) { 309 if (!cnt) {
320 BNX2X_ERR("dmae timeout!\n"); 310 BNX2X_ERR("dmae timeout!\n");
321 break; 311 break;
322 } 312 }
323 cnt--; 313 cnt--;
314 /* adjust delay for emulation/FPGA */
315 if (CHIP_REV_IS_SLOW(bp))
316 msleep(100);
317 else
318 udelay(5);
324 } 319 }
325 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", 320 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
326 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 321 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
@@ -503,6 +498,9 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
503 int i; 498 int i;
504 u16 j, start, end; 499 u16 j, start, end;
505 500
501 bp->stats_state = STATS_STATE_DISABLED;
502 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
503
506 BNX2X_ERR("begin crash dump -----------------\n"); 504 BNX2X_ERR("begin crash dump -----------------\n");
507 505
508 for_each_queue(bp, i) { 506 for_each_queue(bp, i) {
@@ -513,17 +511,20 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
513 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n", 511 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
514 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod, 512 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
515 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb)); 513 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
516 BNX2X_ERR(" rx_comp_prod(%x) rx_comp_cons(%x)" 514 BNX2X_ERR(" rx_bd_prod(%x) rx_bd_cons(%x)"
517 " *rx_cons_sb(%x) *rx_bd_cons_sb(%x)" 515 " *rx_bd_cons_sb(%x) rx_comp_prod(%x)"
518 " rx_sge_prod(%x) last_max_sge(%x)\n", 516 " rx_comp_cons(%x) *rx_cons_sb(%x)\n",
519 fp->rx_comp_prod, fp->rx_comp_cons, 517 fp->rx_bd_prod, fp->rx_bd_cons,
520 le16_to_cpu(*fp->rx_cons_sb), 518 le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
521 le16_to_cpu(*fp->rx_bd_cons_sb), 519 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
522 fp->rx_sge_prod, fp->last_max_sge); 520 BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)"
523 BNX2X_ERR(" fp_c_idx(%x) fp_u_idx(%x)" 521 " fp_c_idx(%x) *sb_c_idx(%x) fp_u_idx(%x)"
524 " bd data(%x,%x) rx_alloc_failed(%lx)\n", 522 " *sb_u_idx(%x) bd data(%x,%x)\n",
525 fp->fp_c_idx, fp->fp_u_idx, hw_prods->packets_prod, 523 fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
526 hw_prods->bds_prod, fp->rx_alloc_failed); 524 fp->status_blk->c_status_block.status_block_index,
525 fp->fp_u_idx,
526 fp->status_blk->u_status_block.status_block_index,
527 hw_prods->packets_prod, hw_prods->bds_prod);
527 528
528 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10); 529 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245); 530 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
@@ -553,8 +554,8 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
553 j, rx_bd[1], rx_bd[0], sw_bd->skb); 554 j, rx_bd[1], rx_bd[0], sw_bd->skb);
554 } 555 }
555 556
556 start = 0; 557 start = RX_SGE(fp->rx_sge_prod);
557 end = RX_SGE_CNT*NUM_RX_SGE_PAGES; 558 end = RX_SGE(fp->last_max_sge);
558 for (j = start; j < end; j++) { 559 for (j = start; j < end; j++) {
559 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 560 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 561 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
@@ -582,9 +583,6 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
582 bnx2x_fw_dump(bp); 583 bnx2x_fw_dump(bp);
583 bnx2x_mc_assert(bp); 584 bnx2x_mc_assert(bp);
584 BNX2X_ERR("end crash dump -----------------\n"); 585 BNX2X_ERR("end crash dump -----------------\n");
585
586 bp->stats_state = STATS_STATE_DISABLED;
587 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
588} 586}
589 587
590static void bnx2x_int_enable(struct bnx2x *bp) 588static void bnx2x_int_enable(struct bnx2x *bp)
@@ -684,7 +682,8 @@ static void bnx2x_int_disable_sync(struct bnx2x *bp)
684static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id, 682static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
685 u8 storm, u16 index, u8 op, u8 update) 683 u8 storm, u16 index, u8 op, u8 update)
686{ 684{
687 u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 685 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
686 COMMAND_REG_INT_ACK);
688 struct igu_ack_register igu_ack; 687 struct igu_ack_register igu_ack;
689 688
690 igu_ack.status_block_index = index; 689 igu_ack.status_block_index = index;
@@ -694,9 +693,9 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
694 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 693 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
695 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 694 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
696 695
697 DP(BNX2X_MSG_OFF, "write 0x%08x to IGU addr 0x%x\n", 696 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
698 (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); 697 (*(u32 *)&igu_ack), hc_addr);
699 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack)); 698 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
700} 699}
701 700
702static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 701static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
@@ -716,36 +715,15 @@ static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
716 return rc; 715 return rc;
717} 716}
718 717
719static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
720{
721 u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
722
723 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
724 rx_cons_sb++;
725
726 if ((fp->rx_comp_cons != rx_cons_sb) ||
727 (fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) ||
728 (fp->tx_pkt_prod != fp->tx_pkt_cons))
729 return 1;
730
731 return 0;
732}
733
734static u16 bnx2x_ack_int(struct bnx2x *bp) 718static u16 bnx2x_ack_int(struct bnx2x *bp)
735{ 719{
736 u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 720 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
737 u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr); 721 COMMAND_REG_SIMD_MASK);
722 u32 result = REG_RD(bp, hc_addr);
738 723
739 DP(BNX2X_MSG_OFF, "read 0x%08x from IGU addr 0x%x\n", 724 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
740 result, BAR_IGU_INTMEM + igu_addr); 725 result, hc_addr);
741 726
742#ifdef IGU_DEBUG
743#warning IGU_DEBUG active
744 if (result == 0) {
745 BNX2X_ERR("read %x from IGU\n", result);
746 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
747 }
748#endif
749 return result; 727 return result;
750} 728}
751 729
@@ -898,6 +876,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
898 netif_tx_lock(bp->dev); 876 netif_tx_lock(bp->dev);
899 877
900 if (netif_queue_stopped(bp->dev) && 878 if (netif_queue_stopped(bp->dev) &&
879 (bp->state == BNX2X_STATE_OPEN) &&
901 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)) 880 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
902 netif_wake_queue(bp->dev); 881 netif_wake_queue(bp->dev);
903 882
@@ -905,6 +884,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
905 } 884 }
906} 885}
907 886
887
908static void bnx2x_sp_event(struct bnx2x_fastpath *fp, 888static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
909 union eth_rx_cqe *rr_cqe) 889 union eth_rx_cqe *rr_cqe)
910{ 890{
@@ -960,6 +940,7 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
960 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED; 940 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
961 break; 941 break;
962 942
943
963 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): 944 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
964 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG): 945 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
965 DP(NETIF_MSG_IFUP, "got set mac ramrod\n"); 946 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
@@ -1169,8 +1150,8 @@ static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1169 memset(fp->sge_mask, 0xff, 1150 memset(fp->sge_mask, 0xff,
1170 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64)); 1151 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1171 1152
1172 /* Clear the two last indeces in the page to 1: 1153 /* Clear the two last indices in the page to 1:
1173 these are the indeces that correspond to the "next" element, 1154 these are the indices that correspond to the "next" element,
1174 hence will never be indicated and should be removed from 1155 hence will never be indicated and should be removed from
1175 the calculations. */ 1156 the calculations. */
1176 bnx2x_clear_sge_mask_next_elems(fp); 1157 bnx2x_clear_sge_mask_next_elems(fp);
@@ -1261,7 +1242,7 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1261 where we are and drop the whole packet */ 1242 where we are and drop the whole packet */
1262 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx); 1243 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1263 if (unlikely(err)) { 1244 if (unlikely(err)) {
1264 fp->rx_alloc_failed++; 1245 bp->eth_stats.rx_skb_alloc_failed++;
1265 return err; 1246 return err;
1266 } 1247 }
1267 1248
@@ -1297,14 +1278,13 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1297 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), 1278 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1298 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 1279 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1299 1280
1300 /* if alloc failed drop the packet and keep the buffer in the bin */
1301 if (likely(new_skb)) { 1281 if (likely(new_skb)) {
1282 /* fix ip xsum and give it to the stack */
1283 /* (no need to map the new skb) */
1302 1284
1303 prefetch(skb); 1285 prefetch(skb);
1304 prefetch(((char *)(skb)) + 128); 1286 prefetch(((char *)(skb)) + 128);
1305 1287
1306 /* else fix ip xsum and give it to the stack */
1307 /* (no need to map the new skb) */
1308#ifdef BNX2X_STOP_ON_ERROR 1288#ifdef BNX2X_STOP_ON_ERROR
1309 if (pad + len > bp->rx_buf_size) { 1289 if (pad + len > bp->rx_buf_size) {
1310 BNX2X_ERR("skb_put is about to fail... " 1290 BNX2X_ERR("skb_put is about to fail... "
@@ -1353,9 +1333,10 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1353 fp->tpa_pool[queue].skb = new_skb; 1333 fp->tpa_pool[queue].skb = new_skb;
1354 1334
1355 } else { 1335 } else {
1336 /* else drop the packet and keep the buffer in the bin */
1356 DP(NETIF_MSG_RX_STATUS, 1337 DP(NETIF_MSG_RX_STATUS,
1357 "Failed to allocate new skb - dropping packet!\n"); 1338 "Failed to allocate new skb - dropping packet!\n");
1358 fp->rx_alloc_failed++; 1339 bp->eth_stats.rx_skb_alloc_failed++;
1359 } 1340 }
1360 1341
1361 fp->tpa_state[queue] = BNX2X_TPA_STOP; 1342 fp->tpa_state[queue] = BNX2X_TPA_STOP;
@@ -1390,7 +1371,6 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1390 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons; 1371 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1391 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod; 1372 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1392 int rx_pkt = 0; 1373 int rx_pkt = 0;
1393 u16 queue;
1394 1374
1395#ifdef BNX2X_STOP_ON_ERROR 1375#ifdef BNX2X_STOP_ON_ERROR
1396 if (unlikely(bp->panic)) 1376 if (unlikely(bp->panic))
@@ -1456,7 +1436,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1456 if ((!fp->disable_tpa) && 1436 if ((!fp->disable_tpa) &&
1457 (TPA_TYPE(cqe_fp_flags) != 1437 (TPA_TYPE(cqe_fp_flags) !=
1458 (TPA_TYPE_START | TPA_TYPE_END))) { 1438 (TPA_TYPE_START | TPA_TYPE_END))) {
1459 queue = cqe->fast_path_cqe.queue_index; 1439 u16 queue = cqe->fast_path_cqe.queue_index;
1460 1440
1461 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) { 1441 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1462 DP(NETIF_MSG_RX_STATUS, 1442 DP(NETIF_MSG_RX_STATUS,
@@ -1503,11 +1483,10 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1503 1483
1504 /* is this an error packet? */ 1484 /* is this an error packet? */
1505 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) { 1485 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1506 /* do we sometimes forward error packets anyway? */
1507 DP(NETIF_MSG_RX_ERR, 1486 DP(NETIF_MSG_RX_ERR,
1508 "ERROR flags %x rx packet %u\n", 1487 "ERROR flags %x rx packet %u\n",
1509 cqe_fp_flags, sw_comp_cons); 1488 cqe_fp_flags, sw_comp_cons);
1510 /* TBD make sure MC counts this as a drop */ 1489 bp->eth_stats.rx_err_discard_pkt++;
1511 goto reuse_rx; 1490 goto reuse_rx;
1512 } 1491 }
1513 1492
@@ -1524,7 +1503,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1524 DP(NETIF_MSG_RX_ERR, 1503 DP(NETIF_MSG_RX_ERR,
1525 "ERROR packet dropped " 1504 "ERROR packet dropped "
1526 "because of alloc failure\n"); 1505 "because of alloc failure\n");
1527 fp->rx_alloc_failed++; 1506 bp->eth_stats.rx_skb_alloc_failed++;
1528 goto reuse_rx; 1507 goto reuse_rx;
1529 } 1508 }
1530 1509
@@ -1550,7 +1529,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1550 DP(NETIF_MSG_RX_ERR, 1529 DP(NETIF_MSG_RX_ERR,
1551 "ERROR packet dropped because " 1530 "ERROR packet dropped because "
1552 "of alloc failure\n"); 1531 "of alloc failure\n");
1553 fp->rx_alloc_failed++; 1532 bp->eth_stats.rx_skb_alloc_failed++;
1554reuse_rx: 1533reuse_rx:
1555 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod); 1534 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1556 goto next_rx; 1535 goto next_rx;
@@ -1559,10 +1538,12 @@ reuse_rx:
1559 skb->protocol = eth_type_trans(skb, bp->dev); 1538 skb->protocol = eth_type_trans(skb, bp->dev);
1560 1539
1561 skb->ip_summed = CHECKSUM_NONE; 1540 skb->ip_summed = CHECKSUM_NONE;
1562 if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe)) 1541 if (bp->rx_csum) {
1563 skb->ip_summed = CHECKSUM_UNNECESSARY; 1542 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1564 1543 skb->ip_summed = CHECKSUM_UNNECESSARY;
1565 /* TBD do we pass bad csum packets in promisc */ 1544 else
1545 bp->eth_stats.hw_csum_err++;
1546 }
1566 } 1547 }
1567 1548
1568#ifdef BCM_VLAN 1549#ifdef BCM_VLAN
@@ -1615,6 +1596,12 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1615 struct net_device *dev = bp->dev; 1596 struct net_device *dev = bp->dev;
1616 int index = FP_IDX(fp); 1597 int index = FP_IDX(fp);
1617 1598
1599 /* Return here if interrupt is disabled */
1600 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1601 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1602 return IRQ_HANDLED;
1603 }
1604
1618 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n", 1605 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1619 index, FP_SB_ID(fp)); 1606 index, FP_SB_ID(fp));
1620 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0); 1607 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
@@ -1648,17 +1635,17 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1648 } 1635 }
1649 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status); 1636 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status);
1650 1637
1651#ifdef BNX2X_STOP_ON_ERROR
1652 if (unlikely(bp->panic))
1653 return IRQ_HANDLED;
1654#endif
1655
1656 /* Return here if interrupt is disabled */ 1638 /* Return here if interrupt is disabled */
1657 if (unlikely(atomic_read(&bp->intr_sem) != 0)) { 1639 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1658 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); 1640 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1659 return IRQ_HANDLED; 1641 return IRQ_HANDLED;
1660 } 1642 }
1661 1643
1644#ifdef BNX2X_STOP_ON_ERROR
1645 if (unlikely(bp->panic))
1646 return IRQ_HANDLED;
1647#endif
1648
1662 mask = 0x2 << bp->fp[0].sb_id; 1649 mask = 0x2 << bp->fp[0].sb_id;
1663 if (status & mask) { 1650 if (status & mask) {
1664 struct bnx2x_fastpath *fp = &bp->fp[0]; 1651 struct bnx2x_fastpath *fp = &bp->fp[0];
@@ -1699,11 +1686,12 @@ static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1699 * General service functions 1686 * General service functions
1700 */ 1687 */
1701 1688
1702static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) 1689static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1703{ 1690{
1704 u32 lock_status; 1691 u32 lock_status;
1705 u32 resource_bit = (1 << resource); 1692 u32 resource_bit = (1 << resource);
1706 u8 port = BP_PORT(bp); 1693 int func = BP_FUNC(bp);
1694 u32 hw_lock_control_reg;
1707 int cnt; 1695 int cnt;
1708 1696
1709 /* Validating that the resource is within range */ 1697 /* Validating that the resource is within range */
@@ -1714,8 +1702,15 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1714 return -EINVAL; 1702 return -EINVAL;
1715 } 1703 }
1716 1704
1705 if (func <= 5) {
1706 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1707 } else {
1708 hw_lock_control_reg =
1709 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1710 }
1711
1717 /* Validating that the resource is not already taken */ 1712 /* Validating that the resource is not already taken */
1718 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); 1713 lock_status = REG_RD(bp, hw_lock_control_reg);
1719 if (lock_status & resource_bit) { 1714 if (lock_status & resource_bit) {
1720 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1715 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1721 lock_status, resource_bit); 1716 lock_status, resource_bit);
@@ -1725,9 +1720,8 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1725 /* Try for 1 second every 5ms */ 1720 /* Try for 1 second every 5ms */
1726 for (cnt = 0; cnt < 200; cnt++) { 1721 for (cnt = 0; cnt < 200; cnt++) {
1727 /* Try to acquire the lock */ 1722 /* Try to acquire the lock */
1728 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4, 1723 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1729 resource_bit); 1724 lock_status = REG_RD(bp, hw_lock_control_reg);
1730 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1731 if (lock_status & resource_bit) 1725 if (lock_status & resource_bit)
1732 return 0; 1726 return 0;
1733 1727
@@ -1737,11 +1731,12 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1737 return -EAGAIN; 1731 return -EAGAIN;
1738} 1732}
1739 1733
1740static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource) 1734static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1741{ 1735{
1742 u32 lock_status; 1736 u32 lock_status;
1743 u32 resource_bit = (1 << resource); 1737 u32 resource_bit = (1 << resource);
1744 u8 port = BP_PORT(bp); 1738 int func = BP_FUNC(bp);
1739 u32 hw_lock_control_reg;
1745 1740
1746 /* Validating that the resource is within range */ 1741 /* Validating that the resource is within range */
1747 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1742 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -1751,20 +1746,27 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1751 return -EINVAL; 1746 return -EINVAL;
1752 } 1747 }
1753 1748
1749 if (func <= 5) {
1750 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1751 } else {
1752 hw_lock_control_reg =
1753 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1754 }
1755
1754 /* Validating that the resource is currently taken */ 1756 /* Validating that the resource is currently taken */
1755 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); 1757 lock_status = REG_RD(bp, hw_lock_control_reg);
1756 if (!(lock_status & resource_bit)) { 1758 if (!(lock_status & resource_bit)) {
1757 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1759 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1758 lock_status, resource_bit); 1760 lock_status, resource_bit);
1759 return -EFAULT; 1761 return -EFAULT;
1760 } 1762 }
1761 1763
1762 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit); 1764 REG_WR(bp, hw_lock_control_reg, resource_bit);
1763 return 0; 1765 return 0;
1764} 1766}
1765 1767
1766/* HW Lock for shared dual port PHYs */ 1768/* HW Lock for shared dual port PHYs */
1767static void bnx2x_phy_hw_lock(struct bnx2x *bp) 1769static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1768{ 1770{
1769 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 1771 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1770 1772
@@ -1772,25 +1774,25 @@ static void bnx2x_phy_hw_lock(struct bnx2x *bp)
1772 1774
1773 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || 1775 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1774 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) 1776 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1775 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); 1777 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1776} 1778}
1777 1779
1778static void bnx2x_phy_hw_unlock(struct bnx2x *bp) 1780static void bnx2x_release_phy_lock(struct bnx2x *bp)
1779{ 1781{
1780 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 1782 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1781 1783
1782 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || 1784 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1783 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) 1785 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1784 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO); 1786 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1785 1787
1786 mutex_unlock(&bp->port.phy_mutex); 1788 mutex_unlock(&bp->port.phy_mutex);
1787} 1789}
1788 1790
1789int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) 1791int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1790{ 1792{
1791 /* The GPIO should be swapped if swap register is set and active */ 1793 /* The GPIO should be swapped if swap register is set and active */
1792 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1794 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1793 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp); 1795 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1794 int gpio_shift = gpio_num + 1796 int gpio_shift = gpio_num +
1795 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1797 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1796 u32 gpio_mask = (1 << gpio_shift); 1798 u32 gpio_mask = (1 << gpio_shift);
@@ -1801,7 +1803,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1801 return -EINVAL; 1803 return -EINVAL;
1802 } 1804 }
1803 1805
1804 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1806 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1805 /* read GPIO and mask except the float bits */ 1807 /* read GPIO and mask except the float bits */
1806 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1808 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1807 1809
@@ -1822,7 +1824,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1822 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1824 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1823 break; 1825 break;
1824 1826
1825 case MISC_REGISTERS_GPIO_INPUT_HI_Z : 1827 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1826 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1828 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1827 gpio_num, gpio_shift); 1829 gpio_num, gpio_shift);
1828 /* set FLOAT */ 1830 /* set FLOAT */
@@ -1834,7 +1836,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1834 } 1836 }
1835 1837
1836 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1838 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1837 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO); 1839 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1838 1840
1839 return 0; 1841 return 0;
1840} 1842}
@@ -1850,19 +1852,19 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1850 return -EINVAL; 1852 return -EINVAL;
1851 } 1853 }
1852 1854
1853 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 1855 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1854 /* read SPIO and mask except the float bits */ 1856 /* read SPIO and mask except the float bits */
1855 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 1857 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1856 1858
1857 switch (mode) { 1859 switch (mode) {
1858 case MISC_REGISTERS_SPIO_OUTPUT_LOW : 1860 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1859 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 1861 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1860 /* clear FLOAT and set CLR */ 1862 /* clear FLOAT and set CLR */
1861 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 1863 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1862 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 1864 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1863 break; 1865 break;
1864 1866
1865 case MISC_REGISTERS_SPIO_OUTPUT_HIGH : 1867 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1866 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 1868 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1867 /* clear FLOAT and set SET */ 1869 /* clear FLOAT and set SET */
1868 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 1870 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
@@ -1880,7 +1882,7 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1880 } 1882 }
1881 1883
1882 REG_WR(bp, MISC_REG_SPIO, spio_reg); 1884 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1883 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO); 1885 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1884 1886
1885 return 0; 1887 return 0;
1886} 1888}
@@ -1940,46 +1942,63 @@ static void bnx2x_link_report(struct bnx2x *bp)
1940 1942
1941static u8 bnx2x_initial_phy_init(struct bnx2x *bp) 1943static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1942{ 1944{
1943 u8 rc; 1945 if (!BP_NOMCP(bp)) {
1946 u8 rc;
1944 1947
1945 /* Initialize link parameters structure variables */ 1948 /* Initialize link parameters structure variables */
1946 bp->link_params.mtu = bp->dev->mtu; 1949 /* It is recommended to turn off RX FC for jumbo frames
1950 for better performance */
1951 if (IS_E1HMF(bp))
1952 bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
1953 else if (bp->dev->mtu > 5000)
1954 bp->link_params.req_fc_auto_adv = FLOW_CTRL_TX;
1955 else
1956 bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
1947 1957
1948 bnx2x_phy_hw_lock(bp); 1958 bnx2x_acquire_phy_lock(bp);
1949 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1959 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1950 bnx2x_phy_hw_unlock(bp); 1960 bnx2x_release_phy_lock(bp);
1951 1961
1952 if (bp->link_vars.link_up) 1962 if (bp->link_vars.link_up)
1953 bnx2x_link_report(bp); 1963 bnx2x_link_report(bp);
1954 1964
1955 bnx2x_calc_fc_adv(bp); 1965 bnx2x_calc_fc_adv(bp);
1956 1966
1957 return rc; 1967 return rc;
1968 }
1969 BNX2X_ERR("Bootcode is missing -not initializing link\n");
1970 return -EINVAL;
1958} 1971}
1959 1972
1960static void bnx2x_link_set(struct bnx2x *bp) 1973static void bnx2x_link_set(struct bnx2x *bp)
1961{ 1974{
1962 bnx2x_phy_hw_lock(bp); 1975 if (!BP_NOMCP(bp)) {
1963 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1976 bnx2x_acquire_phy_lock(bp);
1964 bnx2x_phy_hw_unlock(bp); 1977 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1978 bnx2x_release_phy_lock(bp);
1965 1979
1966 bnx2x_calc_fc_adv(bp); 1980 bnx2x_calc_fc_adv(bp);
1981 } else
1982 BNX2X_ERR("Bootcode is missing -not setting link\n");
1967} 1983}
1968 1984
1969static void bnx2x__link_reset(struct bnx2x *bp) 1985static void bnx2x__link_reset(struct bnx2x *bp)
1970{ 1986{
1971 bnx2x_phy_hw_lock(bp); 1987 if (!BP_NOMCP(bp)) {
1972 bnx2x_link_reset(&bp->link_params, &bp->link_vars); 1988 bnx2x_acquire_phy_lock(bp);
1973 bnx2x_phy_hw_unlock(bp); 1989 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
1990 bnx2x_release_phy_lock(bp);
1991 } else
1992 BNX2X_ERR("Bootcode is missing -not resetting link\n");
1974} 1993}
1975 1994
1976static u8 bnx2x_link_test(struct bnx2x *bp) 1995static u8 bnx2x_link_test(struct bnx2x *bp)
1977{ 1996{
1978 u8 rc; 1997 u8 rc;
1979 1998
1980 bnx2x_phy_hw_lock(bp); 1999 bnx2x_acquire_phy_lock(bp);
1981 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars); 2000 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
1982 bnx2x_phy_hw_unlock(bp); 2001 bnx2x_release_phy_lock(bp);
1983 2002
1984 return rc; 2003 return rc;
1985} 2004}
@@ -1991,7 +2010,7 @@ static u8 bnx2x_link_test(struct bnx2x *bp)
1991 sum of vn_min_rates 2010 sum of vn_min_rates
1992 or 2011 or
1993 0 - if all the min_rates are 0. 2012 0 - if all the min_rates are 0.
1994 In the later case fainess algorithm should be deactivated. 2013 In the later case fairness algorithm should be deactivated.
1995 If not all min_rates are zero then those that are zeroes will 2014 If not all min_rates are zero then those that are zeroes will
1996 be set to 1. 2015 be set to 1.
1997 */ 2016 */
@@ -2114,7 +2133,7 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2114 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2133 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2115 /* If FAIRNESS is enabled (not all min rates are zeroes) and 2134 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2116 if current min rate is zero - set it to 1. 2135 if current min rate is zero - set it to 1.
2117 This is a requirment of the algorithm. */ 2136 This is a requirement of the algorithm. */
2118 if ((vn_min_rate == 0) && wsum) 2137 if ((vn_min_rate == 0) && wsum)
2119 vn_min_rate = DEF_MIN_RATE; 2138 vn_min_rate = DEF_MIN_RATE;
2120 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 2139 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
@@ -2203,9 +2222,9 @@ static void bnx2x_link_attn(struct bnx2x *bp)
2203 /* Make sure that we are synced with the current statistics */ 2222 /* Make sure that we are synced with the current statistics */
2204 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2223 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2205 2224
2206 bnx2x_phy_hw_lock(bp); 2225 bnx2x_acquire_phy_lock(bp);
2207 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2226 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2208 bnx2x_phy_hw_unlock(bp); 2227 bnx2x_release_phy_lock(bp);
2209 2228
2210 if (bp->link_vars.link_up) { 2229 if (bp->link_vars.link_up) {
2211 2230
@@ -2357,7 +2376,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2357} 2376}
2358 2377
2359/* acquire split MCP access lock register */ 2378/* acquire split MCP access lock register */
2360static int bnx2x_lock_alr(struct bnx2x *bp) 2379static int bnx2x_acquire_alr(struct bnx2x *bp)
2361{ 2380{
2362 u32 i, j, val; 2381 u32 i, j, val;
2363 int rc = 0; 2382 int rc = 0;
@@ -2374,15 +2393,15 @@ static int bnx2x_lock_alr(struct bnx2x *bp)
2374 msleep(5); 2393 msleep(5);
2375 } 2394 }
2376 if (!(val & (1L << 31))) { 2395 if (!(val & (1L << 31))) {
2377 BNX2X_ERR("Cannot acquire nvram interface\n"); 2396 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2378 rc = -EBUSY; 2397 rc = -EBUSY;
2379 } 2398 }
2380 2399
2381 return rc; 2400 return rc;
2382} 2401}
2383 2402
2384/* Release split MCP access lock register */ 2403/* release split MCP access lock register */
2385static void bnx2x_unlock_alr(struct bnx2x *bp) 2404static void bnx2x_release_alr(struct bnx2x *bp)
2386{ 2405{
2387 u32 val = 0; 2406 u32 val = 0;
2388 2407
@@ -2395,7 +2414,6 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2395 u16 rc = 0; 2414 u16 rc = 0;
2396 2415
2397 barrier(); /* status block is written to by the chip */ 2416 barrier(); /* status block is written to by the chip */
2398
2399 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 2417 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2400 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 2418 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2401 rc |= 1; 2419 rc |= 1;
@@ -2426,26 +2444,31 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2426static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 2444static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2427{ 2445{
2428 int port = BP_PORT(bp); 2446 int port = BP_PORT(bp);
2429 int func = BP_FUNC(bp); 2447 u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2430 u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_FUNC_BASE * func) * 8; 2448 COMMAND_REG_ATTN_BITS_SET);
2431 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 2449 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2432 MISC_REG_AEU_MASK_ATTN_FUNC_0; 2450 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2433 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 2451 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2434 NIG_REG_MASK_INTERRUPT_PORT0; 2452 NIG_REG_MASK_INTERRUPT_PORT0;
2453 u32 aeu_mask;
2435 2454
2436 if (~bp->aeu_mask & (asserted & 0xff))
2437 BNX2X_ERR("IGU ERROR\n");
2438 if (bp->attn_state & asserted) 2455 if (bp->attn_state & asserted)
2439 BNX2X_ERR("IGU ERROR\n"); 2456 BNX2X_ERR("IGU ERROR\n");
2440 2457
2458 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2459 aeu_mask = REG_RD(bp, aeu_addr);
2460
2441 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 2461 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2442 bp->aeu_mask, asserted); 2462 aeu_mask, asserted);
2443 bp->aeu_mask &= ~(asserted & 0xff); 2463 aeu_mask &= ~(asserted & 0xff);
2444 DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask); 2464 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2445 2465
2446 REG_WR(bp, aeu_addr, bp->aeu_mask); 2466 REG_WR(bp, aeu_addr, aeu_mask);
2467 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2447 2468
2469 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2448 bp->attn_state |= asserted; 2470 bp->attn_state |= asserted;
2471 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2449 2472
2450 if (asserted & ATTN_HARD_WIRED_MASK) { 2473 if (asserted & ATTN_HARD_WIRED_MASK) {
2451 if (asserted & ATTN_NIG_FOR_FUNC) { 2474 if (asserted & ATTN_NIG_FOR_FUNC) {
@@ -2500,9 +2523,9 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2500 2523
2501 } /* if hardwired */ 2524 } /* if hardwired */
2502 2525
2503 DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n", 2526 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2504 asserted, BAR_IGU_INTMEM + igu_addr); 2527 asserted, hc_addr);
2505 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted); 2528 REG_WR(bp, hc_addr, asserted);
2506 2529
2507 /* now set back the mask */ 2530 /* now set back the mask */
2508 if (asserted & ATTN_NIG_FOR_FUNC) 2531 if (asserted & ATTN_NIG_FOR_FUNC)
@@ -2530,12 +2553,12 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2530 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: 2553 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2531 /* Fan failure attention */ 2554 /* Fan failure attention */
2532 2555
2533 /* The PHY reset is controled by GPIO 1 */ 2556 /* The PHY reset is controlled by GPIO 1 */
2534 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 2557 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2535 MISC_REGISTERS_GPIO_OUTPUT_LOW); 2558 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2536 /* Low power mode is controled by GPIO 2 */ 2559 /* Low power mode is controlled by GPIO 2 */
2537 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 2560 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2538 MISC_REGISTERS_GPIO_OUTPUT_LOW); 2561 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2539 /* mark the failure */ 2562 /* mark the failure */
2540 bp->link_params.ext_phy_config &= 2563 bp->link_params.ext_phy_config &=
2541 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 2564 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
@@ -2699,10 +2722,11 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2699 int index; 2722 int index;
2700 u32 reg_addr; 2723 u32 reg_addr;
2701 u32 val; 2724 u32 val;
2725 u32 aeu_mask;
2702 2726
2703 /* need to take HW lock because MCP or other port might also 2727 /* need to take HW lock because MCP or other port might also
2704 try to handle this event */ 2728 try to handle this event */
2705 bnx2x_lock_alr(bp); 2729 bnx2x_acquire_alr(bp);
2706 2730
2707 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 2731 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2708 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 2732 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
@@ -2734,32 +2758,35 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2734 HW_PRTY_ASSERT_SET_1) || 2758 HW_PRTY_ASSERT_SET_1) ||
2735 (attn.sig[2] & group_mask.sig[2] & 2759 (attn.sig[2] & group_mask.sig[2] &
2736 HW_PRTY_ASSERT_SET_2)) 2760 HW_PRTY_ASSERT_SET_2))
2737 BNX2X_ERR("FATAL HW block parity attention\n"); 2761 BNX2X_ERR("FATAL HW block parity attention\n");
2738 } 2762 }
2739 } 2763 }
2740 2764
2741 bnx2x_unlock_alr(bp); 2765 bnx2x_release_alr(bp);
2742 2766
2743 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 2767 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2744 2768
2745 val = ~deasserted; 2769 val = ~deasserted;
2746/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2770 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2747 val, BAR_IGU_INTMEM + reg_addr); */ 2771 val, reg_addr);
2748 REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val); 2772 REG_WR(bp, reg_addr, val);
2749 2773
2750 if (bp->aeu_mask & (deasserted & 0xff))
2751 BNX2X_ERR("IGU BUG!\n");
2752 if (~bp->attn_state & deasserted) 2774 if (~bp->attn_state & deasserted)
2753 BNX2X_ERR("IGU BUG!\n"); 2775 BNX2X_ERR("IGU ERROR\n");
2754 2776
2755 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 2777 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2756 MISC_REG_AEU_MASK_ATTN_FUNC_0; 2778 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2757 2779
2758 DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask); 2780 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2759 bp->aeu_mask |= (deasserted & 0xff); 2781 aeu_mask = REG_RD(bp, reg_addr);
2782
2783 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
2784 aeu_mask, deasserted);
2785 aeu_mask |= (deasserted & 0xff);
2786 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2760 2787
2761 DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask); 2788 REG_WR(bp, reg_addr, aeu_mask);
2762 REG_WR(bp, reg_addr, bp->aeu_mask); 2789 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2763 2790
2764 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 2791 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2765 bp->attn_state &= ~deasserted; 2792 bp->attn_state &= ~deasserted;
@@ -2800,7 +2827,7 @@ static void bnx2x_sp_task(struct work_struct *work)
2800 2827
2801 /* Return here if interrupt is disabled */ 2828 /* Return here if interrupt is disabled */
2802 if (unlikely(atomic_read(&bp->intr_sem) != 0)) { 2829 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2803 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); 2830 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2804 return; 2831 return;
2805 } 2832 }
2806 2833
@@ -2808,7 +2835,7 @@ static void bnx2x_sp_task(struct work_struct *work)
2808/* if (status == 0) */ 2835/* if (status == 0) */
2809/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 2836/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
2810 2837
2811 DP(BNX2X_MSG_SP, "got a slowpath interrupt (updated %x)\n", status); 2838 DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2812 2839
2813 /* HW attentions */ 2840 /* HW attentions */
2814 if (status & 0x1) 2841 if (status & 0x1)
@@ -2838,7 +2865,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2838 2865
2839 /* Return here if interrupt is disabled */ 2866 /* Return here if interrupt is disabled */
2840 if (unlikely(atomic_read(&bp->intr_sem) != 0)) { 2867 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2841 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); 2868 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2842 return IRQ_HANDLED; 2869 return IRQ_HANDLED;
2843 } 2870 }
2844 2871
@@ -2876,11 +2903,11 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2876 /* underflow */ \ 2903 /* underflow */ \
2877 d_hi = m_hi - s_hi; \ 2904 d_hi = m_hi - s_hi; \
2878 if (d_hi > 0) { \ 2905 if (d_hi > 0) { \
2879 /* we can 'loan' 1 */ \ 2906 /* we can 'loan' 1 */ \
2880 d_hi--; \ 2907 d_hi--; \
2881 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \ 2908 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2882 } else { \ 2909 } else { \
2883 /* m_hi <= s_hi */ \ 2910 /* m_hi <= s_hi */ \
2884 d_hi = 0; \ 2911 d_hi = 0; \
2885 d_lo = 0; \ 2912 d_lo = 0; \
2886 } \ 2913 } \
@@ -2890,7 +2917,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2890 d_hi = 0; \ 2917 d_hi = 0; \
2891 d_lo = 0; \ 2918 d_lo = 0; \
2892 } else { \ 2919 } else { \
2893 /* m_hi >= s_hi */ \ 2920 /* m_hi >= s_hi */ \
2894 d_hi = m_hi - s_hi; \ 2921 d_hi = m_hi - s_hi; \
2895 d_lo = m_lo - s_lo; \ 2922 d_lo = m_lo - s_lo; \
2896 } \ 2923 } \
@@ -2963,37 +2990,6 @@ static inline long bnx2x_hilo(u32 *hiref)
2963 * Init service functions 2990 * Init service functions
2964 */ 2991 */
2965 2992
2966static void bnx2x_storm_stats_init(struct bnx2x *bp)
2967{
2968 int func = BP_FUNC(bp);
2969
2970 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func), 1);
2971 REG_WR(bp, BAR_XSTRORM_INTMEM +
2972 XSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2973
2974 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func), 1);
2975 REG_WR(bp, BAR_TSTRORM_INTMEM +
2976 TSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2977
2978 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func), 0);
2979 REG_WR(bp, BAR_CSTRORM_INTMEM +
2980 CSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2981
2982 REG_WR(bp, BAR_XSTRORM_INTMEM +
2983 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
2984 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
2985 REG_WR(bp, BAR_XSTRORM_INTMEM +
2986 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
2987 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
2988
2989 REG_WR(bp, BAR_TSTRORM_INTMEM +
2990 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
2991 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
2992 REG_WR(bp, BAR_TSTRORM_INTMEM +
2993 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
2994 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
2995}
2996
2997static void bnx2x_storm_stats_post(struct bnx2x *bp) 2993static void bnx2x_storm_stats_post(struct bnx2x *bp)
2998{ 2994{
2999 if (!bp->stats_pending) { 2995 if (!bp->stats_pending) {
@@ -3032,6 +3028,8 @@ static void bnx2x_stats_init(struct bnx2x *bp)
3032 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats)); 3028 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3033 bp->port.old_nig_stats.brb_discard = 3029 bp->port.old_nig_stats.brb_discard =
3034 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); 3030 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3031 bp->port.old_nig_stats.brb_truncate =
3032 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3035 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50, 3033 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3036 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2); 3034 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3037 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50, 3035 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
@@ -3101,12 +3099,12 @@ static int bnx2x_stats_comp(struct bnx2x *bp)
3101 3099
3102 might_sleep(); 3100 might_sleep();
3103 while (*stats_comp != DMAE_COMP_VAL) { 3101 while (*stats_comp != DMAE_COMP_VAL) {
3104 msleep(1);
3105 if (!cnt) { 3102 if (!cnt) {
3106 BNX2X_ERR("timeout waiting for stats finished\n"); 3103 BNX2X_ERR("timeout waiting for stats finished\n");
3107 break; 3104 break;
3108 } 3105 }
3109 cnt--; 3106 cnt--;
3107 msleep(1);
3110 } 3108 }
3111 return 1; 3109 return 1;
3112} 3110}
@@ -3451,8 +3449,7 @@ static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3451 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong); 3449 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3452 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments); 3450 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3453 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers); 3451 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3454 UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf); 3452 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3455 UPDATE_STAT64(rx_stat_grxcf, rx_stat_bmac_xcf);
3456 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered); 3453 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3457 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived); 3454 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3458 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent); 3455 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
@@ -3536,6 +3533,8 @@ static int bnx2x_hw_stats_update(struct bnx2x *bp)
3536 3533
3537 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo, 3534 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3538 new->brb_discard - old->brb_discard); 3535 new->brb_discard - old->brb_discard);
3536 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3537 new->brb_truncate - old->brb_truncate);
3539 3538
3540 UPDATE_STAT64_NIG(egress_mac_pkt0, 3539 UPDATE_STAT64_NIG(egress_mac_pkt0,
3541 etherstatspkts1024octetsto1522octets); 3540 etherstatspkts1024octetsto1522octets);
@@ -3713,8 +3712,7 @@ static void bnx2x_net_stats_update(struct bnx2x *bp)
3713 nstats->rx_length_errors = 3712 nstats->rx_length_errors =
3714 estats->rx_stat_etherstatsundersizepkts_lo + 3713 estats->rx_stat_etherstatsundersizepkts_lo +
3715 estats->jabber_packets_received; 3714 estats->jabber_packets_received;
3716 nstats->rx_over_errors = estats->brb_drop_lo + 3715 nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo;
3717 estats->brb_truncate_discard;
3718 nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo; 3716 nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3719 nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo; 3717 nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3720 nstats->rx_fifo_errors = old_tclient->no_buff_discard; 3718 nstats->rx_fifo_errors = old_tclient->no_buff_discard;
@@ -3783,7 +3781,7 @@ static void bnx2x_stats_update(struct bnx2x *bp)
3783 bp->fp->rx_comp_cons), 3781 bp->fp->rx_comp_cons),
3784 le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets); 3782 le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3785 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n", 3783 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n",
3786 netif_queue_stopped(bp->dev)? "Xoff" : "Xon", 3784 netif_queue_stopped(bp->dev) ? "Xoff" : "Xon",
3787 estats->driver_xoff, estats->brb_drop_lo); 3785 estats->driver_xoff, estats->brb_drop_lo);
3788 printk(KERN_DEBUG "tstats: checksum_discard %u " 3786 printk(KERN_DEBUG "tstats: checksum_discard %u "
3789 "packets_too_big_discard %u no_buff_discard %u " 3787 "packets_too_big_discard %u no_buff_discard %u "
@@ -3994,14 +3992,14 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
3994 3992
3995 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + 3993 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
3996 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 3994 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
3997 sizeof(struct ustorm_def_status_block)/4); 3995 sizeof(struct ustorm_status_block)/4);
3998 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + 3996 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
3999 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 3997 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4000 sizeof(struct cstorm_def_status_block)/4); 3998 sizeof(struct cstorm_status_block)/4);
4001} 3999}
4002 4000
4003static void bnx2x_init_sb(struct bnx2x *bp, int sb_id, 4001static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4004 struct host_status_block *sb, dma_addr_t mapping) 4002 dma_addr_t mapping, int sb_id)
4005{ 4003{
4006 int port = BP_PORT(bp); 4004 int port = BP_PORT(bp);
4007 int func = BP_FUNC(bp); 4005 int func = BP_FUNC(bp);
@@ -4077,7 +4075,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4077 atten_status_block); 4075 atten_status_block);
4078 def_sb->atten_status_block.status_block_id = sb_id; 4076 def_sb->atten_status_block.status_block_id = sb_id;
4079 4077
4080 bp->def_att_idx = 0;
4081 bp->attn_state = 0; 4078 bp->attn_state = 0;
4082 4079
4083 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4080 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
@@ -4094,9 +4091,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4094 reg_offset + 0xc + 0x10*index); 4091 reg_offset + 0xc + 0x10*index);
4095 } 4092 }
4096 4093
4097 bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4098 MISC_REG_AEU_MASK_ATTN_FUNC_0));
4099
4100 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 4094 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4101 HC_REG_ATTN_MSG0_ADDR_L); 4095 HC_REG_ATTN_MSG0_ADDR_L);
4102 4096
@@ -4114,17 +4108,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4114 u_def_status_block); 4108 u_def_status_block);
4115 def_sb->u_def_status_block.status_block_id = sb_id; 4109 def_sb->u_def_status_block.status_block_id = sb_id;
4116 4110
4117 bp->def_u_idx = 0;
4118
4119 REG_WR(bp, BAR_USTRORM_INTMEM + 4111 REG_WR(bp, BAR_USTRORM_INTMEM +
4120 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4112 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4121 REG_WR(bp, BAR_USTRORM_INTMEM + 4113 REG_WR(bp, BAR_USTRORM_INTMEM +
4122 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4114 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4123 U64_HI(section)); 4115 U64_HI(section));
4124 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF + 4116 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4125 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4117 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4126 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(func),
4127 BNX2X_BTR);
4128 4118
4129 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++) 4119 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4130 REG_WR16(bp, BAR_USTRORM_INTMEM + 4120 REG_WR16(bp, BAR_USTRORM_INTMEM +
@@ -4135,17 +4125,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4135 c_def_status_block); 4125 c_def_status_block);
4136 def_sb->c_def_status_block.status_block_id = sb_id; 4126 def_sb->c_def_status_block.status_block_id = sb_id;
4137 4127
4138 bp->def_c_idx = 0;
4139
4140 REG_WR(bp, BAR_CSTRORM_INTMEM + 4128 REG_WR(bp, BAR_CSTRORM_INTMEM +
4141 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4129 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4142 REG_WR(bp, BAR_CSTRORM_INTMEM + 4130 REG_WR(bp, BAR_CSTRORM_INTMEM +
4143 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4131 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4144 U64_HI(section)); 4132 U64_HI(section));
4145 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF + 4133 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4146 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4134 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4147 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(func),
4148 BNX2X_BTR);
4149 4135
4150 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++) 4136 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4151 REG_WR16(bp, BAR_CSTRORM_INTMEM + 4137 REG_WR16(bp, BAR_CSTRORM_INTMEM +
@@ -4156,17 +4142,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4156 t_def_status_block); 4142 t_def_status_block);
4157 def_sb->t_def_status_block.status_block_id = sb_id; 4143 def_sb->t_def_status_block.status_block_id = sb_id;
4158 4144
4159 bp->def_t_idx = 0;
4160
4161 REG_WR(bp, BAR_TSTRORM_INTMEM + 4145 REG_WR(bp, BAR_TSTRORM_INTMEM +
4162 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4146 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4163 REG_WR(bp, BAR_TSTRORM_INTMEM + 4147 REG_WR(bp, BAR_TSTRORM_INTMEM +
4164 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4148 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4165 U64_HI(section)); 4149 U64_HI(section));
4166 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF + 4150 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4167 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4151 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4168 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(func),
4169 BNX2X_BTR);
4170 4152
4171 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++) 4153 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4172 REG_WR16(bp, BAR_TSTRORM_INTMEM + 4154 REG_WR16(bp, BAR_TSTRORM_INTMEM +
@@ -4177,23 +4159,20 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4177 x_def_status_block); 4159 x_def_status_block);
4178 def_sb->x_def_status_block.status_block_id = sb_id; 4160 def_sb->x_def_status_block.status_block_id = sb_id;
4179 4161
4180 bp->def_x_idx = 0;
4181
4182 REG_WR(bp, BAR_XSTRORM_INTMEM + 4162 REG_WR(bp, BAR_XSTRORM_INTMEM +
4183 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4163 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4184 REG_WR(bp, BAR_XSTRORM_INTMEM + 4164 REG_WR(bp, BAR_XSTRORM_INTMEM +
4185 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4165 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4186 U64_HI(section)); 4166 U64_HI(section));
4187 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF + 4167 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4188 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4168 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4189 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(func),
4190 BNX2X_BTR);
4191 4169
4192 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++) 4170 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4193 REG_WR16(bp, BAR_XSTRORM_INTMEM + 4171 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4194 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1); 4172 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4195 4173
4196 bp->stats_pending = 0; 4174 bp->stats_pending = 0;
4175 bp->set_mac_pending = 0;
4197 4176
4198 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); 4177 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4199} 4178}
@@ -4209,21 +4188,25 @@ static void bnx2x_update_coalesce(struct bnx2x *bp)
4209 /* HC_INDEX_U_ETH_RX_CQ_CONS */ 4188 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4210 REG_WR8(bp, BAR_USTRORM_INTMEM + 4189 REG_WR8(bp, BAR_USTRORM_INTMEM +
4211 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, 4190 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4212 HC_INDEX_U_ETH_RX_CQ_CONS), 4191 U_SB_ETH_RX_CQ_INDEX),
4213 bp->rx_ticks/12); 4192 bp->rx_ticks/12);
4214 REG_WR16(bp, BAR_USTRORM_INTMEM + 4193 REG_WR16(bp, BAR_USTRORM_INTMEM +
4215 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, 4194 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4216 HC_INDEX_U_ETH_RX_CQ_CONS), 4195 U_SB_ETH_RX_CQ_INDEX),
4196 bp->rx_ticks ? 0 : 1);
4197 REG_WR16(bp, BAR_USTRORM_INTMEM +
4198 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4199 U_SB_ETH_RX_BD_INDEX),
4217 bp->rx_ticks ? 0 : 1); 4200 bp->rx_ticks ? 0 : 1);
4218 4201
4219 /* HC_INDEX_C_ETH_TX_CQ_CONS */ 4202 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4220 REG_WR8(bp, BAR_CSTRORM_INTMEM + 4203 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4221 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, 4204 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4222 HC_INDEX_C_ETH_TX_CQ_CONS), 4205 C_SB_ETH_TX_CQ_INDEX),
4223 bp->tx_ticks/12); 4206 bp->tx_ticks/12);
4224 REG_WR16(bp, BAR_CSTRORM_INTMEM + 4207 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4225 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, 4208 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4226 HC_INDEX_C_ETH_TX_CQ_CONS), 4209 C_SB_ETH_TX_CQ_INDEX),
4227 bp->tx_ticks ? 0 : 1); 4210 bp->tx_ticks ? 0 : 1);
4228 } 4211 }
4229} 4212}
@@ -4256,7 +4239,9 @@ static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4256static void bnx2x_init_rx_rings(struct bnx2x *bp) 4239static void bnx2x_init_rx_rings(struct bnx2x *bp)
4257{ 4240{
4258 int func = BP_FUNC(bp); 4241 int func = BP_FUNC(bp);
4259 u16 ring_prod, cqe_ring_prod = 0; 4242 int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4243 ETH_MAX_AGGREGATION_QUEUES_E1H;
4244 u16 ring_prod, cqe_ring_prod;
4260 int i, j; 4245 int i, j;
4261 4246
4262 bp->rx_buf_use_size = bp->dev->mtu; 4247 bp->rx_buf_use_size = bp->dev->mtu;
@@ -4270,9 +4255,9 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
4270 bp->dev->mtu + ETH_OVREHEAD); 4255 bp->dev->mtu + ETH_OVREHEAD);
4271 4256
4272 for_each_queue(bp, j) { 4257 for_each_queue(bp, j) {
4273 for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1H; i++) { 4258 struct bnx2x_fastpath *fp = &bp->fp[j];
4274 struct bnx2x_fastpath *fp = &bp->fp[j];
4275 4259
4260 for (i = 0; i < max_agg_queues; i++) {
4276 fp->tpa_pool[i].skb = 4261 fp->tpa_pool[i].skb =
4277 netdev_alloc_skb(bp->dev, bp->rx_buf_size); 4262 netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4278 if (!fp->tpa_pool[i].skb) { 4263 if (!fp->tpa_pool[i].skb) {
@@ -4352,8 +4337,7 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
4352 BNX2X_ERR("disabling TPA for queue[%d]\n", j); 4337 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4353 /* Cleanup already allocated elements */ 4338 /* Cleanup already allocated elements */
4354 bnx2x_free_rx_sge_range(bp, fp, ring_prod); 4339 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4355 bnx2x_free_tpa_pool(bp, fp, 4340 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4356 ETH_MAX_AGGREGATION_QUEUES_E1H);
4357 fp->disable_tpa = 1; 4341 fp->disable_tpa = 1;
4358 ring_prod = 0; 4342 ring_prod = 0;
4359 break; 4343 break;
@@ -4363,13 +4347,13 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
4363 fp->rx_sge_prod = ring_prod; 4347 fp->rx_sge_prod = ring_prod;
4364 4348
4365 /* Allocate BDs and initialize BD ring */ 4349 /* Allocate BDs and initialize BD ring */
4366 fp->rx_comp_cons = fp->rx_alloc_failed = 0; 4350 fp->rx_comp_cons = 0;
4367 cqe_ring_prod = ring_prod = 0; 4351 cqe_ring_prod = ring_prod = 0;
4368 for (i = 0; i < bp->rx_ring_size; i++) { 4352 for (i = 0; i < bp->rx_ring_size; i++) {
4369 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) { 4353 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4370 BNX2X_ERR("was only able to allocate " 4354 BNX2X_ERR("was only able to allocate "
4371 "%d rx skbs\n", i); 4355 "%d rx skbs\n", i);
4372 fp->rx_alloc_failed++; 4356 bp->eth_stats.rx_skb_alloc_failed++;
4373 break; 4357 break;
4374 } 4358 }
4375 ring_prod = NEXT_RX_IDX(ring_prod); 4359 ring_prod = NEXT_RX_IDX(ring_prod);
@@ -4497,7 +4481,7 @@ static void bnx2x_init_context(struct bnx2x *bp)
4497 } 4481 }
4498 4482
4499 context->cstorm_st_context.sb_index_number = 4483 context->cstorm_st_context.sb_index_number =
4500 HC_INDEX_C_ETH_TX_CQ_CONS; 4484 C_SB_ETH_TX_CQ_INDEX;
4501 context->cstorm_st_context.status_block_id = sb_id; 4485 context->cstorm_st_context.status_block_id = sb_id;
4502 4486
4503 context->xstorm_ag_context.cdu_reserved = 4487 context->xstorm_ag_context.cdu_reserved =
@@ -4535,7 +4519,7 @@ static void bnx2x_set_client_config(struct bnx2x *bp)
4535 int i; 4519 int i;
4536 4520
4537 tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD; 4521 tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD;
4538 tstorm_client.statistics_counter_id = 0; 4522 tstorm_client.statistics_counter_id = BP_CL_ID(bp);
4539 tstorm_client.config_flags = 4523 tstorm_client.config_flags =
4540 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE; 4524 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4541#ifdef BCM_VLAN 4525#ifdef BCM_VLAN
@@ -4579,7 +4563,7 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4579 int func = BP_FUNC(bp); 4563 int func = BP_FUNC(bp);
4580 int i; 4564 int i;
4581 4565
4582 DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode); 4566 DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask);
4583 4567
4584 switch (mode) { 4568 switch (mode) {
4585 case BNX2X_RX_MODE_NONE: /* no Rx */ 4569 case BNX2X_RX_MODE_NONE: /* no Rx */
@@ -4617,13 +4601,35 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4617 bnx2x_set_client_config(bp); 4601 bnx2x_set_client_config(bp);
4618} 4602}
4619 4603
4620static void bnx2x_init_internal(struct bnx2x *bp) 4604static void bnx2x_init_internal_common(struct bnx2x *bp)
4605{
4606 int i;
4607
4608 /* Zero this manually as its initialization is
4609 currently missing in the initTool */
4610 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4611 REG_WR(bp, BAR_USTRORM_INTMEM +
4612 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4613}
4614
4615static void bnx2x_init_internal_port(struct bnx2x *bp)
4616{
4617 int port = BP_PORT(bp);
4618
4619 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4620 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4621 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4622 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4623}
4624
4625static void bnx2x_init_internal_func(struct bnx2x *bp)
4621{ 4626{
4622 struct tstorm_eth_function_common_config tstorm_config = {0}; 4627 struct tstorm_eth_function_common_config tstorm_config = {0};
4623 struct stats_indication_flags stats_flags = {0}; 4628 struct stats_indication_flags stats_flags = {0};
4624 int port = BP_PORT(bp); 4629 int port = BP_PORT(bp);
4625 int func = BP_FUNC(bp); 4630 int func = BP_FUNC(bp);
4626 int i; 4631 int i;
4632 u16 max_agg_size;
4627 4633
4628 if (is_multi(bp)) { 4634 if (is_multi(bp)) {
4629 tstorm_config.config_flags = MULTI_FLAGS; 4635 tstorm_config.config_flags = MULTI_FLAGS;
@@ -4636,31 +4642,53 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4636 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func), 4642 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4637 (*(u32 *)&tstorm_config)); 4643 (*(u32 *)&tstorm_config));
4638 4644
4639/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n",
4640 (*(u32 *)&tstorm_config)); */
4641
4642 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */ 4645 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4643 bnx2x_set_storm_rx_mode(bp); 4646 bnx2x_set_storm_rx_mode(bp);
4644 4647
4648 /* reset xstorm per client statistics */
4649 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
4650 REG_WR(bp, BAR_XSTRORM_INTMEM +
4651 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4652 i*4, 0);
4653 }
4654 /* reset tstorm per client statistics */
4655 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
4656 REG_WR(bp, BAR_TSTRORM_INTMEM +
4657 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4658 i*4, 0);
4659 }
4660
4661 /* Init statistics related context */
4645 stats_flags.collect_eth = 1; 4662 stats_flags.collect_eth = 1;
4646 4663
4647 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), 4664 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4648 ((u32 *)&stats_flags)[0]); 4665 ((u32 *)&stats_flags)[0]);
4649 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port) + 4, 4666 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4650 ((u32 *)&stats_flags)[1]); 4667 ((u32 *)&stats_flags)[1]);
4651 4668
4652 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port), 4669 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4653 ((u32 *)&stats_flags)[0]); 4670 ((u32 *)&stats_flags)[0]);
4654 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port) + 4, 4671 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4655 ((u32 *)&stats_flags)[1]); 4672 ((u32 *)&stats_flags)[1]);
4656 4673
4657 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port), 4674 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4658 ((u32 *)&stats_flags)[0]); 4675 ((u32 *)&stats_flags)[0]);
4659 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port) + 4, 4676 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4660 ((u32 *)&stats_flags)[1]); 4677 ((u32 *)&stats_flags)[1]);
4661 4678
4662/* DP(NETIF_MSG_IFUP, "stats_flags: 0x%08x 0x%08x\n", 4679 REG_WR(bp, BAR_XSTRORM_INTMEM +
4663 ((u32 *)&stats_flags)[0], ((u32 *)&stats_flags)[1]); */ 4680 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4681 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4682 REG_WR(bp, BAR_XSTRORM_INTMEM +
4683 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4684 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4685
4686 REG_WR(bp, BAR_TSTRORM_INTMEM +
4687 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4688 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4689 REG_WR(bp, BAR_TSTRORM_INTMEM +
4690 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4691 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4664 4692
4665 if (CHIP_IS_E1H(bp)) { 4693 if (CHIP_IS_E1H(bp)) {
4666 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET, 4694 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
@@ -4676,15 +4704,12 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4676 bp->e1hov); 4704 bp->e1hov);
4677 } 4705 }
4678 4706
4679 /* Zero this manualy as its initialization is 4707 /* Init CQ ring mapping and aggregation size */
4680 currently missing in the initTool */ 4708 max_agg_size = min((u32)(bp->rx_buf_use_size +
4681 for (i = 0; i < USTORM_AGG_DATA_SIZE >> 2; i++) 4709 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4682 REG_WR(bp, BAR_USTRORM_INTMEM + 4710 (u32)0xffff);
4683 USTORM_AGG_DATA_OFFSET + 4*i, 0);
4684
4685 for_each_queue(bp, i) { 4711 for_each_queue(bp, i) {
4686 struct bnx2x_fastpath *fp = &bp->fp[i]; 4712 struct bnx2x_fastpath *fp = &bp->fp[i];
4687 u16 max_agg_size;
4688 4713
4689 REG_WR(bp, BAR_USTRORM_INTMEM + 4714 REG_WR(bp, BAR_USTRORM_INTMEM +
4690 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)), 4715 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
@@ -4693,16 +4718,34 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4693 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4, 4718 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4694 U64_HI(fp->rx_comp_mapping)); 4719 U64_HI(fp->rx_comp_mapping));
4695 4720
4696 max_agg_size = min((u32)(bp->rx_buf_use_size +
4697 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4698 (u32)0xffff);
4699 REG_WR16(bp, BAR_USTRORM_INTMEM + 4721 REG_WR16(bp, BAR_USTRORM_INTMEM +
4700 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)), 4722 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4701 max_agg_size); 4723 max_agg_size);
4702 } 4724 }
4703} 4725}
4704 4726
4705static void bnx2x_nic_init(struct bnx2x *bp) 4727static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4728{
4729 switch (load_code) {
4730 case FW_MSG_CODE_DRV_LOAD_COMMON:
4731 bnx2x_init_internal_common(bp);
4732 /* no break */
4733
4734 case FW_MSG_CODE_DRV_LOAD_PORT:
4735 bnx2x_init_internal_port(bp);
4736 /* no break */
4737
4738 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4739 bnx2x_init_internal_func(bp);
4740 break;
4741
4742 default:
4743 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4744 break;
4745 }
4746}
4747
4748static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4706{ 4749{
4707 int i; 4750 int i;
4708 4751
@@ -4717,19 +4760,20 @@ static void bnx2x_nic_init(struct bnx2x *bp)
4717 DP(NETIF_MSG_IFUP, 4760 DP(NETIF_MSG_IFUP,
4718 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n", 4761 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
4719 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp)); 4762 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4720 bnx2x_init_sb(bp, FP_SB_ID(fp), fp->status_blk, 4763 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
4721 fp->status_blk_mapping); 4764 FP_SB_ID(fp));
4765 bnx2x_update_fpsb_idx(fp);
4722 } 4766 }
4723 4767
4724 bnx2x_init_def_sb(bp, bp->def_status_blk, 4768 bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
4725 bp->def_status_blk_mapping, DEF_SB_ID); 4769 DEF_SB_ID);
4770 bnx2x_update_dsb_idx(bp);
4726 bnx2x_update_coalesce(bp); 4771 bnx2x_update_coalesce(bp);
4727 bnx2x_init_rx_rings(bp); 4772 bnx2x_init_rx_rings(bp);
4728 bnx2x_init_tx_ring(bp); 4773 bnx2x_init_tx_ring(bp);
4729 bnx2x_init_sp_ring(bp); 4774 bnx2x_init_sp_ring(bp);
4730 bnx2x_init_context(bp); 4775 bnx2x_init_context(bp);
4731 bnx2x_init_internal(bp); 4776 bnx2x_init_internal(bp, load_code);
4732 bnx2x_storm_stats_init(bp);
4733 bnx2x_init_ind_table(bp); 4777 bnx2x_init_ind_table(bp);
4734 bnx2x_int_enable(bp); 4778 bnx2x_int_enable(bp);
4735} 4779}
@@ -4878,7 +4922,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
4878 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 4922 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4879 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 4923 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4880 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 4924 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4881 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0); 4925 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4882 4926
4883 /* Write 0 to parser credits for CFC search request */ 4927 /* Write 0 to parser credits for CFC search request */
4884 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 4928 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
@@ -4933,7 +4977,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
4933 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 4977 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4934 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 4978 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4935 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 4979 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4936 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0); 4980 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4937 4981
4938 /* Write 0 to parser credits for CFC search request */ 4982 /* Write 0 to parser credits for CFC search request */
4939 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 4983 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
@@ -5000,7 +5044,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
5000 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5044 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5001 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5045 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5002 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5046 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5003 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1); 5047 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5004 5048
5005 DP(NETIF_MSG_HW, "done\n"); 5049 DP(NETIF_MSG_HW, "done\n");
5006 5050
@@ -5089,11 +5133,6 @@ static int bnx2x_init_common(struct bnx2x *bp)
5089 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 5133 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5090#endif 5134#endif
5091 5135
5092#ifndef BCM_ISCSI
5093 /* set NIC mode */
5094 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5095#endif
5096
5097 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2); 5136 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5098#ifdef BCM_ISCSI 5137#ifdef BCM_ISCSI
5099 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5); 5138 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
@@ -5163,6 +5202,8 @@ static int bnx2x_init_common(struct bnx2x *bp)
5163 } 5202 }
5164 5203
5165 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END); 5204 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5205 /* set NIC mode */
5206 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5166 if (CHIP_IS_E1H(bp)) 5207 if (CHIP_IS_E1H(bp))
5167 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp)); 5208 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5168 5209
@@ -5333,6 +5374,13 @@ static int bnx2x_init_common(struct bnx2x *bp)
5333 ((u32 *)&tmp)[1]); 5374 ((u32 *)&tmp)[1]);
5334 } 5375 }
5335 5376
5377 if (!BP_NOMCP(bp)) {
5378 bnx2x_acquire_phy_lock(bp);
5379 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5380 bnx2x_release_phy_lock(bp);
5381 } else
5382 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5383
5336 return 0; 5384 return 0;
5337} 5385}
5338 5386
@@ -5638,18 +5686,23 @@ static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5638 int func = BP_FUNC(bp); 5686 int func = BP_FUNC(bp);
5639 u32 seq = ++bp->fw_seq; 5687 u32 seq = ++bp->fw_seq;
5640 u32 rc = 0; 5688 u32 rc = 0;
5689 u32 cnt = 1;
5690 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
5641 5691
5642 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq)); 5692 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5643 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq)); 5693 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5644 5694
5645 /* let the FW do it's magic ... */ 5695 do {
5646 msleep(100); /* TBD */ 5696 /* let the FW do it's magic ... */
5697 msleep(delay);
5647 5698
5648 if (CHIP_REV_IS_SLOW(bp)) 5699 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5649 msleep(900);
5650 5700
5651 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header); 5701 /* Give the FW up to 2 second (200*10ms) */
5652 DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq); 5702 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
5703
5704 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
5705 cnt*delay, rc, seq);
5653 5706
5654 /* is this a reply to our command? */ 5707 /* is this a reply to our command? */
5655 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { 5708 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
@@ -5713,6 +5766,7 @@ static void bnx2x_free_mem(struct bnx2x *bp)
5713 NUM_RCQ_BD); 5766 NUM_RCQ_BD);
5714 5767
5715 /* SGE ring */ 5768 /* SGE ring */
5769 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5716 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring), 5770 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5717 bnx2x_fp(bp, i, rx_sge_mapping), 5771 bnx2x_fp(bp, i, rx_sge_mapping),
5718 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES); 5772 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
@@ -5890,7 +5944,8 @@ static void bnx2x_free_rx_skbs(struct bnx2x *bp)
5890 dev_kfree_skb(skb); 5944 dev_kfree_skb(skb);
5891 } 5945 }
5892 if (!fp->disable_tpa) 5946 if (!fp->disable_tpa)
5893 bnx2x_free_tpa_pool(bp, fp, 5947 bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
5948 ETH_MAX_AGGREGATION_QUEUES_E1 :
5894 ETH_MAX_AGGREGATION_QUEUES_E1H); 5949 ETH_MAX_AGGREGATION_QUEUES_E1H);
5895 } 5950 }
5896} 5951}
@@ -5976,8 +6031,8 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
5976 bnx2x_msix_fp_int, 0, 6031 bnx2x_msix_fp_int, 0,
5977 bp->dev->name, &bp->fp[i]); 6032 bp->dev->name, &bp->fp[i]);
5978 if (rc) { 6033 if (rc) {
5979 BNX2X_ERR("request fp #%d irq failed rc %d\n", 6034 BNX2X_ERR("request fp #%d irq failed rc -%d\n",
5980 i + offset, rc); 6035 i + offset, -rc);
5981 bnx2x_free_msix_irqs(bp); 6036 bnx2x_free_msix_irqs(bp);
5982 return -EBUSY; 6037 return -EBUSY;
5983 } 6038 }
@@ -6004,7 +6059,7 @@ static int bnx2x_req_irq(struct bnx2x *bp)
6004 * Init service functions 6059 * Init service functions
6005 */ 6060 */
6006 6061
6007static void bnx2x_set_mac_addr_e1(struct bnx2x *bp) 6062static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
6008{ 6063{
6009 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); 6064 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6010 int port = BP_PORT(bp); 6065 int port = BP_PORT(bp);
@@ -6026,11 +6081,15 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6026 config->config_table[0].cam_entry.lsb_mac_addr = 6081 config->config_table[0].cam_entry.lsb_mac_addr =
6027 swab16(*(u16 *)&bp->dev->dev_addr[4]); 6082 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6028 config->config_table[0].cam_entry.flags = cpu_to_le16(port); 6083 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
6029 config->config_table[0].target_table_entry.flags = 0; 6084 if (set)
6085 config->config_table[0].target_table_entry.flags = 0;
6086 else
6087 CAM_INVALIDATE(config->config_table[0]);
6030 config->config_table[0].target_table_entry.client_id = 0; 6088 config->config_table[0].target_table_entry.client_id = 0;
6031 config->config_table[0].target_table_entry.vlan_id = 0; 6089 config->config_table[0].target_table_entry.vlan_id = 0;
6032 6090
6033 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x)\n", 6091 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
6092 (set ? "setting" : "clearing"),
6034 config->config_table[0].cam_entry.msb_mac_addr, 6093 config->config_table[0].cam_entry.msb_mac_addr,
6035 config->config_table[0].cam_entry.middle_mac_addr, 6094 config->config_table[0].cam_entry.middle_mac_addr,
6036 config->config_table[0].cam_entry.lsb_mac_addr); 6095 config->config_table[0].cam_entry.lsb_mac_addr);
@@ -6040,8 +6099,11 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6040 config->config_table[1].cam_entry.middle_mac_addr = 0xffff; 6099 config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
6041 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff; 6100 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
6042 config->config_table[1].cam_entry.flags = cpu_to_le16(port); 6101 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
6043 config->config_table[1].target_table_entry.flags = 6102 if (set)
6103 config->config_table[1].target_table_entry.flags =
6044 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST; 6104 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
6105 else
6106 CAM_INVALIDATE(config->config_table[1]);
6045 config->config_table[1].target_table_entry.client_id = 0; 6107 config->config_table[1].target_table_entry.client_id = 0;
6046 config->config_table[1].target_table_entry.vlan_id = 0; 6108 config->config_table[1].target_table_entry.vlan_id = 0;
6047 6109
@@ -6050,12 +6112,12 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6050 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); 6112 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6051} 6113}
6052 6114
6053static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp) 6115static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
6054{ 6116{
6055 struct mac_configuration_cmd_e1h *config = 6117 struct mac_configuration_cmd_e1h *config =
6056 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); 6118 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
6057 6119
6058 if (bp->state != BNX2X_STATE_OPEN) { 6120 if (set && (bp->state != BNX2X_STATE_OPEN)) {
6059 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 6121 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
6060 return; 6122 return;
6061 } 6123 }
@@ -6079,9 +6141,14 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp)
6079 config->config_table[0].client_id = BP_L_ID(bp); 6141 config->config_table[0].client_id = BP_L_ID(bp);
6080 config->config_table[0].vlan_id = 0; 6142 config->config_table[0].vlan_id = 0;
6081 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); 6143 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
6082 config->config_table[0].flags = BP_PORT(bp); 6144 if (set)
6145 config->config_table[0].flags = BP_PORT(bp);
6146 else
6147 config->config_table[0].flags =
6148 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
6083 6149
6084 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n", 6150 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n",
6151 (set ? "setting" : "clearing"),
6085 config->config_table[0].msb_mac_addr, 6152 config->config_table[0].msb_mac_addr,
6086 config->config_table[0].middle_mac_addr, 6153 config->config_table[0].middle_mac_addr,
6087 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp)); 6154 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));
@@ -6106,13 +6173,13 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6106 bnx2x_rx_int(bp->fp, 10); 6173 bnx2x_rx_int(bp->fp, 10);
6107 /* if index is different from 0 6174 /* if index is different from 0
6108 * the reply for some commands will 6175 * the reply for some commands will
6109 * be on the none default queue 6176 * be on the non default queue
6110 */ 6177 */
6111 if (idx) 6178 if (idx)
6112 bnx2x_rx_int(&bp->fp[idx], 10); 6179 bnx2x_rx_int(&bp->fp[idx], 10);
6113 } 6180 }
6114 mb(); /* state is changed by bnx2x_sp_event() */
6115 6181
6182 mb(); /* state is changed by bnx2x_sp_event() */
6116 if (*state_p == state) 6183 if (*state_p == state)
6117 return 0; 6184 return 0;
6118 6185
@@ -6167,7 +6234,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6167{ 6234{
6168 u32 load_code; 6235 u32 load_code;
6169 int i, rc; 6236 int i, rc;
6170
6171#ifdef BNX2X_STOP_ON_ERROR 6237#ifdef BNX2X_STOP_ON_ERROR
6172 if (unlikely(bp->panic)) 6238 if (unlikely(bp->panic))
6173 return -EPERM; 6239 return -EPERM;
@@ -6183,22 +6249,24 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6183 if (!BP_NOMCP(bp)) { 6249 if (!BP_NOMCP(bp)) {
6184 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ); 6250 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
6185 if (!load_code) { 6251 if (!load_code) {
6186 BNX2X_ERR("MCP response failure, unloading\n"); 6252 BNX2X_ERR("MCP response failure, aborting\n");
6187 return -EBUSY; 6253 return -EBUSY;
6188 } 6254 }
6189 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) 6255 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED)
6190 return -EBUSY; /* other port in diagnostic mode */ 6256 return -EBUSY; /* other port in diagnostic mode */
6191 6257
6192 } else { 6258 } else {
6259 int port = BP_PORT(bp);
6260
6193 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n", 6261 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n",
6194 load_count[0], load_count[1], load_count[2]); 6262 load_count[0], load_count[1], load_count[2]);
6195 load_count[0]++; 6263 load_count[0]++;
6196 load_count[1 + BP_PORT(bp)]++; 6264 load_count[1 + port]++;
6197 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n", 6265 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n",
6198 load_count[0], load_count[1], load_count[2]); 6266 load_count[0], load_count[1], load_count[2]);
6199 if (load_count[0] == 1) 6267 if (load_count[0] == 1)
6200 load_code = FW_MSG_CODE_DRV_LOAD_COMMON; 6268 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
6201 else if (load_count[1 + BP_PORT(bp)] == 1) 6269 else if (load_count[1 + port] == 1)
6202 load_code = FW_MSG_CODE_DRV_LOAD_PORT; 6270 load_code = FW_MSG_CODE_DRV_LOAD_PORT;
6203 else 6271 else
6204 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION; 6272 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
@@ -6247,9 +6315,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6247 bnx2x_fp(bp, i, disable_tpa) = 6315 bnx2x_fp(bp, i, disable_tpa) =
6248 ((bp->flags & TPA_ENABLE_FLAG) == 0); 6316 ((bp->flags & TPA_ENABLE_FLAG) == 0);
6249 6317
6250 /* Disable interrupt handling until HW is initialized */
6251 atomic_set(&bp->intr_sem, 1);
6252
6253 if (bp->flags & USING_MSIX_FLAG) { 6318 if (bp->flags & USING_MSIX_FLAG) {
6254 rc = bnx2x_req_msix_irqs(bp); 6319 rc = bnx2x_req_msix_irqs(bp);
6255 if (rc) { 6320 if (rc) {
@@ -6276,17 +6341,14 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6276 goto load_error; 6341 goto load_error;
6277 } 6342 }
6278 6343
6279 /* Enable interrupt handling */
6280 atomic_set(&bp->intr_sem, 0);
6281
6282 /* Setup NIC internals and enable interrupts */ 6344 /* Setup NIC internals and enable interrupts */
6283 bnx2x_nic_init(bp); 6345 bnx2x_nic_init(bp, load_code);
6284 6346
6285 /* Send LOAD_DONE command to MCP */ 6347 /* Send LOAD_DONE command to MCP */
6286 if (!BP_NOMCP(bp)) { 6348 if (!BP_NOMCP(bp)) {
6287 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE); 6349 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
6288 if (!load_code) { 6350 if (!load_code) {
6289 BNX2X_ERR("MCP response failure, unloading\n"); 6351 BNX2X_ERR("MCP response failure, aborting\n");
6290 rc = -EBUSY; 6352 rc = -EBUSY;
6291 goto load_int_disable; 6353 goto load_int_disable;
6292 } 6354 }
@@ -6301,11 +6363,12 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6301 for_each_queue(bp, i) 6363 for_each_queue(bp, i)
6302 napi_enable(&bnx2x_fp(bp, i, napi)); 6364 napi_enable(&bnx2x_fp(bp, i, napi));
6303 6365
6366 /* Enable interrupt handling */
6367 atomic_set(&bp->intr_sem, 0);
6368
6304 rc = bnx2x_setup_leading(bp); 6369 rc = bnx2x_setup_leading(bp);
6305 if (rc) { 6370 if (rc) {
6306#ifdef BNX2X_STOP_ON_ERROR 6371 BNX2X_ERR("Setup leading failed!\n");
6307 bp->panic = 1;
6308#endif
6309 goto load_stop_netif; 6372 goto load_stop_netif;
6310 } 6373 }
6311 6374
@@ -6323,9 +6386,9 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6323 } 6386 }
6324 6387
6325 if (CHIP_IS_E1(bp)) 6388 if (CHIP_IS_E1(bp))
6326 bnx2x_set_mac_addr_e1(bp); 6389 bnx2x_set_mac_addr_e1(bp, 1);
6327 else 6390 else
6328 bnx2x_set_mac_addr_e1h(bp); 6391 bnx2x_set_mac_addr_e1h(bp, 1);
6329 6392
6330 if (bp->port.pmf) 6393 if (bp->port.pmf)
6331 bnx2x_initial_phy_init(bp); 6394 bnx2x_initial_phy_init(bp);
@@ -6339,7 +6402,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6339 break; 6402 break;
6340 6403
6341 case LOAD_OPEN: 6404 case LOAD_OPEN:
6342 /* IRQ is only requested from bnx2x_open */
6343 netif_start_queue(bp->dev); 6405 netif_start_queue(bp->dev);
6344 bnx2x_set_rx_mode(bp->dev); 6406 bnx2x_set_rx_mode(bp->dev);
6345 if (bp->flags & USING_MSIX_FLAG) 6407 if (bp->flags & USING_MSIX_FLAG)
@@ -6378,8 +6440,7 @@ load_int_disable:
6378 /* Free SKBs, SGEs, TPA pool and driver internals */ 6440 /* Free SKBs, SGEs, TPA pool and driver internals */
6379 bnx2x_free_skbs(bp); 6441 bnx2x_free_skbs(bp);
6380 for_each_queue(bp, i) 6442 for_each_queue(bp, i)
6381 bnx2x_free_rx_sge_range(bp, bp->fp + i, 6443 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
6382 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6383load_error: 6444load_error:
6384 bnx2x_free_mem(bp); 6445 bnx2x_free_mem(bp);
6385 6446
@@ -6411,7 +6472,7 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6411 return rc; 6472 return rc;
6412} 6473}
6413 6474
6414static void bnx2x_stop_leading(struct bnx2x *bp) 6475static int bnx2x_stop_leading(struct bnx2x *bp)
6415{ 6476{
6416 u16 dsb_sp_prod_idx; 6477 u16 dsb_sp_prod_idx;
6417 /* if the other port is handling traffic, 6478 /* if the other port is handling traffic,
@@ -6429,7 +6490,7 @@ static void bnx2x_stop_leading(struct bnx2x *bp)
6429 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0, 6490 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
6430 &(bp->fp[0].state), 1); 6491 &(bp->fp[0].state), 1);
6431 if (rc) /* timeout */ 6492 if (rc) /* timeout */
6432 return; 6493 return rc;
6433 6494
6434 dsb_sp_prod_idx = *bp->dsb_sp_prod; 6495 dsb_sp_prod_idx = *bp->dsb_sp_prod;
6435 6496
@@ -6441,20 +6502,24 @@ static void bnx2x_stop_leading(struct bnx2x *bp)
6441 so there is not much to do if this times out 6502 so there is not much to do if this times out
6442 */ 6503 */
6443 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) { 6504 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
6444 msleep(1);
6445 if (!cnt) { 6505 if (!cnt) {
6446 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del " 6506 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
6447 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n", 6507 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
6448 *bp->dsb_sp_prod, dsb_sp_prod_idx); 6508 *bp->dsb_sp_prod, dsb_sp_prod_idx);
6449#ifdef BNX2X_STOP_ON_ERROR 6509#ifdef BNX2X_STOP_ON_ERROR
6450 bnx2x_panic(); 6510 bnx2x_panic();
6511#else
6512 rc = -EBUSY;
6451#endif 6513#endif
6452 break; 6514 break;
6453 } 6515 }
6454 cnt--; 6516 cnt--;
6517 msleep(1);
6455 } 6518 }
6456 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD; 6519 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
6457 bp->fp[0].state = BNX2X_FP_STATE_CLOSED; 6520 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
6521
6522 return rc;
6458} 6523}
6459 6524
6460static void bnx2x_reset_func(struct bnx2x *bp) 6525static void bnx2x_reset_func(struct bnx2x *bp)
@@ -6496,7 +6561,7 @@ static void bnx2x_reset_port(struct bnx2x *bp)
6496 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 6561 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6497 if (val) 6562 if (val)
6498 DP(NETIF_MSG_IFDOWN, 6563 DP(NETIF_MSG_IFDOWN,
6499 "BRB1 is not empty %d blooks are occupied\n", val); 6564 "BRB1 is not empty %d blocks are occupied\n", val);
6500 6565
6501 /* TODO: Close Doorbell port? */ 6566 /* TODO: Close Doorbell port? */
6502} 6567}
@@ -6536,11 +6601,12 @@ static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6536 } 6601 }
6537} 6602}
6538 6603
6539/* msut be called with rtnl_lock */ 6604/* must be called with rtnl_lock */
6540static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) 6605static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6541{ 6606{
6607 int port = BP_PORT(bp);
6542 u32 reset_code = 0; 6608 u32 reset_code = 0;
6543 int i, cnt; 6609 int i, cnt, rc;
6544 6610
6545 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; 6611 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
6546 6612
@@ -6557,22 +6623,17 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6557 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq)); 6623 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
6558 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 6624 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
6559 6625
6560 /* Wait until all fast path tasks complete */ 6626 /* Wait until tx fast path tasks complete */
6561 for_each_queue(bp, i) { 6627 for_each_queue(bp, i) {
6562 struct bnx2x_fastpath *fp = &bp->fp[i]; 6628 struct bnx2x_fastpath *fp = &bp->fp[i];
6563 6629
6564#ifdef BNX2X_STOP_ON_ERROR
6565#ifdef __powerpc64__
6566 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
6567#else
6568 DP(NETIF_MSG_IFDOWN, "fp->tpa_queue_used = 0x%llx\n",
6569#endif
6570 fp->tpa_queue_used);
6571#endif
6572 cnt = 1000; 6630 cnt = 1000;
6573 smp_rmb(); 6631 smp_rmb();
6574 while (bnx2x_has_work(fp)) { 6632 while (BNX2X_HAS_TX_WORK(fp)) {
6575 msleep(1); 6633
6634 if (!netif_running(bp->dev))
6635 bnx2x_tx_int(fp, 1000);
6636
6576 if (!cnt) { 6637 if (!cnt) {
6577 BNX2X_ERR("timeout waiting for queue[%d]\n", 6638 BNX2X_ERR("timeout waiting for queue[%d]\n",
6578 i); 6639 i);
@@ -6584,14 +6645,13 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6584#endif 6645#endif
6585 } 6646 }
6586 cnt--; 6647 cnt--;
6648 msleep(1);
6587 smp_rmb(); 6649 smp_rmb();
6588 } 6650 }
6589 } 6651 }
6590 6652
6591 /* Wait until all slow path tasks complete */ 6653 /* Give HW time to discard old tx messages */
6592 cnt = 1000; 6654 msleep(1);
6593 while ((bp->spq_left != MAX_SPQ_PENDING) && cnt--)
6594 msleep(1);
6595 6655
6596 for_each_queue(bp, i) 6656 for_each_queue(bp, i)
6597 napi_disable(&bnx2x_fp(bp, i, napi)); 6657 napi_disable(&bnx2x_fp(bp, i, napi));
@@ -6601,52 +6661,79 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6601 /* Release IRQs */ 6661 /* Release IRQs */
6602 bnx2x_free_irq(bp); 6662 bnx2x_free_irq(bp);
6603 6663
6604 if (bp->flags & NO_WOL_FLAG) 6664 if (unload_mode == UNLOAD_NORMAL)
6665 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6666
6667 else if (bp->flags & NO_WOL_FLAG) {
6605 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 6668 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
6669 if (CHIP_IS_E1H(bp))
6670 REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
6606 6671
6607 else if (bp->wol) { 6672 } else if (bp->wol) {
6608 u32 emac_base = BP_PORT(bp) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6673 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6609 u8 *mac_addr = bp->dev->dev_addr; 6674 u8 *mac_addr = bp->dev->dev_addr;
6610 u32 val; 6675 u32 val;
6611
6612 /* The mac address is written to entries 1-4 to 6676 /* The mac address is written to entries 1-4 to
6613 preserve entry 0 which is used by the PMF */ 6677 preserve entry 0 which is used by the PMF */
6678 u8 entry = (BP_E1HVN(bp) + 1)*8;
6679
6614 val = (mac_addr[0] << 8) | mac_addr[1]; 6680 val = (mac_addr[0] << 8) | mac_addr[1];
6615 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8, val); 6681 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
6616 6682
6617 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 6683 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
6618 (mac_addr[4] << 8) | mac_addr[5]; 6684 (mac_addr[4] << 8) | mac_addr[5];
6619 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8 + 4, 6685 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
6620 val);
6621 6686
6622 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 6687 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
6623 6688
6624 } else 6689 } else
6625 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 6690 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6626 6691
6692 if (CHIP_IS_E1(bp)) {
6693 struct mac_configuration_cmd *config =
6694 bnx2x_sp(bp, mcast_config);
6695
6696 bnx2x_set_mac_addr_e1(bp, 0);
6697
6698 for (i = 0; i < config->hdr.length_6b; i++)
6699 CAM_INVALIDATE(config->config_table[i]);
6700
6701 config->hdr.length_6b = i;
6702 if (CHIP_REV_IS_SLOW(bp))
6703 config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
6704 else
6705 config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
6706 config->hdr.client_id = BP_CL_ID(bp);
6707 config->hdr.reserved1 = 0;
6708
6709 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6710 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
6711 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
6712
6713 } else { /* E1H */
6714 bnx2x_set_mac_addr_e1h(bp, 0);
6715
6716 for (i = 0; i < MC_HASH_SIZE; i++)
6717 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6718 }
6719
6720 if (CHIP_IS_E1H(bp))
6721 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
6722
6627 /* Close multi and leading connections 6723 /* Close multi and leading connections
6628 Completions for ramrods are collected in a synchronous way */ 6724 Completions for ramrods are collected in a synchronous way */
6629 for_each_nondefault_queue(bp, i) 6725 for_each_nondefault_queue(bp, i)
6630 if (bnx2x_stop_multi(bp, i)) 6726 if (bnx2x_stop_multi(bp, i))
6631 goto unload_error; 6727 goto unload_error;
6632 6728
6633 if (CHIP_IS_E1H(bp)) 6729 rc = bnx2x_stop_leading(bp);
6634 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + BP_PORT(bp)*8, 0); 6730 if (rc) {
6635
6636 bnx2x_stop_leading(bp);
6637#ifdef BNX2X_STOP_ON_ERROR
6638 /* If ramrod completion timed out - break here! */
6639 if (bp->panic) {
6640 BNX2X_ERR("Stop leading failed!\n"); 6731 BNX2X_ERR("Stop leading failed!\n");
6732#ifdef BNX2X_STOP_ON_ERROR
6641 return -EBUSY; 6733 return -EBUSY;
6642 } 6734#else
6735 goto unload_error;
6643#endif 6736#endif
6644
6645 if ((bp->state != BNX2X_STATE_CLOSING_WAIT4_UNLOAD) ||
6646 (bp->fp[0].state != BNX2X_FP_STATE_CLOSED)) {
6647 DP(NETIF_MSG_IFDOWN, "failed to close leading properly! "
6648 "state 0x%x fp[0].state 0x%x\n",
6649 bp->state, bp->fp[0].state);
6650 } 6737 }
6651 6738
6652unload_error: 6739unload_error:
@@ -6656,12 +6743,12 @@ unload_error:
6656 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n", 6743 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n",
6657 load_count[0], load_count[1], load_count[2]); 6744 load_count[0], load_count[1], load_count[2]);
6658 load_count[0]--; 6745 load_count[0]--;
6659 load_count[1 + BP_PORT(bp)]--; 6746 load_count[1 + port]--;
6660 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n", 6747 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n",
6661 load_count[0], load_count[1], load_count[2]); 6748 load_count[0], load_count[1], load_count[2]);
6662 if (load_count[0] == 0) 6749 if (load_count[0] == 0)
6663 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 6750 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
6664 else if (load_count[1 + BP_PORT(bp)] == 0) 6751 else if (load_count[1 + port] == 0)
6665 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 6752 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
6666 else 6753 else
6667 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 6754 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
@@ -6681,8 +6768,7 @@ unload_error:
6681 /* Free SKBs, SGEs, TPA pool and driver internals */ 6768 /* Free SKBs, SGEs, TPA pool and driver internals */
6682 bnx2x_free_skbs(bp); 6769 bnx2x_free_skbs(bp);
6683 for_each_queue(bp, i) 6770 for_each_queue(bp, i)
6684 bnx2x_free_rx_sge_range(bp, bp->fp + i, 6771 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
6685 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6686 bnx2x_free_mem(bp); 6772 bnx2x_free_mem(bp);
6687 6773
6688 bp->state = BNX2X_STATE_CLOSED; 6774 bp->state = BNX2X_STATE_CLOSED;
@@ -6733,56 +6819,93 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
6733 /* Check if it is the UNDI driver 6819 /* Check if it is the UNDI driver
6734 * UNDI driver initializes CID offset for normal bell to 0x7 6820 * UNDI driver initializes CID offset for normal bell to 0x7
6735 */ 6821 */
6822 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6736 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 6823 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
6737 if (val == 0x7) { 6824 if (val == 0x7) {
6738 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 6825 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6739 /* save our func and fw_seq */ 6826 /* save our func */
6740 int func = BP_FUNC(bp); 6827 int func = BP_FUNC(bp);
6741 u16 fw_seq = bp->fw_seq; 6828 u32 swap_en;
6829 u32 swap_val;
6742 6830
6743 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 6831 BNX2X_DEV_INFO("UNDI is active! reset device\n");
6744 6832
6745 /* try unload UNDI on port 0 */ 6833 /* try unload UNDI on port 0 */
6746 bp->func = 0; 6834 bp->func = 0;
6747 bp->fw_seq = (SHMEM_RD(bp, 6835 bp->fw_seq =
6748 func_mb[bp->func].drv_mb_header) & 6836 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6749 DRV_MSG_SEQ_NUMBER_MASK); 6837 DRV_MSG_SEQ_NUMBER_MASK);
6750
6751 reset_code = bnx2x_fw_command(bp, reset_code); 6838 reset_code = bnx2x_fw_command(bp, reset_code);
6752 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6753 6839
6754 /* if UNDI is loaded on the other port */ 6840 /* if UNDI is loaded on the other port */
6755 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 6841 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
6756 6842
6843 /* send "DONE" for previous unload */
6844 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6845
6846 /* unload UNDI on port 1 */
6757 bp->func = 1; 6847 bp->func = 1;
6758 bp->fw_seq = (SHMEM_RD(bp, 6848 bp->fw_seq =
6759 func_mb[bp->func].drv_mb_header) & 6849 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6760 DRV_MSG_SEQ_NUMBER_MASK); 6850 DRV_MSG_SEQ_NUMBER_MASK);
6761 6851 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6762 bnx2x_fw_command(bp, 6852
6763 DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS); 6853 bnx2x_fw_command(bp, reset_code);
6764 bnx2x_fw_command(bp,
6765 DRV_MSG_CODE_UNLOAD_DONE);
6766
6767 /* restore our func and fw_seq */
6768 bp->func = func;
6769 bp->fw_seq = fw_seq;
6770 } 6854 }
6771 6855
6856 REG_WR(bp, (BP_PORT(bp) ? HC_REG_CONFIG_1 :
6857 HC_REG_CONFIG_0), 0x1000);
6858
6859 /* close input traffic and wait for it */
6860 /* Do not rcv packets to BRB */
6861 REG_WR(bp,
6862 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
6863 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
6864 /* Do not direct rcv packets that are not for MCP to
6865 * the BRB */
6866 REG_WR(bp,
6867 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
6868 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6869 /* clear AEU */
6870 REG_WR(bp,
6871 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
6872 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
6873 msleep(10);
6874
6875 /* save NIG port swap info */
6876 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6877 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6772 /* reset device */ 6878 /* reset device */
6773 REG_WR(bp, 6879 REG_WR(bp,
6774 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6880 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6775 0xd3ffff7f); 6881 0xd3ffffff);
6776 REG_WR(bp, 6882 REG_WR(bp,
6777 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 6883 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6778 0x1403); 6884 0x1403);
6885 /* take the NIG out of reset and restore swap values */
6886 REG_WR(bp,
6887 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6888 MISC_REGISTERS_RESET_REG_1_RST_NIG);
6889 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
6890 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
6891
6892 /* send unload done to the MCP */
6893 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6894
6895 /* restore our func and fw_seq */
6896 bp->func = func;
6897 bp->fw_seq =
6898 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6899 DRV_MSG_SEQ_NUMBER_MASK);
6779 } 6900 }
6901 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6780 } 6902 }
6781} 6903}
6782 6904
6783static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 6905static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6784{ 6906{
6785 u32 val, val2, val3, val4, id; 6907 u32 val, val2, val3, val4, id;
6908 u16 pmc;
6786 6909
6787 /* Get the chip revision id and number. */ 6910 /* Get the chip revision id and number. */
6788 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 6911 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
@@ -6840,8 +6963,16 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6840 BNX2X_ERR("This driver needs bc_ver %X but found %X," 6963 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
6841 " please upgrade BC\n", BNX2X_BC_VER, val); 6964 " please upgrade BC\n", BNX2X_BC_VER, val);
6842 } 6965 }
6843 BNX2X_DEV_INFO("%sWoL Capable\n", 6966
6844 (bp->flags & NO_WOL_FLAG)? "Not " : ""); 6967 if (BP_E1HVN(bp) == 0) {
6968 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
6969 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
6970 } else {
6971 /* no WOL capability for E1HVN != 0 */
6972 bp->flags |= NO_WOL_FLAG;
6973 }
6974 BNX2X_DEV_INFO("%sWoL capable\n",
6975 (bp->flags & NO_WOL_FLAG) ? "Not " : "");
6845 6976
6846 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 6977 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
6847 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 6978 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
@@ -7274,9 +7405,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
7274 bp->mf_config = 7405 bp->mf_config =
7275 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); 7406 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
7276 7407
7277 val = 7408 val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
7278 (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) & 7409 FUNC_MF_CFG_E1HOV_TAG_MASK);
7279 FUNC_MF_CFG_E1HOV_TAG_MASK);
7280 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 7410 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7281 7411
7282 bp->e1hov = val; 7412 bp->e1hov = val;
@@ -7324,7 +7454,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
7324 7454
7325 if (BP_NOMCP(bp)) { 7455 if (BP_NOMCP(bp)) {
7326 /* only supposed to happen on emulation/FPGA */ 7456 /* only supposed to happen on emulation/FPGA */
7327 BNX2X_ERR("warning rendom MAC workaround active\n"); 7457 BNX2X_ERR("warning random MAC workaround active\n");
7328 random_ether_addr(bp->dev->dev_addr); 7458 random_ether_addr(bp->dev->dev_addr);
7329 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 7459 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7330 } 7460 }
@@ -7337,8 +7467,8 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
7337 int func = BP_FUNC(bp); 7467 int func = BP_FUNC(bp);
7338 int rc; 7468 int rc;
7339 7469
7340 if (nomcp) 7470 /* Disable interrupt handling until HW is initialized */
7341 bp->flags |= NO_MCP_FLAG; 7471 atomic_set(&bp->intr_sem, 1);
7342 7472
7343 mutex_init(&bp->port.phy_mutex); 7473 mutex_init(&bp->port.phy_mutex);
7344 7474
@@ -7377,8 +7507,6 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
7377 bp->tx_ticks = 50; 7507 bp->tx_ticks = 50;
7378 bp->rx_ticks = 25; 7508 bp->rx_ticks = 25;
7379 7509
7380 bp->stats_ticks = 1000000 & 0xffff00;
7381
7382 bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 7510 bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
7383 bp->current_interval = (poll ? poll : bp->timer_interval); 7511 bp->current_interval = (poll ? poll : bp->timer_interval);
7384 7512
@@ -7628,25 +7756,25 @@ static void bnx2x_get_drvinfo(struct net_device *dev,
7628 struct ethtool_drvinfo *info) 7756 struct ethtool_drvinfo *info)
7629{ 7757{
7630 struct bnx2x *bp = netdev_priv(dev); 7758 struct bnx2x *bp = netdev_priv(dev);
7631 char phy_fw_ver[PHY_FW_VER_LEN]; 7759 u8 phy_fw_ver[PHY_FW_VER_LEN];
7632 7760
7633 strcpy(info->driver, DRV_MODULE_NAME); 7761 strcpy(info->driver, DRV_MODULE_NAME);
7634 strcpy(info->version, DRV_MODULE_VERSION); 7762 strcpy(info->version, DRV_MODULE_VERSION);
7635 7763
7636 phy_fw_ver[0] = '\0'; 7764 phy_fw_ver[0] = '\0';
7637 if (bp->port.pmf) { 7765 if (bp->port.pmf) {
7638 bnx2x_phy_hw_lock(bp); 7766 bnx2x_acquire_phy_lock(bp);
7639 bnx2x_get_ext_phy_fw_version(&bp->link_params, 7767 bnx2x_get_ext_phy_fw_version(&bp->link_params,
7640 (bp->state != BNX2X_STATE_CLOSED), 7768 (bp->state != BNX2X_STATE_CLOSED),
7641 phy_fw_ver, PHY_FW_VER_LEN); 7769 phy_fw_ver, PHY_FW_VER_LEN);
7642 bnx2x_phy_hw_unlock(bp); 7770 bnx2x_release_phy_lock(bp);
7643 } 7771 }
7644 7772
7645 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s", 7773 snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s",
7646 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION, 7774 (bp->common.bc_ver & 0xff0000) >> 16,
7647 BCM_5710_FW_REVISION_VERSION, 7775 (bp->common.bc_ver & 0xff00) >> 8,
7648 BCM_5710_FW_COMPILE_FLAGS, bp->common.bc_ver, 7776 (bp->common.bc_ver & 0xff),
7649 ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver); 7777 ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver);
7650 strcpy(info->bus_info, pci_name(bp->pdev)); 7778 strcpy(info->bus_info, pci_name(bp->pdev));
7651 info->n_stats = BNX2X_NUM_STATS; 7779 info->n_stats = BNX2X_NUM_STATS;
7652 info->testinfo_len = BNX2X_NUM_TESTS; 7780 info->testinfo_len = BNX2X_NUM_TESTS;
@@ -8097,7 +8225,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8097 if (eeprom->magic == 0x00504859) 8225 if (eeprom->magic == 0x00504859)
8098 if (bp->port.pmf) { 8226 if (bp->port.pmf) {
8099 8227
8100 bnx2x_phy_hw_lock(bp); 8228 bnx2x_acquire_phy_lock(bp);
8101 rc = bnx2x_flash_download(bp, BP_PORT(bp), 8229 rc = bnx2x_flash_download(bp, BP_PORT(bp),
8102 bp->link_params.ext_phy_config, 8230 bp->link_params.ext_phy_config,
8103 (bp->state != BNX2X_STATE_CLOSED), 8231 (bp->state != BNX2X_STATE_CLOSED),
@@ -8109,7 +8237,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8109 rc |= bnx2x_phy_init(&bp->link_params, 8237 rc |= bnx2x_phy_init(&bp->link_params,
8110 &bp->link_vars); 8238 &bp->link_vars);
8111 } 8239 }
8112 bnx2x_phy_hw_unlock(bp); 8240 bnx2x_release_phy_lock(bp);
8113 8241
8114 } else /* Only the PMF can access the PHY */ 8242 } else /* Only the PMF can access the PHY */
8115 return -EINVAL; 8243 return -EINVAL;
@@ -8128,7 +8256,6 @@ static int bnx2x_get_coalesce(struct net_device *dev,
8128 8256
8129 coal->rx_coalesce_usecs = bp->rx_ticks; 8257 coal->rx_coalesce_usecs = bp->rx_ticks;
8130 coal->tx_coalesce_usecs = bp->tx_ticks; 8258 coal->tx_coalesce_usecs = bp->tx_ticks;
8131 coal->stats_block_coalesce_usecs = bp->stats_ticks;
8132 8259
8133 return 0; 8260 return 0;
8134} 8261}
@@ -8146,44 +8273,12 @@ static int bnx2x_set_coalesce(struct net_device *dev,
8146 if (bp->tx_ticks > 0x3000) 8273 if (bp->tx_ticks > 0x3000)
8147 bp->tx_ticks = 0x3000; 8274 bp->tx_ticks = 0x3000;
8148 8275
8149 bp->stats_ticks = coal->stats_block_coalesce_usecs;
8150 if (bp->stats_ticks > 0xffff00)
8151 bp->stats_ticks = 0xffff00;
8152 bp->stats_ticks &= 0xffff00;
8153
8154 if (netif_running(dev)) 8276 if (netif_running(dev))
8155 bnx2x_update_coalesce(bp); 8277 bnx2x_update_coalesce(bp);
8156 8278
8157 return 0; 8279 return 0;
8158} 8280}
8159 8281
8160static int bnx2x_set_flags(struct net_device *dev, u32 data)
8161{
8162 struct bnx2x *bp = netdev_priv(dev);
8163 int changed = 0;
8164 int rc = 0;
8165
8166 if (data & ETH_FLAG_LRO) {
8167 if (!(dev->features & NETIF_F_LRO)) {
8168 dev->features |= NETIF_F_LRO;
8169 bp->flags |= TPA_ENABLE_FLAG;
8170 changed = 1;
8171 }
8172
8173 } else if (dev->features & NETIF_F_LRO) {
8174 dev->features &= ~NETIF_F_LRO;
8175 bp->flags &= ~TPA_ENABLE_FLAG;
8176 changed = 1;
8177 }
8178
8179 if (changed && netif_running(dev)) {
8180 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8181 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8182 }
8183
8184 return rc;
8185}
8186
8187static void bnx2x_get_ringparam(struct net_device *dev, 8282static void bnx2x_get_ringparam(struct net_device *dev,
8188 struct ethtool_ringparam *ering) 8283 struct ethtool_ringparam *ering)
8189{ 8284{
@@ -8266,7 +8361,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
8266 8361
8267 if (epause->autoneg) { 8362 if (epause->autoneg) {
8268 if (!(bp->port.supported & SUPPORTED_Autoneg)) { 8363 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
8269 DP(NETIF_MSG_LINK, "Autoneg not supported\n"); 8364 DP(NETIF_MSG_LINK, "autoneg not supported\n");
8270 return -EINVAL; 8365 return -EINVAL;
8271 } 8366 }
8272 8367
@@ -8285,6 +8380,34 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
8285 return 0; 8380 return 0;
8286} 8381}
8287 8382
8383static int bnx2x_set_flags(struct net_device *dev, u32 data)
8384{
8385 struct bnx2x *bp = netdev_priv(dev);
8386 int changed = 0;
8387 int rc = 0;
8388
8389 /* TPA requires Rx CSUM offloading */
8390 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
8391 if (!(dev->features & NETIF_F_LRO)) {
8392 dev->features |= NETIF_F_LRO;
8393 bp->flags |= TPA_ENABLE_FLAG;
8394 changed = 1;
8395 }
8396
8397 } else if (dev->features & NETIF_F_LRO) {
8398 dev->features &= ~NETIF_F_LRO;
8399 bp->flags &= ~TPA_ENABLE_FLAG;
8400 changed = 1;
8401 }
8402
8403 if (changed && netif_running(dev)) {
8404 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8405 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8406 }
8407
8408 return rc;
8409}
8410
8288static u32 bnx2x_get_rx_csum(struct net_device *dev) 8411static u32 bnx2x_get_rx_csum(struct net_device *dev)
8289{ 8412{
8290 struct bnx2x *bp = netdev_priv(dev); 8413 struct bnx2x *bp = netdev_priv(dev);
@@ -8295,9 +8418,19 @@ static u32 bnx2x_get_rx_csum(struct net_device *dev)
8295static int bnx2x_set_rx_csum(struct net_device *dev, u32 data) 8418static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
8296{ 8419{
8297 struct bnx2x *bp = netdev_priv(dev); 8420 struct bnx2x *bp = netdev_priv(dev);
8421 int rc = 0;
8298 8422
8299 bp->rx_csum = data; 8423 bp->rx_csum = data;
8300 return 0; 8424
8425 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
8426 TPA'ed packets will be discarded due to wrong TCP CSUM */
8427 if (!data) {
8428 u32 flags = ethtool_op_get_flags(dev);
8429
8430 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
8431 }
8432
8433 return rc;
8301} 8434}
8302 8435
8303static int bnx2x_set_tso(struct net_device *dev, u32 data) 8436static int bnx2x_set_tso(struct net_device *dev, u32 data)
@@ -8335,6 +8468,7 @@ static int bnx2x_test_registers(struct bnx2x *bp)
8335{ 8468{
8336 int idx, i, rc = -ENODEV; 8469 int idx, i, rc = -ENODEV;
8337 u32 wr_val = 0; 8470 u32 wr_val = 0;
8471 int port = BP_PORT(bp);
8338 static const struct { 8472 static const struct {
8339 u32 offset0; 8473 u32 offset0;
8340 u32 offset1; 8474 u32 offset1;
@@ -8400,7 +8534,6 @@ static int bnx2x_test_registers(struct bnx2x *bp)
8400 8534
8401 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 8535 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
8402 u32 offset, mask, save_val, val; 8536 u32 offset, mask, save_val, val;
8403 int port = BP_PORT(bp);
8404 8537
8405 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 8538 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
8406 mask = reg_tbl[i].mask; 8539 mask = reg_tbl[i].mask;
@@ -8446,16 +8579,17 @@ static int bnx2x_test_memory(struct bnx2x *bp)
8446 static const struct { 8579 static const struct {
8447 char *name; 8580 char *name;
8448 u32 offset; 8581 u32 offset;
8449 u32 mask; 8582 u32 e1_mask;
8583 u32 e1h_mask;
8450 } prty_tbl[] = { 8584 } prty_tbl[] = {
8451 { "CCM_REG_CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0 }, 8585 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 },
8452 { "CFC_REG_CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0 }, 8586 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 },
8453 { "DMAE_REG_DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0 }, 8587 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 },
8454 { "TCM_REG_TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0 }, 8588 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 },
8455 { "UCM_REG_UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0 }, 8589 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 },
8456 { "XCM_REG_XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x1 }, 8590 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 },
8457 8591
8458 { NULL, 0xffffffff, 0 } 8592 { NULL, 0xffffffff, 0, 0 }
8459 }; 8593 };
8460 8594
8461 if (!netif_running(bp->dev)) 8595 if (!netif_running(bp->dev))
@@ -8469,7 +8603,8 @@ static int bnx2x_test_memory(struct bnx2x *bp)
8469 /* Check the parity status */ 8603 /* Check the parity status */
8470 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 8604 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
8471 val = REG_RD(bp, prty_tbl[i].offset); 8605 val = REG_RD(bp, prty_tbl[i].offset);
8472 if (val & ~(prty_tbl[i].mask)) { 8606 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
8607 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
8473 DP(NETIF_MSG_HW, 8608 DP(NETIF_MSG_HW,
8474 "%s is 0x%x\n", prty_tbl[i].name, val); 8609 "%s is 0x%x\n", prty_tbl[i].name, val);
8475 goto test_mem_exit; 8610 goto test_mem_exit;
@@ -8539,15 +8674,15 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
8539 8674
8540 if (loopback_mode == BNX2X_MAC_LOOPBACK) { 8675 if (loopback_mode == BNX2X_MAC_LOOPBACK) {
8541 bp->link_params.loopback_mode = LOOPBACK_BMAC; 8676 bp->link_params.loopback_mode = LOOPBACK_BMAC;
8542 bnx2x_phy_hw_lock(bp); 8677 bnx2x_acquire_phy_lock(bp);
8543 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 8678 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8544 bnx2x_phy_hw_unlock(bp); 8679 bnx2x_release_phy_lock(bp);
8545 8680
8546 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) { 8681 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
8547 bp->link_params.loopback_mode = LOOPBACK_XGXS_10; 8682 bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
8548 bnx2x_phy_hw_lock(bp); 8683 bnx2x_acquire_phy_lock(bp);
8549 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 8684 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8550 bnx2x_phy_hw_unlock(bp); 8685 bnx2x_release_phy_lock(bp);
8551 /* wait until link state is restored */ 8686 /* wait until link state is restored */
8552 bnx2x_wait_for_link(bp, link_up); 8687 bnx2x_wait_for_link(bp, link_up);
8553 8688
@@ -8771,7 +8906,7 @@ static void bnx2x_self_test(struct net_device *dev,
8771 if (!netif_running(dev)) 8906 if (!netif_running(dev))
8772 return; 8907 return;
8773 8908
8774 /* offline tests are not suppoerted in MF mode */ 8909 /* offline tests are not supported in MF mode */
8775 if (IS_E1HMF(bp)) 8910 if (IS_E1HMF(bp))
8776 etest->flags &= ~ETH_TEST_FL_OFFLINE; 8911 etest->flags &= ~ETH_TEST_FL_OFFLINE;
8777 8912
@@ -8827,76 +8962,99 @@ static const struct {
8827 long offset; 8962 long offset;
8828 int size; 8963 int size;
8829 u32 flags; 8964 u32 flags;
8830 char string[ETH_GSTRING_LEN]; 8965#define STATS_FLAGS_PORT 1
8966#define STATS_FLAGS_FUNC 2
8967 u8 string[ETH_GSTRING_LEN];
8831} bnx2x_stats_arr[BNX2X_NUM_STATS] = { 8968} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
8832/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi), 8, 1, "rx_bytes" }, 8969/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi),
8833 { STATS_OFFSET32(error_bytes_received_hi), 8, 1, "rx_error_bytes" }, 8970 8, STATS_FLAGS_FUNC, "rx_bytes" },
8834 { STATS_OFFSET32(total_bytes_transmitted_hi), 8, 1, "tx_bytes" }, 8971 { STATS_OFFSET32(error_bytes_received_hi),
8835 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 8, 0, "tx_error_bytes" }, 8972 8, STATS_FLAGS_FUNC, "rx_error_bytes" },
8973 { STATS_OFFSET32(total_bytes_transmitted_hi),
8974 8, STATS_FLAGS_FUNC, "tx_bytes" },
8975 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
8976 8, STATS_FLAGS_PORT, "tx_error_bytes" },
8836 { STATS_OFFSET32(total_unicast_packets_received_hi), 8977 { STATS_OFFSET32(total_unicast_packets_received_hi),
8837 8, 1, "rx_ucast_packets" }, 8978 8, STATS_FLAGS_FUNC, "rx_ucast_packets" },
8838 { STATS_OFFSET32(total_multicast_packets_received_hi), 8979 { STATS_OFFSET32(total_multicast_packets_received_hi),
8839 8, 1, "rx_mcast_packets" }, 8980 8, STATS_FLAGS_FUNC, "rx_mcast_packets" },
8840 { STATS_OFFSET32(total_broadcast_packets_received_hi), 8981 { STATS_OFFSET32(total_broadcast_packets_received_hi),
8841 8, 1, "rx_bcast_packets" }, 8982 8, STATS_FLAGS_FUNC, "rx_bcast_packets" },
8842 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 8983 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8843 8, 1, "tx_packets" }, 8984 8, STATS_FLAGS_FUNC, "tx_packets" },
8844 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 8985 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
8845 8, 0, "tx_mac_errors" }, 8986 8, STATS_FLAGS_PORT, "tx_mac_errors" },
8846/* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 8987/* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
8847 8, 0, "tx_carrier_errors" }, 8988 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
8848 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 8989 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
8849 8, 0, "rx_crc_errors" }, 8990 8, STATS_FLAGS_PORT, "rx_crc_errors" },
8850 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 8991 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
8851 8, 0, "rx_align_errors" }, 8992 8, STATS_FLAGS_PORT, "rx_align_errors" },
8852 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 8993 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
8853 8, 0, "tx_single_collisions" }, 8994 8, STATS_FLAGS_PORT, "tx_single_collisions" },
8854 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 8995 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
8855 8, 0, "tx_multi_collisions" }, 8996 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
8856 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 8997 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
8857 8, 0, "tx_deferred" }, 8998 8, STATS_FLAGS_PORT, "tx_deferred" },
8858 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 8999 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
8859 8, 0, "tx_excess_collisions" }, 9000 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
8860 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 9001 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
8861 8, 0, "tx_late_collisions" }, 9002 8, STATS_FLAGS_PORT, "tx_late_collisions" },
8862 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 9003 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
8863 8, 0, "tx_total_collisions" }, 9004 8, STATS_FLAGS_PORT, "tx_total_collisions" },
8864 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 9005 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
8865 8, 0, "rx_fragments" }, 9006 8, STATS_FLAGS_PORT, "rx_fragments" },
8866/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 8, 0, "rx_jabbers" }, 9007/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
9008 8, STATS_FLAGS_PORT, "rx_jabbers" },
8867 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 9009 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
8868 8, 0, "rx_undersize_packets" }, 9010 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
8869 { STATS_OFFSET32(jabber_packets_received), 9011 { STATS_OFFSET32(jabber_packets_received),
8870 4, 1, "rx_oversize_packets" }, 9012 4, STATS_FLAGS_FUNC, "rx_oversize_packets" },
8871 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 9013 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
8872 8, 0, "tx_64_byte_packets" }, 9014 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
8873 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 9015 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
8874 8, 0, "tx_65_to_127_byte_packets" }, 9016 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
8875 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 9017 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
8876 8, 0, "tx_128_to_255_byte_packets" }, 9018 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
8877 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 9019 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
8878 8, 0, "tx_256_to_511_byte_packets" }, 9020 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
8879 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 9021 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
8880 8, 0, "tx_512_to_1023_byte_packets" }, 9022 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
8881 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 9023 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
8882 8, 0, "tx_1024_to_1522_byte_packets" }, 9024 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
8883 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 9025 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
8884 8, 0, "tx_1523_to_9022_byte_packets" }, 9026 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
8885/* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi), 9027/* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi),
8886 8, 0, "rx_xon_frames" }, 9028 8, STATS_FLAGS_PORT, "rx_xon_frames" },
8887 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi), 9029 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi),
8888 8, 0, "rx_xoff_frames" }, 9030 8, STATS_FLAGS_PORT, "rx_xoff_frames" },
8889 { STATS_OFFSET32(tx_stat_outxonsent_hi), 8, 0, "tx_xon_frames" }, 9031 { STATS_OFFSET32(tx_stat_outxonsent_hi),
8890 { STATS_OFFSET32(tx_stat_outxoffsent_hi), 8, 0, "tx_xoff_frames" }, 9032 8, STATS_FLAGS_PORT, "tx_xon_frames" },
9033 { STATS_OFFSET32(tx_stat_outxoffsent_hi),
9034 8, STATS_FLAGS_PORT, "tx_xoff_frames" },
8891 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 9035 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
8892 8, 0, "rx_mac_ctrl_frames" }, 9036 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
8893 { STATS_OFFSET32(mac_filter_discard), 4, 1, "rx_filtered_packets" }, 9037 { STATS_OFFSET32(mac_filter_discard),
8894 { STATS_OFFSET32(no_buff_discard), 4, 1, "rx_discards" }, 9038 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
8895 { STATS_OFFSET32(xxoverflow_discard), 4, 1, "rx_fw_discards" }, 9039 { STATS_OFFSET32(no_buff_discard),
8896 { STATS_OFFSET32(brb_drop_hi), 8, 1, "brb_discard" }, 9040 4, STATS_FLAGS_FUNC, "rx_discards" },
8897/* 39 */{ STATS_OFFSET32(brb_truncate_discard), 8, 1, "brb_truncate" } 9041 { STATS_OFFSET32(xxoverflow_discard),
9042 4, STATS_FLAGS_PORT, "rx_fw_discards" },
9043 { STATS_OFFSET32(brb_drop_hi),
9044 8, STATS_FLAGS_PORT, "brb_discard" },
9045 { STATS_OFFSET32(brb_truncate_hi),
9046 8, STATS_FLAGS_PORT, "brb_truncate" },
9047/* 40 */{ STATS_OFFSET32(rx_err_discard_pkt),
9048 4, STATS_FLAGS_FUNC, "rx_phy_ip_err_discards"},
9049 { STATS_OFFSET32(rx_skb_alloc_failed),
9050 4, STATS_FLAGS_FUNC, "rx_skb_alloc_discard" },
9051/* 42 */{ STATS_OFFSET32(hw_csum_err),
9052 4, STATS_FLAGS_FUNC, "rx_csum_offload_errors" }
8898}; 9053};
8899 9054
9055#define IS_NOT_E1HMF_STAT(bp, i) \
9056 (IS_E1HMF(bp) && (bnx2x_stats_arr[i].flags & STATS_FLAGS_PORT))
9057
8900static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 9058static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
8901{ 9059{
8902 struct bnx2x *bp = netdev_priv(dev); 9060 struct bnx2x *bp = netdev_priv(dev);
@@ -8905,7 +9063,7 @@ static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
8905 switch (stringset) { 9063 switch (stringset) {
8906 case ETH_SS_STATS: 9064 case ETH_SS_STATS:
8907 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 9065 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
8908 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) 9066 if (IS_NOT_E1HMF_STAT(bp, i))
8909 continue; 9067 continue;
8910 strcpy(buf + j*ETH_GSTRING_LEN, 9068 strcpy(buf + j*ETH_GSTRING_LEN,
8911 bnx2x_stats_arr[i].string); 9069 bnx2x_stats_arr[i].string);
@@ -8925,7 +9083,7 @@ static int bnx2x_get_stats_count(struct net_device *dev)
8925 int i, num_stats = 0; 9083 int i, num_stats = 0;
8926 9084
8927 for (i = 0; i < BNX2X_NUM_STATS; i++) { 9085 for (i = 0; i < BNX2X_NUM_STATS; i++) {
8928 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) 9086 if (IS_NOT_E1HMF_STAT(bp, i))
8929 continue; 9087 continue;
8930 num_stats++; 9088 num_stats++;
8931 } 9089 }
@@ -8940,7 +9098,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
8940 int i, j; 9098 int i, j;
8941 9099
8942 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 9100 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
8943 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) 9101 if (IS_NOT_E1HMF_STAT(bp, i))
8944 continue; 9102 continue;
8945 9103
8946 if (bnx2x_stats_arr[i].size == 0) { 9104 if (bnx2x_stats_arr[i].size == 0) {
@@ -9057,7 +9215,7 @@ static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
9057 PCI_PM_CTRL_PME_STATUS)); 9215 PCI_PM_CTRL_PME_STATUS));
9058 9216
9059 if (pmcsr & PCI_PM_CTRL_STATE_MASK) 9217 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
9060 /* delay required during transition out of D3hot */ 9218 /* delay required during transition out of D3hot */
9061 msleep(20); 9219 msleep(20);
9062 break; 9220 break;
9063 9221
@@ -9104,17 +9262,16 @@ static int bnx2x_poll(struct napi_struct *napi, int budget)
9104 9262
9105 bnx2x_update_fpsb_idx(fp); 9263 bnx2x_update_fpsb_idx(fp);
9106 9264
9107 if ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || 9265 if (BNX2X_HAS_TX_WORK(fp))
9108 (fp->tx_pkt_prod != fp->tx_pkt_cons))
9109 bnx2x_tx_int(fp, budget); 9266 bnx2x_tx_int(fp, budget);
9110 9267
9111 if (le16_to_cpu(*fp->rx_cons_sb) != fp->rx_comp_cons) 9268 if (BNX2X_HAS_RX_WORK(fp))
9112 work_done = bnx2x_rx_int(fp, budget); 9269 work_done = bnx2x_rx_int(fp, budget);
9113 9270
9114 rmb(); /* bnx2x_has_work() reads the status block */ 9271 rmb(); /* BNX2X_HAS_WORK() reads the status block */
9115 9272
9116 /* must not complete if we consumed full budget */ 9273 /* must not complete if we consumed full budget */
9117 if ((work_done < budget) && !bnx2x_has_work(fp)) { 9274 if ((work_done < budget) && !BNX2X_HAS_WORK(fp)) {
9118 9275
9119#ifdef BNX2X_STOP_ON_ERROR 9276#ifdef BNX2X_STOP_ON_ERROR
9120poll_panic: 9277poll_panic:
@@ -9131,7 +9288,7 @@ poll_panic:
9131 9288
9132 9289
9133/* we split the first BD into headers and data BDs 9290/* we split the first BD into headers and data BDs
9134 * to ease the pain of our fellow micocode engineers 9291 * to ease the pain of our fellow microcode engineers
9135 * we use one mapping for both BDs 9292 * we use one mapping for both BDs
9136 * So far this has only been observed to happen 9293 * So far this has only been observed to happen
9137 * in Other Operating Systems(TM) 9294 * in Other Operating Systems(TM)
@@ -9238,7 +9395,7 @@ static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
9238 /* Check if LSO packet needs to be copied: 9395 /* Check if LSO packet needs to be copied:
9239 3 = 1 (for headers BD) + 2 (for PBD and last BD) */ 9396 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
9240 int wnd_size = MAX_FETCH_BD - 3; 9397 int wnd_size = MAX_FETCH_BD - 3;
9241 /* Number of widnows to check */ 9398 /* Number of windows to check */
9242 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size; 9399 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
9243 int wnd_idx = 0; 9400 int wnd_idx = 0;
9244 int frag_idx = 0; 9401 int frag_idx = 0;
@@ -9340,7 +9497,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9340 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr, 9497 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
9341 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type); 9498 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
9342 9499
9343 /* First, check if we need to linearaize the skb 9500 /* First, check if we need to linearize the skb
9344 (due to FW restrictions) */ 9501 (due to FW restrictions) */
9345 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) { 9502 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
9346 /* Statistics of linearization */ 9503 /* Statistics of linearization */
@@ -9349,7 +9506,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9349 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - " 9506 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
9350 "silently dropping this SKB\n"); 9507 "silently dropping this SKB\n");
9351 dev_kfree_skb_any(skb); 9508 dev_kfree_skb_any(skb);
9352 return 0; 9509 return NETDEV_TX_OK;
9353 } 9510 }
9354 } 9511 }
9355 9512
@@ -9372,7 +9529,8 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9372 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 9529 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9373 tx_bd->general_data = (UNICAST_ADDRESS << 9530 tx_bd->general_data = (UNICAST_ADDRESS <<
9374 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT); 9531 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
9375 tx_bd->general_data |= 1; /* header nbd */ 9532 /* header nbd */
9533 tx_bd->general_data |= (1 << ETH_TX_BD_HDR_NBDS_SHIFT);
9376 9534
9377 /* remember the first BD of the packet */ 9535 /* remember the first BD of the packet */
9378 tx_buf->first_bd = fp->tx_bd_prod; 9536 tx_buf->first_bd = fp->tx_bd_prod;
@@ -9451,7 +9609,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9451 9609
9452 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 9610 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9453 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 9611 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9454 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2); 9612 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL) ? 1 : 2);
9455 tx_bd->nbd = cpu_to_le16(nbd); 9613 tx_bd->nbd = cpu_to_le16(nbd);
9456 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 9614 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9457 9615
@@ -9721,9 +9879,9 @@ static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9721 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 9879 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9722 if (netif_running(dev)) { 9880 if (netif_running(dev)) {
9723 if (CHIP_IS_E1(bp)) 9881 if (CHIP_IS_E1(bp))
9724 bnx2x_set_mac_addr_e1(bp); 9882 bnx2x_set_mac_addr_e1(bp, 1);
9725 else 9883 else
9726 bnx2x_set_mac_addr_e1h(bp); 9884 bnx2x_set_mac_addr_e1h(bp, 1);
9727 } 9885 }
9728 9886
9729 return 0; 9887 return 0;
@@ -9734,6 +9892,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9734{ 9892{
9735 struct mii_ioctl_data *data = if_mii(ifr); 9893 struct mii_ioctl_data *data = if_mii(ifr);
9736 struct bnx2x *bp = netdev_priv(dev); 9894 struct bnx2x *bp = netdev_priv(dev);
9895 int port = BP_PORT(bp);
9737 int err; 9896 int err;
9738 9897
9739 switch (cmd) { 9898 switch (cmd) {
@@ -9749,7 +9908,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9749 return -EAGAIN; 9908 return -EAGAIN;
9750 9909
9751 mutex_lock(&bp->port.phy_mutex); 9910 mutex_lock(&bp->port.phy_mutex);
9752 err = bnx2x_cl45_read(bp, BP_PORT(bp), 0, bp->port.phy_addr, 9911 err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr,
9753 DEFAULT_PHY_DEV_ADDR, 9912 DEFAULT_PHY_DEV_ADDR,
9754 (data->reg_num & 0x1f), &mii_regval); 9913 (data->reg_num & 0x1f), &mii_regval);
9755 data->val_out = mii_regval; 9914 data->val_out = mii_regval;
@@ -9765,7 +9924,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9765 return -EAGAIN; 9924 return -EAGAIN;
9766 9925
9767 mutex_lock(&bp->port.phy_mutex); 9926 mutex_lock(&bp->port.phy_mutex);
9768 err = bnx2x_cl45_write(bp, BP_PORT(bp), 0, bp->port.phy_addr, 9927 err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr,
9769 DEFAULT_PHY_DEV_ADDR, 9928 DEFAULT_PHY_DEV_ADDR,
9770 (data->reg_num & 0x1f), data->val_in); 9929 (data->reg_num & 0x1f), data->val_in);
9771 mutex_unlock(&bp->port.phy_mutex); 9930 mutex_unlock(&bp->port.phy_mutex);
@@ -10141,7 +10300,7 @@ static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
10141 10300
10142 netif_device_detach(dev); 10301 netif_device_detach(dev);
10143 10302
10144 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 10303 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10145 10304
10146 bnx2x_set_power_state(bp, pci_choose_state(pdev, state)); 10305 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
10147 10306
@@ -10174,7 +10333,7 @@ static int bnx2x_resume(struct pci_dev *pdev)
10174 bnx2x_set_power_state(bp, PCI_D0); 10333 bnx2x_set_power_state(bp, PCI_D0);
10175 netif_device_attach(dev); 10334 netif_device_attach(dev);
10176 10335
10177 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 10336 rc = bnx2x_nic_load(bp, LOAD_OPEN);
10178 10337
10179 rtnl_unlock(); 10338 rtnl_unlock();
10180 10339
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 15c9a9946724..a67b0c358ae4 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -6,7 +6,7 @@
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation. 7 * the Free Software Foundation.
8 * 8 *
9 * The registers description starts with the regsister Access type followed 9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are: 10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only 11 * R - Read only
12 * RC - Clear on read 12 * RC - Clear on read
@@ -49,7 +49,7 @@
49/* [RW 10] Write client 0: Assert pause threshold. */ 49/* [RW 10] Write client 0: Assert pause threshold. */
50#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 50#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
51#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c 51#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
52/* [R 24] The number of full blocks occpied by port. */ 52/* [R 24] The number of full blocks occupied by port. */
53#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 53#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
54/* [RW 1] Reset the design by software. */ 54/* [RW 1] Reset the design by software. */
55#define BRB1_REG_SOFT_RESET 0x600dc 55#define BRB1_REG_SOFT_RESET 0x600dc
@@ -740,6 +740,7 @@
740#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 740#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
741#define HC_REG_ATTN_NUM_P0 0x108038 741#define HC_REG_ATTN_NUM_P0 0x108038
742#define HC_REG_ATTN_NUM_P1 0x10803c 742#define HC_REG_ATTN_NUM_P1 0x10803c
743#define HC_REG_COMMAND_REG 0x108180
743#define HC_REG_CONFIG_0 0x108000 744#define HC_REG_CONFIG_0 0x108000
744#define HC_REG_CONFIG_1 0x108004 745#define HC_REG_CONFIG_1 0x108004
745#define HC_REG_FUNC_NUM_P0 0x1080ac 746#define HC_REG_FUNC_NUM_P0 0x1080ac
@@ -1372,6 +1373,23 @@
1372 be asserted). */ 1373 be asserted). */
1373#define MISC_REG_DRIVER_CONTROL_16 0xa5f0 1374#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1374#define MISC_REG_DRIVER_CONTROL_16_SIZE 2 1375#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1376/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1377 32 clients. Each client can be controlled by one driver only. One in each
1378 bit represent that this driver control the appropriate client (Ex: bit 5
1379 is set means this driver control client number 5). addr1 = set; addr0 =
1380 clear; read from both addresses will give the same result = status. write
1381 to address 1 will set a request to control all the clients that their
1382 appropriate bit (in the write command) is set. if the client is free (the
1383 appropriate bit in all the other drivers is clear) one will be written to
1384 that driver register; if the client isn't free the bit will remain zero.
1385 if the appropriate bit is set (the driver request to gain control on a
1386 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1387 interrupt will be asserted). write to address 0 will set a request to
1388 free all the clients that their appropriate bit (in the write command) is
1389 set. if the appropriate bit is clear (the driver request to free a client
1390 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1391 be asserted). */
1392#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1375/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1393/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1376 only. */ 1394 only. */
1377#define MISC_REG_E1HMF_MODE 0xa5f8 1395#define MISC_REG_E1HMF_MODE 0xa5f8
@@ -1394,13 +1412,13 @@
1394#define MISC_REG_GPIO 0xa490 1412#define MISC_REG_GPIO 0xa490
1395/* [R 28] this field hold the last information that caused reserved 1413/* [R 28] this field hold the last information that caused reserved
1396 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1414 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1397 [27:24] the master thatcaused the attention - according to the following 1415 [27:24] the master that caused the attention - according to the following
1398 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1416 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1399 dbu; 8 = dmae */ 1417 dbu; 8 = dmae */
1400#define MISC_REG_GRC_RSV_ATTN 0xa3c0 1418#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1401/* [R 28] this field hold the last information that caused timeout 1419/* [R 28] this field hold the last information that caused timeout
1402 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1420 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1403 [27:24] the master thatcaused the attention - according to the following 1421 [27:24] the master that caused the attention - according to the following
1404 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1422 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1405 dbu; 8 = dmae */ 1423 dbu; 8 = dmae */
1406#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1424#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
@@ -1677,6 +1695,7 @@
1677/* [RW 8] init credit counter for port0 in LLH */ 1695/* [RW 8] init credit counter for port0 in LLH */
1678#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1696#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1679#define NIG_REG_LLH0_XCM_MASK 0x10130 1697#define NIG_REG_LLH0_XCM_MASK 0x10130
1698#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1680/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1699/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1681#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1700#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1682/* [RW 2] Determine the classification participants. 0: no classification.1: 1701/* [RW 2] Determine the classification participants. 0: no classification.1:
@@ -1727,6 +1746,9 @@
1727/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1746/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1728 for port0 */ 1747 for port0 */
1729#define NIG_REG_STAT0_BRB_DISCARD 0x105f0 1748#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1749/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1750 for port0 */
1751#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1730/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 1752/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1731 between 1024 and 1522 bytes for port0 */ 1753 between 1024 and 1522 bytes for port0 */
1732#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 1754#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
@@ -2298,7 +2320,7 @@
2298/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 2320/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2299 -128k */ 2321 -128k */
2300#define PXP2_REG_RQ_QM_P_SIZE 0x120050 2322#define PXP2_REG_RQ_QM_P_SIZE 0x120050
2301/* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */ 2323/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2302#define PXP2_REG_RQ_RBC_DONE 0x1201b0 2324#define PXP2_REG_RQ_RBC_DONE 0x1201b0
2303/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 2325/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2304 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 2326 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
@@ -2406,7 +2428,7 @@
2406/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2428/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2407 buffer reaches this number has_payload will be asserted */ 2429 buffer reaches this number has_payload will be asserted */
2408#define PXP2_REG_WR_DMAE_MPS 0x1205ec 2430#define PXP2_REG_WR_DMAE_MPS 0x1205ec
2409/* [RW 10] if Number of entries in dmae fifo will be higer than this 2431/* [RW 10] if Number of entries in dmae fifo will be higher than this
2410 threshold then has_payload indication will be asserted; the default value 2432 threshold then has_payload indication will be asserted; the default value
2411 should be equal to &gt; write MBS size! */ 2433 should be equal to &gt; write MBS size! */
2412#define PXP2_REG_WR_DMAE_TH 0x120368 2434#define PXP2_REG_WR_DMAE_TH 0x120368
@@ -2427,7 +2449,7 @@
2427/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2449/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2428 buffer reaches this number has_payload will be asserted */ 2450 buffer reaches this number has_payload will be asserted */
2429#define PXP2_REG_WR_TSDM_MPS 0x1205d4 2451#define PXP2_REG_WR_TSDM_MPS 0x1205d4
2430/* [RW 10] if Number of entries in usdmdp fifo will be higer than this 2452/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
2431 threshold then has_payload indication will be asserted; the default value 2453 threshold then has_payload indication will be asserted; the default value
2432 should be equal to &gt; write MBS size! */ 2454 should be equal to &gt; write MBS size! */
2433#define PXP2_REG_WR_USDMDP_TH 0x120348 2455#define PXP2_REG_WR_USDMDP_TH 0x120348
@@ -3294,12 +3316,12 @@
3294#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3316#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3295#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) 3317#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3296#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 3318#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
3297/* [R 1] debug only: This bit indicates wheter indicates that external 3319/* [R 1] debug only: This bit indicates whether indicates that external
3298 buffer was wrapped (oldest data was thrown); Relevant only when 3320 buffer was wrapped (oldest data was thrown); Relevant only when
3299 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */ 3321 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3300#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124 3322#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3301#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1 3323#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
3302/* [R 1] debug only: This bit indicates wheter the internal buffer was 3324/* [R 1] debug only: This bit indicates whether the internal buffer was
3303 wrapped (oldest data was thrown) Relevant only when 3325 wrapped (oldest data was thrown) Relevant only when
3304 ~dbg_registers_debug_target=0 (internal buffer) */ 3326 ~dbg_registers_debug_target=0 (internal buffer) */
3305#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 3327#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
@@ -4944,6 +4966,7 @@
4944#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 4966#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4945#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 4967#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4946#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 4968#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
4969#define EMAC_TX_MODE_FLOW_EN (1L<<4)
4947#define MISC_REGISTERS_GPIO_0 0 4970#define MISC_REGISTERS_GPIO_0 0
4948#define MISC_REGISTERS_GPIO_1 1 4971#define MISC_REGISTERS_GPIO_1 1
4949#define MISC_REGISTERS_GPIO_2 2 4972#define MISC_REGISTERS_GPIO_2 2
@@ -4959,6 +4982,7 @@
4959#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 4982#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
4960#define MISC_REGISTERS_GPIO_SET_POS 8 4983#define MISC_REGISTERS_GPIO_SET_POS 8
4961#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 4984#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
4985#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
4962#define MISC_REGISTERS_RESET_REG_1_SET 0x584 4986#define MISC_REGISTERS_RESET_REG_1_SET 0x584
4963#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 4987#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
4964#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 4988#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
@@ -4993,7 +5017,9 @@
4993#define HW_LOCK_MAX_RESOURCE_VALUE 31 5017#define HW_LOCK_MAX_RESOURCE_VALUE 31
4994#define HW_LOCK_RESOURCE_8072_MDIO 0 5018#define HW_LOCK_RESOURCE_8072_MDIO 0
4995#define HW_LOCK_RESOURCE_GPIO 1 5019#define HW_LOCK_RESOURCE_GPIO 1
5020#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
4996#define HW_LOCK_RESOURCE_SPIO 2 5021#define HW_LOCK_RESOURCE_SPIO 2
5022#define HW_LOCK_RESOURCE_UNDI 5
4997#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) 5023#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
4998#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) 5024#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
4999#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) 5025#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
@@ -5144,59 +5170,73 @@
5144#define GRCBASE_MISC_AEU GRCBASE_MISC 5170#define GRCBASE_MISC_AEU GRCBASE_MISC
5145 5171
5146 5172
5147/*the offset of the configuration space in the pci core register*/ 5173/* offset of configuration space in the pci core register */
5148#define PCICFG_OFFSET 0x2000 5174#define PCICFG_OFFSET 0x2000
5149#define PCICFG_VENDOR_ID_OFFSET 0x00 5175#define PCICFG_VENDOR_ID_OFFSET 0x00
5150#define PCICFG_DEVICE_ID_OFFSET 0x02 5176#define PCICFG_DEVICE_ID_OFFSET 0x02
5151#define PCICFG_COMMAND_OFFSET 0x04 5177#define PCICFG_COMMAND_OFFSET 0x04
5178#define PCICFG_COMMAND_IO_SPACE (1<<0)
5179#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5180#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5181#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5182#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5183#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5184#define PCICFG_COMMAND_PERR_ENA (1<<6)
5185#define PCICFG_COMMAND_STEPPING (1<<7)
5186#define PCICFG_COMMAND_SERR_ENA (1<<8)
5187#define PCICFG_COMMAND_FAST_B2B (1<<9)
5188#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5189#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5152#define PCICFG_STATUS_OFFSET 0x06 5190#define PCICFG_STATUS_OFFSET 0x06
5153#define PCICFG_REVESION_ID 0x08 5191#define PCICFG_REVESION_ID 0x08
5154#define PCICFG_CACHE_LINE_SIZE 0x0c 5192#define PCICFG_CACHE_LINE_SIZE 0x0c
5155#define PCICFG_LATENCY_TIMER 0x0d 5193#define PCICFG_LATENCY_TIMER 0x0d
5156#define PCICFG_BAR_1_LOW 0x10 5194#define PCICFG_BAR_1_LOW 0x10
5157#define PCICFG_BAR_1_HIGH 0x14 5195#define PCICFG_BAR_1_HIGH 0x14
5158#define PCICFG_BAR_2_LOW 0x18 5196#define PCICFG_BAR_2_LOW 0x18
5159#define PCICFG_BAR_2_HIGH 0x1c 5197#define PCICFG_BAR_2_HIGH 0x1c
5160#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5198#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5161#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5199#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5162#define PCICFG_INT_LINE 0x3c 5200#define PCICFG_INT_LINE 0x3c
5163#define PCICFG_INT_PIN 0x3d 5201#define PCICFG_INT_PIN 0x3d
5164#define PCICFG_PM_CSR_OFFSET 0x4c 5202#define PCICFG_PM_CAPABILITY 0x48
5165#define PCICFG_GRC_ADDRESS 0x78 5203#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5166#define PCICFG_GRC_DATA 0x80 5204#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5205#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5206#define PCICFG_PM_CAPABILITY_DSI (1<<21)
5207#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5208#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5209#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5210#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5211#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5212#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5213#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5214#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5215#define PCICFG_PM_CSR_OFFSET 0x4c
5216#define PCICFG_PM_CSR_STATE (0x3<<0)
5217#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5218#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5219#define PCICFG_GRC_ADDRESS 0x78
5220#define PCICFG_GRC_DATA 0x80
5167#define PCICFG_DEVICE_CONTROL 0xb4 5221#define PCICFG_DEVICE_CONTROL 0xb4
5168#define PCICFG_LINK_CONTROL 0xbc 5222#define PCICFG_LINK_CONTROL 0xbc
5169 5223
5170#define PCICFG_COMMAND_IO_SPACE (1<<0)
5171#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5172#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5173#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5174#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5175#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5176#define PCICFG_COMMAND_PERR_ENA (1<<6)
5177#define PCICFG_COMMAND_STEPPING (1<<7)
5178#define PCICFG_COMMAND_SERR_ENA (1<<8)
5179#define PCICFG_COMMAND_FAST_B2B (1<<9)
5180#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5181#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5182
5183#define PCICFG_PM_CSR_STATE (0x3<<0)
5184#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5185 5224
5186#define BAR_USTRORM_INTMEM 0x400000 5225#define BAR_USTRORM_INTMEM 0x400000
5187#define BAR_CSTRORM_INTMEM 0x410000 5226#define BAR_CSTRORM_INTMEM 0x410000
5188#define BAR_XSTRORM_INTMEM 0x420000 5227#define BAR_XSTRORM_INTMEM 0x420000
5189#define BAR_TSTRORM_INTMEM 0x430000 5228#define BAR_TSTRORM_INTMEM 0x430000
5190 5229
5230/* for accessing the IGU in case of status block ACK */
5191#define BAR_IGU_INTMEM 0x440000 5231#define BAR_IGU_INTMEM 0x440000
5192 5232
5193#define BAR_DOORBELL_OFFSET 0x800000 5233#define BAR_DOORBELL_OFFSET 0x800000
5194 5234
5195#define BAR_ME_REGISTER 0x450000 5235#define BAR_ME_REGISTER 0x450000
5196 5236
5197 5237/* config_2 offset */
5198#define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */ 5238#define GRC_CONFIG_2_SIZE_REG 0x408
5199#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 5239#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5200#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 5240#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5201#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 5241#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5202#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 5242#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
@@ -5213,11 +5253,11 @@
5213#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 5253#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5214#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 5254#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5215#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 5255#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5216#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 5256#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5217#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 5257#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5218#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 5258#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5219#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 5259#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5220#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 5260#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5221#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 5261#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5222#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 5262#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5223#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 5263#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
@@ -5234,46 +5274,44 @@
5234#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 5274#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5235#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 5275#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5236#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 5276#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5237#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 5277#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5238#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 5278#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5239 5279
5240/* config_3 offset */ 5280/* config_3 offset */
5241#define GRC_CONFIG_3_SIZE_REG (0x40c) 5281#define GRC_CONFIG_3_SIZE_REG 0x40c
5242#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 5282#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5243#define PCI_CONFIG_3_FORCE_PME (1L<<24) 5283#define PCI_CONFIG_3_FORCE_PME (1L<<24)
5244#define PCI_CONFIG_3_PME_STATUS (1L<<25) 5284#define PCI_CONFIG_3_PME_STATUS (1L<<25)
5245#define PCI_CONFIG_3_PME_ENABLE (1L<<26) 5285#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5246#define PCI_CONFIG_3_PM_STATE (0x3L<<27) 5286#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5247#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 5287#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5248#define PCI_CONFIG_3_PCI_POWER (1L<<31) 5288#define PCI_CONFIG_3_PCI_POWER (1L<<31)
5249
5250/* config_2 offset */
5251#define GRC_CONFIG_2_SIZE_REG 0x408
5252 5289
5253#define GRC_BAR2_CONFIG 0x4e0 5290#define GRC_BAR2_CONFIG 0x4e0
5254#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 5291#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5255#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 5292#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5256#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 5293#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5257#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 5294#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5258#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 5295#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5259#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 5296#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5260#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 5297#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5261#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 5298#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5262#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 5299#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5263#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 5300#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5264#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 5301#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5265#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 5302#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5266#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 5303#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5267#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 5304#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5268#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 5305#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5269#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 5306#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5270#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 5307#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5271#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 5308#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5309
5310#define PCI_PM_DATA_A 0x410
5311#define PCI_PM_DATA_B 0x414
5312#define PCI_ID_VAL1 0x434
5313#define PCI_ID_VAL2 0x438
5272 5314
5273#define PCI_PM_DATA_A (0x410)
5274#define PCI_PM_DATA_B (0x414)
5275#define PCI_ID_VAL1 (0x434)
5276#define PCI_ID_VAL2 (0x438)
5277 5315
5278#define MDIO_REG_BANK_CL73_IEEEB0 0x0 5316#define MDIO_REG_BANK_CL73_IEEEB0 0x0
5279#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 5317#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
@@ -5522,6 +5560,8 @@ Theotherbitsarereservedandshouldbezero*/
5522#define MDIO_PMA_REG_GEN_CTRL 0xca10 5560#define MDIO_PMA_REG_GEN_CTRL 0xca10
5523#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 5561#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5524#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 5562#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5563#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5564#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
5525#define MDIO_PMA_REG_ROM_VER1 0xca19 5565#define MDIO_PMA_REG_ROM_VER1 0xca19
5526#define MDIO_PMA_REG_ROM_VER2 0xca1a 5566#define MDIO_PMA_REG_ROM_VER2 0xca1a
5527#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 5567#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
@@ -5576,7 +5616,8 @@ Theotherbitsarereservedandshouldbezero*/
5576#define MDIO_AN_REG_LINK_STATUS 0x8304 5616#define MDIO_AN_REG_LINK_STATUS 0x8304
5577#define MDIO_AN_REG_CL37_CL73 0x8370 5617#define MDIO_AN_REG_CL37_CL73 0x8370
5578#define MDIO_AN_REG_CL37_AN 0xffe0 5618#define MDIO_AN_REG_CL37_AN 0xffe0
5579#define MDIO_AN_REG_CL37_FD 0xffe4 5619#define MDIO_AN_REG_CL37_FC_LD 0xffe4
5620#define MDIO_AN_REG_CL37_FC_LP 0xffe5
5580 5621
5581 5622
5582#define IGU_FUNC_BASE 0x0400 5623#define IGU_FUNC_BASE 0x0400
@@ -5600,4 +5641,13 @@ Theotherbitsarereservedandshouldbezero*/
5600#define IGU_INT_NOP 2 5641#define IGU_INT_NOP 2
5601#define IGU_INT_NOP2 3 5642#define IGU_INT_NOP2 3
5602 5643
5644#define COMMAND_REG_INT_ACK 0x0
5645#define COMMAND_REG_PROD_UPD 0x4
5646#define COMMAND_REG_ATTN_BITS_UPD 0x8
5647#define COMMAND_REG_ATTN_BITS_SET 0xc
5648#define COMMAND_REG_ATTN_BITS_CLR 0x10
5649#define COMMAND_REG_COALESCE_NOW 0x14
5650#define COMMAND_REG_SIMD_MASK 0x18
5651#define COMMAND_REG_SIMD_NOMASK 0x1c
5652
5603 5653
diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
index a7800e559090..ec6b0af3d46b 100644
--- a/drivers/net/cpmac.c
+++ b/drivers/net/cpmac.c
@@ -26,7 +26,6 @@
26#include <linux/errno.h> 26#include <linux/errno.h>
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/version.h>
30 29
31#include <linux/netdevice.h> 30#include <linux/netdevice.h>
32#include <linux/etherdevice.h> 31#include <linux/etherdevice.h>
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h
index f823b8ba5785..14b0e6cd3b8d 100644
--- a/drivers/net/e1000e/defines.h
+++ b/drivers/net/e1000e/defines.h
@@ -389,7 +389,7 @@
389 389
390/* Interrupt Cause Set */ 390/* Interrupt Cause Set */
391#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 391#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
392#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 392#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
393#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 393#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
394 394
395/* Transmit Descriptor Control */ 395/* Transmit Descriptor Control */
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index cf57050d99d8..ac4e506b4f88 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -326,6 +326,7 @@ struct e1000_info {
326#define FLAG_RX_CSUM_ENABLED (1 << 28) 326#define FLAG_RX_CSUM_ENABLED (1 << 28)
327#define FLAG_TSO_FORCE (1 << 29) 327#define FLAG_TSO_FORCE (1 << 29)
328#define FLAG_RX_RESTART_NOW (1 << 30) 328#define FLAG_RX_RESTART_NOW (1 << 30)
329#define FLAG_MSI_TEST_FAILED (1 << 31)
329 330
330#define E1000_RX_DESC_PS(R, i) \ 331#define E1000_RX_DESC_PS(R, i) \
331 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 332 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c
index cf9679f2b7c4..e21c9e0f3738 100644
--- a/drivers/net/e1000e/ethtool.c
+++ b/drivers/net/e1000e/ethtool.c
@@ -177,7 +177,7 @@ static u32 e1000_get_link(struct net_device *netdev)
177 u32 status; 177 u32 status;
178 178
179 status = er32(STATUS); 179 status = er32(STATUS);
180 return (status & E1000_STATUS_LU); 180 return (status & E1000_STATUS_LU) ? 1 : 0;
181} 181}
182 182
183static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx) 183static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 05b0b2f9c54b..d266510c8a94 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -510,9 +510,12 @@ static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
510 netdev_alloc_skb(netdev, length + NET_IP_ALIGN); 510 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
511 if (new_skb) { 511 if (new_skb) {
512 skb_reserve(new_skb, NET_IP_ALIGN); 512 skb_reserve(new_skb, NET_IP_ALIGN);
513 memcpy(new_skb->data - NET_IP_ALIGN, 513 skb_copy_to_linear_data_offset(new_skb,
514 skb->data - NET_IP_ALIGN, 514 -NET_IP_ALIGN,
515 length + NET_IP_ALIGN); 515 (skb->data -
516 NET_IP_ALIGN),
517 (length +
518 NET_IP_ALIGN));
516 /* save the skb in buffer_info as good */ 519 /* save the skb in buffer_info as good */
517 buffer_info->skb = skb; 520 buffer_info->skb = skb;
518 skb = new_skb; 521 skb = new_skb;
@@ -1233,26 +1236,36 @@ static irqreturn_t e1000_intr(int irq, void *data)
1233 return IRQ_HANDLED; 1236 return IRQ_HANDLED;
1234} 1237}
1235 1238
1239/**
1240 * e1000_request_irq - initialize interrupts
1241 *
1242 * Attempts to configure interrupts using the best available
1243 * capabilities of the hardware and kernel.
1244 **/
1236static int e1000_request_irq(struct e1000_adapter *adapter) 1245static int e1000_request_irq(struct e1000_adapter *adapter)
1237{ 1246{
1238 struct net_device *netdev = adapter->netdev; 1247 struct net_device *netdev = adapter->netdev;
1239 irq_handler_t handler = e1000_intr;
1240 int irq_flags = IRQF_SHARED; 1248 int irq_flags = IRQF_SHARED;
1241 int err; 1249 int err;
1242 1250
1243 if (!pci_enable_msi(adapter->pdev)) { 1251 if (!(adapter->flags & FLAG_MSI_TEST_FAILED)) {
1244 adapter->flags |= FLAG_MSI_ENABLED; 1252 err = pci_enable_msi(adapter->pdev);
1245 handler = e1000_intr_msi; 1253 if (!err) {
1246 irq_flags = 0; 1254 adapter->flags |= FLAG_MSI_ENABLED;
1255 irq_flags = 0;
1256 }
1247 } 1257 }
1248 1258
1249 err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, 1259 err = request_irq(adapter->pdev->irq,
1250 netdev); 1260 ((adapter->flags & FLAG_MSI_ENABLED) ?
1261 &e1000_intr_msi : &e1000_intr),
1262 irq_flags, netdev->name, netdev);
1251 if (err) { 1263 if (err) {
1252 e_err("Unable to allocate %s interrupt (return: %d)\n", 1264 if (adapter->flags & FLAG_MSI_ENABLED) {
1253 adapter->flags & FLAG_MSI_ENABLED ? "MSI":"INTx", err);
1254 if (adapter->flags & FLAG_MSI_ENABLED)
1255 pci_disable_msi(adapter->pdev); 1265 pci_disable_msi(adapter->pdev);
1266 adapter->flags &= ~FLAG_MSI_ENABLED;
1267 }
1268 e_err("Unable to allocate interrupt, Error: %d\n", err);
1256 } 1269 }
1257 1270
1258 return err; 1271 return err;
@@ -2592,6 +2605,135 @@ err:
2592} 2605}
2593 2606
2594/** 2607/**
2608 * e1000_intr_msi_test - Interrupt Handler
2609 * @irq: interrupt number
2610 * @data: pointer to a network interface device structure
2611 **/
2612static irqreturn_t e1000_intr_msi_test(int irq, void *data)
2613{
2614 struct net_device *netdev = data;
2615 struct e1000_adapter *adapter = netdev_priv(netdev);
2616 struct e1000_hw *hw = &adapter->hw;
2617 u32 icr = er32(ICR);
2618
2619 e_dbg("%s: icr is %08X\n", netdev->name, icr);
2620 if (icr & E1000_ICR_RXSEQ) {
2621 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
2622 wmb();
2623 }
2624
2625 return IRQ_HANDLED;
2626}
2627
2628/**
2629 * e1000_test_msi_interrupt - Returns 0 for successful test
2630 * @adapter: board private struct
2631 *
2632 * code flow taken from tg3.c
2633 **/
2634static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
2635{
2636 struct net_device *netdev = adapter->netdev;
2637 struct e1000_hw *hw = &adapter->hw;
2638 int err;
2639
2640 /* poll_enable hasn't been called yet, so don't need disable */
2641 /* clear any pending events */
2642 er32(ICR);
2643
2644 /* free the real vector and request a test handler */
2645 e1000_free_irq(adapter);
2646
2647 /* Assume that the test fails, if it succeeds then the test
2648 * MSI irq handler will unset this flag */
2649 adapter->flags |= FLAG_MSI_TEST_FAILED;
2650
2651 err = pci_enable_msi(adapter->pdev);
2652 if (err)
2653 goto msi_test_failed;
2654
2655 err = request_irq(adapter->pdev->irq, &e1000_intr_msi_test, 0,
2656 netdev->name, netdev);
2657 if (err) {
2658 pci_disable_msi(adapter->pdev);
2659 goto msi_test_failed;
2660 }
2661
2662 wmb();
2663
2664 e1000_irq_enable(adapter);
2665
2666 /* fire an unusual interrupt on the test handler */
2667 ew32(ICS, E1000_ICS_RXSEQ);
2668 e1e_flush();
2669 msleep(50);
2670
2671 e1000_irq_disable(adapter);
2672
2673 rmb();
2674
2675 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
2676 err = -EIO;
2677 e_info("MSI interrupt test failed!\n");
2678 }
2679
2680 free_irq(adapter->pdev->irq, netdev);
2681 pci_disable_msi(adapter->pdev);
2682
2683 if (err == -EIO)
2684 goto msi_test_failed;
2685
2686 /* okay so the test worked, restore settings */
2687 e_dbg("%s: MSI interrupt test succeeded!\n", netdev->name);
2688msi_test_failed:
2689 /* restore the original vector, even if it failed */
2690 e1000_request_irq(adapter);
2691 return err;
2692}
2693
2694/**
2695 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
2696 * @adapter: board private struct
2697 *
2698 * code flow taken from tg3.c, called with e1000 interrupts disabled.
2699 **/
2700static int e1000_test_msi(struct e1000_adapter *adapter)
2701{
2702 int err;
2703 u16 pci_cmd;
2704
2705 if (!(adapter->flags & FLAG_MSI_ENABLED))
2706 return 0;
2707
2708 /* disable SERR in case the MSI write causes a master abort */
2709 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
2710 pci_write_config_word(adapter->pdev, PCI_COMMAND,
2711 pci_cmd & ~PCI_COMMAND_SERR);
2712
2713 err = e1000_test_msi_interrupt(adapter);
2714
2715 /* restore previous setting of command word */
2716 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
2717
2718 /* success ! */
2719 if (!err)
2720 return 0;
2721
2722 /* EIO means MSI test failed */
2723 if (err != -EIO)
2724 return err;
2725
2726 /* back to INTx mode */
2727 e_warn("MSI interrupt test failed, using legacy interrupt.\n");
2728
2729 e1000_free_irq(adapter);
2730
2731 err = e1000_request_irq(adapter);
2732
2733 return err;
2734}
2735
2736/**
2595 * e1000_open - Called when a network interface is made active 2737 * e1000_open - Called when a network interface is made active
2596 * @netdev: network interface device structure 2738 * @netdev: network interface device structure
2597 * 2739 *
@@ -2649,6 +2791,19 @@ static int e1000_open(struct net_device *netdev)
2649 if (err) 2791 if (err)
2650 goto err_req_irq; 2792 goto err_req_irq;
2651 2793
2794 /*
2795 * Work around PCIe errata with MSI interrupts causing some chipsets to
2796 * ignore e1000e MSI messages, which means we need to test our MSI
2797 * interrupt now
2798 */
2799 {
2800 err = e1000_test_msi(adapter);
2801 if (err) {
2802 e_err("Interrupt allocation failed\n");
2803 goto err_req_irq;
2804 }
2805 }
2806
2652 /* From here on the code is the same as e1000e_up() */ 2807 /* From here on the code is the same as e1000e_up() */
2653 clear_bit(__E1000_DOWN, &adapter->state); 2808 clear_bit(__E1000_DOWN, &adapter->state);
2654 2809
@@ -3055,7 +3210,7 @@ static void e1000_watchdog_task(struct work_struct *work)
3055 case SPEED_10: 3210 case SPEED_10:
3056 txb2b = 0; 3211 txb2b = 0;
3057 netdev->tx_queue_len = 10; 3212 netdev->tx_queue_len = 10;
3058 adapter->tx_timeout_factor = 14; 3213 adapter->tx_timeout_factor = 16;
3059 break; 3214 break;
3060 case SPEED_100: 3215 case SPEED_100:
3061 txb2b = 0; 3216 txb2b = 0;
@@ -3721,7 +3876,7 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
3721 struct e1000_adapter *adapter = netdev_priv(netdev); 3876 struct e1000_adapter *adapter = netdev_priv(netdev);
3722 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 3877 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3723 3878
3724 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || 3879 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
3725 (max_frame > MAX_JUMBO_FRAME_SIZE)) { 3880 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3726 e_err("Invalid MTU setting\n"); 3881 e_err("Invalid MTU setting\n");
3727 return -EINVAL; 3882 return -EINVAL;
diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c
index 8effc3107f9a..ed912e023a72 100644
--- a/drivers/net/e1000e/param.c
+++ b/drivers/net/e1000e/param.c
@@ -324,14 +324,27 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
324 adapter->itr = 20000; 324 adapter->itr = 20000;
325 break; 325 break;
326 default: 326 default:
327 e1000_validate_option(&adapter->itr, &opt,
328 adapter);
329 /* 327 /*
330 * save the setting, because the dynamic bits 328 * Save the setting, because the dynamic bits
331 * change itr. clear the lower two bits 329 * change itr.
332 * because they are used as control
333 */ 330 */
334 adapter->itr_setting = adapter->itr & ~3; 331 if (e1000_validate_option(&adapter->itr, &opt,
332 adapter) &&
333 (adapter->itr == 3)) {
334 /*
335 * In case of invalid user value,
336 * default to conservative mode.
337 */
338 adapter->itr_setting = adapter->itr;
339 adapter->itr = 20000;
340 } else {
341 /*
342 * Clear the lower two bits because
343 * they are used as control.
344 */
345 adapter->itr_setting =
346 adapter->itr & ~3;
347 }
335 break; 348 break;
336 } 349 }
337 } else { 350 } else {
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index ca6cf6ecb37b..999d69168277 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -134,9 +134,7 @@ static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int l
134static void gfar_vlan_rx_register(struct net_device *netdev, 134static void gfar_vlan_rx_register(struct net_device *netdev,
135 struct vlan_group *grp); 135 struct vlan_group *grp);
136void gfar_halt(struct net_device *dev); 136void gfar_halt(struct net_device *dev);
137#ifdef CONFIG_PM
138static void gfar_halt_nodisable(struct net_device *dev); 137static void gfar_halt_nodisable(struct net_device *dev);
139#endif
140void gfar_start(struct net_device *dev); 138void gfar_start(struct net_device *dev);
141static void gfar_clear_exact_match(struct net_device *dev); 139static void gfar_clear_exact_match(struct net_device *dev);
142static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); 140static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
@@ -631,7 +629,6 @@ static void init_registers(struct net_device *dev)
631} 629}
632 630
633 631
634#ifdef CONFIG_PM
635/* Halt the receive and transmit queues */ 632/* Halt the receive and transmit queues */
636static void gfar_halt_nodisable(struct net_device *dev) 633static void gfar_halt_nodisable(struct net_device *dev)
637{ 634{
@@ -657,7 +654,6 @@ static void gfar_halt_nodisable(struct net_device *dev)
657 cpu_relax(); 654 cpu_relax();
658 } 655 }
659} 656}
660#endif
661 657
662/* Halt the receive and transmit queues */ 658/* Halt the receive and transmit queues */
663void gfar_halt(struct net_device *dev) 659void gfar_halt(struct net_device *dev)
@@ -666,6 +662,8 @@ void gfar_halt(struct net_device *dev)
666 struct gfar __iomem *regs = priv->regs; 662 struct gfar __iomem *regs = priv->regs;
667 u32 tempval; 663 u32 tempval;
668 664
665 gfar_halt_nodisable(dev);
666
669 /* Disable Rx and Tx */ 667 /* Disable Rx and Tx */
670 tempval = gfar_read(&regs->maccfg1); 668 tempval = gfar_read(&regs->maccfg1);
671 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 669 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
diff --git a/drivers/net/gianfar_sysfs.c b/drivers/net/gianfar_sysfs.c
index 5116f68e01b9..782c20170082 100644
--- a/drivers/net/gianfar_sysfs.c
+++ b/drivers/net/gianfar_sysfs.c
@@ -33,7 +33,6 @@
33 33
34#include <asm/uaccess.h> 34#include <asm/uaccess.h>
35#include <linux/module.h> 35#include <linux/module.h>
36#include <linux/version.h>
37 36
38#include "gianfar.h" 37#include "gianfar.h"
39 38
diff --git a/drivers/net/ipg.h b/drivers/net/ipg.h
index e0e718ab4c2e..dd9318f19497 100644
--- a/drivers/net/ipg.h
+++ b/drivers/net/ipg.h
@@ -7,7 +7,6 @@
7#ifndef __LINUX_IPG_H 7#ifndef __LINUX_IPG_H
8#define __LINUX_IPG_H 8#define __LINUX_IPG_H
9 9
10#include <linux/version.h>
11#include <linux/module.h> 10#include <linux/module.h>
12 11
13#include <linux/kernel.h> 12#include <linux/kernel.h>
@@ -21,7 +20,6 @@
21#include <linux/etherdevice.h> 20#include <linux/etherdevice.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/skbuff.h> 22#include <linux/skbuff.h>
24#include <linux/version.h>
25#include <asm/bitops.h> 23#include <asm/bitops.h>
26 24
27/* 25/*
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 2f38e847e2cd..f96358b641af 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -190,6 +190,7 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
190 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 190 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
191 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 191 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
192 case IXGBE_DEV_ID_82598EB_CX4: 192 case IXGBE_DEV_ID_82598EB_CX4:
193 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
193 media_type = ixgbe_media_type_fiber; 194 media_type = ixgbe_media_type_fiber;
194 break; 195 break;
195 case IXGBE_DEV_ID_82598AT_DUAL_PORT: 196 case IXGBE_DEV_ID_82598AT_DUAL_PORT:
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index e5f3da8468cc..34bca16d48a6 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -48,7 +48,7 @@ char ixgbe_driver_name[] = "ixgbe";
48static const char ixgbe_driver_string[] = 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver"; 49 "Intel(R) 10 Gigabit PCI Express Network Driver";
50 50
51#define DRV_VERSION "1.3.18-k2" 51#define DRV_VERSION "1.3.18-k4"
52const char ixgbe_driver_version[] = DRV_VERSION; 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] = 53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation."; 54 "Copyright (c) 1999-2007 Intel Corporation.";
@@ -72,6 +72,8 @@ static struct pci_device_id ixgbe_pci_tbl[] = {
72 board_82598 }, 72 board_82598 },
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
74 board_82598 }, 74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
75 77
76 /* required last entry */ 78 /* required last entry */
77 {0, } 79 {0, }
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 1ad7cb9c25a8..c0282a223df3 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -39,6 +39,7 @@
39#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 39#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
40#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8 40#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8
41#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 41#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
42#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
42 43
43/* General Registers */ 44/* General Registers */
44#define IXGBE_CTRL 0x00000 45#define IXGBE_CTRL 0x00000
diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c
index 49f6bc036a92..3b43bfd85a0f 100644
--- a/drivers/net/loopback.c
+++ b/drivers/net/loopback.c
@@ -64,68 +64,6 @@ struct pcpu_lstats {
64 unsigned long bytes; 64 unsigned long bytes;
65}; 65};
66 66
67/* KISS: just allocate small chunks and copy bits.
68 *
69 * So, in fact, this is documentation, explaining what we expect
70 * of largesending device modulo TCP checksum, which is ignored for loopback.
71 */
72
73#ifdef LOOPBACK_TSO
74static void emulate_large_send_offload(struct sk_buff *skb)
75{
76 struct iphdr *iph = ip_hdr(skb);
77 struct tcphdr *th = (struct tcphdr *)(skb_network_header(skb) +
78 (iph->ihl * 4));
79 unsigned int doffset = (iph->ihl + th->doff) * 4;
80 unsigned int mtu = skb_shinfo(skb)->gso_size + doffset;
81 unsigned int offset = 0;
82 u32 seq = ntohl(th->seq);
83 u16 id = ntohs(iph->id);
84
85 while (offset + doffset < skb->len) {
86 unsigned int frag_size = min(mtu, skb->len - offset) - doffset;
87 struct sk_buff *nskb = alloc_skb(mtu + 32, GFP_ATOMIC);
88
89 if (!nskb)
90 break;
91 skb_reserve(nskb, 32);
92 skb_set_mac_header(nskb, -ETH_HLEN);
93 skb_reset_network_header(nskb);
94 iph = ip_hdr(nskb);
95 skb_copy_to_linear_data(nskb, skb_network_header(skb),
96 doffset);
97 if (skb_copy_bits(skb,
98 doffset + offset,
99 nskb->data + doffset,
100 frag_size))
101 BUG();
102 skb_put(nskb, doffset + frag_size);
103 nskb->ip_summed = CHECKSUM_UNNECESSARY;
104 nskb->dev = skb->dev;
105 nskb->priority = skb->priority;
106 nskb->protocol = skb->protocol;
107 nskb->dst = dst_clone(skb->dst);
108 memcpy(nskb->cb, skb->cb, sizeof(skb->cb));
109 nskb->pkt_type = skb->pkt_type;
110
111 th = (struct tcphdr *)(skb_network_header(nskb) + iph->ihl * 4);
112 iph->tot_len = htons(frag_size + doffset);
113 iph->id = htons(id);
114 iph->check = 0;
115 iph->check = ip_fast_csum((unsigned char *) iph, iph->ihl);
116 th->seq = htonl(seq);
117 if (offset + doffset + frag_size < skb->len)
118 th->fin = th->psh = 0;
119 netif_rx(nskb);
120 offset += frag_size;
121 seq += frag_size;
122 id++;
123 }
124
125 dev_kfree_skb(skb);
126}
127#endif /* LOOPBACK_TSO */
128
129/* 67/*
130 * The higher levels take care of making this non-reentrant (it's 68 * The higher levels take care of making this non-reentrant (it's
131 * called with bh's disabled). 69 * called with bh's disabled).
@@ -137,9 +75,6 @@ static int loopback_xmit(struct sk_buff *skb, struct net_device *dev)
137 skb_orphan(skb); 75 skb_orphan(skb);
138 76
139 skb->protocol = eth_type_trans(skb,dev); 77 skb->protocol = eth_type_trans(skb,dev);
140#ifndef LOOPBACK_MUST_CHECKSUM
141 skb->ip_summed = CHECKSUM_UNNECESSARY;
142#endif
143 78
144#ifdef LOOPBACK_TSO 79#ifdef LOOPBACK_TSO
145 if (skb_is_gso(skb)) { 80 if (skb_is_gso(skb)) {
@@ -234,9 +169,7 @@ static void loopback_setup(struct net_device *dev)
234 dev->type = ARPHRD_LOOPBACK; /* 0x0001*/ 169 dev->type = ARPHRD_LOOPBACK; /* 0x0001*/
235 dev->flags = IFF_LOOPBACK; 170 dev->flags = IFF_LOOPBACK;
236 dev->features = NETIF_F_SG | NETIF_F_FRAGLIST 171 dev->features = NETIF_F_SG | NETIF_F_FRAGLIST
237#ifdef LOOPBACK_TSO
238 | NETIF_F_TSO 172 | NETIF_F_TSO
239#endif
240 | NETIF_F_NO_CSUM 173 | NETIF_F_NO_CSUM
241 | NETIF_F_HIGHDMA 174 | NETIF_F_HIGHDMA
242 | NETIF_F_LLTX 175 | NETIF_F_LLTX
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index f1de38f8b742..54cd89cb0838 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -56,7 +56,6 @@
56#include <linux/ethtool.h> 56#include <linux/ethtool.h>
57#include <linux/firmware.h> 57#include <linux/firmware.h>
58#include <linux/delay.h> 58#include <linux/delay.h>
59#include <linux/version.h>
60#include <linux/timer.h> 59#include <linux/timer.h>
61#include <linux/vmalloc.h> 60#include <linux/vmalloc.h>
62#include <linux/crc32.h> 61#include <linux/crc32.h>
@@ -3548,7 +3547,11 @@ static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3548 3547
3549 /* try to load the slice aware rss firmware */ 3548 /* try to load the slice aware rss firmware */
3550 old_fw = mgp->fw_name; 3549 old_fw = mgp->fw_name;
3551 if (old_fw == myri10ge_fw_aligned) 3550 if (myri10ge_fw_name != NULL) {
3551 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3552 myri10ge_fw_name);
3553 mgp->fw_name = myri10ge_fw_name;
3554 } else if (old_fw == myri10ge_fw_aligned)
3552 mgp->fw_name = myri10ge_fw_rss_aligned; 3555 mgp->fw_name = myri10ge_fw_rss_aligned;
3553 else 3556 else
3554 mgp->fw_name = myri10ge_fw_rss_unaligned; 3557 mgp->fw_name = myri10ge_fw_rss_unaligned;
diff --git a/drivers/net/ne.c b/drivers/net/ne.c
index 42443d697423..fa3ceca4e15c 100644
--- a/drivers/net/ne.c
+++ b/drivers/net/ne.c
@@ -118,7 +118,7 @@ bad_clone_list[] __initdata = {
118 {"E-LAN100", "E-LAN200", {0x00, 0x00, 0x5d}}, /* Broken ne1000 clones */ 118 {"E-LAN100", "E-LAN200", {0x00, 0x00, 0x5d}}, /* Broken ne1000 clones */
119 {"PCM-4823", "PCM-4823", {0x00, 0xc0, 0x6c}}, /* Broken Advantech MoBo */ 119 {"PCM-4823", "PCM-4823", {0x00, 0xc0, 0x6c}}, /* Broken Advantech MoBo */
120 {"REALTEK", "RTL8019", {0x00, 0x00, 0xe8}}, /* no-name with Realtek chip */ 120 {"REALTEK", "RTL8019", {0x00, 0x00, 0xe8}}, /* no-name with Realtek chip */
121#if defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) 121#ifdef CONFIG_MACH_TX49XX
122 {"RBHMA4X00-RTL8019", "RBHMA4X00/RTL8019", {0x00, 0x60, 0x0a}}, /* Toshiba built-in */ 122 {"RBHMA4X00-RTL8019", "RBHMA4X00/RTL8019", {0x00, 0x60, 0x0a}}, /* Toshiba built-in */
123#endif 123#endif
124 {"LCS-8834", "LCS-8836", {0x04, 0x04, 0x37}}, /* ShinyNet (SET) */ 124 {"LCS-8834", "LCS-8836", {0x04, 0x04, 0x37}}, /* ShinyNet (SET) */
@@ -142,7 +142,7 @@ bad_clone_list[] __initdata = {
142#if defined(CONFIG_PLAT_MAPPI) 142#if defined(CONFIG_PLAT_MAPPI)
143# define DCR_VAL 0x4b 143# define DCR_VAL 0x4b
144#elif defined(CONFIG_PLAT_OAKS32R) || \ 144#elif defined(CONFIG_PLAT_OAKS32R) || \
145 defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) 145 defined(CONFIG_MACH_TX49XX)
146# define DCR_VAL 0x48 /* 8-bit mode */ 146# define DCR_VAL 0x48 /* 8-bit mode */
147#else 147#else
148# define DCR_VAL 0x49 148# define DCR_VAL 0x49
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index 93a7b9b668d5..244ab49c4337 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -45,7 +45,6 @@
45#include <linux/in.h> 45#include <linux/in.h>
46#include <linux/tcp.h> 46#include <linux/tcp.h>
47#include <linux/skbuff.h> 47#include <linux/skbuff.h>
48#include <linux/version.h>
49 48
50#include <linux/ethtool.h> 49#include <linux/ethtool.h>
51#include <linux/mii.h> 50#include <linux/mii.h>
@@ -66,8 +65,8 @@
66 65
67#define _NETXEN_NIC_LINUX_MAJOR 4 66#define _NETXEN_NIC_LINUX_MAJOR 4
68#define _NETXEN_NIC_LINUX_MINOR 0 67#define _NETXEN_NIC_LINUX_MINOR 0
69#define _NETXEN_NIC_LINUX_SUBVERSION 0 68#define _NETXEN_NIC_LINUX_SUBVERSION 11
70#define NETXEN_NIC_LINUX_VERSIONID "4.0.0" 69#define NETXEN_NIC_LINUX_VERSIONID "4.0.11"
71 70
72#define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c)) 71#define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
73 72
@@ -1615,7 +1614,8 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter)
1615 1614
1616 1615
1617int netxen_is_flash_supported(struct netxen_adapter *adapter); 1616int netxen_is_flash_supported(struct netxen_adapter *adapter);
1618int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]); 1617int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1618int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1619extern void netxen_change_ringparam(struct netxen_adapter *adapter); 1619extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1620extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, 1620extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1621 int *valp); 1621 int *valp);
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index 4ad3e0844b99..b974ca0fc530 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -38,7 +38,6 @@
38#include <asm/io.h> 38#include <asm/io.h>
39#include <linux/netdevice.h> 39#include <linux/netdevice.h>
40#include <linux/ethtool.h> 40#include <linux/ethtool.h>
41#include <linux/version.h>
42 41
43#include "netxen_nic.h" 42#include "netxen_nic.h"
44#include "netxen_nic_hw.h" 43#include "netxen_nic_hw.h"
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h
index e8e8d73f6ed7..e80f9e3e5973 100644
--- a/drivers/net/netxen/netxen_nic_hdr.h
+++ b/drivers/net/netxen/netxen_nic_hdr.h
@@ -32,8 +32,6 @@
32 32
33#include <linux/module.h> 33#include <linux/module.h>
34#include <linux/kernel.h> 34#include <linux/kernel.h>
35#include <linux/version.h>
36
37#include <linux/spinlock.h> 35#include <linux/spinlock.h>
38#include <asm/irq.h> 36#include <asm/irq.h>
39#include <linux/init.h> 37#include <linux/init.h>
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 9aa20f961618..84978f80f396 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -733,31 +733,56 @@ static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
733 return 0; 733 return 0;
734} 734}
735 735
736int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]) 736int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
737{ 737{
738 __le32 *pmac = (__le32 *) & mac[0]; 738 __le32 *pmac = (__le32 *) mac;
739 u32 offset;
739 740
740 if (netxen_get_flash_block(adapter, 741 offset = NETXEN_USER_START +
741 NETXEN_USER_START + 742 offsetof(struct netxen_new_user_info, mac_addr) +
742 offsetof(struct netxen_new_user_info, 743 adapter->portnum * sizeof(u64);
743 mac_addr), 744
744 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) { 745 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
745 return -1; 746 return -1;
746 } 747
747 if (*mac == cpu_to_le64(~0ULL)) { 748 if (*mac == cpu_to_le64(~0ULL)) {
749
750 offset = NETXEN_USER_START_OLD +
751 offsetof(struct netxen_user_old_info, mac_addr) +
752 adapter->portnum * sizeof(u64);
753
748 if (netxen_get_flash_block(adapter, 754 if (netxen_get_flash_block(adapter,
749 NETXEN_USER_START_OLD + 755 offset, sizeof(u64), pmac) == -1)
750 offsetof(struct netxen_user_old_info,
751 mac_addr),
752 FLASH_NUM_PORTS * sizeof(u64),
753 pmac) == -1)
754 return -1; 756 return -1;
757
755 if (*mac == cpu_to_le64(~0ULL)) 758 if (*mac == cpu_to_le64(~0ULL))
756 return -1; 759 return -1;
757 } 760 }
758 return 0; 761 return 0;
759} 762}
760 763
764int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
765{
766 uint32_t crbaddr, mac_hi, mac_lo;
767 int pci_func = adapter->ahw.pci_func;
768
769 crbaddr = CRB_MAC_BLOCK_START +
770 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
771
772 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
773 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
774
775 mac_hi = cpu_to_le32(mac_hi);
776 mac_lo = cpu_to_le32(mac_lo);
777
778 if (pci_func & 1)
779 *mac = ((mac_lo >> 16) | ((u64)mac_hi << 16));
780 else
781 *mac = ((mac_lo) | ((u64)mac_hi << 32));
782
783 return 0;
784}
785
761#define CRB_WIN_LOCK_TIMEOUT 100000000 786#define CRB_WIN_LOCK_TIMEOUT 100000000
762 787
763static int crb_win_lock(struct netxen_adapter *adapter) 788static int crb_win_lock(struct netxen_adapter *adapter)
@@ -2183,10 +2208,10 @@ void netxen_nic_flash_print(struct netxen_adapter *adapter)
2183 if (adapter->portnum == 0) { 2208 if (adapter->portnum == 0) {
2184 get_brd_name_by_type(board_info->board_type, brd_name); 2209 get_brd_name_by_type(board_info->board_type, brd_name);
2185 2210
2186 printk("NetXen %s Board S/N %s Chip id 0x%x\n", 2211 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2187 brd_name, serial_num, board_info->chip_id); 2212 brd_name, serial_num, adapter->ahw.revision_id);
2188 printk("NetXen Firmware version %d.%d.%d\n", fw_major, 2213 printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n",
2189 fw_minor, fw_build); 2214 fw_major, fw_minor, fw_build);
2190 } 2215 }
2191 2216
2192 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) < 2217 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index 519fc860e17e..5bba675d0504 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -1079,10 +1079,12 @@ int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
1079 1079
1080void netxen_free_adapter_offload(struct netxen_adapter *adapter) 1080void netxen_free_adapter_offload(struct netxen_adapter *adapter)
1081{ 1081{
1082 int i; 1082 int i = 100;
1083
1084 if (!adapter->dummy_dma.addr)
1085 return;
1083 1086
1084 if (adapter->dummy_dma.addr) { 1087 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1085 i = 100;
1086 do { 1088 do {
1087 if (dma_watchdog_shutdown_request(adapter) == 1) 1089 if (dma_watchdog_shutdown_request(adapter) == 1)
1088 break; 1090 break;
@@ -1090,17 +1092,17 @@ void netxen_free_adapter_offload(struct netxen_adapter *adapter)
1090 if (dma_watchdog_shutdown_poll_result(adapter) == 1) 1092 if (dma_watchdog_shutdown_poll_result(adapter) == 1)
1091 break; 1093 break;
1092 } while (--i); 1094 } while (--i);
1095 }
1093 1096
1094 if (i) { 1097 if (i) {
1095 pci_free_consistent(adapter->pdev, 1098 pci_free_consistent(adapter->pdev,
1096 NETXEN_HOST_DUMMY_DMA_SIZE, 1099 NETXEN_HOST_DUMMY_DMA_SIZE,
1097 adapter->dummy_dma.addr, 1100 adapter->dummy_dma.addr,
1098 adapter->dummy_dma.phys_addr); 1101 adapter->dummy_dma.phys_addr);
1099 adapter->dummy_dma.addr = NULL; 1102 adapter->dummy_dma.addr = NULL;
1100 } else { 1103 } else {
1101 printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n", 1104 printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
1102 adapter->netdev->name); 1105 adapter->netdev->name);
1103 }
1104 } 1106 }
1105} 1107}
1106 1108
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index 7615c715e66e..32bb47adbe39 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -149,76 +149,18 @@ static uint32_t msi_tgt_status[8] = {
149 149
150static struct netxen_legacy_intr_set legacy_intr[] = NX_LEGACY_INTR_CONFIG; 150static struct netxen_legacy_intr_set legacy_intr[] = NX_LEGACY_INTR_CONFIG;
151 151
152static void netxen_nic_disable_int(struct netxen_adapter *adapter) 152static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
153{ 153{
154 u32 mask = 0x7ff; 154 adapter->pci_write_normalize(adapter, adapter->crb_intr_mask, 0);
155 int retries = 32;
156 int pci_fn = adapter->ahw.pci_func;
157
158 if (adapter->msi_mode != MSI_MODE_MULTIFUNC)
159 adapter->pci_write_normalize(adapter,
160 adapter->crb_intr_mask, 0);
161
162 if (adapter->intr_scheme != -1 &&
163 adapter->intr_scheme != INTR_SCHEME_PERPORT)
164 adapter->pci_write_immediate(adapter, ISR_INT_MASK, mask);
165
166 if (!NETXEN_IS_MSI_FAMILY(adapter)) {
167 do {
168 adapter->pci_write_immediate(adapter,
169 adapter->legacy_intr.tgt_status_reg,
170 0xffffffff);
171 mask = adapter->pci_read_immediate(adapter,
172 ISR_INT_VECTOR);
173 if (!(mask & 0x80))
174 break;
175 udelay(10);
176 } while (--retries);
177
178 if (!retries) {
179 printk(KERN_NOTICE "%s: Failed to disable interrupt\n",
180 netxen_nic_driver_name);
181 }
182 } else {
183 if (adapter->msi_mode == MSI_MODE_MULTIFUNC) {
184 adapter->pci_write_immediate(adapter,
185 msi_tgt_status[pci_fn], 0xffffffff);
186 }
187 }
188} 155}
189 156
190static void netxen_nic_enable_int(struct netxen_adapter *adapter) 157static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
191{ 158{
192 u32 mask;
193
194 if (adapter->intr_scheme != -1 &&
195 adapter->intr_scheme != INTR_SCHEME_PERPORT) {
196 switch (adapter->ahw.board_type) {
197 case NETXEN_NIC_GBE:
198 mask = 0x77b;
199 break;
200 case NETXEN_NIC_XGBE:
201 mask = 0x77f;
202 break;
203 default:
204 mask = 0x7ff;
205 break;
206 }
207
208 adapter->pci_write_immediate(adapter, ISR_INT_MASK, mask);
209 }
210
211 adapter->pci_write_normalize(adapter, adapter->crb_intr_mask, 0x1); 159 adapter->pci_write_normalize(adapter, adapter->crb_intr_mask, 0x1);
212 160
213 if (!NETXEN_IS_MSI_FAMILY(adapter)) { 161 if (!NETXEN_IS_MSI_FAMILY(adapter))
214 mask = 0xbff; 162 adapter->pci_write_immediate(adapter,
215 if (adapter->intr_scheme == INTR_SCHEME_PERPORT) 163 adapter->legacy_intr.tgt_mask_reg, 0xfbff);
216 adapter->pci_write_immediate(adapter,
217 adapter->legacy_intr.tgt_mask_reg, mask);
218 else
219 adapter->pci_write_normalize(adapter,
220 CRB_INT_VECTOR, 0);
221 }
222} 164}
223 165
224static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id) 166static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id)
@@ -501,6 +443,44 @@ static void netxen_init_msix_entries(struct netxen_adapter *adapter)
501 adapter->msix_entries[i].entry = i; 443 adapter->msix_entries[i].entry = i;
502} 444}
503 445
446static int
447netxen_read_mac_addr(struct netxen_adapter *adapter)
448{
449 int i;
450 unsigned char *p;
451 __le64 mac_addr;
452 DECLARE_MAC_BUF(mac);
453 struct net_device *netdev = adapter->netdev;
454 struct pci_dev *pdev = adapter->pdev;
455
456 if (netxen_is_flash_supported(adapter) != 0)
457 return -EIO;
458
459 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
460 if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0)
461 return -EIO;
462 } else {
463 if (netxen_get_flash_mac_addr(adapter, &mac_addr) != 0)
464 return -EIO;
465 }
466
467 p = (unsigned char *)&mac_addr;
468 for (i = 0; i < 6; i++)
469 netdev->dev_addr[i] = *(p + 5 - i);
470
471 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
472
473 /* set station address */
474
475 if (!is_valid_ether_addr(netdev->perm_addr)) {
476 dev_warn(&pdev->dev, "Bad MAC address %s.\n",
477 print_mac(mac, netdev->dev_addr));
478 } else
479 adapter->macaddr_set(adapter, netdev->dev_addr);
480
481 return 0;
482}
483
504/* 484/*
505 * netxen_nic_probe() 485 * netxen_nic_probe()
506 * 486 *
@@ -529,10 +509,8 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
529 unsigned long mem_base, mem_len, db_base, db_len, pci_len0 = 0; 509 unsigned long mem_base, mem_len, db_base, db_len, pci_len0 = 0;
530 int i = 0, err; 510 int i = 0, err;
531 int first_driver, first_boot; 511 int first_driver, first_boot;
532 __le64 mac_addr[FLASH_NUM_PORTS + 1];
533 u32 val; 512 u32 val;
534 int pci_func_id = PCI_FUNC(pdev->devfn); 513 int pci_func_id = PCI_FUNC(pdev->devfn);
535 DECLARE_MAC_BUF(mac);
536 struct netxen_legacy_intr_set *legacy_intrp; 514 struct netxen_legacy_intr_set *legacy_intrp;
537 uint8_t revision_id; 515 uint8_t revision_id;
538 516
@@ -545,6 +523,13 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
545 return -ENODEV; 523 return -ENODEV;
546 } 524 }
547 525
526 if (pdev->revision >= NX_P3_A0 && pdev->revision < NX_P3_B1) {
527 printk(KERN_WARNING "NetXen chip revisions between 0x%x-0x%x"
528 "will not be enabled.\n",
529 NX_P3_A0, NX_P3_B1);
530 return -ENODEV;
531 }
532
548 if ((err = pci_enable_device(pdev))) 533 if ((err = pci_enable_device(pdev)))
549 return err; 534 return err;
550 535
@@ -898,34 +883,14 @@ request_msi:
898 goto err_out_disable_msi; 883 goto err_out_disable_msi;
899 884
900 init_timer(&adapter->watchdog_timer); 885 init_timer(&adapter->watchdog_timer);
901 adapter->ahw.linkup = 0;
902 adapter->watchdog_timer.function = &netxen_watchdog; 886 adapter->watchdog_timer.function = &netxen_watchdog;
903 adapter->watchdog_timer.data = (unsigned long)adapter; 887 adapter->watchdog_timer.data = (unsigned long)adapter;
904 INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task); 888 INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task);
905 INIT_WORK(&adapter->tx_timeout_task, netxen_tx_timeout_task); 889 INIT_WORK(&adapter->tx_timeout_task, netxen_tx_timeout_task);
906 890
907 if (netxen_is_flash_supported(adapter) == 0 && 891 err = netxen_read_mac_addr(adapter);
908 netxen_get_flash_mac_addr(adapter, mac_addr) == 0) { 892 if (err)
909 unsigned char *p; 893 dev_warn(&pdev->dev, "failed to read mac addr\n");
910
911 p = (unsigned char *)&mac_addr[adapter->portnum];
912 netdev->dev_addr[0] = *(p + 5);
913 netdev->dev_addr[1] = *(p + 4);
914 netdev->dev_addr[2] = *(p + 3);
915 netdev->dev_addr[3] = *(p + 2);
916 netdev->dev_addr[4] = *(p + 1);
917 netdev->dev_addr[5] = *(p + 0);
918
919 memcpy(netdev->perm_addr, netdev->dev_addr,
920 netdev->addr_len);
921 if (!is_valid_ether_addr(netdev->perm_addr)) {
922 printk(KERN_ERR "%s: Bad MAC address %s.\n",
923 netxen_nic_driver_name,
924 print_mac(mac, netdev->dev_addr));
925 } else {
926 adapter->macaddr_set(adapter, netdev->dev_addr);
927 }
928 }
929 894
930 netif_carrier_off(netdev); 895 netif_carrier_off(netdev);
931 netif_stop_queue(netdev); 896 netif_stop_queue(netdev);
@@ -1000,6 +965,7 @@ static void __devexit netxen_nic_remove(struct pci_dev *pdev)
1000 965
1001 if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) { 966 if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) {
1002 netxen_free_hw_resources(adapter); 967 netxen_free_hw_resources(adapter);
968 netxen_release_rx_buffers(adapter);
1003 netxen_free_sw_resources(adapter); 969 netxen_free_sw_resources(adapter);
1004 } 970 }
1005 971
@@ -1069,6 +1035,15 @@ static int netxen_nic_open(struct net_device *netdev)
1069 goto err_out_free_sw; 1035 goto err_out_free_sw;
1070 } 1036 }
1071 1037
1038 if ((adapter->msi_mode != MSI_MODE_MULTIFUNC) ||
1039 (adapter->intr_scheme != INTR_SCHEME_PERPORT)) {
1040 printk(KERN_ERR "%s: Firmware interrupt scheme is "
1041 "incompatible with driver\n",
1042 netdev->name);
1043 adapter->driver_mismatch = 1;
1044 goto err_out_free_hw;
1045 }
1046
1072 if (adapter->fw_major < 4) { 1047 if (adapter->fw_major < 4) {
1073 adapter->crb_addr_cmd_producer = 1048 adapter->crb_addr_cmd_producer =
1074 crb_cmd_producer[adapter->portnum]; 1049 crb_cmd_producer[adapter->portnum];
@@ -1094,7 +1069,7 @@ static int netxen_nic_open(struct net_device *netdev)
1094 flags, netdev->name, adapter); 1069 flags, netdev->name, adapter);
1095 if (err) { 1070 if (err) {
1096 printk(KERN_ERR "request_irq failed with: %d\n", err); 1071 printk(KERN_ERR "request_irq failed with: %d\n", err);
1097 goto err_out_free_hw; 1072 goto err_out_free_rxbuf;
1098 } 1073 }
1099 1074
1100 adapter->is_up = NETXEN_ADAPTER_UP_MAGIC; 1075 adapter->is_up = NETXEN_ADAPTER_UP_MAGIC;
@@ -1116,6 +1091,7 @@ static int netxen_nic_open(struct net_device *netdev)
1116 if (adapter->set_mtu) 1091 if (adapter->set_mtu)
1117 adapter->set_mtu(adapter, netdev->mtu); 1092 adapter->set_mtu(adapter, netdev->mtu);
1118 1093
1094 adapter->ahw.linkup = 0;
1119 mod_timer(&adapter->watchdog_timer, jiffies); 1095 mod_timer(&adapter->watchdog_timer, jiffies);
1120 1096
1121 napi_enable(&adapter->napi); 1097 napi_enable(&adapter->napi);
@@ -1127,6 +1103,8 @@ static int netxen_nic_open(struct net_device *netdev)
1127 1103
1128err_out_free_irq: 1104err_out_free_irq:
1129 free_irq(adapter->irq, adapter); 1105 free_irq(adapter->irq, adapter);
1106err_out_free_rxbuf:
1107 netxen_release_rx_buffers(adapter);
1130err_out_free_hw: 1108err_out_free_hw:
1131 netxen_free_hw_resources(adapter); 1109 netxen_free_hw_resources(adapter);
1132err_out_free_sw: 1110err_out_free_sw:
@@ -1152,10 +1130,8 @@ static int netxen_nic_close(struct net_device *netdev)
1152 1130
1153 netxen_release_tx_buffers(adapter); 1131 netxen_release_tx_buffers(adapter);
1154 1132
1155 if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) { 1133 FLUSH_SCHEDULED_WORK();
1156 FLUSH_SCHEDULED_WORK(); 1134 del_timer_sync(&adapter->watchdog_timer);
1157 del_timer_sync(&adapter->watchdog_timer);
1158 }
1159 1135
1160 return 0; 1136 return 0;
1161} 1137}
@@ -1458,7 +1434,8 @@ void netxen_watchdog_task(struct work_struct *work)
1458 1434
1459 netxen_nic_handle_phy_intr(adapter); 1435 netxen_nic_handle_phy_intr(adapter);
1460 1436
1461 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); 1437 if (netif_running(adapter->netdev))
1438 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
1462} 1439}
1463 1440
1464static void netxen_tx_timeout(struct net_device *netdev) 1441static void netxen_tx_timeout(struct net_device *netdev)
@@ -1518,18 +1495,9 @@ struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev)
1518 return stats; 1495 return stats;
1519} 1496}
1520 1497
1521static inline void
1522netxen_handle_int(struct netxen_adapter *adapter)
1523{
1524 netxen_nic_disable_int(adapter);
1525 napi_schedule(&adapter->napi);
1526}
1527
1528static irqreturn_t netxen_intr(int irq, void *data) 1498static irqreturn_t netxen_intr(int irq, void *data)
1529{ 1499{
1530 struct netxen_adapter *adapter = data; 1500 struct netxen_adapter *adapter = data;
1531 u32 our_int = 0;
1532
1533 u32 status = 0; 1501 u32 status = 0;
1534 1502
1535 status = adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); 1503 status = adapter->pci_read_immediate(adapter, ISR_INT_VECTOR);
@@ -1544,22 +1512,32 @@ static irqreturn_t netxen_intr(int irq, void *data)
1544 if (!ISR_LEGACY_INT_TRIGGERED(status)) 1512 if (!ISR_LEGACY_INT_TRIGGERED(status))
1545 return IRQ_NONE; 1513 return IRQ_NONE;
1546 1514
1547 } else if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 1515 } else {
1516 unsigned long our_int = 0;
1548 1517
1549 our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR); 1518 our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR);
1519
1550 /* not our interrupt */ 1520 /* not our interrupt */
1551 if ((our_int & (0x80 << adapter->portnum)) == 0) 1521 if (!test_and_clear_bit((7 + adapter->portnum), &our_int))
1552 return IRQ_NONE; 1522 return IRQ_NONE;
1553 1523
1554 if (adapter->intr_scheme == INTR_SCHEME_PERPORT) { 1524 /* claim interrupt */
1555 /* claim interrupt */ 1525 adapter->pci_write_normalize(adapter,
1556 adapter->pci_write_normalize(adapter, 1526 CRB_INT_VECTOR, (our_int & 0xffffffff));
1557 CRB_INT_VECTOR,
1558 our_int & ~((u32)(0x80 << adapter->portnum)));
1559 }
1560 } 1527 }
1561 1528
1562 netxen_handle_int(adapter); 1529 /* clear interrupt */
1530 if (adapter->fw_major < 4)
1531 netxen_nic_disable_int(adapter);
1532
1533 adapter->pci_write_immediate(adapter,
1534 adapter->legacy_intr.tgt_status_reg,
1535 0xffffffff);
1536 /* read twice to ensure write is flushed */
1537 adapter->pci_read_immediate(adapter, ISR_INT_VECTOR);
1538 adapter->pci_read_immediate(adapter, ISR_INT_VECTOR);
1539
1540 napi_schedule(&adapter->napi);
1563 1541
1564 return IRQ_HANDLED; 1542 return IRQ_HANDLED;
1565} 1543}
@@ -1568,7 +1546,11 @@ static irqreturn_t netxen_msi_intr(int irq, void *data)
1568{ 1546{
1569 struct netxen_adapter *adapter = data; 1547 struct netxen_adapter *adapter = data;
1570 1548
1571 netxen_handle_int(adapter); 1549 /* clear interrupt */
1550 adapter->pci_write_immediate(adapter,
1551 msi_tgt_status[adapter->ahw.pci_func], 0xffffffff);
1552
1553 napi_schedule(&adapter->napi);
1572 return IRQ_HANDLED; 1554 return IRQ_HANDLED;
1573} 1555}
1574 1556
diff --git a/drivers/net/netxen/netxen_nic_phan_reg.h b/drivers/net/netxen/netxen_nic_phan_reg.h
index 83e5ee57bfef..b293adcc95ab 100644
--- a/drivers/net/netxen/netxen_nic_phan_reg.h
+++ b/drivers/net/netxen/netxen_nic_phan_reg.h
@@ -125,6 +125,8 @@
125#define CRB_SW_INT_MASK_2 NETXEN_NIC_REG(0x1e4) 125#define CRB_SW_INT_MASK_2 NETXEN_NIC_REG(0x1e4)
126#define CRB_SW_INT_MASK_3 NETXEN_NIC_REG(0x1e8) 126#define CRB_SW_INT_MASK_3 NETXEN_NIC_REG(0x1e8)
127 127
128#define CRB_MAC_BLOCK_START NETXEN_CAM_RAM(0x1c0)
129
128/* 130/*
129 * capabilities register, can be used to selectively enable/disable features 131 * capabilities register, can be used to selectively enable/disable features
130 * for backward compability 132 * for backward compability
diff --git a/drivers/net/ppp_mppe.c b/drivers/net/ppp_mppe.c
index b35d79449500..88f03c9e9403 100644
--- a/drivers/net/ppp_mppe.c
+++ b/drivers/net/ppp_mppe.c
@@ -46,7 +46,6 @@
46#include <linux/err.h> 46#include <linux/err.h>
47#include <linux/module.h> 47#include <linux/module.h>
48#include <linux/kernel.h> 48#include <linux/kernel.h>
49#include <linux/version.h>
50#include <linux/init.h> 49#include <linux/init.h>
51#include <linux/types.h> 50#include <linux/types.h>
52#include <linux/slab.h> 51#include <linux/slab.h>
diff --git a/drivers/net/pppol2tp.c b/drivers/net/pppol2tp.c
index f9298827a76c..ff175e8f36b2 100644
--- a/drivers/net/pppol2tp.c
+++ b/drivers/net/pppol2tp.c
@@ -61,7 +61,6 @@
61 */ 61 */
62 62
63#include <linux/module.h> 63#include <linux/module.h>
64#include <linux/version.h>
65#include <linux/string.h> 64#include <linux/string.h>
66#include <linux/list.h> 65#include <linux/list.h>
67#include <asm/uaccess.h> 66#include <asm/uaccess.h>
diff --git a/drivers/net/r6040.c b/drivers/net/r6040.c
index 6531ff565c54..5d86281d9363 100644
--- a/drivers/net/r6040.c
+++ b/drivers/net/r6040.c
@@ -24,7 +24,6 @@
24 24
25#include <linux/kernel.h> 25#include <linux/kernel.h>
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/version.h>
28#include <linux/moduleparam.h> 27#include <linux/moduleparam.h>
29#include <linux/string.h> 28#include <linux/string.h>
30#include <linux/timer.h> 29#include <linux/timer.h>
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 25e62cf58d3a..1c370e6aa641 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -20,7 +20,6 @@
20 * the file called "COPYING". 20 * the file called "COPYING".
21 */ 21 */
22 22
23#include <linux/version.h>
24#include <linux/init.h> 23#include <linux/init.h>
25#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h> 25#include <linux/etherdevice.h>
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 7d29edcd40b4..e24b25ca1c69 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -24,7 +24,6 @@
24 24
25#include <linux/crc32.h> 25#include <linux/crc32.h>
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h> 27#include <linux/module.h>
29#include <linux/netdevice.h> 28#include <linux/netdevice.h>
30#include <linux/dma-mapping.h> 29#include <linux/dma-mapping.h>
@@ -666,11 +665,16 @@ static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
666 665
667 if (hw->chip_id != CHIP_ID_YUKON_EC) { 666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
668 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
669 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
670 670
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
671 /* enable Power Down */ 672 /* enable Power Down */
672 ctrl |= PHY_M_PC_POW_D_ENA; 673 ctrl |= PHY_M_PC_POW_D_ENA;
673 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
674 } 678 }
675 679
676 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
diff --git a/drivers/net/tehuti.h b/drivers/net/tehuti.h
index c66dfc9ec1ec..7db48f1cd949 100644
--- a/drivers/net/tehuti.h
+++ b/drivers/net/tehuti.h
@@ -27,7 +27,6 @@
27#include <linux/sched.h> 27#include <linux/sched.h>
28#include <linux/tty.h> 28#include <linux/tty.h>
29#include <linux/if_vlan.h> 29#include <linux/if_vlan.h>
30#include <linux/version.h>
31#include <linux/interrupt.h> 30#include <linux/interrupt.h>
32#include <linux/vmalloc.h> 31#include <linux/vmalloc.h>
33#include <asm/byteorder.h> 32#include <asm/byteorder.h>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d2439b85a790..71d2c5cfdad9 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -66,8 +66,8 @@
66 66
67#define DRV_MODULE_NAME "tg3" 67#define DRV_MODULE_NAME "tg3"
68#define PFX DRV_MODULE_NAME ": " 68#define PFX DRV_MODULE_NAME ": "
69#define DRV_MODULE_VERSION "3.93" 69#define DRV_MODULE_VERSION "3.94"
70#define DRV_MODULE_RELDATE "May 22, 2008" 70#define DRV_MODULE_RELDATE "August 14, 2008"
71 71
72#define TG3_DEF_MAC_MODE 0 72#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0 73#define TG3_DEF_RX_MODE 0
@@ -536,6 +536,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
536 return 0; 536 return 0;
537 537
538 switch (locknum) { 538 switch (locknum) {
539 case TG3_APE_LOCK_GRC:
539 case TG3_APE_LOCK_MEM: 540 case TG3_APE_LOCK_MEM:
540 break; 541 break;
541 default: 542 default:
@@ -573,6 +574,7 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
573 return; 574 return;
574 575
575 switch (locknum) { 576 switch (locknum) {
577 case TG3_APE_LOCK_GRC:
576 case TG3_APE_LOCK_MEM: 578 case TG3_APE_LOCK_MEM:
577 break; 579 break;
578 default: 580 default:
@@ -1018,15 +1020,43 @@ static void tg3_mdio_fini(struct tg3 *tp)
1018} 1020}
1019 1021
1020/* tp->lock is held. */ 1022/* tp->lock is held. */
1023static inline void tg3_generate_fw_event(struct tg3 *tp)
1024{
1025 u32 val;
1026
1027 val = tr32(GRC_RX_CPU_EVENT);
1028 val |= GRC_RX_CPU_DRIVER_EVENT;
1029 tw32_f(GRC_RX_CPU_EVENT, val);
1030
1031 tp->last_event_jiffies = jiffies;
1032}
1033
1034#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1035
1036/* tp->lock is held. */
1021static void tg3_wait_for_event_ack(struct tg3 *tp) 1037static void tg3_wait_for_event_ack(struct tg3 *tp)
1022{ 1038{
1023 int i; 1039 int i;
1040 unsigned int delay_cnt;
1041 long time_remain;
1042
1043 /* If enough time has passed, no wait is necessary. */
1044 time_remain = (long)(tp->last_event_jiffies + 1 +
1045 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1046 (long)jiffies;
1047 if (time_remain < 0)
1048 return;
1024 1049
1025 /* Wait for up to 2.5 milliseconds */ 1050 /* Check if we can shorten the wait time. */
1026 for (i = 0; i < 250000; i++) { 1051 delay_cnt = jiffies_to_usecs(time_remain);
1052 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1053 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1054 delay_cnt = (delay_cnt >> 3) + 1;
1055
1056 for (i = 0; i < delay_cnt; i++) {
1027 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) 1057 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1028 break; 1058 break;
1029 udelay(10); 1059 udelay(8);
1030 } 1060 }
1031} 1061}
1032 1062
@@ -1075,9 +1105,7 @@ static void tg3_ump_link_report(struct tg3 *tp)
1075 val = 0; 1105 val = 0;
1076 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); 1106 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1077 1107
1078 val = tr32(GRC_RX_CPU_EVENT); 1108 tg3_generate_fw_event(tp);
1079 val |= GRC_RX_CPU_DRIVER_EVENT;
1080 tw32_f(GRC_RX_CPU_EVENT, val);
1081} 1109}
1082 1110
1083static void tg3_link_report(struct tg3 *tp) 1111static void tg3_link_report(struct tg3 *tp)
@@ -2124,6 +2152,13 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2124 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) 2152 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2125 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; 2153 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2126 2154
2155 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2156 mac_mode |= tp->mac_mode &
2157 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2158 if (mac_mode & MAC_MODE_APE_TX_EN)
2159 mac_mode |= MAC_MODE_TDE_ENABLE;
2160 }
2161
2127 tw32_f(MAC_MODE, mac_mode); 2162 tw32_f(MAC_MODE, mac_mode);
2128 udelay(100); 2163 udelay(100);
2129 2164
@@ -5493,7 +5528,7 @@ static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5493 return; 5528 return;
5494 5529
5495 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); 5530 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5496 if (apedata != APE_FW_STATUS_READY) 5531 if (!(apedata & APE_FW_STATUS_READY))
5497 return; 5532 return;
5498 5533
5499 /* Wait for up to 1 millisecond for APE to service previous event. */ 5534 /* Wait for up to 1 millisecond for APE to service previous event. */
@@ -5760,6 +5795,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5760 5795
5761 tg3_mdio_stop(tp); 5796 tg3_mdio_stop(tp);
5762 5797
5798 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5799
5763 /* No matching tg3_nvram_unlock() after this because 5800 /* No matching tg3_nvram_unlock() after this because
5764 * chip reset below will undo the nvram lock. 5801 * chip reset below will undo the nvram lock.
5765 */ 5802 */
@@ -5908,12 +5945,19 @@ static int tg3_chip_reset(struct tg3 *tp)
5908 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { 5945 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5909 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; 5946 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5910 tw32_f(MAC_MODE, tp->mac_mode); 5947 tw32_f(MAC_MODE, tp->mac_mode);
5948 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
5949 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
5950 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
5951 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
5952 tw32_f(MAC_MODE, tp->mac_mode);
5911 } else 5953 } else
5912 tw32_f(MAC_MODE, 0); 5954 tw32_f(MAC_MODE, 0);
5913 udelay(40); 5955 udelay(40);
5914 5956
5915 tg3_mdio_start(tp); 5957 tg3_mdio_start(tp);
5916 5958
5959 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
5960
5917 err = tg3_poll_fw(tp); 5961 err = tg3_poll_fw(tp);
5918 if (err) 5962 if (err)
5919 return err; 5963 return err;
@@ -5935,6 +5979,7 @@ static int tg3_chip_reset(struct tg3 *tp)
5935 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); 5979 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5936 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 5980 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5937 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 5981 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5982 tp->last_event_jiffies = jiffies;
5938 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 5983 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5939 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 5984 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5940 } 5985 }
@@ -5948,15 +5993,12 @@ static void tg3_stop_fw(struct tg3 *tp)
5948{ 5993{
5949 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && 5994 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5950 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { 5995 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5951 u32 val;
5952
5953 /* Wait for RX cpu to ACK the previous event. */ 5996 /* Wait for RX cpu to ACK the previous event. */
5954 tg3_wait_for_event_ack(tp); 5997 tg3_wait_for_event_ack(tp);
5955 5998
5956 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); 5999 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5957 val = tr32(GRC_RX_CPU_EVENT); 6000
5958 val |= GRC_RX_CPU_DRIVER_EVENT; 6001 tg3_generate_fw_event(tp);
5959 tw32(GRC_RX_CPU_EVENT, val);
5960 6002
5961 /* Wait for RX cpu to ACK this event. */ 6003 /* Wait for RX cpu to ACK this event. */
5962 tg3_wait_for_event_ack(tp); 6004 tg3_wait_for_event_ack(tp);
@@ -7406,7 +7448,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7406 udelay(10); 7448 udelay(10);
7407 } 7449 }
7408 7450
7409 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | 7451 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7452 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7453 else
7454 tp->mac_mode = 0;
7455 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7410 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; 7456 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7411 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 7457 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7412 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 7458 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
@@ -7840,9 +7886,8 @@ static void tg3_timer(unsigned long __opaque)
7840 * resets. 7886 * resets.
7841 */ 7887 */
7842 if (!--tp->asf_counter) { 7888 if (!--tp->asf_counter) {
7843 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { 7889 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7844 u32 val; 7890 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7845
7846 tg3_wait_for_event_ack(tp); 7891 tg3_wait_for_event_ack(tp);
7847 7892
7848 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, 7893 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
@@ -7850,9 +7895,8 @@ static void tg3_timer(unsigned long __opaque)
7850 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); 7895 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7851 /* 5 seconds timeout */ 7896 /* 5 seconds timeout */
7852 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); 7897 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7853 val = tr32(GRC_RX_CPU_EVENT); 7898
7854 val |= GRC_RX_CPU_DRIVER_EVENT; 7899 tg3_generate_fw_event(tp);
7855 tw32_f(GRC_RX_CPU_EVENT, val);
7856 } 7900 }
7857 tp->asf_counter = tp->asf_multiplier; 7901 tp->asf_counter = tp->asf_multiplier;
7858 } 7902 }
@@ -8422,6 +8466,11 @@ static inline unsigned long get_stat64(tg3_stat64_t *val)
8422 return ret; 8466 return ret;
8423} 8467}
8424 8468
8469static inline u64 get_estat64(tg3_stat64_t *val)
8470{
8471 return ((u64)val->high << 32) | ((u64)val->low);
8472}
8473
8425static unsigned long calc_crc_errors(struct tg3 *tp) 8474static unsigned long calc_crc_errors(struct tg3 *tp)
8426{ 8475{
8427 struct tg3_hw_stats *hw_stats = tp->hw_stats; 8476 struct tg3_hw_stats *hw_stats = tp->hw_stats;
@@ -8450,7 +8499,7 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
8450 8499
8451#define ESTAT_ADD(member) \ 8500#define ESTAT_ADD(member) \
8452 estats->member = old_estats->member + \ 8501 estats->member = old_estats->member + \
8453 get_stat64(&hw_stats->member) 8502 get_estat64(&hw_stats->member)
8454 8503
8455static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) 8504static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8456{ 8505{
@@ -12416,6 +12465,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12416 tp->misc_host_ctrl); 12465 tp->misc_host_ctrl);
12417 } 12466 }
12418 12467
12468 /* Preserve the APE MAC_MODE bits */
12469 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12470 tp->mac_mode = tr32(MAC_MODE) |
12471 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12472 else
12473 tp->mac_mode = TG3_DEF_MAC_MODE;
12474
12419 /* these are limited to 10/100 only */ 12475 /* these are limited to 10/100 only */
12420 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && 12476 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12421 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || 12477 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
@@ -13275,7 +13331,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13275 tp->pdev = pdev; 13331 tp->pdev = pdev;
13276 tp->dev = dev; 13332 tp->dev = dev;
13277 tp->pm_cap = pm_cap; 13333 tp->pm_cap = pm_cap;
13278 tp->mac_mode = TG3_DEF_MAC_MODE;
13279 tp->rx_mode = TG3_DEF_RX_MODE; 13334 tp->rx_mode = TG3_DEF_RX_MODE;
13280 tp->tx_mode = TG3_DEF_TX_MODE; 13335 tp->tx_mode = TG3_DEF_TX_MODE;
13281 13336
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index df07842172b7..f5b8cab8d4b5 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -325,6 +325,8 @@
325#define MAC_MODE_TDE_ENABLE 0x00200000 325#define MAC_MODE_TDE_ENABLE 0x00200000
326#define MAC_MODE_RDE_ENABLE 0x00400000 326#define MAC_MODE_RDE_ENABLE 0x00400000
327#define MAC_MODE_FHDE_ENABLE 0x00800000 327#define MAC_MODE_FHDE_ENABLE 0x00800000
328#define MAC_MODE_APE_RX_EN 0x08000000
329#define MAC_MODE_APE_TX_EN 0x10000000
328#define MAC_STATUS 0x00000404 330#define MAC_STATUS 0x00000404
329#define MAC_STATUS_PCS_SYNCED 0x00000001 331#define MAC_STATUS_PCS_SYNCED 0x00000001
330#define MAC_STATUS_SIGNAL_DET 0x00000002 332#define MAC_STATUS_SIGNAL_DET 0x00000002
@@ -1889,6 +1891,7 @@
1889#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 1891#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
1890 1892
1891/* APE convenience enumerations. */ 1893/* APE convenience enumerations. */
1894#define TG3_APE_LOCK_GRC 1
1892#define TG3_APE_LOCK_MEM 4 1895#define TG3_APE_LOCK_MEM 4
1893 1896
1894#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 1897#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
@@ -2429,7 +2432,10 @@ struct tg3 {
2429 struct tg3_ethtool_stats estats; 2432 struct tg3_ethtool_stats estats;
2430 struct tg3_ethtool_stats estats_prev; 2433 struct tg3_ethtool_stats estats_prev;
2431 2434
2435 union {
2432 unsigned long phy_crc_errors; 2436 unsigned long phy_crc_errors;
2437 unsigned long last_event_jiffies;
2438 };
2433 2439
2434 u32 rx_offset; 2440 u32 rx_offset;
2435 u32 tg3_flags; 2441 u32 tg3_flags;
diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c
index 85246ed7cb9c..ec871f646766 100644
--- a/drivers/net/tlan.c
+++ b/drivers/net/tlan.c
@@ -360,8 +360,8 @@ TLan_GetSKB( const struct tlan_list_tag *tag)
360{ 360{
361 unsigned long addr; 361 unsigned long addr;
362 362
363 addr = tag->buffer[8].address; 363 addr = tag->buffer[9].address;
364 addr |= (tag->buffer[9].address << 16) << 16; 364 addr |= (tag->buffer[8].address << 16) << 16;
365 return (struct sk_buff *) addr; 365 return (struct sk_buff *) addr;
366} 366}
367 367
@@ -1984,7 +1984,6 @@ static void TLan_ResetLists( struct net_device *dev )
1984 TLanList *list; 1984 TLanList *list;
1985 dma_addr_t list_phys; 1985 dma_addr_t list_phys;
1986 struct sk_buff *skb; 1986 struct sk_buff *skb;
1987 void *t = NULL;
1988 1987
1989 priv->txHead = 0; 1988 priv->txHead = 0;
1990 priv->txTail = 0; 1989 priv->txTail = 0;
@@ -2022,7 +2021,8 @@ static void TLan_ResetLists( struct net_device *dev )
2022 } 2021 }
2023 2022
2024 skb_reserve( skb, NET_IP_ALIGN ); 2023 skb_reserve( skb, NET_IP_ALIGN );
2025 list->buffer[0].address = pci_map_single(priv->pciDev, t, 2024 list->buffer[0].address = pci_map_single(priv->pciDev,
2025 skb->data,
2026 TLAN_MAX_FRAME_SIZE, 2026 TLAN_MAX_FRAME_SIZE,
2027 PCI_DMA_FROMDEVICE); 2027 PCI_DMA_FROMDEVICE);
2028 TLan_StoreSKB(list, skb); 2028 TLan_StoreSKB(list, skb);
diff --git a/drivers/net/tokenring/lanstreamer.c b/drivers/net/tokenring/lanstreamer.c
index 47d84cd28097..59d1673f9387 100644
--- a/drivers/net/tokenring/lanstreamer.c
+++ b/drivers/net/tokenring/lanstreamer.c
@@ -119,7 +119,6 @@
119#include <linux/pci.h> 119#include <linux/pci.h>
120#include <linux/dma-mapping.h> 120#include <linux/dma-mapping.h>
121#include <linux/spinlock.h> 121#include <linux/spinlock.h>
122#include <linux/version.h>
123#include <linux/bitops.h> 122#include <linux/bitops.h>
124#include <linux/jiffies.h> 123#include <linux/jiffies.h>
125 124
diff --git a/drivers/net/tokenring/lanstreamer.h b/drivers/net/tokenring/lanstreamer.h
index e7bb3494afc7..13ccee6449c1 100644
--- a/drivers/net/tokenring/lanstreamer.h
+++ b/drivers/net/tokenring/lanstreamer.h
@@ -60,8 +60,6 @@
60 * 60 *
61 */ 61 */
62 62
63#include <linux/version.h>
64
65/* MAX_INTR - the maximum number of times we can loop 63/* MAX_INTR - the maximum number of times we can loop
66 * inside the interrupt function before returning 64 * inside the interrupt function before returning
67 * control to the OS (maximum value is 256) 65 * control to the OS (maximum value is 256)
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index e6bbc639c2d0..6daea0c91862 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -358,6 +358,66 @@ static unsigned int tun_chr_poll(struct file *file, poll_table * wait)
358 return mask; 358 return mask;
359} 359}
360 360
361/* prepad is the amount to reserve at front. len is length after that.
362 * linear is a hint as to how much to copy (usually headers). */
363static struct sk_buff *tun_alloc_skb(size_t prepad, size_t len, size_t linear,
364 gfp_t gfp)
365{
366 struct sk_buff *skb;
367 unsigned int i;
368
369 skb = alloc_skb(prepad + len, gfp|__GFP_NOWARN);
370 if (skb) {
371 skb_reserve(skb, prepad);
372 skb_put(skb, len);
373 return skb;
374 }
375
376 /* Under a page? Don't bother with paged skb. */
377 if (prepad + len < PAGE_SIZE)
378 return NULL;
379
380 /* Start with a normal skb, and add pages. */
381 skb = alloc_skb(prepad + linear, gfp);
382 if (!skb)
383 return NULL;
384
385 skb_reserve(skb, prepad);
386 skb_put(skb, linear);
387
388 len -= linear;
389
390 for (i = 0; i < MAX_SKB_FRAGS; i++) {
391 skb_frag_t *f = &skb_shinfo(skb)->frags[i];
392
393 f->page = alloc_page(gfp|__GFP_ZERO);
394 if (!f->page)
395 break;
396
397 f->page_offset = 0;
398 f->size = PAGE_SIZE;
399
400 skb->data_len += PAGE_SIZE;
401 skb->len += PAGE_SIZE;
402 skb->truesize += PAGE_SIZE;
403 skb_shinfo(skb)->nr_frags++;
404
405 if (len < PAGE_SIZE) {
406 len = 0;
407 break;
408 }
409 len -= PAGE_SIZE;
410 }
411
412 /* Too large, or alloc fail? */
413 if (unlikely(len)) {
414 kfree_skb(skb);
415 skb = NULL;
416 }
417
418 return skb;
419}
420
361/* Get packet from user space buffer */ 421/* Get packet from user space buffer */
362static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv, size_t count) 422static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv, size_t count)
363{ 423{
@@ -391,14 +451,12 @@ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv,
391 return -EINVAL; 451 return -EINVAL;
392 } 452 }
393 453
394 if (!(skb = alloc_skb(len + align, GFP_KERNEL))) { 454 if (!(skb = tun_alloc_skb(align, len, gso.hdr_len, GFP_KERNEL))) {
395 tun->dev->stats.rx_dropped++; 455 tun->dev->stats.rx_dropped++;
396 return -ENOMEM; 456 return -ENOMEM;
397 } 457 }
398 458
399 if (align) 459 if (skb_copy_datagram_from_iovec(skb, 0, iv, len)) {
400 skb_reserve(skb, align);
401 if (memcpy_fromiovec(skb_put(skb, len), iv, len)) {
402 tun->dev->stats.rx_dropped++; 460 tun->dev->stats.rx_dropped++;
403 kfree_skb(skb); 461 kfree_skb(skb);
404 return -EFAULT; 462 return -EFAULT;
@@ -748,6 +806,36 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
748 return err; 806 return err;
749} 807}
750 808
809static int tun_get_iff(struct net *net, struct file *file, struct ifreq *ifr)
810{
811 struct tun_struct *tun = file->private_data;
812
813 if (!tun)
814 return -EBADFD;
815
816 DBG(KERN_INFO "%s: tun_get_iff\n", tun->dev->name);
817
818 strcpy(ifr->ifr_name, tun->dev->name);
819
820 ifr->ifr_flags = 0;
821
822 if (ifr->ifr_flags & TUN_TUN_DEV)
823 ifr->ifr_flags |= IFF_TUN;
824 else
825 ifr->ifr_flags |= IFF_TAP;
826
827 if (tun->flags & TUN_NO_PI)
828 ifr->ifr_flags |= IFF_NO_PI;
829
830 if (tun->flags & TUN_ONE_QUEUE)
831 ifr->ifr_flags |= IFF_ONE_QUEUE;
832
833 if (tun->flags & TUN_VNET_HDR)
834 ifr->ifr_flags |= IFF_VNET_HDR;
835
836 return 0;
837}
838
751/* This is like a cut-down ethtool ops, except done via tun fd so no 839/* This is like a cut-down ethtool ops, except done via tun fd so no
752 * privs required. */ 840 * privs required. */
753static int set_offload(struct net_device *dev, unsigned long arg) 841static int set_offload(struct net_device *dev, unsigned long arg)
@@ -833,6 +921,15 @@ static int tun_chr_ioctl(struct inode *inode, struct file *file,
833 DBG(KERN_INFO "%s: tun_chr_ioctl cmd %d\n", tun->dev->name, cmd); 921 DBG(KERN_INFO "%s: tun_chr_ioctl cmd %d\n", tun->dev->name, cmd);
834 922
835 switch (cmd) { 923 switch (cmd) {
924 case TUNGETIFF:
925 ret = tun_get_iff(current->nsproxy->net_ns, file, &ifr);
926 if (ret)
927 return ret;
928
929 if (copy_to_user(argp, &ifr, sizeof(ifr)))
930 return -EFAULT;
931 break;
932
836 case TUNSETNOCSUM: 933 case TUNSETNOCSUM:
837 /* Disable/Enable checksum */ 934 /* Disable/Enable checksum */
838 if (arg) 935 if (arg)
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c
index 8549f1159a30..734ce0977f02 100644
--- a/drivers/net/typhoon.c
+++ b/drivers/net/typhoon.c
@@ -128,7 +128,6 @@ static const int multicast_filter_limit = 32;
128#include <asm/io.h> 128#include <asm/io.h>
129#include <asm/uaccess.h> 129#include <asm/uaccess.h>
130#include <linux/in6.h> 130#include <linux/in6.h>
131#include <linux/version.h>
132#include <linux/dma-mapping.h> 131#include <linux/dma-mapping.h>
133 132
134#include "typhoon.h" 133#include "typhoon.h"
diff --git a/drivers/net/usb/Kconfig b/drivers/net/usb/Kconfig
index 68e198bd538b..0973b6e37024 100644
--- a/drivers/net/usb/Kconfig
+++ b/drivers/net/usb/Kconfig
@@ -154,17 +154,6 @@ config USB_NET_AX8817X
154 This driver creates an interface named "ethX", where X depends on 154 This driver creates an interface named "ethX", where X depends on
155 what other networking devices you have in use. 155 what other networking devices you have in use.
156 156
157config USB_HSO
158 tristate "Option USB High Speed Mobile Devices"
159 depends on USB && RFKILL
160 default n
161 help
162 Choose this option if you have an Option HSDPA/HSUPA card.
163 These cards support downlink speeds of 7.2Mbps or greater.
164
165 To compile this driver as a module, choose M here: the
166 module will be called hso.
167
168config USB_NET_CDCETHER 157config USB_NET_CDCETHER
169 tristate "CDC Ethernet support (smart devices such as cable modems)" 158 tristate "CDC Ethernet support (smart devices such as cable modems)"
170 depends on USB_USBNET 159 depends on USB_USBNET
@@ -337,5 +326,15 @@ config USB_NET_ZAURUS
337 really need this non-conformant variant of CDC Ethernet (or in 326 really need this non-conformant variant of CDC Ethernet (or in
338 some cases CDC MDLM) protocol, not "g_ether". 327 some cases CDC MDLM) protocol, not "g_ether".
339 328
329config USB_HSO
330 tristate "Option USB High Speed Mobile Devices"
331 depends on USB && RFKILL
332 default n
333 help
334 Choose this option if you have an Option HSDPA/HSUPA card.
335 These cards support downlink speeds of 7.2Mbps or greater.
336
337 To compile this driver as a module, choose M here: the
338 module will be called hso.
340 339
341endmenu 340endmenu
diff --git a/drivers/net/usb/hso.c b/drivers/net/usb/hso.c
index 031d07b105af..1b7cac77159e 100644
--- a/drivers/net/usb/hso.c
+++ b/drivers/net/usb/hso.c
@@ -102,8 +102,12 @@
102 102
103#define MAX_RX_URBS 2 103#define MAX_RX_URBS 2
104 104
105#define get_serial_by_tty(x) \ 105static inline struct hso_serial *get_serial_by_tty(struct tty_struct *tty)
106 (x ? (struct hso_serial *)x->driver_data : NULL) 106{
107 if (tty)
108 return tty->driver_data;
109 return NULL;
110}
107 111
108/*****************************************************************************/ 112/*****************************************************************************/
109/* Debugging functions */ 113/* Debugging functions */
@@ -294,24 +298,25 @@ static int hso_get_activity(struct hso_device *hso_dev);
294 298
295/* #define DEBUG */ 299/* #define DEBUG */
296 300
297#define dev2net(x) (x->port_data.dev_net) 301static inline struct hso_net *dev2net(struct hso_device *hso_dev)
298#define dev2ser(x) (x->port_data.dev_serial) 302{
303 return hso_dev->port_data.dev_net;
304}
305
306static inline struct hso_serial *dev2ser(struct hso_device *hso_dev)
307{
308 return hso_dev->port_data.dev_serial;
309}
299 310
300/* Debugging functions */ 311/* Debugging functions */
301#ifdef DEBUG 312#ifdef DEBUG
302static void dbg_dump(int line_count, const char *func_name, unsigned char *buf, 313static void dbg_dump(int line_count, const char *func_name, unsigned char *buf,
303 unsigned int len) 314 unsigned int len)
304{ 315{
305 u8 i = 0; 316 static char name[255];
306 317
307 printk(KERN_DEBUG "[%d:%s]: len %d", line_count, func_name, len); 318 sprintf(name, "hso[%d:%s]", line_count, func_name);
308 319 print_hex_dump_bytes(name, DUMP_PREFIX_NONE, buf, len);
309 for (i = 0; i < len; i++) {
310 if (!(i % 16))
311 printk("\n 0x%03x: ", i);
312 printk("%02x ", (unsigned char)buf[i]);
313 }
314 printk("\n");
315} 320}
316 321
317#define DUMP(buf_, len_) \ 322#define DUMP(buf_, len_) \
@@ -528,13 +533,12 @@ static struct hso_serial *get_serial_by_shared_int_and_type(
528 533
529static struct hso_serial *get_serial_by_index(unsigned index) 534static struct hso_serial *get_serial_by_index(unsigned index)
530{ 535{
531 struct hso_serial *serial; 536 struct hso_serial *serial = NULL;
532 unsigned long flags; 537 unsigned long flags;
533 538
534 if (!serial_table[index])
535 return NULL;
536 spin_lock_irqsave(&serial_table_lock, flags); 539 spin_lock_irqsave(&serial_table_lock, flags);
537 serial = dev2ser(serial_table[index]); 540 if (serial_table[index])
541 serial = dev2ser(serial_table[index]);
538 spin_unlock_irqrestore(&serial_table_lock, flags); 542 spin_unlock_irqrestore(&serial_table_lock, flags);
539 543
540 return serial; 544 return serial;
@@ -561,6 +565,7 @@ static int get_free_serial_index(void)
561static void set_serial_by_index(unsigned index, struct hso_serial *serial) 565static void set_serial_by_index(unsigned index, struct hso_serial *serial)
562{ 566{
563 unsigned long flags; 567 unsigned long flags;
568
564 spin_lock_irqsave(&serial_table_lock, flags); 569 spin_lock_irqsave(&serial_table_lock, flags);
565 if (serial) 570 if (serial)
566 serial_table[index] = serial->parent; 571 serial_table[index] = serial->parent;
@@ -569,7 +574,7 @@ static void set_serial_by_index(unsigned index, struct hso_serial *serial)
569 spin_unlock_irqrestore(&serial_table_lock, flags); 574 spin_unlock_irqrestore(&serial_table_lock, flags);
570} 575}
571 576
572/* log a meaningfull explanation of an USB status */ 577/* log a meaningful explanation of an USB status */
573static void log_usb_status(int status, const char *function) 578static void log_usb_status(int status, const char *function)
574{ 579{
575 char *explanation; 580 char *explanation;
@@ -1103,8 +1108,8 @@ static void hso_serial_close(struct tty_struct *tty, struct file *filp)
1103 /* reset the rts and dtr */ 1108 /* reset the rts and dtr */
1104 /* do the actual close */ 1109 /* do the actual close */
1105 serial->open_count--; 1110 serial->open_count--;
1111 kref_put(&serial->parent->ref, hso_serial_ref_free);
1106 if (serial->open_count <= 0) { 1112 if (serial->open_count <= 0) {
1107 kref_put(&serial->parent->ref, hso_serial_ref_free);
1108 serial->open_count = 0; 1113 serial->open_count = 0;
1109 if (serial->tty) { 1114 if (serial->tty) {
1110 serial->tty->driver_data = NULL; 1115 serial->tty->driver_data = NULL;
@@ -1467,7 +1472,8 @@ static void hso_std_serial_write_bulk_callback(struct urb *urb)
1467 return; 1472 return;
1468 } 1473 }
1469 hso_put_activity(serial->parent); 1474 hso_put_activity(serial->parent);
1470 tty_wakeup(serial->tty); 1475 if (serial->tty)
1476 tty_wakeup(serial->tty);
1471 hso_kick_transmit(serial); 1477 hso_kick_transmit(serial);
1472 1478
1473 D1(" "); 1479 D1(" ");
@@ -1538,7 +1544,8 @@ static void ctrl_callback(struct urb *urb)
1538 clear_bit(HSO_SERIAL_FLAG_RX_SENT, &serial->flags); 1544 clear_bit(HSO_SERIAL_FLAG_RX_SENT, &serial->flags);
1539 } else { 1545 } else {
1540 hso_put_activity(serial->parent); 1546 hso_put_activity(serial->parent);
1541 tty_wakeup(serial->tty); 1547 if (serial->tty)
1548 tty_wakeup(serial->tty);
1542 /* response to a write command */ 1549 /* response to a write command */
1543 hso_kick_transmit(serial); 1550 hso_kick_transmit(serial);
1544 } 1551 }
@@ -2652,7 +2659,7 @@ static void hso_free_interface(struct usb_interface *interface)
2652 hso_stop_net_device(network_table[i]); 2659 hso_stop_net_device(network_table[i]);
2653 cancel_work_sync(&network_table[i]->async_put_intf); 2660 cancel_work_sync(&network_table[i]->async_put_intf);
2654 cancel_work_sync(&network_table[i]->async_get_intf); 2661 cancel_work_sync(&network_table[i]->async_get_intf);
2655 if(rfk) 2662 if (rfk)
2656 rfkill_unregister(rfk); 2663 rfkill_unregister(rfk);
2657 hso_free_net_device(network_table[i]); 2664 hso_free_net_device(network_table[i]);
2658 } 2665 }
@@ -2723,7 +2730,7 @@ static int hso_mux_submit_intr_urb(struct hso_shared_int *shared_int,
2723} 2730}
2724 2731
2725/* operations setup of the serial interface */ 2732/* operations setup of the serial interface */
2726static struct tty_operations hso_serial_ops = { 2733static const struct tty_operations hso_serial_ops = {
2727 .open = hso_serial_open, 2734 .open = hso_serial_open,
2728 .close = hso_serial_close, 2735 .close = hso_serial_close,
2729 .write = hso_serial_write, 2736 .write = hso_serial_write,
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c
index 2028866f5995..b20a45aa8680 100644
--- a/drivers/net/wireless/ath5k/base.c
+++ b/drivers/net/wireless/ath5k/base.c
@@ -40,7 +40,6 @@
40 * 40 *
41 */ 41 */
42 42
43#include <linux/version.h>
44#include <linux/module.h> 43#include <linux/module.h>
45#include <linux/delay.h> 44#include <linux/delay.h>
46#include <linux/hardirq.h> 45#include <linux/hardirq.h>
@@ -587,7 +586,6 @@ ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
587 ath5k_stop_hw(sc); 586 ath5k_stop_hw(sc);
588 587
589 free_irq(pdev->irq, sc); 588 free_irq(pdev->irq, sc);
590 pci_disable_msi(pdev);
591 pci_save_state(pdev); 589 pci_save_state(pdev);
592 pci_disable_device(pdev); 590 pci_disable_device(pdev);
593 pci_set_power_state(pdev, PCI_D3hot); 591 pci_set_power_state(pdev, PCI_D3hot);
@@ -616,12 +614,10 @@ ath5k_pci_resume(struct pci_dev *pdev)
616 */ 614 */
617 pci_write_config_byte(pdev, 0x41, 0); 615 pci_write_config_byte(pdev, 0x41, 0);
618 616
619 pci_enable_msi(pdev);
620
621 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 617 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
622 if (err) { 618 if (err) {
623 ATH5K_ERR(sc, "request_irq failed\n"); 619 ATH5K_ERR(sc, "request_irq failed\n");
624 goto err_msi; 620 goto err_no_irq;
625 } 621 }
626 622
627 err = ath5k_init(sc); 623 err = ath5k_init(sc);
@@ -642,8 +638,7 @@ ath5k_pci_resume(struct pci_dev *pdev)
642 return 0; 638 return 0;
643err_irq: 639err_irq:
644 free_irq(pdev->irq, sc); 640 free_irq(pdev->irq, sc);
645err_msi: 641err_no_irq:
646 pci_disable_msi(pdev);
647 pci_disable_device(pdev); 642 pci_disable_device(pdev);
648 return err; 643 return err;
649} 644}
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index bde162f128ab..a17eb130f574 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -5017,7 +5017,11 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
5017 5017
5018 for (i = 0; i < 123; i++) { 5018 for (i = 0; i < 123; i++) {
5019 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 5019 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
5020 if ((abs(cur_vit_mask - bin)) < 75) 5020
5021 /* workaround for gcc bug #37014 */
5022 volatile int tmp = abs(cur_vit_mask - bin);
5023
5024 if (tmp < 75)
5021 mask_amt = 1; 5025 mask_amt = 1;
5022 else 5026 else
5023 mask_amt = 0; 5027 mask_amt = 0;
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 3bf3a869361f..7205a936ec74 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -33,7 +33,6 @@
33#include <linux/moduleparam.h> 33#include <linux/moduleparam.h>
34#include <linux/if_arp.h> 34#include <linux/if_arp.h>
35#include <linux/etherdevice.h> 35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h> 36#include <linux/firmware.h>
38#include <linux/wireless.h> 37#include <linux/wireless.h>
39#include <linux/workqueue.h> 38#include <linux/workqueue.h>
@@ -4615,7 +4614,9 @@ static void b43_sprom_fixup(struct ssb_bus *bus)
4615 if (bus->bustype == SSB_BUSTYPE_PCI) { 4614 if (bus->bustype == SSB_BUSTYPE_PCI) {
4616 pdev = bus->host_pci; 4615 pdev = bus->host_pci;
4617 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 4616 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4617 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4618 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 4618 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4619 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4619 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013)) 4620 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
4620 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 4621 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4621 } 4622 }
diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c
index 2541c81932f0..1cb77db5c292 100644
--- a/drivers/net/wireless/b43legacy/main.c
+++ b/drivers/net/wireless/b43legacy/main.c
@@ -34,7 +34,6 @@
34#include <linux/moduleparam.h> 34#include <linux/moduleparam.h>
35#include <linux/if_arp.h> 35#include <linux/if_arp.h>
36#include <linux/etherdevice.h> 36#include <linux/etherdevice.h>
37#include <linux/version.h>
38#include <linux/firmware.h> 37#include <linux/firmware.h>
39#include <linux/wireless.h> 38#include <linux/wireless.h>
40#include <linux/workqueue.h> 39#include <linux/workqueue.h>
diff --git a/drivers/net/wireless/ipw2100.c b/drivers/net/wireless/ipw2100.c
index c6f886ec08a3..19a401c4a0dc 100644
--- a/drivers/net/wireless/ipw2100.c
+++ b/drivers/net/wireless/ipw2100.c
@@ -157,7 +157,6 @@ that only one external action is invoked at a time.
157#include <linux/stringify.h> 157#include <linux/stringify.h>
158#include <linux/tcp.h> 158#include <linux/tcp.h>
159#include <linux/types.h> 159#include <linux/types.h>
160#include <linux/version.h>
161#include <linux/time.h> 160#include <linux/time.h>
162#include <linux/firmware.h> 161#include <linux/firmware.h>
163#include <linux/acpi.h> 162#include <linux/acpi.h>
diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c
index 36e8d2f6e7b4..dcce3542d5a7 100644
--- a/drivers/net/wireless/ipw2200.c
+++ b/drivers/net/wireless/ipw2200.c
@@ -31,7 +31,6 @@
31******************************************************************************/ 31******************************************************************************/
32 32
33#include "ipw2200.h" 33#include "ipw2200.h"
34#include <linux/version.h>
35 34
36 35
37#ifndef KBUILD_EXTMOD 36#ifndef KBUILD_EXTMOD
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-led.c b/drivers/net/wireless/iwlwifi/iwl-3945-led.c
index d3336966b6b5..705c65bed9fd 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-led.c
@@ -27,7 +27,6 @@
27 27
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/version.h>
31#include <linux/init.h> 30#include <linux/init.h>
32#include <linux/pci.h> 31#include <linux/pci.h>
33#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index b3931f6135a4..3f51f3635344 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -26,7 +26,6 @@
26 26
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h> 29#include <linux/init.h>
31#include <linux/pci.h> 30#include <linux/pci.h>
32#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 22bb26985c2e..e2581229d8b2 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -26,7 +26,6 @@
26 26
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h> 29#include <linux/init.h>
31#include <linux/pci.h> 30#include <linux/pci.h>
32#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
@@ -967,7 +966,7 @@ static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
967 966
968 s = iwl4965_get_sub_band(priv, channel); 967 s = iwl4965_get_sub_band(priv, channel);
969 if (s >= EEPROM_TX_POWER_BANDS) { 968 if (s >= EEPROM_TX_POWER_BANDS) {
970 IWL_ERROR("Tx Power can not find channel %d ", channel); 969 IWL_ERROR("Tx Power can not find channel %d\n", channel);
971 return -1; 970 return -1;
972 } 971 }
973 972
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index f3d139b663e6..cbc01a00eaf4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -25,7 +25,6 @@
25 25
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/version.h>
29#include <linux/init.h> 28#include <linux/init.h>
30#include <linux/pci.h> 29#include <linux/pci.h>
31#include <linux/dma-mapping.h> 30#include <linux/dma-mapping.h>
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index ed09e48b1b61..061ffba9c884 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -29,7 +29,6 @@
29 29
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h> 32#include <linux/init.h>
34#include <linux/pci.h> 33#include <linux/pci.h>
35#include <linux/dma-mapping.h> 34#include <linux/dma-mapping.h>
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 9bd61809129f..c72f72579bea 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -28,7 +28,6 @@
28 28
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/version.h>
32#include <net/mac80211.h> 31#include <net/mac80211.h>
33 32
34struct iwl_priv; /* FIXME: remove */ 33struct iwl_priv; /* FIXME: remove */
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index bce53830b301..37155755efc5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -63,7 +63,6 @@
63 63
64#include <linux/kernel.h> 64#include <linux/kernel.h>
65#include <linux/module.h> 65#include <linux/module.h>
66#include <linux/version.h>
67#include <linux/init.h> 66#include <linux/init.h>
68 67
69#include <net/mac80211.h> 68#include <net/mac80211.h>
@@ -146,7 +145,7 @@ int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
146{ 145{
147 u32 gp = iwl_read32(priv, CSR_EEPROM_GP); 146 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
148 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { 147 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
149 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); 148 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
150 return -ENOENT; 149 return -ENOENT;
151 } 150 }
152 return 0; 151 return 0;
@@ -227,7 +226,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
227 226
228 ret = priv->cfg->ops->lib->eeprom_ops.verify_signature(priv); 227 ret = priv->cfg->ops->lib->eeprom_ops.verify_signature(priv);
229 if (ret < 0) { 228 if (ret < 0) {
230 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); 229 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
231 ret = -ENOENT; 230 ret = -ENOENT;
232 goto err; 231 goto err;
233 } 232 }
@@ -254,7 +253,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
254 } 253 }
255 254
256 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) { 255 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
257 IWL_ERROR("Time out reading EEPROM[%d]", addr); 256 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
258 ret = -ETIMEDOUT; 257 ret = -ETIMEDOUT;
259 goto done; 258 goto done;
260 } 259 }
diff --git a/drivers/net/wireless/iwlwifi/iwl-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-hcmd.c
index 6512834bb916..2eb03eea1908 100644
--- a/drivers/net/wireless/iwlwifi/iwl-hcmd.c
+++ b/drivers/net/wireless/iwlwifi/iwl-hcmd.c
@@ -28,7 +28,6 @@
28 28
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/version.h>
32#include <net/mac80211.h> 31#include <net/mac80211.h>
33 32
34#include "iwl-dev.h" /* FIXME: remove */ 33#include "iwl-dev.h" /* FIXME: remove */
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c
index cb11c4a4d691..4eee1b163cd2 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-led.c
@@ -27,7 +27,6 @@
27 27
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/version.h>
31#include <linux/init.h> 30#include <linux/init.h>
32#include <linux/pci.h> 31#include <linux/pci.h>
33#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.c b/drivers/net/wireless/iwlwifi/iwl-power.c
index 028e3053c0ca..a099c9e30e55 100644
--- a/drivers/net/wireless/iwlwifi/iwl-power.c
+++ b/drivers/net/wireless/iwlwifi/iwl-power.c
@@ -29,7 +29,6 @@
29 29
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h> 32#include <linux/init.h>
34 33
35#include <net/mac80211.h> 34#include <net/mac80211.h>
diff --git a/drivers/net/wireless/iwlwifi/iwl-rfkill.c b/drivers/net/wireless/iwlwifi/iwl-rfkill.c
index e5e5846e9f25..5d642298f04c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rfkill.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rfkill.c
@@ -27,7 +27,6 @@
27 *****************************************************************************/ 27 *****************************************************************************/
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/version.h>
31#include <linux/init.h> 30#include <linux/init.h>
32 31
33#include <net/mac80211.h> 32#include <net/mac80211.h>
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c
index 60a6e0106036..6283a3a707f5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.c
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.c
@@ -207,7 +207,7 @@ static void iwl_set_ht_add_station(struct iwl_priv *priv, u8 index,
207 case WLAN_HT_CAP_MIMO_PS_DISABLED: 207 case WLAN_HT_CAP_MIMO_PS_DISABLED:
208 break; 208 break;
209 default: 209 default:
210 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode); 210 IWL_WARNING("Invalid MIMO PS mode %d\n", mimo_ps_mode);
211 break; 211 break;
212 } 212 }
213 213
@@ -969,7 +969,7 @@ int iwl_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
969 return priv->hw_params.bcast_sta_id; 969 return priv->hw_params.bcast_sta_id;
970 970
971 default: 971 default:
972 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); 972 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
973 return priv->hw_params.bcast_sta_id; 973 return priv->hw_params.bcast_sta_id;
974 } 974 }
975} 975}
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index 4108c7c8f00f..d82823b5c8ab 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -493,7 +493,7 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
493 /* Alloc keep-warm buffer */ 493 /* Alloc keep-warm buffer */
494 ret = iwl_kw_alloc(priv); 494 ret = iwl_kw_alloc(priv);
495 if (ret) { 495 if (ret) {
496 IWL_ERROR("Keep Warm allocation failed"); 496 IWL_ERROR("Keep Warm allocation failed\n");
497 goto error_kw; 497 goto error_kw;
498 } 498 }
499 spin_lock_irqsave(&priv->lock, flags); 499 spin_lock_irqsave(&priv->lock, flags);
@@ -1463,7 +1463,7 @@ void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1463 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); 1463 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1464 1464
1465 if (scd_flow >= priv->hw_params.max_txq_num) { 1465 if (scd_flow >= priv->hw_params.max_txq_num) {
1466 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues"); 1466 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
1467 return; 1467 return;
1468 } 1468 }
1469 1469
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 444847ab1b5a..b775d5bab668 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -29,7 +29,6 @@
29 29
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h> 32#include <linux/init.h>
34#include <linux/pci.h> 33#include <linux/pci.h>
35#include <linux/dma-mapping.h> 34#include <linux/dma-mapping.h>
@@ -1558,7 +1557,7 @@ int iwl3945_eeprom_init(struct iwl3945_priv *priv)
1558 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE); 1557 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1559 1558
1560 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { 1559 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1561 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); 1560 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
1562 return -ENOENT; 1561 return -ENOENT;
1563 } 1562 }
1564 1563
@@ -1583,7 +1582,7 @@ int iwl3945_eeprom_init(struct iwl3945_priv *priv)
1583 } 1582 }
1584 1583
1585 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) { 1584 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1586 IWL_ERROR("Time out reading EEPROM[%d]", addr); 1585 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
1587 return -ETIMEDOUT; 1586 return -ETIMEDOUT;
1588 } 1587 }
1589 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); 1588 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
@@ -2507,7 +2506,7 @@ static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *h
2507 return priv->hw_setting.bcast_sta_id; 2506 return priv->hw_setting.bcast_sta_id;
2508 2507
2509 default: 2508 default:
2510 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); 2509 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
2511 return priv->hw_setting.bcast_sta_id; 2510 return priv->hw_setting.bcast_sta_id;
2512 } 2511 }
2513} 2512}
diff --git a/drivers/net/wireless/p54/p54common.c b/drivers/net/wireless/p54/p54common.c
index 83cd85e1f847..29be3dc8ee09 100644
--- a/drivers/net/wireless/p54/p54common.c
+++ b/drivers/net/wireless/p54/p54common.c
@@ -413,12 +413,12 @@ static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
413 last_addr = range->end_addr; 413 last_addr = range->end_addr;
414 __skb_unlink(entry, &priv->tx_queue); 414 __skb_unlink(entry, &priv->tx_queue);
415 memset(&info->status, 0, sizeof(info->status)); 415 memset(&info->status, 0, sizeof(info->status));
416 priv->tx_stats[skb_get_queue_mapping(skb)].len--;
417 entry_hdr = (struct p54_control_hdr *) entry->data; 416 entry_hdr = (struct p54_control_hdr *) entry->data;
418 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data; 417 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
419 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0) 418 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
420 pad = entry_data->align[0]; 419 pad = entry_data->align[0];
421 420
421 priv->tx_stats[entry_data->hw_queue - 4].len--;
422 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 422 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
423 if (!(payload->status & 0x01)) 423 if (!(payload->status & 0x01))
424 info->flags |= IEEE80211_TX_STAT_ACK; 424 info->flags |= IEEE80211_TX_STAT_ACK;
@@ -557,6 +557,7 @@ static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
557 struct p54_tx_control_allocdata *txhdr; 557 struct p54_tx_control_allocdata *txhdr;
558 size_t padding, len; 558 size_t padding, len;
559 u8 rate; 559 u8 rate;
560 u8 cts_rate = 0x20;
560 561
561 current_queue = &priv->tx_stats[skb_get_queue_mapping(skb)]; 562 current_queue = &priv->tx_stats[skb_get_queue_mapping(skb)];
562 if (unlikely(current_queue->len > current_queue->limit)) 563 if (unlikely(current_queue->len > current_queue->limit))
@@ -581,28 +582,28 @@ static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
581 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1); 582 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1);
582 hdr->retry1 = hdr->retry2 = info->control.retry_limit; 583 hdr->retry1 = hdr->retry2 = info->control.retry_limit;
583 584
584 memset(txhdr->wep_key, 0x0, 16);
585 txhdr->padding = 0;
586 txhdr->padding2 = 0;
587
588 /* TODO: add support for alternate retry TX rates */ 585 /* TODO: add support for alternate retry TX rates */
589 rate = ieee80211_get_tx_rate(dev, info)->hw_value; 586 rate = ieee80211_get_tx_rate(dev, info)->hw_value;
590 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) 587 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) {
591 rate |= 0x10; 588 rate |= 0x10;
592 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) 589 cts_rate |= 0x10;
590 }
591 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
593 rate |= 0x40; 592 rate |= 0x40;
594 else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) 593 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
594 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
595 rate |= 0x20; 595 rate |= 0x20;
596 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
597 }
596 memset(txhdr->rateset, rate, 8); 598 memset(txhdr->rateset, rate, 8);
597 txhdr->wep_key_present = 0; 599 txhdr->key_type = 0;
598 txhdr->wep_key_len = 0; 600 txhdr->key_len = 0;
599 txhdr->frame_type = cpu_to_le32(skb_get_queue_mapping(skb) + 4); 601 txhdr->hw_queue = skb_get_queue_mapping(skb) + 4;
600 txhdr->magic4 = 0; 602 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
601 txhdr->antenna = (info->antenna_sel_tx == 0) ?
602 2 : info->antenna_sel_tx - 1; 603 2 : info->antenna_sel_tx - 1;
603 txhdr->output_power = 0x7f; // HW Maximum 604 txhdr->output_power = 0x7f; // HW Maximum
604 txhdr->magic5 = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 605 txhdr->cts_rate = (info->flags & IEEE80211_TX_CTL_NO_ACK) ?
605 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23)); 606 0 : cts_rate;
606 if (padding) 607 if (padding)
607 txhdr->align[0] = padding; 608 txhdr->align[0] = padding;
608 609
@@ -836,10 +837,21 @@ static int p54_start(struct ieee80211_hw *dev)
836 struct p54_common *priv = dev->priv; 837 struct p54_common *priv = dev->priv;
837 int err; 838 int err;
838 839
840 if (!priv->cached_vdcf) {
841 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf)+
842 priv->tx_hdr_len + sizeof(struct p54_control_hdr),
843 GFP_KERNEL);
844
845 if (!priv->cached_vdcf)
846 return -ENOMEM;
847 }
848
839 err = priv->open(dev); 849 err = priv->open(dev);
840 if (!err) 850 if (!err)
841 priv->mode = IEEE80211_IF_TYPE_MNTR; 851 priv->mode = IEEE80211_IF_TYPE_MNTR;
842 852
853 p54_init_vdcf(dev);
854
843 return err; 855 return err;
844} 856}
845 857
@@ -1019,15 +1031,6 @@ struct ieee80211_hw *p54_init_common(size_t priv_data_len)
1019 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 + 1031 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
1020 sizeof(struct p54_tx_control_allocdata); 1032 sizeof(struct p54_tx_control_allocdata);
1021 1033
1022 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf) +
1023 priv->tx_hdr_len + sizeof(struct p54_control_hdr), GFP_KERNEL);
1024
1025 if (!priv->cached_vdcf) {
1026 ieee80211_free_hw(dev);
1027 return NULL;
1028 }
1029
1030 p54_init_vdcf(dev);
1031 mutex_init(&priv->conf_mutex); 1034 mutex_init(&priv->conf_mutex);
1032 1035
1033 return dev; 1036 return dev;
diff --git a/drivers/net/wireless/p54/p54common.h b/drivers/net/wireless/p54/p54common.h
index 2245fcce92dc..8db6c0e8e540 100644
--- a/drivers/net/wireless/p54/p54common.h
+++ b/drivers/net/wireless/p54/p54common.h
@@ -183,16 +183,16 @@ struct p54_frame_sent_hdr {
183 183
184struct p54_tx_control_allocdata { 184struct p54_tx_control_allocdata {
185 u8 rateset[8]; 185 u8 rateset[8];
186 u16 padding; 186 u8 unalloc0[2];
187 u8 wep_key_present; 187 u8 key_type;
188 u8 wep_key_len; 188 u8 key_len;
189 u8 wep_key[16]; 189 u8 key[16];
190 __le32 frame_type; 190 u8 hw_queue;
191 u32 padding2; 191 u8 unalloc1[9];
192 __le16 magic4; 192 u8 tx_antenna;
193 u8 antenna;
194 u8 output_power; 193 u8 output_power;
195 __le32 magic5; 194 u8 cts_rate;
195 u8 unalloc2[3];
196 u8 align[0]; 196 u8 align[0];
197} __attribute__ ((packed)); 197} __attribute__ ((packed));
198 198
diff --git a/drivers/net/wireless/p54/p54usb.c b/drivers/net/wireless/p54/p54usb.c
index 815c095ef797..cbaca23a9453 100644
--- a/drivers/net/wireless/p54/p54usb.c
+++ b/drivers/net/wireless/p54/p54usb.c
@@ -109,7 +109,17 @@ static void p54u_rx_cb(struct urb *urb)
109 urb->context = skb; 109 urb->context = skb;
110 skb_queue_tail(&priv->rx_queue, skb); 110 skb_queue_tail(&priv->rx_queue, skb);
111 } else { 111 } else {
112 if (!priv->hw_type)
113 skb_push(skb, sizeof(struct net2280_tx_hdr));
114
115 skb_reset_tail_pointer(skb);
112 skb_trim(skb, 0); 116 skb_trim(skb, 0);
117 if (urb->transfer_buffer != skb_tail_pointer(skb)) {
118 /* this should not happen */
119 WARN_ON(1);
120 urb->transfer_buffer = skb_tail_pointer(skb);
121 }
122
113 skb_queue_tail(&priv->rx_queue, skb); 123 skb_queue_tail(&priv->rx_queue, skb);
114 } 124 }
115 125
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index a4a8c57004db..ff78e52ce43c 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -173,10 +173,10 @@ struct rxdone_entry_desc {
173 * frame transmission failed due to excessive retries. 173 * frame transmission failed due to excessive retries.
174 */ 174 */
175enum txdone_entry_desc_flags { 175enum txdone_entry_desc_flags {
176 TXDONE_UNKNOWN = 1 << 0, 176 TXDONE_UNKNOWN,
177 TXDONE_SUCCESS = 1 << 1, 177 TXDONE_SUCCESS,
178 TXDONE_FAILURE = 1 << 2, 178 TXDONE_FAILURE,
179 TXDONE_EXCESSIVE_RETRY = 1 << 3, 179 TXDONE_EXCESSIVE_RETRY,
180}; 180};
181 181
182/** 182/**
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index 8d76bb2e0312..2050227ea530 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -181,6 +181,7 @@ static void rt2x00usb_interrupt_txdone(struct urb *urb)
181 * (Only indirectly by looking at the failed TX counters 181 * (Only indirectly by looking at the failed TX counters
182 * in the register). 182 * in the register).
183 */ 183 */
184 txdesc.flags = 0;
184 if (!urb->status) 185 if (!urb->status)
185 __set_bit(TXDONE_UNKNOWN, &txdesc.flags); 186 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
186 else 187 else
diff --git a/drivers/net/wireless/rtl8187_dev.c b/drivers/net/wireless/rtl8187_dev.c
index 57376fb993ed..ca5deb6244e6 100644
--- a/drivers/net/wireless/rtl8187_dev.c
+++ b/drivers/net/wireless/rtl8187_dev.c
@@ -40,6 +40,7 @@ static struct usb_device_id rtl8187_table[] __devinitdata = {
40 /* Netgear */ 40 /* Netgear */
41 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187}, 41 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
42 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187}, 42 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
43 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
43 /* HP */ 44 /* HP */
44 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187}, 45 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
45 /* Sitecom */ 46 /* Sitecom */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 15:30:11 -0500