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-rw-r--r--drivers/net/3c59x.c166
-rw-r--r--drivers/net/8139cp.c35
-rw-r--r--drivers/net/8139too.c39
-rw-r--r--drivers/net/appletalk/Kconfig2
-rw-r--r--drivers/net/b44.c27
-rw-r--r--drivers/net/bnx2.c32
-rw-r--r--drivers/net/cassini.c25
-rw-r--r--drivers/net/chelsio/sge.c2
-rw-r--r--drivers/net/declance.c7
-rw-r--r--drivers/net/dl2k.c43
-rw-r--r--drivers/net/dummy.c1
-rw-r--r--drivers/net/e1000/e1000.h13
-rw-r--r--drivers/net/e1000/e1000_ethtool.c141
-rw-r--r--drivers/net/e1000/e1000_hw.c1772
-rw-r--r--drivers/net/e1000/e1000_hw.h398
-rw-r--r--drivers/net/e1000/e1000_main.c446
-rw-r--r--drivers/net/e1000/e1000_osdep.h13
-rw-r--r--drivers/net/e1000/e1000_param.c199
-rw-r--r--drivers/net/eepro100.c6
-rw-r--r--drivers/net/epic100.c93
-rw-r--r--drivers/net/fealnx.c36
-rw-r--r--drivers/net/forcedeth.c51
-rw-r--r--drivers/net/gt96100eth.c3
-rw-r--r--drivers/net/gt96100eth.h2
-rw-r--r--drivers/net/hamachi.c16
-rw-r--r--drivers/net/hamradio/bpqether.c7
-rw-r--r--drivers/net/ifb.c1
-rw-r--r--drivers/net/irda/ali-ircc.c3
-rw-r--r--drivers/net/irda/smsc-ircc2.c2
-rw-r--r--drivers/net/ixgb/ixgb_main.c6
-rw-r--r--drivers/net/loopback.c2
-rw-r--r--drivers/net/myri10ge/myri10ge.c58
-rw-r--r--drivers/net/natsemi.c117
-rw-r--r--drivers/net/ne2k-pci.c9
-rw-r--r--drivers/net/ni5010.c52
-rw-r--r--drivers/net/ns83820.c41
-rw-r--r--drivers/net/pci-skeleton.c19
-rw-r--r--drivers/net/pcnet32.c520
-rw-r--r--drivers/net/phy/cicada.c42
-rw-r--r--drivers/net/phy/phy.c8
-rw-r--r--drivers/net/r8169.c40
-rw-r--r--drivers/net/s2io.c671
-rw-r--r--drivers/net/s2io.h15
-rw-r--r--drivers/net/sk98lin/h/xmac_ii.h2
-rw-r--r--drivers/net/skge.c5
-rw-r--r--drivers/net/skge.h4
-rw-r--r--drivers/net/sky2.c52
-rw-r--r--drivers/net/sky2.h2
-rw-r--r--drivers/net/smc91x.h18
-rw-r--r--drivers/net/spider_net.c580
-rw-r--r--drivers/net/spider_net.h73
-rw-r--r--drivers/net/starfire.c123
-rw-r--r--drivers/net/sundance.c106
-rw-r--r--drivers/net/sunhme.c9
-rw-r--r--drivers/net/sunlance.c8
-rw-r--r--drivers/net/tg3.c124
-rw-r--r--drivers/net/tulip/winbond-840.c29
-rw-r--r--drivers/net/tulip/xircom_tulip_cb.c27
-rw-r--r--drivers/net/typhoon.c4
-rw-r--r--drivers/net/via-rhine.c121
-rw-r--r--drivers/net/via-velocity.c119
-rw-r--r--drivers/net/via-velocity.h4
-rw-r--r--drivers/net/wan/Kconfig12
-rw-r--r--drivers/net/wan/Makefile1
-rw-r--r--drivers/net/wan/c101.c30
-rw-r--r--drivers/net/wan/hd6457x.c26
-rw-r--r--drivers/net/wan/hdlc_cisco.c14
-rw-r--r--drivers/net/wan/hdlc_fr.c14
-rw-r--r--drivers/net/wan/hdlc_generic.c65
-rw-r--r--drivers/net/wan/hdlc_ppp.c1
-rw-r--r--drivers/net/wan/hdlc_raw.c1
-rw-r--r--drivers/net/wan/hdlc_raw_eth.c1
-rw-r--r--drivers/net/wan/hdlc_x25.c1
-rw-r--r--drivers/net/wan/n2.c3
-rw-r--r--drivers/net/wan/wanxl.c5
-rw-r--r--drivers/net/wireless/Kconfig2
-rw-r--r--drivers/net/wireless/Makefile1
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_main.c33
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_main.h24
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_radio.c7
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_wx.c2
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_xmit.c5
-rw-r--r--drivers/net/wireless/hostap/hostap_plx.c2
-rw-r--r--drivers/net/wireless/orinoco.c4
-rw-r--r--drivers/net/wireless/spectrum_cs.c37
-rw-r--r--drivers/net/wireless/zd1201.c2
-rw-r--r--drivers/net/wireless/zd1211rw/Kconfig19
-rw-r--r--drivers/net/wireless/zd1211rw/Makefile11
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.c1615
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.h827
-rw-r--r--drivers/net/wireless/zd1211rw/zd_def.h48
-rw-r--r--drivers/net/wireless/zd1211rw/zd_ieee80211.c191
-rw-r--r--drivers/net/wireless/zd1211rw/zd_ieee80211.h85
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.c1057
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.h190
-rw-r--r--drivers/net/wireless/zd1211rw/zd_netdev.c267
-rw-r--r--drivers/net/wireless/zd1211rw/zd_netdev.h45
-rw-r--r--drivers/net/wireless/zd1211rw/zd_rf.c151
-rw-r--r--drivers/net/wireless/zd1211rw/zd_rf.h82
-rw-r--r--drivers/net/wireless/zd1211rw/zd_rf_al2230.c308
-rw-r--r--drivers/net/wireless/zd1211rw/zd_rf_rf2959.c279
-rw-r--r--drivers/net/wireless/zd1211rw/zd_types.h71
-rw-r--r--drivers/net/wireless/zd1211rw/zd_usb.c1309
-rw-r--r--drivers/net/wireless/zd1211rw/zd_usb.h240
-rw-r--r--drivers/net/wireless/zd1211rw/zd_util.c82
-rw-r--r--drivers/net/wireless/zd1211rw/zd_util.h29
-rw-r--r--drivers/net/yellowfin.c39
107 files changed, 11199 insertions, 2630 deletions
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c
index 2819de79442c..80e8ca013e44 100644
--- a/drivers/net/3c59x.c
+++ b/drivers/net/3c59x.c
@@ -17,172 +17,6 @@
17 410 Severn Ave., Suite 210 17 410 Severn Ave., Suite 210
18 Annapolis MD 21403 18 Annapolis MD 21403
19 19
20 Linux Kernel Additions:
21
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
28
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
39 by Bogdan Costescu.
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
42 insertion oops)
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
51
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
56 as in the hardware.
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
58
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
69
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
80 Donald Becker)
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
83
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
92 have one.
93 - Added 802.3x MAC-layer flow control support
94
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
104
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
115 things happen.
116
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
121
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
124
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
132
133 LK1.1.13 27 Jan 2001
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
142
143 LK1.1.14 15 Feb 2001
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
148
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
155
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
164 NICs).
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
167 clash.
168
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
171 And it has NWAY.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
175 global_full_duplex.
176
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
180
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
183
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
186*/ 20*/
187 21
188/* 22/*
diff --git a/drivers/net/8139cp.c b/drivers/net/8139cp.c
index 1959654cbec8..1428bb7715af 100644
--- a/drivers/net/8139cp.c
+++ b/drivers/net/8139cp.c
@@ -1836,9 +1836,10 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1836 1836
1837 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 1837 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1838 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) { 1838 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1839 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n", 1839 dev_err(&pdev->dev,
1840 pci_name(pdev), pdev->vendor, pdev->device, pci_rev); 1840 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1841 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n"); 1841 pdev->vendor, pdev->device, pci_rev);
1842 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1842 return -ENODEV; 1843 return -ENODEV;
1843 } 1844 }
1844 1845
@@ -1876,14 +1877,13 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1876 pciaddr = pci_resource_start(pdev, 1); 1877 pciaddr = pci_resource_start(pdev, 1);
1877 if (!pciaddr) { 1878 if (!pciaddr) {
1878 rc = -EIO; 1879 rc = -EIO;
1879 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n", 1880 dev_err(&pdev->dev, "no MMIO resource\n");
1880 pci_name(pdev));
1881 goto err_out_res; 1881 goto err_out_res;
1882 } 1882 }
1883 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) { 1883 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1884 rc = -EIO; 1884 rc = -EIO;
1885 printk(KERN_ERR PFX "MMIO resource (%llx) too small on pci dev %s\n", 1885 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1886 (unsigned long long)pci_resource_len(pdev, 1), pci_name(pdev)); 1886 (unsigned long long)pci_resource_len(pdev, 1));
1887 goto err_out_res; 1887 goto err_out_res;
1888 } 1888 }
1889 1889
@@ -1897,14 +1897,15 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1897 1897
1898 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1898 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1899 if (rc) { 1899 if (rc) {
1900 printk(KERN_ERR PFX "No usable DMA configuration, " 1900 dev_err(&pdev->dev,
1901 "aborting.\n"); 1901 "No usable DMA configuration, aborting.\n");
1902 goto err_out_res; 1902 goto err_out_res;
1903 } 1903 }
1904 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1904 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1905 if (rc) { 1905 if (rc) {
1906 printk(KERN_ERR PFX "No usable consistent DMA configuration, " 1906 dev_err(&pdev->dev,
1907 "aborting.\n"); 1907 "No usable consistent DMA configuration, "
1908 "aborting.\n");
1908 goto err_out_res; 1909 goto err_out_res;
1909 } 1910 }
1910 } 1911 }
@@ -1915,9 +1916,9 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1915 regs = ioremap(pciaddr, CP_REGS_SIZE); 1916 regs = ioremap(pciaddr, CP_REGS_SIZE);
1916 if (!regs) { 1917 if (!regs) {
1917 rc = -EIO; 1918 rc = -EIO;
1918 printk(KERN_ERR PFX "Cannot map PCI MMIO (%llx@%llx) on pci dev %s\n", 1919 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1919 (unsigned long long)pci_resource_len(pdev, 1), 1920 (unsigned long long)pci_resource_len(pdev, 1),
1920 (unsigned long long)pciaddr, pci_name(pdev)); 1921 (unsigned long long)pciaddr);
1921 goto err_out_res; 1922 goto err_out_res;
1922 } 1923 }
1923 dev->base_addr = (unsigned long) regs; 1924 dev->base_addr = (unsigned long) regs;
@@ -1986,7 +1987,8 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1986 /* enable busmastering and memory-write-invalidate */ 1987 /* enable busmastering and memory-write-invalidate */
1987 pci_set_master(pdev); 1988 pci_set_master(pdev);
1988 1989
1989 if (cp->wol_enabled) cp_set_d3_state (cp); 1990 if (cp->wol_enabled)
1991 cp_set_d3_state (cp);
1990 1992
1991 return 0; 1993 return 0;
1992 1994
@@ -2011,7 +2013,8 @@ static void cp_remove_one (struct pci_dev *pdev)
2011 BUG_ON(!dev); 2013 BUG_ON(!dev);
2012 unregister_netdev(dev); 2014 unregister_netdev(dev);
2013 iounmap(cp->regs); 2015 iounmap(cp->regs);
2014 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0); 2016 if (cp->wol_enabled)
2017 pci_set_power_state (pdev, PCI_D0);
2015 pci_release_regions(pdev); 2018 pci_release_regions(pdev);
2016 pci_clear_mwi(pdev); 2019 pci_clear_mwi(pdev);
2017 pci_disable_device(pdev); 2020 pci_disable_device(pdev);
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index 717506b2b13a..e4f4eaff7679 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -768,7 +768,7 @@ static int __devinit rtl8139_init_board (struct pci_dev *pdev,
768 /* dev and priv zeroed in alloc_etherdev */ 768 /* dev and priv zeroed in alloc_etherdev */
769 dev = alloc_etherdev (sizeof (*tp)); 769 dev = alloc_etherdev (sizeof (*tp));
770 if (dev == NULL) { 770 if (dev == NULL) {
771 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev)); 771 dev_err(&pdev->dev, "Unable to alloc new net device\n");
772 return -ENOMEM; 772 return -ENOMEM;
773 } 773 }
774 SET_MODULE_OWNER(dev); 774 SET_MODULE_OWNER(dev);
@@ -800,31 +800,31 @@ static int __devinit rtl8139_init_board (struct pci_dev *pdev,
800#ifdef USE_IO_OPS 800#ifdef USE_IO_OPS
801 /* make sure PCI base addr 0 is PIO */ 801 /* make sure PCI base addr 0 is PIO */
802 if (!(pio_flags & IORESOURCE_IO)) { 802 if (!(pio_flags & IORESOURCE_IO)) {
803 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev)); 803 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
804 rc = -ENODEV; 804 rc = -ENODEV;
805 goto err_out; 805 goto err_out;
806 } 806 }
807 /* check for weird/broken PCI region reporting */ 807 /* check for weird/broken PCI region reporting */
808 if (pio_len < RTL_MIN_IO_SIZE) { 808 if (pio_len < RTL_MIN_IO_SIZE) {
809 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev)); 809 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
810 rc = -ENODEV; 810 rc = -ENODEV;
811 goto err_out; 811 goto err_out;
812 } 812 }
813#else 813#else
814 /* make sure PCI base addr 1 is MMIO */ 814 /* make sure PCI base addr 1 is MMIO */
815 if (!(mmio_flags & IORESOURCE_MEM)) { 815 if (!(mmio_flags & IORESOURCE_MEM)) {
816 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev)); 816 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
817 rc = -ENODEV; 817 rc = -ENODEV;
818 goto err_out; 818 goto err_out;
819 } 819 }
820 if (mmio_len < RTL_MIN_IO_SIZE) { 820 if (mmio_len < RTL_MIN_IO_SIZE) {
821 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev)); 821 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
822 rc = -ENODEV; 822 rc = -ENODEV;
823 goto err_out; 823 goto err_out;
824 } 824 }
825#endif 825#endif
826 826
827 rc = pci_request_regions (pdev, "8139too"); 827 rc = pci_request_regions (pdev, DRV_NAME);
828 if (rc) 828 if (rc)
829 goto err_out; 829 goto err_out;
830 disable_dev_on_err = 1; 830 disable_dev_on_err = 1;
@@ -835,7 +835,7 @@ static int __devinit rtl8139_init_board (struct pci_dev *pdev,
835#ifdef USE_IO_OPS 835#ifdef USE_IO_OPS
836 ioaddr = ioport_map(pio_start, pio_len); 836 ioaddr = ioport_map(pio_start, pio_len);
837 if (!ioaddr) { 837 if (!ioaddr) {
838 printk (KERN_ERR PFX "%s: cannot map PIO, aborting\n", pci_name(pdev)); 838 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
839 rc = -EIO; 839 rc = -EIO;
840 goto err_out; 840 goto err_out;
841 } 841 }
@@ -846,7 +846,7 @@ static int __devinit rtl8139_init_board (struct pci_dev *pdev,
846 /* ioremap MMIO region */ 846 /* ioremap MMIO region */
847 ioaddr = pci_iomap(pdev, 1, 0); 847 ioaddr = pci_iomap(pdev, 1, 0);
848 if (ioaddr == NULL) { 848 if (ioaddr == NULL) {
849 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev)); 849 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
850 rc = -EIO; 850 rc = -EIO;
851 goto err_out; 851 goto err_out;
852 } 852 }
@@ -860,8 +860,7 @@ static int __devinit rtl8139_init_board (struct pci_dev *pdev,
860 860
861 /* check for missing/broken hardware */ 861 /* check for missing/broken hardware */
862 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 862 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
863 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n", 863 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
864 pci_name(pdev));
865 rc = -EIO; 864 rc = -EIO;
866 goto err_out; 865 goto err_out;
867 } 866 }
@@ -875,9 +874,10 @@ static int __devinit rtl8139_init_board (struct pci_dev *pdev,
875 } 874 }
876 875
877 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 876 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
878 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n", 877 dev_printk (KERN_DEBUG, &pdev->dev,
879 pci_name(pdev)); 878 "unknown chip version, assuming RTL-8139\n");
880 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig)); 879 dev_printk (KERN_DEBUG, &pdev->dev,
880 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
881 tp->chipset = 0; 881 tp->chipset = 0;
882 882
883match: 883match:
@@ -954,9 +954,11 @@ static int __devinit rtl8139_init_one (struct pci_dev *pdev,
954 954
955 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 955 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
956 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) { 956 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
957 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n", 957 dev_info(&pdev->dev,
958 pci_name(pdev), pdev->vendor, pdev->device, pci_rev); 958 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
959 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n"); 959 pdev->vendor, pdev->device, pci_rev);
960 dev_info(&pdev->dev,
961 "Use the \"8139cp\" driver for improved performance and stability.\n");
960 } 962 }
961 963
962 i = rtl8139_init_board (pdev, &dev); 964 i = rtl8139_init_board (pdev, &dev);
@@ -1707,6 +1709,7 @@ static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1707 void __iomem *ioaddr = tp->mmio_addr; 1709 void __iomem *ioaddr = tp->mmio_addr;
1708 unsigned int entry; 1710 unsigned int entry;
1709 unsigned int len = skb->len; 1711 unsigned int len = skb->len;
1712 unsigned long flags;
1710 1713
1711 /* Calculate the next Tx descriptor entry. */ 1714 /* Calculate the next Tx descriptor entry. */
1712 entry = tp->cur_tx % NUM_TX_DESC; 1715 entry = tp->cur_tx % NUM_TX_DESC;
@@ -1723,7 +1726,7 @@ static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1723 return 0; 1726 return 0;
1724 } 1727 }
1725 1728
1726 spin_lock_irq(&tp->lock); 1729 spin_lock_irqsave(&tp->lock, flags);
1727 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1730 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1728 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1731 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1729 1732
@@ -1734,7 +1737,7 @@ static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1734 1737
1735 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1738 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1736 netif_stop_queue (dev); 1739 netif_stop_queue (dev);
1737 spin_unlock_irq(&tp->lock); 1740 spin_unlock_irqrestore(&tp->lock, flags);
1738 1741
1739 if (netif_msg_tx_queued(tp)) 1742 if (netif_msg_tx_queued(tp))
1740 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n", 1743 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
diff --git a/drivers/net/appletalk/Kconfig b/drivers/net/appletalk/Kconfig
index b14e89004c3a..0a0e0cd81a23 100644
--- a/drivers/net/appletalk/Kconfig
+++ b/drivers/net/appletalk/Kconfig
@@ -29,7 +29,7 @@ config ATALK
29 even politically correct people are allowed to say Y here. 29 even politically correct people are allowed to say Y here.
30 30
31config DEV_APPLETALK 31config DEV_APPLETALK
32 bool "Appletalk interfaces support" 32 tristate "Appletalk interfaces support"
33 depends on ATALK 33 depends on ATALK
34 help 34 help
35 AppleTalk is the protocol that Apple computers can use to communicate 35 AppleTalk is the protocol that Apple computers can use to communicate
diff --git a/drivers/net/b44.c b/drivers/net/b44.c
index cd98d31dee8c..bea0fc0ede2f 100644
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -2120,13 +2120,14 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
2120 2120
2121 err = pci_enable_device(pdev); 2121 err = pci_enable_device(pdev);
2122 if (err) { 2122 if (err) {
2123 printk(KERN_ERR PFX "Cannot enable PCI device, " 2123 dev_err(&pdev->dev, "Cannot enable PCI device, "
2124 "aborting.\n"); 2124 "aborting.\n");
2125 return err; 2125 return err;
2126 } 2126 }
2127 2127
2128 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2128 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2129 printk(KERN_ERR PFX "Cannot find proper PCI device " 2129 dev_err(&pdev->dev,
2130 "Cannot find proper PCI device "
2130 "base address, aborting.\n"); 2131 "base address, aborting.\n");
2131 err = -ENODEV; 2132 err = -ENODEV;
2132 goto err_out_disable_pdev; 2133 goto err_out_disable_pdev;
@@ -2134,8 +2135,8 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
2134 2135
2135 err = pci_request_regions(pdev, DRV_MODULE_NAME); 2136 err = pci_request_regions(pdev, DRV_MODULE_NAME);
2136 if (err) { 2137 if (err) {
2137 printk(KERN_ERR PFX "Cannot obtain PCI resources, " 2138 dev_err(&pdev->dev,
2138 "aborting.\n"); 2139 "Cannot obtain PCI resources, aborting.\n");
2139 goto err_out_disable_pdev; 2140 goto err_out_disable_pdev;
2140 } 2141 }
2141 2142
@@ -2143,15 +2144,13 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
2143 2144
2144 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK); 2145 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
2145 if (err) { 2146 if (err) {
2146 printk(KERN_ERR PFX "No usable DMA configuration, " 2147 dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
2147 "aborting.\n");
2148 goto err_out_free_res; 2148 goto err_out_free_res;
2149 } 2149 }
2150 2150
2151 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK); 2151 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
2152 if (err) { 2152 if (err) {
2153 printk(KERN_ERR PFX "No usable DMA configuration, " 2153 dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
2154 "aborting.\n");
2155 goto err_out_free_res; 2154 goto err_out_free_res;
2156 } 2155 }
2157 2156
@@ -2160,7 +2159,7 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
2160 2159
2161 dev = alloc_etherdev(sizeof(*bp)); 2160 dev = alloc_etherdev(sizeof(*bp));
2162 if (!dev) { 2161 if (!dev) {
2163 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); 2162 dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
2164 err = -ENOMEM; 2163 err = -ENOMEM;
2165 goto err_out_free_res; 2164 goto err_out_free_res;
2166 } 2165 }
@@ -2181,8 +2180,7 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
2181 2180
2182 bp->regs = ioremap(b44reg_base, b44reg_len); 2181 bp->regs = ioremap(b44reg_base, b44reg_len);
2183 if (bp->regs == 0UL) { 2182 if (bp->regs == 0UL) {
2184 printk(KERN_ERR PFX "Cannot map device registers, " 2183 dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
2185 "aborting.\n");
2186 err = -ENOMEM; 2184 err = -ENOMEM;
2187 goto err_out_free_dev; 2185 goto err_out_free_dev;
2188 } 2186 }
@@ -2212,8 +2210,8 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
2212 2210
2213 err = b44_get_invariants(bp); 2211 err = b44_get_invariants(bp);
2214 if (err) { 2212 if (err) {
2215 printk(KERN_ERR PFX "Problem fetching invariants of chip, " 2213 dev_err(&pdev->dev,
2216 "aborting.\n"); 2214 "Problem fetching invariants of chip, aborting.\n");
2217 goto err_out_iounmap; 2215 goto err_out_iounmap;
2218 } 2216 }
2219 2217
@@ -2233,8 +2231,7 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
2233 2231
2234 err = register_netdev(dev); 2232 err = register_netdev(dev);
2235 if (err) { 2233 if (err) {
2236 printk(KERN_ERR PFX "Cannot register net device, " 2234 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2237 "aborting.\n");
2238 goto err_out_iounmap; 2235 goto err_out_iounmap;
2239 } 2236 }
2240 2237
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 4f4db5ae503b..db73de0d2511 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -1639,7 +1639,7 @@ bnx2_tx_int(struct bnx2 *bp)
1639 skb = tx_buf->skb; 1639 skb = tx_buf->skb;
1640#ifdef BCM_TSO 1640#ifdef BCM_TSO
1641 /* partial BD completions possible with TSO packets */ 1641 /* partial BD completions possible with TSO packets */
1642 if (skb_shinfo(skb)->gso_size) { 1642 if (skb_is_gso(skb)) {
1643 u16 last_idx, last_ring_idx; 1643 u16 last_idx, last_ring_idx;
1644 1644
1645 last_idx = sw_cons + 1645 last_idx = sw_cons +
@@ -5575,20 +5575,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5575 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 5575 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5576 rc = pci_enable_device(pdev); 5576 rc = pci_enable_device(pdev);
5577 if (rc) { 5577 if (rc) {
5578 printk(KERN_ERR PFX "Cannot enable PCI device, aborting."); 5578 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
5579 goto err_out; 5579 goto err_out;
5580 } 5580 }
5581 5581
5582 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 5582 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5583 printk(KERN_ERR PFX "Cannot find PCI device base address, " 5583 dev_err(&pdev->dev,
5584 "aborting.\n"); 5584 "Cannot find PCI device base address, aborting.\n");
5585 rc = -ENODEV; 5585 rc = -ENODEV;
5586 goto err_out_disable; 5586 goto err_out_disable;
5587 } 5587 }
5588 5588
5589 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 5589 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5590 if (rc) { 5590 if (rc) {
5591 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n"); 5591 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
5592 goto err_out_disable; 5592 goto err_out_disable;
5593 } 5593 }
5594 5594
@@ -5596,15 +5596,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5596 5596
5597 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 5597 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5598 if (bp->pm_cap == 0) { 5598 if (bp->pm_cap == 0) {
5599 printk(KERN_ERR PFX "Cannot find power management capability, " 5599 dev_err(&pdev->dev,
5600 "aborting.\n"); 5600 "Cannot find power management capability, aborting.\n");
5601 rc = -EIO; 5601 rc = -EIO;
5602 goto err_out_release; 5602 goto err_out_release;
5603 } 5603 }
5604 5604
5605 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); 5605 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5606 if (bp->pcix_cap == 0) { 5606 if (bp->pcix_cap == 0) {
5607 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n"); 5607 dev_err(&pdev->dev, "Cannot find PCIX capability, aborting.\n");
5608 rc = -EIO; 5608 rc = -EIO;
5609 goto err_out_release; 5609 goto err_out_release;
5610 } 5610 }
@@ -5612,14 +5612,14 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5612 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { 5612 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5613 bp->flags |= USING_DAC_FLAG; 5613 bp->flags |= USING_DAC_FLAG;
5614 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { 5614 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5615 printk(KERN_ERR PFX "pci_set_consistent_dma_mask " 5615 dev_err(&pdev->dev,
5616 "failed, aborting.\n"); 5616 "pci_set_consistent_dma_mask failed, aborting.\n");
5617 rc = -EIO; 5617 rc = -EIO;
5618 goto err_out_release; 5618 goto err_out_release;
5619 } 5619 }
5620 } 5620 }
5621 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { 5621 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5622 printk(KERN_ERR PFX "System does not support DMA, aborting.\n"); 5622 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
5623 rc = -EIO; 5623 rc = -EIO;
5624 goto err_out_release; 5624 goto err_out_release;
5625 } 5625 }
@@ -5639,7 +5639,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5639 bp->regview = ioremap_nocache(dev->base_addr, mem_len); 5639 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5640 5640
5641 if (!bp->regview) { 5641 if (!bp->regview) {
5642 printk(KERN_ERR PFX "Cannot map register space, aborting.\n"); 5642 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
5643 rc = -ENOMEM; 5643 rc = -ENOMEM;
5644 goto err_out_release; 5644 goto err_out_release;
5645 } 5645 }
@@ -5711,8 +5711,8 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5711 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && 5711 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5712 !(bp->flags & PCIX_FLAG)) { 5712 !(bp->flags & PCIX_FLAG)) {
5713 5713
5714 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, " 5714 dev_err(&pdev->dev,
5715 "aborting.\n"); 5715 "5706 A1 can only be used in a PCIX bus, aborting.\n");
5716 goto err_out_unmap; 5716 goto err_out_unmap;
5717 } 5717 }
5718 5718
@@ -5733,7 +5733,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5733 5733
5734 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5734 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5735 BNX2_DEV_INFO_SIGNATURE_MAGIC) { 5735 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5736 printk(KERN_ERR PFX "Firmware not running, aborting.\n"); 5736 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
5737 rc = -ENODEV; 5737 rc = -ENODEV;
5738 goto err_out_unmap; 5738 goto err_out_unmap;
5739 } 5739 }
@@ -5895,7 +5895,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5895#endif 5895#endif
5896 5896
5897 if ((rc = register_netdev(dev))) { 5897 if ((rc = register_netdev(dev))) {
5898 printk(KERN_ERR PFX "Cannot register net device\n"); 5898 dev_err(&pdev->dev, "Cannot register net device\n");
5899 if (bp->regview) 5899 if (bp->regview)
5900 iounmap(bp->regview); 5900 iounmap(bp->regview);
5901 pci_release_regions(pdev); 5901 pci_release_regions(pdev);
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index d33130f64700..a31544ccb3c4 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -4887,13 +4887,12 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
4887 4887
4888 err = pci_enable_device(pdev); 4888 err = pci_enable_device(pdev);
4889 if (err) { 4889 if (err) {
4890 printk(KERN_ERR PFX "Cannot enable PCI device, " 4890 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
4891 "aborting.\n");
4892 return err; 4891 return err;
4893 } 4892 }
4894 4893
4895 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 4894 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4896 printk(KERN_ERR PFX "Cannot find proper PCI device " 4895 dev_err(&pdev->dev, "Cannot find proper PCI device "
4897 "base address, aborting.\n"); 4896 "base address, aborting.\n");
4898 err = -ENODEV; 4897 err = -ENODEV;
4899 goto err_out_disable_pdev; 4898 goto err_out_disable_pdev;
@@ -4901,7 +4900,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
4901 4900
4902 dev = alloc_etherdev(sizeof(*cp)); 4901 dev = alloc_etherdev(sizeof(*cp));
4903 if (!dev) { 4902 if (!dev) {
4904 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); 4903 dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
4905 err = -ENOMEM; 4904 err = -ENOMEM;
4906 goto err_out_disable_pdev; 4905 goto err_out_disable_pdev;
4907 } 4906 }
@@ -4910,8 +4909,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
4910 4909
4911 err = pci_request_regions(pdev, dev->name); 4910 err = pci_request_regions(pdev, dev->name);
4912 if (err) { 4911 if (err) {
4913 printk(KERN_ERR PFX "Cannot obtain PCI resources, " 4912 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
4914 "aborting.\n");
4915 goto err_out_free_netdev; 4913 goto err_out_free_netdev;
4916 } 4914 }
4917 pci_set_master(pdev); 4915 pci_set_master(pdev);
@@ -4941,7 +4939,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
4941 if (pci_write_config_byte(pdev, 4939 if (pci_write_config_byte(pdev,
4942 PCI_CACHE_LINE_SIZE, 4940 PCI_CACHE_LINE_SIZE,
4943 cas_cacheline_size)) { 4941 cas_cacheline_size)) {
4944 printk(KERN_ERR PFX "Could not set PCI cache " 4942 dev_err(&pdev->dev, "Could not set PCI cache "
4945 "line size\n"); 4943 "line size\n");
4946 goto err_write_cacheline; 4944 goto err_write_cacheline;
4947 } 4945 }
@@ -4955,7 +4953,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
4955 err = pci_set_consistent_dma_mask(pdev, 4953 err = pci_set_consistent_dma_mask(pdev,
4956 DMA_64BIT_MASK); 4954 DMA_64BIT_MASK);
4957 if (err < 0) { 4955 if (err < 0) {
4958 printk(KERN_ERR PFX "Unable to obtain 64-bit DMA " 4956 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
4959 "for consistent allocations\n"); 4957 "for consistent allocations\n");
4960 goto err_out_free_res; 4958 goto err_out_free_res;
4961 } 4959 }
@@ -4963,7 +4961,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
4963 } else { 4961 } else {
4964 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 4962 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4965 if (err) { 4963 if (err) {
4966 printk(KERN_ERR PFX "No usable DMA configuration, " 4964 dev_err(&pdev->dev, "No usable DMA configuration, "
4967 "aborting.\n"); 4965 "aborting.\n");
4968 goto err_out_free_res; 4966 goto err_out_free_res;
4969 } 4967 }
@@ -5023,8 +5021,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
5023 /* give us access to cassini registers */ 5021 /* give us access to cassini registers */
5024 cp->regs = pci_iomap(pdev, 0, casreg_len); 5022 cp->regs = pci_iomap(pdev, 0, casreg_len);
5025 if (cp->regs == 0UL) { 5023 if (cp->regs == 0UL) {
5026 printk(KERN_ERR PFX "Cannot map device registers, " 5024 dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
5027 "aborting.\n");
5028 goto err_out_free_res; 5025 goto err_out_free_res;
5029 } 5026 }
5030 cp->casreg_len = casreg_len; 5027 cp->casreg_len = casreg_len;
@@ -5040,8 +5037,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
5040 pci_alloc_consistent(pdev, sizeof(struct cas_init_block), 5037 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5041 &cp->block_dvma); 5038 &cp->block_dvma);
5042 if (!cp->init_block) { 5039 if (!cp->init_block) {
5043 printk(KERN_ERR PFX "Cannot allocate init block, " 5040 dev_err(&pdev->dev, "Cannot allocate init block, aborting.\n");
5044 "aborting.\n");
5045 goto err_out_iounmap; 5041 goto err_out_iounmap;
5046 } 5042 }
5047 5043
@@ -5085,8 +5081,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
5085 dev->features |= NETIF_F_HIGHDMA; 5081 dev->features |= NETIF_F_HIGHDMA;
5086 5082
5087 if (register_netdev(dev)) { 5083 if (register_netdev(dev)) {
5088 printk(KERN_ERR PFX "Cannot register net device, " 5084 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5089 "aborting.\n");
5090 goto err_out_free_consistent; 5085 goto err_out_free_consistent;
5091 } 5086 }
5092 5087
diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
index 87f94d939ff8..61b3754f50ff 100644
--- a/drivers/net/chelsio/sge.c
+++ b/drivers/net/chelsio/sge.c
@@ -1417,7 +1417,7 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1417 struct cpl_tx_pkt *cpl; 1417 struct cpl_tx_pkt *cpl;
1418 1418
1419#ifdef NETIF_F_TSO 1419#ifdef NETIF_F_TSO
1420 if (skb_shinfo(skb)->gso_size) { 1420 if (skb_is_gso(skb)) {
1421 int eth_type; 1421 int eth_type;
1422 struct cpl_tx_pkt_lso *hdr; 1422 struct cpl_tx_pkt_lso *hdr;
1423 1423
diff --git a/drivers/net/declance.c b/drivers/net/declance.c
index 2038ca7e49ce..6ad5796121c8 100644
--- a/drivers/net/declance.c
+++ b/drivers/net/declance.c
@@ -703,8 +703,8 @@ static irqreturn_t lance_dma_merr_int(const int irq, void *dev_id,
703 return IRQ_HANDLED; 703 return IRQ_HANDLED;
704} 704}
705 705
706static irqreturn_t 706static irqreturn_t lance_interrupt(const int irq, void *dev_id,
707lance_interrupt(const int irq, void *dev_id, struct pt_regs *regs) 707 struct pt_regs *regs)
708{ 708{
709 struct net_device *dev = (struct net_device *) dev_id; 709 struct net_device *dev = (struct net_device *) dev_id;
710 struct lance_private *lp = netdev_priv(dev); 710 struct lance_private *lp = netdev_priv(dev);
@@ -1253,7 +1253,7 @@ static int __init dec_lance_init(const int type, const int slot)
1253 return 0; 1253 return 0;
1254 1254
1255err_out_free_dev: 1255err_out_free_dev:
1256 kfree(dev); 1256 free_netdev(dev);
1257 1257
1258err_out: 1258err_out:
1259 return ret; 1259 return ret;
@@ -1299,6 +1299,7 @@ static void __exit dec_lance_cleanup(void)
1299 while (root_lance_dev) { 1299 while (root_lance_dev) {
1300 struct net_device *dev = root_lance_dev; 1300 struct net_device *dev = root_lance_dev;
1301 struct lance_private *lp = netdev_priv(dev); 1301 struct lance_private *lp = netdev_priv(dev);
1302
1302 unregister_netdev(dev); 1303 unregister_netdev(dev);
1303#ifdef CONFIG_TC 1304#ifdef CONFIG_TC
1304 if (lp->slot >= 0) 1305 if (lp->slot >= 0)
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c
index 4b6ddb70f921..402961e68c89 100644
--- a/drivers/net/dl2k.c
+++ b/drivers/net/dl2k.c
@@ -9,49 +9,10 @@
9 the Free Software Foundation; either version 2 of the License, or 9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version. 10 (at your option) any later version.
11*/ 11*/
12/*
13 Rev Date Description
14 ==========================================================================
15 0.01 2001/05/03 Created DL2000-based linux driver
16 0.02 2001/05/21 Added VLAN and hardware checksum support.
17 1.00 2001/06/26 Added jumbo frame support.
18 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
19 1.02 2001/10/08 Supported fiber media.
20 Added flow control parameters.
21 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
22 the fiber devices.
23 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
24 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
25 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
26 Fixed tx_full flag incorrect.
27 Added tx_coalesce paramter.
28 1.07 2002/01/03 Fixed miscount of RX frame error.
29 1.08 2002/01/17 Fixed the multicast bug.
30 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
31 Added rio_timer() to watch rx buffers.
32 1.10 2002/04/16 Fixed miscount of carrier error.
33 1.11 2002/05/23 Added ISR schedule scheme
34 Fixed miscount of rx frame error for DGE-550SX.
35 Fixed VLAN bug.
36 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
37 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
38 errs) with some mainboards.
39 2. Use definition "DRV_NAME" "DRV_VERSION"
40 "DRV_RELDATE" for flexibility.
41 1.14 2002/08/14 Support ethtool.
42 1.15 2002/08/27 Changed the default media to Auto-Negotiation
43 for the fiber devices.
44 1.16 2002/09/04 More power down time for fiber devices auto-
45 negotiation.
46 Fix disconnect bug after ifup and ifdown.
47 1.17 2002/10/03 Fix RMON statistics overflow.
48 Always use I/O mapping to access eeprom,
49 avoid system freezing with some chipsets.
50 12
51*/
52#define DRV_NAME "D-Link DL2000-based linux driver" 13#define DRV_NAME "D-Link DL2000-based linux driver"
53#define DRV_VERSION "v1.17b" 14#define DRV_VERSION "v1.18"
54#define DRV_RELDATE "2006/03/10" 15#define DRV_RELDATE "2006/06/27"
55#include "dl2k.h" 16#include "dl2k.h"
56#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
57 18
diff --git a/drivers/net/dummy.c b/drivers/net/dummy.c
index 36d511729f71..2146cf74425e 100644
--- a/drivers/net/dummy.c
+++ b/drivers/net/dummy.c
@@ -132,6 +132,7 @@ static int __init dummy_init_module(void)
132 for (i = 0; i < numdummies && !err; i++) 132 for (i = 0; i < numdummies && !err; i++)
133 err = dummy_init_one(i); 133 err = dummy_init_one(i);
134 if (err) { 134 if (err) {
135 i--;
135 while (--i >= 0) 136 while (--i >= 0)
136 dummy_free_one(i); 137 dummy_free_one(i);
137 } 138 }
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index 3042d33e2d4d..d304297c496c 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -68,7 +68,6 @@
68#ifdef NETIF_F_TSO 68#ifdef NETIF_F_TSO
69#include <net/checksum.h> 69#include <net/checksum.h>
70#endif 70#endif
71#include <linux/workqueue.h>
72#include <linux/mii.h> 71#include <linux/mii.h>
73#include <linux/ethtool.h> 72#include <linux/ethtool.h>
74#include <linux/if_vlan.h> 73#include <linux/if_vlan.h>
@@ -111,6 +110,9 @@ struct e1000_adapter;
111#define E1000_MIN_RXD 80 110#define E1000_MIN_RXD 80
112#define E1000_MAX_82544_RXD 4096 111#define E1000_MAX_82544_RXD 4096
113 112
113/* this is the size past which hardware will drop packets when setting LPE=0 */
114#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
115
114/* Supported Rx Buffer Sizes */ 116/* Supported Rx Buffer Sizes */
115#define E1000_RXBUFFER_128 128 /* Used for packet split */ 117#define E1000_RXBUFFER_128 128 /* Used for packet split */
116#define E1000_RXBUFFER_256 256 /* Used for packet split */ 118#define E1000_RXBUFFER_256 256 /* Used for packet split */
@@ -143,6 +145,7 @@ struct e1000_adapter;
143 145
144#define AUTO_ALL_MODES 0 146#define AUTO_ALL_MODES 0
145#define E1000_EEPROM_82544_APM 0x0004 147#define E1000_EEPROM_82544_APM 0x0004
148#define E1000_EEPROM_ICH8_APME 0x0004
146#define E1000_EEPROM_APME 0x0400 149#define E1000_EEPROM_APME 0x0400
147 150
148#ifndef E1000_MASTER_SLAVE 151#ifndef E1000_MASTER_SLAVE
@@ -254,7 +257,6 @@ struct e1000_adapter {
254 spinlock_t tx_queue_lock; 257 spinlock_t tx_queue_lock;
255#endif 258#endif
256 atomic_t irq_sem; 259 atomic_t irq_sem;
257 struct work_struct watchdog_task;
258 struct work_struct reset_task; 260 struct work_struct reset_task;
259 uint8_t fc_autoneg; 261 uint8_t fc_autoneg;
260 262
@@ -339,8 +341,14 @@ struct e1000_adapter {
339#ifdef NETIF_F_TSO 341#ifdef NETIF_F_TSO
340 boolean_t tso_force; 342 boolean_t tso_force;
341#endif 343#endif
344 boolean_t smart_power_down; /* phy smart power down */
345 unsigned long flags;
342}; 346};
343 347
348enum e1000_state_t {
349 __E1000_DRIVER_TESTING,
350 __E1000_RESETTING,
351};
344 352
345/* e1000_main.c */ 353/* e1000_main.c */
346extern char e1000_driver_name[]; 354extern char e1000_driver_name[];
@@ -348,6 +356,7 @@ extern char e1000_driver_version[];
348int e1000_up(struct e1000_adapter *adapter); 356int e1000_up(struct e1000_adapter *adapter);
349void e1000_down(struct e1000_adapter *adapter); 357void e1000_down(struct e1000_adapter *adapter);
350void e1000_reset(struct e1000_adapter *adapter); 358void e1000_reset(struct e1000_adapter *adapter);
359void e1000_reinit_locked(struct e1000_adapter *adapter);
351int e1000_setup_all_tx_resources(struct e1000_adapter *adapter); 360int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
352void e1000_free_all_tx_resources(struct e1000_adapter *adapter); 361void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
353int e1000_setup_all_rx_resources(struct e1000_adapter *adapter); 362int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index d19664891768..88a82ba88f57 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -109,7 +109,8 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
109 SUPPORTED_1000baseT_Full| 109 SUPPORTED_1000baseT_Full|
110 SUPPORTED_Autoneg | 110 SUPPORTED_Autoneg |
111 SUPPORTED_TP); 111 SUPPORTED_TP);
112 112 if (hw->phy_type == e1000_phy_ife)
113 ecmd->supported &= ~SUPPORTED_1000baseT_Full;
113 ecmd->advertising = ADVERTISED_TP; 114 ecmd->advertising = ADVERTISED_TP;
114 115
115 if (hw->autoneg == 1) { 116 if (hw->autoneg == 1) {
@@ -203,11 +204,9 @@ e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
203 204
204 /* reset the link */ 205 /* reset the link */
205 206
206 if (netif_running(adapter->netdev)) { 207 if (netif_running(adapter->netdev))
207 e1000_down(adapter); 208 e1000_reinit_locked(adapter);
208 e1000_reset(adapter); 209 else
209 e1000_up(adapter);
210 } else
211 e1000_reset(adapter); 210 e1000_reset(adapter);
212 211
213 return 0; 212 return 0;
@@ -254,10 +253,9 @@ e1000_set_pauseparam(struct net_device *netdev,
254 hw->original_fc = hw->fc; 253 hw->original_fc = hw->fc;
255 254
256 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 255 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
257 if (netif_running(adapter->netdev)) { 256 if (netif_running(adapter->netdev))
258 e1000_down(adapter); 257 e1000_reinit_locked(adapter);
259 e1000_up(adapter); 258 else
260 } else
261 e1000_reset(adapter); 259 e1000_reset(adapter);
262 } else 260 } else
263 return ((hw->media_type == e1000_media_type_fiber) ? 261 return ((hw->media_type == e1000_media_type_fiber) ?
@@ -279,10 +277,9 @@ e1000_set_rx_csum(struct net_device *netdev, uint32_t data)
279 struct e1000_adapter *adapter = netdev_priv(netdev); 277 struct e1000_adapter *adapter = netdev_priv(netdev);
280 adapter->rx_csum = data; 278 adapter->rx_csum = data;
281 279
282 if (netif_running(netdev)) { 280 if (netif_running(netdev))
283 e1000_down(adapter); 281 e1000_reinit_locked(adapter);
284 e1000_up(adapter); 282 else
285 } else
286 e1000_reset(adapter); 283 e1000_reset(adapter);
287 return 0; 284 return 0;
288} 285}
@@ -577,6 +574,7 @@ e1000_get_drvinfo(struct net_device *netdev,
577 case e1000_82572: 574 case e1000_82572:
578 case e1000_82573: 575 case e1000_82573:
579 case e1000_80003es2lan: 576 case e1000_80003es2lan:
577 case e1000_ich8lan:
580 sprintf(firmware_version, "%d.%d-%d", 578 sprintf(firmware_version, "%d.%d-%d",
581 (eeprom_data & 0xF000) >> 12, 579 (eeprom_data & 0xF000) >> 12,
582 (eeprom_data & 0x0FF0) >> 4, 580 (eeprom_data & 0x0FF0) >> 4,
@@ -631,6 +629,9 @@ e1000_set_ringparam(struct net_device *netdev,
631 tx_ring_size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues; 629 tx_ring_size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
632 rx_ring_size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues; 630 rx_ring_size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
633 631
632 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
633 msleep(1);
634
634 if (netif_running(adapter->netdev)) 635 if (netif_running(adapter->netdev))
635 e1000_down(adapter); 636 e1000_down(adapter);
636 637
@@ -691,9 +692,11 @@ e1000_set_ringparam(struct net_device *netdev,
691 adapter->rx_ring = rx_new; 692 adapter->rx_ring = rx_new;
692 adapter->tx_ring = tx_new; 693 adapter->tx_ring = tx_new;
693 if ((err = e1000_up(adapter))) 694 if ((err = e1000_up(adapter)))
694 return err; 695 goto err_setup;
695 } 696 }
696 697
698 clear_bit(__E1000_RESETTING, &adapter->flags);
699
697 return 0; 700 return 0;
698err_setup_tx: 701err_setup_tx:
699 e1000_free_all_rx_resources(adapter); 702 e1000_free_all_rx_resources(adapter);
@@ -701,6 +704,8 @@ err_setup_rx:
701 adapter->rx_ring = rx_old; 704 adapter->rx_ring = rx_old;
702 adapter->tx_ring = tx_old; 705 adapter->tx_ring = tx_old;
703 e1000_up(adapter); 706 e1000_up(adapter);
707err_setup:
708 clear_bit(__E1000_RESETTING, &adapter->flags);
704 return err; 709 return err;
705} 710}
706 711
@@ -754,6 +759,7 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
754 toggle = 0x7FFFF3FF; 759 toggle = 0x7FFFF3FF;
755 break; 760 break;
756 case e1000_82573: 761 case e1000_82573:
762 case e1000_ich8lan:
757 toggle = 0x7FFFF033; 763 toggle = 0x7FFFF033;
758 break; 764 break;
759 default: 765 default:
@@ -773,11 +779,12 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
773 } 779 }
774 /* restore previous status */ 780 /* restore previous status */
775 E1000_WRITE_REG(&adapter->hw, STATUS, before); 781 E1000_WRITE_REG(&adapter->hw, STATUS, before);
776 782 if (adapter->hw.mac_type != e1000_ich8lan) {
777 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); 783 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
778 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); 784 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
779 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); 785 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
780 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); 786 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
787 }
781 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); 788 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
782 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); 789 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
783 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF); 790 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
@@ -790,20 +797,22 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
790 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF); 797 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
791 798
792 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); 799 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
793 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0x003FFFFB); 800 before = (adapter->hw.mac_type == e1000_ich8lan ?
801 0x06C3B33E : 0x06DFB3FE);
802 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
794 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); 803 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
795 804
796 if (adapter->hw.mac_type >= e1000_82543) { 805 if (adapter->hw.mac_type >= e1000_82543) {
797 806
798 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0xFFFFFFFF); 807 REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
799 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 808 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
800 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF); 809 if (adapter->hw.mac_type != e1000_ich8lan)
810 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
801 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 811 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
802 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); 812 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
803 813 value = (adapter->hw.mac_type == e1000_ich8lan ?
804 for (i = 0; i < E1000_RAR_ENTRIES; i++) { 814 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
805 REG_PATTERN_TEST(RA + ((i << 1) << 2), 0xFFFFFFFF, 815 for (i = 0; i < value; i++) {
806 0xFFFFFFFF);
807 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, 816 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
808 0xFFFFFFFF); 817 0xFFFFFFFF);
809 } 818 }
@@ -817,7 +826,9 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
817 826
818 } 827 }
819 828
820 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 829 value = (adapter->hw.mac_type == e1000_ich8lan ?
830 E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE);
831 for (i = 0; i < value; i++)
821 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF); 832 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
822 833
823 *data = 0; 834 *data = 0;
@@ -889,6 +900,8 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
889 /* Test each interrupt */ 900 /* Test each interrupt */
890 for (; i < 10; i++) { 901 for (; i < 10; i++) {
891 902
903 if (adapter->hw.mac_type == e1000_ich8lan && i == 8)
904 continue;
892 /* Interrupt to test */ 905 /* Interrupt to test */
893 mask = 1 << i; 906 mask = 1 << i;
894 907
@@ -1246,18 +1259,33 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1246 } else if (adapter->hw.phy_type == e1000_phy_gg82563) { 1259 } else if (adapter->hw.phy_type == e1000_phy_gg82563) {
1247 e1000_write_phy_reg(&adapter->hw, 1260 e1000_write_phy_reg(&adapter->hw,
1248 GG82563_PHY_KMRN_MODE_CTRL, 1261 GG82563_PHY_KMRN_MODE_CTRL,
1249 0x1CE); 1262 0x1CC);
1250 } 1263 }
1251 /* force 1000, set loopback */
1252 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1253 1264
1254 /* Now set up the MAC to the same speed/duplex as the PHY. */
1255 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL); 1265 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1256 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1266
1257 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1267 if (adapter->hw.phy_type == e1000_phy_ife) {
1258 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1268 /* force 100, set loopback */
1259 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1269 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x6100);
1260 E1000_CTRL_FD); /* Force Duplex to FULL */ 1270
1271 /* Now set up the MAC to the same speed/duplex as the PHY. */
1272 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1273 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1274 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1275 E1000_CTRL_SPD_100 |/* Force Speed to 100 */
1276 E1000_CTRL_FD); /* Force Duplex to FULL */
1277 } else {
1278 /* force 1000, set loopback */
1279 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1280
1281 /* Now set up the MAC to the same speed/duplex as the PHY. */
1282 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1283 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1284 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1285 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1286 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1287 E1000_CTRL_FD); /* Force Duplex to FULL */
1288 }
1261 1289
1262 if (adapter->hw.media_type == e1000_media_type_copper && 1290 if (adapter->hw.media_type == e1000_media_type_copper &&
1263 adapter->hw.phy_type == e1000_phy_m88) { 1291 adapter->hw.phy_type == e1000_phy_m88) {
@@ -1317,6 +1345,7 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
1317 case e1000_82572: 1345 case e1000_82572:
1318 case e1000_82573: 1346 case e1000_82573:
1319 case e1000_80003es2lan: 1347 case e1000_80003es2lan:
1348 case e1000_ich8lan:
1320 return e1000_integrated_phy_loopback(adapter); 1349 return e1000_integrated_phy_loopback(adapter);
1321 break; 1350 break;
1322 1351
@@ -1568,6 +1597,7 @@ e1000_diag_test(struct net_device *netdev,
1568 struct e1000_adapter *adapter = netdev_priv(netdev); 1597 struct e1000_adapter *adapter = netdev_priv(netdev);
1569 boolean_t if_running = netif_running(netdev); 1598 boolean_t if_running = netif_running(netdev);
1570 1599
1600 set_bit(__E1000_DRIVER_TESTING, &adapter->flags);
1571 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1601 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1572 /* Offline tests */ 1602 /* Offline tests */
1573 1603
@@ -1582,7 +1612,8 @@ e1000_diag_test(struct net_device *netdev,
1582 eth_test->flags |= ETH_TEST_FL_FAILED; 1612 eth_test->flags |= ETH_TEST_FL_FAILED;
1583 1613
1584 if (if_running) 1614 if (if_running)
1585 e1000_down(adapter); 1615 /* indicate we're in test mode */
1616 dev_close(netdev);
1586 else 1617 else
1587 e1000_reset(adapter); 1618 e1000_reset(adapter);
1588 1619
@@ -1607,8 +1638,9 @@ e1000_diag_test(struct net_device *netdev,
1607 adapter->hw.autoneg = autoneg; 1638 adapter->hw.autoneg = autoneg;
1608 1639
1609 e1000_reset(adapter); 1640 e1000_reset(adapter);
1641 clear_bit(__E1000_DRIVER_TESTING, &adapter->flags);
1610 if (if_running) 1642 if (if_running)
1611 e1000_up(adapter); 1643 dev_open(netdev);
1612 } else { 1644 } else {
1613 /* Online tests */ 1645 /* Online tests */
1614 if (e1000_link_test(adapter, &data[4])) 1646 if (e1000_link_test(adapter, &data[4]))
@@ -1619,6 +1651,8 @@ e1000_diag_test(struct net_device *netdev,
1619 data[1] = 0; 1651 data[1] = 0;
1620 data[2] = 0; 1652 data[2] = 0;
1621 data[3] = 0; 1653 data[3] = 0;
1654
1655 clear_bit(__E1000_DRIVER_TESTING, &adapter->flags);
1622 } 1656 }
1623 msleep_interruptible(4 * 1000); 1657 msleep_interruptible(4 * 1000);
1624} 1658}
@@ -1778,21 +1812,18 @@ e1000_phys_id(struct net_device *netdev, uint32_t data)
1778 mod_timer(&adapter->blink_timer, jiffies); 1812 mod_timer(&adapter->blink_timer, jiffies);
1779 msleep_interruptible(data * 1000); 1813 msleep_interruptible(data * 1000);
1780 del_timer_sync(&adapter->blink_timer); 1814 del_timer_sync(&adapter->blink_timer);
1781 } else if (adapter->hw.mac_type < e1000_82573) { 1815 } else if (adapter->hw.phy_type == e1000_phy_ife) {
1782 E1000_WRITE_REG(&adapter->hw, LEDCTL, 1816 if (!adapter->blink_timer.function) {
1783 (E1000_LEDCTL_LED2_BLINK_RATE | 1817 init_timer(&adapter->blink_timer);
1784 E1000_LEDCTL_LED0_BLINK | E1000_LEDCTL_LED2_BLINK | 1818 adapter->blink_timer.function = e1000_led_blink_callback;
1785 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED2_MODE_SHIFT) | 1819 adapter->blink_timer.data = (unsigned long) adapter;
1786 (E1000_LEDCTL_MODE_LINK_ACTIVITY << E1000_LEDCTL_LED0_MODE_SHIFT) | 1820 }
1787 (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED1_MODE_SHIFT))); 1821 mod_timer(&adapter->blink_timer, jiffies);
1788 msleep_interruptible(data * 1000); 1822 msleep_interruptible(data * 1000);
1823 del_timer_sync(&adapter->blink_timer);
1824 e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
1789 } else { 1825 } else {
1790 E1000_WRITE_REG(&adapter->hw, LEDCTL, 1826 e1000_blink_led_start(&adapter->hw);
1791 (E1000_LEDCTL_LED2_BLINK_RATE |
1792 E1000_LEDCTL_LED1_BLINK | E1000_LEDCTL_LED2_BLINK |
1793 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED2_MODE_SHIFT) |
1794 (E1000_LEDCTL_MODE_LINK_ACTIVITY << E1000_LEDCTL_LED1_MODE_SHIFT) |
1795 (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT)));
1796 msleep_interruptible(data * 1000); 1827 msleep_interruptible(data * 1000);
1797 } 1828 }
1798 1829
@@ -1807,10 +1838,8 @@ static int
1807e1000_nway_reset(struct net_device *netdev) 1838e1000_nway_reset(struct net_device *netdev)
1808{ 1839{
1809 struct e1000_adapter *adapter = netdev_priv(netdev); 1840 struct e1000_adapter *adapter = netdev_priv(netdev);
1810 if (netif_running(netdev)) { 1841 if (netif_running(netdev))
1811 e1000_down(adapter); 1842 e1000_reinit_locked(adapter);
1812 e1000_up(adapter);
1813 }
1814 return 0; 1843 return 0;
1815} 1844}
1816 1845
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 3959039b16ec..583518ae49ce 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -101,7 +101,8 @@ static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 101
102#define E1000_WRITE_REG_IO(a, reg, val) \ 102#define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val) 103 e1000_write_reg_io((a), E1000_##reg, val)
104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw); 104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
105 uint16_t duplex);
105static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 106static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
106 107
107/* IGP cable length table */ 108/* IGP cable length table */
@@ -156,6 +157,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
156 hw->phy_type = e1000_phy_igp; 157 hw->phy_type = e1000_phy_igp;
157 break; 158 break;
158 } 159 }
160 case IGP03E1000_E_PHY_ID:
161 hw->phy_type = e1000_phy_igp_3;
162 break;
163 case IFE_E_PHY_ID:
164 case IFE_PLUS_E_PHY_ID:
165 case IFE_C_E_PHY_ID:
166 hw->phy_type = e1000_phy_ife;
167 break;
159 case GG82563_E_PHY_ID: 168 case GG82563_E_PHY_ID:
160 if (hw->mac_type == e1000_80003es2lan) { 169 if (hw->mac_type == e1000_80003es2lan) {
161 hw->phy_type = e1000_phy_gg82563; 170 hw->phy_type = e1000_phy_gg82563;
@@ -332,6 +341,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
332 break; 341 break;
333 case E1000_DEV_ID_82541EI: 342 case E1000_DEV_ID_82541EI:
334 case E1000_DEV_ID_82541EI_MOBILE: 343 case E1000_DEV_ID_82541EI_MOBILE:
344 case E1000_DEV_ID_82541ER_LOM:
335 hw->mac_type = e1000_82541; 345 hw->mac_type = e1000_82541;
336 break; 346 break;
337 case E1000_DEV_ID_82541ER: 347 case E1000_DEV_ID_82541ER:
@@ -341,6 +351,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
341 hw->mac_type = e1000_82541_rev_2; 351 hw->mac_type = e1000_82541_rev_2;
342 break; 352 break;
343 case E1000_DEV_ID_82547EI: 353 case E1000_DEV_ID_82547EI:
354 case E1000_DEV_ID_82547EI_MOBILE:
344 hw->mac_type = e1000_82547; 355 hw->mac_type = e1000_82547;
345 break; 356 break;
346 case E1000_DEV_ID_82547GI: 357 case E1000_DEV_ID_82547GI:
@@ -354,6 +365,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
354 case E1000_DEV_ID_82572EI_COPPER: 365 case E1000_DEV_ID_82572EI_COPPER:
355 case E1000_DEV_ID_82572EI_FIBER: 366 case E1000_DEV_ID_82572EI_FIBER:
356 case E1000_DEV_ID_82572EI_SERDES: 367 case E1000_DEV_ID_82572EI_SERDES:
368 case E1000_DEV_ID_82572EI:
357 hw->mac_type = e1000_82572; 369 hw->mac_type = e1000_82572;
358 break; 370 break;
359 case E1000_DEV_ID_82573E: 371 case E1000_DEV_ID_82573E:
@@ -361,16 +373,29 @@ e1000_set_mac_type(struct e1000_hw *hw)
361 case E1000_DEV_ID_82573L: 373 case E1000_DEV_ID_82573L:
362 hw->mac_type = e1000_82573; 374 hw->mac_type = e1000_82573;
363 break; 375 break;
376 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
377 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
364 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 378 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
365 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 379 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
366 hw->mac_type = e1000_80003es2lan; 380 hw->mac_type = e1000_80003es2lan;
367 break; 381 break;
382 case E1000_DEV_ID_ICH8_IGP_M_AMT:
383 case E1000_DEV_ID_ICH8_IGP_AMT:
384 case E1000_DEV_ID_ICH8_IGP_C:
385 case E1000_DEV_ID_ICH8_IFE:
386 case E1000_DEV_ID_ICH8_IGP_M:
387 hw->mac_type = e1000_ich8lan;
388 break;
368 default: 389 default:
369 /* Should never have loaded on this device */ 390 /* Should never have loaded on this device */
370 return -E1000_ERR_MAC_TYPE; 391 return -E1000_ERR_MAC_TYPE;
371 } 392 }
372 393
373 switch(hw->mac_type) { 394 switch(hw->mac_type) {
395 case e1000_ich8lan:
396 hw->swfwhw_semaphore_present = TRUE;
397 hw->asf_firmware_present = TRUE;
398 break;
374 case e1000_80003es2lan: 399 case e1000_80003es2lan:
375 hw->swfw_sync_present = TRUE; 400 hw->swfw_sync_present = TRUE;
376 /* fall through */ 401 /* fall through */
@@ -423,6 +448,7 @@ e1000_set_media_type(struct e1000_hw *hw)
423 case e1000_82542_rev2_1: 448 case e1000_82542_rev2_1:
424 hw->media_type = e1000_media_type_fiber; 449 hw->media_type = e1000_media_type_fiber;
425 break; 450 break;
451 case e1000_ich8lan:
426 case e1000_82573: 452 case e1000_82573:
427 /* The STATUS_TBIMODE bit is reserved or reused for the this 453 /* The STATUS_TBIMODE bit is reserved or reused for the this
428 * device. 454 * device.
@@ -527,6 +553,14 @@ e1000_reset_hw(struct e1000_hw *hw)
527 } while(timeout); 553 } while(timeout);
528 } 554 }
529 555
556 /* Workaround for ICH8 bit corruption issue in FIFO memory */
557 if (hw->mac_type == e1000_ich8lan) {
558 /* Set Tx and Rx buffer allocation to 8k apiece. */
559 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
560 /* Set Packet Buffer Size to 16k. */
561 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
562 }
563
530 /* Issue a global reset to the MAC. This will reset the chip's 564 /* Issue a global reset to the MAC. This will reset the chip's
531 * transmit, receive, DMA, and link units. It will not effect 565 * transmit, receive, DMA, and link units. It will not effect
532 * the current PCI configuration. The global reset bit is self- 566 * the current PCI configuration. The global reset bit is self-
@@ -550,6 +584,20 @@ e1000_reset_hw(struct e1000_hw *hw)
550 /* Reset is performed on a shadow of the control register */ 584 /* Reset is performed on a shadow of the control register */
551 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 585 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
552 break; 586 break;
587 case e1000_ich8lan:
588 if (!hw->phy_reset_disable &&
589 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
590 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
591 * at the same time to make sure the interface between
592 * MAC and the external PHY is reset.
593 */
594 ctrl |= E1000_CTRL_PHY_RST;
595 }
596
597 e1000_get_software_flag(hw);
598 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
599 msec_delay(5);
600 break;
553 default: 601 default:
554 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 602 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
555 break; 603 break;
@@ -591,6 +639,7 @@ e1000_reset_hw(struct e1000_hw *hw)
591 /* fall through */ 639 /* fall through */
592 case e1000_82571: 640 case e1000_82571:
593 case e1000_82572: 641 case e1000_82572:
642 case e1000_ich8lan:
594 case e1000_80003es2lan: 643 case e1000_80003es2lan:
595 ret_val = e1000_get_auto_rd_done(hw); 644 ret_val = e1000_get_auto_rd_done(hw);
596 if(ret_val) 645 if(ret_val)
@@ -633,6 +682,12 @@ e1000_reset_hw(struct e1000_hw *hw)
633 e1000_pci_set_mwi(hw); 682 e1000_pci_set_mwi(hw);
634 } 683 }
635 684
685 if (hw->mac_type == e1000_ich8lan) {
686 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
687 kab |= E1000_KABGTXD_BGSQLBIAS;
688 E1000_WRITE_REG(hw, KABGTXD, kab);
689 }
690
636 return E1000_SUCCESS; 691 return E1000_SUCCESS;
637} 692}
638 693
@@ -675,9 +730,12 @@ e1000_init_hw(struct e1000_hw *hw)
675 730
676 /* Disabling VLAN filtering. */ 731 /* Disabling VLAN filtering. */
677 DEBUGOUT("Initializing the IEEE VLAN\n"); 732 DEBUGOUT("Initializing the IEEE VLAN\n");
678 if (hw->mac_type < e1000_82545_rev_3) 733 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
679 E1000_WRITE_REG(hw, VET, 0); 734 if (hw->mac_type != e1000_ich8lan) {
680 e1000_clear_vfta(hw); 735 if (hw->mac_type < e1000_82545_rev_3)
736 E1000_WRITE_REG(hw, VET, 0);
737 e1000_clear_vfta(hw);
738 }
681 739
682 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 740 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
683 if(hw->mac_type == e1000_82542_rev2_0) { 741 if(hw->mac_type == e1000_82542_rev2_0) {
@@ -705,8 +763,14 @@ e1000_init_hw(struct e1000_hw *hw)
705 /* Zero out the Multicast HASH table */ 763 /* Zero out the Multicast HASH table */
706 DEBUGOUT("Zeroing the MTA\n"); 764 DEBUGOUT("Zeroing the MTA\n");
707 mta_size = E1000_MC_TBL_SIZE; 765 mta_size = E1000_MC_TBL_SIZE;
708 for(i = 0; i < mta_size; i++) 766 if (hw->mac_type == e1000_ich8lan)
767 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
768 for(i = 0; i < mta_size; i++) {
709 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 769 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
770 /* use write flush to prevent Memory Write Block (MWB) from
771 * occuring when accessing our register space */
772 E1000_WRITE_FLUSH(hw);
773 }
710 774
711 /* Set the PCI priority bit correctly in the CTRL register. This 775 /* Set the PCI priority bit correctly in the CTRL register. This
712 * determines if the adapter gives priority to receives, or if it 776 * determines if the adapter gives priority to receives, or if it
@@ -744,6 +808,10 @@ e1000_init_hw(struct e1000_hw *hw)
744 break; 808 break;
745 } 809 }
746 810
811 /* More time needed for PHY to initialize */
812 if (hw->mac_type == e1000_ich8lan)
813 msec_delay(15);
814
747 /* Call a subroutine to configure the link and setup flow control. */ 815 /* Call a subroutine to configure the link and setup flow control. */
748 ret_val = e1000_setup_link(hw); 816 ret_val = e1000_setup_link(hw);
749 817
@@ -757,6 +825,7 @@ e1000_init_hw(struct e1000_hw *hw)
757 case e1000_82571: 825 case e1000_82571:
758 case e1000_82572: 826 case e1000_82572:
759 case e1000_82573: 827 case e1000_82573:
828 case e1000_ich8lan:
760 case e1000_80003es2lan: 829 case e1000_80003es2lan:
761 ctrl |= E1000_TXDCTL_COUNT_DESC; 830 ctrl |= E1000_TXDCTL_COUNT_DESC;
762 break; 831 break;
@@ -795,6 +864,7 @@ e1000_init_hw(struct e1000_hw *hw)
795 /* Fall through */ 864 /* Fall through */
796 case e1000_82571: 865 case e1000_82571:
797 case e1000_82572: 866 case e1000_82572:
867 case e1000_ich8lan:
798 ctrl = E1000_READ_REG(hw, TXDCTL1); 868 ctrl = E1000_READ_REG(hw, TXDCTL1);
799 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 869 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
800 if(hw->mac_type >= e1000_82571) 870 if(hw->mac_type >= e1000_82571)
@@ -818,6 +888,11 @@ e1000_init_hw(struct e1000_hw *hw)
818 */ 888 */
819 e1000_clear_hw_cntrs(hw); 889 e1000_clear_hw_cntrs(hw);
820 890
891 /* ICH8 No-snoop bits are opposite polarity.
892 * Set to snoop by default after reset. */
893 if (hw->mac_type == e1000_ich8lan)
894 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
895
821 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 896 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
822 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 897 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
823 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 898 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
@@ -905,6 +980,7 @@ e1000_setup_link(struct e1000_hw *hw)
905 */ 980 */
906 if (hw->fc == e1000_fc_default) { 981 if (hw->fc == e1000_fc_default) {
907 switch (hw->mac_type) { 982 switch (hw->mac_type) {
983 case e1000_ich8lan:
908 case e1000_82573: 984 case e1000_82573:
909 hw->fc = e1000_fc_full; 985 hw->fc = e1000_fc_full;
910 break; 986 break;
@@ -971,9 +1047,12 @@ e1000_setup_link(struct e1000_hw *hw)
971 */ 1047 */
972 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1048 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
973 1049
974 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1050 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
975 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1051 if (hw->mac_type != e1000_ich8lan) {
976 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1052 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1053 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1054 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1055 }
977 1056
978 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1057 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
979 1058
@@ -1237,12 +1316,13 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1237 1316
1238 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1317 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1239 msec_delay(15); 1318 msec_delay(15);
1240 1319 if (hw->mac_type != e1000_ich8lan) {
1241 /* Configure activity LED after PHY reset */ 1320 /* Configure activity LED after PHY reset */
1242 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1321 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1243 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1322 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1244 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1323 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1245 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1324 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1325 }
1246 1326
1247 /* disable lplu d3 during driver init */ 1327 /* disable lplu d3 during driver init */
1248 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1328 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
@@ -1478,8 +1558,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1478 if (ret_val) 1558 if (ret_val)
1479 return ret_val; 1559 return ret_val;
1480 1560
1481 /* Enable Pass False Carrier on the PHY */ 1561 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1482 phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1483 1562
1484 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1563 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1485 phy_data); 1564 phy_data);
@@ -1561,28 +1640,40 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1561 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1640 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1562 if(hw->disable_polarity_correction == 1) 1641 if(hw->disable_polarity_correction == 1)
1563 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1642 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1564 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1643 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1565 if(ret_val) 1644 if (ret_val)
1566 return ret_val;
1567
1568 /* Force TX_CLK in the Extended PHY Specific Control Register
1569 * to 25MHz clock.
1570 */
1571 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1572 if(ret_val)
1573 return ret_val; 1645 return ret_val;
1574 1646
1575 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1576
1577 if (hw->phy_revision < M88E1011_I_REV_4) { 1647 if (hw->phy_revision < M88E1011_I_REV_4) {
1578 /* Configure Master and Slave downshift values */ 1648 /* Force TX_CLK in the Extended PHY Specific Control Register
1579 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1649 * to 25MHz clock.
1650 */
1651 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1652 if (ret_val)
1653 return ret_val;
1654
1655 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1656
1657 if ((hw->phy_revision == E1000_REVISION_2) &&
1658 (hw->phy_id == M88E1111_I_PHY_ID)) {
1659 /* Vidalia Phy, set the downshift counter to 5x */
1660 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1661 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1662 ret_val = e1000_write_phy_reg(hw,
1663 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1664 if (ret_val)
1665 return ret_val;
1666 } else {
1667 /* Configure Master and Slave downshift values */
1668 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1580 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1669 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1581 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1670 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1582 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1671 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1583 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1672 ret_val = e1000_write_phy_reg(hw,
1584 if(ret_val) 1673 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1585 return ret_val; 1674 if (ret_val)
1675 return ret_val;
1676 }
1586 } 1677 }
1587 1678
1588 /* SW Reset the PHY so all changes take effect */ 1679 /* SW Reset the PHY so all changes take effect */
@@ -1620,6 +1711,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1620 if(hw->autoneg_advertised == 0) 1711 if(hw->autoneg_advertised == 0)
1621 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1712 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1622 1713
1714 /* IFE phy only supports 10/100 */
1715 if (hw->phy_type == e1000_phy_ife)
1716 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1717
1623 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1718 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1624 ret_val = e1000_phy_setup_autoneg(hw); 1719 ret_val = e1000_phy_setup_autoneg(hw);
1625 if(ret_val) { 1720 if(ret_val) {
@@ -1717,6 +1812,26 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1717 1812
1718 DEBUGFUNC("e1000_setup_copper_link"); 1813 DEBUGFUNC("e1000_setup_copper_link");
1719 1814
1815 switch (hw->mac_type) {
1816 case e1000_80003es2lan:
1817 case e1000_ich8lan:
1818 /* Set the mac to wait the maximum time between each
1819 * iteration and increase the max iterations when
1820 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1821 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1822 if (ret_val)
1823 return ret_val;
1824 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1825 if (ret_val)
1826 return ret_val;
1827 reg_data |= 0x3F;
1828 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1829 if (ret_val)
1830 return ret_val;
1831 default:
1832 break;
1833 }
1834
1720 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1835 /* Check if it is a valid PHY and set PHY mode if necessary. */
1721 ret_val = e1000_copper_link_preconfig(hw); 1836 ret_val = e1000_copper_link_preconfig(hw);
1722 if(ret_val) 1837 if(ret_val)
@@ -1724,10 +1839,8 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1724 1839
1725 switch (hw->mac_type) { 1840 switch (hw->mac_type) {
1726 case e1000_80003es2lan: 1841 case e1000_80003es2lan:
1727 ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1842 /* Kumeran registers are written-only */
1728 &reg_data); 1843 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1729 if (ret_val)
1730 return ret_val;
1731 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 1844 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1732 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1845 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1733 reg_data); 1846 reg_data);
@@ -1739,6 +1852,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1739 } 1852 }
1740 1853
1741 if (hw->phy_type == e1000_phy_igp || 1854 if (hw->phy_type == e1000_phy_igp ||
1855 hw->phy_type == e1000_phy_igp_3 ||
1742 hw->phy_type == e1000_phy_igp_2) { 1856 hw->phy_type == e1000_phy_igp_2) {
1743 ret_val = e1000_copper_link_igp_setup(hw); 1857 ret_val = e1000_copper_link_igp_setup(hw);
1744 if(ret_val) 1858 if(ret_val)
@@ -1803,7 +1917,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1803* hw - Struct containing variables accessed by shared code 1917* hw - Struct containing variables accessed by shared code
1804******************************************************************************/ 1918******************************************************************************/
1805static int32_t 1919static int32_t
1806e1000_configure_kmrn_for_10_100(struct e1000_hw *hw) 1920e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1807{ 1921{
1808 int32_t ret_val = E1000_SUCCESS; 1922 int32_t ret_val = E1000_SUCCESS;
1809 uint32_t tipg; 1923 uint32_t tipg;
@@ -1823,6 +1937,18 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw)
1823 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 1937 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1824 E1000_WRITE_REG(hw, TIPG, tipg); 1938 E1000_WRITE_REG(hw, TIPG, tipg);
1825 1939
1940 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1941
1942 if (ret_val)
1943 return ret_val;
1944
1945 if (duplex == HALF_DUPLEX)
1946 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1947 else
1948 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1949
1950 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1951
1826 return ret_val; 1952 return ret_val;
1827} 1953}
1828 1954
@@ -1847,6 +1973,14 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1847 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1973 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1848 E1000_WRITE_REG(hw, TIPG, tipg); 1974 E1000_WRITE_REG(hw, TIPG, tipg);
1849 1975
1976 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1977
1978 if (ret_val)
1979 return ret_val;
1980
1981 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1982 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1983
1850 return ret_val; 1984 return ret_val;
1851} 1985}
1852 1986
@@ -1869,10 +2003,13 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1869 if(ret_val) 2003 if(ret_val)
1870 return ret_val; 2004 return ret_val;
1871 2005
1872 /* Read the MII 1000Base-T Control Register (Address 9). */ 2006 if (hw->phy_type != e1000_phy_ife) {
1873 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 2007 /* Read the MII 1000Base-T Control Register (Address 9). */
1874 if(ret_val) 2008 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1875 return ret_val; 2009 if (ret_val)
2010 return ret_val;
2011 } else
2012 mii_1000t_ctrl_reg=0;
1876 2013
1877 /* Need to parse both autoneg_advertised and fc and set up 2014 /* Need to parse both autoneg_advertised and fc and set up
1878 * the appropriate PHY registers. First we will parse for 2015 * the appropriate PHY registers. First we will parse for
@@ -1923,6 +2060,9 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1923 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2060 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1924 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2061 DEBUGOUT("Advertise 1000mb Full duplex\n");
1925 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2062 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2063 if (hw->phy_type == e1000_phy_ife) {
2064 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2065 }
1926 } 2066 }
1927 2067
1928 /* Check for a software override of the flow control settings, and 2068 /* Check for a software override of the flow control settings, and
@@ -1984,9 +2124,11 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1984 2124
1985 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2125 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1986 2126
1987 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 2127 if (hw->phy_type != e1000_phy_ife) {
1988 if(ret_val) 2128 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1989 return ret_val; 2129 if (ret_val)
2130 return ret_val;
2131 }
1990 2132
1991 return E1000_SUCCESS; 2133 return E1000_SUCCESS;
1992} 2134}
@@ -2089,6 +2231,18 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2089 2231
2090 /* Need to reset the PHY or these changes will be ignored */ 2232 /* Need to reset the PHY or these changes will be ignored */
2091 mii_ctrl_reg |= MII_CR_RESET; 2233 mii_ctrl_reg |= MII_CR_RESET;
2234 /* Disable MDI-X support for 10/100 */
2235 } else if (hw->phy_type == e1000_phy_ife) {
2236 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2237 if (ret_val)
2238 return ret_val;
2239
2240 phy_data &= ~IFE_PMC_AUTO_MDIX;
2241 phy_data &= ~IFE_PMC_FORCE_MDIX;
2242
2243 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2244 if (ret_val)
2245 return ret_val;
2092 } else { 2246 } else {
2093 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2247 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2094 * forced whenever speed or duplex are forced. 2248 * forced whenever speed or duplex are forced.
@@ -2721,8 +2875,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2721 */ 2875 */
2722 if(hw->tbi_compatibility_en) { 2876 if(hw->tbi_compatibility_en) {
2723 uint16_t speed, duplex; 2877 uint16_t speed, duplex;
2724 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2878 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2725 if(speed != SPEED_1000) { 2879 if (ret_val) {
2880 DEBUGOUT("Error getting link speed and duplex\n");
2881 return ret_val;
2882 }
2883 if (speed != SPEED_1000) {
2726 /* If link speed is not set to gigabit speed, we do not need 2884 /* If link speed is not set to gigabit speed, we do not need
2727 * to enable TBI compatibility. 2885 * to enable TBI compatibility.
2728 */ 2886 */
@@ -2889,7 +3047,13 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2889 if (*speed == SPEED_1000) 3047 if (*speed == SPEED_1000)
2890 ret_val = e1000_configure_kmrn_for_1000(hw); 3048 ret_val = e1000_configure_kmrn_for_1000(hw);
2891 else 3049 else
2892 ret_val = e1000_configure_kmrn_for_10_100(hw); 3050 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3051 if (ret_val)
3052 return ret_val;
3053 }
3054
3055 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3056 ret_val = e1000_kumeran_lock_loss_workaround(hw);
2893 if (ret_val) 3057 if (ret_val)
2894 return ret_val; 3058 return ret_val;
2895 } 3059 }
@@ -3079,6 +3243,9 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3079 3243
3080 DEBUGFUNC("e1000_swfw_sync_acquire"); 3244 DEBUGFUNC("e1000_swfw_sync_acquire");
3081 3245
3246 if (hw->swfwhw_semaphore_present)
3247 return e1000_get_software_flag(hw);
3248
3082 if (!hw->swfw_sync_present) 3249 if (!hw->swfw_sync_present)
3083 return e1000_get_hw_eeprom_semaphore(hw); 3250 return e1000_get_hw_eeprom_semaphore(hw);
3084 3251
@@ -3118,6 +3285,11 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3118 3285
3119 DEBUGFUNC("e1000_swfw_sync_release"); 3286 DEBUGFUNC("e1000_swfw_sync_release");
3120 3287
3288 if (hw->swfwhw_semaphore_present) {
3289 e1000_release_software_flag(hw);
3290 return;
3291 }
3292
3121 if (!hw->swfw_sync_present) { 3293 if (!hw->swfw_sync_present) {
3122 e1000_put_hw_eeprom_semaphore(hw); 3294 e1000_put_hw_eeprom_semaphore(hw);
3123 return; 3295 return;
@@ -3160,7 +3332,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3160 if (e1000_swfw_sync_acquire(hw, swfw)) 3332 if (e1000_swfw_sync_acquire(hw, swfw))
3161 return -E1000_ERR_SWFW_SYNC; 3333 return -E1000_ERR_SWFW_SYNC;
3162 3334
3163 if((hw->phy_type == e1000_phy_igp || 3335 if ((hw->phy_type == e1000_phy_igp ||
3336 hw->phy_type == e1000_phy_igp_3 ||
3164 hw->phy_type == e1000_phy_igp_2) && 3337 hw->phy_type == e1000_phy_igp_2) &&
3165 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3338 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3166 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3339 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3299,7 +3472,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3299 if (e1000_swfw_sync_acquire(hw, swfw)) 3472 if (e1000_swfw_sync_acquire(hw, swfw))
3300 return -E1000_ERR_SWFW_SYNC; 3473 return -E1000_ERR_SWFW_SYNC;
3301 3474
3302 if((hw->phy_type == e1000_phy_igp || 3475 if ((hw->phy_type == e1000_phy_igp ||
3476 hw->phy_type == e1000_phy_igp_3 ||
3303 hw->phy_type == e1000_phy_igp_2) && 3477 hw->phy_type == e1000_phy_igp_2) &&
3304 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3478 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3305 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3479 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3514,7 +3688,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3514 E1000_WRITE_FLUSH(hw); 3688 E1000_WRITE_FLUSH(hw);
3515 3689
3516 if (hw->mac_type >= e1000_82571) 3690 if (hw->mac_type >= e1000_82571)
3517 msec_delay(10); 3691 msec_delay_irq(10);
3518 e1000_swfw_sync_release(hw, swfw); 3692 e1000_swfw_sync_release(hw, swfw);
3519 } else { 3693 } else {
3520 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3694 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3544,6 +3718,12 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3544 ret_val = e1000_get_phy_cfg_done(hw); 3718 ret_val = e1000_get_phy_cfg_done(hw);
3545 e1000_release_software_semaphore(hw); 3719 e1000_release_software_semaphore(hw);
3546 3720
3721 if ((hw->mac_type == e1000_ich8lan) &&
3722 (hw->phy_type == e1000_phy_igp_3)) {
3723 ret_val = e1000_init_lcd_from_nvm(hw);
3724 if (ret_val)
3725 return ret_val;
3726 }
3547 return ret_val; 3727 return ret_val;
3548} 3728}
3549 3729
@@ -3572,9 +3752,11 @@ e1000_phy_reset(struct e1000_hw *hw)
3572 case e1000_82541_rev_2: 3752 case e1000_82541_rev_2:
3573 case e1000_82571: 3753 case e1000_82571:
3574 case e1000_82572: 3754 case e1000_82572:
3755 case e1000_ich8lan:
3575 ret_val = e1000_phy_hw_reset(hw); 3756 ret_val = e1000_phy_hw_reset(hw);
3576 if(ret_val) 3757 if(ret_val)
3577 return ret_val; 3758 return ret_val;
3759
3578 break; 3760 break;
3579 default: 3761 default:
3580 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3762 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
@@ -3597,11 +3779,120 @@ e1000_phy_reset(struct e1000_hw *hw)
3597} 3779}
3598 3780
3599/****************************************************************************** 3781/******************************************************************************
3782* Work-around for 82566 power-down: on D3 entry-
3783* 1) disable gigabit link
3784* 2) write VR power-down enable
3785* 3) read it back
3786* if successful continue, else issue LCD reset and repeat
3787*
3788* hw - struct containing variables accessed by shared code
3789******************************************************************************/
3790void
3791e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3792{
3793 int32_t reg;
3794 uint16_t phy_data;
3795 int32_t retry = 0;
3796
3797 DEBUGFUNC("e1000_phy_powerdown_workaround");
3798
3799 if (hw->phy_type != e1000_phy_igp_3)
3800 return;
3801
3802 do {
3803 /* Disable link */
3804 reg = E1000_READ_REG(hw, PHY_CTRL);
3805 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3806 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3807
3808 /* Write VR power-down enable */
3809 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3810 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3811 IGP3_VR_CTRL_MODE_SHUT);
3812
3813 /* Read it back and test */
3814 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3815 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3816 break;
3817
3818 /* Issue PHY reset and repeat at most one more time */
3819 reg = E1000_READ_REG(hw, CTRL);
3820 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3821 retry++;
3822 } while (retry);
3823
3824 return;
3825
3826}
3827
3828/******************************************************************************
3829* Work-around for 82566 Kumeran PCS lock loss:
3830* On link status change (i.e. PCI reset, speed change) and link is up and
3831* speed is gigabit-
3832* 0) if workaround is optionally disabled do nothing
3833* 1) wait 1ms for Kumeran link to come up
3834* 2) check Kumeran Diagnostic register PCS lock loss bit
3835* 3) if not set the link is locked (all is good), otherwise...
3836* 4) reset the PHY
3837* 5) repeat up to 10 times
3838* Note: this is only called for IGP3 copper when speed is 1gb.
3839*
3840* hw - struct containing variables accessed by shared code
3841******************************************************************************/
3842int32_t
3843e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3844{
3845 int32_t ret_val;
3846 int32_t reg;
3847 int32_t cnt;
3848 uint16_t phy_data;
3849
3850 if (hw->kmrn_lock_loss_workaround_disabled)
3851 return E1000_SUCCESS;
3852
3853 /* Make sure link is up before proceeding. If not just return.
3854 * Attempting this while link is negotiating fouls up link
3855 * stability */
3856 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3857 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3858
3859 if (phy_data & MII_SR_LINK_STATUS) {
3860 for (cnt = 0; cnt < 10; cnt++) {
3861 /* read once to clear */
3862 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3863 if (ret_val)
3864 return ret_val;
3865 /* and again to get new status */
3866 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3867 if (ret_val)
3868 return ret_val;
3869
3870 /* check for PCS lock */
3871 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3872 return E1000_SUCCESS;
3873
3874 /* Issue PHY reset */
3875 e1000_phy_hw_reset(hw);
3876 msec_delay_irq(5);
3877 }
3878 /* Disable GigE link negotiation */
3879 reg = E1000_READ_REG(hw, PHY_CTRL);
3880 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3881 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3882
3883 /* unable to acquire PCS lock */
3884 return E1000_ERR_PHY;
3885 }
3886
3887 return E1000_SUCCESS;
3888}
3889
3890/******************************************************************************
3600* Probes the expected PHY address for known PHY IDs 3891* Probes the expected PHY address for known PHY IDs
3601* 3892*
3602* hw - Struct containing variables accessed by shared code 3893* hw - Struct containing variables accessed by shared code
3603******************************************************************************/ 3894******************************************************************************/
3604static int32_t 3895int32_t
3605e1000_detect_gig_phy(struct e1000_hw *hw) 3896e1000_detect_gig_phy(struct e1000_hw *hw)
3606{ 3897{
3607 int32_t phy_init_status, ret_val; 3898 int32_t phy_init_status, ret_val;
@@ -3613,8 +3904,8 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3613 /* The 82571 firmware may still be configuring the PHY. In this 3904 /* The 82571 firmware may still be configuring the PHY. In this
3614 * case, we cannot access the PHY until the configuration is done. So 3905 * case, we cannot access the PHY until the configuration is done. So
3615 * we explicitly set the PHY values. */ 3906 * we explicitly set the PHY values. */
3616 if(hw->mac_type == e1000_82571 || 3907 if (hw->mac_type == e1000_82571 ||
3617 hw->mac_type == e1000_82572) { 3908 hw->mac_type == e1000_82572) {
3618 hw->phy_id = IGP01E1000_I_PHY_ID; 3909 hw->phy_id = IGP01E1000_I_PHY_ID;
3619 hw->phy_type = e1000_phy_igp_2; 3910 hw->phy_type = e1000_phy_igp_2;
3620 return E1000_SUCCESS; 3911 return E1000_SUCCESS;
@@ -3631,7 +3922,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3631 3922
3632 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3923 /* Read the PHY ID Registers to identify which PHY is onboard. */
3633 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3924 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3634 if(ret_val) 3925 if (ret_val)
3635 return ret_val; 3926 return ret_val;
3636 3927
3637 hw->phy_id = (uint32_t) (phy_id_high << 16); 3928 hw->phy_id = (uint32_t) (phy_id_high << 16);
@@ -3669,6 +3960,12 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3669 case e1000_80003es2lan: 3960 case e1000_80003es2lan:
3670 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 3961 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3671 break; 3962 break;
3963 case e1000_ich8lan:
3964 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
3965 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
3966 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
3967 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
3968 break;
3672 default: 3969 default:
3673 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3970 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3674 return -E1000_ERR_CONFIG; 3971 return -E1000_ERR_CONFIG;
@@ -3784,6 +4081,53 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
3784} 4081}
3785 4082
3786/****************************************************************************** 4083/******************************************************************************
4084* Get PHY information from various PHY registers for ife PHY only.
4085*
4086* hw - Struct containing variables accessed by shared code
4087* phy_info - PHY information structure
4088******************************************************************************/
4089int32_t
4090e1000_phy_ife_get_info(struct e1000_hw *hw,
4091 struct e1000_phy_info *phy_info)
4092{
4093 int32_t ret_val;
4094 uint16_t phy_data, polarity;
4095
4096 DEBUGFUNC("e1000_phy_ife_get_info");
4097
4098 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4099 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4100
4101 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4102 if (ret_val)
4103 return ret_val;
4104 phy_info->polarity_correction =
4105 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4106 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4107
4108 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4109 ret_val = e1000_check_polarity(hw, &polarity);
4110 if (ret_val)
4111 return ret_val;
4112 } else {
4113 /* Polarity is forced. */
4114 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4115 IFE_PSC_FORCE_POLARITY_SHIFT;
4116 }
4117 phy_info->cable_polarity = polarity;
4118
4119 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4120 if (ret_val)
4121 return ret_val;
4122
4123 phy_info->mdix_mode =
4124 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4125 IFE_PMC_MDIX_MODE_SHIFT;
4126
4127 return E1000_SUCCESS;
4128}
4129
4130/******************************************************************************
3787* Get PHY information from various PHY registers fot m88 PHY only. 4131* Get PHY information from various PHY registers fot m88 PHY only.
3788* 4132*
3789* hw - Struct containing variables accessed by shared code 4133* hw - Struct containing variables accessed by shared code
@@ -3898,9 +4242,12 @@ e1000_phy_get_info(struct e1000_hw *hw,
3898 return -E1000_ERR_CONFIG; 4242 return -E1000_ERR_CONFIG;
3899 } 4243 }
3900 4244
3901 if(hw->phy_type == e1000_phy_igp || 4245 if (hw->phy_type == e1000_phy_igp ||
4246 hw->phy_type == e1000_phy_igp_3 ||
3902 hw->phy_type == e1000_phy_igp_2) 4247 hw->phy_type == e1000_phy_igp_2)
3903 return e1000_phy_igp_get_info(hw, phy_info); 4248 return e1000_phy_igp_get_info(hw, phy_info);
4249 else if (hw->phy_type == e1000_phy_ife)
4250 return e1000_phy_ife_get_info(hw, phy_info);
3904 else 4251 else
3905 return e1000_phy_m88_get_info(hw, phy_info); 4252 return e1000_phy_m88_get_info(hw, phy_info);
3906} 4253}
@@ -4049,6 +4396,35 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4049 eeprom->use_eerd = TRUE; 4396 eeprom->use_eerd = TRUE;
4050 eeprom->use_eewr = FALSE; 4397 eeprom->use_eewr = FALSE;
4051 break; 4398 break;
4399 case e1000_ich8lan:
4400 {
4401 int32_t i = 0;
4402 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4403
4404 eeprom->type = e1000_eeprom_ich8;
4405 eeprom->use_eerd = FALSE;
4406 eeprom->use_eewr = FALSE;
4407 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4408
4409 /* Zero the shadow RAM structure. But don't load it from NVM
4410 * so as to save time for driver init */
4411 if (hw->eeprom_shadow_ram != NULL) {
4412 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4413 hw->eeprom_shadow_ram[i].modified = FALSE;
4414 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4415 }
4416 }
4417
4418 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4419 ICH8_FLASH_SECTOR_SIZE;
4420
4421 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4422 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4423 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4424 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4425
4426 break;
4427 }
4052 default: 4428 default:
4053 break; 4429 break;
4054 } 4430 }
@@ -4469,7 +4845,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
4469 return ret_val; 4845 return ret_val;
4470 } 4846 }
4471 4847
4472 if(eeprom->type == e1000_eeprom_spi) { 4848 if (eeprom->type == e1000_eeprom_ich8)
4849 return e1000_read_eeprom_ich8(hw, offset, words, data);
4850
4851 if (eeprom->type == e1000_eeprom_spi) {
4473 uint16_t word_in; 4852 uint16_t word_in;
4474 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4853 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4475 4854
@@ -4636,7 +5015,10 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4636 5015
4637 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5016 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
4638 5017
4639 if(hw->mac_type == e1000_82573) { 5018 if (hw->mac_type == e1000_ich8lan)
5019 return FALSE;
5020
5021 if (hw->mac_type == e1000_82573) {
4640 eecd = E1000_READ_REG(hw, EECD); 5022 eecd = E1000_READ_REG(hw, EECD);
4641 5023
4642 /* Isolate bits 15 & 16 */ 5024 /* Isolate bits 15 & 16 */
@@ -4686,8 +5068,22 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4686 } 5068 }
4687 } 5069 }
4688 5070
4689 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 5071 if (hw->mac_type == e1000_ich8lan) {
4690 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5072 /* Drivers must allocate the shadow ram structure for the
5073 * EEPROM checksum to be updated. Otherwise, this bit as well
5074 * as the checksum must both be set correctly for this
5075 * validation to pass.
5076 */
5077 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5078 if ((eeprom_data & 0x40) == 0) {
5079 eeprom_data |= 0x40;
5080 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5081 e1000_update_eeprom_checksum(hw);
5082 }
5083 }
5084
5085 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5086 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4691 DEBUGOUT("EEPROM Read Error\n"); 5087 DEBUGOUT("EEPROM Read Error\n");
4692 return -E1000_ERR_EEPROM; 5088 return -E1000_ERR_EEPROM;
4693 } 5089 }
@@ -4713,6 +5109,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4713int32_t 5109int32_t
4714e1000_update_eeprom_checksum(struct e1000_hw *hw) 5110e1000_update_eeprom_checksum(struct e1000_hw *hw)
4715{ 5111{
5112 uint32_t ctrl_ext;
4716 uint16_t checksum = 0; 5113 uint16_t checksum = 0;
4717 uint16_t i, eeprom_data; 5114 uint16_t i, eeprom_data;
4718 5115
@@ -4731,6 +5128,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
4731 return -E1000_ERR_EEPROM; 5128 return -E1000_ERR_EEPROM;
4732 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5129 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4733 e1000_commit_shadow_ram(hw); 5130 e1000_commit_shadow_ram(hw);
5131 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5132 e1000_commit_shadow_ram(hw);
5133 /* Reload the EEPROM, or else modifications will not appear
5134 * until after next adapter reset. */
5135 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5136 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5137 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5138 msec_delay(10);
4734 } 5139 }
4735 return E1000_SUCCESS; 5140 return E1000_SUCCESS;
4736} 5141}
@@ -4770,6 +5175,9 @@ e1000_write_eeprom(struct e1000_hw *hw,
4770 if(eeprom->use_eewr == TRUE) 5175 if(eeprom->use_eewr == TRUE)
4771 return e1000_write_eeprom_eewr(hw, offset, words, data); 5176 return e1000_write_eeprom_eewr(hw, offset, words, data);
4772 5177
5178 if (eeprom->type == e1000_eeprom_ich8)
5179 return e1000_write_eeprom_ich8(hw, offset, words, data);
5180
4773 /* Prepare the EEPROM for writing */ 5181 /* Prepare the EEPROM for writing */
4774 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5182 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4775 return -E1000_ERR_EEPROM; 5183 return -E1000_ERR_EEPROM;
@@ -4957,11 +5365,17 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4957 uint32_t flop = 0; 5365 uint32_t flop = 0;
4958 uint32_t i = 0; 5366 uint32_t i = 0;
4959 int32_t error = E1000_SUCCESS; 5367 int32_t error = E1000_SUCCESS;
4960 5368 uint32_t old_bank_offset = 0;
4961 /* The flop register will be used to determine if flash type is STM */ 5369 uint32_t new_bank_offset = 0;
4962 flop = E1000_READ_REG(hw, FLOP); 5370 uint32_t sector_retries = 0;
5371 uint8_t low_byte = 0;
5372 uint8_t high_byte = 0;
5373 uint8_t temp_byte = 0;
5374 boolean_t sector_write_failed = FALSE;
4963 5375
4964 if (hw->mac_type == e1000_82573) { 5376 if (hw->mac_type == e1000_82573) {
5377 /* The flop register will be used to determine if flash type is STM */
5378 flop = E1000_READ_REG(hw, FLOP);
4965 for (i=0; i < attempts; i++) { 5379 for (i=0; i < attempts; i++) {
4966 eecd = E1000_READ_REG(hw, EECD); 5380 eecd = E1000_READ_REG(hw, EECD);
4967 if ((eecd & E1000_EECD_FLUPD) == 0) { 5381 if ((eecd & E1000_EECD_FLUPD) == 0) {
@@ -4995,6 +5409,106 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4995 } 5409 }
4996 } 5410 }
4997 5411
5412 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5413 /* We're writing to the opposite bank so if we're on bank 1,
5414 * write to bank 0 etc. We also need to erase the segment that
5415 * is going to be written */
5416 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5417 new_bank_offset = hw->flash_bank_size * 2;
5418 old_bank_offset = 0;
5419 e1000_erase_ich8_4k_segment(hw, 1);
5420 } else {
5421 old_bank_offset = hw->flash_bank_size * 2;
5422 new_bank_offset = 0;
5423 e1000_erase_ich8_4k_segment(hw, 0);
5424 }
5425
5426 do {
5427 sector_write_failed = FALSE;
5428 /* Loop for every byte in the shadow RAM,
5429 * which is in units of words. */
5430 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5431 /* Determine whether to write the value stored
5432 * in the other NVM bank or a modified value stored
5433 * in the shadow RAM */
5434 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5435 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5436 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5437 &temp_byte);
5438 udelay(100);
5439 error = e1000_verify_write_ich8_byte(hw,
5440 (i << 1) + new_bank_offset,
5441 low_byte);
5442 if (error != E1000_SUCCESS)
5443 sector_write_failed = TRUE;
5444 high_byte =
5445 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5446 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5447 &temp_byte);
5448 udelay(100);
5449 } else {
5450 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5451 &low_byte);
5452 udelay(100);
5453 error = e1000_verify_write_ich8_byte(hw,
5454 (i << 1) + new_bank_offset, low_byte);
5455 if (error != E1000_SUCCESS)
5456 sector_write_failed = TRUE;
5457 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5458 &high_byte);
5459 }
5460
5461 /* If the word is 0x13, then make sure the signature bits
5462 * (15:14) are 11b until the commit has completed.
5463 * This will allow us to write 10b which indicates the
5464 * signature is valid. We want to do this after the write
5465 * has completed so that we don't mark the segment valid
5466 * while the write is still in progress */
5467 if (i == E1000_ICH8_NVM_SIG_WORD)
5468 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5469
5470 error = e1000_verify_write_ich8_byte(hw,
5471 (i << 1) + new_bank_offset + 1, high_byte);
5472 if (error != E1000_SUCCESS)
5473 sector_write_failed = TRUE;
5474
5475 if (sector_write_failed == FALSE) {
5476 /* Clear the now not used entry in the cache */
5477 hw->eeprom_shadow_ram[i].modified = FALSE;
5478 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5479 }
5480 }
5481
5482 /* Don't bother writing the segment valid bits if sector
5483 * programming failed. */
5484 if (sector_write_failed == FALSE) {
5485 /* Finally validate the new segment by setting bit 15:14
5486 * to 10b in word 0x13 , this can be done without an
5487 * erase as well since these bits are 11 to start with
5488 * and we need to change bit 14 to 0b */
5489 e1000_read_ich8_byte(hw,
5490 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5491 &high_byte);
5492 high_byte &= 0xBF;
5493 error = e1000_verify_write_ich8_byte(hw,
5494 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5495 high_byte);
5496 if (error != E1000_SUCCESS)
5497 sector_write_failed = TRUE;
5498
5499 /* And invalidate the previously valid segment by setting
5500 * its signature word (0x13) high_byte to 0b. This can be
5501 * done without an erase because flash erase sets all bits
5502 * to 1's. We can write 1's to 0's without an erase */
5503 error = e1000_verify_write_ich8_byte(hw,
5504 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5505 0);
5506 if (error != E1000_SUCCESS)
5507 sector_write_failed = TRUE;
5508 }
5509 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5510 }
5511
4998 return error; 5512 return error;
4999} 5513}
5000 5514
@@ -5102,15 +5616,19 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5102 * the other port. */ 5616 * the other port. */
5103 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5617 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5104 rar_num -= 1; 5618 rar_num -= 1;
5619 if (hw->mac_type == e1000_ich8lan)
5620 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5621
5105 /* Zero out the other 15 receive addresses. */ 5622 /* Zero out the other 15 receive addresses. */
5106 DEBUGOUT("Clearing RAR[1-15]\n"); 5623 DEBUGOUT("Clearing RAR[1-15]\n");
5107 for(i = 1; i < rar_num; i++) { 5624 for(i = 1; i < rar_num; i++) {
5108 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5625 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5626 E1000_WRITE_FLUSH(hw);
5109 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5627 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5628 E1000_WRITE_FLUSH(hw);
5110 } 5629 }
5111} 5630}
5112 5631
5113#if 0
5114/****************************************************************************** 5632/******************************************************************************
5115 * Updates the MAC's list of multicast addresses. 5633 * Updates the MAC's list of multicast addresses.
5116 * 5634 *
@@ -5145,6 +5663,8 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5145 /* Clear RAR[1-15] */ 5663 /* Clear RAR[1-15] */
5146 DEBUGOUT(" Clearing RAR[1-15]\n"); 5664 DEBUGOUT(" Clearing RAR[1-15]\n");
5147 num_rar_entry = E1000_RAR_ENTRIES; 5665 num_rar_entry = E1000_RAR_ENTRIES;
5666 if (hw->mac_type == e1000_ich8lan)
5667 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5148 /* Reserve a spot for the Locally Administered Address to work around 5668 /* Reserve a spot for the Locally Administered Address to work around
5149 * an 82571 issue in which a reset on one port will reload the MAC on 5669 * an 82571 issue in which a reset on one port will reload the MAC on
5150 * the other port. */ 5670 * the other port. */
@@ -5153,14 +5673,19 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5153 5673
5154 for(i = rar_used_count; i < num_rar_entry; i++) { 5674 for(i = rar_used_count; i < num_rar_entry; i++) {
5155 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5675 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5676 E1000_WRITE_FLUSH(hw);
5156 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5677 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5678 E1000_WRITE_FLUSH(hw);
5157 } 5679 }
5158 5680
5159 /* Clear the MTA */ 5681 /* Clear the MTA */
5160 DEBUGOUT(" Clearing MTA\n"); 5682 DEBUGOUT(" Clearing MTA\n");
5161 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5683 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5684 if (hw->mac_type == e1000_ich8lan)
5685 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5162 for(i = 0; i < num_mta_entry; i++) { 5686 for(i = 0; i < num_mta_entry; i++) {
5163 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5687 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5688 E1000_WRITE_FLUSH(hw);
5164 } 5689 }
5165 5690
5166 /* Add the new addresses */ 5691 /* Add the new addresses */
@@ -5194,7 +5719,6 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5194 } 5719 }
5195 DEBUGOUT("MC Update Complete\n"); 5720 DEBUGOUT("MC Update Complete\n");
5196} 5721}
5197#endif /* 0 */
5198 5722
5199/****************************************************************************** 5723/******************************************************************************
5200 * Hashes an address to determine its location in the multicast table 5724 * Hashes an address to determine its location in the multicast table
@@ -5217,24 +5741,46 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5217 * LSB MSB 5741 * LSB MSB
5218 */ 5742 */
5219 case 0: 5743 case 0:
5220 /* [47:36] i.e. 0x563 for above example address */ 5744 if (hw->mac_type == e1000_ich8lan) {
5221 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5745 /* [47:38] i.e. 0x158 for above example address */
5746 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5747 } else {
5748 /* [47:36] i.e. 0x563 for above example address */
5749 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5750 }
5222 break; 5751 break;
5223 case 1: 5752 case 1:
5224 /* [46:35] i.e. 0xAC6 for above example address */ 5753 if (hw->mac_type == e1000_ich8lan) {
5225 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5754 /* [46:37] i.e. 0x2B1 for above example address */
5755 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5756 } else {
5757 /* [46:35] i.e. 0xAC6 for above example address */
5758 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5759 }
5226 break; 5760 break;
5227 case 2: 5761 case 2:
5228 /* [45:34] i.e. 0x5D8 for above example address */ 5762 if (hw->mac_type == e1000_ich8lan) {
5229 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5763 /*[45:36] i.e. 0x163 for above example address */
5764 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5765 } else {
5766 /* [45:34] i.e. 0x5D8 for above example address */
5767 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5768 }
5230 break; 5769 break;
5231 case 3: 5770 case 3:
5232 /* [43:32] i.e. 0x634 for above example address */ 5771 if (hw->mac_type == e1000_ich8lan) {
5233 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5772 /* [43:34] i.e. 0x18D for above example address */
5773 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5774 } else {
5775 /* [43:32] i.e. 0x634 for above example address */
5776 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5777 }
5234 break; 5778 break;
5235 } 5779 }
5236 5780
5237 hash_value &= 0xFFF; 5781 hash_value &= 0xFFF;
5782 if (hw->mac_type == e1000_ich8lan)
5783 hash_value &= 0x3FF;
5238 5784
5239 return hash_value; 5785 return hash_value;
5240} 5786}
@@ -5262,6 +5808,8 @@ e1000_mta_set(struct e1000_hw *hw,
5262 * register are determined by the lower 5 bits of the value. 5808 * register are determined by the lower 5 bits of the value.
5263 */ 5809 */
5264 hash_reg = (hash_value >> 5) & 0x7F; 5810 hash_reg = (hash_value >> 5) & 0x7F;
5811 if (hw->mac_type == e1000_ich8lan)
5812 hash_reg &= 0x1F;
5265 hash_bit = hash_value & 0x1F; 5813 hash_bit = hash_value & 0x1F;
5266 5814
5267 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5815 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -5275,9 +5823,12 @@ e1000_mta_set(struct e1000_hw *hw,
5275 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5823 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5276 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5824 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5277 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5825 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5826 E1000_WRITE_FLUSH(hw);
5278 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5827 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5828 E1000_WRITE_FLUSH(hw);
5279 } else { 5829 } else {
5280 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5830 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5831 E1000_WRITE_FLUSH(hw);
5281 } 5832 }
5282} 5833}
5283 5834
@@ -5334,7 +5885,9 @@ e1000_rar_set(struct e1000_hw *hw,
5334 } 5885 }
5335 5886
5336 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5887 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5888 E1000_WRITE_FLUSH(hw);
5337 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5889 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5890 E1000_WRITE_FLUSH(hw);
5338} 5891}
5339 5892
5340/****************************************************************************** 5893/******************************************************************************
@@ -5351,12 +5904,18 @@ e1000_write_vfta(struct e1000_hw *hw,
5351{ 5904{
5352 uint32_t temp; 5905 uint32_t temp;
5353 5906
5354 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5907 if (hw->mac_type == e1000_ich8lan)
5908 return;
5909
5910 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5355 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5911 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5356 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5912 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5913 E1000_WRITE_FLUSH(hw);
5357 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 5914 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5915 E1000_WRITE_FLUSH(hw);
5358 } else { 5916 } else {
5359 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5917 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5918 E1000_WRITE_FLUSH(hw);
5360 } 5919 }
5361} 5920}
5362 5921
@@ -5373,6 +5932,9 @@ e1000_clear_vfta(struct e1000_hw *hw)
5373 uint32_t vfta_offset = 0; 5932 uint32_t vfta_offset = 0;
5374 uint32_t vfta_bit_in_reg = 0; 5933 uint32_t vfta_bit_in_reg = 0;
5375 5934
5935 if (hw->mac_type == e1000_ich8lan)
5936 return;
5937
5376 if (hw->mac_type == e1000_82573) { 5938 if (hw->mac_type == e1000_82573) {
5377 if (hw->mng_cookie.vlan_id != 0) { 5939 if (hw->mng_cookie.vlan_id != 0) {
5378 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 5940 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
@@ -5392,6 +5954,7 @@ e1000_clear_vfta(struct e1000_hw *hw)
5392 * manageability unit */ 5954 * manageability unit */
5393 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5955 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5394 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5956 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5957 E1000_WRITE_FLUSH(hw);
5395 } 5958 }
5396} 5959}
5397 5960
@@ -5421,9 +5984,18 @@ e1000_id_led_init(struct e1000_hw * hw)
5421 DEBUGOUT("EEPROM Read Error\n"); 5984 DEBUGOUT("EEPROM Read Error\n");
5422 return -E1000_ERR_EEPROM; 5985 return -E1000_ERR_EEPROM;
5423 } 5986 }
5424 if((eeprom_data== ID_LED_RESERVED_0000) || 5987
5425 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; 5988 if ((hw->mac_type == e1000_82573) &&
5426 for(i = 0; i < 4; i++) { 5989 (eeprom_data == ID_LED_RESERVED_82573))
5990 eeprom_data = ID_LED_DEFAULT_82573;
5991 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5992 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5993 if (hw->mac_type == e1000_ich8lan)
5994 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5995 else
5996 eeprom_data = ID_LED_DEFAULT;
5997 }
5998 for (i = 0; i < 4; i++) {
5427 temp = (eeprom_data >> (i << 2)) & led_mask; 5999 temp = (eeprom_data >> (i << 2)) & led_mask;
5428 switch(temp) { 6000 switch(temp) {
5429 case ID_LED_ON1_DEF2: 6001 case ID_LED_ON1_DEF2:
@@ -5519,6 +6091,44 @@ e1000_setup_led(struct e1000_hw *hw)
5519} 6091}
5520 6092
5521/****************************************************************************** 6093/******************************************************************************
6094 * Used on 82571 and later Si that has LED blink bits.
6095 * Callers must use their own timer and should have already called
6096 * e1000_id_led_init()
6097 * Call e1000_cleanup led() to stop blinking
6098 *
6099 * hw - Struct containing variables accessed by shared code
6100 *****************************************************************************/
6101int32_t
6102e1000_blink_led_start(struct e1000_hw *hw)
6103{
6104 int16_t i;
6105 uint32_t ledctl_blink = 0;
6106
6107 DEBUGFUNC("e1000_id_led_blink_on");
6108
6109 if (hw->mac_type < e1000_82571) {
6110 /* Nothing to do */
6111 return E1000_SUCCESS;
6112 }
6113 if (hw->media_type == e1000_media_type_fiber) {
6114 /* always blink LED0 for PCI-E fiber */
6115 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6116 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6117 } else {
6118 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6119 ledctl_blink = hw->ledctl_mode2;
6120 for (i=0; i < 4; i++)
6121 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6122 E1000_LEDCTL_MODE_LED_ON)
6123 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6124 }
6125
6126 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6127
6128 return E1000_SUCCESS;
6129}
6130
6131/******************************************************************************
5522 * Restores the saved state of the SW controlable LED. 6132 * Restores the saved state of the SW controlable LED.
5523 * 6133 *
5524 * hw - Struct containing variables accessed by shared code 6134 * hw - Struct containing variables accessed by shared code
@@ -5548,6 +6158,10 @@ e1000_cleanup_led(struct e1000_hw *hw)
5548 return ret_val; 6158 return ret_val;
5549 /* Fall Through */ 6159 /* Fall Through */
5550 default: 6160 default:
6161 if (hw->phy_type == e1000_phy_ife) {
6162 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6163 break;
6164 }
5551 /* Restore LEDCTL settings */ 6165 /* Restore LEDCTL settings */
5552 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6166 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
5553 break; 6167 break;
@@ -5592,7 +6206,10 @@ e1000_led_on(struct e1000_hw *hw)
5592 /* Clear SW Defineable Pin 0 to turn on the LED */ 6206 /* Clear SW Defineable Pin 0 to turn on the LED */
5593 ctrl &= ~E1000_CTRL_SWDPIN0; 6207 ctrl &= ~E1000_CTRL_SWDPIN0;
5594 ctrl |= E1000_CTRL_SWDPIO0; 6208 ctrl |= E1000_CTRL_SWDPIO0;
5595 } else if(hw->media_type == e1000_media_type_copper) { 6209 } else if (hw->phy_type == e1000_phy_ife) {
6210 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6211 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6212 } else if (hw->media_type == e1000_media_type_copper) {
5596 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6213 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5597 return E1000_SUCCESS; 6214 return E1000_SUCCESS;
5598 } 6215 }
@@ -5640,7 +6257,10 @@ e1000_led_off(struct e1000_hw *hw)
5640 /* Set SW Defineable Pin 0 to turn off the LED */ 6257 /* Set SW Defineable Pin 0 to turn off the LED */
5641 ctrl |= E1000_CTRL_SWDPIN0; 6258 ctrl |= E1000_CTRL_SWDPIN0;
5642 ctrl |= E1000_CTRL_SWDPIO0; 6259 ctrl |= E1000_CTRL_SWDPIO0;
5643 } else if(hw->media_type == e1000_media_type_copper) { 6260 } else if (hw->phy_type == e1000_phy_ife) {
6261 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6262 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6263 } else if (hw->media_type == e1000_media_type_copper) {
5644 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6264 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5645 return E1000_SUCCESS; 6265 return E1000_SUCCESS;
5646 } 6266 }
@@ -5678,12 +6298,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5678 temp = E1000_READ_REG(hw, XOFFRXC); 6298 temp = E1000_READ_REG(hw, XOFFRXC);
5679 temp = E1000_READ_REG(hw, XOFFTXC); 6299 temp = E1000_READ_REG(hw, XOFFTXC);
5680 temp = E1000_READ_REG(hw, FCRUC); 6300 temp = E1000_READ_REG(hw, FCRUC);
6301
6302 if (hw->mac_type != e1000_ich8lan) {
5681 temp = E1000_READ_REG(hw, PRC64); 6303 temp = E1000_READ_REG(hw, PRC64);
5682 temp = E1000_READ_REG(hw, PRC127); 6304 temp = E1000_READ_REG(hw, PRC127);
5683 temp = E1000_READ_REG(hw, PRC255); 6305 temp = E1000_READ_REG(hw, PRC255);
5684 temp = E1000_READ_REG(hw, PRC511); 6306 temp = E1000_READ_REG(hw, PRC511);
5685 temp = E1000_READ_REG(hw, PRC1023); 6307 temp = E1000_READ_REG(hw, PRC1023);
5686 temp = E1000_READ_REG(hw, PRC1522); 6308 temp = E1000_READ_REG(hw, PRC1522);
6309 }
6310
5687 temp = E1000_READ_REG(hw, GPRC); 6311 temp = E1000_READ_REG(hw, GPRC);
5688 temp = E1000_READ_REG(hw, BPRC); 6312 temp = E1000_READ_REG(hw, BPRC);
5689 temp = E1000_READ_REG(hw, MPRC); 6313 temp = E1000_READ_REG(hw, MPRC);
@@ -5703,12 +6327,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5703 temp = E1000_READ_REG(hw, TOTH); 6327 temp = E1000_READ_REG(hw, TOTH);
5704 temp = E1000_READ_REG(hw, TPR); 6328 temp = E1000_READ_REG(hw, TPR);
5705 temp = E1000_READ_REG(hw, TPT); 6329 temp = E1000_READ_REG(hw, TPT);
6330
6331 if (hw->mac_type != e1000_ich8lan) {
5706 temp = E1000_READ_REG(hw, PTC64); 6332 temp = E1000_READ_REG(hw, PTC64);
5707 temp = E1000_READ_REG(hw, PTC127); 6333 temp = E1000_READ_REG(hw, PTC127);
5708 temp = E1000_READ_REG(hw, PTC255); 6334 temp = E1000_READ_REG(hw, PTC255);
5709 temp = E1000_READ_REG(hw, PTC511); 6335 temp = E1000_READ_REG(hw, PTC511);
5710 temp = E1000_READ_REG(hw, PTC1023); 6336 temp = E1000_READ_REG(hw, PTC1023);
5711 temp = E1000_READ_REG(hw, PTC1522); 6337 temp = E1000_READ_REG(hw, PTC1522);
6338 }
6339
5712 temp = E1000_READ_REG(hw, MPTC); 6340 temp = E1000_READ_REG(hw, MPTC);
5713 temp = E1000_READ_REG(hw, BPTC); 6341 temp = E1000_READ_REG(hw, BPTC);
5714 6342
@@ -5731,6 +6359,9 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5731 6359
5732 temp = E1000_READ_REG(hw, IAC); 6360 temp = E1000_READ_REG(hw, IAC);
5733 temp = E1000_READ_REG(hw, ICRXOC); 6361 temp = E1000_READ_REG(hw, ICRXOC);
6362
6363 if (hw->mac_type == e1000_ich8lan) return;
6364
5734 temp = E1000_READ_REG(hw, ICRXPTC); 6365 temp = E1000_READ_REG(hw, ICRXPTC);
5735 temp = E1000_READ_REG(hw, ICRXATC); 6366 temp = E1000_READ_REG(hw, ICRXATC);
5736 temp = E1000_READ_REG(hw, ICTXPTC); 6367 temp = E1000_READ_REG(hw, ICTXPTC);
@@ -5911,6 +6542,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
5911 hw->bus_width = e1000_bus_width_pciex_1; 6542 hw->bus_width = e1000_bus_width_pciex_1;
5912 break; 6543 break;
5913 case e1000_82571: 6544 case e1000_82571:
6545 case e1000_ich8lan:
5914 case e1000_80003es2lan: 6546 case e1000_80003es2lan:
5915 hw->bus_type = e1000_bus_type_pci_express; 6547 hw->bus_type = e1000_bus_type_pci_express;
5916 hw->bus_speed = e1000_bus_speed_2500; 6548 hw->bus_speed = e1000_bus_speed_2500;
@@ -5948,8 +6580,6 @@ e1000_get_bus_info(struct e1000_hw *hw)
5948 break; 6580 break;
5949 } 6581 }
5950} 6582}
5951
5952#if 0
5953/****************************************************************************** 6583/******************************************************************************
5954 * Reads a value from one of the devices registers using port I/O (as opposed 6584 * Reads a value from one of the devices registers using port I/O (as opposed
5955 * memory mapped I/O). Only 82544 and newer devices support port I/O. 6585 * memory mapped I/O). Only 82544 and newer devices support port I/O.
@@ -5967,7 +6597,6 @@ e1000_read_reg_io(struct e1000_hw *hw,
5967 e1000_io_write(hw, io_addr, offset); 6597 e1000_io_write(hw, io_addr, offset);
5968 return e1000_io_read(hw, io_data); 6598 return e1000_io_read(hw, io_data);
5969} 6599}
5970#endif /* 0 */
5971 6600
5972/****************************************************************************** 6601/******************************************************************************
5973 * Writes a value to one of the devices registers using port I/O (as opposed to 6602 * Writes a value to one of the devices registers using port I/O (as opposed to
@@ -6012,8 +6641,6 @@ e1000_get_cable_length(struct e1000_hw *hw,
6012{ 6641{
6013 int32_t ret_val; 6642 int32_t ret_val;
6014 uint16_t agc_value = 0; 6643 uint16_t agc_value = 0;
6015 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6016 uint16_t max_agc = 0;
6017 uint16_t i, phy_data; 6644 uint16_t i, phy_data;
6018 uint16_t cable_length; 6645 uint16_t cable_length;
6019 6646
@@ -6086,6 +6713,8 @@ e1000_get_cable_length(struct e1000_hw *hw,
6086 break; 6713 break;
6087 } 6714 }
6088 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6715 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6716 uint16_t cur_agc_value;
6717 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6089 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6718 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6090 {IGP01E1000_PHY_AGC_A, 6719 {IGP01E1000_PHY_AGC_A,
6091 IGP01E1000_PHY_AGC_B, 6720 IGP01E1000_PHY_AGC_B,
@@ -6098,23 +6727,23 @@ e1000_get_cable_length(struct e1000_hw *hw,
6098 if(ret_val) 6727 if(ret_val)
6099 return ret_val; 6728 return ret_val;
6100 6729
6101 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6730 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6102 6731
6103 /* Array bound check. */ 6732 /* Value bound check. */
6104 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 6733 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6105 (cur_agc == 0)) 6734 (cur_agc_value == 0))
6106 return -E1000_ERR_PHY; 6735 return -E1000_ERR_PHY;
6107 6736
6108 agc_value += cur_agc; 6737 agc_value += cur_agc_value;
6109 6738
6110 /* Update minimal AGC value. */ 6739 /* Update minimal AGC value. */
6111 if(min_agc > cur_agc) 6740 if (min_agc_value > cur_agc_value)
6112 min_agc = cur_agc; 6741 min_agc_value = cur_agc_value;
6113 } 6742 }
6114 6743
6115 /* Remove the minimal AGC result for length < 50m */ 6744 /* Remove the minimal AGC result for length < 50m */
6116 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 6745 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6117 agc_value -= min_agc; 6746 agc_value -= min_agc_value;
6118 6747
6119 /* Get the average length of the remaining 3 channels */ 6748 /* Get the average length of the remaining 3 channels */
6120 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 6749 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
@@ -6130,7 +6759,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6130 IGP01E1000_AGC_RANGE) : 0; 6759 IGP01E1000_AGC_RANGE) : 0;
6131 *max_length = e1000_igp_cable_length_table[agc_value] + 6760 *max_length = e1000_igp_cable_length_table[agc_value] +
6132 IGP01E1000_AGC_RANGE; 6761 IGP01E1000_AGC_RANGE;
6133 } else if (hw->phy_type == e1000_phy_igp_2) { 6762 } else if (hw->phy_type == e1000_phy_igp_2 ||
6763 hw->phy_type == e1000_phy_igp_3) {
6764 uint16_t cur_agc_index, max_agc_index = 0;
6765 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6134 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6766 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6135 {IGP02E1000_PHY_AGC_A, 6767 {IGP02E1000_PHY_AGC_A,
6136 IGP02E1000_PHY_AGC_B, 6768 IGP02E1000_PHY_AGC_B,
@@ -6145,19 +6777,27 @@ e1000_get_cable_length(struct e1000_hw *hw,
6145 /* Getting bits 15:9, which represent the combination of course and 6777 /* Getting bits 15:9, which represent the combination of course and
6146 * fine gain values. The result is a number that can be put into 6778 * fine gain values. The result is a number that can be put into
6147 * the lookup table to obtain the approximate cable length. */ 6779 * the lookup table to obtain the approximate cable length. */
6148 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6780 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6149 IGP02E1000_AGC_LENGTH_MASK; 6781 IGP02E1000_AGC_LENGTH_MASK;
6150 6782
6151 /* Remove min & max AGC values from calculation. */ 6783 /* Array index bound check. */
6152 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) 6784 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6153 min_agc = cur_agc; 6785 (cur_agc_index == 0))
6154 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) 6786 return -E1000_ERR_PHY;
6155 max_agc = cur_agc;
6156 6787
6157 agc_value += e1000_igp_2_cable_length_table[cur_agc]; 6788 /* Remove min & max AGC values from calculation. */
6789 if (e1000_igp_2_cable_length_table[min_agc_index] >
6790 e1000_igp_2_cable_length_table[cur_agc_index])
6791 min_agc_index = cur_agc_index;
6792 if (e1000_igp_2_cable_length_table[max_agc_index] <
6793 e1000_igp_2_cable_length_table[cur_agc_index])
6794 max_agc_index = cur_agc_index;
6795
6796 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6158 } 6797 }
6159 6798
6160 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); 6799 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6800 e1000_igp_2_cable_length_table[max_agc_index]);
6161 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 6801 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6162 6802
6163 /* Calculate cable length with the error range of +/- 10 meters. */ 6803 /* Calculate cable length with the error range of +/- 10 meters. */
@@ -6203,7 +6843,8 @@ e1000_check_polarity(struct e1000_hw *hw,
6203 return ret_val; 6843 return ret_val;
6204 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6844 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6205 M88E1000_PSSR_REV_POLARITY_SHIFT; 6845 M88E1000_PSSR_REV_POLARITY_SHIFT;
6206 } else if(hw->phy_type == e1000_phy_igp || 6846 } else if (hw->phy_type == e1000_phy_igp ||
6847 hw->phy_type == e1000_phy_igp_3 ||
6207 hw->phy_type == e1000_phy_igp_2) { 6848 hw->phy_type == e1000_phy_igp_2) {
6208 /* Read the Status register to check the speed */ 6849 /* Read the Status register to check the speed */
6209 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6850 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
@@ -6229,6 +6870,13 @@ e1000_check_polarity(struct e1000_hw *hw,
6229 * 100 Mbps this bit is always 0) */ 6870 * 100 Mbps this bit is always 0) */
6230 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; 6871 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6231 } 6872 }
6873 } else if (hw->phy_type == e1000_phy_ife) {
6874 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6875 &phy_data);
6876 if (ret_val)
6877 return ret_val;
6878 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6879 IFE_PESC_POLARITY_REVERSED_SHIFT;
6232 } 6880 }
6233 return E1000_SUCCESS; 6881 return E1000_SUCCESS;
6234} 6882}
@@ -6256,7 +6904,8 @@ e1000_check_downshift(struct e1000_hw *hw)
6256 6904
6257 DEBUGFUNC("e1000_check_downshift"); 6905 DEBUGFUNC("e1000_check_downshift");
6258 6906
6259 if(hw->phy_type == e1000_phy_igp || 6907 if (hw->phy_type == e1000_phy_igp ||
6908 hw->phy_type == e1000_phy_igp_3 ||
6260 hw->phy_type == e1000_phy_igp_2) { 6909 hw->phy_type == e1000_phy_igp_2) {
6261 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6910 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6262 &phy_data); 6911 &phy_data);
@@ -6273,6 +6922,9 @@ e1000_check_downshift(struct e1000_hw *hw)
6273 6922
6274 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6923 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6275 M88E1000_PSSR_DOWNSHIFT_SHIFT; 6924 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6925 } else if (hw->phy_type == e1000_phy_ife) {
6926 /* e1000_phy_ife supports 10/100 speed only */
6927 hw->speed_downgraded = FALSE;
6276 } 6928 }
6277 6929
6278 return E1000_SUCCESS; 6930 return E1000_SUCCESS;
@@ -6317,7 +6969,9 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6317 6969
6318 if(speed == SPEED_1000) { 6970 if(speed == SPEED_1000) {
6319 6971
6320 e1000_get_cable_length(hw, &min_length, &max_length); 6972 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6973 if (ret_val)
6974 return ret_val;
6321 6975
6322 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 6976 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6323 min_length >= e1000_igp_cable_length_50) { 6977 min_length >= e1000_igp_cable_length_50) {
@@ -6525,20 +7179,27 @@ static int32_t
6525e1000_set_d3_lplu_state(struct e1000_hw *hw, 7179e1000_set_d3_lplu_state(struct e1000_hw *hw,
6526 boolean_t active) 7180 boolean_t active)
6527{ 7181{
7182 uint32_t phy_ctrl = 0;
6528 int32_t ret_val; 7183 int32_t ret_val;
6529 uint16_t phy_data; 7184 uint16_t phy_data;
6530 DEBUGFUNC("e1000_set_d3_lplu_state"); 7185 DEBUGFUNC("e1000_set_d3_lplu_state");
6531 7186
6532 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) 7187 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7188 && hw->phy_type != e1000_phy_igp_3)
6533 return E1000_SUCCESS; 7189 return E1000_SUCCESS;
6534 7190
6535 /* During driver activity LPLU should not be used or it will attain link 7191 /* During driver activity LPLU should not be used or it will attain link
6536 * from the lowest speeds starting from 10Mbps. The capability is used for 7192 * from the lowest speeds starting from 10Mbps. The capability is used for
6537 * Dx transitions and states */ 7193 * Dx transitions and states */
6538 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 7194 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
6539 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 7195 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
6540 if(ret_val) 7196 if (ret_val)
6541 return ret_val; 7197 return ret_val;
7198 } else if (hw->mac_type == e1000_ich8lan) {
7199 /* MAC writes into PHY register based on the state transition
7200 * and start auto-negotiation. SW driver can overwrite the settings
7201 * in CSR PHY power control E1000_PHY_CTRL register. */
7202 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
6542 } else { 7203 } else {
6543 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7204 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6544 if(ret_val) 7205 if(ret_val)
@@ -6553,11 +7214,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6553 if(ret_val) 7214 if(ret_val)
6554 return ret_val; 7215 return ret_val;
6555 } else { 7216 } else {
7217 if (hw->mac_type == e1000_ich8lan) {
7218 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7219 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7220 } else {
6556 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7221 phy_data &= ~IGP02E1000_PM_D3_LPLU;
6557 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7222 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6558 phy_data); 7223 phy_data);
6559 if (ret_val) 7224 if (ret_val)
6560 return ret_val; 7225 return ret_val;
7226 }
6561 } 7227 }
6562 7228
6563 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7229 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
@@ -6593,17 +7259,22 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6593 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7259 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
6594 7260
6595 if(hw->mac_type == e1000_82541_rev_2 || 7261 if(hw->mac_type == e1000_82541_rev_2 ||
6596 hw->mac_type == e1000_82547_rev_2) { 7262 hw->mac_type == e1000_82547_rev_2) {
6597 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7263 phy_data |= IGP01E1000_GMII_FLEX_SPD;
6598 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7264 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6599 if(ret_val) 7265 if(ret_val)
6600 return ret_val; 7266 return ret_val;
6601 } else { 7267 } else {
7268 if (hw->mac_type == e1000_ich8lan) {
7269 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7270 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7271 } else {
6602 phy_data |= IGP02E1000_PM_D3_LPLU; 7272 phy_data |= IGP02E1000_PM_D3_LPLU;
6603 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7273 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6604 phy_data); 7274 phy_data);
6605 if (ret_val) 7275 if (ret_val)
6606 return ret_val; 7276 return ret_val;
7277 }
6607 } 7278 }
6608 7279
6609 /* When LPLU is enabled we should disable SmartSpeed */ 7280 /* When LPLU is enabled we should disable SmartSpeed */
@@ -6638,6 +7309,7 @@ static int32_t
6638e1000_set_d0_lplu_state(struct e1000_hw *hw, 7309e1000_set_d0_lplu_state(struct e1000_hw *hw,
6639 boolean_t active) 7310 boolean_t active)
6640{ 7311{
7312 uint32_t phy_ctrl = 0;
6641 int32_t ret_val; 7313 int32_t ret_val;
6642 uint16_t phy_data; 7314 uint16_t phy_data;
6643 DEBUGFUNC("e1000_set_d0_lplu_state"); 7315 DEBUGFUNC("e1000_set_d0_lplu_state");
@@ -6645,15 +7317,24 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6645 if(hw->mac_type <= e1000_82547_rev_2) 7317 if(hw->mac_type <= e1000_82547_rev_2)
6646 return E1000_SUCCESS; 7318 return E1000_SUCCESS;
6647 7319
7320 if (hw->mac_type == e1000_ich8lan) {
7321 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7322 } else {
6648 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7323 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6649 if(ret_val) 7324 if(ret_val)
6650 return ret_val; 7325 return ret_val;
7326 }
6651 7327
6652 if (!active) { 7328 if (!active) {
7329 if (hw->mac_type == e1000_ich8lan) {
7330 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7331 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7332 } else {
6653 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7333 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6654 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7334 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6655 if (ret_val) 7335 if (ret_val)
6656 return ret_val; 7336 return ret_val;
7337 }
6657 7338
6658 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7339 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6659 * Dx states where the power conservation is most important. During 7340 * Dx states where the power conservation is most important. During
@@ -6686,10 +7367,15 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6686 7367
6687 } else { 7368 } else {
6688 7369
7370 if (hw->mac_type == e1000_ich8lan) {
7371 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7372 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7373 } else {
6689 phy_data |= IGP02E1000_PM_D0_LPLU; 7374 phy_data |= IGP02E1000_PM_D0_LPLU;
6690 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7375 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6691 if (ret_val) 7376 if (ret_val)
6692 return ret_val; 7377 return ret_val;
7378 }
6693 7379
6694 /* When LPLU is enabled we should disable SmartSpeed */ 7380 /* When LPLU is enabled we should disable SmartSpeed */
6695 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7381 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
@@ -6928,8 +7614,10 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
6928 7614
6929 length >>= 2; 7615 length >>= 2;
6930 /* The device driver writes the relevant command block into the ram area. */ 7616 /* The device driver writes the relevant command block into the ram area. */
6931 for (i = 0; i < length; i++) 7617 for (i = 0; i < length; i++) {
6932 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); 7618 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7619 E1000_WRITE_FLUSH(hw);
7620 }
6933 7621
6934 return E1000_SUCCESS; 7622 return E1000_SUCCESS;
6935} 7623}
@@ -6961,15 +7649,18 @@ e1000_mng_write_commit(
6961 * returns - TRUE when the mode is IAMT or FALSE. 7649 * returns - TRUE when the mode is IAMT or FALSE.
6962 ****************************************************************************/ 7650 ****************************************************************************/
6963boolean_t 7651boolean_t
6964e1000_check_mng_mode( 7652e1000_check_mng_mode(struct e1000_hw *hw)
6965 struct e1000_hw *hw)
6966{ 7653{
6967 uint32_t fwsm; 7654 uint32_t fwsm;
6968 7655
6969 fwsm = E1000_READ_REG(hw, FWSM); 7656 fwsm = E1000_READ_REG(hw, FWSM);
6970 7657
6971 if((fwsm & E1000_FWSM_MODE_MASK) == 7658 if (hw->mac_type == e1000_ich8lan) {
6972 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7659 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7660 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7661 return TRUE;
7662 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7663 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6973 return TRUE; 7664 return TRUE;
6974 7665
6975 return FALSE; 7666 return FALSE;
@@ -7209,7 +7900,6 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7209 E1000_WRITE_REG(hw, CTRL, ctrl); 7900 E1000_WRITE_REG(hw, CTRL, ctrl);
7210} 7901}
7211 7902
7212#if 0
7213/*************************************************************************** 7903/***************************************************************************
7214 * 7904 *
7215 * Enables PCI-Express master access. 7905 * Enables PCI-Express master access.
@@ -7233,7 +7923,6 @@ e1000_enable_pciex_master(struct e1000_hw *hw)
7233 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 7923 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7234 E1000_WRITE_REG(hw, CTRL, ctrl); 7924 E1000_WRITE_REG(hw, CTRL, ctrl);
7235} 7925}
7236#endif /* 0 */
7237 7926
7238/******************************************************************************* 7927/*******************************************************************************
7239 * 7928 *
@@ -7299,8 +7988,10 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
7299 case e1000_82572: 7988 case e1000_82572:
7300 case e1000_82573: 7989 case e1000_82573:
7301 case e1000_80003es2lan: 7990 case e1000_80003es2lan:
7302 while(timeout) { 7991 case e1000_ich8lan:
7303 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; 7992 while (timeout) {
7993 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
7994 break;
7304 else msec_delay(1); 7995 else msec_delay(1);
7305 timeout--; 7996 timeout--;
7306 } 7997 }
@@ -7340,7 +8031,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
7340 8031
7341 switch (hw->mac_type) { 8032 switch (hw->mac_type) {
7342 default: 8033 default:
7343 msec_delay(10); 8034 msec_delay_irq(10);
7344 break; 8035 break;
7345 case e1000_80003es2lan: 8036 case e1000_80003es2lan:
7346 /* Separate *_CFG_DONE_* bit for each port */ 8037 /* Separate *_CFG_DONE_* bit for each port */
@@ -7523,6 +8214,13 @@ int32_t
7523e1000_check_phy_reset_block(struct e1000_hw *hw) 8214e1000_check_phy_reset_block(struct e1000_hw *hw)
7524{ 8215{
7525 uint32_t manc = 0; 8216 uint32_t manc = 0;
8217 uint32_t fwsm = 0;
8218
8219 if (hw->mac_type == e1000_ich8lan) {
8220 fwsm = E1000_READ_REG(hw, FWSM);
8221 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8222 : E1000_BLK_PHY_RESET;
8223 }
7526 8224
7527 if (hw->mac_type > e1000_82547_rev_2) 8225 if (hw->mac_type > e1000_82547_rev_2)
7528 manc = E1000_READ_REG(hw, MANC); 8226 manc = E1000_READ_REG(hw, MANC);
@@ -7549,6 +8247,8 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7549 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8247 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
7550 return TRUE; 8248 return TRUE;
7551 break; 8249 break;
8250 case e1000_ich8lan:
8251 return TRUE;
7552 default: 8252 default:
7553 break; 8253 break;
7554 } 8254 }
@@ -7556,4 +8256,846 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7556} 8256}
7557 8257
7558 8258
8259/******************************************************************************
8260 * Configure PCI-Ex no-snoop
8261 *
8262 * hw - Struct containing variables accessed by shared code.
8263 * no_snoop - Bitmap of no-snoop events.
8264 *
8265 * returns: E1000_SUCCESS
8266 *
8267 *****************************************************************************/
8268int32_t
8269e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8270{
8271 uint32_t gcr_reg = 0;
8272
8273 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8274
8275 if (hw->bus_type == e1000_bus_type_unknown)
8276 e1000_get_bus_info(hw);
8277
8278 if (hw->bus_type != e1000_bus_type_pci_express)
8279 return E1000_SUCCESS;
8280
8281 if (no_snoop) {
8282 gcr_reg = E1000_READ_REG(hw, GCR);
8283 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8284 gcr_reg |= no_snoop;
8285 E1000_WRITE_REG(hw, GCR, gcr_reg);
8286 }
8287 if (hw->mac_type == e1000_ich8lan) {
8288 uint32_t ctrl_ext;
8289
8290 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8291
8292 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8293 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8294 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8295 }
8296
8297 return E1000_SUCCESS;
8298}
8299
8300/***************************************************************************
8301 *
8302 * Get software semaphore FLAG bit (SWFLAG).
8303 * SWFLAG is used to synchronize the access to all shared resource between
8304 * SW, FW and HW.
8305 *
8306 * hw: Struct containing variables accessed by shared code
8307 *
8308 ***************************************************************************/
8309int32_t
8310e1000_get_software_flag(struct e1000_hw *hw)
8311{
8312 int32_t timeout = PHY_CFG_TIMEOUT;
8313 uint32_t extcnf_ctrl;
8314
8315 DEBUGFUNC("e1000_get_software_flag");
8316
8317 if (hw->mac_type == e1000_ich8lan) {
8318 while (timeout) {
8319 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8320 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8321 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8322
8323 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8324 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8325 break;
8326 msec_delay_irq(1);
8327 timeout--;
8328 }
8329
8330 if (!timeout) {
8331 DEBUGOUT("FW or HW locks the resource too long.\n");
8332 return -E1000_ERR_CONFIG;
8333 }
8334 }
8335
8336 return E1000_SUCCESS;
8337}
8338
8339/***************************************************************************
8340 *
8341 * Release software semaphore FLAG bit (SWFLAG).
8342 * SWFLAG is used to synchronize the access to all shared resource between
8343 * SW, FW and HW.
8344 *
8345 * hw: Struct containing variables accessed by shared code
8346 *
8347 ***************************************************************************/
8348void
8349e1000_release_software_flag(struct e1000_hw *hw)
8350{
8351 uint32_t extcnf_ctrl;
8352
8353 DEBUGFUNC("e1000_release_software_flag");
8354
8355 if (hw->mac_type == e1000_ich8lan) {
8356 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8357 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8358 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8359 }
8360
8361 return;
8362}
8363
8364/***************************************************************************
8365 *
8366 * Disable dynamic power down mode in ife PHY.
8367 * It can be used to workaround band-gap problem.
8368 *
8369 * hw: Struct containing variables accessed by shared code
8370 *
8371 ***************************************************************************/
8372int32_t
8373e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8374{
8375 uint16_t phy_data;
8376 int32_t ret_val = E1000_SUCCESS;
8377
8378 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8379
8380 if (hw->phy_type == e1000_phy_ife) {
8381 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8382 if (ret_val)
8383 return ret_val;
8384
8385 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8386 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8387 }
8388
8389 return ret_val;
8390}
8391
8392/***************************************************************************
8393 *
8394 * Enable dynamic power down mode in ife PHY.
8395 * It can be used to workaround band-gap problem.
8396 *
8397 * hw: Struct containing variables accessed by shared code
8398 *
8399 ***************************************************************************/
8400int32_t
8401e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8402{
8403 uint16_t phy_data;
8404 int32_t ret_val = E1000_SUCCESS;
8405
8406 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8407
8408 if (hw->phy_type == e1000_phy_ife) {
8409 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8410 if (ret_val)
8411 return ret_val;
8412
8413 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8414 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8415 }
8416
8417 return ret_val;
8418}
8419
8420/******************************************************************************
8421 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8422 * register.
8423 *
8424 * hw - Struct containing variables accessed by shared code
8425 * offset - offset of word in the EEPROM to read
8426 * data - word read from the EEPROM
8427 * words - number of words to read
8428 *****************************************************************************/
8429int32_t
8430e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8431 uint16_t *data)
8432{
8433 int32_t error = E1000_SUCCESS;
8434 uint32_t flash_bank = 0;
8435 uint32_t act_offset = 0;
8436 uint32_t bank_offset = 0;
8437 uint16_t word = 0;
8438 uint16_t i = 0;
8439
8440 /* We need to know which is the valid flash bank. In the event
8441 * that we didn't allocate eeprom_shadow_ram, we may not be
8442 * managing flash_bank. So it cannot be trusted and needs
8443 * to be updated with each read.
8444 */
8445 /* Value of bit 22 corresponds to the flash bank we're on. */
8446 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8447
8448 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8449 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8450
8451 error = e1000_get_software_flag(hw);
8452 if (error != E1000_SUCCESS)
8453 return error;
8454
8455 for (i = 0; i < words; i++) {
8456 if (hw->eeprom_shadow_ram != NULL &&
8457 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8458 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8459 } else {
8460 /* The NVM part needs a byte offset, hence * 2 */
8461 act_offset = bank_offset + ((offset + i) * 2);
8462 error = e1000_read_ich8_word(hw, act_offset, &word);
8463 if (error != E1000_SUCCESS)
8464 break;
8465 data[i] = word;
8466 }
8467 }
8468
8469 e1000_release_software_flag(hw);
8470
8471 return error;
8472}
8473
8474/******************************************************************************
8475 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8476 * register. Actually, writes are written to the shadow ram cache in the hw
8477 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8478 * the NVM, which occurs when the NVM checksum is updated.
8479 *
8480 * hw - Struct containing variables accessed by shared code
8481 * offset - offset of word in the EEPROM to write
8482 * words - number of words to write
8483 * data - words to write to the EEPROM
8484 *****************************************************************************/
8485int32_t
8486e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8487 uint16_t *data)
8488{
8489 uint32_t i = 0;
8490 int32_t error = E1000_SUCCESS;
8491
8492 error = e1000_get_software_flag(hw);
8493 if (error != E1000_SUCCESS)
8494 return error;
8495
8496 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8497 * allocated. Subsequent reads to the modified words are read from
8498 * this cached structure as well. Writes will only go into this
8499 * cached structure unless it's followed by a call to
8500 * e1000_update_eeprom_checksum() where it will commit the changes
8501 * and clear the "modified" field.
8502 */
8503 if (hw->eeprom_shadow_ram != NULL) {
8504 for (i = 0; i < words; i++) {
8505 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8506 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8507 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8508 } else {
8509 error = -E1000_ERR_EEPROM;
8510 break;
8511 }
8512 }
8513 } else {
8514 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8515 * as they don't perform any NVM writes. An attempt in doing so
8516 * will result in this error.
8517 */
8518 error = -E1000_ERR_EEPROM;
8519 }
8520
8521 e1000_release_software_flag(hw);
8522
8523 return error;
8524}
8525
8526/******************************************************************************
8527 * This function does initial flash setup so that a new read/write/erase cycle
8528 * can be started.
8529 *
8530 * hw - The pointer to the hw structure
8531 ****************************************************************************/
8532int32_t
8533e1000_ich8_cycle_init(struct e1000_hw *hw)
8534{
8535 union ich8_hws_flash_status hsfsts;
8536 int32_t error = E1000_ERR_EEPROM;
8537 int32_t i = 0;
8538
8539 DEBUGFUNC("e1000_ich8_cycle_init");
8540
8541 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8542
8543 /* May be check the Flash Des Valid bit in Hw status */
8544 if (hsfsts.hsf_status.fldesvalid == 0) {
8545 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8546 return error;
8547 }
8548
8549 /* Clear FCERR in Hw status by writing 1 */
8550 /* Clear DAEL in Hw status by writing a 1 */
8551 hsfsts.hsf_status.flcerr = 1;
8552 hsfsts.hsf_status.dael = 1;
8553
8554 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8555
8556 /* Either we should have a hardware SPI cycle in progress bit to check
8557 * against, in order to start a new cycle or FDONE bit should be changed
8558 * in the hardware so that it is 1 after harware reset, which can then be
8559 * used as an indication whether a cycle is in progress or has been
8560 * completed .. we should also have some software semaphore mechanism to
8561 * guard FDONE or the cycle in progress bit so that two threads access to
8562 * those bits can be sequentiallized or a way so that 2 threads dont
8563 * start the cycle at the same time */
8564
8565 if (hsfsts.hsf_status.flcinprog == 0) {
8566 /* There is no cycle running at present, so we can start a cycle */
8567 /* Begin by setting Flash Cycle Done. */
8568 hsfsts.hsf_status.flcdone = 1;
8569 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8570 error = E1000_SUCCESS;
8571 } else {
8572 /* otherwise poll for sometime so the current cycle has a chance
8573 * to end before giving up. */
8574 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8575 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8576 if (hsfsts.hsf_status.flcinprog == 0) {
8577 error = E1000_SUCCESS;
8578 break;
8579 }
8580 udelay(1);
8581 }
8582 if (error == E1000_SUCCESS) {
8583 /* Successful in waiting for previous cycle to timeout,
8584 * now set the Flash Cycle Done. */
8585 hsfsts.hsf_status.flcdone = 1;
8586 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8587 } else {
8588 DEBUGOUT("Flash controller busy, cannot get access");
8589 }
8590 }
8591 return error;
8592}
8593
8594/******************************************************************************
8595 * This function starts a flash cycle and waits for its completion
8596 *
8597 * hw - The pointer to the hw structure
8598 ****************************************************************************/
8599int32_t
8600e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8601{
8602 union ich8_hws_flash_ctrl hsflctl;
8603 union ich8_hws_flash_status hsfsts;
8604 int32_t error = E1000_ERR_EEPROM;
8605 uint32_t i = 0;
8606
8607 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8608 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8609 hsflctl.hsf_ctrl.flcgo = 1;
8610 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8611
8612 /* wait till FDONE bit is set to 1 */
8613 do {
8614 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8615 if (hsfsts.hsf_status.flcdone == 1)
8616 break;
8617 udelay(1);
8618 i++;
8619 } while (i < timeout);
8620 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8621 error = E1000_SUCCESS;
8622 }
8623 return error;
8624}
8625
8626/******************************************************************************
8627 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8628 *
8629 * hw - The pointer to the hw structure
8630 * index - The index of the byte or word to read.
8631 * size - Size of data to read, 1=byte 2=word
8632 * data - Pointer to the word to store the value read.
8633 *****************************************************************************/
8634int32_t
8635e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8636 uint32_t size, uint16_t* data)
8637{
8638 union ich8_hws_flash_status hsfsts;
8639 union ich8_hws_flash_ctrl hsflctl;
8640 uint32_t flash_linear_address;
8641 uint32_t flash_data = 0;
8642 int32_t error = -E1000_ERR_EEPROM;
8643 int32_t count = 0;
8644
8645 DEBUGFUNC("e1000_read_ich8_data");
8646
8647 if (size < 1 || size > 2 || data == 0x0 ||
8648 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8649 return error;
8650
8651 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8652 hw->flash_base_addr;
8653
8654 do {
8655 udelay(1);
8656 /* Steps */
8657 error = e1000_ich8_cycle_init(hw);
8658 if (error != E1000_SUCCESS)
8659 break;
8660
8661 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8662 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8663 hsflctl.hsf_ctrl.fldbcount = size - 1;
8664 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8665 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8666
8667 /* Write the last 24 bits of index into Flash Linear address field in
8668 * Flash Address */
8669 /* TODO: TBD maybe check the index against the size of flash */
8670
8671 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8672
8673 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8674
8675 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8676 * sequence a few more times, else read in (shift in) the Flash Data0,
8677 * the order is least significant byte first msb to lsb */
8678 if (error == E1000_SUCCESS) {
8679 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8680 if (size == 1) {
8681 *data = (uint8_t)(flash_data & 0x000000FF);
8682 } else if (size == 2) {
8683 *data = (uint16_t)(flash_data & 0x0000FFFF);
8684 }
8685 break;
8686 } else {
8687 /* If we've gotten here, then things are probably completely hosed,
8688 * but if the error condition is detected, it won't hurt to give
8689 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8690 */
8691 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8692 if (hsfsts.hsf_status.flcerr == 1) {
8693 /* Repeat for some time before giving up. */
8694 continue;
8695 } else if (hsfsts.hsf_status.flcdone == 0) {
8696 DEBUGOUT("Timeout error - flash cycle did not complete.");
8697 break;
8698 }
8699 }
8700 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8701
8702 return error;
8703}
8704
8705/******************************************************************************
8706 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8707 *
8708 * hw - The pointer to the hw structure
8709 * index - The index of the byte/word to read.
8710 * size - Size of data to read, 1=byte 2=word
8711 * data - The byte(s) to write to the NVM.
8712 *****************************************************************************/
8713int32_t
8714e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8715 uint16_t data)
8716{
8717 union ich8_hws_flash_status hsfsts;
8718 union ich8_hws_flash_ctrl hsflctl;
8719 uint32_t flash_linear_address;
8720 uint32_t flash_data = 0;
8721 int32_t error = -E1000_ERR_EEPROM;
8722 int32_t count = 0;
8723
8724 DEBUGFUNC("e1000_write_ich8_data");
8725
8726 if (size < 1 || size > 2 || data > size * 0xff ||
8727 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8728 return error;
8729
8730 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8731 hw->flash_base_addr;
8732
8733 do {
8734 udelay(1);
8735 /* Steps */
8736 error = e1000_ich8_cycle_init(hw);
8737 if (error != E1000_SUCCESS)
8738 break;
8739
8740 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8741 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8742 hsflctl.hsf_ctrl.fldbcount = size -1;
8743 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8744 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8745
8746 /* Write the last 24 bits of index into Flash Linear address field in
8747 * Flash Address */
8748 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8749
8750 if (size == 1)
8751 flash_data = (uint32_t)data & 0x00FF;
8752 else
8753 flash_data = (uint32_t)data;
8754
8755 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8756
8757 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8758 * sequence a few more times else done */
8759 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8760 if (error == E1000_SUCCESS) {
8761 break;
8762 } else {
8763 /* If we're here, then things are most likely completely hosed,
8764 * but if the error condition is detected, it won't hurt to give
8765 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8766 */
8767 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8768 if (hsfsts.hsf_status.flcerr == 1) {
8769 /* Repeat for some time before giving up. */
8770 continue;
8771 } else if (hsfsts.hsf_status.flcdone == 0) {
8772 DEBUGOUT("Timeout error - flash cycle did not complete.");
8773 break;
8774 }
8775 }
8776 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8777
8778 return error;
8779}
8780
8781/******************************************************************************
8782 * Reads a single byte from the NVM using the ICH8 flash access registers.
8783 *
8784 * hw - pointer to e1000_hw structure
8785 * index - The index of the byte to read.
8786 * data - Pointer to a byte to store the value read.
8787 *****************************************************************************/
8788int32_t
8789e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8790{
8791 int32_t status = E1000_SUCCESS;
8792 uint16_t word = 0;
8793
8794 status = e1000_read_ich8_data(hw, index, 1, &word);
8795 if (status == E1000_SUCCESS) {
8796 *data = (uint8_t)word;
8797 }
8798
8799 return status;
8800}
8801
8802/******************************************************************************
8803 * Writes a single byte to the NVM using the ICH8 flash access registers.
8804 * Performs verification by reading back the value and then going through
8805 * a retry algorithm before giving up.
8806 *
8807 * hw - pointer to e1000_hw structure
8808 * index - The index of the byte to write.
8809 * byte - The byte to write to the NVM.
8810 *****************************************************************************/
8811int32_t
8812e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8813{
8814 int32_t error = E1000_SUCCESS;
8815 int32_t program_retries;
8816 uint8_t temp_byte;
8817
8818 e1000_write_ich8_byte(hw, index, byte);
8819 udelay(100);
8820
8821 for (program_retries = 0; program_retries < 100; program_retries++) {
8822 e1000_read_ich8_byte(hw, index, &temp_byte);
8823 if (temp_byte == byte)
8824 break;
8825 udelay(10);
8826 e1000_write_ich8_byte(hw, index, byte);
8827 udelay(100);
8828 }
8829 if (program_retries == 100)
8830 error = E1000_ERR_EEPROM;
8831
8832 return error;
8833}
8834
8835/******************************************************************************
8836 * Writes a single byte to the NVM using the ICH8 flash access registers.
8837 *
8838 * hw - pointer to e1000_hw structure
8839 * index - The index of the byte to read.
8840 * data - The byte to write to the NVM.
8841 *****************************************************************************/
8842int32_t
8843e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8844{
8845 int32_t status = E1000_SUCCESS;
8846 uint16_t word = (uint16_t)data;
8847
8848 status = e1000_write_ich8_data(hw, index, 1, word);
8849
8850 return status;
8851}
8852
8853/******************************************************************************
8854 * Reads a word from the NVM using the ICH8 flash access registers.
8855 *
8856 * hw - pointer to e1000_hw structure
8857 * index - The starting byte index of the word to read.
8858 * data - Pointer to a word to store the value read.
8859 *****************************************************************************/
8860int32_t
8861e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8862{
8863 int32_t status = E1000_SUCCESS;
8864 status = e1000_read_ich8_data(hw, index, 2, data);
8865 return status;
8866}
8867
8868/******************************************************************************
8869 * Writes a word to the NVM using the ICH8 flash access registers.
8870 *
8871 * hw - pointer to e1000_hw structure
8872 * index - The starting byte index of the word to read.
8873 * data - The word to write to the NVM.
8874 *****************************************************************************/
8875int32_t
8876e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8877{
8878 int32_t status = E1000_SUCCESS;
8879 status = e1000_write_ich8_data(hw, index, 2, data);
8880 return status;
8881}
8882
8883/******************************************************************************
8884 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8885 * segment N is 4096 * N + flash_reg_addr.
8886 *
8887 * hw - pointer to e1000_hw structure
8888 * segment - 0 for first segment, 1 for second segment, etc.
8889 *****************************************************************************/
8890int32_t
8891e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8892{
8893 union ich8_hws_flash_status hsfsts;
8894 union ich8_hws_flash_ctrl hsflctl;
8895 uint32_t flash_linear_address;
8896 int32_t count = 0;
8897 int32_t error = E1000_ERR_EEPROM;
8898 int32_t iteration, seg_size;
8899 int32_t sector_size;
8900 int32_t j = 0;
8901 int32_t error_flag = 0;
8902
8903 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8904
8905 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8906 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8907 * consecutive sectors. The start index for the nth Hw sector can be
8908 * calculated as = segment * 4096 + n * 256
8909 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8910 * The start index for the nth Hw sector can be calculated
8911 * as = segment * 4096
8912 * 10: Error condition
8913 * 11: The Hw sector size is much bigger than the size asked to
8914 * erase...error condition */
8915 if (hsfsts.hsf_status.berasesz == 0x0) {
8916 /* Hw sector size 256 */
8917 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8918 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8919 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8920 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8921 iteration = 1;
8922 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8923 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8924 iteration = 1;
8925 } else {
8926 return error;
8927 }
8928
8929 for (j = 0; j < iteration ; j++) {
8930 do {
8931 count++;
8932 /* Steps */
8933 error = e1000_ich8_cycle_init(hw);
8934 if (error != E1000_SUCCESS) {
8935 error_flag = 1;
8936 break;
8937 }
8938
8939 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8940 * Control */
8941 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8942 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8943 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8944
8945 /* Write the last 24 bits of an index within the block into Flash
8946 * Linear address field in Flash Address. This probably needs to
8947 * be calculated here based off the on-chip segment size and the
8948 * software segment size assumed (4K) */
8949 /* TBD */
8950 flash_linear_address = segment * sector_size + j * seg_size;
8951 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8952 flash_linear_address += hw->flash_base_addr;
8953
8954 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8955
8956 error = e1000_ich8_flash_cycle(hw, 1000000);
8957 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8958 * sequence a few more times else Done */
8959 if (error == E1000_SUCCESS) {
8960 break;
8961 } else {
8962 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8963 if (hsfsts.hsf_status.flcerr == 1) {
8964 /* repeat for some time before giving up */
8965 continue;
8966 } else if (hsfsts.hsf_status.flcdone == 0) {
8967 error_flag = 1;
8968 break;
8969 }
8970 }
8971 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8972 if (error_flag == 1)
8973 break;
8974 }
8975 if (error_flag != 1)
8976 error = E1000_SUCCESS;
8977 return error;
8978}
8979
8980/******************************************************************************
8981 *
8982 * Reverse duplex setting without breaking the link.
8983 *
8984 * hw: Struct containing variables accessed by shared code
8985 *
8986 *****************************************************************************/
8987int32_t
8988e1000_duplex_reversal(struct e1000_hw *hw)
8989{
8990 int32_t ret_val;
8991 uint16_t phy_data;
8992
8993 if (hw->phy_type != e1000_phy_igp_3)
8994 return E1000_SUCCESS;
8995
8996 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8997 if (ret_val)
8998 return ret_val;
8999
9000 phy_data ^= MII_CR_FULL_DUPLEX;
9001
9002 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9003 if (ret_val)
9004 return ret_val;
9005
9006 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9007 if (ret_val)
9008 return ret_val;
9009
9010 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9011 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9012
9013 return ret_val;
9014}
9015
9016int32_t
9017e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9018 uint32_t cnf_base_addr, uint32_t cnf_size)
9019{
9020 uint32_t ret_val = E1000_SUCCESS;
9021 uint16_t word_addr, reg_data, reg_addr;
9022 uint16_t i;
9023
9024 /* cnf_base_addr is in DWORD */
9025 word_addr = (uint16_t)(cnf_base_addr << 1);
9026
9027 /* cnf_size is returned in size of dwords */
9028 for (i = 0; i < cnf_size; i++) {
9029 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9030 if (ret_val)
9031 return ret_val;
9032
9033 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9034 if (ret_val)
9035 return ret_val;
9036
9037 ret_val = e1000_get_software_flag(hw);
9038 if (ret_val != E1000_SUCCESS)
9039 return ret_val;
9040
9041 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9042
9043 e1000_release_software_flag(hw);
9044 }
9045
9046 return ret_val;
9047}
9048
9049
9050int32_t
9051e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9052{
9053 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9054
9055 if (hw->phy_type != e1000_phy_igp_3)
9056 return E1000_SUCCESS;
9057
9058 /* Check if SW needs configure the PHY */
9059 reg_data = E1000_READ_REG(hw, FEXTNVM);
9060 if (!(reg_data & FEXTNVM_SW_CONFIG))
9061 return E1000_SUCCESS;
9062
9063 /* Wait for basic configuration completes before proceeding*/
9064 loop = 0;
9065 do {
9066 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9067 udelay(100);
9068 loop++;
9069 } while ((!reg_data) && (loop < 50));
9070
9071 /* Clear the Init Done bit for the next init event */
9072 reg_data = E1000_READ_REG(hw, STATUS);
9073 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9074 E1000_WRITE_REG(hw, STATUS, reg_data);
9075
9076 /* Make sure HW does not configure LCD from PHY extended configuration
9077 before SW configuration */
9078 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9079 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9080 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9081 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9082 cnf_size >>= 16;
9083 if (cnf_size) {
9084 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9085 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9086 /* cnf_base_addr is in DWORD */
9087 cnf_base_addr >>= 16;
9088
9089 /* Configure LCD from extended configuration region. */
9090 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9091 cnf_size);
9092 if (ret_val)
9093 return ret_val;
9094 }
9095 }
9096
9097 return E1000_SUCCESS;
9098}
9099
9100
7559 9101
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 467c9ed944f8..f9341e3276b3 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -62,6 +62,7 @@ typedef enum {
62 e1000_82572, 62 e1000_82572,
63 e1000_82573, 63 e1000_82573,
64 e1000_80003es2lan, 64 e1000_80003es2lan,
65 e1000_ich8lan,
65 e1000_num_macs 66 e1000_num_macs
66} e1000_mac_type; 67} e1000_mac_type;
67 68
@@ -70,6 +71,7 @@ typedef enum {
70 e1000_eeprom_spi, 71 e1000_eeprom_spi,
71 e1000_eeprom_microwire, 72 e1000_eeprom_microwire,
72 e1000_eeprom_flash, 73 e1000_eeprom_flash,
74 e1000_eeprom_ich8,
73 e1000_eeprom_none, /* No NVM support */ 75 e1000_eeprom_none, /* No NVM support */
74 e1000_num_eeprom_types 76 e1000_num_eeprom_types
75} e1000_eeprom_type; 77} e1000_eeprom_type;
@@ -98,6 +100,11 @@ typedef enum {
98 e1000_fc_default = 0xFF 100 e1000_fc_default = 0xFF
99} e1000_fc_type; 101} e1000_fc_type;
100 102
103struct e1000_shadow_ram {
104 uint16_t eeprom_word;
105 boolean_t modified;
106};
107
101/* PCI bus types */ 108/* PCI bus types */
102typedef enum { 109typedef enum {
103 e1000_bus_type_unknown = 0, 110 e1000_bus_type_unknown = 0,
@@ -218,6 +225,8 @@ typedef enum {
218 e1000_phy_igp, 225 e1000_phy_igp,
219 e1000_phy_igp_2, 226 e1000_phy_igp_2,
220 e1000_phy_gg82563, 227 e1000_phy_gg82563,
228 e1000_phy_igp_3,
229 e1000_phy_ife,
221 e1000_phy_undefined = 0xFF 230 e1000_phy_undefined = 0xFF
222} e1000_phy_type; 231} e1000_phy_type;
223 232
@@ -313,6 +322,10 @@ int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy
313int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 322int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
314int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 323int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
315int32_t e1000_phy_reset(struct e1000_hw *hw); 324int32_t e1000_phy_reset(struct e1000_hw *hw);
325void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
326int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
327int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
328int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
316int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 329int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
317int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 330int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
318int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); 331int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
@@ -331,6 +344,7 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
331#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 344#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
332#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 345#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
333#define E1000_MNG_IAMT_MODE 0x3 346#define E1000_MNG_IAMT_MODE 0x3
347#define E1000_MNG_ICH_IAMT_MODE 0x2
334#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 348#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
335 349
336#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 350#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
@@ -388,6 +402,8 @@ int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
388int32_t e1000_read_mac_addr(struct e1000_hw * hw); 402int32_t e1000_read_mac_addr(struct e1000_hw * hw);
389int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 403int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
390void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 404void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
405void e1000_release_software_flag(struct e1000_hw *hw);
406int32_t e1000_get_software_flag(struct e1000_hw *hw);
391 407
392/* Filters (multicast, vlan, receive) */ 408/* Filters (multicast, vlan, receive) */
393void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count); 409void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
@@ -401,6 +417,7 @@ int32_t e1000_setup_led(struct e1000_hw *hw);
401int32_t e1000_cleanup_led(struct e1000_hw *hw); 417int32_t e1000_cleanup_led(struct e1000_hw *hw);
402int32_t e1000_led_on(struct e1000_hw *hw); 418int32_t e1000_led_on(struct e1000_hw *hw);
403int32_t e1000_led_off(struct e1000_hw *hw); 419int32_t e1000_led_off(struct e1000_hw *hw);
420int32_t e1000_blink_led_start(struct e1000_hw *hw);
404 421
405/* Adaptive IFS Functions */ 422/* Adaptive IFS Functions */
406 423
@@ -422,6 +439,29 @@ int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
422int32_t e1000_get_software_semaphore(struct e1000_hw *hw); 439int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
423void e1000_release_software_semaphore(struct e1000_hw *hw); 440void e1000_release_software_semaphore(struct e1000_hw *hw);
424int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 441int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
442int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
443
444int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
445 uint8_t *data);
446int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
447 uint8_t byte);
448int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
449 uint8_t byte);
450int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
451 uint16_t *data);
452int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
453 uint32_t size, uint16_t *data);
454int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
455 uint16_t words, uint16_t *data);
456int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
457 uint16_t words, uint16_t *data);
458int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment);
459
460
461#define E1000_READ_REG_IO(a, reg) \
462 e1000_read_reg_io((a), E1000_##reg)
463#define E1000_WRITE_REG_IO(a, reg, val) \
464 e1000_write_reg_io((a), E1000_##reg, val)
425 465
426/* PCI Device IDs */ 466/* PCI Device IDs */
427#define E1000_DEV_ID_82542 0x1000 467#define E1000_DEV_ID_82542 0x1000
@@ -446,6 +486,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
446#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 486#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
447#define E1000_DEV_ID_82541EI 0x1013 487#define E1000_DEV_ID_82541EI 0x1013
448#define E1000_DEV_ID_82541EI_MOBILE 0x1018 488#define E1000_DEV_ID_82541EI_MOBILE 0x1018
489#define E1000_DEV_ID_82541ER_LOM 0x1014
449#define E1000_DEV_ID_82541ER 0x1078 490#define E1000_DEV_ID_82541ER 0x1078
450#define E1000_DEV_ID_82547GI 0x1075 491#define E1000_DEV_ID_82547GI 0x1075
451#define E1000_DEV_ID_82541GI 0x1076 492#define E1000_DEV_ID_82541GI 0x1076
@@ -457,18 +498,28 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
457#define E1000_DEV_ID_82546GB_PCIE 0x108A 498#define E1000_DEV_ID_82546GB_PCIE 0x108A
458#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 499#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
459#define E1000_DEV_ID_82547EI 0x1019 500#define E1000_DEV_ID_82547EI 0x1019
501#define E1000_DEV_ID_82547EI_MOBILE 0x101A
460#define E1000_DEV_ID_82571EB_COPPER 0x105E 502#define E1000_DEV_ID_82571EB_COPPER 0x105E
461#define E1000_DEV_ID_82571EB_FIBER 0x105F 503#define E1000_DEV_ID_82571EB_FIBER 0x105F
462#define E1000_DEV_ID_82571EB_SERDES 0x1060 504#define E1000_DEV_ID_82571EB_SERDES 0x1060
463#define E1000_DEV_ID_82572EI_COPPER 0x107D 505#define E1000_DEV_ID_82572EI_COPPER 0x107D
464#define E1000_DEV_ID_82572EI_FIBER 0x107E 506#define E1000_DEV_ID_82572EI_FIBER 0x107E
465#define E1000_DEV_ID_82572EI_SERDES 0x107F 507#define E1000_DEV_ID_82572EI_SERDES 0x107F
508#define E1000_DEV_ID_82572EI 0x10B9
466#define E1000_DEV_ID_82573E 0x108B 509#define E1000_DEV_ID_82573E 0x108B
467#define E1000_DEV_ID_82573E_IAMT 0x108C 510#define E1000_DEV_ID_82573E_IAMT 0x108C
468#define E1000_DEV_ID_82573L 0x109A 511#define E1000_DEV_ID_82573L 0x109A
469#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 512#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
470#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 513#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
471#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 514#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
515#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
516#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
517
518#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
519#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
520#define E1000_DEV_ID_ICH8_IGP_C 0x104B
521#define E1000_DEV_ID_ICH8_IFE 0x104C
522#define E1000_DEV_ID_ICH8_IGP_M 0x104D
472 523
473 524
474#define NODE_ADDRESS_SIZE 6 525#define NODE_ADDRESS_SIZE 6
@@ -539,6 +590,14 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
539 E1000_IMS_RXSEQ | \ 590 E1000_IMS_RXSEQ | \
540 E1000_IMS_LSC) 591 E1000_IMS_LSC)
541 592
593/* Additional interrupts need to be handled for e1000_ich8lan:
594 DSW = The FW changed the status of the DISSW bit in FWSM
595 PHYINT = The LAN connected device generates an interrupt
596 EPRST = Manageability reset event */
597#define IMS_ICH8LAN_ENABLE_MASK (\
598 E1000_IMS_DSW | \
599 E1000_IMS_PHYINT | \
600 E1000_IMS_EPRST)
542 601
543/* Number of high/low register pairs in the RAR. The RAR (Receive Address 602/* Number of high/low register pairs in the RAR. The RAR (Receive Address
544 * Registers) holds the directed and multicast addresses that we monitor. We 603 * Registers) holds the directed and multicast addresses that we monitor. We
@@ -546,6 +605,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
546 * E1000_RAR_ENTRIES - 1 multicast addresses. 605 * E1000_RAR_ENTRIES - 1 multicast addresses.
547 */ 606 */
548#define E1000_RAR_ENTRIES 15 607#define E1000_RAR_ENTRIES 15
608#define E1000_RAR_ENTRIES_ICH8LAN 7
549 609
550#define MIN_NUMBER_OF_DESCRIPTORS 8 610#define MIN_NUMBER_OF_DESCRIPTORS 8
551#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 611#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
@@ -767,6 +827,9 @@ struct e1000_data_desc {
767#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 827#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
768#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 828#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
769 829
830#define E1000_NUM_UNICAST_ICH8LAN 7
831#define E1000_MC_TBL_SIZE_ICH8LAN 32
832
770 833
771/* Receive Address Register */ 834/* Receive Address Register */
772struct e1000_rar { 835struct e1000_rar {
@@ -776,6 +839,7 @@ struct e1000_rar {
776 839
777/* Number of entries in the Multicast Table Array (MTA). */ 840/* Number of entries in the Multicast Table Array (MTA). */
778#define E1000_NUM_MTA_REGISTERS 128 841#define E1000_NUM_MTA_REGISTERS 128
842#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
779 843
780/* IPv4 Address Table Entry */ 844/* IPv4 Address Table Entry */
781struct e1000_ipv4_at_entry { 845struct e1000_ipv4_at_entry {
@@ -786,6 +850,7 @@ struct e1000_ipv4_at_entry {
786/* Four wakeup IP addresses are supported */ 850/* Four wakeup IP addresses are supported */
787#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 851#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
788#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 852#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
853#define E1000_IP4AT_SIZE_ICH8LAN 3
789#define E1000_IP6AT_SIZE 1 854#define E1000_IP6AT_SIZE 1
790 855
791/* IPv6 Address Table Entry */ 856/* IPv6 Address Table Entry */
@@ -844,6 +909,7 @@ struct e1000_ffvt_entry {
844#define E1000_FLA 0x0001C /* Flash Access - RW */ 909#define E1000_FLA 0x0001C /* Flash Access - RW */
845#define E1000_MDIC 0x00020 /* MDI Control - RW */ 910#define E1000_MDIC 0x00020 /* MDI Control - RW */
846#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 911#define E1000_SCTL 0x00024 /* SerDes Control - RW */
912#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
847#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 913#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
848#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 914#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
849#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 915#define E1000_FCT 0x00030 /* Flow Control Type - RW */
@@ -872,6 +938,8 @@ struct e1000_ffvt_entry {
872#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 938#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
873#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 939#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
874#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 940#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
941#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
942#define FEXTNVM_SW_CONFIG 0x0001
875#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 943#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
876#define E1000_PBS 0x01008 /* Packet Buffer Size */ 944#define E1000_PBS 0x01008 /* Packet Buffer Size */
877#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 945#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
@@ -899,11 +967,13 @@ struct e1000_ffvt_entry {
899#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 967#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
900#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 968#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
901#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 969#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
902#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 970#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
971#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
903#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 972#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
904#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 973#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
905#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 974#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
906#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 975#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
976#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
907#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 977#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
908#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 978#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
909#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 979#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
@@ -1050,6 +1120,7 @@ struct e1000_ffvt_entry {
1050#define E1000_82542_FLA E1000_FLA 1120#define E1000_82542_FLA E1000_FLA
1051#define E1000_82542_MDIC E1000_MDIC 1121#define E1000_82542_MDIC E1000_MDIC
1052#define E1000_82542_SCTL E1000_SCTL 1122#define E1000_82542_SCTL E1000_SCTL
1123#define E1000_82542_FEXTNVM E1000_FEXTNVM
1053#define E1000_82542_FCAL E1000_FCAL 1124#define E1000_82542_FCAL E1000_FCAL
1054#define E1000_82542_FCAH E1000_FCAH 1125#define E1000_82542_FCAH E1000_FCAH
1055#define E1000_82542_FCT E1000_FCT 1126#define E1000_82542_FCT E1000_FCT
@@ -1073,6 +1144,19 @@ struct e1000_ffvt_entry {
1073#define E1000_82542_RDLEN0 E1000_82542_RDLEN 1144#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1074#define E1000_82542_RDH0 E1000_82542_RDH 1145#define E1000_82542_RDH0 E1000_82542_RDH
1075#define E1000_82542_RDT0 E1000_82542_RDT 1146#define E1000_82542_RDT0 E1000_82542_RDT
1147#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1148 * RX Control - RW */
1149#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1150#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1151#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1152#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1153#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1154#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1155#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1156#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1157#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1158#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1159#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1076#define E1000_82542_RDTR1 0x00130 1160#define E1000_82542_RDTR1 0x00130
1077#define E1000_82542_RDBAL1 0x00138 1161#define E1000_82542_RDBAL1 0x00138
1078#define E1000_82542_RDBAH1 0x0013C 1162#define E1000_82542_RDBAH1 0x0013C
@@ -1110,11 +1194,14 @@ struct e1000_ffvt_entry {
1110#define E1000_82542_FLOP E1000_FLOP 1194#define E1000_82542_FLOP E1000_FLOP
1111#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL 1195#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1112#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE 1196#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1197#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1113#define E1000_82542_ERT E1000_ERT 1198#define E1000_82542_ERT E1000_ERT
1114#define E1000_82542_RXDCTL E1000_RXDCTL 1199#define E1000_82542_RXDCTL E1000_RXDCTL
1200#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1115#define E1000_82542_RADV E1000_RADV 1201#define E1000_82542_RADV E1000_RADV
1116#define E1000_82542_RSRPD E1000_RSRPD 1202#define E1000_82542_RSRPD E1000_RSRPD
1117#define E1000_82542_TXDMAC E1000_TXDMAC 1203#define E1000_82542_TXDMAC E1000_TXDMAC
1204#define E1000_82542_KABGTXD E1000_KABGTXD
1118#define E1000_82542_TDFHS E1000_TDFHS 1205#define E1000_82542_TDFHS E1000_TDFHS
1119#define E1000_82542_TDFTS E1000_TDFTS 1206#define E1000_82542_TDFTS E1000_TDFTS
1120#define E1000_82542_TDFPC E1000_TDFPC 1207#define E1000_82542_TDFPC E1000_TDFPC
@@ -1310,13 +1397,16 @@ struct e1000_hw_stats {
1310 1397
1311/* Structure containing variables used by the shared code (e1000_hw.c) */ 1398/* Structure containing variables used by the shared code (e1000_hw.c) */
1312struct e1000_hw { 1399struct e1000_hw {
1313 uint8_t __iomem *hw_addr; 1400 uint8_t *hw_addr;
1314 uint8_t *flash_address; 1401 uint8_t *flash_address;
1315 e1000_mac_type mac_type; 1402 e1000_mac_type mac_type;
1316 e1000_phy_type phy_type; 1403 e1000_phy_type phy_type;
1317 uint32_t phy_init_script; 1404 uint32_t phy_init_script;
1318 e1000_media_type media_type; 1405 e1000_media_type media_type;
1319 void *back; 1406 void *back;
1407 struct e1000_shadow_ram *eeprom_shadow_ram;
1408 uint32_t flash_bank_size;
1409 uint32_t flash_base_addr;
1320 e1000_fc_type fc; 1410 e1000_fc_type fc;
1321 e1000_bus_speed bus_speed; 1411 e1000_bus_speed bus_speed;
1322 e1000_bus_width bus_width; 1412 e1000_bus_width bus_width;
@@ -1328,6 +1418,7 @@ struct e1000_hw {
1328 uint32_t asf_firmware_present; 1418 uint32_t asf_firmware_present;
1329 uint32_t eeprom_semaphore_present; 1419 uint32_t eeprom_semaphore_present;
1330 uint32_t swfw_sync_present; 1420 uint32_t swfw_sync_present;
1421 uint32_t swfwhw_semaphore_present;
1331 unsigned long io_base; 1422 unsigned long io_base;
1332 uint32_t phy_id; 1423 uint32_t phy_id;
1333 uint32_t phy_revision; 1424 uint32_t phy_revision;
@@ -1387,6 +1478,7 @@ struct e1000_hw {
1387 boolean_t in_ifs_mode; 1478 boolean_t in_ifs_mode;
1388 boolean_t mng_reg_access_disabled; 1479 boolean_t mng_reg_access_disabled;
1389 boolean_t leave_av_bit_off; 1480 boolean_t leave_av_bit_off;
1481 boolean_t kmrn_lock_loss_workaround_disabled;
1390}; 1482};
1391 1483
1392 1484
@@ -1435,6 +1527,7 @@ struct e1000_hw {
1435#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1527#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1436#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1528#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1437#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1529#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1530#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1438 1531
1439/* Device Status */ 1532/* Device Status */
1440#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1533#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
@@ -1449,6 +1542,8 @@ struct e1000_hw {
1449#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1542#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1450#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1543#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1451#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1544#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1545#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1546 by EEPROM/Flash */
1452#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1547#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1453#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1548#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1454#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1549#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
@@ -1506,6 +1601,10 @@ struct e1000_hw {
1506#define E1000_STM_OPCODE 0xDB00 1601#define E1000_STM_OPCODE 0xDB00
1507#define E1000_HICR_FW_RESET 0xC0 1602#define E1000_HICR_FW_RESET 0xC0
1508 1603
1604#define E1000_SHADOW_RAM_WORDS 2048
1605#define E1000_ICH8_NVM_SIG_WORD 0x13
1606#define E1000_ICH8_NVM_SIG_MASK 0xC0
1607
1509/* EEPROM Read */ 1608/* EEPROM Read */
1510#define E1000_EERD_START 0x00000001 /* Start Read */ 1609#define E1000_EERD_START 0x00000001 /* Start Read */
1511#define E1000_EERD_DONE 0x00000010 /* Read Done */ 1610#define E1000_EERD_DONE 0x00000010 /* Read Done */
@@ -1551,7 +1650,6 @@ struct e1000_hw {
1551#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1650#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1552#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1651#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1553#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1652#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1554#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1555#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1653#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1556#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1654#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1557#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1655#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
@@ -1591,12 +1689,31 @@ struct e1000_hw {
1591#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 1689#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1592 1690
1593/* In-Band Control */ 1691/* In-Band Control */
1692#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1594#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 1693#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1595 1694
1596/* Half-Duplex Control */ 1695/* Half-Duplex Control */
1597#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 1696#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1598#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 1697#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1599 1698
1699#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1700
1701#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1702#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1703
1704#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1705#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1706#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1707
1708#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1709
1710#define E1000_PHY_CTRL_SPD_EN 0x00000001
1711#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1712#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1713#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1714#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1715#define E1000_PHY_CTRL_B2B_EN 0x00000080
1716
1600/* LED Control */ 1717/* LED Control */
1601#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1718#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1602#define E1000_LEDCTL_LED0_MODE_SHIFT 0 1719#define E1000_LEDCTL_LED0_MODE_SHIFT 0
@@ -1666,6 +1783,9 @@ struct e1000_hw {
1666#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1783#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1667#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1784#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1668#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1785#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1786#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1787#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1788#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
1669 1789
1670/* Interrupt Cause Set */ 1790/* Interrupt Cause Set */
1671#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1791#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1692,6 +1812,9 @@ struct e1000_hw {
1692#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1812#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1693#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1813#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1694#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1814#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1815#define E1000_ICS_DSW E1000_ICR_DSW
1816#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1817#define E1000_ICS_EPRST E1000_ICR_EPRST
1695 1818
1696/* Interrupt Mask Set */ 1819/* Interrupt Mask Set */
1697#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1820#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1718,6 +1841,9 @@ struct e1000_hw {
1718#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1841#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1719#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1842#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1720#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1843#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1844#define E1000_IMS_DSW E1000_ICR_DSW
1845#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1846#define E1000_IMS_EPRST E1000_ICR_EPRST
1721 1847
1722/* Interrupt Mask Clear */ 1848/* Interrupt Mask Clear */
1723#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1849#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1744,6 +1870,9 @@ struct e1000_hw {
1744#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1870#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1745#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1871#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1746#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1872#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1873#define E1000_IMC_DSW E1000_ICR_DSW
1874#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1875#define E1000_IMC_EPRST E1000_ICR_EPRST
1747 1876
1748/* Receive Control */ 1877/* Receive Control */
1749#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1878#define E1000_RCTL_RST 0x00000001 /* Software reset */
@@ -1918,9 +2047,10 @@ struct e1000_hw {
1918#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 2047#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1919#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2048#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1920#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 2049#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1921#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000 2050#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
1922#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2051#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1923#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 2052#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2053#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1924 2054
1925/* Definitions for power management and wakeup registers */ 2055/* Definitions for power management and wakeup registers */
1926/* Wake Up Control */ 2056/* Wake Up Control */
@@ -2010,6 +2140,15 @@ struct e1000_hw {
2010#define E1000_FWSM_MODE_SHIFT 1 2140#define E1000_FWSM_MODE_SHIFT 1
2011#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2141#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2012 2142
2143#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2144#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2145#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2146#define E1000_FWSM_SKUEL_SHIFT 29
2147#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2148#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2149#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2150#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2151
2013/* FFLT Debug Register */ 2152/* FFLT Debug Register */
2014#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2153#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2015 2154
@@ -2082,6 +2221,8 @@ struct e1000_host_command_info {
2082 E1000_GCR_TXDSCW_NO_SNOOP | \ 2221 E1000_GCR_TXDSCW_NO_SNOOP | \
2083 E1000_GCR_TXDSCR_NO_SNOOP) 2222 E1000_GCR_TXDSCR_NO_SNOOP)
2084 2223
2224#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2225
2085#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2226#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2086/* Function Active and Power State to MNG */ 2227/* Function Active and Power State to MNG */
2087#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 2228#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
@@ -2140,8 +2281,10 @@ struct e1000_host_command_info {
2140#define EEPROM_PHY_CLASS_WORD 0x0007 2281#define EEPROM_PHY_CLASS_WORD 0x0007
2141#define EEPROM_INIT_CONTROL1_REG 0x000A 2282#define EEPROM_INIT_CONTROL1_REG 0x000A
2142#define EEPROM_INIT_CONTROL2_REG 0x000F 2283#define EEPROM_INIT_CONTROL2_REG 0x000F
2284#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2143#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 2285#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2144#define EEPROM_INIT_3GIO_3 0x001A 2286#define EEPROM_INIT_3GIO_3 0x001A
2287#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2145#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 2288#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2146#define EEPROM_CFG 0x0012 2289#define EEPROM_CFG 0x0012
2147#define EEPROM_FLASH_VERSION 0x0032 2290#define EEPROM_FLASH_VERSION 0x0032
@@ -2153,10 +2296,16 @@ struct e1000_host_command_info {
2153/* Word definitions for ID LED Settings */ 2296/* Word definitions for ID LED Settings */
2154#define ID_LED_RESERVED_0000 0x0000 2297#define ID_LED_RESERVED_0000 0x0000
2155#define ID_LED_RESERVED_FFFF 0xFFFF 2298#define ID_LED_RESERVED_FFFF 0xFFFF
2299#define ID_LED_RESERVED_82573 0xF746
2300#define ID_LED_DEFAULT_82573 0x1811
2156#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2301#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2157 (ID_LED_OFF1_OFF2 << 8) | \ 2302 (ID_LED_OFF1_OFF2 << 8) | \
2158 (ID_LED_DEF1_DEF2 << 4) | \ 2303 (ID_LED_DEF1_DEF2 << 4) | \
2159 (ID_LED_DEF1_DEF2)) 2304 (ID_LED_DEF1_DEF2))
2305#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2306 (ID_LED_DEF1_OFF2 << 8) | \
2307 (ID_LED_DEF1_ON2 << 4) | \
2308 (ID_LED_DEF1_DEF2))
2160#define ID_LED_DEF1_DEF2 0x1 2309#define ID_LED_DEF1_DEF2 0x1
2161#define ID_LED_DEF1_ON2 0x2 2310#define ID_LED_DEF1_ON2 0x2
2162#define ID_LED_DEF1_OFF2 0x3 2311#define ID_LED_DEF1_OFF2 0x3
@@ -2191,6 +2340,11 @@ struct e1000_host_command_info {
2191#define EEPROM_WORD0F_ASM_DIR 0x2000 2340#define EEPROM_WORD0F_ASM_DIR 0x2000
2192#define EEPROM_WORD0F_ANE 0x0800 2341#define EEPROM_WORD0F_ANE 0x0800
2193#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 2342#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2343#define EEPROM_WORD0F_LPLU 0x0001
2344
2345/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2346#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2347#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2194 2348
2195/* Mask bits for fields in Word 0x1a of the EEPROM */ 2349/* Mask bits for fields in Word 0x1a of the EEPROM */
2196#define EEPROM_WORD1A_ASPM_MASK 0x000C 2350#define EEPROM_WORD1A_ASPM_MASK 0x000C
@@ -2265,23 +2419,29 @@ struct e1000_host_command_info {
2265#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 2419#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2266#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 2420#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2267#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 2421#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2268#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000 2422#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2269 2423
2270#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF 2424#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2271#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 2425#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2272#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 2426#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2427#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2428#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2273 2429
2274/* PBA constants */ 2430/* PBA constants */
2431#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2275#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2432#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2276#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2433#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2277#define E1000_PBA_22K 0x0016 2434#define E1000_PBA_22K 0x0016
2278#define E1000_PBA_24K 0x0018 2435#define E1000_PBA_24K 0x0018
2279#define E1000_PBA_30K 0x001E 2436#define E1000_PBA_30K 0x001E
2280#define E1000_PBA_32K 0x0020 2437#define E1000_PBA_32K 0x0020
2438#define E1000_PBA_34K 0x0022
2281#define E1000_PBA_38K 0x0026 2439#define E1000_PBA_38K 0x0026
2282#define E1000_PBA_40K 0x0028 2440#define E1000_PBA_40K 0x0028
2283#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2441#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2284 2442
2443#define E1000_PBS_16K E1000_PBA_16K
2444
2285/* Flow Control Constants */ 2445/* Flow Control Constants */
2286#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 2446#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2287#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 2447#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
@@ -2336,7 +2496,7 @@ struct e1000_host_command_info {
2336/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2496/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2337#define AUTO_READ_DONE_TIMEOUT 10 2497#define AUTO_READ_DONE_TIMEOUT 10
2338/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2498/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2339#define PHY_CFG_TIMEOUT 40 2499#define PHY_CFG_TIMEOUT 100
2340 2500
2341#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2501#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2342 2502
@@ -2764,6 +2924,17 @@ struct e1000_host_command_info {
2764#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2924#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2765#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2925#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2766 2926
2927/* M88EC018 Rev 2 specific DownShift settings */
2928#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2929#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2930#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2931#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2932#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2933#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2934#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2935#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2936#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2937
2767/* IGP01E1000 Specific Port Config Register - R/W */ 2938/* IGP01E1000 Specific Port Config Register - R/W */
2768#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 2939#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2769#define IGP01E1000_PSCFR_PRE_EN 0x0020 2940#define IGP01E1000_PSCFR_PRE_EN 0x0020
@@ -2990,6 +3161,221 @@ struct e1000_host_command_info {
2990#define L1LXT971A_PHY_ID 0x001378E0 3161#define L1LXT971A_PHY_ID 0x001378E0
2991#define GG82563_E_PHY_ID 0x01410CA0 3162#define GG82563_E_PHY_ID 0x01410CA0
2992 3163
3164
3165/* Bits...
3166 * 15-5: page
3167 * 4-0: register offset
3168 */
3169#define PHY_PAGE_SHIFT 5
3170#define PHY_REG(page, reg) \
3171 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3172
3173#define IGP3_PHY_PORT_CTRL \
3174 PHY_REG(769, 17) /* Port General Configuration */
3175#define IGP3_PHY_RATE_ADAPT_CTRL \
3176 PHY_REG(769, 25) /* Rate Adapter Control Register */
3177
3178#define IGP3_KMRN_FIFO_CTRL_STATS \
3179 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3180#define IGP3_KMRN_POWER_MNG_CTRL \
3181 PHY_REG(770, 17) /* KMRN Power Management Control Register */
3182#define IGP3_KMRN_INBAND_CTRL \
3183 PHY_REG(770, 18) /* KMRN Inband Control Register */
3184#define IGP3_KMRN_DIAG \
3185 PHY_REG(770, 19) /* KMRN Diagnostic register */
3186#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3187#define IGP3_KMRN_ACK_TIMEOUT \
3188 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3189
3190#define IGP3_VR_CTRL \
3191 PHY_REG(776, 18) /* Voltage regulator control register */
3192#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3193
3194#define IGP3_CAPABILITY \
3195 PHY_REG(776, 19) /* IGP3 Capability Register */
3196
3197/* Capabilities for SKU Control */
3198#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3199#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3200#define IGP3_CAP_ASF 0x0004 /* Support ASF */
3201#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3202#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3203#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3204#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3205#define IGP3_CAP_RSS 0x0080 /* Support RSS */
3206#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3207#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3208
3209#define IGP3_PPC_JORDAN_EN 0x0001
3210#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
3211
3212#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
3213#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
3214#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3215#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3216
3217#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3218#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3219
3220#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3221#define IGP3_KMRN_EC_DIS_INBAND 0x0080
3222
3223#define IGP03E1000_E_PHY_ID 0x02A80390
3224#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3225#define IFE_PLUS_E_PHY_ID 0x02A80320
3226#define IFE_C_E_PHY_ID 0x02A80310
3227
3228#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3229#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3230#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3231#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
3232#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3233#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3234#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3235#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3236#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3237#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3238#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3239#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3240#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3241
3242#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
3243#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3244#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3245#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3246#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3247#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3248#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3249#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3250
3251#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
3252#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3253#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3254#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3255#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3256#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3257
3258#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3259#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3260#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3261#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */
3262#define IFE_PMC_MDIX_MODE_SHIFT 6
3263#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3264
3265#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3266#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3267#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3268#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3269#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3270#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3271#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3272#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3273#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3274#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3275#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3276
3277#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
3278#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
3279#define ICH8_FLASH_SEG_SIZE_256 256
3280#define ICH8_FLASH_SEG_SIZE_4K 4096
3281#define ICH8_FLASH_SEG_SIZE_64K 65536
3282
3283#define ICH8_CYCLE_READ 0x0
3284#define ICH8_CYCLE_RESERVED 0x1
3285#define ICH8_CYCLE_WRITE 0x2
3286#define ICH8_CYCLE_ERASE 0x3
3287
3288#define ICH8_FLASH_GFPREG 0x0000
3289#define ICH8_FLASH_HSFSTS 0x0004
3290#define ICH8_FLASH_HSFCTL 0x0006
3291#define ICH8_FLASH_FADDR 0x0008
3292#define ICH8_FLASH_FDATA0 0x0010
3293#define ICH8_FLASH_FRACC 0x0050
3294#define ICH8_FLASH_FREG0 0x0054
3295#define ICH8_FLASH_FREG1 0x0058
3296#define ICH8_FLASH_FREG2 0x005C
3297#define ICH8_FLASH_FREG3 0x0060
3298#define ICH8_FLASH_FPR0 0x0074
3299#define ICH8_FLASH_FPR1 0x0078
3300#define ICH8_FLASH_SSFSTS 0x0090
3301#define ICH8_FLASH_SSFCTL 0x0092
3302#define ICH8_FLASH_PREOP 0x0094
3303#define ICH8_FLASH_OPTYPE 0x0096
3304#define ICH8_FLASH_OPMENU 0x0098
3305
3306#define ICH8_FLASH_REG_MAPSIZE 0x00A0
3307#define ICH8_FLASH_SECTOR_SIZE 4096
3308#define ICH8_GFPREG_BASE_MASK 0x1FFF
3309#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3310
3311/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3312/* Offset 04h HSFSTS */
3313union ich8_hws_flash_status {
3314 struct ich8_hsfsts {
3315#ifdef E1000_BIG_ENDIAN
3316 uint16_t reserved2 :6;
3317 uint16_t fldesvalid :1;
3318 uint16_t flockdn :1;
3319 uint16_t flcdone :1;
3320 uint16_t flcerr :1;
3321 uint16_t dael :1;
3322 uint16_t berasesz :2;
3323 uint16_t flcinprog :1;
3324 uint16_t reserved1 :2;
3325#else
3326 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */
3327 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */
3328 uint16_t dael :1; /* bit 2 Direct Access error Log */
3329 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3330 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3331 uint16_t reserved1 :2; /* bit 13:6 Reserved */
3332 uint16_t reserved2 :6; /* bit 13:6 Reserved */
3333 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3334 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3335#endif
3336 } hsf_status;
3337 uint16_t regval;
3338};
3339
3340/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3341/* Offset 06h FLCTL */
3342union ich8_hws_flash_ctrl {
3343 struct ich8_hsflctl {
3344#ifdef E1000_BIG_ENDIAN
3345 uint16_t fldbcount :2;
3346 uint16_t flockdn :6;
3347 uint16_t flcgo :1;
3348 uint16_t flcycle :2;
3349 uint16_t reserved :5;
3350#else
3351 uint16_t flcgo :1; /* 0 Flash Cycle Go */
3352 uint16_t flcycle :2; /* 2:1 Flash Cycle */
3353 uint16_t reserved :5; /* 7:3 Reserved */
3354 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */
3355 uint16_t flockdn :6; /* 15:10 Reserved */
3356#endif
3357 } hsf_ctrl;
3358 uint16_t regval;
3359};
3360
3361/* ICH8 Flash Region Access Permissions */
3362union ich8_hws_flash_regacc {
3363 struct ich8_flracc {
3364#ifdef E1000_BIG_ENDIAN
3365 uint32_t gmwag :8;
3366 uint32_t gmrag :8;
3367 uint32_t grwa :8;
3368 uint32_t grra :8;
3369#else
3370 uint32_t grra :8; /* 0:7 GbE region Read Access */
3371 uint32_t grwa :8; /* 8:15 GbE region Write Access */
3372 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */
3373 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */
3374#endif
3375 } hsf_flregacc;
3376 uint16_t regval;
3377};
3378
2993/* Miscellaneous PHY bit definitions. */ 3379/* Miscellaneous PHY bit definitions. */
2994#define PHY_PREAMBLE 0xFFFFFFFF 3380#define PHY_PREAMBLE 0xFFFFFFFF
2995#define PHY_SOF 0x01 3381#define PHY_SOF 0x01
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index f77624f5f17b..627f224d78bc 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -36,7 +36,7 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
36#else 36#else
37#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
38#endif 38#endif
39#define DRV_VERSION "7.0.38-k4"DRIVERNAPI 39#define DRV_VERSION "7.1.9-k4"DRIVERNAPI
40char e1000_driver_version[] = DRV_VERSION; 40char e1000_driver_version[] = DRV_VERSION;
41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
42 42
@@ -73,6 +73,11 @@ static struct pci_device_id e1000_pci_tbl[] = {
73 INTEL_E1000_ETHERNET_DEVICE(0x1026), 73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027), 74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028), 75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
76 INTEL_E1000_ETHERNET_DEVICE(0x1049),
77 INTEL_E1000_ETHERNET_DEVICE(0x104A),
78 INTEL_E1000_ETHERNET_DEVICE(0x104B),
79 INTEL_E1000_ETHERNET_DEVICE(0x104C),
80 INTEL_E1000_ETHERNET_DEVICE(0x104D),
76 INTEL_E1000_ETHERNET_DEVICE(0x105E), 81 INTEL_E1000_ETHERNET_DEVICE(0x105E),
77 INTEL_E1000_ETHERNET_DEVICE(0x105F), 82 INTEL_E1000_ETHERNET_DEVICE(0x105F),
78 INTEL_E1000_ETHERNET_DEVICE(0x1060), 83 INTEL_E1000_ETHERNET_DEVICE(0x1060),
@@ -96,6 +101,8 @@ static struct pci_device_id e1000_pci_tbl[] = {
96 INTEL_E1000_ETHERNET_DEVICE(0x109A), 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
97 INTEL_E1000_ETHERNET_DEVICE(0x10B5), 102 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
98 INTEL_E1000_ETHERNET_DEVICE(0x10B9), 103 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
105 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
99 /* required last entry */ 106 /* required last entry */
100 {0,} 107 {0,}
101}; 108};
@@ -133,7 +140,6 @@ static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
133static void e1000_set_multi(struct net_device *netdev); 140static void e1000_set_multi(struct net_device *netdev);
134static void e1000_update_phy_info(unsigned long data); 141static void e1000_update_phy_info(unsigned long data);
135static void e1000_watchdog(unsigned long data); 142static void e1000_watchdog(unsigned long data);
136static void e1000_watchdog_task(struct e1000_adapter *adapter);
137static void e1000_82547_tx_fifo_stall(unsigned long data); 143static void e1000_82547_tx_fifo_stall(unsigned long data);
138static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 144static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
139static struct net_device_stats * e1000_get_stats(struct net_device *netdev); 145static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
@@ -178,8 +184,8 @@ static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
178static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid); 184static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
179static void e1000_restore_vlan(struct e1000_adapter *adapter); 185static void e1000_restore_vlan(struct e1000_adapter *adapter);
180 186
181#ifdef CONFIG_PM
182static int e1000_suspend(struct pci_dev *pdev, pm_message_t state); 187static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
188#ifdef CONFIG_PM
183static int e1000_resume(struct pci_dev *pdev); 189static int e1000_resume(struct pci_dev *pdev);
184#endif 190#endif
185static void e1000_shutdown(struct pci_dev *pdev); 191static void e1000_shutdown(struct pci_dev *pdev);
@@ -206,8 +212,8 @@ static struct pci_driver e1000_driver = {
206 .probe = e1000_probe, 212 .probe = e1000_probe,
207 .remove = __devexit_p(e1000_remove), 213 .remove = __devexit_p(e1000_remove),
208 /* Power Managment Hooks */ 214 /* Power Managment Hooks */
209#ifdef CONFIG_PM
210 .suspend = e1000_suspend, 215 .suspend = e1000_suspend,
216#ifdef CONFIG_PM
211 .resume = e1000_resume, 217 .resume = e1000_resume,
212#endif 218#endif
213 .shutdown = e1000_shutdown, 219 .shutdown = e1000_shutdown,
@@ -261,6 +267,44 @@ e1000_exit_module(void)
261 267
262module_exit(e1000_exit_module); 268module_exit(e1000_exit_module);
263 269
270static int e1000_request_irq(struct e1000_adapter *adapter)
271{
272 struct net_device *netdev = adapter->netdev;
273 int flags, err = 0;
274
275 flags = IRQF_SHARED;
276#ifdef CONFIG_PCI_MSI
277 if (adapter->hw.mac_type > e1000_82547_rev_2) {
278 adapter->have_msi = TRUE;
279 if ((err = pci_enable_msi(adapter->pdev))) {
280 DPRINTK(PROBE, ERR,
281 "Unable to allocate MSI interrupt Error: %d\n", err);
282 adapter->have_msi = FALSE;
283 }
284 }
285 if (adapter->have_msi)
286 flags &= ~IRQF_SHARED;
287#endif
288 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
289 netdev->name, netdev)))
290 DPRINTK(PROBE, ERR,
291 "Unable to allocate interrupt Error: %d\n", err);
292
293 return err;
294}
295
296static void e1000_free_irq(struct e1000_adapter *adapter)
297{
298 struct net_device *netdev = adapter->netdev;
299
300 free_irq(adapter->pdev->irq, netdev);
301
302#ifdef CONFIG_PCI_MSI
303 if (adapter->have_msi)
304 pci_disable_msi(adapter->pdev);
305#endif
306}
307
264/** 308/**
265 * e1000_irq_disable - Mask off interrupt generation on the NIC 309 * e1000_irq_disable - Mask off interrupt generation on the NIC
266 * @adapter: board private structure 310 * @adapter: board private structure
@@ -329,6 +373,7 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
329{ 373{
330 uint32_t ctrl_ext; 374 uint32_t ctrl_ext;
331 uint32_t swsm; 375 uint32_t swsm;
376 uint32_t extcnf;
332 377
333 /* Let firmware taken over control of h/w */ 378 /* Let firmware taken over control of h/w */
334 switch (adapter->hw.mac_type) { 379 switch (adapter->hw.mac_type) {
@@ -343,6 +388,11 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
343 swsm = E1000_READ_REG(&adapter->hw, SWSM); 388 swsm = E1000_READ_REG(&adapter->hw, SWSM);
344 E1000_WRITE_REG(&adapter->hw, SWSM, 389 E1000_WRITE_REG(&adapter->hw, SWSM,
345 swsm & ~E1000_SWSM_DRV_LOAD); 390 swsm & ~E1000_SWSM_DRV_LOAD);
391 case e1000_ich8lan:
392 extcnf = E1000_READ_REG(&adapter->hw, CTRL_EXT);
393 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
394 extcnf & ~E1000_CTRL_EXT_DRV_LOAD);
395 break;
346 default: 396 default:
347 break; 397 break;
348 } 398 }
@@ -364,6 +414,7 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
364{ 414{
365 uint32_t ctrl_ext; 415 uint32_t ctrl_ext;
366 uint32_t swsm; 416 uint32_t swsm;
417 uint32_t extcnf;
367 /* Let firmware know the driver has taken over */ 418 /* Let firmware know the driver has taken over */
368 switch (adapter->hw.mac_type) { 419 switch (adapter->hw.mac_type) {
369 case e1000_82571: 420 case e1000_82571:
@@ -378,6 +429,11 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
378 E1000_WRITE_REG(&adapter->hw, SWSM, 429 E1000_WRITE_REG(&adapter->hw, SWSM,
379 swsm | E1000_SWSM_DRV_LOAD); 430 swsm | E1000_SWSM_DRV_LOAD);
380 break; 431 break;
432 case e1000_ich8lan:
433 extcnf = E1000_READ_REG(&adapter->hw, EXTCNF_CTRL);
434 E1000_WRITE_REG(&adapter->hw, EXTCNF_CTRL,
435 extcnf | E1000_EXTCNF_CTRL_SWFLAG);
436 break;
381 default: 437 default:
382 break; 438 break;
383 } 439 }
@@ -387,18 +443,10 @@ int
387e1000_up(struct e1000_adapter *adapter) 443e1000_up(struct e1000_adapter *adapter)
388{ 444{
389 struct net_device *netdev = adapter->netdev; 445 struct net_device *netdev = adapter->netdev;
390 int i, err; 446 int i;
391 447
392 /* hardware has been reset, we need to reload some things */ 448 /* hardware has been reset, we need to reload some things */
393 449
394 /* Reset the PHY if it was previously powered down */
395 if (adapter->hw.media_type == e1000_media_type_copper) {
396 uint16_t mii_reg;
397 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
398 if (mii_reg & MII_CR_POWER_DOWN)
399 e1000_phy_hw_reset(&adapter->hw);
400 }
401
402 e1000_set_multi(netdev); 450 e1000_set_multi(netdev);
403 451
404 e1000_restore_vlan(adapter); 452 e1000_restore_vlan(adapter);
@@ -415,24 +463,6 @@ e1000_up(struct e1000_adapter *adapter)
415 E1000_DESC_UNUSED(ring)); 463 E1000_DESC_UNUSED(ring));
416 } 464 }
417 465
418#ifdef CONFIG_PCI_MSI
419 if (adapter->hw.mac_type > e1000_82547_rev_2) {
420 adapter->have_msi = TRUE;
421 if ((err = pci_enable_msi(adapter->pdev))) {
422 DPRINTK(PROBE, ERR,
423 "Unable to allocate MSI interrupt Error: %d\n", err);
424 adapter->have_msi = FALSE;
425 }
426 }
427#endif
428 if ((err = request_irq(adapter->pdev->irq, &e1000_intr,
429 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
430 netdev->name, netdev))) {
431 DPRINTK(PROBE, ERR,
432 "Unable to allocate interrupt Error: %d\n", err);
433 return err;
434 }
435
436 adapter->tx_queue_len = netdev->tx_queue_len; 466 adapter->tx_queue_len = netdev->tx_queue_len;
437 467
438 mod_timer(&adapter->watchdog_timer, jiffies); 468 mod_timer(&adapter->watchdog_timer, jiffies);
@@ -445,21 +475,60 @@ e1000_up(struct e1000_adapter *adapter)
445 return 0; 475 return 0;
446} 476}
447 477
478/**
479 * e1000_power_up_phy - restore link in case the phy was powered down
480 * @adapter: address of board private structure
481 *
482 * The phy may be powered down to save power and turn off link when the
483 * driver is unloaded and wake on lan is not enabled (among others)
484 * *** this routine MUST be followed by a call to e1000_reset ***
485 *
486 **/
487
488static void e1000_power_up_phy(struct e1000_adapter *adapter)
489{
490 uint16_t mii_reg = 0;
491
492 /* Just clear the power down bit to wake the phy back up */
493 if (adapter->hw.media_type == e1000_media_type_copper) {
494 /* according to the manual, the phy will retain its
495 * settings across a power-down/up cycle */
496 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
497 mii_reg &= ~MII_CR_POWER_DOWN;
498 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
499 }
500}
501
502static void e1000_power_down_phy(struct e1000_adapter *adapter)
503{
504 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
505 e1000_check_mng_mode(&adapter->hw);
506 /* Power down the PHY so no link is implied when interface is down
507 * The PHY cannot be powered down if any of the following is TRUE
508 * (a) WoL is enabled
509 * (b) AMT is active
510 * (c) SoL/IDER session is active */
511 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
512 adapter->hw.mac_type != e1000_ich8lan &&
513 adapter->hw.media_type == e1000_media_type_copper &&
514 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
515 !mng_mode_enabled &&
516 !e1000_check_phy_reset_block(&adapter->hw)) {
517 uint16_t mii_reg = 0;
518 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
519 mii_reg |= MII_CR_POWER_DOWN;
520 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
521 mdelay(1);
522 }
523}
524
448void 525void
449e1000_down(struct e1000_adapter *adapter) 526e1000_down(struct e1000_adapter *adapter)
450{ 527{
451 struct net_device *netdev = adapter->netdev; 528 struct net_device *netdev = adapter->netdev;
452 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
453 e1000_check_mng_mode(&adapter->hw);
454 529
455 e1000_irq_disable(adapter); 530 e1000_irq_disable(adapter);
456 531
457 free_irq(adapter->pdev->irq, netdev);
458#ifdef CONFIG_PCI_MSI
459 if (adapter->hw.mac_type > e1000_82547_rev_2 &&
460 adapter->have_msi == TRUE)
461 pci_disable_msi(adapter->pdev);
462#endif
463 del_timer_sync(&adapter->tx_fifo_stall_timer); 532 del_timer_sync(&adapter->tx_fifo_stall_timer);
464 del_timer_sync(&adapter->watchdog_timer); 533 del_timer_sync(&adapter->watchdog_timer);
465 del_timer_sync(&adapter->phy_info_timer); 534 del_timer_sync(&adapter->phy_info_timer);
@@ -476,23 +545,17 @@ e1000_down(struct e1000_adapter *adapter)
476 e1000_reset(adapter); 545 e1000_reset(adapter);
477 e1000_clean_all_tx_rings(adapter); 546 e1000_clean_all_tx_rings(adapter);
478 e1000_clean_all_rx_rings(adapter); 547 e1000_clean_all_rx_rings(adapter);
548}
479 549
480 /* Power down the PHY so no link is implied when interface is down * 550void
481 * The PHY cannot be powered down if any of the following is TRUE * 551e1000_reinit_locked(struct e1000_adapter *adapter)
482 * (a) WoL is enabled 552{
483 * (b) AMT is active 553 WARN_ON(in_interrupt());
484 * (c) SoL/IDER session is active */ 554 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
485 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 && 555 msleep(1);
486 adapter->hw.media_type == e1000_media_type_copper && 556 e1000_down(adapter);
487 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) && 557 e1000_up(adapter);
488 !mng_mode_enabled && 558 clear_bit(__E1000_RESETTING, &adapter->flags);
489 !e1000_check_phy_reset_block(&adapter->hw)) {
490 uint16_t mii_reg;
491 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
492 mii_reg |= MII_CR_POWER_DOWN;
493 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
494 mdelay(1);
495 }
496} 559}
497 560
498void 561void
@@ -518,6 +581,9 @@ e1000_reset(struct e1000_adapter *adapter)
518 case e1000_82573: 581 case e1000_82573:
519 pba = E1000_PBA_12K; 582 pba = E1000_PBA_12K;
520 break; 583 break;
584 case e1000_ich8lan:
585 pba = E1000_PBA_8K;
586 break;
521 default: 587 default:
522 pba = E1000_PBA_48K; 588 pba = E1000_PBA_48K;
523 break; 589 break;
@@ -542,6 +608,12 @@ e1000_reset(struct e1000_adapter *adapter)
542 /* Set the FC high water mark to 90% of the FIFO size. 608 /* Set the FC high water mark to 90% of the FIFO size.
543 * Required to clear last 3 LSB */ 609 * Required to clear last 3 LSB */
544 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8; 610 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
611 /* We can't use 90% on small FIFOs because the remainder
612 * would be less than 1 full frame. In this case, we size
613 * it to allow at least a full frame above the high water
614 * mark. */
615 if (pba < E1000_PBA_16K)
616 fc_high_water_mark = (pba * 1024) - 1600;
545 617
546 adapter->hw.fc_high_water = fc_high_water_mark; 618 adapter->hw.fc_high_water = fc_high_water_mark;
547 adapter->hw.fc_low_water = fc_high_water_mark - 8; 619 adapter->hw.fc_low_water = fc_high_water_mark - 8;
@@ -564,6 +636,23 @@ e1000_reset(struct e1000_adapter *adapter)
564 636
565 e1000_reset_adaptive(&adapter->hw); 637 e1000_reset_adaptive(&adapter->hw);
566 e1000_phy_get_info(&adapter->hw, &adapter->phy_info); 638 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
639
640 if (!adapter->smart_power_down &&
641 (adapter->hw.mac_type == e1000_82571 ||
642 adapter->hw.mac_type == e1000_82572)) {
643 uint16_t phy_data = 0;
644 /* speed up time to link by disabling smart power down, ignore
645 * the return value of this function because there is nothing
646 * different we would do if it failed */
647 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
648 &phy_data);
649 phy_data &= ~IGP02E1000_PM_SPD;
650 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
651 phy_data);
652 }
653
654 if (adapter->hw.mac_type < e1000_ich8lan)
655 /* FIXME: this code is duplicate and wrong for PCI Express */
567 if (adapter->en_mng_pt) { 656 if (adapter->en_mng_pt) {
568 manc = E1000_READ_REG(&adapter->hw, MANC); 657 manc = E1000_READ_REG(&adapter->hw, MANC);
569 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST); 658 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
@@ -590,6 +679,7 @@ e1000_probe(struct pci_dev *pdev,
590 struct net_device *netdev; 679 struct net_device *netdev;
591 struct e1000_adapter *adapter; 680 struct e1000_adapter *adapter;
592 unsigned long mmio_start, mmio_len; 681 unsigned long mmio_start, mmio_len;
682 unsigned long flash_start, flash_len;
593 683
594 static int cards_found = 0; 684 static int cards_found = 0;
595 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */ 685 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
@@ -599,10 +689,12 @@ e1000_probe(struct pci_dev *pdev,
599 if ((err = pci_enable_device(pdev))) 689 if ((err = pci_enable_device(pdev)))
600 return err; 690 return err;
601 691
602 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { 692 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
693 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
603 pci_using_dac = 1; 694 pci_using_dac = 1;
604 } else { 695 } else {
605 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { 696 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
697 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
606 E1000_ERR("No usable DMA configuration, aborting\n"); 698 E1000_ERR("No usable DMA configuration, aborting\n");
607 return err; 699 return err;
608 } 700 }
@@ -682,6 +774,19 @@ e1000_probe(struct pci_dev *pdev,
682 if ((err = e1000_sw_init(adapter))) 774 if ((err = e1000_sw_init(adapter)))
683 goto err_sw_init; 775 goto err_sw_init;
684 776
777 /* Flash BAR mapping must happen after e1000_sw_init
778 * because it depends on mac_type */
779 if ((adapter->hw.mac_type == e1000_ich8lan) &&
780 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
781 flash_start = pci_resource_start(pdev, 1);
782 flash_len = pci_resource_len(pdev, 1);
783 adapter->hw.flash_address = ioremap(flash_start, flash_len);
784 if (!adapter->hw.flash_address) {
785 err = -EIO;
786 goto err_flashmap;
787 }
788 }
789
685 if ((err = e1000_check_phy_reset_block(&adapter->hw))) 790 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
686 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); 791 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
687 792
@@ -700,6 +805,8 @@ e1000_probe(struct pci_dev *pdev,
700 NETIF_F_HW_VLAN_TX | 805 NETIF_F_HW_VLAN_TX |
701 NETIF_F_HW_VLAN_RX | 806 NETIF_F_HW_VLAN_RX |
702 NETIF_F_HW_VLAN_FILTER; 807 NETIF_F_HW_VLAN_FILTER;
808 if (adapter->hw.mac_type == e1000_ich8lan)
809 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
703 } 810 }
704 811
705#ifdef NETIF_F_TSO 812#ifdef NETIF_F_TSO
@@ -715,11 +822,17 @@ e1000_probe(struct pci_dev *pdev,
715 if (pci_using_dac) 822 if (pci_using_dac)
716 netdev->features |= NETIF_F_HIGHDMA; 823 netdev->features |= NETIF_F_HIGHDMA;
717 824
718 /* hard_start_xmit is safe against parallel locking */
719 netdev->features |= NETIF_F_LLTX; 825 netdev->features |= NETIF_F_LLTX;
720 826
721 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw); 827 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
722 828
829 /* initialize eeprom parameters */
830
831 if (e1000_init_eeprom_params(&adapter->hw)) {
832 E1000_ERR("EEPROM initialization failed\n");
833 return -EIO;
834 }
835
723 /* before reading the EEPROM, reset the controller to 836 /* before reading the EEPROM, reset the controller to
724 * put the device in a known good starting state */ 837 * put the device in a known good starting state */
725 838
@@ -758,9 +871,6 @@ e1000_probe(struct pci_dev *pdev,
758 adapter->watchdog_timer.function = &e1000_watchdog; 871 adapter->watchdog_timer.function = &e1000_watchdog;
759 adapter->watchdog_timer.data = (unsigned long) adapter; 872 adapter->watchdog_timer.data = (unsigned long) adapter;
760 873
761 INIT_WORK(&adapter->watchdog_task,
762 (void (*)(void *))e1000_watchdog_task, adapter);
763
764 init_timer(&adapter->phy_info_timer); 874 init_timer(&adapter->phy_info_timer);
765 adapter->phy_info_timer.function = &e1000_update_phy_info; 875 adapter->phy_info_timer.function = &e1000_update_phy_info;
766 adapter->phy_info_timer.data = (unsigned long) adapter; 876 adapter->phy_info_timer.data = (unsigned long) adapter;
@@ -790,6 +900,11 @@ e1000_probe(struct pci_dev *pdev,
790 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 900 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
791 eeprom_apme_mask = E1000_EEPROM_82544_APM; 901 eeprom_apme_mask = E1000_EEPROM_82544_APM;
792 break; 902 break;
903 case e1000_ich8lan:
904 e1000_read_eeprom(&adapter->hw,
905 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
906 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
907 break;
793 case e1000_82546: 908 case e1000_82546:
794 case e1000_82546_rev_3: 909 case e1000_82546_rev_3:
795 case e1000_82571: 910 case e1000_82571:
@@ -849,6 +964,9 @@ e1000_probe(struct pci_dev *pdev,
849 return 0; 964 return 0;
850 965
851err_register: 966err_register:
967 if (adapter->hw.flash_address)
968 iounmap(adapter->hw.flash_address);
969err_flashmap:
852err_sw_init: 970err_sw_init:
853err_eeprom: 971err_eeprom:
854 iounmap(adapter->hw.hw_addr); 972 iounmap(adapter->hw.hw_addr);
@@ -882,6 +1000,7 @@ e1000_remove(struct pci_dev *pdev)
882 flush_scheduled_work(); 1000 flush_scheduled_work();
883 1001
884 if (adapter->hw.mac_type >= e1000_82540 && 1002 if (adapter->hw.mac_type >= e1000_82540 &&
1003 adapter->hw.mac_type != e1000_ich8lan &&
885 adapter->hw.media_type == e1000_media_type_copper) { 1004 adapter->hw.media_type == e1000_media_type_copper) {
886 manc = E1000_READ_REG(&adapter->hw, MANC); 1005 manc = E1000_READ_REG(&adapter->hw, MANC);
887 if (manc & E1000_MANC_SMBUS_EN) { 1006 if (manc & E1000_MANC_SMBUS_EN) {
@@ -910,6 +1029,8 @@ e1000_remove(struct pci_dev *pdev)
910#endif 1029#endif
911 1030
912 iounmap(adapter->hw.hw_addr); 1031 iounmap(adapter->hw.hw_addr);
1032 if (adapter->hw.flash_address)
1033 iounmap(adapter->hw.flash_address);
913 pci_release_regions(pdev); 1034 pci_release_regions(pdev);
914 1035
915 free_netdev(netdev); 1036 free_netdev(netdev);
@@ -947,7 +1068,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
947 1068
948 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 1069 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
949 1070
950 adapter->rx_buffer_len = MAXIMUM_ETHERNET_FRAME_SIZE; 1071 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
951 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128; 1072 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
952 hw->max_frame_size = netdev->mtu + 1073 hw->max_frame_size = netdev->mtu +
953 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 1074 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
@@ -960,13 +1081,6 @@ e1000_sw_init(struct e1000_adapter *adapter)
960 return -EIO; 1081 return -EIO;
961 } 1082 }
962 1083
963 /* initialize eeprom parameters */
964
965 if (e1000_init_eeprom_params(hw)) {
966 E1000_ERR("EEPROM initialization failed\n");
967 return -EIO;
968 }
969
970 switch (hw->mac_type) { 1084 switch (hw->mac_type) {
971 default: 1085 default:
972 break; 1086 break;
@@ -1078,6 +1192,10 @@ e1000_open(struct net_device *netdev)
1078 struct e1000_adapter *adapter = netdev_priv(netdev); 1192 struct e1000_adapter *adapter = netdev_priv(netdev);
1079 int err; 1193 int err;
1080 1194
1195 /* disallow open during test */
1196 if (test_bit(__E1000_DRIVER_TESTING, &adapter->flags))
1197 return -EBUSY;
1198
1081 /* allocate transmit descriptors */ 1199 /* allocate transmit descriptors */
1082 1200
1083 if ((err = e1000_setup_all_tx_resources(adapter))) 1201 if ((err = e1000_setup_all_tx_resources(adapter)))
@@ -1088,6 +1206,12 @@ e1000_open(struct net_device *netdev)
1088 if ((err = e1000_setup_all_rx_resources(adapter))) 1206 if ((err = e1000_setup_all_rx_resources(adapter)))
1089 goto err_setup_rx; 1207 goto err_setup_rx;
1090 1208
1209 err = e1000_request_irq(adapter);
1210 if (err)
1211 goto err_up;
1212
1213 e1000_power_up_phy(adapter);
1214
1091 if ((err = e1000_up(adapter))) 1215 if ((err = e1000_up(adapter)))
1092 goto err_up; 1216 goto err_up;
1093 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 1217 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
@@ -1131,7 +1255,10 @@ e1000_close(struct net_device *netdev)
1131{ 1255{
1132 struct e1000_adapter *adapter = netdev_priv(netdev); 1256 struct e1000_adapter *adapter = netdev_priv(netdev);
1133 1257
1258 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1134 e1000_down(adapter); 1259 e1000_down(adapter);
1260 e1000_power_down_phy(adapter);
1261 e1000_free_irq(adapter);
1135 1262
1136 e1000_free_all_tx_resources(adapter); 1263 e1000_free_all_tx_resources(adapter);
1137 e1000_free_all_rx_resources(adapter); 1264 e1000_free_all_rx_resources(adapter);
@@ -1189,8 +1316,7 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter,
1189 int size; 1316 int size;
1190 1317
1191 size = sizeof(struct e1000_buffer) * txdr->count; 1318 size = sizeof(struct e1000_buffer) * txdr->count;
1192 1319 txdr->buffer_info = vmalloc(size);
1193 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
1194 if (!txdr->buffer_info) { 1320 if (!txdr->buffer_info) {
1195 DPRINTK(PROBE, ERR, 1321 DPRINTK(PROBE, ERR,
1196 "Unable to allocate memory for the transmit descriptor ring\n"); 1322 "Unable to allocate memory for the transmit descriptor ring\n");
@@ -1302,11 +1428,11 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1302 tdba = adapter->tx_ring[0].dma; 1428 tdba = adapter->tx_ring[0].dma;
1303 tdlen = adapter->tx_ring[0].count * 1429 tdlen = adapter->tx_ring[0].count *
1304 sizeof(struct e1000_tx_desc); 1430 sizeof(struct e1000_tx_desc);
1305 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1306 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1307 E1000_WRITE_REG(hw, TDLEN, tdlen); 1431 E1000_WRITE_REG(hw, TDLEN, tdlen);
1308 E1000_WRITE_REG(hw, TDH, 0); 1432 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1433 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1309 E1000_WRITE_REG(hw, TDT, 0); 1434 E1000_WRITE_REG(hw, TDT, 0);
1435 E1000_WRITE_REG(hw, TDH, 0);
1310 adapter->tx_ring[0].tdh = E1000_TDH; 1436 adapter->tx_ring[0].tdh = E1000_TDH;
1311 adapter->tx_ring[0].tdt = E1000_TDT; 1437 adapter->tx_ring[0].tdt = E1000_TDT;
1312 break; 1438 break;
@@ -1418,7 +1544,7 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter,
1418 int size, desc_len; 1544 int size, desc_len;
1419 1545
1420 size = sizeof(struct e1000_buffer) * rxdr->count; 1546 size = sizeof(struct e1000_buffer) * rxdr->count;
1421 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus)); 1547 rxdr->buffer_info = vmalloc(size);
1422 if (!rxdr->buffer_info) { 1548 if (!rxdr->buffer_info) {
1423 DPRINTK(PROBE, ERR, 1549 DPRINTK(PROBE, ERR,
1424 "Unable to allocate memory for the receive descriptor ring\n"); 1550 "Unable to allocate memory for the receive descriptor ring\n");
@@ -1560,9 +1686,6 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1560 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 1686 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1561 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 1687 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1562 1688
1563 if (adapter->hw.mac_type > e1000_82543)
1564 rctl |= E1000_RCTL_SECRC;
1565
1566 if (adapter->hw.tbi_compatibility_on == 1) 1689 if (adapter->hw.tbi_compatibility_on == 1)
1567 rctl |= E1000_RCTL_SBP; 1690 rctl |= E1000_RCTL_SBP;
1568 else 1691 else
@@ -1628,7 +1751,7 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1628 rfctl |= E1000_RFCTL_IPV6_DIS; 1751 rfctl |= E1000_RFCTL_IPV6_DIS;
1629 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl); 1752 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1630 1753
1631 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC; 1754 rctl |= E1000_RCTL_DTYP_PS;
1632 1755
1633 psrctl |= adapter->rx_ps_bsize0 >> 1756 psrctl |= adapter->rx_ps_bsize0 >>
1634 E1000_PSRCTL_BSIZE0_SHIFT; 1757 E1000_PSRCTL_BSIZE0_SHIFT;
@@ -1712,11 +1835,11 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1712 case 1: 1835 case 1:
1713 default: 1836 default:
1714 rdba = adapter->rx_ring[0].dma; 1837 rdba = adapter->rx_ring[0].dma;
1715 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1716 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1717 E1000_WRITE_REG(hw, RDLEN, rdlen); 1838 E1000_WRITE_REG(hw, RDLEN, rdlen);
1718 E1000_WRITE_REG(hw, RDH, 0); 1839 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1840 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1719 E1000_WRITE_REG(hw, RDT, 0); 1841 E1000_WRITE_REG(hw, RDT, 0);
1842 E1000_WRITE_REG(hw, RDH, 0);
1720 adapter->rx_ring[0].rdh = E1000_RDH; 1843 adapter->rx_ring[0].rdh = E1000_RDH;
1721 adapter->rx_ring[0].rdt = E1000_RDT; 1844 adapter->rx_ring[0].rdt = E1000_RDT;
1722 break; 1845 break;
@@ -1741,9 +1864,6 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1741 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 1864 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1742 } 1865 }
1743 1866
1744 if (hw->mac_type == e1000_82573)
1745 E1000_WRITE_REG(hw, ERT, 0x0100);
1746
1747 /* Enable Receives */ 1867 /* Enable Receives */
1748 E1000_WRITE_REG(hw, RCTL, rctl); 1868 E1000_WRITE_REG(hw, RCTL, rctl);
1749} 1869}
@@ -2083,6 +2203,12 @@ e1000_set_multi(struct net_device *netdev)
2083 uint32_t rctl; 2203 uint32_t rctl;
2084 uint32_t hash_value; 2204 uint32_t hash_value;
2085 int i, rar_entries = E1000_RAR_ENTRIES; 2205 int i, rar_entries = E1000_RAR_ENTRIES;
2206 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2207 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2208 E1000_NUM_MTA_REGISTERS;
2209
2210 if (adapter->hw.mac_type == e1000_ich8lan)
2211 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
2086 2212
2087 /* reserve RAR[14] for LAA over-write work-around */ 2213 /* reserve RAR[14] for LAA over-write work-around */
2088 if (adapter->hw.mac_type == e1000_82571) 2214 if (adapter->hw.mac_type == e1000_82571)
@@ -2121,14 +2247,18 @@ e1000_set_multi(struct net_device *netdev)
2121 mc_ptr = mc_ptr->next; 2247 mc_ptr = mc_ptr->next;
2122 } else { 2248 } else {
2123 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0); 2249 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2250 E1000_WRITE_FLUSH(hw);
2124 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0); 2251 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2252 E1000_WRITE_FLUSH(hw);
2125 } 2253 }
2126 } 2254 }
2127 2255
2128 /* clear the old settings from the multicast hash table */ 2256 /* clear the old settings from the multicast hash table */
2129 2257
2130 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++) 2258 for (i = 0; i < mta_reg_count; i++) {
2131 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 2259 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2260 E1000_WRITE_FLUSH(hw);
2261 }
2132 2262
2133 /* load any remaining addresses into the hash table */ 2263 /* load any remaining addresses into the hash table */
2134 2264
@@ -2201,19 +2331,19 @@ static void
2201e1000_watchdog(unsigned long data) 2331e1000_watchdog(unsigned long data)
2202{ 2332{
2203 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 2333 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2204
2205 /* Do the rest outside of interrupt context */
2206 schedule_work(&adapter->watchdog_task);
2207}
2208
2209static void
2210e1000_watchdog_task(struct e1000_adapter *adapter)
2211{
2212 struct net_device *netdev = adapter->netdev; 2334 struct net_device *netdev = adapter->netdev;
2213 struct e1000_tx_ring *txdr = adapter->tx_ring; 2335 struct e1000_tx_ring *txdr = adapter->tx_ring;
2214 uint32_t link, tctl; 2336 uint32_t link, tctl;
2215 2337 int32_t ret_val;
2216 e1000_check_for_link(&adapter->hw); 2338
2339 ret_val = e1000_check_for_link(&adapter->hw);
2340 if ((ret_val == E1000_ERR_PHY) &&
2341 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2342 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2343 /* See e1000_kumeran_lock_loss_workaround() */
2344 DPRINTK(LINK, INFO,
2345 "Gigabit has been disabled, downgrading speed\n");
2346 }
2217 if (adapter->hw.mac_type == e1000_82573) { 2347 if (adapter->hw.mac_type == e1000_82573) {
2218 e1000_enable_tx_pkt_filtering(&adapter->hw); 2348 e1000_enable_tx_pkt_filtering(&adapter->hw);
2219 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id) 2349 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
@@ -2394,7 +2524,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2394 uint8_t ipcss, ipcso, tucss, tucso, hdr_len; 2524 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2395 int err; 2525 int err;
2396 2526
2397 if (skb_shinfo(skb)->gso_size) { 2527 if (skb_is_gso(skb)) {
2398 if (skb_header_cloned(skb)) { 2528 if (skb_header_cloned(skb)) {
2399 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 2529 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2400 if (err) 2530 if (err)
@@ -2519,7 +2649,7 @@ e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2519 * tso gets written back prematurely before the data is fully 2649 * tso gets written back prematurely before the data is fully
2520 * DMA'd to the controller */ 2650 * DMA'd to the controller */
2521 if (!skb->data_len && tx_ring->last_tx_tso && 2651 if (!skb->data_len && tx_ring->last_tx_tso &&
2522 !skb_shinfo(skb)->gso_size) { 2652 !skb_is_gso(skb)) {
2523 tx_ring->last_tx_tso = 0; 2653 tx_ring->last_tx_tso = 0;
2524 size -= 4; 2654 size -= 4;
2525 } 2655 }
@@ -2779,9 +2909,10 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2779 case e1000_82571: 2909 case e1000_82571:
2780 case e1000_82572: 2910 case e1000_82572:
2781 case e1000_82573: 2911 case e1000_82573:
2912 case e1000_ich8lan:
2782 pull_size = min((unsigned int)4, skb->data_len); 2913 pull_size = min((unsigned int)4, skb->data_len);
2783 if (!__pskb_pull_tail(skb, pull_size)) { 2914 if (!__pskb_pull_tail(skb, pull_size)) {
2784 printk(KERN_ERR 2915 DPRINTK(DRV, ERR,
2785 "__pskb_pull_tail failed.\n"); 2916 "__pskb_pull_tail failed.\n");
2786 dev_kfree_skb_any(skb); 2917 dev_kfree_skb_any(skb);
2787 return NETDEV_TX_OK; 2918 return NETDEV_TX_OK;
@@ -2806,8 +2937,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2806 2937
2807#ifdef NETIF_F_TSO 2938#ifdef NETIF_F_TSO
2808 /* Controller Erratum workaround */ 2939 /* Controller Erratum workaround */
2809 if (!skb->data_len && tx_ring->last_tx_tso && 2940 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
2810 !skb_shinfo(skb)->gso_size)
2811 count++; 2941 count++;
2812#endif 2942#endif
2813 2943
@@ -2919,8 +3049,7 @@ e1000_reset_task(struct net_device *netdev)
2919{ 3049{
2920 struct e1000_adapter *adapter = netdev_priv(netdev); 3050 struct e1000_adapter *adapter = netdev_priv(netdev);
2921 3051
2922 e1000_down(adapter); 3052 e1000_reinit_locked(adapter);
2923 e1000_up(adapter);
2924} 3053}
2925 3054
2926/** 3055/**
@@ -2964,6 +3093,7 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
2964 /* Adapter-specific max frame size limits. */ 3093 /* Adapter-specific max frame size limits. */
2965 switch (adapter->hw.mac_type) { 3094 switch (adapter->hw.mac_type) {
2966 case e1000_undefined ... e1000_82542_rev2_1: 3095 case e1000_undefined ... e1000_82542_rev2_1:
3096 case e1000_ich8lan:
2967 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) { 3097 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2968 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n"); 3098 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2969 return -EINVAL; 3099 return -EINVAL;
@@ -2997,7 +3127,7 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
2997 break; 3127 break;
2998 } 3128 }
2999 3129
3000 /* NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 3130 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3001 * means we reserve 2 more, this pushes us to allocate from the next 3131 * means we reserve 2 more, this pushes us to allocate from the next
3002 * larger slab size 3132 * larger slab size
3003 * i.e. RXBUFFER_2048 --> size-4096 slab */ 3133 * i.e. RXBUFFER_2048 --> size-4096 slab */
@@ -3018,7 +3148,6 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
3018 adapter->rx_buffer_len = E1000_RXBUFFER_16384; 3148 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3019 3149
3020 /* adjust allocation if LPE protects us, and we aren't using SBP */ 3150 /* adjust allocation if LPE protects us, and we aren't using SBP */
3021#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
3022 if (!adapter->hw.tbi_compatibility_on && 3151 if (!adapter->hw.tbi_compatibility_on &&
3023 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) || 3152 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3024 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))) 3153 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
@@ -3026,10 +3155,8 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
3026 3155
3027 netdev->mtu = new_mtu; 3156 netdev->mtu = new_mtu;
3028 3157
3029 if (netif_running(netdev)) { 3158 if (netif_running(netdev))
3030 e1000_down(adapter); 3159 e1000_reinit_locked(adapter);
3031 e1000_up(adapter);
3032 }
3033 3160
3034 adapter->hw.max_frame_size = max_frame; 3161 adapter->hw.max_frame_size = max_frame;
3035 3162
@@ -3074,12 +3201,15 @@ e1000_update_stats(struct e1000_adapter *adapter)
3074 adapter->stats.bprc += E1000_READ_REG(hw, BPRC); 3201 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3075 adapter->stats.mprc += E1000_READ_REG(hw, MPRC); 3202 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3076 adapter->stats.roc += E1000_READ_REG(hw, ROC); 3203 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3204
3205 if (adapter->hw.mac_type != e1000_ich8lan) {
3077 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64); 3206 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3078 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127); 3207 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3079 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255); 3208 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3080 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511); 3209 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3081 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023); 3210 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3082 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522); 3211 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3212 }
3083 3213
3084 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS); 3214 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3085 adapter->stats.mpc += E1000_READ_REG(hw, MPC); 3215 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
@@ -3107,12 +3237,16 @@ e1000_update_stats(struct e1000_adapter *adapter)
3107 adapter->stats.totl += E1000_READ_REG(hw, TOTL); 3237 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3108 adapter->stats.toth += E1000_READ_REG(hw, TOTH); 3238 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3109 adapter->stats.tpr += E1000_READ_REG(hw, TPR); 3239 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3240
3241 if (adapter->hw.mac_type != e1000_ich8lan) {
3110 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64); 3242 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3111 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127); 3243 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3112 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255); 3244 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3113 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511); 3245 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3114 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023); 3246 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3115 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522); 3247 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3248 }
3249
3116 adapter->stats.mptc += E1000_READ_REG(hw, MPTC); 3250 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3117 adapter->stats.bptc += E1000_READ_REG(hw, BPTC); 3251 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3118 3252
@@ -3134,6 +3268,8 @@ e1000_update_stats(struct e1000_adapter *adapter)
3134 if (hw->mac_type > e1000_82547_rev_2) { 3268 if (hw->mac_type > e1000_82547_rev_2) {
3135 adapter->stats.iac += E1000_READ_REG(hw, IAC); 3269 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3136 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC); 3270 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3271
3272 if (adapter->hw.mac_type != e1000_ich8lan) {
3137 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC); 3273 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3138 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC); 3274 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3139 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC); 3275 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
@@ -3141,6 +3277,7 @@ e1000_update_stats(struct e1000_adapter *adapter)
3141 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC); 3277 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3142 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC); 3278 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3143 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC); 3279 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3280 }
3144 } 3281 }
3145 3282
3146 /* Fill out the OS statistics structure */ 3283 /* Fill out the OS statistics structure */
@@ -3249,8 +3386,8 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
3249 E1000_WRITE_REG(hw, IMC, ~0); 3386 E1000_WRITE_REG(hw, IMC, ~0);
3250 E1000_WRITE_FLUSH(hw); 3387 E1000_WRITE_FLUSH(hw);
3251 } 3388 }
3252 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0]))) 3389 if (likely(netif_rx_schedule_prep(netdev)))
3253 __netif_rx_schedule(&adapter->polling_netdev[0]); 3390 __netif_rx_schedule(netdev);
3254 else 3391 else
3255 e1000_irq_enable(adapter); 3392 e1000_irq_enable(adapter);
3256#else 3393#else
@@ -3293,34 +3430,26 @@ e1000_clean(struct net_device *poll_dev, int *budget)
3293{ 3430{
3294 struct e1000_adapter *adapter; 3431 struct e1000_adapter *adapter;
3295 int work_to_do = min(*budget, poll_dev->quota); 3432 int work_to_do = min(*budget, poll_dev->quota);
3296 int tx_cleaned = 0, i = 0, work_done = 0; 3433 int tx_cleaned = 0, work_done = 0;
3297 3434
3298 /* Must NOT use netdev_priv macro here. */ 3435 /* Must NOT use netdev_priv macro here. */
3299 adapter = poll_dev->priv; 3436 adapter = poll_dev->priv;
3300 3437
3301 /* Keep link state information with original netdev */ 3438 /* Keep link state information with original netdev */
3302 if (!netif_carrier_ok(adapter->netdev)) 3439 if (!netif_carrier_ok(poll_dev))
3303 goto quit_polling; 3440 goto quit_polling;
3304 3441
3305 while (poll_dev != &adapter->polling_netdev[i]) { 3442 /* e1000_clean is called per-cpu. This lock protects
3306 i++; 3443 * tx_ring[0] from being cleaned by multiple cpus
3307 BUG_ON(i == adapter->num_rx_queues); 3444 * simultaneously. A failure obtaining the lock means
3445 * tx_ring[0] is currently being cleaned anyway. */
3446 if (spin_trylock(&adapter->tx_queue_lock)) {
3447 tx_cleaned = e1000_clean_tx_irq(adapter,
3448 &adapter->tx_ring[0]);
3449 spin_unlock(&adapter->tx_queue_lock);
3308 } 3450 }
3309 3451
3310 if (likely(adapter->num_tx_queues == 1)) { 3452 adapter->clean_rx(adapter, &adapter->rx_ring[0],
3311 /* e1000_clean is called per-cpu. This lock protects
3312 * tx_ring[0] from being cleaned by multiple cpus
3313 * simultaneously. A failure obtaining the lock means
3314 * tx_ring[0] is currently being cleaned anyway. */
3315 if (spin_trylock(&adapter->tx_queue_lock)) {
3316 tx_cleaned = e1000_clean_tx_irq(adapter,
3317 &adapter->tx_ring[0]);
3318 spin_unlock(&adapter->tx_queue_lock);
3319 }
3320 } else
3321 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3322
3323 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3324 &work_done, work_to_do); 3453 &work_done, work_to_do);
3325 3454
3326 *budget -= work_done; 3455 *budget -= work_done;
@@ -3328,7 +3457,7 @@ e1000_clean(struct net_device *poll_dev, int *budget)
3328 3457
3329 /* If no Tx and not enough Rx work done, exit the polling mode */ 3458 /* If no Tx and not enough Rx work done, exit the polling mode */
3330 if ((!tx_cleaned && (work_done == 0)) || 3459 if ((!tx_cleaned && (work_done == 0)) ||
3331 !netif_running(adapter->netdev)) { 3460 !netif_running(poll_dev)) {
3332quit_polling: 3461quit_polling:
3333 netif_rx_complete(poll_dev); 3462 netif_rx_complete(poll_dev);
3334 e1000_irq_enable(adapter); 3463 e1000_irq_enable(adapter);
@@ -3543,11 +3672,15 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3543 3672
3544 length = le16_to_cpu(rx_desc->length); 3673 length = le16_to_cpu(rx_desc->length);
3545 3674
3675 /* adjust length to remove Ethernet CRC */
3676 length -= 4;
3677
3546 if (unlikely(!(status & E1000_RXD_STAT_EOP))) { 3678 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3547 /* All receives must fit into a single buffer */ 3679 /* All receives must fit into a single buffer */
3548 E1000_DBG("%s: Receive packet consumed multiple" 3680 E1000_DBG("%s: Receive packet consumed multiple"
3549 " buffers\n", netdev->name); 3681 " buffers\n", netdev->name);
3550 dev_kfree_skb_irq(skb); 3682 /* recycle */
3683 buffer_info-> skb = skb;
3551 goto next_desc; 3684 goto next_desc;
3552 } 3685 }
3553 3686
@@ -3575,7 +3708,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3575#define E1000_CB_LENGTH 256 3708#define E1000_CB_LENGTH 256
3576 if (length < E1000_CB_LENGTH) { 3709 if (length < E1000_CB_LENGTH) {
3577 struct sk_buff *new_skb = 3710 struct sk_buff *new_skb =
3578 dev_alloc_skb(length + NET_IP_ALIGN); 3711 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
3579 if (new_skb) { 3712 if (new_skb) {
3580 skb_reserve(new_skb, NET_IP_ALIGN); 3713 skb_reserve(new_skb, NET_IP_ALIGN);
3581 new_skb->dev = netdev; 3714 new_skb->dev = netdev;
@@ -3675,7 +3808,6 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3675 buffer_info = &rx_ring->buffer_info[i]; 3808 buffer_info = &rx_ring->buffer_info[i];
3676 3809
3677 while (staterr & E1000_RXD_STAT_DD) { 3810 while (staterr & E1000_RXD_STAT_DD) {
3678 buffer_info = &rx_ring->buffer_info[i];
3679 ps_page = &rx_ring->ps_page[i]; 3811 ps_page = &rx_ring->ps_page[i];
3680 ps_page_dma = &rx_ring->ps_page_dma[i]; 3812 ps_page_dma = &rx_ring->ps_page_dma[i];
3681#ifdef CONFIG_E1000_NAPI 3813#ifdef CONFIG_E1000_NAPI
@@ -3747,8 +3879,9 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3747 pci_dma_sync_single_for_device(pdev, 3879 pci_dma_sync_single_for_device(pdev,
3748 ps_page_dma->ps_page_dma[0], 3880 ps_page_dma->ps_page_dma[0],
3749 PAGE_SIZE, PCI_DMA_FROMDEVICE); 3881 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3882 /* remove the CRC */
3883 l1 -= 4;
3750 skb_put(skb, l1); 3884 skb_put(skb, l1);
3751 length += l1;
3752 goto copydone; 3885 goto copydone;
3753 } /* if */ 3886 } /* if */
3754 } 3887 }
@@ -3767,6 +3900,10 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3767 skb->truesize += length; 3900 skb->truesize += length;
3768 } 3901 }
3769 3902
3903 /* strip the ethernet crc, problem is we're using pages now so
3904 * this whole operation can get a little cpu intensive */
3905 pskb_trim(skb, skb->len - 4);
3906
3770copydone: 3907copydone:
3771 e1000_rx_checksum(adapter, staterr, 3908 e1000_rx_checksum(adapter, staterr,
3772 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb); 3909 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
@@ -3842,7 +3979,7 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3842 3979
3843 while (cleaned_count--) { 3980 while (cleaned_count--) {
3844 if (!(skb = buffer_info->skb)) 3981 if (!(skb = buffer_info->skb))
3845 skb = dev_alloc_skb(bufsz); 3982 skb = netdev_alloc_skb(netdev, bufsz);
3846 else { 3983 else {
3847 skb_trim(skb, 0); 3984 skb_trim(skb, 0);
3848 goto map_skb; 3985 goto map_skb;
@@ -3860,7 +3997,7 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3860 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes " 3997 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3861 "at %p\n", bufsz, skb->data); 3998 "at %p\n", bufsz, skb->data);
3862 /* Try again, without freeing the previous */ 3999 /* Try again, without freeing the previous */
3863 skb = dev_alloc_skb(bufsz); 4000 skb = netdev_alloc_skb(netdev, bufsz);
3864 /* Failed allocation, critical failure */ 4001 /* Failed allocation, critical failure */
3865 if (!skb) { 4002 if (!skb) {
3866 dev_kfree_skb(oldskb); 4003 dev_kfree_skb(oldskb);
@@ -3984,7 +4121,8 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
3984 rx_desc->read.buffer_addr[j+1] = ~0; 4121 rx_desc->read.buffer_addr[j+1] = ~0;
3985 } 4122 }
3986 4123
3987 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN); 4124 skb = netdev_alloc_skb(netdev,
4125 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3988 4126
3989 if (unlikely(!skb)) { 4127 if (unlikely(!skb)) {
3990 adapter->alloc_rx_buff_failed++; 4128 adapter->alloc_rx_buff_failed++;
@@ -4180,10 +4318,9 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4180 return retval; 4318 return retval;
4181 } 4319 }
4182 } 4320 }
4183 if (netif_running(adapter->netdev)) { 4321 if (netif_running(adapter->netdev))
4184 e1000_down(adapter); 4322 e1000_reinit_locked(adapter);
4185 e1000_up(adapter); 4323 else
4186 } else
4187 e1000_reset(adapter); 4324 e1000_reset(adapter);
4188 break; 4325 break;
4189 case M88E1000_PHY_SPEC_CTRL: 4326 case M88E1000_PHY_SPEC_CTRL:
@@ -4200,10 +4337,9 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4200 case PHY_CTRL: 4337 case PHY_CTRL:
4201 if (mii_reg & MII_CR_POWER_DOWN) 4338 if (mii_reg & MII_CR_POWER_DOWN)
4202 break; 4339 break;
4203 if (netif_running(adapter->netdev)) { 4340 if (netif_running(adapter->netdev))
4204 e1000_down(adapter); 4341 e1000_reinit_locked(adapter);
4205 e1000_up(adapter); 4342 else
4206 } else
4207 e1000_reset(adapter); 4343 e1000_reset(adapter);
4208 break; 4344 break;
4209 } 4345 }
@@ -4277,18 +4413,21 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4277 ctrl |= E1000_CTRL_VME; 4413 ctrl |= E1000_CTRL_VME;
4278 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4414 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4279 4415
4416 if (adapter->hw.mac_type != e1000_ich8lan) {
4280 /* enable VLAN receive filtering */ 4417 /* enable VLAN receive filtering */
4281 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4418 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4282 rctl |= E1000_RCTL_VFE; 4419 rctl |= E1000_RCTL_VFE;
4283 rctl &= ~E1000_RCTL_CFIEN; 4420 rctl &= ~E1000_RCTL_CFIEN;
4284 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4421 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4285 e1000_update_mng_vlan(adapter); 4422 e1000_update_mng_vlan(adapter);
4423 }
4286 } else { 4424 } else {
4287 /* disable VLAN tag insert/strip */ 4425 /* disable VLAN tag insert/strip */
4288 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 4426 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4289 ctrl &= ~E1000_CTRL_VME; 4427 ctrl &= ~E1000_CTRL_VME;
4290 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4428 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4291 4429
4430 if (adapter->hw.mac_type != e1000_ich8lan) {
4292 /* disable VLAN filtering */ 4431 /* disable VLAN filtering */
4293 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4432 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4294 rctl &= ~E1000_RCTL_VFE; 4433 rctl &= ~E1000_RCTL_VFE;
@@ -4297,6 +4436,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4297 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4436 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4298 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4437 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4299 } 4438 }
4439 }
4300 } 4440 }
4301 4441
4302 e1000_irq_enable(adapter); 4442 e1000_irq_enable(adapter);
@@ -4458,12 +4598,16 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4458 struct e1000_adapter *adapter = netdev_priv(netdev); 4598 struct e1000_adapter *adapter = netdev_priv(netdev);
4459 uint32_t ctrl, ctrl_ext, rctl, manc, status; 4599 uint32_t ctrl, ctrl_ext, rctl, manc, status;
4460 uint32_t wufc = adapter->wol; 4600 uint32_t wufc = adapter->wol;
4601#ifdef CONFIG_PM
4461 int retval = 0; 4602 int retval = 0;
4603#endif
4462 4604
4463 netif_device_detach(netdev); 4605 netif_device_detach(netdev);
4464 4606
4465 if (netif_running(netdev)) 4607 if (netif_running(netdev)) {
4608 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
4466 e1000_down(adapter); 4609 e1000_down(adapter);
4610 }
4467 4611
4468#ifdef CONFIG_PM 4612#ifdef CONFIG_PM
4469 /* Implement our own version of pci_save_state(pdev) because pci- 4613 /* Implement our own version of pci_save_state(pdev) because pci-
@@ -4521,7 +4665,9 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4521 pci_enable_wake(pdev, PCI_D3cold, 0); 4665 pci_enable_wake(pdev, PCI_D3cold, 0);
4522 } 4666 }
4523 4667
4668 /* FIXME: this code is incorrect for PCI Express */
4524 if (adapter->hw.mac_type >= e1000_82540 && 4669 if (adapter->hw.mac_type >= e1000_82540 &&
4670 adapter->hw.mac_type != e1000_ich8lan &&
4525 adapter->hw.media_type == e1000_media_type_copper) { 4671 adapter->hw.media_type == e1000_media_type_copper) {
4526 manc = E1000_READ_REG(&adapter->hw, MANC); 4672 manc = E1000_READ_REG(&adapter->hw, MANC);
4527 if (manc & E1000_MANC_SMBUS_EN) { 4673 if (manc & E1000_MANC_SMBUS_EN) {
@@ -4532,6 +4678,9 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4532 } 4678 }
4533 } 4679 }
4534 4680
4681 if (adapter->hw.phy_type == e1000_phy_igp_3)
4682 e1000_phy_powerdown_workaround(&adapter->hw);
4683
4535 /* Release control of h/w to f/w. If f/w is AMT enabled, this 4684 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4536 * would have already happened in close and is redundant. */ 4685 * would have already happened in close and is redundant. */
4537 e1000_release_hw_control(adapter); 4686 e1000_release_hw_control(adapter);
@@ -4567,7 +4716,9 @@ e1000_resume(struct pci_dev *pdev)
4567 4716
4568 netif_device_attach(netdev); 4717 netif_device_attach(netdev);
4569 4718
4719 /* FIXME: this code is incorrect for PCI Express */
4570 if (adapter->hw.mac_type >= e1000_82540 && 4720 if (adapter->hw.mac_type >= e1000_82540 &&
4721 adapter->hw.mac_type != e1000_ich8lan &&
4571 adapter->hw.media_type == e1000_media_type_copper) { 4722 adapter->hw.media_type == e1000_media_type_copper) {
4572 manc = E1000_READ_REG(&adapter->hw, MANC); 4723 manc = E1000_READ_REG(&adapter->hw, MANC);
4573 manc &= ~(E1000_MANC_ARP_EN); 4724 manc &= ~(E1000_MANC_ARP_EN);
@@ -4601,6 +4752,7 @@ static void
4601e1000_netpoll(struct net_device *netdev) 4752e1000_netpoll(struct net_device *netdev)
4602{ 4753{
4603 struct e1000_adapter *adapter = netdev_priv(netdev); 4754 struct e1000_adapter *adapter = netdev_priv(netdev);
4755
4604 disable_irq(adapter->pdev->irq); 4756 disable_irq(adapter->pdev->irq);
4605 e1000_intr(adapter->pdev->irq, netdev, NULL); 4757 e1000_intr(adapter->pdev->irq, netdev, NULL);
4606 e1000_clean_tx_irq(adapter, adapter->tx_ring); 4758 e1000_clean_tx_irq(adapter, adapter->tx_ring);
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index 048d052be29d..2d3e8b06cab0 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -127,4 +127,17 @@ typedef enum {
127 127
128#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 128#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
129 129
130#define E1000_WRITE_ICH8_REG(a, reg, value) ( \
131 writel((value), ((a)->flash_address + reg)))
132
133#define E1000_READ_ICH8_REG(a, reg) ( \
134 readl((a)->flash_address + reg))
135
136#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
137 writew((value), ((a)->flash_address + reg)))
138
139#define E1000_READ_ICH8_REG16(a, reg) ( \
140 readw((a)->flash_address + reg))
141
142
130#endif /* _E1000_OSDEP_H_ */ 143#endif /* _E1000_OSDEP_H_ */
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index e55f8969a0fb..0ef413172c68 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -45,6 +45,16 @@
45 */ 45 */
46 46
47#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } 47#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
48/* Module Parameters are always initialized to -1, so that the driver
49 * can tell the difference between no user specified value or the
50 * user asking for the default value.
51 * The true default values are loaded in when e1000_check_options is called.
52 *
53 * This is a GCC extension to ANSI C.
54 * See the item "Labeled Elements in Initializers" in the section
55 * "Extensions to the C Language Family" of the GCC documentation.
56 */
57
48#define E1000_PARAM(X, desc) \ 58#define E1000_PARAM(X, desc) \
49 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ 59 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
50 static int num_##X = 0; \ 60 static int num_##X = 0; \
@@ -183,6 +193,24 @@ E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
183 193
184E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); 194E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
185 195
196/* Enable Smart Power Down of the PHY
197 *
198 * Valid Range: 0, 1
199 *
200 * Default Value: 0 (disabled)
201 */
202
203E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
204
205/* Enable Kumeran Lock Loss workaround
206 *
207 * Valid Range: 0, 1
208 *
209 * Default Value: 1 (enabled)
210 */
211
212E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
213
186#define AUTONEG_ADV_DEFAULT 0x2F 214#define AUTONEG_ADV_DEFAULT 0x2F
187#define AUTONEG_ADV_MASK 0x2F 215#define AUTONEG_ADV_MASK 0x2F
188#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 216#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
@@ -296,6 +324,7 @@ e1000_check_options(struct e1000_adapter *adapter)
296 DPRINTK(PROBE, NOTICE, 324 DPRINTK(PROBE, NOTICE,
297 "Warning: no configuration for board #%i\n", bd); 325 "Warning: no configuration for board #%i\n", bd);
298 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n"); 326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n");
327 bd = E1000_MAX_NIC;
299 } 328 }
300 329
301 { /* Transmit Descriptor Count */ 330 { /* Transmit Descriptor Count */
@@ -313,14 +342,9 @@ e1000_check_options(struct e1000_adapter *adapter)
313 opt.arg.r.max = mac_type < e1000_82544 ? 342 opt.arg.r.max = mac_type < e1000_82544 ?
314 E1000_MAX_TXD : E1000_MAX_82544_TXD; 343 E1000_MAX_TXD : E1000_MAX_82544_TXD;
315 344
316 if (num_TxDescriptors > bd) { 345 tx_ring->count = TxDescriptors[bd];
317 tx_ring->count = TxDescriptors[bd]; 346 e1000_validate_option(&tx_ring->count, &opt, adapter);
318 e1000_validate_option(&tx_ring->count, &opt, adapter); 347 E1000_ROUNDUP(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE);
319 E1000_ROUNDUP(tx_ring->count,
320 REQ_TX_DESCRIPTOR_MULTIPLE);
321 } else {
322 tx_ring->count = opt.def;
323 }
324 for (i = 0; i < adapter->num_tx_queues; i++) 348 for (i = 0; i < adapter->num_tx_queues; i++)
325 tx_ring[i].count = tx_ring->count; 349 tx_ring[i].count = tx_ring->count;
326 } 350 }
@@ -339,14 +363,9 @@ e1000_check_options(struct e1000_adapter *adapter)
339 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD : 363 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD :
340 E1000_MAX_82544_RXD; 364 E1000_MAX_82544_RXD;
341 365
342 if (num_RxDescriptors > bd) { 366 rx_ring->count = RxDescriptors[bd];
343 rx_ring->count = RxDescriptors[bd]; 367 e1000_validate_option(&rx_ring->count, &opt, adapter);
344 e1000_validate_option(&rx_ring->count, &opt, adapter); 368 E1000_ROUNDUP(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE);
345 E1000_ROUNDUP(rx_ring->count,
346 REQ_RX_DESCRIPTOR_MULTIPLE);
347 } else {
348 rx_ring->count = opt.def;
349 }
350 for (i = 0; i < adapter->num_rx_queues; i++) 369 for (i = 0; i < adapter->num_rx_queues; i++)
351 rx_ring[i].count = rx_ring->count; 370 rx_ring[i].count = rx_ring->count;
352 } 371 }
@@ -358,13 +377,9 @@ e1000_check_options(struct e1000_adapter *adapter)
358 .def = OPTION_ENABLED 377 .def = OPTION_ENABLED
359 }; 378 };
360 379
361 if (num_XsumRX > bd) { 380 int rx_csum = XsumRX[bd];
362 int rx_csum = XsumRX[bd]; 381 e1000_validate_option(&rx_csum, &opt, adapter);
363 e1000_validate_option(&rx_csum, &opt, adapter); 382 adapter->rx_csum = rx_csum;
364 adapter->rx_csum = rx_csum;
365 } else {
366 adapter->rx_csum = opt.def;
367 }
368 } 383 }
369 { /* Flow Control */ 384 { /* Flow Control */
370 385
@@ -384,13 +399,9 @@ e1000_check_options(struct e1000_adapter *adapter)
384 .p = fc_list }} 399 .p = fc_list }}
385 }; 400 };
386 401
387 if (num_FlowControl > bd) { 402 int fc = FlowControl[bd];
388 int fc = FlowControl[bd]; 403 e1000_validate_option(&fc, &opt, adapter);
389 e1000_validate_option(&fc, &opt, adapter); 404 adapter->hw.fc = adapter->hw.original_fc = fc;
390 adapter->hw.fc = adapter->hw.original_fc = fc;
391 } else {
392 adapter->hw.fc = adapter->hw.original_fc = opt.def;
393 }
394 } 405 }
395 { /* Transmit Interrupt Delay */ 406 { /* Transmit Interrupt Delay */
396 struct e1000_option opt = { 407 struct e1000_option opt = {
@@ -402,13 +413,8 @@ e1000_check_options(struct e1000_adapter *adapter)
402 .max = MAX_TXDELAY }} 413 .max = MAX_TXDELAY }}
403 }; 414 };
404 415
405 if (num_TxIntDelay > bd) { 416 adapter->tx_int_delay = TxIntDelay[bd];
406 adapter->tx_int_delay = TxIntDelay[bd]; 417 e1000_validate_option(&adapter->tx_int_delay, &opt, adapter);
407 e1000_validate_option(&adapter->tx_int_delay, &opt,
408 adapter);
409 } else {
410 adapter->tx_int_delay = opt.def;
411 }
412 } 418 }
413 { /* Transmit Absolute Interrupt Delay */ 419 { /* Transmit Absolute Interrupt Delay */
414 struct e1000_option opt = { 420 struct e1000_option opt = {
@@ -420,13 +426,9 @@ e1000_check_options(struct e1000_adapter *adapter)
420 .max = MAX_TXABSDELAY }} 426 .max = MAX_TXABSDELAY }}
421 }; 427 };
422 428
423 if (num_TxAbsIntDelay > bd) { 429 adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
424 adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; 430 e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
425 e1000_validate_option(&adapter->tx_abs_int_delay, &opt, 431 adapter);
426 adapter);
427 } else {
428 adapter->tx_abs_int_delay = opt.def;
429 }
430 } 432 }
431 { /* Receive Interrupt Delay */ 433 { /* Receive Interrupt Delay */
432 struct e1000_option opt = { 434 struct e1000_option opt = {
@@ -438,13 +440,8 @@ e1000_check_options(struct e1000_adapter *adapter)
438 .max = MAX_RXDELAY }} 440 .max = MAX_RXDELAY }}
439 }; 441 };
440 442
441 if (num_RxIntDelay > bd) { 443 adapter->rx_int_delay = RxIntDelay[bd];
442 adapter->rx_int_delay = RxIntDelay[bd]; 444 e1000_validate_option(&adapter->rx_int_delay, &opt, adapter);
443 e1000_validate_option(&adapter->rx_int_delay, &opt,
444 adapter);
445 } else {
446 adapter->rx_int_delay = opt.def;
447 }
448 } 445 }
449 { /* Receive Absolute Interrupt Delay */ 446 { /* Receive Absolute Interrupt Delay */
450 struct e1000_option opt = { 447 struct e1000_option opt = {
@@ -456,13 +453,9 @@ e1000_check_options(struct e1000_adapter *adapter)
456 .max = MAX_RXABSDELAY }} 453 .max = MAX_RXABSDELAY }}
457 }; 454 };
458 455
459 if (num_RxAbsIntDelay > bd) { 456 adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
460 adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; 457 e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
461 e1000_validate_option(&adapter->rx_abs_int_delay, &opt, 458 adapter);
462 adapter);
463 } else {
464 adapter->rx_abs_int_delay = opt.def;
465 }
466 } 459 }
467 { /* Interrupt Throttling Rate */ 460 { /* Interrupt Throttling Rate */
468 struct e1000_option opt = { 461 struct e1000_option opt = {
@@ -474,26 +467,44 @@ e1000_check_options(struct e1000_adapter *adapter)
474 .max = MAX_ITR }} 467 .max = MAX_ITR }}
475 }; 468 };
476 469
477 if (num_InterruptThrottleRate > bd) { 470 adapter->itr = InterruptThrottleRate[bd];
478 adapter->itr = InterruptThrottleRate[bd]; 471 switch (adapter->itr) {
479 switch (adapter->itr) { 472 case 0:
480 case 0: 473 DPRINTK(PROBE, INFO, "%s turned off\n", opt.name);
481 DPRINTK(PROBE, INFO, "%s turned off\n", 474 break;
482 opt.name); 475 case 1:
483 break; 476 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
484 case 1: 477 opt.name);
485 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 478 break;
486 opt.name); 479 default:
487 break; 480 e1000_validate_option(&adapter->itr, &opt, adapter);
488 default: 481 break;
489 e1000_validate_option(&adapter->itr, &opt,
490 adapter);
491 break;
492 }
493 } else {
494 adapter->itr = opt.def;
495 } 482 }
496 } 483 }
484 { /* Smart Power Down */
485 struct e1000_option opt = {
486 .type = enable_option,
487 .name = "PHY Smart Power Down",
488 .err = "defaulting to Disabled",
489 .def = OPTION_DISABLED
490 };
491
492 int spd = SmartPowerDownEnable[bd];
493 e1000_validate_option(&spd, &opt, adapter);
494 adapter->smart_power_down = spd;
495 }
496 { /* Kumeran Lock Loss Workaround */
497 struct e1000_option opt = {
498 .type = enable_option,
499 .name = "Kumeran Lock Loss Workaround",
500 .err = "defaulting to Enabled",
501 .def = OPTION_ENABLED
502 };
503
504 int kmrn_lock_loss = KumeranLockLoss[bd];
505 e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
506 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss;
507 }
497 508
498 switch (adapter->hw.media_type) { 509 switch (adapter->hw.media_type) {
499 case e1000_media_type_fiber: 510 case e1000_media_type_fiber:
@@ -519,17 +530,18 @@ static void __devinit
519e1000_check_fiber_options(struct e1000_adapter *adapter) 530e1000_check_fiber_options(struct e1000_adapter *adapter)
520{ 531{
521 int bd = adapter->bd_number; 532 int bd = adapter->bd_number;
522 if (num_Speed > bd) { 533 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd;
534 if ((Speed[bd] != OPTION_UNSET)) {
523 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, " 535 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, "
524 "parameter ignored\n"); 536 "parameter ignored\n");
525 } 537 }
526 538
527 if (num_Duplex > bd) { 539 if ((Duplex[bd] != OPTION_UNSET)) {
528 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, " 540 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, "
529 "parameter ignored\n"); 541 "parameter ignored\n");
530 } 542 }
531 543
532 if ((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) { 544 if ((AutoNeg[bd] != OPTION_UNSET) && (AutoNeg[bd] != 0x20)) {
533 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is " 545 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is "
534 "not valid for fiber adapters, " 546 "not valid for fiber adapters, "
535 "parameter ignored\n"); 547 "parameter ignored\n");
@@ -548,6 +560,7 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
548{ 560{
549 int speed, dplx, an; 561 int speed, dplx, an;
550 int bd = adapter->bd_number; 562 int bd = adapter->bd_number;
563 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd;
551 564
552 { /* Speed */ 565 { /* Speed */
553 struct e1000_opt_list speed_list[] = {{ 0, "" }, 566 struct e1000_opt_list speed_list[] = {{ 0, "" },
@@ -564,12 +577,8 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
564 .p = speed_list }} 577 .p = speed_list }}
565 }; 578 };
566 579
567 if (num_Speed > bd) { 580 speed = Speed[bd];
568 speed = Speed[bd]; 581 e1000_validate_option(&speed, &opt, adapter);
569 e1000_validate_option(&speed, &opt, adapter);
570 } else {
571 speed = opt.def;
572 }
573 } 582 }
574 { /* Duplex */ 583 { /* Duplex */
575 struct e1000_opt_list dplx_list[] = {{ 0, "" }, 584 struct e1000_opt_list dplx_list[] = {{ 0, "" },
@@ -591,15 +600,11 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
591 "Speed/Duplex/AutoNeg parameter ignored.\n"); 600 "Speed/Duplex/AutoNeg parameter ignored.\n");
592 return; 601 return;
593 } 602 }
594 if (num_Duplex > bd) { 603 dplx = Duplex[bd];
595 dplx = Duplex[bd]; 604 e1000_validate_option(&dplx, &opt, adapter);
596 e1000_validate_option(&dplx, &opt, adapter);
597 } else {
598 dplx = opt.def;
599 }
600 } 605 }
601 606
602 if ((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) { 607 if (AutoNeg[bd] != OPTION_UNSET && (speed != 0 || dplx != 0)) {
603 DPRINTK(PROBE, INFO, 608 DPRINTK(PROBE, INFO,
604 "AutoNeg specified along with Speed or Duplex, " 609 "AutoNeg specified along with Speed or Duplex, "
605 "parameter ignored\n"); 610 "parameter ignored\n");
@@ -648,19 +653,15 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
648 .p = an_list }} 653 .p = an_list }}
649 }; 654 };
650 655
651 if (num_AutoNeg > bd) { 656 an = AutoNeg[bd];
652 an = AutoNeg[bd]; 657 e1000_validate_option(&an, &opt, adapter);
653 e1000_validate_option(&an, &opt, adapter);
654 } else {
655 an = opt.def;
656 }
657 adapter->hw.autoneg_advertised = an; 658 adapter->hw.autoneg_advertised = an;
658 } 659 }
659 660
660 switch (speed + dplx) { 661 switch (speed + dplx) {
661 case 0: 662 case 0:
662 adapter->hw.autoneg = adapter->fc_autoneg = 1; 663 adapter->hw.autoneg = adapter->fc_autoneg = 1;
663 if ((num_Speed > bd) && (speed != 0 || dplx != 0)) 664 if (Speed[bd] != OPTION_UNSET || Duplex[bd] != OPTION_UNSET)
664 DPRINTK(PROBE, INFO, 665 DPRINTK(PROBE, INFO,
665 "Speed and duplex autonegotiation enabled\n"); 666 "Speed and duplex autonegotiation enabled\n");
666 break; 667 break;
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 2ad327542927..e445988c92ee 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -555,12 +555,12 @@ static int __devinit eepro100_init_one (struct pci_dev *pdev,
555 555
556 if (!request_region(pci_resource_start(pdev, 1), 556 if (!request_region(pci_resource_start(pdev, 1),
557 pci_resource_len(pdev, 1), "eepro100")) { 557 pci_resource_len(pdev, 1), "eepro100")) {
558 printk (KERN_ERR "eepro100: cannot reserve I/O ports\n"); 558 dev_err(&pdev->dev, "eepro100: cannot reserve I/O ports\n");
559 goto err_out_none; 559 goto err_out_none;
560 } 560 }
561 if (!request_mem_region(pci_resource_start(pdev, 0), 561 if (!request_mem_region(pci_resource_start(pdev, 0),
562 pci_resource_len(pdev, 0), "eepro100")) { 562 pci_resource_len(pdev, 0), "eepro100")) {
563 printk (KERN_ERR "eepro100: cannot reserve MMIO region\n"); 563 dev_err(&pdev->dev, "eepro100: cannot reserve MMIO region\n");
564 goto err_out_free_pio_region; 564 goto err_out_free_pio_region;
565 } 565 }
566 566
@@ -573,7 +573,7 @@ static int __devinit eepro100_init_one (struct pci_dev *pdev,
573 573
574 ioaddr = pci_iomap(pdev, pci_bar, 0); 574 ioaddr = pci_iomap(pdev, pci_bar, 0);
575 if (!ioaddr) { 575 if (!ioaddr) {
576 printk (KERN_ERR "eepro100: cannot remap IO\n"); 576 dev_err(&pdev->dev, "eepro100: cannot remap IO\n");
577 goto err_out_free_mmio_region; 577 goto err_out_free_mmio_region;
578 } 578 }
579 579
diff --git a/drivers/net/epic100.c b/drivers/net/epic100.c
index 9f3e09a3d88c..a67650ccf084 100644
--- a/drivers/net/epic100.c
+++ b/drivers/net/epic100.c
@@ -19,62 +19,15 @@
19 19
20 Information and updates available at 20 Information and updates available at
21 http://www.scyld.com/network/epic100.html 21 http://www.scyld.com/network/epic100.html
22 [this link no longer provides anything useful -jgarzik]
22 23
23 --------------------------------------------------------------------- 24 ---------------------------------------------------------------------
24 25
25 Linux kernel-specific changes:
26
27 LK1.1.2 (jgarzik):
28 * Merge becker version 1.09 (4/08/2000)
29
30 LK1.1.3:
31 * Major bugfix to 1.09 driver (Francis Romieu)
32
33 LK1.1.4 (jgarzik):
34 * Merge becker test version 1.09 (5/29/2000)
35
36 LK1.1.5:
37 * Fix locking (jgarzik)
38 * Limit 83c175 probe to ethernet-class PCI devices (rgooch)
39
40 LK1.1.6:
41 * Merge becker version 1.11
42 * Move pci_enable_device before any PCI BAR len checks
43
44 LK1.1.7:
45 * { fill me in }
46
47 LK1.1.8:
48 * ethtool driver info support (jgarzik)
49
50 LK1.1.9:
51 * ethtool media get/set support (jgarzik)
52
53 LK1.1.10:
54 * revert MII transceiver init change (jgarzik)
55
56 LK1.1.11:
57 * implement ETHTOOL_[GS]SET, _NWAY_RST, _[GS]MSGLVL, _GLINK (jgarzik)
58 * replace some MII-related magic numbers with constants
59
60 LK1.1.12:
61 * fix power-up sequence
62
63 LK1.1.13:
64 * revert version 1.1.12, power-up sequence "fix"
65
66 LK1.1.14 (Kryzsztof Halasa):
67 * fix spurious bad initializations
68 * pound phy a la SMSC's app note on the subject
69
70 AC1.1.14ac
71 * fix power up/down for ethtool that broke in 1.11
72
73*/ 26*/
74 27
75#define DRV_NAME "epic100" 28#define DRV_NAME "epic100"
76#define DRV_VERSION "1.11+LK1.1.14+AC1.1.14" 29#define DRV_VERSION "2.0"
77#define DRV_RELDATE "June 2, 2004" 30#define DRV_RELDATE "June 27, 2006"
78 31
79/* The user-configurable values. 32/* The user-configurable values.
80 These may be modified when a driver module is loaded.*/ 33 These may be modified when a driver module is loaded.*/
@@ -204,19 +157,15 @@ typedef enum {
204 157
205struct epic_chip_info { 158struct epic_chip_info {
206 const char *name; 159 const char *name;
207 int io_size; /* Needed for I/O region check or ioremap(). */
208 int drv_flags; /* Driver use, intended as capability flags. */ 160 int drv_flags; /* Driver use, intended as capability flags. */
209}; 161};
210 162
211 163
212/* indexed by chip_t */ 164/* indexed by chip_t */
213static const struct epic_chip_info pci_id_tbl[] = { 165static const struct epic_chip_info pci_id_tbl[] = {
214 { "SMSC EPIC/100 83c170", 166 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
215 EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN }, 167 { "SMSC EPIC/100 83c170", TYPE2_INTR },
216 { "SMSC EPIC/100 83c170", 168 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
217 EPIC_TOTAL_SIZE, TYPE2_INTR },
218 { "SMSC EPIC/C 83c175",
219 EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },
220}; 169};
221 170
222 171
@@ -385,8 +334,8 @@ static int __devinit epic_init_one (struct pci_dev *pdev,
385 goto out; 334 goto out;
386 irq = pdev->irq; 335 irq = pdev->irq;
387 336
388 if (pci_resource_len(pdev, 0) < pci_id_tbl[chip_idx].io_size) { 337 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
389 printk (KERN_ERR "card %d: no PCI region space\n", card_idx); 338 dev_err(&pdev->dev, "no PCI region space\n");
390 ret = -ENODEV; 339 ret = -ENODEV;
391 goto err_out_disable; 340 goto err_out_disable;
392 } 341 }
@@ -401,7 +350,7 @@ static int __devinit epic_init_one (struct pci_dev *pdev,
401 350
402 dev = alloc_etherdev(sizeof (*ep)); 351 dev = alloc_etherdev(sizeof (*ep));
403 if (!dev) { 352 if (!dev) {
404 printk (KERN_ERR "card %d: no memory for eth device\n", card_idx); 353 dev_err(&pdev->dev, "no memory for eth device\n");
405 goto err_out_free_res; 354 goto err_out_free_res;
406 } 355 }
407 SET_MODULE_OWNER(dev); 356 SET_MODULE_OWNER(dev);
@@ -413,7 +362,7 @@ static int __devinit epic_init_one (struct pci_dev *pdev,
413 ioaddr = pci_resource_start (pdev, 1); 362 ioaddr = pci_resource_start (pdev, 1);
414 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1)); 363 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
415 if (!ioaddr) { 364 if (!ioaddr) {
416 printk (KERN_ERR DRV_NAME " %d: ioremap failed\n", card_idx); 365 dev_err(&pdev->dev, "ioremap failed\n");
417 goto err_out_free_netdev; 366 goto err_out_free_netdev;
418 } 367 }
419#endif 368#endif
@@ -473,8 +422,7 @@ static int __devinit epic_init_one (struct pci_dev *pdev,
473 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4)); 422 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
474 423
475 if (debug > 2) { 424 if (debug > 2) {
476 printk(KERN_DEBUG DRV_NAME "(%s): EEPROM contents\n", 425 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
477 pci_name(pdev));
478 for (i = 0; i < 64; i++) 426 for (i = 0; i < 64; i++)
479 printk(" %4.4x%s", read_eeprom(ioaddr, i), 427 printk(" %4.4x%s", read_eeprom(ioaddr, i),
480 i % 16 == 15 ? "\n" : ""); 428 i % 16 == 15 ? "\n" : "");
@@ -496,21 +444,23 @@ static int __devinit epic_init_one (struct pci_dev *pdev,
496 int mii_status = mdio_read(dev, phy, MII_BMSR); 444 int mii_status = mdio_read(dev, phy, MII_BMSR);
497 if (mii_status != 0xffff && mii_status != 0x0000) { 445 if (mii_status != 0xffff && mii_status != 0x0000) {
498 ep->phys[phy_idx++] = phy; 446 ep->phys[phy_idx++] = phy;
499 printk(KERN_INFO DRV_NAME "(%s): MII transceiver #%d control " 447 dev_info(&pdev->dev,
500 "%4.4x status %4.4x.\n", 448 "MII transceiver #%d control "
501 pci_name(pdev), phy, mdio_read(dev, phy, 0), mii_status); 449 "%4.4x status %4.4x.\n",
450 phy, mdio_read(dev, phy, 0), mii_status);
502 } 451 }
503 } 452 }
504 ep->mii_phy_cnt = phy_idx; 453 ep->mii_phy_cnt = phy_idx;
505 if (phy_idx != 0) { 454 if (phy_idx != 0) {
506 phy = ep->phys[0]; 455 phy = ep->phys[0];
507 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE); 456 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
508 printk(KERN_INFO DRV_NAME "(%s): Autonegotiation advertising %4.4x link " 457 dev_info(&pdev->dev,
458 "Autonegotiation advertising %4.4x link "
509 "partner %4.4x.\n", 459 "partner %4.4x.\n",
510 pci_name(pdev), ep->mii.advertising, mdio_read(dev, phy, 5)); 460 ep->mii.advertising, mdio_read(dev, phy, 5));
511 } else if ( ! (ep->chip_flags & NO_MII)) { 461 } else if ( ! (ep->chip_flags & NO_MII)) {
512 printk(KERN_WARNING DRV_NAME "(%s): ***WARNING***: No MII transceiver found!\n", 462 dev_warn(&pdev->dev,
513 pci_name(pdev)); 463 "***WARNING***: No MII transceiver found!\n");
514 /* Use the known PHY address of the EPII. */ 464 /* Use the known PHY address of the EPII. */
515 ep->phys[0] = 3; 465 ep->phys[0] = 3;
516 } 466 }
@@ -525,8 +475,7 @@ static int __devinit epic_init_one (struct pci_dev *pdev,
525 /* The lower four bits are the media type. */ 475 /* The lower four bits are the media type. */
526 if (duplex) { 476 if (duplex) {
527 ep->mii.force_media = ep->mii.full_duplex = 1; 477 ep->mii.force_media = ep->mii.full_duplex = 1;
528 printk(KERN_INFO DRV_NAME "(%s): Forced full duplex operation requested.\n", 478 dev_info(&pdev->dev, "Forced full duplex requested.\n");
529 pci_name(pdev));
530 } 479 }
531 dev->if_port = ep->default_port = option; 480 dev->if_port = ep->default_port = option;
532 481
diff --git a/drivers/net/fealnx.c b/drivers/net/fealnx.c
index c701951dcd6f..97d34fee8c1f 100644
--- a/drivers/net/fealnx.c
+++ b/drivers/net/fealnx.c
@@ -124,7 +124,9 @@ MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered mult
124MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex"); 124MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
125MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)"); 125MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
126 126
127#define MIN_REGION_SIZE 136 127enum {
128 MIN_REGION_SIZE = 136,
129};
128 130
129/* A chip capabilities table, matching the entries in pci_tbl[] above. */ 131/* A chip capabilities table, matching the entries in pci_tbl[] above. */
130enum chip_capability_flags { 132enum chip_capability_flags {
@@ -146,14 +148,13 @@ enum phy_type_flags {
146 148
147struct chip_info { 149struct chip_info {
148 char *chip_name; 150 char *chip_name;
149 int io_size;
150 int flags; 151 int flags;
151}; 152};
152 153
153static const struct chip_info skel_netdrv_tbl[] = { 154static const struct chip_info skel_netdrv_tbl[] __devinitdata = {
154 {"100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR}, 155 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
155 {"100/10M Ethernet PCI Adapter", 136, HAS_CHIP_XCVR}, 156 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
156 {"1000/100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR}, 157 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
157}; 158};
158 159
159/* Offsets to the Command and Status Registers. */ 160/* Offsets to the Command and Status Registers. */
@@ -504,13 +505,14 @@ static int __devinit fealnx_init_one(struct pci_dev *pdev,
504 505
505 len = pci_resource_len(pdev, bar); 506 len = pci_resource_len(pdev, bar);
506 if (len < MIN_REGION_SIZE) { 507 if (len < MIN_REGION_SIZE) {
507 printk(KERN_ERR "%s: region size %ld too small, aborting\n", 508 dev_err(&pdev->dev,
508 boardname, len); 509 "region size %ld too small, aborting\n", len);
509 return -ENODEV; 510 return -ENODEV;
510 } 511 }
511 512
512 i = pci_request_regions(pdev, boardname); 513 i = pci_request_regions(pdev, boardname);
513 if (i) return i; 514 if (i)
515 return i;
514 516
515 irq = pdev->irq; 517 irq = pdev->irq;
516 518
@@ -576,9 +578,9 @@ static int __devinit fealnx_init_one(struct pci_dev *pdev,
576 578
577 if (mii_status != 0xffff && mii_status != 0x0000) { 579 if (mii_status != 0xffff && mii_status != 0x0000) {
578 np->phys[phy_idx++] = phy; 580 np->phys[phy_idx++] = phy;
579 printk(KERN_INFO 581 dev_info(&pdev->dev,
580 "%s: MII PHY found at address %d, status " 582 "MII PHY found at address %d, status "
581 "0x%4.4x.\n", dev->name, phy, mii_status); 583 "0x%4.4x.\n", phy, mii_status);
582 /* get phy type */ 584 /* get phy type */
583 { 585 {
584 unsigned int data; 586 unsigned int data;
@@ -601,10 +603,10 @@ static int __devinit fealnx_init_one(struct pci_dev *pdev,
601 } 603 }
602 604
603 np->mii_cnt = phy_idx; 605 np->mii_cnt = phy_idx;
604 if (phy_idx == 0) { 606 if (phy_idx == 0)
605 printk(KERN_WARNING "%s: MII PHY not found -- this device may " 607 dev_warn(&pdev->dev,
606 "not operate correctly.\n", dev->name); 608 "MII PHY not found -- this device may "
607 } 609 "not operate correctly.\n");
608 } else { 610 } else {
609 np->phys[0] = 32; 611 np->phys[0] = 32;
610/* 89/6/23 add, (begin) */ 612/* 89/6/23 add, (begin) */
@@ -630,7 +632,7 @@ static int __devinit fealnx_init_one(struct pci_dev *pdev,
630 np->mii.full_duplex = full_duplex[card_idx]; 632 np->mii.full_duplex = full_duplex[card_idx];
631 633
632 if (np->mii.full_duplex) { 634 if (np->mii.full_duplex) {
633 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name); 635 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
634/* 89/6/13 add, (begin) */ 636/* 89/6/13 add, (begin) */
635// if (np->PHYType==MarvellPHY) 637// if (np->PHYType==MarvellPHY)
636 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) { 638 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 037d870712ff..11b8f1b43dd5 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -240,10 +240,12 @@ enum {
240#define NVREG_RNDSEED_FORCE2 0x2d00 240#define NVREG_RNDSEED_FORCE2 0x2d00
241#define NVREG_RNDSEED_FORCE3 0x7400 241#define NVREG_RNDSEED_FORCE3 0x7400
242 242
243 NvRegUnknownSetupReg1 = 0xA0, 243 NvRegTxDeferral = 0xA0,
244#define NVREG_UNKSETUP1_VAL 0x16070f 244#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
245 NvRegUnknownSetupReg2 = 0xA4, 245#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
246#define NVREG_UNKSETUP2_VAL 0x16 246#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
247 NvRegRxDeferral = 0xA4,
248#define NVREG_RX_DEFERRAL_DEFAULT 0x16
247 NvRegMacAddrA = 0xA8, 249 NvRegMacAddrA = 0xA8,
248 NvRegMacAddrB = 0xAC, 250 NvRegMacAddrB = 0xAC,
249 NvRegMulticastAddrA = 0xB0, 251 NvRegMulticastAddrA = 0xB0,
@@ -269,8 +271,10 @@ enum {
269#define NVREG_LINKSPEED_MASK (0xFFF) 271#define NVREG_LINKSPEED_MASK (0xFFF)
270 NvRegUnknownSetupReg5 = 0x130, 272 NvRegUnknownSetupReg5 = 0x130,
271#define NVREG_UNKSETUP5_BIT31 (1<<31) 273#define NVREG_UNKSETUP5_BIT31 (1<<31)
272 NvRegUnknownSetupReg3 = 0x13c, 274 NvRegTxWatermark = 0x13c,
273#define NVREG_UNKSETUP3_VAL1 0x200010 275#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
276#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
277#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
274 NvRegTxRxControl = 0x144, 278 NvRegTxRxControl = 0x144,
275#define NVREG_TXRXCTL_KICK 0x0001 279#define NVREG_TXRXCTL_KICK 0x0001
276#define NVREG_TXRXCTL_BIT1 0x0002 280#define NVREG_TXRXCTL_BIT1 0x0002
@@ -658,7 +662,7 @@ static const struct register_test nv_registers_test[] = {
658 { NvRegMisc1, 0x03c }, 662 { NvRegMisc1, 0x03c },
659 { NvRegOffloadConfig, 0x03ff }, 663 { NvRegOffloadConfig, 0x03ff },
660 { NvRegMulticastAddrA, 0xffffffff }, 664 { NvRegMulticastAddrA, 0xffffffff },
661 { NvRegUnknownSetupReg3, 0x0ff }, 665 { NvRegTxWatermark, 0x0ff },
662 { NvRegWakeUpFlags, 0x07777 }, 666 { NvRegWakeUpFlags, 0x07777 },
663 { 0,0 } 667 { 0,0 }
664}; 668};
@@ -1495,7 +1499,7 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1495 np->tx_skbuff[nr] = skb; 1499 np->tx_skbuff[nr] = skb;
1496 1500
1497#ifdef NETIF_F_TSO 1501#ifdef NETIF_F_TSO
1498 if (skb_shinfo(skb)->gso_size) 1502 if (skb_is_gso(skb))
1499 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); 1503 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1500 else 1504 else
1501#endif 1505#endif
@@ -2127,7 +2131,7 @@ static int nv_update_linkspeed(struct net_device *dev)
2127 int newdup = np->duplex; 2131 int newdup = np->duplex;
2128 int mii_status; 2132 int mii_status;
2129 int retval = 0; 2133 int retval = 0;
2130 u32 control_1000, status_1000, phyreg, pause_flags; 2134 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2131 2135
2132 /* BMSR_LSTATUS is latched, read it twice: 2136 /* BMSR_LSTATUS is latched, read it twice:
2133 * we want the current value. 2137 * we want the current value.
@@ -2245,6 +2249,26 @@ set_speed:
2245 phyreg |= PHY_1000; 2249 phyreg |= PHY_1000;
2246 writel(phyreg, base + NvRegPhyInterface); 2250 writel(phyreg, base + NvRegPhyInterface);
2247 2251
2252 if (phyreg & PHY_RGMII) {
2253 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2254 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2255 else
2256 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2257 } else {
2258 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2259 }
2260 writel(txreg, base + NvRegTxDeferral);
2261
2262 if (np->desc_ver == DESC_VER_1) {
2263 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2264 } else {
2265 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2266 txreg = NVREG_TX_WM_DESC2_3_1000;
2267 else
2268 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2269 }
2270 writel(txreg, base + NvRegTxWatermark);
2271
2248 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), 2272 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2249 base + NvRegMisc1); 2273 base + NvRegMisc1);
2250 pci_push(base); 2274 pci_push(base);
@@ -3910,7 +3934,10 @@ static int nv_open(struct net_device *dev)
3910 3934
3911 /* 5) continue setup */ 3935 /* 5) continue setup */
3912 writel(np->linkspeed, base + NvRegLinkSpeed); 3936 writel(np->linkspeed, base + NvRegLinkSpeed);
3913 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); 3937 if (np->desc_ver == DESC_VER_1)
3938 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
3939 else
3940 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
3914 writel(np->txrxctl_bits, base + NvRegTxRxControl); 3941 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3915 writel(np->vlanctl_bits, base + NvRegVlanControl); 3942 writel(np->vlanctl_bits, base + NvRegVlanControl);
3916 pci_push(base); 3943 pci_push(base);
@@ -3932,8 +3959,8 @@ static int nv_open(struct net_device *dev)
3932 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); 3959 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3933 get_random_bytes(&i, sizeof(i)); 3960 get_random_bytes(&i, sizeof(i));
3934 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); 3961 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3935 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); 3962 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
3936 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); 3963 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
3937 if (poll_interval == -1) { 3964 if (poll_interval == -1) {
3938 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) 3965 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3939 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); 3966 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
diff --git a/drivers/net/gt96100eth.c b/drivers/net/gt96100eth.c
index 49dacc6e35aa..2b4db7414475 100644
--- a/drivers/net/gt96100eth.c
+++ b/drivers/net/gt96100eth.c
@@ -699,7 +699,6 @@ static int __init gt96100_probe1(struct pci_dev *pci, int port_num)
699 memset(gp, 0, sizeof(*gp)); // clear it 699 memset(gp, 0, sizeof(*gp)); // clear it
700 700
701 gp->port_num = port_num; 701 gp->port_num = port_num;
702 gp->io_size = GT96100_ETH_IO_SIZE;
703 gp->port_offset = port_num * GT96100_ETH_IO_SIZE; 702 gp->port_offset = port_num * GT96100_ETH_IO_SIZE;
704 gp->phy_addr = phy_addr; 703 gp->phy_addr = phy_addr;
705 gp->chip_rev = chip_rev; 704 gp->chip_rev = chip_rev;
@@ -1531,7 +1530,7 @@ static void gt96100_cleanup_module(void)
1531 + sizeof(gt96100_td_t) * TX_RING_SIZE, 1530 + sizeof(gt96100_td_t) * TX_RING_SIZE,
1532 gp->rx_ring); 1531 gp->rx_ring);
1533 free_netdev(gtif->dev); 1532 free_netdev(gtif->dev);
1534 release_region(gtif->iobase, gp->io_size); 1533 release_region(gtif->iobase, GT96100_ETH_IO_SIZE);
1535 } 1534 }
1536 } 1535 }
1537} 1536}
diff --git a/drivers/net/gt96100eth.h b/drivers/net/gt96100eth.h
index 2a8331938b84..3b62a87c7d7f 100644
--- a/drivers/net/gt96100eth.h
+++ b/drivers/net/gt96100eth.h
@@ -331,7 +331,6 @@ struct gt96100_private {
331 mib_counters_t mib; 331 mib_counters_t mib;
332 struct net_device_stats stats; 332 struct net_device_stats stats;
333 333
334 int io_size;
335 int port_num; // 0 or 1 334 int port_num; // 0 or 1
336 int chip_rev; 335 int chip_rev;
337 u32 port_offset; 336 u32 port_offset;
@@ -340,7 +339,6 @@ struct gt96100_private {
340 u32 last_psr; // last value of the port status register 339 u32 last_psr; // last value of the port status register
341 340
342 int options; /* User-settable misc. driver options. */ 341 int options; /* User-settable misc. driver options. */
343 int drv_flags;
344 struct timer_list timer; 342 struct timer_list timer;
345 spinlock_t lock; /* Serialise access to device */ 343 spinlock_t lock; /* Serialise access to device */
346}; 344};
diff --git a/drivers/net/hamachi.c b/drivers/net/hamachi.c
index 7bcd939c6edd..409c6aab0411 100644
--- a/drivers/net/hamachi.c
+++ b/drivers/net/hamachi.c
@@ -20,22 +20,15 @@
20 20
21 Support and updates available at 21 Support and updates available at
22 http://www.scyld.com/network/hamachi.html 22 http://www.scyld.com/network/hamachi.html
23 [link no longer provides useful info -jgarzik]
23 or 24 or
24 http://www.parl.clemson.edu/~keithu/hamachi.html 25 http://www.parl.clemson.edu/~keithu/hamachi.html
25 26
26
27
28 Linux kernel changelog:
29
30 LK1.0.1:
31 - fix lack of pci_dev<->dev association
32 - ethtool support (jgarzik)
33
34*/ 27*/
35 28
36#define DRV_NAME "hamachi" 29#define DRV_NAME "hamachi"
37#define DRV_VERSION "1.01+LK1.0.1" 30#define DRV_VERSION "2.0"
38#define DRV_RELDATE "5/18/2001" 31#define DRV_RELDATE "June 27, 2006"
39 32
40 33
41/* A few user-configurable values. */ 34/* A few user-configurable values. */
@@ -608,7 +601,8 @@ static int __devinit hamachi_init_one (struct pci_dev *pdev,
608 pci_set_master(pdev); 601 pci_set_master(pdev);
609 602
610 i = pci_request_regions(pdev, DRV_NAME); 603 i = pci_request_regions(pdev, DRV_NAME);
611 if (i) return i; 604 if (i)
605 return i;
612 606
613 irq = pdev->irq; 607 irq = pdev->irq;
614 ioaddr = ioremap(base, 0x400); 608 ioaddr = ioremap(base, 0x400);
diff --git a/drivers/net/hamradio/bpqether.c b/drivers/net/hamradio/bpqether.c
index 0641f54fc638..889f338132fa 100644
--- a/drivers/net/hamradio/bpqether.c
+++ b/drivers/net/hamradio/bpqether.c
@@ -122,6 +122,12 @@ struct bpqdev {
122 122
123static LIST_HEAD(bpq_devices); 123static LIST_HEAD(bpq_devices);
124 124
125/*
126 * bpqether network devices are paired with ethernet devices below them, so
127 * form a special "super class" of normal ethernet devices; split their locks
128 * off into a separate class since they always nest.
129 */
130static struct lock_class_key bpq_netdev_xmit_lock_key;
125 131
126/* ------------------------------------------------------------------------ */ 132/* ------------------------------------------------------------------------ */
127 133
@@ -528,6 +534,7 @@ static int bpq_new_device(struct net_device *edev)
528 err = register_netdevice(ndev); 534 err = register_netdevice(ndev);
529 if (err) 535 if (err)
530 goto error; 536 goto error;
537 lockdep_set_class(&ndev->_xmit_lock, &bpq_netdev_xmit_lock_key);
531 538
532 /* List protected by RTNL */ 539 /* List protected by RTNL */
533 list_add_rcu(&bpq->bpq_list, &bpq_devices); 540 list_add_rcu(&bpq->bpq_list, &bpq_devices);
diff --git a/drivers/net/ifb.c b/drivers/net/ifb.c
index 3a42afab5036..43e3f33ed5e2 100644
--- a/drivers/net/ifb.c
+++ b/drivers/net/ifb.c
@@ -271,6 +271,7 @@ static int __init ifb_init_module(void)
271 for (i = 0; i < numifbs && !err; i++) 271 for (i = 0; i < numifbs && !err; i++)
272 err = ifb_init_one(i); 272 err = ifb_init_one(i);
273 if (err) { 273 if (err) {
274 i--;
274 while (--i >= 0) 275 while (--i >= 0)
275 ifb_free_one(i); 276 ifb_free_one(i);
276 } 277 }
diff --git a/drivers/net/irda/ali-ircc.c b/drivers/net/irda/ali-ircc.c
index bf1fca5a3fa0..e3c8cd5eca67 100644
--- a/drivers/net/irda/ali-ircc.c
+++ b/drivers/net/irda/ali-ircc.c
@@ -146,7 +146,7 @@ static int __init ali_ircc_init(void)
146{ 146{
147 ali_chip_t *chip; 147 ali_chip_t *chip;
148 chipio_t info; 148 chipio_t info;
149 int ret = -ENODEV; 149 int ret;
150 int cfg, cfg_base; 150 int cfg, cfg_base;
151 int reg, revision; 151 int reg, revision;
152 int i = 0; 152 int i = 0;
@@ -160,6 +160,7 @@ static int __init ali_ircc_init(void)
160 return ret; 160 return ret;
161 } 161 }
162 162
163 ret = -ENODEV;
163 164
164 /* Probe for all the ALi chipsets we know about */ 165 /* Probe for all the ALi chipsets we know about */
165 for (chip= chips; chip->name; chip++, i++) 166 for (chip= chips; chip->name; chip++, i++)
diff --git a/drivers/net/irda/smsc-ircc2.c b/drivers/net/irda/smsc-ircc2.c
index a4674044bd6f..2eff45bedc7c 100644
--- a/drivers/net/irda/smsc-ircc2.c
+++ b/drivers/net/irda/smsc-ircc2.c
@@ -2353,7 +2353,7 @@ static int __init smsc_superio_lpc(unsigned short cfg_base)
2353#ifdef CONFIG_PCI 2353#ifdef CONFIG_PCI
2354#define PCIID_VENDOR_INTEL 0x8086 2354#define PCIID_VENDOR_INTEL 0x8086
2355#define PCIID_VENDOR_ALI 0x10b9 2355#define PCIID_VENDOR_ALI 0x10b9
2356static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __devinitdata = { 2356static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2357 { 2357 {
2358 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2358 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2359 .device = 0x24cc, 2359 .device = 0x24cc,
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index b91e082483f6..7bbd447289b5 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -1173,7 +1173,7 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1173 uint16_t ipcse, tucse, mss; 1173 uint16_t ipcse, tucse, mss;
1174 int err; 1174 int err;
1175 1175
1176 if(likely(skb_shinfo(skb)->gso_size)) { 1176 if (likely(skb_is_gso(skb))) {
1177 if (skb_header_cloned(skb)) { 1177 if (skb_header_cloned(skb)) {
1178 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 1178 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1179 if (err) 1179 if (err)
@@ -1281,7 +1281,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1281 1281
1282 while(len) { 1282 while(len) {
1283 buffer_info = &tx_ring->buffer_info[i]; 1283 buffer_info = &tx_ring->buffer_info[i];
1284 size = min(len, IXGB_MAX_JUMBO_FRAME_SIZE); 1284 size = min(len, IXGB_MAX_DATA_PER_TXD);
1285 buffer_info->length = size; 1285 buffer_info->length = size;
1286 buffer_info->dma = 1286 buffer_info->dma =
1287 pci_map_single(adapter->pdev, 1287 pci_map_single(adapter->pdev,
@@ -1306,7 +1306,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1306 1306
1307 while(len) { 1307 while(len) {
1308 buffer_info = &tx_ring->buffer_info[i]; 1308 buffer_info = &tx_ring->buffer_info[i];
1309 size = min(len, IXGB_MAX_JUMBO_FRAME_SIZE); 1309 size = min(len, IXGB_MAX_DATA_PER_TXD);
1310 buffer_info->length = size; 1310 buffer_info->length = size;
1311 buffer_info->dma = 1311 buffer_info->dma =
1312 pci_map_page(adapter->pdev, 1312 pci_map_page(adapter->pdev,
diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c
index 43fef7de8cb9..997cbce9af6e 100644
--- a/drivers/net/loopback.c
+++ b/drivers/net/loopback.c
@@ -139,7 +139,7 @@ static int loopback_xmit(struct sk_buff *skb, struct net_device *dev)
139#endif 139#endif
140 140
141#ifdef LOOPBACK_TSO 141#ifdef LOOPBACK_TSO
142 if (skb_shinfo(skb)->gso_size) { 142 if (skb_is_gso(skb)) {
143 BUG_ON(skb->protocol != htons(ETH_P_IP)); 143 BUG_ON(skb->protocol != htons(ETH_P_IP));
144 BUG_ON(skb->nh.iph->protocol != IPPROTO_TCP); 144 BUG_ON(skb->nh.iph->protocol != IPPROTO_TCP);
145 145
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 72aad42db7b4..06440a86baef 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -177,6 +177,7 @@ struct myri10ge_priv {
177 struct work_struct watchdog_work; 177 struct work_struct watchdog_work;
178 struct timer_list watchdog_timer; 178 struct timer_list watchdog_timer;
179 int watchdog_tx_done; 179 int watchdog_tx_done;
180 int watchdog_tx_req;
180 int watchdog_resets; 181 int watchdog_resets;
181 int tx_linearized; 182 int tx_linearized;
182 int pause; 183 int pause;
@@ -188,7 +189,6 @@ struct myri10ge_priv {
188 int vendor_specific_offset; 189 int vendor_specific_offset;
189 u32 devctl; 190 u32 devctl;
190 u16 msi_flags; 191 u16 msi_flags;
191 u32 pm_state[16];
192 u32 read_dma; 192 u32 read_dma;
193 u32 write_dma; 193 u32 write_dma;
194 u32 read_write_dma; 194 u32 read_write_dma;
@@ -449,6 +449,7 @@ static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
449 struct mcp_gen_header *hdr; 449 struct mcp_gen_header *hdr;
450 size_t hdr_offset; 450 size_t hdr_offset;
451 int status; 451 int status;
452 unsigned i;
452 453
453 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) { 454 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
454 dev_err(dev, "Unable to load %s firmware image via hotplug\n", 455 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
@@ -480,18 +481,12 @@ static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
480 goto abort_with_fw; 481 goto abort_with_fw;
481 482
482 crc = crc32(~0, fw->data, fw->size); 483 crc = crc32(~0, fw->data, fw->size);
483 if (mgp->tx.boundary == 2048) { 484 for (i = 0; i < fw->size; i += 256) {
484 /* Avoid PCI burst on chipset with unaligned completions. */ 485 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
485 int i; 486 fw->data + i,
486 __iomem u32 *ptr = (__iomem u32 *) (mgp->sram + 487 min(256U, (unsigned)(fw->size - i)));
487 MYRI10GE_FW_OFFSET); 488 mb();
488 for (i = 0; i < fw->size / 4; i++) { 489 readb(mgp->sram);
489 __raw_writel(((u32 *) fw->data)[i], ptr + i);
490 wmb();
491 }
492 } else {
493 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET, fw->data,
494 fw->size);
495 } 490 }
496 /* corruption checking is good for parity recovery and buggy chipset */ 491 /* corruption checking is good for parity recovery and buggy chipset */
497 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size); 492 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
@@ -621,7 +616,7 @@ static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
621 return -ENXIO; 616 return -ENXIO;
622 } 617 }
623 dev_info(&mgp->pdev->dev, "handoff confirmed\n"); 618 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
624 myri10ge_dummy_rdma(mgp, mgp->tx.boundary != 4096); 619 myri10ge_dummy_rdma(mgp, 1);
625 620
626 return 0; 621 return 0;
627} 622}
@@ -1289,6 +1284,7 @@ static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1289 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 1284 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1290 "tx_heartbeat_errors", "tx_window_errors", 1285 "tx_heartbeat_errors", "tx_window_errors",
1291 /* device-specific stats */ 1286 /* device-specific stats */
1287 "tx_boundary", "WC", "irq", "MSI",
1292 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs", 1288 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1293 "serial_number", "tx_pkt_start", "tx_pkt_done", 1289 "serial_number", "tx_pkt_start", "tx_pkt_done",
1294 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt", 1290 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
@@ -1327,6 +1323,10 @@ myri10ge_get_ethtool_stats(struct net_device *netdev,
1327 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++) 1323 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1328 data[i] = ((unsigned long *)&mgp->stats)[i]; 1324 data[i] = ((unsigned long *)&mgp->stats)[i];
1329 1325
1326 data[i++] = (unsigned int)mgp->tx.boundary;
1327 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1328 data[i++] = (unsigned int)mgp->pdev->irq;
1329 data[i++] = (unsigned int)mgp->msi_enabled;
1330 data[i++] = (unsigned int)mgp->read_dma; 1330 data[i++] = (unsigned int)mgp->read_dma;
1331 data[i++] = (unsigned int)mgp->write_dma; 1331 data[i++] = (unsigned int)mgp->write_dma;
1332 data[i++] = (unsigned int)mgp->read_write_dma; 1332 data[i++] = (unsigned int)mgp->read_write_dma;
@@ -2112,7 +2112,7 @@ abort_linearize:
2112 } 2112 }
2113 idx = (idx + 1) & tx->mask; 2113 idx = (idx + 1) & tx->mask;
2114 } while (idx != last_idx); 2114 } while (idx != last_idx);
2115 if (skb_shinfo(skb)->gso_size) { 2115 if (skb_is_gso(skb)) {
2116 printk(KERN_ERR 2116 printk(KERN_ERR
2117 "myri10ge: %s: TSO but wanted to linearize?!?!?\n", 2117 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2118 mgp->dev->name); 2118 mgp->dev->name);
@@ -2197,8 +2197,6 @@ static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2197 * any other device, except if forced with myri10ge_ecrc_enable > 1. 2197 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2198 */ 2198 */
2199 2199
2200#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_PCIE 0x005d
2201
2202static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp) 2200static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2203{ 2201{
2204 struct pci_dev *bridge = mgp->pdev->bus->self; 2202 struct pci_dev *bridge = mgp->pdev->bus->self;
@@ -2410,14 +2408,20 @@ static int myri10ge_resume(struct pci_dev *pdev)
2410 return -EIO; 2408 return -EIO;
2411 } 2409 }
2412 myri10ge_restore_state(mgp); 2410 myri10ge_restore_state(mgp);
2413 pci_enable_device(pdev); 2411
2412 status = pci_enable_device(pdev);
2413 if (status < 0) {
2414 dev_err(&pdev->dev, "failed to enable device\n");
2415 return -EIO;
2416 }
2417
2414 pci_set_master(pdev); 2418 pci_set_master(pdev);
2415 2419
2416 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED, 2420 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2417 netdev->name, mgp); 2421 netdev->name, mgp);
2418 if (status != 0) { 2422 if (status != 0) {
2419 dev_err(&pdev->dev, "failed to allocate IRQ\n"); 2423 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2420 goto abort_with_msi; 2424 goto abort_with_enabled;
2421 } 2425 }
2422 2426
2423 myri10ge_reset(mgp); 2427 myri10ge_reset(mgp);
@@ -2436,7 +2440,8 @@ static int myri10ge_resume(struct pci_dev *pdev)
2436 2440
2437 return 0; 2441 return 0;
2438 2442
2439abort_with_msi: 2443abort_with_enabled:
2444 pci_disable_device(pdev);
2440 return -EIO; 2445 return -EIO;
2441 2446
2442} 2447}
@@ -2538,7 +2543,8 @@ static void myri10ge_watchdog_timer(unsigned long arg)
2538 2543
2539 mgp = (struct myri10ge_priv *)arg; 2544 mgp = (struct myri10ge_priv *)arg;
2540 if (mgp->tx.req != mgp->tx.done && 2545 if (mgp->tx.req != mgp->tx.done &&
2541 mgp->tx.done == mgp->watchdog_tx_done) 2546 mgp->tx.done == mgp->watchdog_tx_done &&
2547 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
2542 /* nic seems like it might be stuck.. */ 2548 /* nic seems like it might be stuck.. */
2543 schedule_work(&mgp->watchdog_work); 2549 schedule_work(&mgp->watchdog_work);
2544 else 2550 else
@@ -2547,6 +2553,7 @@ static void myri10ge_watchdog_timer(unsigned long arg)
2547 jiffies + myri10ge_watchdog_timeout * HZ); 2553 jiffies + myri10ge_watchdog_timeout * HZ);
2548 2554
2549 mgp->watchdog_tx_done = mgp->tx.done; 2555 mgp->watchdog_tx_done = mgp->tx.done;
2556 mgp->watchdog_tx_req = mgp->tx.req;
2550} 2557}
2551 2558
2552static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2559static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
@@ -2737,11 +2744,10 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2737 dev_err(&pdev->dev, "register_netdev failed: %d\n", status); 2744 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2738 goto abort_with_irq; 2745 goto abort_with_irq;
2739 } 2746 }
2740 2747 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2741 printk(KERN_INFO "myri10ge: %s: %s IRQ %d, tx bndry %d, fw %s, WC %s\n", 2748 (mgp->msi_enabled ? "MSI" : "xPIC"),
2742 netdev->name, (mgp->msi_enabled ? "MSI" : "xPIC"), 2749 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2743 pdev->irq, mgp->tx.boundary, mgp->fw_name, 2750 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2744 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2745 2751
2746 return 0; 2752 return 0;
2747 2753
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 9df2628be1e7..db0475a1102f 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -20,120 +20,9 @@
20 20
21 Support information and updates available at 21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html 22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
23 24
24 25
25 Linux kernel modifications:
26
27 Version 1.0.1:
28 - Spinlock fixes
29 - Bug fixes and better intr performance (Tjeerd)
30 Version 1.0.2:
31 - Now reads correct MAC address from eeprom
32 Version 1.0.3:
33 - Eliminate redundant priv->tx_full flag
34 - Call netif_start_queue from dev->tx_timeout
35 - wmb() in start_tx() to flush data
36 - Update Tx locking
37 - Clean up PCI enable (davej)
38 Version 1.0.4:
39 - Merge Donald Becker's natsemi.c version 1.07
40 Version 1.0.5:
41 - { fill me in }
42 Version 1.0.6:
43 * ethtool support (jgarzik)
44 * Proper initialization of the card (which sometimes
45 fails to occur and leaves the card in a non-functional
46 state). (uzi)
47
48 * Some documented register settings to optimize some
49 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
50
51 * Polling of the PHY intr for stuff like link state
52 change and auto- negotiation to finally work properly. (uzi)
53
54 * One-liner removal of a duplicate declaration of
55 netdev_error(). (uzi)
56
57 Version 1.0.7: (Manfred Spraul)
58 * pci dma
59 * SMP locking update
60 * full reset added into tx_timeout
61 * correct multicast hash generation (both big and little endian)
62 [copied from a natsemi driver version
63 from Myrio Corporation, Greg Smith]
64 * suspend/resume
65
66 version 1.0.8 (Tim Hockin <thockin@sun.com>)
67 * ETHTOOL_* support
68 * Wake on lan support (Erik Gilling)
69 * MXDMA fixes for serverworks
70 * EEPROM reload
71
72 version 1.0.9 (Manfred Spraul)
73 * Main change: fix lack of synchronize
74 netif_close/netif_suspend against a last interrupt
75 or packet.
76 * do not enable superflous interrupts (e.g. the
77 drivers relies on TxDone - TxIntr not needed)
78 * wait that the hardware has really stopped in close
79 and suspend.
80 * workaround for the (at least) gcc-2.95.1 compiler
81 problem. Also simplifies the code a bit.
82 * disable_irq() in tx_timeout - needed to protect
83 against rx interrupts.
84 * stop the nic before switching into silent rx mode
85 for wol (required according to docu).
86
87 version 1.0.10:
88 * use long for ee_addr (various)
89 * print pointers properly (DaveM)
90 * include asm/irq.h (?)
91
92 version 1.0.11:
93 * check and reset if PHY errors appear (Adrian Sun)
94 * WoL cleanup (Tim Hockin)
95 * Magic number cleanup (Tim Hockin)
96 * Don't reload EEPROM on every reset (Tim Hockin)
97 * Save and restore EEPROM state across reset (Tim Hockin)
98 * MDIO Cleanup (Tim Hockin)
99 * Reformat register offsets/bits (jgarzik)
100
101 version 1.0.12:
102 * ETHTOOL_* further support (Tim Hockin)
103
104 version 1.0.13:
105 * ETHTOOL_[G]EEPROM support (Tim Hockin)
106
107 version 1.0.13:
108 * crc cleanup (Matt Domsch <Matt_Domsch@dell.com>)
109
110 version 1.0.14:
111 * Cleanup some messages and autoneg in ethtool (Tim Hockin)
112
113 version 1.0.15:
114 * Get rid of cable_magic flag
115 * use new (National provided) solution for cable magic issue
116
117 version 1.0.16:
118 * call netdev_rx() for RxErrors (Manfred Spraul)
119 * formatting and cleanups
120 * change options and full_duplex arrays to be zero
121 initialized
122 * enable only the WoL and PHY interrupts in wol mode
123
124 version 1.0.17:
125 * only do cable_magic on 83815 and early 83816 (Tim Hockin)
126 * create a function for rx refill (Manfred Spraul)
127 * combine drain_ring and init_ring (Manfred Spraul)
128 * oom handling (Manfred Spraul)
129 * hands_off instead of playing with netif_device_{de,a}ttach
130 (Manfred Spraul)
131 * be sure to write the MAC back to the chip (Manfred Spraul)
132 * lengthen EEPROM timeout, and always warn about timeouts
133 (Manfred Spraul)
134 * comments update (Manfred)
135 * do the right thing on a phy-reset (Manfred and Tim)
136
137 TODO: 26 TODO:
138 * big endian support with CFG:BEM instead of cpu_to_le32 27 * big endian support with CFG:BEM instead of cpu_to_le32
139*/ 28*/
@@ -165,8 +54,8 @@
165#include <asm/uaccess.h> 54#include <asm/uaccess.h>
166 55
167#define DRV_NAME "natsemi" 56#define DRV_NAME "natsemi"
168#define DRV_VERSION "1.07+LK1.0.17" 57#define DRV_VERSION "2.0"
169#define DRV_RELDATE "Sep 27, 2002" 58#define DRV_RELDATE "June 27, 2006"
170 59
171#define RX_OFFSET 2 60#define RX_OFFSET 2
172 61
diff --git a/drivers/net/ne2k-pci.c b/drivers/net/ne2k-pci.c
index fa50eb889408..34bdba9eec79 100644
--- a/drivers/net/ne2k-pci.c
+++ b/drivers/net/ne2k-pci.c
@@ -231,12 +231,12 @@ static int __devinit ne2k_pci_init_one (struct pci_dev *pdev,
231 irq = pdev->irq; 231 irq = pdev->irq;
232 232
233 if (!ioaddr || ((pci_resource_flags (pdev, 0) & IORESOURCE_IO) == 0)) { 233 if (!ioaddr || ((pci_resource_flags (pdev, 0) & IORESOURCE_IO) == 0)) {
234 printk (KERN_ERR PFX "no I/O resource at PCI BAR #0\n"); 234 dev_err(&pdev->dev, "no I/O resource at PCI BAR #0\n");
235 return -ENODEV; 235 return -ENODEV;
236 } 236 }
237 237
238 if (request_region (ioaddr, NE_IO_EXTENT, DRV_NAME) == NULL) { 238 if (request_region (ioaddr, NE_IO_EXTENT, DRV_NAME) == NULL) {
239 printk (KERN_ERR PFX "I/O resource 0x%x @ 0x%lx busy\n", 239 dev_err(&pdev->dev, "I/O resource 0x%x @ 0x%lx busy\n",
240 NE_IO_EXTENT, ioaddr); 240 NE_IO_EXTENT, ioaddr);
241 return -EBUSY; 241 return -EBUSY;
242 } 242 }
@@ -263,7 +263,7 @@ static int __devinit ne2k_pci_init_one (struct pci_dev *pdev,
263 /* Allocate net_device, dev->priv; fill in 8390 specific dev fields. */ 263 /* Allocate net_device, dev->priv; fill in 8390 specific dev fields. */
264 dev = alloc_ei_netdev(); 264 dev = alloc_ei_netdev();
265 if (!dev) { 265 if (!dev) {
266 printk (KERN_ERR PFX "cannot allocate ethernet device\n"); 266 dev_err(&pdev->dev, "cannot allocate ethernet device\n");
267 goto err_out_free_res; 267 goto err_out_free_res;
268 } 268 }
269 SET_MODULE_OWNER(dev); 269 SET_MODULE_OWNER(dev);
@@ -281,7 +281,8 @@ static int __devinit ne2k_pci_init_one (struct pci_dev *pdev,
281 while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0) 281 while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0)
282 /* Limit wait: '2' avoids jiffy roll-over. */ 282 /* Limit wait: '2' avoids jiffy roll-over. */
283 if (jiffies - reset_start_time > 2) { 283 if (jiffies - reset_start_time > 2) {
284 printk(KERN_ERR PFX "Card failure (no reset ack).\n"); 284 dev_err(&pdev->dev,
285 "Card failure (no reset ack).\n");
285 goto err_out_free_netdev; 286 goto err_out_free_netdev;
286 } 287 }
287 288
diff --git a/drivers/net/ni5010.c b/drivers/net/ni5010.c
index a68bf474f6ed..d4be207d321a 100644
--- a/drivers/net/ni5010.c
+++ b/drivers/net/ni5010.c
@@ -1,17 +1,12 @@
1/* ni5010.c: A network driver for the MiCom-Interlan NI5010 ethercard. 1/* ni5010.c: A network driver for the MiCom-Interlan NI5010 ethercard.
2 * 2 *
3 * Copyright 1996,1997 Jan-Pascal van Best and Andreas Mohr. 3 * Copyright 1996,1997,2006 Jan-Pascal van Best and Andreas Mohr.
4 * 4 *
5 * This software may be used and distributed according to the terms 5 * This software may be used and distributed according to the terms
6 * of the GNU General Public License, incorporated herein by reference. 6 * of the GNU General Public License, incorporated herein by reference.
7 * 7 *
8 * The authors may be reached as: 8 * The authors may be reached as:
9 * jvbest@wi.leidenuniv.nl a.mohr@mailto.de 9 * janpascal@vanbest.org andi@lisas.de
10 * or by snail mail as
11 * Jan-Pascal van Best Andreas Mohr
12 * Klikspaanweg 58-4 Stauferstr. 6
13 * 2324 LZ Leiden D-71272 Renningen
14 * The Netherlands Germany
15 * 10 *
16 * Sources: 11 * Sources:
17 * Donald Becker's "skeleton.c" 12 * Donald Becker's "skeleton.c"
@@ -27,8 +22,9 @@
27 * 970503 v0.93: Fixed auto-irq failure on warm reboot (JB) 22 * 970503 v0.93: Fixed auto-irq failure on warm reboot (JB)
28 * 970623 v1.00: First kernel version (AM) 23 * 970623 v1.00: First kernel version (AM)
29 * 970814 v1.01: Added detection of onboard receive buffer size (AM) 24 * 970814 v1.01: Added detection of onboard receive buffer size (AM)
25 * 060611 v1.02: slight cleanup: email addresses, driver modernization.
30 * Bugs: 26 * Bugs:
31 * - None known... 27 * - not SMP-safe (no locking of I/O accesses)
32 * - Note that you have to patch ifconfig for the new /proc/net/dev 28 * - Note that you have to patch ifconfig for the new /proc/net/dev
33 * format. It gives incorrect stats otherwise. 29 * format. It gives incorrect stats otherwise.
34 * 30 *
@@ -39,7 +35,7 @@
39 * Complete merge with Andreas' driver 35 * Complete merge with Andreas' driver
40 * Implement ring buffers (Is this useful? You can't squeeze 36 * Implement ring buffers (Is this useful? You can't squeeze
41 * too many packet in a 2k buffer!) 37 * too many packet in a 2k buffer!)
42 * Implement DMA (Again, is this useful? Some docs says DMA is 38 * Implement DMA (Again, is this useful? Some docs say DMA is
43 * slower than programmed I/O) 39 * slower than programmed I/O)
44 * 40 *
45 * Compile with: 41 * Compile with:
@@ -47,7 +43,7 @@
47 * -DMODULE -c ni5010.c 43 * -DMODULE -c ni5010.c
48 * 44 *
49 * Insert with e.g.: 45 * Insert with e.g.:
50 * insmod ni5010.o io=0x300 irq=5 46 * insmod ni5010.ko io=0x300 irq=5
51 */ 47 */
52 48
53#include <linux/module.h> 49#include <linux/module.h>
@@ -69,15 +65,15 @@
69 65
70#include "ni5010.h" 66#include "ni5010.h"
71 67
72static const char *boardname = "NI5010"; 68static const char boardname[] = "NI5010";
73static char *version = 69static char version[] __initdata =
74 "ni5010.c: v1.00 06/23/97 Jan-Pascal van Best and Andreas Mohr\n"; 70 "ni5010.c: v1.02 20060611 Jan-Pascal van Best and Andreas Mohr\n";
75 71
76/* bufsize_rcv == 0 means autoprobing */ 72/* bufsize_rcv == 0 means autoprobing */
77static unsigned int bufsize_rcv; 73static unsigned int bufsize_rcv;
78 74
79#define jumpered_interrupts /* IRQ line jumpered on board */ 75#define JUMPERED_INTERRUPTS /* IRQ line jumpered on board */
80#undef jumpered_dma /* No DMA used */ 76#undef JUMPERED_DMA /* No DMA used */
81#undef FULL_IODETECT /* Only detect in portlist */ 77#undef FULL_IODETECT /* Only detect in portlist */
82 78
83#ifndef FULL_IODETECT 79#ifndef FULL_IODETECT
@@ -281,7 +277,7 @@ static int __init ni5010_probe1(struct net_device *dev, int ioaddr)
281 277
282 PRINTK2((KERN_DEBUG "%s: I/O #4 passed!\n", dev->name)); 278 PRINTK2((KERN_DEBUG "%s: I/O #4 passed!\n", dev->name));
283 279
284#ifdef jumpered_interrupts 280#ifdef JUMPERED_INTERRUPTS
285 if (dev->irq == 0xff) 281 if (dev->irq == 0xff)
286 ; 282 ;
287 else if (dev->irq < 2) { 283 else if (dev->irq < 2) {
@@ -305,7 +301,7 @@ static int __init ni5010_probe1(struct net_device *dev, int ioaddr)
305 } else if (dev->irq == 2) { 301 } else if (dev->irq == 2) {
306 dev->irq = 9; 302 dev->irq = 9;
307 } 303 }
308#endif /* jumpered_irq */ 304#endif /* JUMPERED_INTERRUPTS */
309 PRINTK2((KERN_DEBUG "%s: I/O #9 passed!\n", dev->name)); 305 PRINTK2((KERN_DEBUG "%s: I/O #9 passed!\n", dev->name));
310 306
311 /* DMA is not supported (yet?), so no use detecting it */ 307 /* DMA is not supported (yet?), so no use detecting it */
@@ -334,7 +330,7 @@ static int __init ni5010_probe1(struct net_device *dev, int ioaddr)
334 outw(0, IE_GP); /* Point GP at start of packet */ 330 outw(0, IE_GP); /* Point GP at start of packet */
335 outb(0, IE_RBUF); /* set buffer byte 0 to 0 again */ 331 outb(0, IE_RBUF); /* set buffer byte 0 to 0 again */
336 } 332 }
337 printk("// bufsize rcv/xmt=%d/%d\n", bufsize_rcv, NI5010_BUFSIZE); 333 printk("-> bufsize rcv/xmt=%d/%d\n", bufsize_rcv, NI5010_BUFSIZE);
338 memset(dev->priv, 0, sizeof(struct ni5010_local)); 334 memset(dev->priv, 0, sizeof(struct ni5010_local));
339 335
340 dev->open = ni5010_open; 336 dev->open = ni5010_open;
@@ -354,11 +350,9 @@ static int __init ni5010_probe1(struct net_device *dev, int ioaddr)
354 outb(0xff, EDLC_XCLR); /* Kill all pending xmt interrupts */ 350 outb(0xff, EDLC_XCLR); /* Kill all pending xmt interrupts */
355 351
356 printk(KERN_INFO "%s: NI5010 found at 0x%x, using IRQ %d", dev->name, ioaddr, dev->irq); 352 printk(KERN_INFO "%s: NI5010 found at 0x%x, using IRQ %d", dev->name, ioaddr, dev->irq);
357 if (dev->dma) printk(" & DMA %d", dev->dma); 353 if (dev->dma)
354 printk(" & DMA %d", dev->dma);
358 printk(".\n"); 355 printk(".\n");
359
360 printk(KERN_INFO "Join the NI5010 driver development team!\n");
361 printk(KERN_INFO "Mail to a.mohr@mailto.de or jvbest@wi.leidenuniv.nl\n");
362 return 0; 356 return 0;
363out: 357out:
364 release_region(dev->base_addr, NI5010_IO_EXTENT); 358 release_region(dev->base_addr, NI5010_IO_EXTENT);
@@ -371,7 +365,7 @@ out:
371 * 365 *
372 * This routine should set everything up anew at each open, even 366 * This routine should set everything up anew at each open, even
373 * registers that "should" only need to be set once at boot, so that 367 * registers that "should" only need to be set once at boot, so that
374 * there is non-reboot way to recover if something goes wrong. 368 * there is a non-reboot way to recover if something goes wrong.
375 */ 369 */
376 370
377static int ni5010_open(struct net_device *dev) 371static int ni5010_open(struct net_device *dev)
@@ -390,13 +384,13 @@ static int ni5010_open(struct net_device *dev)
390 * Always allocate the DMA channel after the IRQ, 384 * Always allocate the DMA channel after the IRQ,
391 * and clean up on failure. 385 * and clean up on failure.
392 */ 386 */
393#ifdef jumpered_dma 387#ifdef JUMPERED_DMA
394 if (request_dma(dev->dma, cardname)) { 388 if (request_dma(dev->dma, cardname)) {
395 printk(KERN_WARNING "%s: Cannot get dma %#2x\n", dev->name, dev->dma); 389 printk(KERN_WARNING "%s: Cannot get dma %#2x\n", dev->name, dev->dma);
396 free_irq(dev->irq, NULL); 390 free_irq(dev->irq, NULL);
397 return -EAGAIN; 391 return -EAGAIN;
398 } 392 }
399#endif /* jumpered_dma */ 393#endif /* JUMPERED_DMA */
400 394
401 PRINTK3((KERN_DEBUG "%s: passed open() #2\n", dev->name)); 395 PRINTK3((KERN_DEBUG "%s: passed open() #2\n", dev->name));
402 /* Reset the hardware here. Don't forget to set the station address. */ 396 /* Reset the hardware here. Don't forget to set the station address. */
@@ -633,7 +627,7 @@ static int ni5010_close(struct net_device *dev)
633 int ioaddr = dev->base_addr; 627 int ioaddr = dev->base_addr;
634 628
635 PRINTK2((KERN_DEBUG "%s: entering ni5010_close\n", dev->name)); 629 PRINTK2((KERN_DEBUG "%s: entering ni5010_close\n", dev->name));
636#ifdef jumpered_interrupts 630#ifdef JUMPERED_INTERRUPTS
637 free_irq(dev->irq, NULL); 631 free_irq(dev->irq, NULL);
638#endif 632#endif
639 /* Put card in held-RESET state */ 633 /* Put card in held-RESET state */
@@ -771,7 +765,7 @@ module_param(irq, int, 0);
771MODULE_PARM_DESC(io, "ni5010 I/O base address"); 765MODULE_PARM_DESC(io, "ni5010 I/O base address");
772MODULE_PARM_DESC(irq, "ni5010 IRQ number"); 766MODULE_PARM_DESC(irq, "ni5010 IRQ number");
773 767
774int init_module(void) 768static int __init ni5010_init_module(void)
775{ 769{
776 PRINTK2((KERN_DEBUG "%s: entering init_module\n", boardname)); 770 PRINTK2((KERN_DEBUG "%s: entering init_module\n", boardname));
777 /* 771 /*
@@ -792,13 +786,15 @@ int init_module(void)
792 return 0; 786 return 0;
793} 787}
794 788
795void cleanup_module(void) 789static void __exit ni5010_cleanup_module(void)
796{ 790{
797 PRINTK2((KERN_DEBUG "%s: entering cleanup_module\n", boardname)); 791 PRINTK2((KERN_DEBUG "%s: entering cleanup_module\n", boardname));
798 unregister_netdev(dev_ni5010); 792 unregister_netdev(dev_ni5010);
799 release_region(dev_ni5010->base_addr, NI5010_IO_EXTENT); 793 release_region(dev_ni5010->base_addr, NI5010_IO_EXTENT);
800 free_netdev(dev_ni5010); 794 free_netdev(dev_ni5010);
801} 795}
796module_init(ni5010_init_module);
797module_exit(ni5010_cleanup_module);
802#endif /* MODULE */ 798#endif /* MODULE */
803MODULE_LICENSE("GPL"); 799MODULE_LICENSE("GPL");
804 800
diff --git a/drivers/net/ns83820.c b/drivers/net/ns83820.c
index 70429108c40d..0e76859c90a2 100644
--- a/drivers/net/ns83820.c
+++ b/drivers/net/ns83820.c
@@ -803,7 +803,7 @@ static int ns83820_setup_rx(struct net_device *ndev)
803 803
804 writel(dev->IMR_cache, dev->base + IMR); 804 writel(dev->IMR_cache, dev->base + IMR);
805 writel(1, dev->base + IER); 805 writel(1, dev->base + IER);
806 spin_unlock_irq(&dev->misc_lock); 806 spin_unlock(&dev->misc_lock);
807 807
808 kick_rx(ndev); 808 kick_rx(ndev);
809 809
@@ -1012,8 +1012,6 @@ static void do_tx_done(struct net_device *ndev)
1012 struct ns83820 *dev = PRIV(ndev); 1012 struct ns83820 *dev = PRIV(ndev);
1013 u32 cmdsts, tx_done_idx, *desc; 1013 u32 cmdsts, tx_done_idx, *desc;
1014 1014
1015 spin_lock_irq(&dev->tx_lock);
1016
1017 dprintk("do_tx_done(%p)\n", ndev); 1015 dprintk("do_tx_done(%p)\n", ndev);
1018 tx_done_idx = dev->tx_done_idx; 1016 tx_done_idx = dev->tx_done_idx;
1019 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1017 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
@@ -1069,7 +1067,6 @@ static void do_tx_done(struct net_device *ndev)
1069 netif_start_queue(ndev); 1067 netif_start_queue(ndev);
1070 netif_wake_queue(ndev); 1068 netif_wake_queue(ndev);
1071 } 1069 }
1072 spin_unlock_irq(&dev->tx_lock);
1073} 1070}
1074 1071
1075static void ns83820_cleanup_tx(struct ns83820 *dev) 1072static void ns83820_cleanup_tx(struct ns83820 *dev)
@@ -1281,11 +1278,13 @@ static struct ethtool_ops ops = {
1281 .get_link = ns83820_get_link 1278 .get_link = ns83820_get_link
1282}; 1279};
1283 1280
1281/* this function is called in irq context from the ISR */
1284static void ns83820_mib_isr(struct ns83820 *dev) 1282static void ns83820_mib_isr(struct ns83820 *dev)
1285{ 1283{
1286 spin_lock(&dev->misc_lock); 1284 unsigned long flags;
1285 spin_lock_irqsave(&dev->misc_lock, flags);
1287 ns83820_update_stats(dev); 1286 ns83820_update_stats(dev);
1288 spin_unlock(&dev->misc_lock); 1287 spin_unlock_irqrestore(&dev->misc_lock, flags);
1289} 1288}
1290 1289
1291static void ns83820_do_isr(struct net_device *ndev, u32 isr); 1290static void ns83820_do_isr(struct net_device *ndev, u32 isr);
@@ -1307,6 +1306,8 @@ static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1307static void ns83820_do_isr(struct net_device *ndev, u32 isr) 1306static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1308{ 1307{
1309 struct ns83820 *dev = PRIV(ndev); 1308 struct ns83820 *dev = PRIV(ndev);
1309 unsigned long flags;
1310
1310#ifdef DEBUG 1311#ifdef DEBUG
1311 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC)) 1312 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1312 Dprintk("odd isr? 0x%08x\n", isr); 1313 Dprintk("odd isr? 0x%08x\n", isr);
@@ -1321,10 +1322,10 @@ static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1321 if ((ISR_RXDESC | ISR_RXOK) & isr) { 1322 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1322 prefetch(dev->rx_info.next_rx_desc); 1323 prefetch(dev->rx_info.next_rx_desc);
1323 1324
1324 spin_lock_irq(&dev->misc_lock); 1325 spin_lock_irqsave(&dev->misc_lock, flags);
1325 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK); 1326 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1326 writel(dev->IMR_cache, dev->base + IMR); 1327 writel(dev->IMR_cache, dev->base + IMR);
1327 spin_unlock_irq(&dev->misc_lock); 1328 spin_unlock_irqrestore(&dev->misc_lock, flags);
1328 1329
1329 tasklet_schedule(&dev->rx_tasklet); 1330 tasklet_schedule(&dev->rx_tasklet);
1330 //rx_irq(ndev); 1331 //rx_irq(ndev);
@@ -1370,16 +1371,18 @@ static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1370 * work has accumulated 1371 * work has accumulated
1371 */ 1372 */
1372 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) { 1373 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1374 spin_lock_irqsave(&dev->tx_lock, flags);
1373 do_tx_done(ndev); 1375 do_tx_done(ndev);
1376 spin_unlock_irqrestore(&dev->tx_lock, flags);
1374 1377
1375 /* Disable TxOk if there are no outstanding tx packets. 1378 /* Disable TxOk if there are no outstanding tx packets.
1376 */ 1379 */
1377 if ((dev->tx_done_idx == dev->tx_free_idx) && 1380 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1378 (dev->IMR_cache & ISR_TXOK)) { 1381 (dev->IMR_cache & ISR_TXOK)) {
1379 spin_lock_irq(&dev->misc_lock); 1382 spin_lock_irqsave(&dev->misc_lock, flags);
1380 dev->IMR_cache &= ~ISR_TXOK; 1383 dev->IMR_cache &= ~ISR_TXOK;
1381 writel(dev->IMR_cache, dev->base + IMR); 1384 writel(dev->IMR_cache, dev->base + IMR);
1382 spin_unlock_irq(&dev->misc_lock); 1385 spin_unlock_irqrestore(&dev->misc_lock, flags);
1383 } 1386 }
1384 } 1387 }
1385 1388
@@ -1390,10 +1393,10 @@ static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1390 * nature are expected, we must enable TxOk. 1393 * nature are expected, we must enable TxOk.
1391 */ 1394 */
1392 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) { 1395 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1393 spin_lock_irq(&dev->misc_lock); 1396 spin_lock_irqsave(&dev->misc_lock, flags);
1394 dev->IMR_cache |= ISR_TXOK; 1397 dev->IMR_cache |= ISR_TXOK;
1395 writel(dev->IMR_cache, dev->base + IMR); 1398 writel(dev->IMR_cache, dev->base + IMR);
1396 spin_unlock_irq(&dev->misc_lock); 1399 spin_unlock_irqrestore(&dev->misc_lock, flags);
1397 } 1400 }
1398 1401
1399 /* MIB interrupt: one of the statistics counters is about to overflow */ 1402 /* MIB interrupt: one of the statistics counters is about to overflow */
@@ -1455,7 +1458,7 @@ static void ns83820_tx_timeout(struct net_device *ndev)
1455 u32 tx_done_idx, *desc; 1458 u32 tx_done_idx, *desc;
1456 unsigned long flags; 1459 unsigned long flags;
1457 1460
1458 local_irq_save(flags); 1461 spin_lock_irqsave(&dev->tx_lock, flags);
1459 1462
1460 tx_done_idx = dev->tx_done_idx; 1463 tx_done_idx = dev->tx_done_idx;
1461 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1464 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
@@ -1482,7 +1485,7 @@ static void ns83820_tx_timeout(struct net_device *ndev)
1482 ndev->name, 1485 ndev->name,
1483 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 1486 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1484 1487
1485 local_irq_restore(flags); 1488 spin_unlock_irqrestore(&dev->tx_lock, flags);
1486} 1489}
1487 1490
1488static void ns83820_tx_watch(unsigned long data) 1491static void ns83820_tx_watch(unsigned long data)
@@ -1832,7 +1835,7 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
1832 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) { 1835 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1833 using_dac = 0; 1836 using_dac = 0;
1834 } else { 1837 } else {
1835 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n"); 1838 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1836 return -ENODEV; 1839 return -ENODEV;
1837 } 1840 }
1838 1841
@@ -1855,7 +1858,7 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
1855 1858
1856 err = pci_enable_device(pci_dev); 1859 err = pci_enable_device(pci_dev);
1857 if (err) { 1860 if (err) {
1858 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err); 1861 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1859 goto out_free; 1862 goto out_free;
1860 } 1863 }
1861 1864
@@ -1884,8 +1887,8 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
1884 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED, 1887 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1885 DRV_NAME, ndev); 1888 DRV_NAME, ndev);
1886 if (err) { 1889 if (err) {
1887 printk(KERN_INFO "ns83820: unable to register irq %d\n", 1890 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1888 pci_dev->irq); 1891 pci_dev->irq, err);
1889 goto out_disable; 1892 goto out_disable;
1890 } 1893 }
1891 1894
@@ -1899,7 +1902,7 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
1899 rtnl_lock(); 1902 rtnl_lock();
1900 err = dev_alloc_name(ndev, ndev->name); 1903 err = dev_alloc_name(ndev, ndev->name);
1901 if (err < 0) { 1904 if (err < 0) {
1902 printk(KERN_INFO "ns83820: unable to get netdev name: %d\n", err); 1905 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1903 goto out_free_irq; 1906 goto out_free_irq;
1904 } 1907 }
1905 1908
diff --git a/drivers/net/pci-skeleton.c b/drivers/net/pci-skeleton.c
index 3388ee1313ea..e0e293964042 100644
--- a/drivers/net/pci-skeleton.c
+++ b/drivers/net/pci-skeleton.c
@@ -601,7 +601,7 @@ static int __devinit netdrv_init_board (struct pci_dev *pdev,
601 /* dev zeroed in alloc_etherdev */ 601 /* dev zeroed in alloc_etherdev */
602 dev = alloc_etherdev (sizeof (*tp)); 602 dev = alloc_etherdev (sizeof (*tp));
603 if (dev == NULL) { 603 if (dev == NULL) {
604 printk (KERN_ERR PFX "unable to alloc new ethernet\n"); 604 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
605 DPRINTK ("EXIT, returning -ENOMEM\n"); 605 DPRINTK ("EXIT, returning -ENOMEM\n");
606 return -ENOMEM; 606 return -ENOMEM;
607 } 607 }
@@ -631,14 +631,14 @@ static int __devinit netdrv_init_board (struct pci_dev *pdev,
631 631
632 /* make sure PCI base addr 0 is PIO */ 632 /* make sure PCI base addr 0 is PIO */
633 if (!(pio_flags & IORESOURCE_IO)) { 633 if (!(pio_flags & IORESOURCE_IO)) {
634 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n"); 634 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
635 rc = -ENODEV; 635 rc = -ENODEV;
636 goto err_out; 636 goto err_out;
637 } 637 }
638 638
639 /* make sure PCI base addr 1 is MMIO */ 639 /* make sure PCI base addr 1 is MMIO */
640 if (!(mmio_flags & IORESOURCE_MEM)) { 640 if (!(mmio_flags & IORESOURCE_MEM)) {
641 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n"); 641 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
642 rc = -ENODEV; 642 rc = -ENODEV;
643 goto err_out; 643 goto err_out;
644 } 644 }
@@ -646,12 +646,12 @@ static int __devinit netdrv_init_board (struct pci_dev *pdev,
646 /* check for weird/broken PCI region reporting */ 646 /* check for weird/broken PCI region reporting */
647 if ((pio_len < NETDRV_MIN_IO_SIZE) || 647 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
648 (mmio_len < NETDRV_MIN_IO_SIZE)) { 648 (mmio_len < NETDRV_MIN_IO_SIZE)) {
649 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n"); 649 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
650 rc = -ENODEV; 650 rc = -ENODEV;
651 goto err_out; 651 goto err_out;
652 } 652 }
653 653
654 rc = pci_request_regions (pdev, "pci-skeleton"); 654 rc = pci_request_regions (pdev, MODNAME);
655 if (rc) 655 if (rc)
656 goto err_out; 656 goto err_out;
657 657
@@ -663,7 +663,7 @@ static int __devinit netdrv_init_board (struct pci_dev *pdev,
663 /* ioremap MMIO region */ 663 /* ioremap MMIO region */
664 ioaddr = ioremap (mmio_start, mmio_len); 664 ioaddr = ioremap (mmio_start, mmio_len);
665 if (ioaddr == NULL) { 665 if (ioaddr == NULL) {
666 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n"); 666 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
667 rc = -EIO; 667 rc = -EIO;
668 goto err_out_free_res; 668 goto err_out_free_res;
669 } 669 }
@@ -699,9 +699,10 @@ static int __devinit netdrv_init_board (struct pci_dev *pdev,
699 } 699 }
700 700
701 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 701 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
702 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n", 702 dev_printk (KERN_DEBUG, &pdev->dev,
703 pci_name(pdev)); 703 "unknown chip version, assuming RTL-8139\n");
704 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pci_name(pdev), NETDRV_R32 (TxConfig)); 704 dev_printk (KERN_DEBUG, &pdev->dev, "TxConfig = 0x%lx\n",
705 NETDRV_R32 (TxConfig));
705 tp->chipset = 0; 706 tp->chipset = 0;
706 707
707match: 708match:
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index d768f3d1ac28..4daafe303358 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -58,18 +58,15 @@ static const char *const version =
58 * PCI device identifiers for "new style" Linux PCI Device Drivers 58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */ 59 */
60static struct pci_device_id pcnet32_pci_tbl[] = { 60static struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
63 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
64 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
65 63
66 /* 64 /*
67 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have 65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
68 * the incorrect vendor id. 66 * the incorrect vendor id.
69 */ 67 */
70 { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
71 PCI_ANY_ID, PCI_ANY_ID, 69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
72 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0},
73 70
74 { } /* terminate list */ 71 { } /* terminate list */
75}; 72};
@@ -188,6 +185,23 @@ static int homepna[MAX_UNITS];
188 185
189#define PCNET32_TOTAL_SIZE 0x20 186#define PCNET32_TOTAL_SIZE 0x20
190 187
188#define CSR0 0
189#define CSR0_INIT 0x1
190#define CSR0_START 0x2
191#define CSR0_STOP 0x4
192#define CSR0_TXPOLL 0x8
193#define CSR0_INTEN 0x40
194#define CSR0_IDON 0x0100
195#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196#define PCNET32_INIT_LOW 1
197#define PCNET32_INIT_HIGH 2
198#define CSR3 3
199#define CSR4 4
200#define CSR5 5
201#define CSR5_SUSPEND 0x0001
202#define CSR15 15
203#define PCNET32_MC_FILTER 8
204
191/* The PCNET32 Rx and Tx ring descriptors. */ 205/* The PCNET32 Rx and Tx ring descriptors. */
192struct pcnet32_rx_head { 206struct pcnet32_rx_head {
193 u32 base; 207 u32 base;
@@ -277,7 +291,6 @@ struct pcnet32_private {
277 u32 phymask; 291 u32 phymask;
278}; 292};
279 293
280static void pcnet32_probe_vlbus(void);
281static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); 294static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
282static int pcnet32_probe1(unsigned long, int, struct pci_dev *); 295static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
283static int pcnet32_open(struct net_device *); 296static int pcnet32_open(struct net_device *);
@@ -419,6 +432,238 @@ static struct pcnet32_access pcnet32_dwio = {
419 .reset = pcnet32_dwio_reset 432 .reset = pcnet32_dwio_reset
420}; 433};
421 434
435static void pcnet32_netif_stop(struct net_device *dev)
436{
437 dev->trans_start = jiffies;
438 netif_poll_disable(dev);
439 netif_tx_disable(dev);
440}
441
442static void pcnet32_netif_start(struct net_device *dev)
443{
444 netif_wake_queue(dev);
445 netif_poll_enable(dev);
446}
447
448/*
449 * Allocate space for the new sized tx ring.
450 * Free old resources
451 * Save new resources.
452 * Any failure keeps old resources.
453 * Must be called with lp->lock held.
454 */
455static void pcnet32_realloc_tx_ring(struct net_device *dev,
456 struct pcnet32_private *lp,
457 unsigned int size)
458{
459 dma_addr_t new_ring_dma_addr;
460 dma_addr_t *new_dma_addr_list;
461 struct pcnet32_tx_head *new_tx_ring;
462 struct sk_buff **new_skb_list;
463
464 pcnet32_purge_tx_ring(dev);
465
466 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
467 sizeof(struct pcnet32_tx_head) *
468 (1 << size),
469 &new_ring_dma_addr);
470 if (new_tx_ring == NULL) {
471 if (netif_msg_drv(lp))
472 printk("\n" KERN_ERR
473 "%s: Consistent memory allocation failed.\n",
474 dev->name);
475 return;
476 }
477 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
478
479 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
480 GFP_ATOMIC);
481 if (!new_dma_addr_list) {
482 if (netif_msg_drv(lp))
483 printk("\n" KERN_ERR
484 "%s: Memory allocation failed.\n", dev->name);
485 goto free_new_tx_ring;
486 }
487
488 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
489 GFP_ATOMIC);
490 if (!new_skb_list) {
491 if (netif_msg_drv(lp))
492 printk("\n" KERN_ERR
493 "%s: Memory allocation failed.\n", dev->name);
494 goto free_new_lists;
495 }
496
497 kfree(lp->tx_skbuff);
498 kfree(lp->tx_dma_addr);
499 pci_free_consistent(lp->pci_dev,
500 sizeof(struct pcnet32_tx_head) *
501 lp->tx_ring_size, lp->tx_ring,
502 lp->tx_ring_dma_addr);
503
504 lp->tx_ring_size = (1 << size);
505 lp->tx_mod_mask = lp->tx_ring_size - 1;
506 lp->tx_len_bits = (size << 12);
507 lp->tx_ring = new_tx_ring;
508 lp->tx_ring_dma_addr = new_ring_dma_addr;
509 lp->tx_dma_addr = new_dma_addr_list;
510 lp->tx_skbuff = new_skb_list;
511 return;
512
513 free_new_lists:
514 kfree(new_dma_addr_list);
515 free_new_tx_ring:
516 pci_free_consistent(lp->pci_dev,
517 sizeof(struct pcnet32_tx_head) *
518 (1 << size),
519 new_tx_ring,
520 new_ring_dma_addr);
521 return;
522}
523
524/*
525 * Allocate space for the new sized rx ring.
526 * Re-use old receive buffers.
527 * alloc extra buffers
528 * free unneeded buffers
529 * free unneeded buffers
530 * Save new resources.
531 * Any failure keeps old resources.
532 * Must be called with lp->lock held.
533 */
534static void pcnet32_realloc_rx_ring(struct net_device *dev,
535 struct pcnet32_private *lp,
536 unsigned int size)
537{
538 dma_addr_t new_ring_dma_addr;
539 dma_addr_t *new_dma_addr_list;
540 struct pcnet32_rx_head *new_rx_ring;
541 struct sk_buff **new_skb_list;
542 int new, overlap;
543
544 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
545 sizeof(struct pcnet32_rx_head) *
546 (1 << size),
547 &new_ring_dma_addr);
548 if (new_rx_ring == NULL) {
549 if (netif_msg_drv(lp))
550 printk("\n" KERN_ERR
551 "%s: Consistent memory allocation failed.\n",
552 dev->name);
553 return;
554 }
555 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
556
557 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
558 GFP_ATOMIC);
559 if (!new_dma_addr_list) {
560 if (netif_msg_drv(lp))
561 printk("\n" KERN_ERR
562 "%s: Memory allocation failed.\n", dev->name);
563 goto free_new_rx_ring;
564 }
565
566 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
567 GFP_ATOMIC);
568 if (!new_skb_list) {
569 if (netif_msg_drv(lp))
570 printk("\n" KERN_ERR
571 "%s: Memory allocation failed.\n", dev->name);
572 goto free_new_lists;
573 }
574
575 /* first copy the current receive buffers */
576 overlap = min(size, lp->rx_ring_size);
577 for (new = 0; new < overlap; new++) {
578 new_rx_ring[new] = lp->rx_ring[new];
579 new_dma_addr_list[new] = lp->rx_dma_addr[new];
580 new_skb_list[new] = lp->rx_skbuff[new];
581 }
582 /* now allocate any new buffers needed */
583 for (; new < size; new++ ) {
584 struct sk_buff *rx_skbuff;
585 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
586 if (!(rx_skbuff = new_skb_list[new])) {
587 /* keep the original lists and buffers */
588 if (netif_msg_drv(lp))
589 printk(KERN_ERR
590 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
591 dev->name);
592 goto free_all_new;
593 }
594 skb_reserve(rx_skbuff, 2);
595
596 new_dma_addr_list[new] =
597 pci_map_single(lp->pci_dev, rx_skbuff->data,
598 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
599 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
600 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
601 new_rx_ring[new].status = le16_to_cpu(0x8000);
602 }
603 /* and free any unneeded buffers */
604 for (; new < lp->rx_ring_size; new++) {
605 if (lp->rx_skbuff[new]) {
606 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
607 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
608 dev_kfree_skb(lp->rx_skbuff[new]);
609 }
610 }
611
612 kfree(lp->rx_skbuff);
613 kfree(lp->rx_dma_addr);
614 pci_free_consistent(lp->pci_dev,
615 sizeof(struct pcnet32_rx_head) *
616 lp->rx_ring_size, lp->rx_ring,
617 lp->rx_ring_dma_addr);
618
619 lp->rx_ring_size = (1 << size);
620 lp->rx_mod_mask = lp->rx_ring_size - 1;
621 lp->rx_len_bits = (size << 4);
622 lp->rx_ring = new_rx_ring;
623 lp->rx_ring_dma_addr = new_ring_dma_addr;
624 lp->rx_dma_addr = new_dma_addr_list;
625 lp->rx_skbuff = new_skb_list;
626 return;
627
628 free_all_new:
629 for (; --new >= lp->rx_ring_size; ) {
630 if (new_skb_list[new]) {
631 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
632 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
633 dev_kfree_skb(new_skb_list[new]);
634 }
635 }
636 kfree(new_skb_list);
637 free_new_lists:
638 kfree(new_dma_addr_list);
639 free_new_rx_ring:
640 pci_free_consistent(lp->pci_dev,
641 sizeof(struct pcnet32_rx_head) *
642 (1 << size),
643 new_rx_ring,
644 new_ring_dma_addr);
645 return;
646}
647
648static void pcnet32_purge_rx_ring(struct net_device *dev)
649{
650 struct pcnet32_private *lp = dev->priv;
651 int i;
652
653 /* free all allocated skbuffs */
654 for (i = 0; i < lp->rx_ring_size; i++) {
655 lp->rx_ring[i].status = 0; /* CPU owns buffer */
656 wmb(); /* Make sure adapter sees owner change */
657 if (lp->rx_skbuff[i]) {
658 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
659 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
660 dev_kfree_skb_any(lp->rx_skbuff[i]);
661 }
662 lp->rx_skbuff[i] = NULL;
663 lp->rx_dma_addr[i] = 0;
664 }
665}
666
422#ifdef CONFIG_NET_POLL_CONTROLLER 667#ifdef CONFIG_NET_POLL_CONTROLLER
423static void pcnet32_poll_controller(struct net_device *dev) 668static void pcnet32_poll_controller(struct net_device *dev)
424{ 669{
@@ -519,10 +764,10 @@ static void pcnet32_get_ringparam(struct net_device *dev,
519{ 764{
520 struct pcnet32_private *lp = dev->priv; 765 struct pcnet32_private *lp = dev->priv;
521 766
522 ering->tx_max_pending = TX_MAX_RING_SIZE - 1; 767 ering->tx_max_pending = TX_MAX_RING_SIZE;
523 ering->tx_pending = lp->tx_ring_size - 1; 768 ering->tx_pending = lp->tx_ring_size;
524 ering->rx_max_pending = RX_MAX_RING_SIZE - 1; 769 ering->rx_max_pending = RX_MAX_RING_SIZE;
525 ering->rx_pending = lp->rx_ring_size - 1; 770 ering->rx_pending = lp->rx_ring_size;
526} 771}
527 772
528static int pcnet32_set_ringparam(struct net_device *dev, 773static int pcnet32_set_ringparam(struct net_device *dev,
@@ -530,56 +775,53 @@ static int pcnet32_set_ringparam(struct net_device *dev,
530{ 775{
531 struct pcnet32_private *lp = dev->priv; 776 struct pcnet32_private *lp = dev->priv;
532 unsigned long flags; 777 unsigned long flags;
778 unsigned int size;
779 ulong ioaddr = dev->base_addr;
533 int i; 780 int i;
534 781
535 if (ering->rx_mini_pending || ering->rx_jumbo_pending) 782 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
536 return -EINVAL; 783 return -EINVAL;
537 784
538 if (netif_running(dev)) 785 if (netif_running(dev))
539 pcnet32_close(dev); 786 pcnet32_netif_stop(dev);
540 787
541 spin_lock_irqsave(&lp->lock, flags); 788 spin_lock_irqsave(&lp->lock, flags);
542 pcnet32_free_ring(dev); 789 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
543 lp->tx_ring_size = 790
544 min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); 791 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
545 lp->rx_ring_size =
546 min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
547 792
548 /* set the minimum ring size to 4, to allow the loopback test to work 793 /* set the minimum ring size to 4, to allow the loopback test to work
549 * unchanged. 794 * unchanged.
550 */ 795 */
551 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { 796 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
552 if (lp->tx_ring_size <= (1 << i)) 797 if (size <= (1 << i))
553 break; 798 break;
554 } 799 }
555 lp->tx_ring_size = (1 << i); 800 if ((1 << i) != lp->tx_ring_size)
556 lp->tx_mod_mask = lp->tx_ring_size - 1; 801 pcnet32_realloc_tx_ring(dev, lp, i);
557 lp->tx_len_bits = (i << 12); 802
558 803 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
559 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { 804 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
560 if (lp->rx_ring_size <= (1 << i)) 805 if (size <= (1 << i))
561 break; 806 break;
562 } 807 }
563 lp->rx_ring_size = (1 << i); 808 if ((1 << i) != lp->rx_ring_size)
564 lp->rx_mod_mask = lp->rx_ring_size - 1; 809 pcnet32_realloc_rx_ring(dev, lp, i);
565 lp->rx_len_bits = (i << 4); 810
811 dev->weight = lp->rx_ring_size / 2;
566 812
567 if (pcnet32_alloc_ring(dev, dev->name)) { 813 if (netif_running(dev)) {
568 pcnet32_free_ring(dev); 814 pcnet32_netif_start(dev);
569 spin_unlock_irqrestore(&lp->lock, flags); 815 pcnet32_restart(dev, CSR0_NORMAL);
570 return -ENOMEM;
571 } 816 }
572 817
573 spin_unlock_irqrestore(&lp->lock, flags); 818 spin_unlock_irqrestore(&lp->lock, flags);
574 819
575 if (pcnet32_debug & NETIF_MSG_DRV) 820 if (netif_msg_drv(lp))
576 printk(KERN_INFO PFX 821 printk(KERN_INFO
577 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name, 822 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
578 lp->rx_ring_size, lp->tx_ring_size); 823 lp->rx_ring_size, lp->tx_ring_size);
579 824
580 if (netif_running(dev))
581 pcnet32_open(dev);
582
583 return 0; 825 return 0;
584} 826}
585 827
@@ -633,29 +875,27 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
633 unsigned long flags; 875 unsigned long flags;
634 unsigned long ticks; 876 unsigned long ticks;
635 877
636 *data1 = 1; /* status of test, default to fail */
637 rc = 1; /* default to fail */ 878 rc = 1; /* default to fail */
638 879
639 if (netif_running(dev)) 880 if (netif_running(dev))
640 pcnet32_close(dev); 881 pcnet32_close(dev);
641 882
642 spin_lock_irqsave(&lp->lock, flags); 883 spin_lock_irqsave(&lp->lock, flags);
884 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
885
886 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
643 887
644 /* Reset the PCNET32 */ 888 /* Reset the PCNET32 */
645 lp->a.reset(ioaddr); 889 lp->a.reset(ioaddr);
890 lp->a.write_csr(ioaddr, CSR4, 0x0915);
646 891
647 /* switch pcnet32 to 32bit mode */ 892 /* switch pcnet32 to 32bit mode */
648 lp->a.write_bcr(ioaddr, 20, 2); 893 lp->a.write_bcr(ioaddr, 20, 2);
649 894
650 lp->init_block.mode =
651 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
652 lp->init_block.filter[0] = 0;
653 lp->init_block.filter[1] = 0;
654
655 /* purge & init rings but don't actually restart */ 895 /* purge & init rings but don't actually restart */
656 pcnet32_restart(dev, 0x0000); 896 pcnet32_restart(dev, 0x0000);
657 897
658 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ 898 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
659 899
660 /* Initialize Transmit buffers. */ 900 /* Initialize Transmit buffers. */
661 size = data_len + 15; 901 size = data_len + 15;
@@ -697,14 +937,15 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
697 } 937 }
698 } 938 }
699 939
700 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */ 940 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
701 x = x | 0x0002; 941 a->write_bcr(ioaddr, 32, x | 0x0002);
702 a->write_bcr(ioaddr, 32, x);
703 942
704 lp->a.write_csr(ioaddr, 15, 0x0044); /* set int loopback in CSR15 */ 943 /* set int loopback in CSR15 */
944 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
945 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
705 946
706 teststatus = le16_to_cpu(0x8000); 947 teststatus = le16_to_cpu(0x8000);
707 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */ 948 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
708 949
709 /* Check status of descriptors */ 950 /* Check status of descriptors */
710 for (x = 0; x < numbuffs; x++) { 951 for (x = 0; x < numbuffs; x++) {
@@ -712,7 +953,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
712 rmb(); 953 rmb();
713 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { 954 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
714 spin_unlock_irqrestore(&lp->lock, flags); 955 spin_unlock_irqrestore(&lp->lock, flags);
715 mdelay(1); 956 msleep(1);
716 spin_lock_irqsave(&lp->lock, flags); 957 spin_lock_irqsave(&lp->lock, flags);
717 rmb(); 958 rmb();
718 ticks++; 959 ticks++;
@@ -725,7 +966,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
725 } 966 }
726 } 967 }
727 968
728 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ 969 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
729 wmb(); 970 wmb();
730 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { 971 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
731 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name); 972 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
@@ -758,25 +999,24 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
758 } 999 }
759 x++; 1000 x++;
760 } 1001 }
761 if (!rc) {
762 *data1 = 0;
763 }
764 1002
765 clean_up: 1003 clean_up:
1004 *data1 = rc;
766 pcnet32_purge_tx_ring(dev); 1005 pcnet32_purge_tx_ring(dev);
767 x = a->read_csr(ioaddr, 15) & 0xFFFF;
768 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
769 1006
770 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1007 x = a->read_csr(ioaddr, CSR15);
771 x = x & ~0x0002; 1008 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
772 a->write_bcr(ioaddr, 32, x);
773 1009
774 spin_unlock_irqrestore(&lp->lock, flags); 1010 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1011 a->write_bcr(ioaddr, 32, (x & ~0x0002));
775 1012
776 if (netif_running(dev)) { 1013 if (netif_running(dev)) {
1014 spin_unlock_irqrestore(&lp->lock, flags);
777 pcnet32_open(dev); 1015 pcnet32_open(dev);
778 } else { 1016 } else {
1017 pcnet32_purge_rx_ring(dev);
779 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1018 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1019 spin_unlock_irqrestore(&lp->lock, flags);
780 } 1020 }
781 1021
782 return (rc); 1022 return (rc);
@@ -839,6 +1079,43 @@ static int pcnet32_phys_id(struct net_device *dev, u32 data)
839 return 0; 1079 return 0;
840} 1080}
841 1081
1082/*
1083 * lp->lock must be held.
1084 */
1085static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1086 int can_sleep)
1087{
1088 int csr5;
1089 struct pcnet32_private *lp = dev->priv;
1090 struct pcnet32_access *a = &lp->a;
1091 ulong ioaddr = dev->base_addr;
1092 int ticks;
1093
1094 /* set SUSPEND (SPND) - CSR5 bit 0 */
1095 csr5 = a->read_csr(ioaddr, CSR5);
1096 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1097
1098 /* poll waiting for bit to be set */
1099 ticks = 0;
1100 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1101 spin_unlock_irqrestore(&lp->lock, *flags);
1102 if (can_sleep)
1103 msleep(1);
1104 else
1105 mdelay(1);
1106 spin_lock_irqsave(&lp->lock, *flags);
1107 ticks++;
1108 if (ticks > 200) {
1109 if (netif_msg_hw(lp))
1110 printk(KERN_DEBUG
1111 "%s: Error getting into suspend!\n",
1112 dev->name);
1113 return 0;
1114 }
1115 }
1116 return 1;
1117}
1118
842#define PCNET32_REGS_PER_PHY 32 1119#define PCNET32_REGS_PER_PHY 32
843#define PCNET32_MAX_PHYS 32 1120#define PCNET32_MAX_PHYS 32
844static int pcnet32_get_regs_len(struct net_device *dev) 1121static int pcnet32_get_regs_len(struct net_device *dev)
@@ -857,32 +1134,13 @@ static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
857 struct pcnet32_private *lp = dev->priv; 1134 struct pcnet32_private *lp = dev->priv;
858 struct pcnet32_access *a = &lp->a; 1135 struct pcnet32_access *a = &lp->a;
859 ulong ioaddr = dev->base_addr; 1136 ulong ioaddr = dev->base_addr;
860 int ticks;
861 unsigned long flags; 1137 unsigned long flags;
862 1138
863 spin_lock_irqsave(&lp->lock, flags); 1139 spin_lock_irqsave(&lp->lock, flags);
864 1140
865 csr0 = a->read_csr(ioaddr, 0); 1141 csr0 = a->read_csr(ioaddr, CSR0);
866 if (!(csr0 & 0x0004)) { /* If not stopped */ 1142 if (!(csr0 & CSR0_STOP)) /* If not stopped */
867 /* set SUSPEND (SPND) - CSR5 bit 0 */ 1143 pcnet32_suspend(dev, &flags, 1);
868 a->write_csr(ioaddr, 5, 0x0001);
869
870 /* poll waiting for bit to be set */
871 ticks = 0;
872 while (!(a->read_csr(ioaddr, 5) & 0x0001)) {
873 spin_unlock_irqrestore(&lp->lock, flags);
874 mdelay(1);
875 spin_lock_irqsave(&lp->lock, flags);
876 ticks++;
877 if (ticks > 200) {
878 if (netif_msg_hw(lp))
879 printk(KERN_DEBUG
880 "%s: Error getting into suspend!\n",
881 dev->name);
882 break;
883 }
884 }
885 }
886 1144
887 /* read address PROM */ 1145 /* read address PROM */
888 for (i = 0; i < 16; i += 2) 1146 for (i = 0; i < 16; i += 2)
@@ -919,9 +1177,12 @@ static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
919 } 1177 }
920 } 1178 }
921 1179
922 if (!(csr0 & 0x0004)) { /* If not stopped */ 1180 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1181 int csr5;
1182
923 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 1183 /* clear SUSPEND (SPND) - CSR5 bit 0 */
924 a->write_csr(ioaddr, 5, 0x0000); 1184 csr5 = a->read_csr(ioaddr, CSR5);
1185 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
925 } 1186 }
926 1187
927 spin_unlock_irqrestore(&lp->lock, flags); 1188 spin_unlock_irqrestore(&lp->lock, flags);
@@ -952,7 +1213,7 @@ static struct ethtool_ops pcnet32_ethtool_ops = {
952/* only probes for non-PCI devices, the rest are handled by 1213/* only probes for non-PCI devices, the rest are handled by
953 * pci_register_driver via pcnet32_probe_pci */ 1214 * pci_register_driver via pcnet32_probe_pci */
954 1215
955static void __devinit pcnet32_probe_vlbus(void) 1216static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
956{ 1217{
957 unsigned int *port, ioaddr; 1218 unsigned int *port, ioaddr;
958 1219
@@ -1436,7 +1697,7 @@ static int pcnet32_alloc_ring(struct net_device *dev, char *name)
1436 lp->tx_ring_size, 1697 lp->tx_ring_size,
1437 &lp->tx_ring_dma_addr); 1698 &lp->tx_ring_dma_addr);
1438 if (lp->tx_ring == NULL) { 1699 if (lp->tx_ring == NULL) {
1439 if (pcnet32_debug & NETIF_MSG_DRV) 1700 if (netif_msg_drv(lp))
1440 printk("\n" KERN_ERR PFX 1701 printk("\n" KERN_ERR PFX
1441 "%s: Consistent memory allocation failed.\n", 1702 "%s: Consistent memory allocation failed.\n",
1442 name); 1703 name);
@@ -1448,52 +1709,48 @@ static int pcnet32_alloc_ring(struct net_device *dev, char *name)
1448 lp->rx_ring_size, 1709 lp->rx_ring_size,
1449 &lp->rx_ring_dma_addr); 1710 &lp->rx_ring_dma_addr);
1450 if (lp->rx_ring == NULL) { 1711 if (lp->rx_ring == NULL) {
1451 if (pcnet32_debug & NETIF_MSG_DRV) 1712 if (netif_msg_drv(lp))
1452 printk("\n" KERN_ERR PFX 1713 printk("\n" KERN_ERR PFX
1453 "%s: Consistent memory allocation failed.\n", 1714 "%s: Consistent memory allocation failed.\n",
1454 name); 1715 name);
1455 return -ENOMEM; 1716 return -ENOMEM;
1456 } 1717 }
1457 1718
1458 lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size, 1719 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1459 GFP_ATOMIC); 1720 GFP_ATOMIC);
1460 if (!lp->tx_dma_addr) { 1721 if (!lp->tx_dma_addr) {
1461 if (pcnet32_debug & NETIF_MSG_DRV) 1722 if (netif_msg_drv(lp))
1462 printk("\n" KERN_ERR PFX 1723 printk("\n" KERN_ERR PFX
1463 "%s: Memory allocation failed.\n", name); 1724 "%s: Memory allocation failed.\n", name);
1464 return -ENOMEM; 1725 return -ENOMEM;
1465 } 1726 }
1466 memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size);
1467 1727
1468 lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size, 1728 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1469 GFP_ATOMIC); 1729 GFP_ATOMIC);
1470 if (!lp->rx_dma_addr) { 1730 if (!lp->rx_dma_addr) {
1471 if (pcnet32_debug & NETIF_MSG_DRV) 1731 if (netif_msg_drv(lp))
1472 printk("\n" KERN_ERR PFX 1732 printk("\n" KERN_ERR PFX
1473 "%s: Memory allocation failed.\n", name); 1733 "%s: Memory allocation failed.\n", name);
1474 return -ENOMEM; 1734 return -ENOMEM;
1475 } 1735 }
1476 memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size);
1477 1736
1478 lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size, 1737 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1479 GFP_ATOMIC); 1738 GFP_ATOMIC);
1480 if (!lp->tx_skbuff) { 1739 if (!lp->tx_skbuff) {
1481 if (pcnet32_debug & NETIF_MSG_DRV) 1740 if (netif_msg_drv(lp))
1482 printk("\n" KERN_ERR PFX 1741 printk("\n" KERN_ERR PFX
1483 "%s: Memory allocation failed.\n", name); 1742 "%s: Memory allocation failed.\n", name);
1484 return -ENOMEM; 1743 return -ENOMEM;
1485 } 1744 }
1486 memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size);
1487 1745
1488 lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size, 1746 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1489 GFP_ATOMIC); 1747 GFP_ATOMIC);
1490 if (!lp->rx_skbuff) { 1748 if (!lp->rx_skbuff) {
1491 if (pcnet32_debug & NETIF_MSG_DRV) 1749 if (netif_msg_drv(lp))
1492 printk("\n" KERN_ERR PFX 1750 printk("\n" KERN_ERR PFX
1493 "%s: Memory allocation failed.\n", name); 1751 "%s: Memory allocation failed.\n", name);
1494 return -ENOMEM; 1752 return -ENOMEM;
1495 } 1753 }
1496 memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size);
1497 1754
1498 return 0; 1755 return 0;
1499} 1756}
@@ -1757,16 +2014,7 @@ static int pcnet32_open(struct net_device *dev)
1757 2014
1758 err_free_ring: 2015 err_free_ring:
1759 /* free any allocated skbuffs */ 2016 /* free any allocated skbuffs */
1760 for (i = 0; i < lp->rx_ring_size; i++) { 2017 pcnet32_purge_rx_ring(dev);
1761 lp->rx_ring[i].status = 0;
1762 if (lp->rx_skbuff[i]) {
1763 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
1764 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
1765 dev_kfree_skb(lp->rx_skbuff[i]);
1766 }
1767 lp->rx_skbuff[i] = NULL;
1768 lp->rx_dma_addr[i] = 0;
1769 }
1770 2018
1771 /* 2019 /*
1772 * Switch back to 16bit mode to avoid problems with dumb 2020 * Switch back to 16bit mode to avoid problems with dumb
@@ -2348,7 +2596,6 @@ static int pcnet32_close(struct net_device *dev)
2348{ 2596{
2349 unsigned long ioaddr = dev->base_addr; 2597 unsigned long ioaddr = dev->base_addr;
2350 struct pcnet32_private *lp = dev->priv; 2598 struct pcnet32_private *lp = dev->priv;
2351 int i;
2352 unsigned long flags; 2599 unsigned long flags;
2353 2600
2354 del_timer_sync(&lp->watchdog_timer); 2601 del_timer_sync(&lp->watchdog_timer);
@@ -2379,31 +2626,8 @@ static int pcnet32_close(struct net_device *dev)
2379 2626
2380 spin_lock_irqsave(&lp->lock, flags); 2627 spin_lock_irqsave(&lp->lock, flags);
2381 2628
2382 /* free all allocated skbuffs */ 2629 pcnet32_purge_rx_ring(dev);
2383 for (i = 0; i < lp->rx_ring_size; i++) { 2630 pcnet32_purge_tx_ring(dev);
2384 lp->rx_ring[i].status = 0;
2385 wmb(); /* Make sure adapter sees owner change */
2386 if (lp->rx_skbuff[i]) {
2387 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
2388 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2389 dev_kfree_skb(lp->rx_skbuff[i]);
2390 }
2391 lp->rx_skbuff[i] = NULL;
2392 lp->rx_dma_addr[i] = 0;
2393 }
2394
2395 for (i = 0; i < lp->tx_ring_size; i++) {
2396 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2397 wmb(); /* Make sure adapter sees owner change */
2398 if (lp->tx_skbuff[i]) {
2399 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2400 lp->tx_skbuff[i]->len,
2401 PCI_DMA_TODEVICE);
2402 dev_kfree_skb(lp->tx_skbuff[i]);
2403 }
2404 lp->tx_skbuff[i] = NULL;
2405 lp->tx_dma_addr[i] = 0;
2406 }
2407 2631
2408 spin_unlock_irqrestore(&lp->lock, flags); 2632 spin_unlock_irqrestore(&lp->lock, flags);
2409 2633
@@ -2433,6 +2657,7 @@ static void pcnet32_load_multicast(struct net_device *dev)
2433 volatile struct pcnet32_init_block *ib = &lp->init_block; 2657 volatile struct pcnet32_init_block *ib = &lp->init_block;
2434 volatile u16 *mcast_table = (u16 *) & ib->filter; 2658 volatile u16 *mcast_table = (u16 *) & ib->filter;
2435 struct dev_mc_list *dmi = dev->mc_list; 2659 struct dev_mc_list *dmi = dev->mc_list;
2660 unsigned long ioaddr = dev->base_addr;
2436 char *addrs; 2661 char *addrs;
2437 int i; 2662 int i;
2438 u32 crc; 2663 u32 crc;
@@ -2441,6 +2666,10 @@ static void pcnet32_load_multicast(struct net_device *dev)
2441 if (dev->flags & IFF_ALLMULTI) { 2666 if (dev->flags & IFF_ALLMULTI) {
2442 ib->filter[0] = 0xffffffff; 2667 ib->filter[0] = 0xffffffff;
2443 ib->filter[1] = 0xffffffff; 2668 ib->filter[1] = 0xffffffff;
2669 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2670 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2671 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2672 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2444 return; 2673 return;
2445 } 2674 }
2446 /* clear the multicast filter */ 2675 /* clear the multicast filter */
@@ -2462,6 +2691,9 @@ static void pcnet32_load_multicast(struct net_device *dev)
2462 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) | 2691 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2463 (1 << (crc & 0xf))); 2692 (1 << (crc & 0xf)));
2464 } 2693 }
2694 for (i = 0; i < 4; i++)
2695 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2696 le16_to_cpu(mcast_table[i]));
2465 return; 2697 return;
2466} 2698}
2467 2699
@@ -2472,8 +2704,11 @@ static void pcnet32_set_multicast_list(struct net_device *dev)
2472{ 2704{
2473 unsigned long ioaddr = dev->base_addr, flags; 2705 unsigned long ioaddr = dev->base_addr, flags;
2474 struct pcnet32_private *lp = dev->priv; 2706 struct pcnet32_private *lp = dev->priv;
2707 int csr15, suspended;
2475 2708
2476 spin_lock_irqsave(&lp->lock, flags); 2709 spin_lock_irqsave(&lp->lock, flags);
2710 suspended = pcnet32_suspend(dev, &flags, 0);
2711 csr15 = lp->a.read_csr(ioaddr, CSR15);
2477 if (dev->flags & IFF_PROMISC) { 2712 if (dev->flags & IFF_PROMISC) {
2478 /* Log any net taps. */ 2713 /* Log any net taps. */
2479 if (netif_msg_hw(lp)) 2714 if (netif_msg_hw(lp))
@@ -2482,15 +2717,24 @@ static void pcnet32_set_multicast_list(struct net_device *dev)
2482 lp->init_block.mode = 2717 lp->init_block.mode =
2483 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2718 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2484 7); 2719 7);
2720 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2485 } else { 2721 } else {
2486 lp->init_block.mode = 2722 lp->init_block.mode =
2487 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); 2723 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2724 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2488 pcnet32_load_multicast(dev); 2725 pcnet32_load_multicast(dev);
2489 } 2726 }
2490 2727
2491 lp->a.write_csr(ioaddr, 0, 0x0004); /* Temporarily stop the lance. */ 2728 if (suspended) {
2492 pcnet32_restart(dev, 0x0042); /* Resume normal operation */ 2729 int csr5;
2493 netif_wake_queue(dev); 2730 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2731 csr5 = lp->a.read_csr(ioaddr, CSR5);
2732 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2733 } else {
2734 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2735 pcnet32_restart(dev, CSR0_NORMAL);
2736 netif_wake_queue(dev);
2737 }
2494 2738
2495 spin_unlock_irqrestore(&lp->lock, flags); 2739 spin_unlock_irqrestore(&lp->lock, flags);
2496} 2740}
@@ -2730,7 +2974,7 @@ static int __init pcnet32_init_module(void)
2730 2974
2731 /* should we find any remaining VLbus devices ? */ 2975 /* should we find any remaining VLbus devices ? */
2732 if (pcnet32vlb) 2976 if (pcnet32vlb)
2733 pcnet32_probe_vlbus(); 2977 pcnet32_probe_vlbus(pcnet32_portlist);
2734 2978
2735 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) 2979 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2736 printk(KERN_INFO PFX "%d cards_found.\n", cards_found); 2980 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
diff --git a/drivers/net/phy/cicada.c b/drivers/net/phy/cicada.c
index 3efb715c28dc..ae60e6e4107c 100644
--- a/drivers/net/phy/cicada.c
+++ b/drivers/net/phy/cicada.c
@@ -103,7 +103,22 @@ static int cis820x_config_intr(struct phy_device *phydev)
103 return err; 103 return err;
104} 104}
105 105
106/* Cicada 820x */ 106/* Cicada 8201, a.k.a Vitesse VSC8201 */
107static struct phy_driver cis8201_driver = {
108 .phy_id = 0x000fc410,
109 .name = "Cicada Cis8201",
110 .phy_id_mask = 0x000ffff0,
111 .features = PHY_GBIT_FEATURES,
112 .flags = PHY_HAS_INTERRUPT,
113 .config_init = &cis820x_config_init,
114 .config_aneg = &genphy_config_aneg,
115 .read_status = &genphy_read_status,
116 .ack_interrupt = &cis820x_ack_interrupt,
117 .config_intr = &cis820x_config_intr,
118 .driver = { .owner = THIS_MODULE,},
119};
120
121/* Cicada 8204 */
107static struct phy_driver cis8204_driver = { 122static struct phy_driver cis8204_driver = {
108 .phy_id = 0x000fc440, 123 .phy_id = 0x000fc440,
109 .name = "Cicada Cis8204", 124 .name = "Cicada Cis8204",
@@ -118,15 +133,30 @@ static struct phy_driver cis8204_driver = {
118 .driver = { .owner = THIS_MODULE,}, 133 .driver = { .owner = THIS_MODULE,},
119}; 134};
120 135
121static int __init cis8204_init(void) 136static int __init cicada_init(void)
122{ 137{
123 return phy_driver_register(&cis8204_driver); 138 int ret;
139
140 ret = phy_driver_register(&cis8204_driver);
141 if (ret)
142 goto err1;
143
144 ret = phy_driver_register(&cis8201_driver);
145 if (ret)
146 goto err2;
147 return 0;
148
149err2:
150 phy_driver_unregister(&cis8204_driver);
151err1:
152 return ret;
124} 153}
125 154
126static void __exit cis8204_exit(void) 155static void __exit cicada_exit(void)
127{ 156{
128 phy_driver_unregister(&cis8204_driver); 157 phy_driver_unregister(&cis8204_driver);
158 phy_driver_unregister(&cis8201_driver);
129} 159}
130 160
131module_init(cis8204_init); 161module_init(cicada_init);
132module_exit(cis8204_exit); 162module_exit(cicada_exit);
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 7d5c2233c252..f5aad77288f9 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -419,9 +419,8 @@ void phy_start_machine(struct phy_device *phydev,
419 419
420/* phy_stop_machine 420/* phy_stop_machine
421 * 421 *
422 * description: Stops the state machine timer, sets the state to 422 * description: Stops the state machine timer, sets the state to UP
423 * UP (unless it wasn't up yet), and then frees the interrupt, 423 * (unless it wasn't up yet). This function must be called BEFORE
424 * if it is in use. This function must be called BEFORE
425 * phy_detach. 424 * phy_detach.
426 */ 425 */
427void phy_stop_machine(struct phy_device *phydev) 426void phy_stop_machine(struct phy_device *phydev)
@@ -433,9 +432,6 @@ void phy_stop_machine(struct phy_device *phydev)
433 phydev->state = PHY_UP; 432 phydev->state = PHY_UP;
434 spin_unlock(&phydev->lock); 433 spin_unlock(&phydev->lock);
435 434
436 if (phydev->irq != PHY_POLL)
437 phy_stop_interrupts(phydev);
438
439 phydev->adjust_state = NULL; 435 phydev->adjust_state = NULL;
440} 436}
441 437
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 16a0ef1b1369..4c2f575faad7 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -1406,7 +1406,7 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1406 dev = alloc_etherdev(sizeof (*tp)); 1406 dev = alloc_etherdev(sizeof (*tp));
1407 if (dev == NULL) { 1407 if (dev == NULL) {
1408 if (netif_msg_drv(&debug)) 1408 if (netif_msg_drv(&debug))
1409 printk(KERN_ERR PFX "unable to alloc new ethernet\n"); 1409 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1410 goto err_out; 1410 goto err_out;
1411 } 1411 }
1412 1412
@@ -1418,10 +1418,8 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1418 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 1418 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1419 rc = pci_enable_device(pdev); 1419 rc = pci_enable_device(pdev);
1420 if (rc < 0) { 1420 if (rc < 0) {
1421 if (netif_msg_probe(tp)) { 1421 if (netif_msg_probe(tp))
1422 printk(KERN_ERR PFX "%s: enable failure\n", 1422 dev_err(&pdev->dev, "enable failure\n");
1423 pci_name(pdev));
1424 }
1425 goto err_out_free_dev; 1423 goto err_out_free_dev;
1426 } 1424 }
1427 1425
@@ -1437,37 +1435,32 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1437 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command); 1435 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1438 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK; 1436 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1439 } else { 1437 } else {
1440 if (netif_msg_probe(tp)) { 1438 if (netif_msg_probe(tp))
1441 printk(KERN_ERR PFX 1439 dev_err(&pdev->dev,
1442 "PowerManagement capability not found.\n"); 1440 "PowerManagement capability not found.\n");
1443 }
1444 } 1441 }
1445 1442
1446 /* make sure PCI base addr 1 is MMIO */ 1443 /* make sure PCI base addr 1 is MMIO */
1447 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { 1444 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
1448 if (netif_msg_probe(tp)) { 1445 if (netif_msg_probe(tp))
1449 printk(KERN_ERR PFX 1446 dev_err(&pdev->dev,
1450 "region #1 not an MMIO resource, aborting\n"); 1447 "region #1 not an MMIO resource, aborting\n");
1451 }
1452 rc = -ENODEV; 1448 rc = -ENODEV;
1453 goto err_out_mwi; 1449 goto err_out_mwi;
1454 } 1450 }
1455 /* check for weird/broken PCI region reporting */ 1451 /* check for weird/broken PCI region reporting */
1456 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) { 1452 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
1457 if (netif_msg_probe(tp)) { 1453 if (netif_msg_probe(tp))
1458 printk(KERN_ERR PFX 1454 dev_err(&pdev->dev,
1459 "Invalid PCI region size(s), aborting\n"); 1455 "Invalid PCI region size(s), aborting\n");
1460 }
1461 rc = -ENODEV; 1456 rc = -ENODEV;
1462 goto err_out_mwi; 1457 goto err_out_mwi;
1463 } 1458 }
1464 1459
1465 rc = pci_request_regions(pdev, MODULENAME); 1460 rc = pci_request_regions(pdev, MODULENAME);
1466 if (rc < 0) { 1461 if (rc < 0) {
1467 if (netif_msg_probe(tp)) { 1462 if (netif_msg_probe(tp))
1468 printk(KERN_ERR PFX "%s: could not request regions.\n", 1463 dev_err(&pdev->dev, "could not request regions.\n");
1469 pci_name(pdev));
1470 }
1471 goto err_out_mwi; 1464 goto err_out_mwi;
1472 } 1465 }
1473 1466
@@ -1480,10 +1473,9 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1480 } else { 1473 } else {
1481 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1474 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1482 if (rc < 0) { 1475 if (rc < 0) {
1483 if (netif_msg_probe(tp)) { 1476 if (netif_msg_probe(tp))
1484 printk(KERN_ERR PFX 1477 dev_err(&pdev->dev,
1485 "DMA configuration failed.\n"); 1478 "DMA configuration failed.\n");
1486 }
1487 goto err_out_free_res; 1479 goto err_out_free_res;
1488 } 1480 }
1489 } 1481 }
@@ -1494,7 +1486,7 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1494 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE); 1486 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1495 if (ioaddr == NULL) { 1487 if (ioaddr == NULL) {
1496 if (netif_msg_probe(tp)) 1488 if (netif_msg_probe(tp))
1497 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n"); 1489 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1498 rc = -EIO; 1490 rc = -EIO;
1499 goto err_out_free_res; 1491 goto err_out_free_res;
1500 } 1492 }
@@ -1526,9 +1518,9 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1526 if (i < 0) { 1518 if (i < 0) {
1527 /* Unknown chip: assume array element #0, original RTL-8169 */ 1519 /* Unknown chip: assume array element #0, original RTL-8169 */
1528 if (netif_msg_probe(tp)) { 1520 if (netif_msg_probe(tp)) {
1529 printk(KERN_DEBUG PFX "PCI device %s: " 1521 dev_printk(KERN_DEBUG, &pdev->dev,
1530 "unknown chip version, assuming %s\n", 1522 "unknown chip version, assuming %s\n",
1531 pci_name(pdev), rtl_chip_info[0].name); 1523 rtl_chip_info[0].name);
1532 } 1524 }
1533 i++; 1525 i++;
1534 } 1526 }
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index c6b77acb35ef..132ed32bce1a 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -76,7 +76,7 @@
76#include "s2io.h" 76#include "s2io.h"
77#include "s2io-regs.h" 77#include "s2io-regs.h"
78 78
79#define DRV_VERSION "2.0.14.2" 79#define DRV_VERSION "2.0.15.2"
80 80
81/* S2io Driver name & version. */ 81/* S2io Driver name & version. */
82static char s2io_driver_name[] = "Neterion"; 82static char s2io_driver_name[] = "Neterion";
@@ -370,38 +370,50 @@ static const u64 fix_mac[] = {
370 END_SIGN 370 END_SIGN
371}; 371};
372 372
373MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
374MODULE_LICENSE("GPL");
375MODULE_VERSION(DRV_VERSION);
376
377
373/* Module Loadable parameters. */ 378/* Module Loadable parameters. */
374static unsigned int tx_fifo_num = 1; 379S2IO_PARM_INT(tx_fifo_num, 1);
375static unsigned int tx_fifo_len[MAX_TX_FIFOS] = 380S2IO_PARM_INT(rx_ring_num, 1);
376 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN}; 381
377static unsigned int rx_ring_num = 1; 382
378static unsigned int rx_ring_sz[MAX_RX_RINGS] = 383S2IO_PARM_INT(rx_ring_mode, 1);
379 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT}; 384S2IO_PARM_INT(use_continuous_tx_intrs, 1);
380static unsigned int rts_frm_len[MAX_RX_RINGS] = 385S2IO_PARM_INT(rmac_pause_time, 0x100);
381 {[0 ...(MAX_RX_RINGS - 1)] = 0 }; 386S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
382static unsigned int rx_ring_mode = 1; 387S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
383static unsigned int use_continuous_tx_intrs = 1; 388S2IO_PARM_INT(shared_splits, 0);
384static unsigned int rmac_pause_time = 0x100; 389S2IO_PARM_INT(tmac_util_period, 5);
385static unsigned int mc_pause_threshold_q0q3 = 187; 390S2IO_PARM_INT(rmac_util_period, 5);
386static unsigned int mc_pause_threshold_q4q7 = 187; 391S2IO_PARM_INT(bimodal, 0);
387static unsigned int shared_splits; 392S2IO_PARM_INT(l3l4hdr_size, 128);
388static unsigned int tmac_util_period = 5;
389static unsigned int rmac_util_period = 5;
390static unsigned int bimodal = 0;
391static unsigned int l3l4hdr_size = 128;
392#ifndef CONFIG_S2IO_NAPI
393static unsigned int indicate_max_pkts;
394#endif
395/* Frequency of Rx desc syncs expressed as power of 2 */ 393/* Frequency of Rx desc syncs expressed as power of 2 */
396static unsigned int rxsync_frequency = 3; 394S2IO_PARM_INT(rxsync_frequency, 3);
397/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */ 395/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
398static unsigned int intr_type = 0; 396S2IO_PARM_INT(intr_type, 0);
399/* Large receive offload feature */ 397/* Large receive offload feature */
400static unsigned int lro = 0; 398S2IO_PARM_INT(lro, 0);
401/* Max pkts to be aggregated by LRO at one time. If not specified, 399/* Max pkts to be aggregated by LRO at one time. If not specified,
402 * aggregation happens until we hit max IP pkt size(64K) 400 * aggregation happens until we hit max IP pkt size(64K)
403 */ 401 */
404static unsigned int lro_max_pkts = 0xFFFF; 402S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
403#ifndef CONFIG_S2IO_NAPI
404S2IO_PARM_INT(indicate_max_pkts, 0);
405#endif
406
407static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
408 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
409static unsigned int rx_ring_sz[MAX_RX_RINGS] =
410 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
411static unsigned int rts_frm_len[MAX_RX_RINGS] =
412 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
413
414module_param_array(tx_fifo_len, uint, NULL, 0);
415module_param_array(rx_ring_sz, uint, NULL, 0);
416module_param_array(rts_frm_len, uint, NULL, 0);
405 417
406/* 418/*
407 * S2IO device table. 419 * S2IO device table.
@@ -464,10 +476,9 @@ static int init_shared_mem(struct s2io_nic *nic)
464 size += config->tx_cfg[i].fifo_len; 476 size += config->tx_cfg[i].fifo_len;
465 } 477 }
466 if (size > MAX_AVAILABLE_TXDS) { 478 if (size > MAX_AVAILABLE_TXDS) {
467 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ", 479 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
468 __FUNCTION__);
469 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size); 480 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
470 return FAILURE; 481 return -EINVAL;
471 } 482 }
472 483
473 lst_size = (sizeof(TxD_t) * config->max_txds); 484 lst_size = (sizeof(TxD_t) * config->max_txds);
@@ -547,6 +558,7 @@ static int init_shared_mem(struct s2io_nic *nic)
547 nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL); 558 nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
548 if (!nic->ufo_in_band_v) 559 if (!nic->ufo_in_band_v)
549 return -ENOMEM; 560 return -ENOMEM;
561 memset(nic->ufo_in_band_v, 0, size);
550 562
551 /* Allocation and initialization of RXDs in Rings */ 563 /* Allocation and initialization of RXDs in Rings */
552 size = 0; 564 size = 0;
@@ -1213,7 +1225,7 @@ static int init_nic(struct s2io_nic *nic)
1213 break; 1225 break;
1214 } 1226 }
1215 1227
1216 /* Enable Tx FIFO partition 0. */ 1228 /* Enable all configured Tx FIFO partitions */
1217 val64 = readq(&bar0->tx_fifo_partition_0); 1229 val64 = readq(&bar0->tx_fifo_partition_0);
1218 val64 |= (TX_FIFO_PARTITION_EN); 1230 val64 |= (TX_FIFO_PARTITION_EN);
1219 writeq(val64, &bar0->tx_fifo_partition_0); 1231 writeq(val64, &bar0->tx_fifo_partition_0);
@@ -1650,7 +1662,7 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1650 writeq(temp64, &bar0->general_int_mask); 1662 writeq(temp64, &bar0->general_int_mask);
1651 /* 1663 /*
1652 * If Hercules adapter enable GPIO otherwise 1664 * If Hercules adapter enable GPIO otherwise
1653 * disabled all PCIX, Flash, MDIO, IIC and GPIO 1665 * disable all PCIX, Flash, MDIO, IIC and GPIO
1654 * interrupts for now. 1666 * interrupts for now.
1655 * TODO 1667 * TODO
1656 */ 1668 */
@@ -1976,7 +1988,6 @@ static int start_nic(struct s2io_nic *nic)
1976 XENA_dev_config_t __iomem *bar0 = nic->bar0; 1988 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1977 struct net_device *dev = nic->dev; 1989 struct net_device *dev = nic->dev;
1978 register u64 val64 = 0; 1990 register u64 val64 = 0;
1979 u16 interruptible;
1980 u16 subid, i; 1991 u16 subid, i;
1981 mac_info_t *mac_control; 1992 mac_info_t *mac_control;
1982 struct config_param *config; 1993 struct config_param *config;
@@ -2047,16 +2058,6 @@ static int start_nic(struct s2io_nic *nic)
2047 return FAILURE; 2058 return FAILURE;
2048 } 2059 }
2049 2060
2050 /* Enable select interrupts */
2051 if (nic->intr_type != INTA)
2052 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2053 else {
2054 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2055 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2056 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2057 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
2058 }
2059
2060 /* 2061 /*
2061 * With some switches, link might be already up at this point. 2062 * With some switches, link might be already up at this point.
2062 * Because of this weird behavior, when we enable laser, 2063 * Because of this weird behavior, when we enable laser,
@@ -2130,7 +2131,7 @@ static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, in
2130 frag->size, PCI_DMA_TODEVICE); 2131 frag->size, PCI_DMA_TODEVICE);
2131 } 2132 }
2132 } 2133 }
2133 txdlp->Host_Control = 0; 2134 memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2134 return(skb); 2135 return(skb);
2135} 2136}
2136 2137
@@ -2382,9 +2383,14 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2382 skb->data = (void *) (unsigned long)tmp; 2383 skb->data = (void *) (unsigned long)tmp;
2383 skb->tail = (void *) (unsigned long)tmp; 2384 skb->tail = (void *) (unsigned long)tmp;
2384 2385
2385 ((RxD3_t*)rxdp)->Buffer0_ptr = 2386 if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2386 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN, 2387 ((RxD3_t*)rxdp)->Buffer0_ptr =
2388 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2387 PCI_DMA_FROMDEVICE); 2389 PCI_DMA_FROMDEVICE);
2390 else
2391 pci_dma_sync_single_for_device(nic->pdev,
2392 (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2393 BUF0_LEN, PCI_DMA_FROMDEVICE);
2388 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); 2394 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2389 if (nic->rxd_mode == RXD_MODE_3B) { 2395 if (nic->rxd_mode == RXD_MODE_3B) {
2390 /* Two buffer mode */ 2396 /* Two buffer mode */
@@ -2397,10 +2403,13 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2397 (nic->pdev, skb->data, dev->mtu + 4, 2403 (nic->pdev, skb->data, dev->mtu + 4,
2398 PCI_DMA_FROMDEVICE); 2404 PCI_DMA_FROMDEVICE);
2399 2405
2400 /* Buffer-1 will be dummy buffer not used */ 2406 /* Buffer-1 will be dummy buffer. Not used */
2401 ((RxD3_t*)rxdp)->Buffer1_ptr = 2407 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2402 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN, 2408 ((RxD3_t*)rxdp)->Buffer1_ptr =
2403 PCI_DMA_FROMDEVICE); 2409 pci_map_single(nic->pdev,
2410 ba->ba_1, BUF1_LEN,
2411 PCI_DMA_FROMDEVICE);
2412 }
2404 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); 2413 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2405 rxdp->Control_2 |= SET_BUFFER2_SIZE_3 2414 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2406 (dev->mtu + 4); 2415 (dev->mtu + 4);
@@ -2625,23 +2634,23 @@ no_rx:
2625} 2634}
2626#endif 2635#endif
2627 2636
2637#ifdef CONFIG_NET_POLL_CONTROLLER
2628/** 2638/**
2629 * s2io_netpoll - Rx interrupt service handler for netpoll support 2639 * s2io_netpoll - netpoll event handler entry point
2630 * @dev : pointer to the device structure. 2640 * @dev : pointer to the device structure.
2631 * Description: 2641 * Description:
2632 * Polling 'interrupt' - used by things like netconsole to send skbs 2642 * This function will be called by upper layer to check for events on the
2633 * without having to re-enable interrupts. It's not called while 2643 * interface in situations where interrupts are disabled. It is used for
2634 * the interrupt routine is executing. 2644 * specific in-kernel networking tasks, such as remote consoles and kernel
2645 * debugging over the network (example netdump in RedHat).
2635 */ 2646 */
2636
2637#ifdef CONFIG_NET_POLL_CONTROLLER
2638static void s2io_netpoll(struct net_device *dev) 2647static void s2io_netpoll(struct net_device *dev)
2639{ 2648{
2640 nic_t *nic = dev->priv; 2649 nic_t *nic = dev->priv;
2641 mac_info_t *mac_control; 2650 mac_info_t *mac_control;
2642 struct config_param *config; 2651 struct config_param *config;
2643 XENA_dev_config_t __iomem *bar0 = nic->bar0; 2652 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2644 u64 val64; 2653 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2645 int i; 2654 int i;
2646 2655
2647 disable_irq(dev->irq); 2656 disable_irq(dev->irq);
@@ -2650,9 +2659,17 @@ static void s2io_netpoll(struct net_device *dev)
2650 mac_control = &nic->mac_control; 2659 mac_control = &nic->mac_control;
2651 config = &nic->config; 2660 config = &nic->config;
2652 2661
2653 val64 = readq(&bar0->rx_traffic_int);
2654 writeq(val64, &bar0->rx_traffic_int); 2662 writeq(val64, &bar0->rx_traffic_int);
2663 writeq(val64, &bar0->tx_traffic_int);
2655 2664
2665 /* we need to free up the transmitted skbufs or else netpoll will
2666 * run out of skbs and will fail and eventually netpoll application such
2667 * as netdump will fail.
2668 */
2669 for (i = 0; i < config->tx_fifo_num; i++)
2670 tx_intr_handler(&mac_control->fifos[i]);
2671
2672 /* check for received packet and indicate up to network */
2656 for (i = 0; i < config->rx_ring_num; i++) 2673 for (i = 0; i < config->rx_ring_num; i++)
2657 rx_intr_handler(&mac_control->rings[i]); 2674 rx_intr_handler(&mac_control->rings[i]);
2658 2675
@@ -2719,7 +2736,7 @@ static void rx_intr_handler(ring_info_t *ring_data)
2719 /* If your are next to put index then it's FIFO full condition */ 2736 /* If your are next to put index then it's FIFO full condition */
2720 if ((get_block == put_block) && 2737 if ((get_block == put_block) &&
2721 (get_info.offset + 1) == put_info.offset) { 2738 (get_info.offset + 1) == put_info.offset) {
2722 DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name); 2739 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2723 break; 2740 break;
2724 } 2741 }
2725 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control); 2742 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
@@ -2739,18 +2756,15 @@ static void rx_intr_handler(ring_info_t *ring_data)
2739 HEADER_SNAP_SIZE, 2756 HEADER_SNAP_SIZE,
2740 PCI_DMA_FROMDEVICE); 2757 PCI_DMA_FROMDEVICE);
2741 } else if (nic->rxd_mode == RXD_MODE_3B) { 2758 } else if (nic->rxd_mode == RXD_MODE_3B) {
2742 pci_unmap_single(nic->pdev, (dma_addr_t) 2759 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2743 ((RxD3_t*)rxdp)->Buffer0_ptr, 2760 ((RxD3_t*)rxdp)->Buffer0_ptr,
2744 BUF0_LEN, PCI_DMA_FROMDEVICE); 2761 BUF0_LEN, PCI_DMA_FROMDEVICE);
2745 pci_unmap_single(nic->pdev, (dma_addr_t) 2762 pci_unmap_single(nic->pdev, (dma_addr_t)
2746 ((RxD3_t*)rxdp)->Buffer1_ptr,
2747 BUF1_LEN, PCI_DMA_FROMDEVICE);
2748 pci_unmap_single(nic->pdev, (dma_addr_t)
2749 ((RxD3_t*)rxdp)->Buffer2_ptr, 2763 ((RxD3_t*)rxdp)->Buffer2_ptr,
2750 dev->mtu + 4, 2764 dev->mtu + 4,
2751 PCI_DMA_FROMDEVICE); 2765 PCI_DMA_FROMDEVICE);
2752 } else { 2766 } else {
2753 pci_unmap_single(nic->pdev, (dma_addr_t) 2767 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2754 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN, 2768 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2755 PCI_DMA_FROMDEVICE); 2769 PCI_DMA_FROMDEVICE);
2756 pci_unmap_single(nic->pdev, (dma_addr_t) 2770 pci_unmap_single(nic->pdev, (dma_addr_t)
@@ -3338,7 +3352,7 @@ static void s2io_reset(nic_t * sp)
3338 3352
3339 /* Clear certain PCI/PCI-X fields after reset */ 3353 /* Clear certain PCI/PCI-X fields after reset */
3340 if (sp->device_type == XFRAME_II_DEVICE) { 3354 if (sp->device_type == XFRAME_II_DEVICE) {
3341 /* Clear parity err detect bit */ 3355 /* Clear "detected parity error" bit */
3342 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000); 3356 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3343 3357
3344 /* Clearing PCIX Ecc status register */ 3358 /* Clearing PCIX Ecc status register */
@@ -3539,7 +3553,7 @@ static void restore_xmsi_data(nic_t *nic)
3539 u64 val64; 3553 u64 val64;
3540 int i; 3554 int i;
3541 3555
3542 for (i=0; i< nic->avail_msix_vectors; i++) { 3556 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3543 writeq(nic->msix_info[i].addr, &bar0->xmsi_address); 3557 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3544 writeq(nic->msix_info[i].data, &bar0->xmsi_data); 3558 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3545 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6)); 3559 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
@@ -3558,7 +3572,7 @@ static void store_xmsi_data(nic_t *nic)
3558 int i; 3572 int i;
3559 3573
3560 /* Store and display */ 3574 /* Store and display */
3561 for (i=0; i< nic->avail_msix_vectors; i++) { 3575 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3562 val64 = (BIT(15) | vBIT(i, 26, 6)); 3576 val64 = (BIT(15) | vBIT(i, 26, 6));
3563 writeq(val64, &bar0->xmsi_access); 3577 writeq(val64, &bar0->xmsi_access);
3564 if (wait_for_msix_trans(nic, i)) { 3578 if (wait_for_msix_trans(nic, i)) {
@@ -3749,101 +3763,19 @@ static int s2io_open(struct net_device *dev)
3749 if (err) { 3763 if (err) {
3750 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", 3764 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3751 dev->name); 3765 dev->name);
3752 if (err == -ENODEV) 3766 goto hw_init_failed;
3753 goto hw_init_failed;
3754 else
3755 goto hw_enable_failed;
3756 }
3757
3758 /* Store the values of the MSIX table in the nic_t structure */
3759 store_xmsi_data(sp);
3760
3761 /* After proper initialization of H/W, register ISR */
3762 if (sp->intr_type == MSI) {
3763 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
3764 IRQF_SHARED, sp->name, dev);
3765 if (err) {
3766 DBG_PRINT(ERR_DBG, "%s: MSI registration \
3767failed\n", dev->name);
3768 goto isr_registration_failed;
3769 }
3770 }
3771 if (sp->intr_type == MSI_X) {
3772 int i;
3773
3774 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3775 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3776 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
3777 dev->name, i);
3778 err = request_irq(sp->entries[i].vector,
3779 s2io_msix_fifo_handle, 0, sp->desc1,
3780 sp->s2io_entries[i].arg);
3781 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1,
3782 (unsigned long long)sp->msix_info[i].addr);
3783 } else {
3784 sprintf(sp->desc2, "%s:MSI-X-%d-RX",
3785 dev->name, i);
3786 err = request_irq(sp->entries[i].vector,
3787 s2io_msix_ring_handle, 0, sp->desc2,
3788 sp->s2io_entries[i].arg);
3789 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2,
3790 (unsigned long long)sp->msix_info[i].addr);
3791 }
3792 if (err) {
3793 DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
3794failed\n", dev->name, i);
3795 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
3796 goto isr_registration_failed;
3797 }
3798 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
3799 }
3800 }
3801 if (sp->intr_type == INTA) {
3802 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
3803 sp->name, dev);
3804 if (err) {
3805 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
3806 dev->name);
3807 goto isr_registration_failed;
3808 }
3809 } 3767 }
3810 3768
3811 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) { 3769 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3812 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n"); 3770 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3771 s2io_card_down(sp);
3813 err = -ENODEV; 3772 err = -ENODEV;
3814 goto setting_mac_address_failed; 3773 goto hw_init_failed;
3815 } 3774 }
3816 3775
3817 netif_start_queue(dev); 3776 netif_start_queue(dev);
3818 return 0; 3777 return 0;
3819 3778
3820setting_mac_address_failed:
3821 if (sp->intr_type != MSI_X)
3822 free_irq(sp->pdev->irq, dev);
3823isr_registration_failed:
3824 del_timer_sync(&sp->alarm_timer);
3825 if (sp->intr_type == MSI_X) {
3826 int i;
3827 u16 msi_control; /* Temp variable */
3828
3829 for (i=1; (sp->s2io_entries[i].in_use ==
3830 MSIX_REGISTERED_SUCCESS); i++) {
3831 int vector = sp->entries[i].vector;
3832 void *arg = sp->s2io_entries[i].arg;
3833
3834 free_irq(vector, arg);
3835 }
3836 pci_disable_msix(sp->pdev);
3837
3838 /* Temp */
3839 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3840 msi_control &= 0xFFFE; /* Disable MSI */
3841 pci_write_config_word(sp->pdev, 0x42, msi_control);
3842 }
3843 else if (sp->intr_type == MSI)
3844 pci_disable_msi(sp->pdev);
3845hw_enable_failed:
3846 s2io_reset(sp);
3847hw_init_failed: 3779hw_init_failed:
3848 if (sp->intr_type == MSI_X) { 3780 if (sp->intr_type == MSI_X) {
3849 if (sp->entries) 3781 if (sp->entries)
@@ -3874,7 +3806,7 @@ static int s2io_close(struct net_device *dev)
3874 flush_scheduled_work(); 3806 flush_scheduled_work();
3875 netif_stop_queue(dev); 3807 netif_stop_queue(dev);
3876 /* Reset card, kill tasklet and free Tx and Rx buffers. */ 3808 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3877 s2io_card_down(sp, 1); 3809 s2io_card_down(sp);
3878 3810
3879 sp->device_close_flag = TRUE; /* Device is shut down. */ 3811 sp->device_close_flag = TRUE; /* Device is shut down. */
3880 return 0; 3812 return 0;
@@ -3901,13 +3833,11 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3901 TxD_t *txdp; 3833 TxD_t *txdp;
3902 TxFIFO_element_t __iomem *tx_fifo; 3834 TxFIFO_element_t __iomem *tx_fifo;
3903 unsigned long flags; 3835 unsigned long flags;
3904#ifdef NETIF_F_TSO
3905 int mss;
3906#endif
3907 u16 vlan_tag = 0; 3836 u16 vlan_tag = 0;
3908 int vlan_priority = 0; 3837 int vlan_priority = 0;
3909 mac_info_t *mac_control; 3838 mac_info_t *mac_control;
3910 struct config_param *config; 3839 struct config_param *config;
3840 int offload_type;
3911 3841
3912 mac_control = &sp->mac_control; 3842 mac_control = &sp->mac_control;
3913 config = &sp->config; 3843 config = &sp->config;
@@ -3955,13 +3885,11 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3955 return 0; 3885 return 0;
3956 } 3886 }
3957 3887
3958 txdp->Control_1 = 0; 3888 offload_type = s2io_offload_type(skb);
3959 txdp->Control_2 = 0;
3960#ifdef NETIF_F_TSO 3889#ifdef NETIF_F_TSO
3961 mss = skb_shinfo(skb)->gso_size; 3890 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3962 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3963 txdp->Control_1 |= TXD_TCP_LSO_EN; 3891 txdp->Control_1 |= TXD_TCP_LSO_EN;
3964 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss); 3892 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3965 } 3893 }
3966#endif 3894#endif
3967 if (skb->ip_summed == CHECKSUM_HW) { 3895 if (skb->ip_summed == CHECKSUM_HW) {
@@ -3979,10 +3907,10 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3979 } 3907 }
3980 3908
3981 frg_len = skb->len - skb->data_len; 3909 frg_len = skb->len - skb->data_len;
3982 if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP) { 3910 if (offload_type == SKB_GSO_UDP) {
3983 int ufo_size; 3911 int ufo_size;
3984 3912
3985 ufo_size = skb_shinfo(skb)->gso_size; 3913 ufo_size = s2io_udp_mss(skb);
3986 ufo_size &= ~7; 3914 ufo_size &= ~7;
3987 txdp->Control_1 |= TXD_UFO_EN; 3915 txdp->Control_1 |= TXD_UFO_EN;
3988 txdp->Control_1 |= TXD_UFO_MSS(ufo_size); 3916 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
@@ -3999,16 +3927,13 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3999 sp->ufo_in_band_v, 3927 sp->ufo_in_band_v,
4000 sizeof(u64), PCI_DMA_TODEVICE); 3928 sizeof(u64), PCI_DMA_TODEVICE);
4001 txdp++; 3929 txdp++;
4002 txdp->Control_1 = 0;
4003 txdp->Control_2 = 0;
4004 } 3930 }
4005 3931
4006 txdp->Buffer_Pointer = pci_map_single 3932 txdp->Buffer_Pointer = pci_map_single
4007 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE); 3933 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4008 txdp->Host_Control = (unsigned long) skb; 3934 txdp->Host_Control = (unsigned long) skb;
4009 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len); 3935 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4010 3936 if (offload_type == SKB_GSO_UDP)
4011 if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP)
4012 txdp->Control_1 |= TXD_UFO_EN; 3937 txdp->Control_1 |= TXD_UFO_EN;
4013 3938
4014 frg_cnt = skb_shinfo(skb)->nr_frags; 3939 frg_cnt = skb_shinfo(skb)->nr_frags;
@@ -4023,12 +3948,12 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4023 (sp->pdev, frag->page, frag->page_offset, 3948 (sp->pdev, frag->page, frag->page_offset,
4024 frag->size, PCI_DMA_TODEVICE); 3949 frag->size, PCI_DMA_TODEVICE);
4025 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size); 3950 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4026 if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP) 3951 if (offload_type == SKB_GSO_UDP)
4027 txdp->Control_1 |= TXD_UFO_EN; 3952 txdp->Control_1 |= TXD_UFO_EN;
4028 } 3953 }
4029 txdp->Control_1 |= TXD_GATHER_CODE_LAST; 3954 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4030 3955
4031 if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP) 3956 if (offload_type == SKB_GSO_UDP)
4032 frg_cnt++; /* as Txd0 was used for inband header */ 3957 frg_cnt++; /* as Txd0 was used for inband header */
4033 3958
4034 tx_fifo = mac_control->tx_FIFO_start[queue]; 3959 tx_fifo = mac_control->tx_FIFO_start[queue];
@@ -4037,13 +3962,9 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4037 3962
4038 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | 3963 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4039 TX_FIFO_LAST_LIST); 3964 TX_FIFO_LAST_LIST);
4040 3965 if (offload_type)
4041#ifdef NETIF_F_TSO
4042 if (mss)
4043 val64 |= TX_FIFO_SPECIAL_FUNC;
4044#endif
4045 if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP)
4046 val64 |= TX_FIFO_SPECIAL_FUNC; 3966 val64 |= TX_FIFO_SPECIAL_FUNC;
3967
4047 writeq(val64, &tx_fifo->List_Control); 3968 writeq(val64, &tx_fifo->List_Control);
4048 3969
4049 mmiowb(); 3970 mmiowb();
@@ -4077,13 +3998,41 @@ s2io_alarm_handle(unsigned long data)
4077 mod_timer(&sp->alarm_timer, jiffies + HZ / 2); 3998 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4078} 3999}
4079 4000
4001static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
4002{
4003 int rxb_size, level;
4004
4005 if (!sp->lro) {
4006 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4007 level = rx_buffer_level(sp, rxb_size, rng_n);
4008
4009 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4010 int ret;
4011 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4012 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4013 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4014 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4015 __FUNCTION__);
4016 clear_bit(0, (&sp->tasklet_status));
4017 return -1;
4018 }
4019 clear_bit(0, (&sp->tasklet_status));
4020 } else if (level == LOW)
4021 tasklet_schedule(&sp->task);
4022
4023 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4024 DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4025 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4026 }
4027 return 0;
4028}
4029
4080static irqreturn_t 4030static irqreturn_t
4081s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs) 4031s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
4082{ 4032{
4083 struct net_device *dev = (struct net_device *) dev_id; 4033 struct net_device *dev = (struct net_device *) dev_id;
4084 nic_t *sp = dev->priv; 4034 nic_t *sp = dev->priv;
4085 int i; 4035 int i;
4086 int ret;
4087 mac_info_t *mac_control; 4036 mac_info_t *mac_control;
4088 struct config_param *config; 4037 struct config_param *config;
4089 4038
@@ -4105,35 +4054,8 @@ s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
4105 * reallocate the buffers from the interrupt handler itself, 4054 * reallocate the buffers from the interrupt handler itself,
4106 * else schedule a tasklet to reallocate the buffers. 4055 * else schedule a tasklet to reallocate the buffers.
4107 */ 4056 */
4108 for (i = 0; i < config->rx_ring_num; i++) { 4057 for (i = 0; i < config->rx_ring_num; i++)
4109 if (!sp->lro) { 4058 s2io_chk_rx_buffers(sp, i);
4110 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
4111 int level = rx_buffer_level(sp, rxb_size, i);
4112
4113 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4114 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
4115 dev->name);
4116 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4117 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
4118 DBG_PRINT(ERR_DBG, "%s:Out of memory",
4119 dev->name);
4120 DBG_PRINT(ERR_DBG, " in ISR!!\n");
4121 clear_bit(0, (&sp->tasklet_status));
4122 atomic_dec(&sp->isr_cnt);
4123 return IRQ_HANDLED;
4124 }
4125 clear_bit(0, (&sp->tasklet_status));
4126 } else if (level == LOW) {
4127 tasklet_schedule(&sp->task);
4128 }
4129 }
4130 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
4131 DBG_PRINT(ERR_DBG, "%s:Out of memory",
4132 dev->name);
4133 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4134 break;
4135 }
4136 }
4137 4059
4138 atomic_dec(&sp->isr_cnt); 4060 atomic_dec(&sp->isr_cnt);
4139 return IRQ_HANDLED; 4061 return IRQ_HANDLED;
@@ -4144,39 +4066,13 @@ s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
4144{ 4066{
4145 ring_info_t *ring = (ring_info_t *)dev_id; 4067 ring_info_t *ring = (ring_info_t *)dev_id;
4146 nic_t *sp = ring->nic; 4068 nic_t *sp = ring->nic;
4147 struct net_device *dev = (struct net_device *) dev_id;
4148 int rxb_size, level, rng_n;
4149 4069
4150 atomic_inc(&sp->isr_cnt); 4070 atomic_inc(&sp->isr_cnt);
4151 rx_intr_handler(ring);
4152 4071
4153 rng_n = ring->ring_no; 4072 rx_intr_handler(ring);
4154 if (!sp->lro) { 4073 s2io_chk_rx_buffers(sp, ring->ring_no);
4155 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4156 level = rx_buffer_level(sp, rxb_size, rng_n);
4157
4158 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4159 int ret;
4160 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4161 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4162 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4163 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4164 __FUNCTION__);
4165 clear_bit(0, (&sp->tasklet_status));
4166 return IRQ_HANDLED;
4167 }
4168 clear_bit(0, (&sp->tasklet_status));
4169 } else if (level == LOW) {
4170 tasklet_schedule(&sp->task);
4171 }
4172 }
4173 else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4174 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
4175 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4176 }
4177 4074
4178 atomic_dec(&sp->isr_cnt); 4075 atomic_dec(&sp->isr_cnt);
4179
4180 return IRQ_HANDLED; 4076 return IRQ_HANDLED;
4181} 4077}
4182 4078
@@ -4341,37 +4237,8 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
4341 * else schedule a tasklet to reallocate the buffers. 4237 * else schedule a tasklet to reallocate the buffers.
4342 */ 4238 */
4343#ifndef CONFIG_S2IO_NAPI 4239#ifndef CONFIG_S2IO_NAPI
4344 for (i = 0; i < config->rx_ring_num; i++) { 4240 for (i = 0; i < config->rx_ring_num; i++)
4345 if (!sp->lro) { 4241 s2io_chk_rx_buffers(sp, i);
4346 int ret;
4347 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
4348 int level = rx_buffer_level(sp, rxb_size, i);
4349
4350 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4351 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
4352 dev->name);
4353 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4354 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
4355 DBG_PRINT(ERR_DBG, "%s:Out of memory",
4356 dev->name);
4357 DBG_PRINT(ERR_DBG, " in ISR!!\n");
4358 clear_bit(0, (&sp->tasklet_status));
4359 atomic_dec(&sp->isr_cnt);
4360 writeq(org_mask, &bar0->general_int_mask);
4361 return IRQ_HANDLED;
4362 }
4363 clear_bit(0, (&sp->tasklet_status));
4364 } else if (level == LOW) {
4365 tasklet_schedule(&sp->task);
4366 }
4367 }
4368 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
4369 DBG_PRINT(ERR_DBG, "%s:Out of memory",
4370 dev->name);
4371 DBG_PRINT(ERR_DBG, " in Rx intr!!\n");
4372 break;
4373 }
4374 }
4375#endif 4242#endif
4376 writeq(org_mask, &bar0->general_int_mask); 4243 writeq(org_mask, &bar0->general_int_mask);
4377 atomic_dec(&sp->isr_cnt); 4244 atomic_dec(&sp->isr_cnt);
@@ -4401,6 +4268,8 @@ static void s2io_updt_stats(nic_t *sp)
4401 if (cnt == 5) 4268 if (cnt == 5)
4402 break; /* Updt failed */ 4269 break; /* Updt failed */
4403 } while(1); 4270 } while(1);
4271 } else {
4272 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t));
4404 } 4273 }
4405} 4274}
4406 4275
@@ -5035,7 +4904,8 @@ static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
5035} 4904}
5036static void s2io_vpd_read(nic_t *nic) 4905static void s2io_vpd_read(nic_t *nic)
5037{ 4906{
5038 u8 vpd_data[256],data; 4907 u8 *vpd_data;
4908 u8 data;
5039 int i=0, cnt, fail = 0; 4909 int i=0, cnt, fail = 0;
5040 int vpd_addr = 0x80; 4910 int vpd_addr = 0x80;
5041 4911
@@ -5048,6 +4918,10 @@ static void s2io_vpd_read(nic_t *nic)
5048 vpd_addr = 0x50; 4918 vpd_addr = 0x50;
5049 } 4919 }
5050 4920
4921 vpd_data = kmalloc(256, GFP_KERNEL);
4922 if (!vpd_data)
4923 return;
4924
5051 for (i = 0; i < 256; i +=4 ) { 4925 for (i = 0; i < 256; i +=4 ) {
5052 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i); 4926 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5053 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data); 4927 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
@@ -5070,6 +4944,7 @@ static void s2io_vpd_read(nic_t *nic)
5070 memset(nic->product_name, 0, vpd_data[1]); 4944 memset(nic->product_name, 0, vpd_data[1]);
5071 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]); 4945 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5072 } 4946 }
4947 kfree(vpd_data);
5073} 4948}
5074 4949
5075/** 4950/**
@@ -5388,7 +5263,7 @@ static int s2io_link_test(nic_t * sp, uint64_t * data)
5388 else 5263 else
5389 *data = 0; 5264 *data = 0;
5390 5265
5391 return 0; 5266 return *data;
5392} 5267}
5393 5268
5394/** 5269/**
@@ -5846,6 +5721,19 @@ static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5846 return 0; 5721 return 0;
5847} 5722}
5848 5723
5724static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5725{
5726 return (dev->features & NETIF_F_TSO) != 0;
5727}
5728static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5729{
5730 if (data)
5731 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5732 else
5733 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5734
5735 return 0;
5736}
5849 5737
5850static struct ethtool_ops netdev_ethtool_ops = { 5738static struct ethtool_ops netdev_ethtool_ops = {
5851 .get_settings = s2io_ethtool_gset, 5739 .get_settings = s2io_ethtool_gset,
@@ -5866,8 +5754,8 @@ static struct ethtool_ops netdev_ethtool_ops = {
5866 .get_sg = ethtool_op_get_sg, 5754 .get_sg = ethtool_op_get_sg,
5867 .set_sg = ethtool_op_set_sg, 5755 .set_sg = ethtool_op_set_sg,
5868#ifdef NETIF_F_TSO 5756#ifdef NETIF_F_TSO
5869 .get_tso = ethtool_op_get_tso, 5757 .get_tso = s2io_ethtool_op_get_tso,
5870 .set_tso = ethtool_op_set_tso, 5758 .set_tso = s2io_ethtool_op_set_tso,
5871#endif 5759#endif
5872 .get_ufo = ethtool_op_get_ufo, 5760 .get_ufo = ethtool_op_get_ufo,
5873 .set_ufo = ethtool_op_set_ufo, 5761 .set_ufo = ethtool_op_set_ufo,
@@ -5919,7 +5807,7 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5919 5807
5920 dev->mtu = new_mtu; 5808 dev->mtu = new_mtu;
5921 if (netif_running(dev)) { 5809 if (netif_running(dev)) {
5922 s2io_card_down(sp, 0); 5810 s2io_card_down(sp);
5923 netif_stop_queue(dev); 5811 netif_stop_queue(dev);
5924 if (s2io_card_up(sp)) { 5812 if (s2io_card_up(sp)) {
5925 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", 5813 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
@@ -6216,43 +6104,106 @@ static int rxd_owner_bit_reset(nic_t *sp)
6216 6104
6217} 6105}
6218 6106
6219static void s2io_card_down(nic_t * sp, int flag) 6107static int s2io_add_isr(nic_t * sp)
6220{ 6108{
6221 int cnt = 0; 6109 int ret = 0;
6222 XENA_dev_config_t __iomem *bar0 = sp->bar0;
6223 unsigned long flags;
6224 register u64 val64 = 0;
6225 struct net_device *dev = sp->dev; 6110 struct net_device *dev = sp->dev;
6111 int err = 0;
6226 6112
6227 del_timer_sync(&sp->alarm_timer); 6113 if (sp->intr_type == MSI)
6228 /* If s2io_set_link task is executing, wait till it completes. */ 6114 ret = s2io_enable_msi(sp);
6229 while (test_and_set_bit(0, &(sp->link_state))) { 6115 else if (sp->intr_type == MSI_X)
6230 msleep(50); 6116 ret = s2io_enable_msi_x(sp);
6117 if (ret) {
6118 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6119 sp->intr_type = INTA;
6231 } 6120 }
6232 atomic_set(&sp->card_state, CARD_DOWN);
6233 6121
6234 /* disable Tx and Rx traffic on the NIC */ 6122 /* Store the values of the MSIX table in the nic_t structure */
6235 stop_nic(sp); 6123 store_xmsi_data(sp);
6236 if (flag) {
6237 if (sp->intr_type == MSI_X) {
6238 int i;
6239 u16 msi_control;
6240 6124
6241 for (i=1; (sp->s2io_entries[i].in_use == 6125 /* After proper initialization of H/W, register ISR */
6242 MSIX_REGISTERED_SUCCESS); i++) { 6126 if (sp->intr_type == MSI) {
6243 int vector = sp->entries[i].vector; 6127 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6244 void *arg = sp->s2io_entries[i].arg; 6128 IRQF_SHARED, sp->name, dev);
6129 if (err) {
6130 pci_disable_msi(sp->pdev);
6131 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6132 dev->name);
6133 return -1;
6134 }
6135 }
6136 if (sp->intr_type == MSI_X) {
6137 int i;
6245 6138
6246 free_irq(vector, arg); 6139 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6140 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6141 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6142 dev->name, i);
6143 err = request_irq(sp->entries[i].vector,
6144 s2io_msix_fifo_handle, 0, sp->desc[i],
6145 sp->s2io_entries[i].arg);
6146 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6147 (unsigned long long)sp->msix_info[i].addr);
6148 } else {
6149 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6150 dev->name, i);
6151 err = request_irq(sp->entries[i].vector,
6152 s2io_msix_ring_handle, 0, sp->desc[i],
6153 sp->s2io_entries[i].arg);
6154 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6155 (unsigned long long)sp->msix_info[i].addr);
6247 } 6156 }
6248 pci_read_config_word(sp->pdev, 0x42, &msi_control); 6157 if (err) {
6249 msi_control &= 0xFFFE; /* Disable MSI */ 6158 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6250 pci_write_config_word(sp->pdev, 0x42, msi_control); 6159 "failed\n", dev->name, i);
6251 pci_disable_msix(sp->pdev); 6160 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6252 } else { 6161 return -1;
6253 free_irq(sp->pdev->irq, dev); 6162 }
6254 if (sp->intr_type == MSI) 6163 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6255 pci_disable_msi(sp->pdev); 6164 }
6165 }
6166 if (sp->intr_type == INTA) {
6167 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6168 sp->name, dev);
6169 if (err) {
6170 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6171 dev->name);
6172 return -1;
6173 }
6174 }
6175 return 0;
6176}
6177static void s2io_rem_isr(nic_t * sp)
6178{
6179 int cnt = 0;
6180 struct net_device *dev = sp->dev;
6181
6182 if (sp->intr_type == MSI_X) {
6183 int i;
6184 u16 msi_control;
6185
6186 for (i=1; (sp->s2io_entries[i].in_use ==
6187 MSIX_REGISTERED_SUCCESS); i++) {
6188 int vector = sp->entries[i].vector;
6189 void *arg = sp->s2io_entries[i].arg;
6190
6191 free_irq(vector, arg);
6192 }
6193 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6194 msi_control &= 0xFFFE; /* Disable MSI */
6195 pci_write_config_word(sp->pdev, 0x42, msi_control);
6196
6197 pci_disable_msix(sp->pdev);
6198 } else {
6199 free_irq(sp->pdev->irq, dev);
6200 if (sp->intr_type == MSI) {
6201 u16 val;
6202
6203 pci_disable_msi(sp->pdev);
6204 pci_read_config_word(sp->pdev, 0x4c, &val);
6205 val ^= 0x1;
6206 pci_write_config_word(sp->pdev, 0x4c, val);
6256 } 6207 }
6257 } 6208 }
6258 /* Waiting till all Interrupt handlers are complete */ 6209 /* Waiting till all Interrupt handlers are complete */
@@ -6263,6 +6214,26 @@ static void s2io_card_down(nic_t * sp, int flag)
6263 break; 6214 break;
6264 cnt++; 6215 cnt++;
6265 } while(cnt < 5); 6216 } while(cnt < 5);
6217}
6218
6219static void s2io_card_down(nic_t * sp)
6220{
6221 int cnt = 0;
6222 XENA_dev_config_t __iomem *bar0 = sp->bar0;
6223 unsigned long flags;
6224 register u64 val64 = 0;
6225
6226 del_timer_sync(&sp->alarm_timer);
6227 /* If s2io_set_link task is executing, wait till it completes. */
6228 while (test_and_set_bit(0, &(sp->link_state))) {
6229 msleep(50);
6230 }
6231 atomic_set(&sp->card_state, CARD_DOWN);
6232
6233 /* disable Tx and Rx traffic on the NIC */
6234 stop_nic(sp);
6235
6236 s2io_rem_isr(sp);
6266 6237
6267 /* Kill tasklet. */ 6238 /* Kill tasklet. */
6268 tasklet_kill(&sp->task); 6239 tasklet_kill(&sp->task);
@@ -6314,23 +6285,16 @@ static int s2io_card_up(nic_t * sp)
6314 mac_info_t *mac_control; 6285 mac_info_t *mac_control;
6315 struct config_param *config; 6286 struct config_param *config;
6316 struct net_device *dev = (struct net_device *) sp->dev; 6287 struct net_device *dev = (struct net_device *) sp->dev;
6288 u16 interruptible;
6317 6289
6318 /* Initialize the H/W I/O registers */ 6290 /* Initialize the H/W I/O registers */
6319 if (init_nic(sp) != 0) { 6291 if (init_nic(sp) != 0) {
6320 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", 6292 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6321 dev->name); 6293 dev->name);
6294 s2io_reset(sp);
6322 return -ENODEV; 6295 return -ENODEV;
6323 } 6296 }
6324 6297
6325 if (sp->intr_type == MSI)
6326 ret = s2io_enable_msi(sp);
6327 else if (sp->intr_type == MSI_X)
6328 ret = s2io_enable_msi_x(sp);
6329 if (ret) {
6330 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6331 sp->intr_type = INTA;
6332 }
6333
6334 /* 6298 /*
6335 * Initializing the Rx buffers. For now we are considering only 1 6299 * Initializing the Rx buffers. For now we are considering only 1
6336 * Rx ring and initializing buffers into 30 Rx blocks 6300 * Rx ring and initializing buffers into 30 Rx blocks
@@ -6354,28 +6318,46 @@ static int s2io_card_up(nic_t * sp)
6354 s2io_set_multicast(dev); 6318 s2io_set_multicast(dev);
6355 6319
6356 if (sp->lro) { 6320 if (sp->lro) {
6357 /* Initialize max aggregatable pkts based on MTU */ 6321 /* Initialize max aggregatable pkts per session based on MTU */
6358 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu; 6322 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6359 /* Check if we can use(if specified) user provided value */ 6323 /* Check if we can use(if specified) user provided value */
6360 if (lro_max_pkts < sp->lro_max_aggr_per_sess) 6324 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6361 sp->lro_max_aggr_per_sess = lro_max_pkts; 6325 sp->lro_max_aggr_per_sess = lro_max_pkts;
6362 } 6326 }
6363 6327
6364 /* Enable tasklet for the device */
6365 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6366
6367 /* Enable Rx Traffic and interrupts on the NIC */ 6328 /* Enable Rx Traffic and interrupts on the NIC */
6368 if (start_nic(sp)) { 6329 if (start_nic(sp)) {
6369 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name); 6330 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6370 tasklet_kill(&sp->task);
6371 s2io_reset(sp); 6331 s2io_reset(sp);
6372 free_irq(dev->irq, dev); 6332 free_rx_buffers(sp);
6333 return -ENODEV;
6334 }
6335
6336 /* Add interrupt service routine */
6337 if (s2io_add_isr(sp) != 0) {
6338 if (sp->intr_type == MSI_X)
6339 s2io_rem_isr(sp);
6340 s2io_reset(sp);
6373 free_rx_buffers(sp); 6341 free_rx_buffers(sp);
6374 return -ENODEV; 6342 return -ENODEV;
6375 } 6343 }
6376 6344
6377 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2)); 6345 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6378 6346
6347 /* Enable tasklet for the device */
6348 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6349
6350 /* Enable select interrupts */
6351 if (sp->intr_type != INTA)
6352 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6353 else {
6354 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6355 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6356 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6357 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6358 }
6359
6360
6379 atomic_set(&sp->card_state, CARD_UP); 6361 atomic_set(&sp->card_state, CARD_UP);
6380 return 0; 6362 return 0;
6381} 6363}
@@ -6395,7 +6377,7 @@ static void s2io_restart_nic(unsigned long data)
6395 struct net_device *dev = (struct net_device *) data; 6377 struct net_device *dev = (struct net_device *) data;
6396 nic_t *sp = dev->priv; 6378 nic_t *sp = dev->priv;
6397 6379
6398 s2io_card_down(sp, 0); 6380 s2io_card_down(sp);
6399 if (s2io_card_up(sp)) { 6381 if (s2io_card_up(sp)) {
6400 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", 6382 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6401 dev->name); 6383 dev->name);
@@ -6437,7 +6419,7 @@ static void s2io_tx_watchdog(struct net_device *dev)
6437 * @cksum : FCS checksum of the frame. 6419 * @cksum : FCS checksum of the frame.
6438 * @ring_no : the ring from which this RxD was extracted. 6420 * @ring_no : the ring from which this RxD was extracted.
6439 * Description: 6421 * Description:
6440 * This function is called by the Tx interrupt serivce routine to perform 6422 * This function is called by the Rx interrupt serivce routine to perform
6441 * some OS related operations on the SKB before passing it to the upper 6423 * some OS related operations on the SKB before passing it to the upper
6442 * layers. It mainly checks if the checksum is OK, if so adds it to the 6424 * layers. It mainly checks if the checksum is OK, if so adds it to the
6443 * SKBs cksum variable, increments the Rx packet count and passes the SKB 6425 * SKBs cksum variable, increments the Rx packet count and passes the SKB
@@ -6697,33 +6679,6 @@ static void s2io_init_pci(nic_t * sp)
6697 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); 6679 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6698} 6680}
6699 6681
6700MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
6701MODULE_LICENSE("GPL");
6702MODULE_VERSION(DRV_VERSION);
6703
6704module_param(tx_fifo_num, int, 0);
6705module_param(rx_ring_num, int, 0);
6706module_param(rx_ring_mode, int, 0);
6707module_param_array(tx_fifo_len, uint, NULL, 0);
6708module_param_array(rx_ring_sz, uint, NULL, 0);
6709module_param_array(rts_frm_len, uint, NULL, 0);
6710module_param(use_continuous_tx_intrs, int, 1);
6711module_param(rmac_pause_time, int, 0);
6712module_param(mc_pause_threshold_q0q3, int, 0);
6713module_param(mc_pause_threshold_q4q7, int, 0);
6714module_param(shared_splits, int, 0);
6715module_param(tmac_util_period, int, 0);
6716module_param(rmac_util_period, int, 0);
6717module_param(bimodal, bool, 0);
6718module_param(l3l4hdr_size, int , 0);
6719#ifndef CONFIG_S2IO_NAPI
6720module_param(indicate_max_pkts, int, 0);
6721#endif
6722module_param(rxsync_frequency, int, 0);
6723module_param(intr_type, int, 0);
6724module_param(lro, int, 0);
6725module_param(lro_max_pkts, int, 0);
6726
6727static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type) 6682static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6728{ 6683{
6729 if ( tx_fifo_num > 8) { 6684 if ( tx_fifo_num > 8) {
@@ -6831,8 +6786,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6831 } 6786 }
6832 if (dev_intr_type != MSI_X) { 6787 if (dev_intr_type != MSI_X) {
6833 if (pci_request_regions(pdev, s2io_driver_name)) { 6788 if (pci_request_regions(pdev, s2io_driver_name)) {
6834 DBG_PRINT(ERR_DBG, "Request Regions failed\n"), 6789 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6835 pci_disable_device(pdev); 6790 pci_disable_device(pdev);
6836 return -ENODEV; 6791 return -ENODEV;
6837 } 6792 }
6838 } 6793 }
@@ -6956,7 +6911,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6956 /* initialize the shared memory used by the NIC and the host */ 6911 /* initialize the shared memory used by the NIC and the host */
6957 if (init_shared_mem(sp)) { 6912 if (init_shared_mem(sp)) {
6958 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", 6913 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6959 __FUNCTION__); 6914 dev->name);
6960 ret = -ENOMEM; 6915 ret = -ENOMEM;
6961 goto mem_alloc_failed; 6916 goto mem_alloc_failed;
6962 } 6917 }
@@ -7093,6 +7048,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7093 dev->addr_len = ETH_ALEN; 7048 dev->addr_len = ETH_ALEN;
7094 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); 7049 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7095 7050
7051 /* reset Nic and bring it to known state */
7052 s2io_reset(sp);
7053
7096 /* 7054 /*
7097 * Initialize the tasklet status and link state flags 7055 * Initialize the tasklet status and link state flags
7098 * and the card state parameter 7056 * and the card state parameter
@@ -7130,11 +7088,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7130 goto register_failed; 7088 goto register_failed;
7131 } 7089 }
7132 s2io_vpd_read(sp); 7090 s2io_vpd_read(sp);
7133 DBG_PRINT(ERR_DBG, "%s: Neterion %s",dev->name, sp->product_name);
7134 DBG_PRINT(ERR_DBG, "(rev %d), Driver version %s\n",
7135 get_xena_rev_id(sp->pdev),
7136 s2io_driver_version);
7137 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n"); 7091 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
7092 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7093 sp->product_name, get_xena_rev_id(sp->pdev));
7094 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7095 s2io_driver_version);
7138 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: " 7096 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7139 "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, 7097 "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
7140 sp->def_mac_addr[0].mac_addr[0], 7098 sp->def_mac_addr[0].mac_addr[0],
@@ -7435,8 +7393,13 @@ static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7435 if (ip->ihl != 5) /* IP has options */ 7393 if (ip->ihl != 5) /* IP has options */
7436 return -1; 7394 return -1;
7437 7395
7396 /* If we see CE codepoint in IP header, packet is not mergeable */
7397 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7398 return -1;
7399
7400 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7438 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin || 7401 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7439 !tcp->ack) { 7402 tcp->ece || tcp->cwr || !tcp->ack) {
7440 /* 7403 /*
7441 * Currently recognize only the ack control word and 7404 * Currently recognize only the ack control word and
7442 * any other control field being set would result in 7405 * any other control field being set would result in
@@ -7590,18 +7553,16 @@ static void queue_rx_frame(struct sk_buff *skb)
7590static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, 7553static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7591 u32 tcp_len) 7554 u32 tcp_len)
7592{ 7555{
7593 struct sk_buff *tmp, *first = lro->parent; 7556 struct sk_buff *first = lro->parent;
7594 7557
7595 first->len += tcp_len; 7558 first->len += tcp_len;
7596 first->data_len = lro->frags_len; 7559 first->data_len = lro->frags_len;
7597 skb_pull(skb, (skb->len - tcp_len)); 7560 skb_pull(skb, (skb->len - tcp_len));
7598 if ((tmp = skb_shinfo(first)->frag_list)) { 7561 if (skb_shinfo(first)->frag_list)
7599 while (tmp->next) 7562 lro->last_frag->next = skb;
7600 tmp = tmp->next;
7601 tmp->next = skb;
7602 }
7603 else 7563 else
7604 skb_shinfo(first)->frag_list = skb; 7564 skb_shinfo(first)->frag_list = skb;
7565 lro->last_frag = skb;
7605 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++; 7566 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7606 return; 7567 return;
7607} 7568}
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index c43f52179708..5ed49c3be1e9 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -719,6 +719,7 @@ struct msix_info_st {
719/* Data structure to represent a LRO session */ 719/* Data structure to represent a LRO session */
720typedef struct lro { 720typedef struct lro {
721 struct sk_buff *parent; 721 struct sk_buff *parent;
722 struct sk_buff *last_frag;
722 u8 *l2h; 723 u8 *l2h;
723 struct iphdr *iph; 724 struct iphdr *iph;
724 struct tcphdr *tcph; 725 struct tcphdr *tcph;
@@ -829,8 +830,7 @@ struct s2io_nic {
829#define MSIX_FLG 0xA5 830#define MSIX_FLG 0xA5
830 struct msix_entry *entries; 831 struct msix_entry *entries;
831 struct s2io_msix_entry *s2io_entries; 832 struct s2io_msix_entry *s2io_entries;
832 char desc1[35]; 833 char desc[MAX_REQUESTED_MSI_X][25];
833 char desc2[35];
834 834
835 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */ 835 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
836 836
@@ -1002,7 +1002,7 @@ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
1002static struct ethtool_ops netdev_ethtool_ops; 1002static struct ethtool_ops netdev_ethtool_ops;
1003static void s2io_set_link(unsigned long data); 1003static void s2io_set_link(unsigned long data);
1004static int s2io_set_swapper(nic_t * sp); 1004static int s2io_set_swapper(nic_t * sp);
1005static void s2io_card_down(nic_t *nic, int flag); 1005static void s2io_card_down(nic_t *nic);
1006static int s2io_card_up(nic_t *nic); 1006static int s2io_card_up(nic_t *nic);
1007static int get_xena_rev_id(struct pci_dev *pdev); 1007static int get_xena_rev_id(struct pci_dev *pdev);
1008static void restore_xmsi_data(nic_t *nic); 1008static void restore_xmsi_data(nic_t *nic);
@@ -1012,4 +1012,13 @@ static void clear_lro_session(lro_t *lro);
1012static void queue_rx_frame(struct sk_buff *skb); 1012static void queue_rx_frame(struct sk_buff *skb);
1013static void update_L3L4_header(nic_t *sp, lro_t *lro); 1013static void update_L3L4_header(nic_t *sp, lro_t *lro);
1014static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, u32 tcp_len); 1014static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, u32 tcp_len);
1015
1016#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1017#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1018#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1019
1020#define S2IO_PARM_INT(X, def_val) \
1021 static unsigned int X = def_val;\
1022 module_param(X , uint, 0);
1023
1015#endif /* _S2IO_H */ 1024#endif /* _S2IO_H */
diff --git a/drivers/net/sk98lin/h/xmac_ii.h b/drivers/net/sk98lin/h/xmac_ii.h
index 2b19f8ad0318..7f8e6d0084c7 100644
--- a/drivers/net/sk98lin/h/xmac_ii.h
+++ b/drivers/net/sk98lin/h/xmac_ii.h
@@ -1473,7 +1473,7 @@ extern "C" {
1473#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */ 1473#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
1474#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */ 1474#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
1475#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */ 1475#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
1476#define GM_TXCR_COL_THR_MSK (1<<10) /* Bit 12..10: Collision Threshold */ 1476#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold */
1477 1477
1478#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1478#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
1479 1479
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 82200bfaa8ed..7de9a07b2ac2 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -516,10 +516,7 @@ static int skge_set_pauseparam(struct net_device *dev,
516/* Chip internal frequency for clock calculations */ 516/* Chip internal frequency for clock calculations */
517static inline u32 hwkhz(const struct skge_hw *hw) 517static inline u32 hwkhz(const struct skge_hw *hw)
518{ 518{
519 if (hw->chip_id == CHIP_ID_GENESIS) 519 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
520 return 53215; /* or: 53.125 MHz */
521 else
522 return 78215; /* or: 78.125 MHz */
523} 520}
524 521
525/* Chip HZ to microseconds */ 522/* Chip HZ to microseconds */
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index ed19ff47ce11..593387b3c0dd 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -1734,11 +1734,11 @@ enum {
1734 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ 1734 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1735 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ 1735 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1736 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ 1736 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1737 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */ 1737 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1738}; 1738};
1739 1739
1740#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) 1740#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1741#define TX_COL_DEF 0x04 1741#define TX_COL_DEF 0x04 /* late collision after 64 byte */
1742 1742
1743/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1743/* GM_RX_CTRL 16 bit r/w Receive Control Register */
1744enum { 1744enum {
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 418f169a6a31..de91609ca112 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -50,7 +50,7 @@
50#include "sky2.h" 50#include "sky2.h"
51 51
52#define DRV_NAME "sky2" 52#define DRV_NAME "sky2"
53#define DRV_VERSION "1.4" 53#define DRV_VERSION "1.5"
54#define PFX DRV_NAME " " 54#define PFX DRV_NAME " "
55 55
56/* 56/*
@@ -65,6 +65,7 @@
65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66#define RX_DEF_PENDING RX_MAX_PENDING 66#define RX_DEF_PENDING RX_MAX_PENDING
67#define RX_SKB_ALIGN 8 67#define RX_SKB_ALIGN 8
68#define RX_BUF_WRITE 16
68 69
69#define TX_RING_SIZE 512 70#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1) 71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
@@ -234,7 +235,6 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
234 } 235 }
235 236
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 237 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
237 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
238 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
239 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); 239 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
240 reg1 &= P_ASPM_CONTROL_MSK; 240 reg1 &= P_ASPM_CONTROL_MSK;
@@ -243,6 +243,7 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
243 } 243 }
244 244
245 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 245 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
246 udelay(100);
246 247
247 break; 248 break;
248 249
@@ -255,6 +256,7 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
255 else 256 else
256 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 257 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
257 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 258 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
259 udelay(100);
258 260
259 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
260 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
@@ -1159,7 +1161,7 @@ static unsigned tx_le_req(const struct sk_buff *skb)
1159 count = sizeof(dma_addr_t) / sizeof(u32); 1161 count = sizeof(dma_addr_t) / sizeof(u32);
1160 count += skb_shinfo(skb)->nr_frags * count; 1162 count += skb_shinfo(skb)->nr_frags * count;
1161 1163
1162 if (skb_shinfo(skb)->gso_size) 1164 if (skb_is_gso(skb))
1163 ++count; 1165 ++count;
1164 1166
1165 if (skb->ip_summed == CHECKSUM_HW) 1167 if (skb->ip_summed == CHECKSUM_HW)
@@ -1389,7 +1391,7 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1389 } 1391 }
1390 1392
1391 sky2->tx_cons = put; 1393 sky2->tx_cons = put;
1392 if (tx_avail(sky2) > MAX_SKB_TX_LE) 1394 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1393 netif_wake_queue(dev); 1395 netif_wake_queue(dev);
1394} 1396}
1395 1397
@@ -1888,9 +1890,6 @@ resubmit:
1888 re->skb->ip_summed = CHECKSUM_NONE; 1890 re->skb->ip_summed = CHECKSUM_NONE;
1889 sky2_rx_add(sky2, re->mapaddr); 1891 sky2_rx_add(sky2, re->mapaddr);
1890 1892
1891 /* Tell receiver about new buffers. */
1892 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1893
1894 return skb; 1893 return skb;
1895 1894
1896oversize: 1895oversize:
@@ -1937,7 +1936,9 @@ static inline int sky2_more_work(const struct sky2_hw *hw)
1937/* Process status response ring */ 1936/* Process status response ring */
1938static int sky2_status_intr(struct sky2_hw *hw, int to_do) 1937static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1939{ 1938{
1939 struct sky2_port *sky2;
1940 int work_done = 0; 1940 int work_done = 0;
1941 unsigned buf_write[2] = { 0, 0 };
1941 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX); 1942 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1942 1943
1943 rmb(); 1944 rmb();
@@ -1945,7 +1946,6 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1945 while (hw->st_idx != hwidx) { 1946 while (hw->st_idx != hwidx) {
1946 struct sky2_status_le *le = hw->st_le + hw->st_idx; 1947 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1947 struct net_device *dev; 1948 struct net_device *dev;
1948 struct sky2_port *sky2;
1949 struct sk_buff *skb; 1949 struct sk_buff *skb;
1950 u32 status; 1950 u32 status;
1951 u16 length; 1951 u16 length;
@@ -1978,6 +1978,14 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1978#endif 1978#endif
1979 netif_receive_skb(skb); 1979 netif_receive_skb(skb);
1980 1980
1981 /* Update receiver after 16 frames */
1982 if (++buf_write[le->link] == RX_BUF_WRITE) {
1983 sky2_put_idx(hw, rxqaddr[le->link],
1984 sky2->rx_put);
1985 buf_write[le->link] = 0;
1986 }
1987
1988 /* Stop after net poll weight */
1981 if (++work_done >= to_do) 1989 if (++work_done >= to_do)
1982 goto exit_loop; 1990 goto exit_loop;
1983 break; 1991 break;
@@ -2016,6 +2024,16 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2016 } 2024 }
2017 2025
2018exit_loop: 2026exit_loop:
2027 if (buf_write[0]) {
2028 sky2 = netdev_priv(hw->dev[0]);
2029 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2030 }
2031
2032 if (buf_write[1]) {
2033 sky2 = netdev_priv(hw->dev[1]);
2034 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2035 }
2036
2019 return work_done; 2037 return work_done;
2020} 2038}
2021 2039
@@ -2186,9 +2204,6 @@ static int sky2_poll(struct net_device *dev0, int *budget)
2186 int work_done = 0; 2204 int work_done = 0;
2187 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 2205 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2188 2206
2189 if (!~status)
2190 goto out;
2191
2192 if (status & Y2_IS_HW_ERR) 2207 if (status & Y2_IS_HW_ERR)
2193 sky2_hw_intr(hw); 2208 sky2_hw_intr(hw);
2194 2209
@@ -2225,7 +2240,7 @@ static int sky2_poll(struct net_device *dev0, int *budget)
2225 2240
2226 if (sky2_more_work(hw)) 2241 if (sky2_more_work(hw))
2227 return 1; 2242 return 1;
2228out: 2243
2229 netif_rx_complete(dev0); 2244 netif_rx_complete(dev0);
2230 2245
2231 sky2_read32(hw, B0_Y2_SP_LISR); 2246 sky2_read32(hw, B0_Y2_SP_LISR);
@@ -2286,7 +2301,7 @@ static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2286} 2301}
2287 2302
2288 2303
2289static int __devinit sky2_reset(struct sky2_hw *hw) 2304static int sky2_reset(struct sky2_hw *hw)
2290{ 2305{
2291 u16 status; 2306 u16 status;
2292 u8 t8, pmd_type; 2307 u8 t8, pmd_type;
@@ -3437,17 +3452,14 @@ static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3437 return -EINVAL; 3452 return -EINVAL;
3438 3453
3439 del_timer_sync(&hw->idle_timer); 3454 del_timer_sync(&hw->idle_timer);
3455 netif_poll_disable(hw->dev[0]);
3440 3456
3441 for (i = 0; i < hw->ports; i++) { 3457 for (i = 0; i < hw->ports; i++) {
3442 struct net_device *dev = hw->dev[i]; 3458 struct net_device *dev = hw->dev[i];
3443 3459
3444 if (dev) { 3460 if (netif_running(dev)) {
3445 if (!netif_running(dev))
3446 continue;
3447
3448 sky2_down(dev); 3461 sky2_down(dev);
3449 netif_device_detach(dev); 3462 netif_device_detach(dev);
3450 netif_poll_disable(dev);
3451 } 3463 }
3452 } 3464 }
3453 3465
@@ -3474,9 +3486,8 @@ static int sky2_resume(struct pci_dev *pdev)
3474 3486
3475 for (i = 0; i < hw->ports; i++) { 3487 for (i = 0; i < hw->ports; i++) {
3476 struct net_device *dev = hw->dev[i]; 3488 struct net_device *dev = hw->dev[i];
3477 if (dev && netif_running(dev)) { 3489 if (netif_running(dev)) {
3478 netif_device_attach(dev); 3490 netif_device_attach(dev);
3479 netif_poll_enable(dev);
3480 3491
3481 err = sky2_up(dev); 3492 err = sky2_up(dev);
3482 if (err) { 3493 if (err) {
@@ -3488,6 +3499,7 @@ static int sky2_resume(struct pci_dev *pdev)
3488 } 3499 }
3489 } 3500 }
3490 3501
3502 netif_poll_enable(hw->dev[0]);
3491 sky2_idle_start(hw); 3503 sky2_idle_start(hw);
3492out: 3504out:
3493 return err; 3505 return err;
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 8a0bc5525f0a..2db8d19b22d1 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -1480,7 +1480,7 @@ enum {
1480 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ 1480 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1481 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ 1481 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1482 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ 1482 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1483 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */ 1483 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1484}; 1484};
1485 1485
1486#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) 1486#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index b4028049ed76..4ec4b4d23ae5 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -354,6 +354,24 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
354 354
355#define SMC_IRQ_FLAGS (0) 355#define SMC_IRQ_FLAGS (0)
356 356
357#elif defined(CONFIG_ARCH_VERSATILE)
358
359#define SMC_CAN_USE_8BIT 1
360#define SMC_CAN_USE_16BIT 1
361#define SMC_CAN_USE_32BIT 1
362#define SMC_NOWAIT 1
363
364#define SMC_inb(a, r) readb((a) + (r))
365#define SMC_inw(a, r) readw((a) + (r))
366#define SMC_inl(a, r) readl((a) + (r))
367#define SMC_outb(v, a, r) writeb(v, (a) + (r))
368#define SMC_outw(v, a, r) writew(v, (a) + (r))
369#define SMC_outl(v, a, r) writel(v, (a) + (r))
370#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
371#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
372
373#define SMC_IRQ_FLAGS (0)
374
357#else 375#else
358 376
359#define SMC_CAN_USE_8BIT 1 377#define SMC_CAN_USE_8BIT 1
diff --git a/drivers/net/spider_net.c b/drivers/net/spider_net.c
index fb1d5a8a45cf..647f62e9707d 100644
--- a/drivers/net/spider_net.c
+++ b/drivers/net/spider_net.c
@@ -84,7 +84,7 @@ MODULE_DEVICE_TABLE(pci, spider_net_pci_tbl);
84 * 84 *
85 * returns the content of the specified SMMIO register. 85 * returns the content of the specified SMMIO register.
86 */ 86 */
87static u32 87static inline u32
88spider_net_read_reg(struct spider_net_card *card, u32 reg) 88spider_net_read_reg(struct spider_net_card *card, u32 reg)
89{ 89{
90 u32 value; 90 u32 value;
@@ -101,7 +101,7 @@ spider_net_read_reg(struct spider_net_card *card, u32 reg)
101 * @reg: register to write to 101 * @reg: register to write to
102 * @value: value to write into the specified SMMIO register 102 * @value: value to write into the specified SMMIO register
103 */ 103 */
104static void 104static inline void
105spider_net_write_reg(struct spider_net_card *card, u32 reg, u32 value) 105spider_net_write_reg(struct spider_net_card *card, u32 reg, u32 value)
106{ 106{
107 value = cpu_to_le32(value); 107 value = cpu_to_le32(value);
@@ -259,39 +259,10 @@ spider_net_get_mac_address(struct net_device *netdev)
259 * 259 *
260 * returns the status as in the dmac_cmd_status field of the descriptor 260 * returns the status as in the dmac_cmd_status field of the descriptor
261 */ 261 */
262static enum spider_net_descr_status 262static inline int
263spider_net_get_descr_status(struct spider_net_descr *descr) 263spider_net_get_descr_status(struct spider_net_descr *descr)
264{ 264{
265 u32 cmd_status; 265 return descr->dmac_cmd_status & SPIDER_NET_DESCR_IND_PROC_MASK;
266
267 cmd_status = descr->dmac_cmd_status;
268 cmd_status >>= SPIDER_NET_DESCR_IND_PROC_SHIFT;
269 /* no need to mask out any bits, as cmd_status is 32 bits wide only
270 * (and unsigned) */
271 return cmd_status;
272}
273
274/**
275 * spider_net_set_descr_status -- sets the status of a descriptor
276 * @descr: descriptor to change
277 * @status: status to set in the descriptor
278 *
279 * changes the status to the specified value. Doesn't change other bits
280 * in the status
281 */
282static void
283spider_net_set_descr_status(struct spider_net_descr *descr,
284 enum spider_net_descr_status status)
285{
286 u32 cmd_status;
287 /* read the status */
288 cmd_status = descr->dmac_cmd_status;
289 /* clean the upper 4 bits */
290 cmd_status &= SPIDER_NET_DESCR_IND_PROC_MASKO;
291 /* add the status to it */
292 cmd_status |= ((u32)status)<<SPIDER_NET_DESCR_IND_PROC_SHIFT;
293 /* and write it back */
294 descr->dmac_cmd_status = cmd_status;
295} 266}
296 267
297/** 268/**
@@ -328,24 +299,23 @@ spider_net_free_chain(struct spider_net_card *card,
328static int 299static int
329spider_net_init_chain(struct spider_net_card *card, 300spider_net_init_chain(struct spider_net_card *card,
330 struct spider_net_descr_chain *chain, 301 struct spider_net_descr_chain *chain,
331 struct spider_net_descr *start_descr, int no) 302 struct spider_net_descr *start_descr,
303 int direction, int no)
332{ 304{
333 int i; 305 int i;
334 struct spider_net_descr *descr; 306 struct spider_net_descr *descr;
335 dma_addr_t buf; 307 dma_addr_t buf;
336 308
337 atomic_set(&card->rx_chain_refill,0);
338
339 descr = start_descr; 309 descr = start_descr;
340 memset(descr, 0, sizeof(*descr) * no); 310 memset(descr, 0, sizeof(*descr) * no);
341 311
342 /* set up the hardware pointers in each descriptor */ 312 /* set up the hardware pointers in each descriptor */
343 for (i=0; i<no; i++, descr++) { 313 for (i=0; i<no; i++, descr++) {
344 spider_net_set_descr_status(descr, SPIDER_NET_DESCR_NOT_IN_USE); 314 descr->dmac_cmd_status = SPIDER_NET_DESCR_NOT_IN_USE;
345 315
346 buf = pci_map_single(card->pdev, descr, 316 buf = pci_map_single(card->pdev, descr,
347 SPIDER_NET_DESCR_SIZE, 317 SPIDER_NET_DESCR_SIZE,
348 PCI_DMA_BIDIRECTIONAL); 318 direction);
349 319
350 if (buf == DMA_ERROR_CODE) 320 if (buf == DMA_ERROR_CODE)
351 goto iommu_error; 321 goto iommu_error;
@@ -360,10 +330,11 @@ spider_net_init_chain(struct spider_net_card *card,
360 start_descr->prev = descr-1; 330 start_descr->prev = descr-1;
361 331
362 descr = start_descr; 332 descr = start_descr;
363 for (i=0; i < no; i++, descr++) { 333 if (direction == PCI_DMA_FROMDEVICE)
364 descr->next_descr_addr = descr->next->bus_addr; 334 for (i=0; i < no; i++, descr++)
365 } 335 descr->next_descr_addr = descr->next->bus_addr;
366 336
337 spin_lock_init(&chain->lock);
367 chain->head = start_descr; 338 chain->head = start_descr;
368 chain->tail = start_descr; 339 chain->tail = start_descr;
369 340
@@ -375,7 +346,7 @@ iommu_error:
375 if (descr->bus_addr) 346 if (descr->bus_addr)
376 pci_unmap_single(card->pdev, descr->bus_addr, 347 pci_unmap_single(card->pdev, descr->bus_addr,
377 SPIDER_NET_DESCR_SIZE, 348 SPIDER_NET_DESCR_SIZE,
378 PCI_DMA_BIDIRECTIONAL); 349 direction);
379 return -ENOMEM; 350 return -ENOMEM;
380} 351}
381 352
@@ -396,7 +367,7 @@ spider_net_free_rx_chain_contents(struct spider_net_card *card)
396 dev_kfree_skb(descr->skb); 367 dev_kfree_skb(descr->skb);
397 pci_unmap_single(card->pdev, descr->buf_addr, 368 pci_unmap_single(card->pdev, descr->buf_addr,
398 SPIDER_NET_MAX_FRAME, 369 SPIDER_NET_MAX_FRAME,
399 PCI_DMA_BIDIRECTIONAL); 370 PCI_DMA_FROMDEVICE);
400 } 371 }
401 descr = descr->next; 372 descr = descr->next;
402 } 373 }
@@ -446,15 +417,16 @@ spider_net_prepare_rx_descr(struct spider_net_card *card,
446 skb_reserve(descr->skb, SPIDER_NET_RXBUF_ALIGN - offset); 417 skb_reserve(descr->skb, SPIDER_NET_RXBUF_ALIGN - offset);
447 /* io-mmu-map the skb */ 418 /* io-mmu-map the skb */
448 buf = pci_map_single(card->pdev, descr->skb->data, 419 buf = pci_map_single(card->pdev, descr->skb->data,
449 SPIDER_NET_MAX_FRAME, PCI_DMA_BIDIRECTIONAL); 420 SPIDER_NET_MAX_FRAME, PCI_DMA_FROMDEVICE);
450 descr->buf_addr = buf; 421 descr->buf_addr = buf;
451 if (buf == DMA_ERROR_CODE) { 422 if (buf == DMA_ERROR_CODE) {
452 dev_kfree_skb_any(descr->skb); 423 dev_kfree_skb_any(descr->skb);
453 if (netif_msg_rx_err(card) && net_ratelimit()) 424 if (netif_msg_rx_err(card) && net_ratelimit())
454 pr_err("Could not iommu-map rx buffer\n"); 425 pr_err("Could not iommu-map rx buffer\n");
455 spider_net_set_descr_status(descr, SPIDER_NET_DESCR_NOT_IN_USE); 426 descr->dmac_cmd_status = SPIDER_NET_DESCR_NOT_IN_USE;
456 } else { 427 } else {
457 descr->dmac_cmd_status = SPIDER_NET_DMAC_RX_CARDOWNED; 428 descr->dmac_cmd_status = SPIDER_NET_DESCR_CARDOWNED |
429 SPIDER_NET_DMAC_NOINTR_COMPLETE;
458 } 430 }
459 431
460 return error; 432 return error;
@@ -468,7 +440,7 @@ spider_net_prepare_rx_descr(struct spider_net_card *card,
468 * chip by writing to the appropriate register. DMA is enabled in 440 * chip by writing to the appropriate register. DMA is enabled in
469 * spider_net_enable_rxdmac. 441 * spider_net_enable_rxdmac.
470 */ 442 */
471static void 443static inline void
472spider_net_enable_rxchtails(struct spider_net_card *card) 444spider_net_enable_rxchtails(struct spider_net_card *card)
473{ 445{
474 /* assume chain is aligned correctly */ 446 /* assume chain is aligned correctly */
@@ -483,7 +455,7 @@ spider_net_enable_rxchtails(struct spider_net_card *card)
483 * spider_net_enable_rxdmac enables the DMA controller by setting RX_DMA_EN 455 * spider_net_enable_rxdmac enables the DMA controller by setting RX_DMA_EN
484 * in the GDADMACCNTR register 456 * in the GDADMACCNTR register
485 */ 457 */
486static void 458static inline void
487spider_net_enable_rxdmac(struct spider_net_card *card) 459spider_net_enable_rxdmac(struct spider_net_card *card)
488{ 460{
489 wmb(); 461 wmb();
@@ -500,23 +472,24 @@ spider_net_enable_rxdmac(struct spider_net_card *card)
500static void 472static void
501spider_net_refill_rx_chain(struct spider_net_card *card) 473spider_net_refill_rx_chain(struct spider_net_card *card)
502{ 474{
503 struct spider_net_descr_chain *chain; 475 struct spider_net_descr_chain *chain = &card->rx_chain;
504 476 unsigned long flags;
505 chain = &card->rx_chain;
506 477
507 /* one context doing the refill (and a second context seeing that 478 /* one context doing the refill (and a second context seeing that
508 * and omitting it) is ok. If called by NAPI, we'll be called again 479 * and omitting it) is ok. If called by NAPI, we'll be called again
509 * as spider_net_decode_one_descr is called several times. If some 480 * as spider_net_decode_one_descr is called several times. If some
510 * interrupt calls us, the NAPI is about to clean up anyway. */ 481 * interrupt calls us, the NAPI is about to clean up anyway. */
511 if (atomic_inc_return(&card->rx_chain_refill) == 1) 482 if (!spin_trylock_irqsave(&chain->lock, flags))
512 while (spider_net_get_descr_status(chain->head) == 483 return;
513 SPIDER_NET_DESCR_NOT_IN_USE) { 484
514 if (spider_net_prepare_rx_descr(card, chain->head)) 485 while (spider_net_get_descr_status(chain->head) ==
515 break; 486 SPIDER_NET_DESCR_NOT_IN_USE) {
516 chain->head = chain->head->next; 487 if (spider_net_prepare_rx_descr(card, chain->head))
517 } 488 break;
489 chain->head = chain->head->next;
490 }
518 491
519 atomic_dec(&card->rx_chain_refill); 492 spin_unlock_irqrestore(&chain->lock, flags);
520} 493}
521 494
522/** 495/**
@@ -554,111 +527,6 @@ error:
554} 527}
555 528
556/** 529/**
557 * spider_net_release_tx_descr - processes a used tx descriptor
558 * @card: card structure
559 * @descr: descriptor to release
560 *
561 * releases a used tx descriptor (unmapping, freeing of skb)
562 */
563static void
564spider_net_release_tx_descr(struct spider_net_card *card,
565 struct spider_net_descr *descr)
566{
567 struct sk_buff *skb;
568
569 /* unmap the skb */
570 skb = descr->skb;
571 pci_unmap_single(card->pdev, descr->buf_addr, skb->len,
572 PCI_DMA_BIDIRECTIONAL);
573
574 dev_kfree_skb_any(skb);
575
576 /* set status to not used */
577 spider_net_set_descr_status(descr, SPIDER_NET_DESCR_NOT_IN_USE);
578}
579
580/**
581 * spider_net_release_tx_chain - processes sent tx descriptors
582 * @card: adapter structure
583 * @brutal: if set, don't care about whether descriptor seems to be in use
584 *
585 * returns 0 if the tx ring is empty, otherwise 1.
586 *
587 * spider_net_release_tx_chain releases the tx descriptors that spider has
588 * finished with (if non-brutal) or simply release tx descriptors (if brutal).
589 * If some other context is calling this function, we return 1 so that we're
590 * scheduled again (if we were scheduled) and will not loose initiative.
591 */
592static int
593spider_net_release_tx_chain(struct spider_net_card *card, int brutal)
594{
595 struct spider_net_descr_chain *tx_chain = &card->tx_chain;
596 enum spider_net_descr_status status;
597
598 if (atomic_inc_return(&card->tx_chain_release) != 1) {
599 atomic_dec(&card->tx_chain_release);
600 return 1;
601 }
602
603 for (;;) {
604 status = spider_net_get_descr_status(tx_chain->tail);
605 switch (status) {
606 case SPIDER_NET_DESCR_CARDOWNED:
607 if (!brutal)
608 goto out;
609 /* fallthrough, if we release the descriptors
610 * brutally (then we don't care about
611 * SPIDER_NET_DESCR_CARDOWNED) */
612 case SPIDER_NET_DESCR_RESPONSE_ERROR:
613 case SPIDER_NET_DESCR_PROTECTION_ERROR:
614 case SPIDER_NET_DESCR_FORCE_END:
615 if (netif_msg_tx_err(card))
616 pr_err("%s: forcing end of tx descriptor "
617 "with status x%02x\n",
618 card->netdev->name, status);
619 card->netdev_stats.tx_dropped++;
620 break;
621
622 case SPIDER_NET_DESCR_COMPLETE:
623 card->netdev_stats.tx_packets++;
624 card->netdev_stats.tx_bytes +=
625 tx_chain->tail->skb->len;
626 break;
627
628 default: /* any other value (== SPIDER_NET_DESCR_NOT_IN_USE) */
629 goto out;
630 }
631 spider_net_release_tx_descr(card, tx_chain->tail);
632 tx_chain->tail = tx_chain->tail->next;
633 }
634out:
635 atomic_dec(&card->tx_chain_release);
636
637 netif_wake_queue(card->netdev);
638
639 if (status == SPIDER_NET_DESCR_CARDOWNED)
640 return 1;
641 return 0;
642}
643
644/**
645 * spider_net_cleanup_tx_ring - cleans up the TX ring
646 * @card: card structure
647 *
648 * spider_net_cleanup_tx_ring is called by the tx_timer (as we don't use
649 * interrupts to cleanup our TX ring) and returns sent packets to the stack
650 * by freeing them
651 */
652static void
653spider_net_cleanup_tx_ring(struct spider_net_card *card)
654{
655 if ( (spider_net_release_tx_chain(card, 0)) &&
656 (card->netdev->flags & IFF_UP) ) {
657 mod_timer(&card->tx_timer, jiffies + SPIDER_NET_TX_TIMER);
658 }
659}
660
661/**
662 * spider_net_get_multicast_hash - generates hash for multicast filter table 530 * spider_net_get_multicast_hash - generates hash for multicast filter table
663 * @addr: multicast address 531 * @addr: multicast address
664 * 532 *
@@ -761,97 +629,6 @@ spider_net_disable_rxdmac(struct spider_net_card *card)
761} 629}
762 630
763/** 631/**
764 * spider_net_stop - called upon ifconfig down
765 * @netdev: interface device structure
766 *
767 * always returns 0
768 */
769int
770spider_net_stop(struct net_device *netdev)
771{
772 struct spider_net_card *card = netdev_priv(netdev);
773
774 tasklet_kill(&card->rxram_full_tl);
775 netif_poll_disable(netdev);
776 netif_carrier_off(netdev);
777 netif_stop_queue(netdev);
778 del_timer_sync(&card->tx_timer);
779
780 /* disable/mask all interrupts */
781 spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK, 0);
782 spider_net_write_reg(card, SPIDER_NET_GHIINT1MSK, 0);
783 spider_net_write_reg(card, SPIDER_NET_GHIINT2MSK, 0);
784
785 /* free_irq(netdev->irq, netdev);*/
786 free_irq(to_pci_dev(netdev->class_dev.dev)->irq, netdev);
787
788 spider_net_write_reg(card, SPIDER_NET_GDTDMACCNTR,
789 SPIDER_NET_DMA_TX_FEND_VALUE);
790
791 /* turn off DMA, force end */
792 spider_net_disable_rxdmac(card);
793
794 /* release chains */
795 spider_net_release_tx_chain(card, 1);
796
797 spider_net_free_chain(card, &card->tx_chain);
798 spider_net_free_chain(card, &card->rx_chain);
799
800 return 0;
801}
802
803/**
804 * spider_net_get_next_tx_descr - returns the next available tx descriptor
805 * @card: device structure to get descriptor from
806 *
807 * returns the address of the next descriptor, or NULL if not available.
808 */
809static struct spider_net_descr *
810spider_net_get_next_tx_descr(struct spider_net_card *card)
811{
812 /* check, if head points to not-in-use descr */
813 if ( spider_net_get_descr_status(card->tx_chain.head) ==
814 SPIDER_NET_DESCR_NOT_IN_USE ) {
815 return card->tx_chain.head;
816 } else {
817 return NULL;
818 }
819}
820
821/**
822 * spider_net_set_txdescr_cmdstat - sets the tx descriptor command field
823 * @descr: descriptor structure to fill out
824 * @skb: packet to consider
825 *
826 * fills out the command and status field of the descriptor structure,
827 * depending on hardware checksum settings.
828 */
829static void
830spider_net_set_txdescr_cmdstat(struct spider_net_descr *descr,
831 struct sk_buff *skb)
832{
833 /* make sure the other fields in the descriptor are written */
834 wmb();
835
836 if (skb->ip_summed != CHECKSUM_HW) {
837 descr->dmac_cmd_status = SPIDER_NET_DMAC_CMDSTAT_NOCS;
838 return;
839 }
840
841 /* is packet ip?
842 * if yes: tcp? udp? */
843 if (skb->protocol == htons(ETH_P_IP)) {
844 if (skb->nh.iph->protocol == IPPROTO_TCP)
845 descr->dmac_cmd_status = SPIDER_NET_DMAC_CMDSTAT_TCPCS;
846 else if (skb->nh.iph->protocol == IPPROTO_UDP)
847 descr->dmac_cmd_status = SPIDER_NET_DMAC_CMDSTAT_UDPCS;
848 else /* the stack should checksum non-tcp and non-udp
849 packets on his own: NETIF_F_IP_CSUM */
850 descr->dmac_cmd_status = SPIDER_NET_DMAC_CMDSTAT_NOCS;
851 }
852}
853
854/**
855 * spider_net_prepare_tx_descr - fill tx descriptor with skb data 632 * spider_net_prepare_tx_descr - fill tx descriptor with skb data
856 * @card: card structure 633 * @card: card structure
857 * @descr: descriptor structure to fill out 634 * @descr: descriptor structure to fill out
@@ -864,13 +641,12 @@ spider_net_set_txdescr_cmdstat(struct spider_net_descr *descr,
864 */ 641 */
865static int 642static int
866spider_net_prepare_tx_descr(struct spider_net_card *card, 643spider_net_prepare_tx_descr(struct spider_net_card *card,
867 struct spider_net_descr *descr,
868 struct sk_buff *skb) 644 struct sk_buff *skb)
869{ 645{
646 struct spider_net_descr *descr = card->tx_chain.head;
870 dma_addr_t buf; 647 dma_addr_t buf;
871 648
872 buf = pci_map_single(card->pdev, skb->data, 649 buf = pci_map_single(card->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
873 skb->len, PCI_DMA_BIDIRECTIONAL);
874 if (buf == DMA_ERROR_CODE) { 650 if (buf == DMA_ERROR_CODE) {
875 if (netif_msg_tx_err(card) && net_ratelimit()) 651 if (netif_msg_tx_err(card) && net_ratelimit())
876 pr_err("could not iommu-map packet (%p, %i). " 652 pr_err("could not iommu-map packet (%p, %i). "
@@ -880,10 +656,101 @@ spider_net_prepare_tx_descr(struct spider_net_card *card,
880 656
881 descr->buf_addr = buf; 657 descr->buf_addr = buf;
882 descr->buf_size = skb->len; 658 descr->buf_size = skb->len;
659 descr->next_descr_addr = 0;
883 descr->skb = skb; 660 descr->skb = skb;
884 descr->data_status = 0; 661 descr->data_status = 0;
885 662
886 spider_net_set_txdescr_cmdstat(descr,skb); 663 descr->dmac_cmd_status =
664 SPIDER_NET_DESCR_CARDOWNED | SPIDER_NET_DMAC_NOCS;
665 if (skb->protocol == htons(ETH_P_IP))
666 switch (skb->nh.iph->protocol) {
667 case IPPROTO_TCP:
668 descr->dmac_cmd_status |= SPIDER_NET_DMAC_TCP;
669 break;
670 case IPPROTO_UDP:
671 descr->dmac_cmd_status |= SPIDER_NET_DMAC_UDP;
672 break;
673 }
674
675 descr->prev->next_descr_addr = descr->bus_addr;
676
677 return 0;
678}
679
680/**
681 * spider_net_release_tx_descr - processes a used tx descriptor
682 * @card: card structure
683 * @descr: descriptor to release
684 *
685 * releases a used tx descriptor (unmapping, freeing of skb)
686 */
687static inline void
688spider_net_release_tx_descr(struct spider_net_card *card)
689{
690 struct spider_net_descr *descr = card->tx_chain.tail;
691 struct sk_buff *skb;
692
693 card->tx_chain.tail = card->tx_chain.tail->next;
694 descr->dmac_cmd_status |= SPIDER_NET_DESCR_NOT_IN_USE;
695
696 /* unmap the skb */
697 skb = descr->skb;
698 pci_unmap_single(card->pdev, descr->buf_addr, skb->len,
699 PCI_DMA_TODEVICE);
700 dev_kfree_skb_any(skb);
701}
702
703/**
704 * spider_net_release_tx_chain - processes sent tx descriptors
705 * @card: adapter structure
706 * @brutal: if set, don't care about whether descriptor seems to be in use
707 *
708 * returns 0 if the tx ring is empty, otherwise 1.
709 *
710 * spider_net_release_tx_chain releases the tx descriptors that spider has
711 * finished with (if non-brutal) or simply release tx descriptors (if brutal).
712 * If some other context is calling this function, we return 1 so that we're
713 * scheduled again (if we were scheduled) and will not loose initiative.
714 */
715static int
716spider_net_release_tx_chain(struct spider_net_card *card, int brutal)
717{
718 struct spider_net_descr_chain *chain = &card->tx_chain;
719 int status;
720
721 spider_net_read_reg(card, SPIDER_NET_GDTDMACCNTR);
722
723 while (chain->tail != chain->head) {
724 status = spider_net_get_descr_status(chain->tail);
725 switch (status) {
726 case SPIDER_NET_DESCR_COMPLETE:
727 card->netdev_stats.tx_packets++;
728 card->netdev_stats.tx_bytes += chain->tail->skb->len;
729 break;
730
731 case SPIDER_NET_DESCR_CARDOWNED:
732 if (!brutal)
733 return 1;
734 /* fallthrough, if we release the descriptors
735 * brutally (then we don't care about
736 * SPIDER_NET_DESCR_CARDOWNED) */
737
738 case SPIDER_NET_DESCR_RESPONSE_ERROR:
739 case SPIDER_NET_DESCR_PROTECTION_ERROR:
740 case SPIDER_NET_DESCR_FORCE_END:
741 if (netif_msg_tx_err(card))
742 pr_err("%s: forcing end of tx descriptor "
743 "with status x%02x\n",
744 card->netdev->name, status);
745 card->netdev_stats.tx_errors++;
746 break;
747
748 default:
749 card->netdev_stats.tx_dropped++;
750 return 1;
751 }
752 spider_net_release_tx_descr(card);
753 }
887 754
888 return 0; 755 return 0;
889} 756}
@@ -896,18 +763,32 @@ spider_net_prepare_tx_descr(struct spider_net_card *card,
896 * spider_net_kick_tx_dma writes the current tx chain head as start address 763 * spider_net_kick_tx_dma writes the current tx chain head as start address
897 * of the tx descriptor chain and enables the transmission DMA engine 764 * of the tx descriptor chain and enables the transmission DMA engine
898 */ 765 */
899static void 766static inline void
900spider_net_kick_tx_dma(struct spider_net_card *card, 767spider_net_kick_tx_dma(struct spider_net_card *card)
901 struct spider_net_descr *descr)
902{ 768{
903 /* this is the only descriptor in the output chain. 769 struct spider_net_descr *descr;
904 * Enable TX DMA */
905 770
906 spider_net_write_reg(card, SPIDER_NET_GDTDCHA, 771 if (spider_net_read_reg(card, SPIDER_NET_GDTDMACCNTR) &
907 descr->bus_addr); 772 SPIDER_NET_TX_DMA_EN)
773 goto out;
908 774
909 spider_net_write_reg(card, SPIDER_NET_GDTDMACCNTR, 775 descr = card->tx_chain.tail;
910 SPIDER_NET_DMA_TX_VALUE); 776 for (;;) {
777 if (spider_net_get_descr_status(descr) ==
778 SPIDER_NET_DESCR_CARDOWNED) {
779 spider_net_write_reg(card, SPIDER_NET_GDTDCHA,
780 descr->bus_addr);
781 spider_net_write_reg(card, SPIDER_NET_GDTDMACCNTR,
782 SPIDER_NET_DMA_TX_VALUE);
783 break;
784 }
785 if (descr == card->tx_chain.head)
786 break;
787 descr = descr->next;
788 }
789
790out:
791 mod_timer(&card->tx_timer, jiffies + SPIDER_NET_TX_TIMER);
911} 792}
912 793
913/** 794/**
@@ -915,47 +796,69 @@ spider_net_kick_tx_dma(struct spider_net_card *card,
915 * @skb: packet to send out 796 * @skb: packet to send out
916 * @netdev: interface device structure 797 * @netdev: interface device structure
917 * 798 *
918 * returns 0 on success, <0 on failure 799 * returns 0 on success, !0 on failure
919 */ 800 */
920static int 801static int
921spider_net_xmit(struct sk_buff *skb, struct net_device *netdev) 802spider_net_xmit(struct sk_buff *skb, struct net_device *netdev)
922{ 803{
923 struct spider_net_card *card = netdev_priv(netdev); 804 struct spider_net_card *card = netdev_priv(netdev);
924 struct spider_net_descr *descr; 805 struct spider_net_descr_chain *chain = &card->tx_chain;
806 struct spider_net_descr *descr = chain->head;
807 unsigned long flags;
925 int result; 808 int result;
926 809
810 spin_lock_irqsave(&chain->lock, flags);
811
927 spider_net_release_tx_chain(card, 0); 812 spider_net_release_tx_chain(card, 0);
928 813
929 descr = spider_net_get_next_tx_descr(card); 814 if (chain->head->next == chain->tail->prev) {
815 card->netdev_stats.tx_dropped++;
816 result = NETDEV_TX_LOCKED;
817 goto out;
818 }
930 819
931 if (!descr) 820 if (spider_net_get_descr_status(descr) != SPIDER_NET_DESCR_NOT_IN_USE) {
932 goto error; 821 result = NETDEV_TX_LOCKED;
822 goto out;
823 }
933 824
934 result = spider_net_prepare_tx_descr(card, descr, skb); 825 if (spider_net_prepare_tx_descr(card, skb) != 0) {
935 if (result) 826 card->netdev_stats.tx_dropped++;
936 goto error; 827 result = NETDEV_TX_BUSY;
828 goto out;
829 }
830
831 result = NETDEV_TX_OK;
937 832
833 spider_net_kick_tx_dma(card);
938 card->tx_chain.head = card->tx_chain.head->next; 834 card->tx_chain.head = card->tx_chain.head->next;
939 835
940 if (spider_net_get_descr_status(descr->prev) != 836out:
941 SPIDER_NET_DESCR_CARDOWNED) { 837 spin_unlock_irqrestore(&chain->lock, flags);
942 /* make sure the current descriptor is in memory. Then 838 netif_wake_queue(netdev);
943 * kicking it on again makes sense, if the previous is not 839 return result;
944 * card-owned anymore. Check the previous descriptor twice 840}
945 * to omit an mb() in heavy traffic cases */
946 mb();
947 if (spider_net_get_descr_status(descr->prev) !=
948 SPIDER_NET_DESCR_CARDOWNED)
949 spider_net_kick_tx_dma(card, descr);
950 }
951 841
952 mod_timer(&card->tx_timer, jiffies + SPIDER_NET_TX_TIMER); 842/**
843 * spider_net_cleanup_tx_ring - cleans up the TX ring
844 * @card: card structure
845 *
846 * spider_net_cleanup_tx_ring is called by the tx_timer (as we don't use
847 * interrupts to cleanup our TX ring) and returns sent packets to the stack
848 * by freeing them
849 */
850static void
851spider_net_cleanup_tx_ring(struct spider_net_card *card)
852{
853 unsigned long flags;
953 854
954 return NETDEV_TX_OK; 855 spin_lock_irqsave(&card->tx_chain.lock, flags);
955 856
956error: 857 if ((spider_net_release_tx_chain(card, 0) != 0) &&
957 card->netdev_stats.tx_dropped++; 858 (card->netdev->flags & IFF_UP))
958 return NETDEV_TX_BUSY; 859 spider_net_kick_tx_dma(card);
860
861 spin_unlock_irqrestore(&card->tx_chain.lock, flags);
959} 862}
960 863
961/** 864/**
@@ -1002,7 +905,7 @@ spider_net_pass_skb_up(struct spider_net_descr *descr,
1002 905
1003 /* unmap descriptor */ 906 /* unmap descriptor */
1004 pci_unmap_single(card->pdev, descr->buf_addr, SPIDER_NET_MAX_FRAME, 907 pci_unmap_single(card->pdev, descr->buf_addr, SPIDER_NET_MAX_FRAME,
1005 PCI_DMA_BIDIRECTIONAL); 908 PCI_DMA_FROMDEVICE);
1006 909
1007 /* the cases we'll throw away the packet immediately */ 910 /* the cases we'll throw away the packet immediately */
1008 if (data_error & SPIDER_NET_DESTROY_RX_FLAGS) { 911 if (data_error & SPIDER_NET_DESTROY_RX_FLAGS) {
@@ -1067,14 +970,11 @@ spider_net_pass_skb_up(struct spider_net_descr *descr,
1067static int 970static int
1068spider_net_decode_one_descr(struct spider_net_card *card, int napi) 971spider_net_decode_one_descr(struct spider_net_card *card, int napi)
1069{ 972{
1070 enum spider_net_descr_status status; 973 struct spider_net_descr_chain *chain = &card->rx_chain;
1071 struct spider_net_descr *descr; 974 struct spider_net_descr *descr = chain->tail;
1072 struct spider_net_descr_chain *chain; 975 int status;
1073 int result; 976 int result;
1074 977
1075 chain = &card->rx_chain;
1076 descr = chain->tail;
1077
1078 status = spider_net_get_descr_status(descr); 978 status = spider_net_get_descr_status(descr);
1079 979
1080 if (status == SPIDER_NET_DESCR_CARDOWNED) { 980 if (status == SPIDER_NET_DESCR_CARDOWNED) {
@@ -1103,7 +1003,7 @@ spider_net_decode_one_descr(struct spider_net_card *card, int napi)
1103 card->netdev->name, status); 1003 card->netdev->name, status);
1104 card->netdev_stats.rx_dropped++; 1004 card->netdev_stats.rx_dropped++;
1105 pci_unmap_single(card->pdev, descr->buf_addr, 1005 pci_unmap_single(card->pdev, descr->buf_addr,
1106 SPIDER_NET_MAX_FRAME, PCI_DMA_BIDIRECTIONAL); 1006 SPIDER_NET_MAX_FRAME, PCI_DMA_FROMDEVICE);
1107 dev_kfree_skb_irq(descr->skb); 1007 dev_kfree_skb_irq(descr->skb);
1108 goto refill; 1008 goto refill;
1109 } 1009 }
@@ -1119,7 +1019,7 @@ spider_net_decode_one_descr(struct spider_net_card *card, int napi)
1119 /* ok, we've got a packet in descr */ 1019 /* ok, we've got a packet in descr */
1120 result = spider_net_pass_skb_up(descr, card, napi); 1020 result = spider_net_pass_skb_up(descr, card, napi);
1121refill: 1021refill:
1122 spider_net_set_descr_status(descr, SPIDER_NET_DESCR_NOT_IN_USE); 1022 descr->dmac_cmd_status = SPIDER_NET_DESCR_NOT_IN_USE;
1123 /* change the descriptor state: */ 1023 /* change the descriptor state: */
1124 if (!napi) 1024 if (!napi)
1125 spider_net_refill_rx_chain(card); 1025 spider_net_refill_rx_chain(card);
@@ -1291,21 +1191,6 @@ spider_net_set_mac(struct net_device *netdev, void *p)
1291} 1191}
1292 1192
1293/** 1193/**
1294 * spider_net_enable_txdmac - enables a TX DMA controller
1295 * @card: card structure
1296 *
1297 * spider_net_enable_txdmac enables the TX DMA controller by setting the
1298 * descriptor chain tail address
1299 */
1300static void
1301spider_net_enable_txdmac(struct spider_net_card *card)
1302{
1303 /* assume chain is aligned correctly */
1304 spider_net_write_reg(card, SPIDER_NET_GDTDCHA,
1305 card->tx_chain.tail->bus_addr);
1306}
1307
1308/**
1309 * spider_net_handle_rxram_full - cleans up RX ring upon RX RAM full interrupt 1194 * spider_net_handle_rxram_full - cleans up RX ring upon RX RAM full interrupt
1310 * @card: card structure 1195 * @card: card structure
1311 * 1196 *
@@ -1653,7 +1538,6 @@ spider_net_enable_card(struct spider_net_card *card)
1653 { SPIDER_NET_GMRWOLCTRL, 0 }, 1538 { SPIDER_NET_GMRWOLCTRL, 0 },
1654 { SPIDER_NET_GTESTMD, 0x10000000 }, 1539 { SPIDER_NET_GTESTMD, 0x10000000 },
1655 { SPIDER_NET_GTTQMSK, 0x00400040 }, 1540 { SPIDER_NET_GTTQMSK, 0x00400040 },
1656 { SPIDER_NET_GTESTMD, 0 },
1657 1541
1658 { SPIDER_NET_GMACINTEN, 0 }, 1542 { SPIDER_NET_GMACINTEN, 0 },
1659 1543
@@ -1692,9 +1576,6 @@ spider_net_enable_card(struct spider_net_card *card)
1692 1576
1693 spider_net_write_reg(card, SPIDER_NET_GRXDMAEN, SPIDER_NET_WOL_VALUE); 1577 spider_net_write_reg(card, SPIDER_NET_GRXDMAEN, SPIDER_NET_WOL_VALUE);
1694 1578
1695 /* set chain tail adress for TX chain */
1696 spider_net_enable_txdmac(card);
1697
1698 spider_net_write_reg(card, SPIDER_NET_GMACLENLMT, 1579 spider_net_write_reg(card, SPIDER_NET_GMACLENLMT,
1699 SPIDER_NET_LENLMT_VALUE); 1580 SPIDER_NET_LENLMT_VALUE);
1700 spider_net_write_reg(card, SPIDER_NET_GMACMODE, 1581 spider_net_write_reg(card, SPIDER_NET_GMACMODE,
@@ -1709,6 +1590,9 @@ spider_net_enable_card(struct spider_net_card *card)
1709 SPIDER_NET_INT1_MASK_VALUE); 1590 SPIDER_NET_INT1_MASK_VALUE);
1710 spider_net_write_reg(card, SPIDER_NET_GHIINT2MSK, 1591 spider_net_write_reg(card, SPIDER_NET_GHIINT2MSK,
1711 SPIDER_NET_INT2_MASK_VALUE); 1592 SPIDER_NET_INT2_MASK_VALUE);
1593
1594 spider_net_write_reg(card, SPIDER_NET_GDTDMACCNTR,
1595 SPIDER_NET_GDTDCEIDIS);
1712} 1596}
1713 1597
1714/** 1598/**
@@ -1728,10 +1612,12 @@ spider_net_open(struct net_device *netdev)
1728 1612
1729 result = -ENOMEM; 1613 result = -ENOMEM;
1730 if (spider_net_init_chain(card, &card->tx_chain, 1614 if (spider_net_init_chain(card, &card->tx_chain,
1731 card->descr, tx_descriptors)) 1615 card->descr,
1616 PCI_DMA_TODEVICE, tx_descriptors))
1732 goto alloc_tx_failed; 1617 goto alloc_tx_failed;
1733 if (spider_net_init_chain(card, &card->rx_chain, 1618 if (spider_net_init_chain(card, &card->rx_chain,
1734 card->descr + tx_descriptors, rx_descriptors)) 1619 card->descr + tx_descriptors,
1620 PCI_DMA_FROMDEVICE, rx_descriptors))
1735 goto alloc_rx_failed; 1621 goto alloc_rx_failed;
1736 1622
1737 /* allocate rx skbs */ 1623 /* allocate rx skbs */
@@ -1938,7 +1824,7 @@ spider_net_workaround_rxramfull(struct spider_net_card *card)
1938 /* empty sequencer data */ 1824 /* empty sequencer data */
1939 for (sequencer = 0; sequencer < SPIDER_NET_FIRMWARE_SEQS; 1825 for (sequencer = 0; sequencer < SPIDER_NET_FIRMWARE_SEQS;
1940 sequencer++) { 1826 sequencer++) {
1941 spider_net_write_reg(card, SPIDER_NET_GSnPRGDAT + 1827 spider_net_write_reg(card, SPIDER_NET_GSnPRGADR +
1942 sequencer * 8, 0x0); 1828 sequencer * 8, 0x0);
1943 for (i = 0; i < SPIDER_NET_FIRMWARE_SEQWORDS; i++) { 1829 for (i = 0; i < SPIDER_NET_FIRMWARE_SEQWORDS; i++) {
1944 spider_net_write_reg(card, SPIDER_NET_GSnPRGDAT + 1830 spider_net_write_reg(card, SPIDER_NET_GSnPRGDAT +
@@ -1955,6 +1841,49 @@ spider_net_workaround_rxramfull(struct spider_net_card *card)
1955} 1841}
1956 1842
1957/** 1843/**
1844 * spider_net_stop - called upon ifconfig down
1845 * @netdev: interface device structure
1846 *
1847 * always returns 0
1848 */
1849int
1850spider_net_stop(struct net_device *netdev)
1851{
1852 struct spider_net_card *card = netdev_priv(netdev);
1853
1854 tasklet_kill(&card->rxram_full_tl);
1855 netif_poll_disable(netdev);
1856 netif_carrier_off(netdev);
1857 netif_stop_queue(netdev);
1858 del_timer_sync(&card->tx_timer);
1859
1860 /* disable/mask all interrupts */
1861 spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK, 0);
1862 spider_net_write_reg(card, SPIDER_NET_GHIINT1MSK, 0);
1863 spider_net_write_reg(card, SPIDER_NET_GHIINT2MSK, 0);
1864
1865 /* free_irq(netdev->irq, netdev);*/
1866 free_irq(to_pci_dev(netdev->class_dev.dev)->irq, netdev);
1867
1868 spider_net_write_reg(card, SPIDER_NET_GDTDMACCNTR,
1869 SPIDER_NET_DMA_TX_FEND_VALUE);
1870
1871 /* turn off DMA, force end */
1872 spider_net_disable_rxdmac(card);
1873
1874 /* release chains */
1875 if (spin_trylock(&card->tx_chain.lock)) {
1876 spider_net_release_tx_chain(card, 1);
1877 spin_unlock(&card->tx_chain.lock);
1878 }
1879
1880 spider_net_free_chain(card, &card->tx_chain);
1881 spider_net_free_chain(card, &card->rx_chain);
1882
1883 return 0;
1884}
1885
1886/**
1958 * spider_net_tx_timeout_task - task scheduled by the watchdog timeout 1887 * spider_net_tx_timeout_task - task scheduled by the watchdog timeout
1959 * function (to be called not under interrupt status) 1888 * function (to be called not under interrupt status)
1960 * @data: data, is interface device structure 1889 * @data: data, is interface device structure
@@ -1982,7 +1911,7 @@ spider_net_tx_timeout_task(void *data)
1982 goto out; 1911 goto out;
1983 1912
1984 spider_net_open(netdev); 1913 spider_net_open(netdev);
1985 spider_net_kick_tx_dma(card, card->tx_chain.head); 1914 spider_net_kick_tx_dma(card);
1986 netif_device_attach(netdev); 1915 netif_device_attach(netdev);
1987 1916
1988out: 1917out:
@@ -2065,7 +1994,6 @@ spider_net_setup_netdev(struct spider_net_card *card)
2065 1994
2066 pci_set_drvdata(card->pdev, netdev); 1995 pci_set_drvdata(card->pdev, netdev);
2067 1996
2068 atomic_set(&card->tx_chain_release,0);
2069 card->rxram_full_tl.data = (unsigned long) card; 1997 card->rxram_full_tl.data = (unsigned long) card;
2070 card->rxram_full_tl.func = 1998 card->rxram_full_tl.func =
2071 (void (*)(unsigned long)) spider_net_handle_rxram_full; 1999 (void (*)(unsigned long)) spider_net_handle_rxram_full;
@@ -2079,7 +2007,7 @@ spider_net_setup_netdev(struct spider_net_card *card)
2079 2007
2080 spider_net_setup_netdev_ops(netdev); 2008 spider_net_setup_netdev_ops(netdev);
2081 2009
2082 netdev->features = NETIF_F_HW_CSUM; 2010 netdev->features = NETIF_F_HW_CSUM | NETIF_F_LLTX;
2083 /* some time: NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | 2011 /* some time: NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2084 * NETIF_F_HW_VLAN_FILTER */ 2012 * NETIF_F_HW_VLAN_FILTER */
2085 2013
diff --git a/drivers/net/spider_net.h b/drivers/net/spider_net.h
index 3b8d951cf73c..f6dcf180ae3d 100644
--- a/drivers/net/spider_net.h
+++ b/drivers/net/spider_net.h
@@ -208,7 +208,10 @@ extern char spider_net_driver_name[];
208#define SPIDER_NET_DMA_RX_VALUE 0x80000000 208#define SPIDER_NET_DMA_RX_VALUE 0x80000000
209#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003 209#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
210/* to set TX_DMA_EN */ 210/* to set TX_DMA_EN */
211#define SPIDER_NET_DMA_TX_VALUE 0x80000000 211#define SPIDER_NET_TX_DMA_EN 0x80000000
212#define SPIDER_NET_GDTDCEIDIS 0x00000002
213#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \
214 SPIDER_NET_GDTDCEIDIS
212#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003 215#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
213 216
214/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */ 217/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
@@ -329,55 +332,23 @@ enum spider_net_int2_status {
329 (~SPIDER_NET_TXINT) & \ 332 (~SPIDER_NET_TXINT) & \
330 (~SPIDER_NET_RXINT) ) 333 (~SPIDER_NET_RXINT) )
331 334
332#define SPIDER_NET_GPREXEC 0x80000000 335#define SPIDER_NET_GPREXEC 0x80000000
333#define SPIDER_NET_GPRDAT_MASK 0x0000ffff 336#define SPIDER_NET_GPRDAT_MASK 0x0000ffff
334 337
335/* descriptor bits 338#define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000
336 * 339#define SPIDER_NET_DMAC_NOCS 0x00040000
337 * 1010 descriptor ready 340#define SPIDER_NET_DMAC_TCP 0x00020000
338 * 0 descr in middle of chain 341#define SPIDER_NET_DMAC_UDP 0x00030000
339 * 000 fixed to 0 342#define SPIDER_NET_TXDCEST 0x08000000
340 * 343
341 * 0 no interrupt on completion 344#define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000
342 * 000 fixed to 0 345#define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */
343 * 1 no ipsec processing 346#define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */
344 * 1 last descriptor for this frame 347#define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */
345 * 00 no checksum 348#define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */
346 * 10 tcp checksum 349#define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */
347 * 11 udp checksum 350#define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */
348 * 351#define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000
349 * 00 fixed to 0
350 * 0 fixed to 0
351 * 0 no interrupt on response errors
352 * 0 no interrupt on invalid descr
353 * 0 no interrupt on dma process termination
354 * 0 no interrupt on descr chain end
355 * 0 no interrupt on descr complete
356 *
357 * 000 fixed to 0
358 * 0 response error interrupt status
359 * 0 invalid descr status
360 * 0 dma termination status
361 * 0 descr chain end status
362 * 0 descr complete status */
363#define SPIDER_NET_DMAC_CMDSTAT_NOCS 0xa00c0000
364#define SPIDER_NET_DMAC_CMDSTAT_TCPCS 0xa00e0000
365#define SPIDER_NET_DMAC_CMDSTAT_UDPCS 0xa00f0000
366#define SPIDER_NET_DESCR_IND_PROC_SHIFT 28
367#define SPIDER_NET_DESCR_IND_PROC_MASKO 0x0fffffff
368
369/* descr ready, descr is in middle of chain, get interrupt on completion */
370#define SPIDER_NET_DMAC_RX_CARDOWNED 0xa0800000
371
372enum spider_net_descr_status {
373 SPIDER_NET_DESCR_COMPLETE = 0x00, /* used in rx and tx */
374 SPIDER_NET_DESCR_RESPONSE_ERROR = 0x01, /* used in rx and tx */
375 SPIDER_NET_DESCR_PROTECTION_ERROR = 0x02, /* used in rx and tx */
376 SPIDER_NET_DESCR_FRAME_END = 0x04, /* used in rx */
377 SPIDER_NET_DESCR_FORCE_END = 0x05, /* used in rx and tx */
378 SPIDER_NET_DESCR_CARDOWNED = 0x0a, /* used in rx and tx */
379 SPIDER_NET_DESCR_NOT_IN_USE /* any other value */
380};
381 352
382struct spider_net_descr { 353struct spider_net_descr {
383 /* as defined by the hardware */ 354 /* as defined by the hardware */
@@ -398,7 +369,7 @@ struct spider_net_descr {
398} __attribute__((aligned(32))); 369} __attribute__((aligned(32)));
399 370
400struct spider_net_descr_chain { 371struct spider_net_descr_chain {
401 /* we walk from tail to head */ 372 spinlock_t lock;
402 struct spider_net_descr *head; 373 struct spider_net_descr *head;
403 struct spider_net_descr *tail; 374 struct spider_net_descr *tail;
404}; 375};
@@ -453,8 +424,6 @@ struct spider_net_card {
453 424
454 struct spider_net_descr_chain tx_chain; 425 struct spider_net_descr_chain tx_chain;
455 struct spider_net_descr_chain rx_chain; 426 struct spider_net_descr_chain rx_chain;
456 atomic_t rx_chain_refill;
457 atomic_t tx_chain_release;
458 427
459 struct net_device_stats netdev_stats; 428 struct net_device_stats netdev_stats;
460 429
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index ed1f59901ff4..c0a62b00ffc8 100644
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -22,129 +22,13 @@
22 22
23 Support and updates available at 23 Support and updates available at
24 http://www.scyld.com/network/starfire.html 24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
25 26
26 -----------------------------------------------------------
27
28 Linux kernel-specific changes:
29
30 LK1.1.1 (jgarzik):
31 - Use PCI driver interface
32 - Fix MOD_xxx races
33 - softnet fixups
34
35 LK1.1.2 (jgarzik):
36 - Merge Becker version 0.15
37
38 LK1.1.3 (Andrew Morton)
39 - Timer cleanups
40
41 LK1.1.4 (jgarzik):
42 - Merge Becker version 1.03
43
44 LK1.2.1 (Ion Badulescu <ionut@cs.columbia.edu>)
45 - Support hardware Rx/Tx checksumming
46 - Use the GFP firmware taken from Adaptec's Netware driver
47
48 LK1.2.2 (Ion Badulescu)
49 - Backported to 2.2.x
50
51 LK1.2.3 (Ion Badulescu)
52 - Fix the flaky mdio interface
53 - More compat clean-ups
54
55 LK1.2.4 (Ion Badulescu)
56 - More 2.2.x initialization fixes
57
58 LK1.2.5 (Ion Badulescu)
59 - Several fixes from Manfred Spraul
60
61 LK1.2.6 (Ion Badulescu)
62 - Fixed ifup/ifdown/ifup problem in 2.4.x
63
64 LK1.2.7 (Ion Badulescu)
65 - Removed unused code
66 - Made more functions static and __init
67
68 LK1.2.8 (Ion Badulescu)
69 - Quell bogus error messages, inform about the Tx threshold
70 - Removed #ifdef CONFIG_PCI, this driver is PCI only
71
72 LK1.2.9 (Ion Badulescu)
73 - Merged Jeff Garzik's changes from 2.4.4-pre5
74 - Added 2.2.x compatibility stuff required by the above changes
75
76 LK1.2.9a (Ion Badulescu)
77 - More updates from Jeff Garzik
78
79 LK1.3.0 (Ion Badulescu)
80 - Merged zerocopy support
81
82 LK1.3.1 (Ion Badulescu)
83 - Added ethtool support
84 - Added GPIO (media change) interrupt support
85
86 LK1.3.2 (Ion Badulescu)
87 - Fixed 2.2.x compatibility issues introduced in 1.3.1
88 - Fixed ethtool ioctl returning uninitialized memory
89
90 LK1.3.3 (Ion Badulescu)
91 - Initialize the TxMode register properly
92 - Don't dereference dev->priv after freeing it
93
94 LK1.3.4 (Ion Badulescu)
95 - Fixed initialization timing problems
96 - Fixed interrupt mask definitions
97
98 LK1.3.5 (jgarzik)
99 - ethtool NWAY_RST, GLINK, [GS]MSGLVL support
100
101 LK1.3.6:
102 - Sparc64 support and fixes (Ion Badulescu)
103 - Better stats and error handling (Ion Badulescu)
104 - Use new pci_set_mwi() PCI API function (jgarzik)
105
106 LK1.3.7 (Ion Badulescu)
107 - minimal implementation of tx_timeout()
108 - correctly shutdown the Rx/Tx engines in netdev_close()
109 - added calls to netif_carrier_on/off
110 (patch from Stefan Rompf <srompf@isg.de>)
111 - VLAN support
112
113 LK1.3.8 (Ion Badulescu)
114 - adjust DMA burst size on sparc64
115 - 64-bit support
116 - reworked zerocopy support for 64-bit buffers
117 - working and usable interrupt mitigation/latency
118 - reduced Tx interrupt frequency for lower interrupt overhead
119
120 LK1.3.9 (Ion Badulescu)
121 - bugfix for mcast filter
122 - enable the right kind of Tx interrupts (TxDMADone, not TxDone)
123
124 LK1.4.0 (Ion Badulescu)
125 - NAPI support
126
127 LK1.4.1 (Ion Badulescu)
128 - flush PCI posting buffers after disabling Rx interrupts
129 - put the chip to a D3 slumber on driver unload
130 - added config option to enable/disable NAPI
131
132 LK1.4.2 (Ion Badulescu)
133 - finally added firmware (GPL'ed by Adaptec)
134 - removed compatibility code for 2.2.x
135
136 LK1.4.2.1 (Ion Badulescu)
137 - fixed 32/64 bit issues on i386 + CONFIG_HIGHMEM
138 - added 32-bit padding to outgoing skb's, removed previous workaround
139
140TODO: - fix forced speed/duplexing code (broken a long time ago, when
141 somebody converted the driver to use the generic MII code)
142 - fix VLAN support
143*/ 27*/
144 28
145#define DRV_NAME "starfire" 29#define DRV_NAME "starfire"
146#define DRV_VERSION "1.03+LK1.4.2.1" 30#define DRV_VERSION "2.0"
147#define DRV_RELDATE "October 3, 2005" 31#define DRV_RELDATE "June 27, 2006"
148 32
149#include <linux/module.h> 33#include <linux/module.h>
150#include <linux/kernel.h> 34#include <linux/kernel.h>
@@ -846,7 +730,6 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
846 goto err_out_free_netdev; 730 goto err_out_free_netdev;
847 } 731 }
848 732
849 /* ioremap is borken in Linux-2.2.x/sparc64 */
850 base = ioremap(ioaddr, io_size); 733 base = ioremap(ioaddr, io_size);
851 if (!base) { 734 if (!base) {
852 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n", 735 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
diff --git a/drivers/net/sundance.c b/drivers/net/sundance.c
index 643fceae3db5..ac17377b3e9f 100644
--- a/drivers/net/sundance.c
+++ b/drivers/net/sundance.c
@@ -16,91 +16,13 @@
16 16
17 Support and updates available at 17 Support and updates available at
18 http://www.scyld.com/network/sundance.html 18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik]
19 20
20
21 Version LK1.01a (jgarzik):
22 - Replace some MII-related magic numbers with constants
23
24 Version LK1.02 (D-Link):
25 - Add new board to PCI ID list
26 - Fix multicast bug
27
28 Version LK1.03 (D-Link):
29 - New Rx scheme, reduce Rx congestion
30 - Option to disable flow control
31
32 Version LK1.04 (D-Link):
33 - Tx timeout recovery
34 - More support for ethtool.
35
36 Version LK1.04a:
37 - Remove unused/constant members from struct pci_id_info
38 (which then allows removal of 'drv_flags' from private struct)
39 (jgarzik)
40 - If no phy is found, fail to load that board (jgarzik)
41 - Always start phy id scan at id 1 to avoid problems (Donald Becker)
42 - Autodetect where mii_preable_required is needed,
43 default to not needed. (Donald Becker)
44
45 Version LK1.04b:
46 - Remove mii_preamble_required module parameter (Donald Becker)
47 - Add per-interface mii_preamble_required (setting is autodetected)
48 (Donald Becker)
49 - Remove unnecessary cast from void pointer (jgarzik)
50 - Re-align comments in private struct (jgarzik)
51
52 Version LK1.04c (jgarzik):
53 - Support bitmapped message levels (NETIF_MSG_xxx), and the
54 two ethtool ioctls that get/set them
55 - Don't hand-code MII ethtool support, use standard API/lib
56
57 Version LK1.04d:
58 - Merge from Donald Becker's sundance.c: (Jason Lunz)
59 * proper support for variably-sized MTUs
60 * default to PIO, to fix chip bugs
61 - Add missing unregister_netdev (Jason Lunz)
62 - Add CONFIG_SUNDANCE_MMIO config option (jgarzik)
63 - Better rx buf size calculation (Donald Becker)
64
65 Version LK1.05 (D-Link):
66 - Fix DFE-580TX packet drop issue (for DL10050C)
67 - Fix reset_tx logic
68
69 Version LK1.06 (D-Link):
70 - Fix crash while unloading driver
71
72 Versin LK1.06b (D-Link):
73 - New tx scheme, adaptive tx_coalesce
74
75 Version LK1.07 (D-Link):
76 - Fix tx bugs in big-endian machines
77 - Remove unused max_interrupt_work module parameter, the new
78 NAPI-like rx scheme doesn't need it.
79 - Remove redundancy get_stats() in intr_handler(), those
80 I/O access could affect performance in ARM-based system
81 - Add Linux software VLAN support
82
83 Version LK1.08 (Philippe De Muyter phdm@macqel.be):
84 - Fix bug of custom mac address
85 (StationAddr register only accept word write)
86
87 Version LK1.09 (D-Link):
88 - Fix the flowctrl bug.
89 - Set Pause bit in MII ANAR if flow control enabled.
90
91 Version LK1.09a (ICPlus):
92 - Add the delay time in reading the contents of EEPROM
93
94 Version LK1.10 (Philippe De Muyter phdm@macqel.be):
95 - Make 'unblock interface after Tx underrun' work
96
97 Version LK1.11 (Pedro Alejandro Lopez-Valencia palopezv at gmail.com):
98 - Add support for IC Plus Corporation IP100A chipset
99*/ 21*/
100 22
101#define DRV_NAME "sundance" 23#define DRV_NAME "sundance"
102#define DRV_VERSION "1.01+LK1.11" 24#define DRV_VERSION "1.1"
103#define DRV_RELDATE "14-Jun-2006" 25#define DRV_RELDATE "27-Jun-2006"
104 26
105 27
106/* The user-configurable values. 28/* The user-configurable values.
@@ -282,15 +204,15 @@ IVc. Errata
282#define USE_IO_OPS 1 204#define USE_IO_OPS 1
283#endif 205#endif
284 206
285static struct pci_device_id sundance_pci_tbl[] = { 207static const struct pci_device_id sundance_pci_tbl[] = {
286 {0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0}, 208 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
287 {0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1}, 209 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
288 {0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2}, 210 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
289 {0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3}, 211 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
290 {0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, 212 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
291 {0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, 213 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
292 {0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, 214 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
293 {0,} 215 { }
294}; 216};
295MODULE_DEVICE_TABLE(pci, sundance_pci_tbl); 217MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
296 218
@@ -301,7 +223,7 @@ enum {
301struct pci_id_info { 223struct pci_id_info {
302 const char *name; 224 const char *name;
303}; 225};
304static const struct pci_id_info pci_id_tbl[] = { 226static const struct pci_id_info pci_id_tbl[] __devinitdata = {
305 {"D-Link DFE-550TX FAST Ethernet Adapter"}, 227 {"D-Link DFE-550TX FAST Ethernet Adapter"},
306 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"}, 228 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
307 {"D-Link DFE-580TX 4 port Server Adapter"}, 229 {"D-Link DFE-580TX 4 port Server Adapter"},
@@ -309,7 +231,7 @@ static const struct pci_id_info pci_id_tbl[] = {
309 {"D-Link DL10050-based FAST Ethernet Adapter"}, 231 {"D-Link DL10050-based FAST Ethernet Adapter"},
310 {"Sundance Technology Alta"}, 232 {"Sundance Technology Alta"},
311 {"IC Plus Corporation IP100A FAST Ethernet Adapter"}, 233 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
312 {NULL,}, /* 0 terminated list. */ 234 { } /* terminate list. */
313}; 235};
314 236
315/* This driver was written to use PCI memory space, however x86-oriented 237/* This driver was written to use PCI memory space, however x86-oriented
diff --git a/drivers/net/sunhme.c b/drivers/net/sunhme.c
index 8673fd4c08c7..c6f5bc3c042f 100644
--- a/drivers/net/sunhme.c
+++ b/drivers/net/sunhme.c
@@ -3255,12 +3255,7 @@ static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
3255} 3255}
3256 3256
3257static struct pci_device_id happymeal_pci_ids[] = { 3257static struct pci_device_id happymeal_pci_ids[] = {
3258 { 3258 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3259 .vendor = PCI_VENDOR_ID_SUN,
3260 .device = PCI_DEVICE_ID_SUN_HAPPYMEAL,
3261 .subvendor = PCI_ANY_ID,
3262 .subdevice = PCI_ANY_ID,
3263 },
3264 { } /* Terminating entry */ 3259 { } /* Terminating entry */
3265}; 3260};
3266 3261
@@ -3275,7 +3270,7 @@ static struct pci_driver hme_pci_driver = {
3275 3270
3276static int __init happy_meal_pci_init(void) 3271static int __init happy_meal_pci_init(void)
3277{ 3272{
3278 return pci_module_init(&hme_pci_driver); 3273 return pci_register_driver(&hme_pci_driver);
3279} 3274}
3280 3275
3281static void happy_meal_pci_exit(void) 3276static void happy_meal_pci_exit(void)
diff --git a/drivers/net/sunlance.c b/drivers/net/sunlance.c
index 1ef9fd39a79a..0e3fdf7c6dd3 100644
--- a/drivers/net/sunlance.c
+++ b/drivers/net/sunlance.c
@@ -1537,7 +1537,7 @@ static int __init sparc_lance_init(void)
1537{ 1537{
1538 if ((idprom->id_machtype == (SM_SUN4|SM_4_330)) || 1538 if ((idprom->id_machtype == (SM_SUN4|SM_4_330)) ||
1539 (idprom->id_machtype == (SM_SUN4|SM_4_470))) { 1539 (idprom->id_machtype == (SM_SUN4|SM_4_470))) {
1540 memset(&sun4_sdev, 0, sizeof(sdev)); 1540 memset(&sun4_sdev, 0, sizeof(struct sbus_dev));
1541 sun4_sdev.reg_addrs[0].phys_addr = sun4_eth_physaddr; 1541 sun4_sdev.reg_addrs[0].phys_addr = sun4_eth_physaddr;
1542 sun4_sdev.irqs[0] = 6; 1542 sun4_sdev.irqs[0] = 6;
1543 return sparc_lance_probe_one(&sun4_sdev, NULL, NULL); 1543 return sparc_lance_probe_one(&sun4_sdev, NULL, NULL);
@@ -1547,16 +1547,16 @@ static int __init sparc_lance_init(void)
1547 1547
1548static int __exit sunlance_sun4_remove(void) 1548static int __exit sunlance_sun4_remove(void)
1549{ 1549{
1550 struct lance_private *lp = dev_get_drvdata(&sun4_sdev->dev); 1550 struct lance_private *lp = dev_get_drvdata(&sun4_sdev.ofdev.dev);
1551 struct net_device *net_dev = lp->dev; 1551 struct net_device *net_dev = lp->dev;
1552 1552
1553 unregister_netdevice(net_dev); 1553 unregister_netdevice(net_dev);
1554 1554
1555 lance_free_hwresources(root_lance_dev); 1555 lance_free_hwresources(lp);
1556 1556
1557 free_netdev(net_dev); 1557 free_netdev(net_dev);
1558 1558
1559 dev_set_drvdata(&sun4_sdev->dev, NULL); 1559 dev_set_drvdata(&sun4_sdev.ofdev.dev, NULL);
1560 1560
1561 return 0; 1561 return 0;
1562} 1562}
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index f645921aff8b..6f97962dd06b 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.62" 71#define DRV_MODULE_VERSION "3.64"
72#define DRV_MODULE_RELDATE "June 30, 2006" 72#define DRV_MODULE_RELDATE "July 31, 2006"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -3097,7 +3097,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3097 * Callers depend upon this behavior and assume that 3097 * Callers depend upon this behavior and assume that
3098 * we leave everything unchanged if we fail. 3098 * we leave everything unchanged if we fail.
3099 */ 3099 */
3100 skb = dev_alloc_skb(skb_size); 3100 skb = netdev_alloc_skb(tp->dev, skb_size);
3101 if (skb == NULL) 3101 if (skb == NULL)
3102 return -ENOMEM; 3102 return -ENOMEM;
3103 3103
@@ -3270,7 +3270,7 @@ static int tg3_rx(struct tg3 *tp, int budget)
3270 tg3_recycle_rx(tp, opaque_key, 3270 tg3_recycle_rx(tp, opaque_key,
3271 desc_idx, *post_ptr); 3271 desc_idx, *post_ptr);
3272 3272
3273 copy_skb = dev_alloc_skb(len + 2); 3273 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3274 if (copy_skb == NULL) 3274 if (copy_skb == NULL)
3275 goto drop_it_no_recycle; 3275 goto drop_it_no_recycle;
3276 3276
@@ -3590,6 +3590,28 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3590static int tg3_init_hw(struct tg3 *, int); 3590static int tg3_init_hw(struct tg3 *, int);
3591static int tg3_halt(struct tg3 *, int, int); 3591static int tg3_halt(struct tg3 *, int, int);
3592 3592
3593/* Restart hardware after configuration changes, self-test, etc.
3594 * Invoked with tp->lock held.
3595 */
3596static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3597{
3598 int err;
3599
3600 err = tg3_init_hw(tp, reset_phy);
3601 if (err) {
3602 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3603 "aborting.\n", tp->dev->name);
3604 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3605 tg3_full_unlock(tp);
3606 del_timer_sync(&tp->timer);
3607 tp->irq_sync = 0;
3608 netif_poll_enable(tp->dev);
3609 dev_close(tp->dev);
3610 tg3_full_lock(tp, 0);
3611 }
3612 return err;
3613}
3614
3593#ifdef CONFIG_NET_POLL_CONTROLLER 3615#ifdef CONFIG_NET_POLL_CONTROLLER
3594static void tg3_poll_controller(struct net_device *dev) 3616static void tg3_poll_controller(struct net_device *dev)
3595{ 3617{
@@ -3630,13 +3652,15 @@ static void tg3_reset_task(void *_data)
3630 } 3652 }
3631 3653
3632 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); 3654 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3633 tg3_init_hw(tp, 1); 3655 if (tg3_init_hw(tp, 1))
3656 goto out;
3634 3657
3635 tg3_netif_start(tp); 3658 tg3_netif_start(tp);
3636 3659
3637 if (restart_timer) 3660 if (restart_timer)
3638 mod_timer(&tp->timer, jiffies + 1); 3661 mod_timer(&tp->timer, jiffies + 1);
3639 3662
3663out:
3640 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK; 3664 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3641 3665
3642 tg3_full_unlock(tp); 3666 tg3_full_unlock(tp);
@@ -4124,6 +4148,7 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4124static int tg3_change_mtu(struct net_device *dev, int new_mtu) 4148static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4125{ 4149{
4126 struct tg3 *tp = netdev_priv(dev); 4150 struct tg3 *tp = netdev_priv(dev);
4151 int err;
4127 4152
4128 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) 4153 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4129 return -EINVAL; 4154 return -EINVAL;
@@ -4144,13 +4169,14 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4144 4169
4145 tg3_set_mtu(dev, tp, new_mtu); 4170 tg3_set_mtu(dev, tp, new_mtu);
4146 4171
4147 tg3_init_hw(tp, 0); 4172 err = tg3_restart_hw(tp, 0);
4148 4173
4149 tg3_netif_start(tp); 4174 if (!err)
4175 tg3_netif_start(tp);
4150 4176
4151 tg3_full_unlock(tp); 4177 tg3_full_unlock(tp);
4152 4178
4153 return 0; 4179 return err;
4154} 4180}
4155 4181
4156/* Free up pending packets in all rx/tx rings. 4182/* Free up pending packets in all rx/tx rings.
@@ -4232,7 +4258,7 @@ static void tg3_free_rings(struct tg3 *tp)
4232 * end up in the driver. tp->{tx,}lock are held and thus 4258 * end up in the driver. tp->{tx,}lock are held and thus
4233 * we may not sleep. 4259 * we may not sleep.
4234 */ 4260 */
4235static void tg3_init_rings(struct tg3 *tp) 4261static int tg3_init_rings(struct tg3 *tp)
4236{ 4262{
4237 u32 i; 4263 u32 i;
4238 4264
@@ -4281,18 +4307,38 @@ static void tg3_init_rings(struct tg3 *tp)
4281 4307
4282 /* Now allocate fresh SKBs for each rx ring. */ 4308 /* Now allocate fresh SKBs for each rx ring. */
4283 for (i = 0; i < tp->rx_pending; i++) { 4309 for (i = 0; i < tp->rx_pending; i++) {
4284 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, 4310 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4285 -1, i) < 0) 4311 printk(KERN_WARNING PFX
4312 "%s: Using a smaller RX standard ring, "
4313 "only %d out of %d buffers were allocated "
4314 "successfully.\n",
4315 tp->dev->name, i, tp->rx_pending);
4316 if (i == 0)
4317 return -ENOMEM;
4318 tp->rx_pending = i;
4286 break; 4319 break;
4320 }
4287 } 4321 }
4288 4322
4289 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { 4323 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4290 for (i = 0; i < tp->rx_jumbo_pending; i++) { 4324 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4291 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO, 4325 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4292 -1, i) < 0) 4326 -1, i) < 0) {
4327 printk(KERN_WARNING PFX
4328 "%s: Using a smaller RX jumbo ring, "
4329 "only %d out of %d buffers were "
4330 "allocated successfully.\n",
4331 tp->dev->name, i, tp->rx_jumbo_pending);
4332 if (i == 0) {
4333 tg3_free_rings(tp);
4334 return -ENOMEM;
4335 }
4336 tp->rx_jumbo_pending = i;
4293 break; 4337 break;
4338 }
4294 } 4339 }
4295 } 4340 }
4341 return 0;
4296} 4342}
4297 4343
4298/* 4344/*
@@ -5815,6 +5861,7 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
5815{ 5861{
5816 struct tg3 *tp = netdev_priv(dev); 5862 struct tg3 *tp = netdev_priv(dev);
5817 struct sockaddr *addr = p; 5863 struct sockaddr *addr = p;
5864 int err = 0;
5818 5865
5819 if (!is_valid_ether_addr(addr->sa_data)) 5866 if (!is_valid_ether_addr(addr->sa_data))
5820 return -EINVAL; 5867 return -EINVAL;
@@ -5832,9 +5879,9 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
5832 tg3_full_lock(tp, 1); 5879 tg3_full_lock(tp, 1);
5833 5880
5834 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 5881 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5835 tg3_init_hw(tp, 0); 5882 err = tg3_restart_hw(tp, 0);
5836 5883 if (!err)
5837 tg3_netif_start(tp); 5884 tg3_netif_start(tp);
5838 tg3_full_unlock(tp); 5885 tg3_full_unlock(tp);
5839 } else { 5886 } else {
5840 spin_lock_bh(&tp->lock); 5887 spin_lock_bh(&tp->lock);
@@ -5842,7 +5889,7 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
5842 spin_unlock_bh(&tp->lock); 5889 spin_unlock_bh(&tp->lock);
5843 } 5890 }
5844 5891
5845 return 0; 5892 return err;
5846} 5893}
5847 5894
5848/* tp->lock is held. */ 5895/* tp->lock is held. */
@@ -5942,7 +5989,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5942 * can only do this after the hardware has been 5989 * can only do this after the hardware has been
5943 * successfully reset. 5990 * successfully reset.
5944 */ 5991 */
5945 tg3_init_rings(tp); 5992 err = tg3_init_rings(tp);
5993 if (err)
5994 return err;
5946 5995
5947 /* This value is determined during the probe time DMA 5996 /* This value is determined during the probe time DMA
5948 * engine test, tg3_test_dma. 5997 * engine test, tg3_test_dma.
@@ -7956,7 +8005,7 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *
7956static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 8005static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7957{ 8006{
7958 struct tg3 *tp = netdev_priv(dev); 8007 struct tg3 *tp = netdev_priv(dev);
7959 int irq_sync = 0; 8008 int irq_sync = 0, err = 0;
7960 8009
7961 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || 8010 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7962 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || 8011 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
@@ -7980,13 +8029,14 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
7980 8029
7981 if (netif_running(dev)) { 8030 if (netif_running(dev)) {
7982 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 8031 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7983 tg3_init_hw(tp, 1); 8032 err = tg3_restart_hw(tp, 1);
7984 tg3_netif_start(tp); 8033 if (!err)
8034 tg3_netif_start(tp);
7985 } 8035 }
7986 8036
7987 tg3_full_unlock(tp); 8037 tg3_full_unlock(tp);
7988 8038
7989 return 0; 8039 return err;
7990} 8040}
7991 8041
7992static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 8042static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
@@ -8001,7 +8051,7 @@ static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam
8001static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 8051static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8002{ 8052{
8003 struct tg3 *tp = netdev_priv(dev); 8053 struct tg3 *tp = netdev_priv(dev);
8004 int irq_sync = 0; 8054 int irq_sync = 0, err = 0;
8005 8055
8006 if (netif_running(dev)) { 8056 if (netif_running(dev)) {
8007 tg3_netif_stop(tp); 8057 tg3_netif_stop(tp);
@@ -8025,13 +8075,14 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
8025 8075
8026 if (netif_running(dev)) { 8076 if (netif_running(dev)) {
8027 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 8077 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8028 tg3_init_hw(tp, 1); 8078 err = tg3_restart_hw(tp, 1);
8029 tg3_netif_start(tp); 8079 if (!err)
8080 tg3_netif_start(tp);
8030 } 8081 }
8031 8082
8032 tg3_full_unlock(tp); 8083 tg3_full_unlock(tp);
8033 8084
8034 return 0; 8085 return err;
8035} 8086}
8036 8087
8037static u32 tg3_get_rx_csum(struct net_device *dev) 8088static u32 tg3_get_rx_csum(struct net_device *dev)
@@ -8567,7 +8618,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8567 err = -EIO; 8618 err = -EIO;
8568 8619
8569 tx_len = 1514; 8620 tx_len = 1514;
8570 skb = dev_alloc_skb(tx_len); 8621 skb = netdev_alloc_skb(tp->dev, tx_len);
8571 if (!skb) 8622 if (!skb)
8572 return -ENOMEM; 8623 return -ENOMEM;
8573 8624
@@ -8666,7 +8717,9 @@ static int tg3_test_loopback(struct tg3 *tp)
8666 if (!netif_running(tp->dev)) 8717 if (!netif_running(tp->dev))
8667 return TG3_LOOPBACK_FAILED; 8718 return TG3_LOOPBACK_FAILED;
8668 8719
8669 tg3_reset_hw(tp, 1); 8720 err = tg3_reset_hw(tp, 1);
8721 if (err)
8722 return TG3_LOOPBACK_FAILED;
8670 8723
8671 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) 8724 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8672 err |= TG3_MAC_LOOPBACK_FAILED; 8725 err |= TG3_MAC_LOOPBACK_FAILED;
@@ -8740,8 +8793,8 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8740 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 8793 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8741 if (netif_running(dev)) { 8794 if (netif_running(dev)) {
8742 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 8795 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8743 tg3_init_hw(tp, 1); 8796 if (!tg3_restart_hw(tp, 1))
8744 tg3_netif_start(tp); 8797 tg3_netif_start(tp);
8745 } 8798 }
8746 8799
8747 tg3_full_unlock(tp); 8800 tg3_full_unlock(tp);
@@ -10078,6 +10131,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10078 static struct pci_device_id write_reorder_chipsets[] = { 10131 static struct pci_device_id write_reorder_chipsets[] = {
10079 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 10132 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10080 PCI_DEVICE_ID_AMD_FE_GATE_700C) }, 10133 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10134 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10135 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10081 { PCI_DEVICE(PCI_VENDOR_ID_VIA, 10136 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10082 PCI_DEVICE_ID_VIA_8385_0) }, 10137 PCI_DEVICE_ID_VIA_8385_0) },
10083 { }, 10138 { },
@@ -11697,7 +11752,8 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11697 tg3_full_lock(tp, 0); 11752 tg3_full_lock(tp, 0);
11698 11753
11699 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 11754 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11700 tg3_init_hw(tp, 1); 11755 if (tg3_restart_hw(tp, 1))
11756 goto out;
11701 11757
11702 tp->timer.expires = jiffies + tp->timer_offset; 11758 tp->timer.expires = jiffies + tp->timer_offset;
11703 add_timer(&tp->timer); 11759 add_timer(&tp->timer);
@@ -11705,6 +11761,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11705 netif_device_attach(dev); 11761 netif_device_attach(dev);
11706 tg3_netif_start(tp); 11762 tg3_netif_start(tp);
11707 11763
11764out:
11708 tg3_full_unlock(tp); 11765 tg3_full_unlock(tp);
11709 } 11766 }
11710 11767
@@ -11731,16 +11788,19 @@ static int tg3_resume(struct pci_dev *pdev)
11731 tg3_full_lock(tp, 0); 11788 tg3_full_lock(tp, 0);
11732 11789
11733 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 11790 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11734 tg3_init_hw(tp, 1); 11791 err = tg3_restart_hw(tp, 1);
11792 if (err)
11793 goto out;
11735 11794
11736 tp->timer.expires = jiffies + tp->timer_offset; 11795 tp->timer.expires = jiffies + tp->timer_offset;
11737 add_timer(&tp->timer); 11796 add_timer(&tp->timer);
11738 11797
11739 tg3_netif_start(tp); 11798 tg3_netif_start(tp);
11740 11799
11800out:
11741 tg3_full_unlock(tp); 11801 tg3_full_unlock(tp);
11742 11802
11743 return 0; 11803 return err;
11744} 11804}
11745 11805
11746static struct pci_driver tg3_driver = { 11806static struct pci_driver tg3_driver = {
diff --git a/drivers/net/tulip/winbond-840.c b/drivers/net/tulip/winbond-840.c
index b4c0d101a7d7..7f414815cc62 100644
--- a/drivers/net/tulip/winbond-840.c
+++ b/drivers/net/tulip/winbond-840.c
@@ -224,24 +224,21 @@ static const struct pci_device_id w840_pci_tbl[] = {
224}; 224};
225MODULE_DEVICE_TABLE(pci, w840_pci_tbl); 225MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
226 226
227enum {
228 netdev_res_size = 128, /* size of PCI BAR resource */
229};
230
227struct pci_id_info { 231struct pci_id_info {
228 const char *name; 232 const char *name;
229 struct match_info { 233 int drv_flags; /* Driver use, intended as capability flags. */
230 int pci, pci_mask, subsystem, subsystem_mask;
231 int revision, revision_mask; /* Only 8 bits. */
232 } id;
233 int io_size; /* Needed for I/O region check or ioremap(). */
234 int drv_flags; /* Driver use, intended as capability flags. */
235}; 234};
236static struct pci_id_info pci_id_tbl[] = { 235
237 {"Winbond W89c840", /* Sometime a Level-One switch card. */ 236static const struct pci_id_info pci_id_tbl[] __devinitdata = {
238 { 0x08401050, 0xffffffff, 0x81530000, 0xffff0000 }, 237 { /* Sometime a Level-One switch card. */
239 128, CanHaveMII | HasBrokenTx | FDXOnNoMII}, 238 "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
240 {"Winbond W89c840", { 0x08401050, 0xffffffff, }, 239 { "Winbond W89c840", CanHaveMII | HasBrokenTx},
241 128, CanHaveMII | HasBrokenTx}, 240 { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
242 {"Compex RL100-ATX", { 0x201111F6, 0xffffffff,}, 241 { } /* terminate list. */
243 128, CanHaveMII | HasBrokenTx},
244 {NULL,}, /* 0 terminated list. */
245}; 242};
246 243
247/* This driver was written to use PCI memory space, however some x86 systems 244/* This driver was written to use PCI memory space, however some x86 systems
@@ -399,7 +396,7 @@ static int __devinit w840_probe1 (struct pci_dev *pdev,
399#ifdef USE_IO_OPS 396#ifdef USE_IO_OPS
400 bar = 0; 397 bar = 0;
401#endif 398#endif
402 ioaddr = pci_iomap(pdev, bar, pci_id_tbl[chip_idx].io_size); 399 ioaddr = pci_iomap(pdev, bar, netdev_res_size);
403 if (!ioaddr) 400 if (!ioaddr)
404 goto err_out_free_res; 401 goto err_out_free_res;
405 402
diff --git a/drivers/net/tulip/xircom_tulip_cb.c b/drivers/net/tulip/xircom_tulip_cb.c
index 091ebb7a62f6..17ca7dc42e6f 100644
--- a/drivers/net/tulip/xircom_tulip_cb.c
+++ b/drivers/net/tulip/xircom_tulip_cb.c
@@ -10,26 +10,11 @@
10 410 Severn Ave., Suite 210 10 410 Severn Ave., Suite 210
11 Annapolis MD 21403 11 Annapolis MD 21403
12 12
13 -----------------------------------------------------------
14
15 Linux kernel-specific changes:
16
17 LK1.0 (Ion Badulescu)
18 - Major cleanup
19 - Use 2.4 PCI API
20 - Support ethtool
21 - Rewrite perfect filter/hash code
22 - Use interrupts for media changes
23
24 LK1.1 (Ion Badulescu)
25 - Disallow negotiation of unsupported full-duplex modes
26*/ 13*/
27 14
28#define DRV_NAME "xircom_tulip_cb" 15#define DRV_NAME "xircom_tulip_cb"
29#define DRV_VERSION "0.91+LK1.1" 16#define DRV_VERSION "0.92"
30#define DRV_RELDATE "October 11, 2001" 17#define DRV_RELDATE "June 27, 2006"
31
32#define CARDBUS 1
33 18
34/* A few user-configurable values. */ 19/* A few user-configurable values. */
35 20
@@ -306,10 +291,10 @@ struct xircom_private {
306 struct xircom_tx_desc tx_ring[TX_RING_SIZE]; 291 struct xircom_tx_desc tx_ring[TX_RING_SIZE];
307 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 292 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
308 struct sk_buff* tx_skbuff[TX_RING_SIZE]; 293 struct sk_buff* tx_skbuff[TX_RING_SIZE];
309#ifdef CARDBUS 294
310 /* The X3201-3 requires 4-byte aligned tx bufs */ 295 /* The X3201-3 requires 4-byte aligned tx bufs */
311 struct sk_buff* tx_aligned_skbuff[TX_RING_SIZE]; 296 struct sk_buff* tx_aligned_skbuff[TX_RING_SIZE];
312#endif 297
313 /* The addresses of receive-in-place skbuffs. */ 298 /* The addresses of receive-in-place skbuffs. */
314 struct sk_buff* rx_skbuff[RX_RING_SIZE]; 299 struct sk_buff* rx_skbuff[RX_RING_SIZE];
315 u16 setup_frame[PKT_SETUP_SZ / sizeof(u16)]; /* Pseudo-Tx frame to init address table. */ 300 u16 setup_frame[PKT_SETUP_SZ / sizeof(u16)]; /* Pseudo-Tx frame to init address table. */
@@ -908,10 +893,8 @@ static void xircom_init_ring(struct net_device *dev)
908 tp->tx_skbuff[i] = NULL; 893 tp->tx_skbuff[i] = NULL;
909 tp->tx_ring[i].status = 0; 894 tp->tx_ring[i].status = 0;
910 tp->tx_ring[i].buffer2 = virt_to_bus(&tp->tx_ring[i+1]); 895 tp->tx_ring[i].buffer2 = virt_to_bus(&tp->tx_ring[i+1]);
911#ifdef CARDBUS
912 if (tp->chip_id == X3201_3) 896 if (tp->chip_id == X3201_3)
913 tp->tx_aligned_skbuff[i] = dev_alloc_skb(PKT_BUF_SZ); 897 tp->tx_aligned_skbuff[i] = dev_alloc_skb(PKT_BUF_SZ);
914#endif /* CARDBUS */
915 } 898 }
916 tp->tx_ring[i-1].buffer2 = virt_to_bus(&tp->tx_ring[0]); 899 tp->tx_ring[i-1].buffer2 = virt_to_bus(&tp->tx_ring[0]);
917} 900}
@@ -931,12 +914,10 @@ xircom_start_xmit(struct sk_buff *skb, struct net_device *dev)
931 entry = tp->cur_tx % TX_RING_SIZE; 914 entry = tp->cur_tx % TX_RING_SIZE;
932 915
933 tp->tx_skbuff[entry] = skb; 916 tp->tx_skbuff[entry] = skb;
934#ifdef CARDBUS
935 if (tp->chip_id == X3201_3) { 917 if (tp->chip_id == X3201_3) {
936 memcpy(tp->tx_aligned_skbuff[entry]->data,skb->data,skb->len); 918 memcpy(tp->tx_aligned_skbuff[entry]->data,skb->data,skb->len);
937 tp->tx_ring[entry].buffer1 = virt_to_bus(tp->tx_aligned_skbuff[entry]->data); 919 tp->tx_ring[entry].buffer1 = virt_to_bus(tp->tx_aligned_skbuff[entry]->data);
938 } else 920 } else
939#endif
940 tp->tx_ring[entry].buffer1 = virt_to_bus(skb->data); 921 tp->tx_ring[entry].buffer1 = virt_to_bus(skb->data);
941 922
942 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */ 923 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c
index 063816f2b11e..4103c37172f9 100644
--- a/drivers/net/typhoon.c
+++ b/drivers/net/typhoon.c
@@ -805,7 +805,7 @@ typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
805 * If problems develop with TSO, check this first. 805 * If problems develop with TSO, check this first.
806 */ 806 */
807 numDesc = skb_shinfo(skb)->nr_frags + 1; 807 numDesc = skb_shinfo(skb)->nr_frags + 1;
808 if(skb_tso_size(skb)) 808 if (skb_is_gso(skb))
809 numDesc++; 809 numDesc++;
810 810
811 /* When checking for free space in the ring, we need to also 811 /* When checking for free space in the ring, we need to also
@@ -845,7 +845,7 @@ typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
845 TYPHOON_TX_PF_VLAN_TAG_SHIFT); 845 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
846 } 846 }
847 847
848 if(skb_tso_size(skb)) { 848 if (skb_is_gso(skb)) {
849 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT; 849 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
850 first_txd->numDesc++; 850 first_txd->numDesc++;
851 851
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c
index 98b6f3207d3d..d3d0ec970318 100644
--- a/drivers/net/via-rhine.c
+++ b/drivers/net/via-rhine.c
@@ -25,117 +25,13 @@
25 version. He may or may not be interested in bug reports on this 25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at: 26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html 27 http://www.scyld.com/network/via-rhine.html
28 28 [link no longer provides useful info -jgarzik]
29
30 Linux kernel version history:
31
32 LK1.1.0:
33 - Jeff Garzik: softnet 'n stuff
34
35 LK1.1.1:
36 - Justin Guyett: softnet and locking fixes
37 - Jeff Garzik: use PCI interface
38
39 LK1.1.2:
40 - Urban Widmark: minor cleanups, merges from Becker 1.03a/1.04 versions
41
42 LK1.1.3:
43 - Urban Widmark: use PCI DMA interface (with thanks to the eepro100.c
44 code) update "Theory of Operation" with
45 softnet/locking changes
46 - Dave Miller: PCI DMA and endian fixups
47 - Jeff Garzik: MOD_xxx race fixes, updated PCI resource allocation
48
49 LK1.1.4:
50 - Urban Widmark: fix gcc 2.95.2 problem and
51 remove writel's to fixed address 0x7c
52
53 LK1.1.5:
54 - Urban Widmark: mdio locking, bounce buffer changes
55 merges from Beckers 1.05 version
56 added netif_running_on/off support
57
58 LK1.1.6:
59 - Urban Widmark: merges from Beckers 1.08b version (VT6102 + mdio)
60 set netif_running_on/off on startup, del_timer_sync
61
62 LK1.1.7:
63 - Manfred Spraul: added reset into tx_timeout
64
65 LK1.1.9:
66 - Urban Widmark: merges from Beckers 1.10 version
67 (media selection + eeprom reload)
68 - David Vrabel: merges from D-Link "1.11" version
69 (disable WOL and PME on startup)
70
71 LK1.1.10:
72 - Manfred Spraul: use "singlecopy" for unaligned buffers
73 don't allocate bounce buffers for !ReqTxAlign cards
74
75 LK1.1.11:
76 - David Woodhouse: Set dev->base_addr before the first time we call
77 wait_for_reset(). It's a lot happier that way.
78 Free np->tx_bufs only if we actually allocated it.
79
80 LK1.1.12:
81 - Martin Eriksson: Allow Memory-Mapped IO to be enabled.
82
83 LK1.1.13 (jgarzik):
84 - Add ethtool support
85 - Replace some MII-related magic numbers with constants
86
87 LK1.1.14 (Ivan G.):
88 - fixes comments for Rhine-III
89 - removes W_MAX_TIMEOUT (unused)
90 - adds HasDavicomPhy for Rhine-I (basis: linuxfet driver; my card
91 is R-I and has Davicom chip, flag is referenced in kernel driver)
92 - sends chip_id as a parameter to wait_for_reset since np is not
93 initialized on first call
94 - changes mmio "else if (chip_id==VT6102)" to "else" so it will work
95 for Rhine-III's (documentation says same bit is correct)
96 - transmit frame queue message is off by one - fixed
97 - adds IntrNormalSummary to "Something Wicked" exclusion list
98 so normal interrupts will not trigger the message (src: Donald Becker)
99 (Roger Luethi)
100 - show confused chip where to continue after Tx error
101 - location of collision counter is chip specific
102 - allow selecting backoff algorithm (module parameter)
103
104 LK1.1.15 (jgarzik):
105 - Use new MII lib helper generic_mii_ioctl
106
107 LK1.1.16 (Roger Luethi)
108 - Etherleak fix
109 - Handle Tx buffer underrun
110 - Fix bugs in full duplex handling
111 - New reset code uses "force reset" cmd on Rhine-II
112 - Various clean ups
113
114 LK1.1.17 (Roger Luethi)
115 - Fix race in via_rhine_start_tx()
116 - On errors, wait for Tx engine to turn off before scavenging
117 - Handle Tx descriptor write-back race on Rhine-II
118 - Force flushing for PCI posted writes
119 - More reset code changes
120
121 LK1.1.18 (Roger Luethi)
122 - No filtering multicast in promisc mode (Edward Peng)
123 - Fix for Rhine-I Tx timeouts
124
125 LK1.1.19 (Roger Luethi)
126 - Increase Tx threshold for unspecified errors
127
128 LK1.2.0-2.6 (Roger Luethi)
129 - Massive clean-up
130 - Rewrite PHY, media handling (remove options, full_duplex, backoff)
131 - Fix Tx engine race for good
132 - Craig Brind: Zero padded aligned buffers for short packets.
133 29
134*/ 30*/
135 31
136#define DRV_NAME "via-rhine" 32#define DRV_NAME "via-rhine"
137#define DRV_VERSION "1.2.0-2.6" 33#define DRV_VERSION "1.4.0"
138#define DRV_RELDATE "June-10-2004" 34#define DRV_RELDATE "June-27-2006"
139 35
140 36
141/* A few user-configurable values. 37/* A few user-configurable values.
@@ -356,12 +252,11 @@ enum rhine_quirks {
356/* Beware of PCI posted writes */ 252/* Beware of PCI posted writes */
357#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0) 253#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
358 254
359static struct pci_device_id rhine_pci_tbl[] = 255static const struct pci_device_id rhine_pci_tbl[] = {
360{ 256 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
361 {0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT86C100A */ 257 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
362 {0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6102 */ 258 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
363 {0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* 6105{,L,LOM} */ 259 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
364 {0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6105M */
365 { } /* terminate list */ 260 { } /* terminate list */
366}; 261};
367MODULE_DEVICE_TABLE(pci, rhine_pci_tbl); 262MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c
index ba2972ba3757..aa9cd92f46b2 100644
--- a/drivers/net/via-velocity.c
+++ b/drivers/net/via-velocity.c
@@ -229,7 +229,8 @@ static int rx_copybreak = 200;
229module_param(rx_copybreak, int, 0644); 229module_param(rx_copybreak, int, 0644);
230MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); 230MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
231 231
232static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr, struct velocity_info_tbl *info); 232static void velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr,
233 const struct velocity_info_tbl *info);
233static int velocity_get_pci_info(struct velocity_info *, struct pci_dev *pdev); 234static int velocity_get_pci_info(struct velocity_info *, struct pci_dev *pdev);
234static void velocity_print_info(struct velocity_info *vptr); 235static void velocity_print_info(struct velocity_info *vptr);
235static int velocity_open(struct net_device *dev); 236static int velocity_open(struct net_device *dev);
@@ -294,9 +295,9 @@ static void velocity_unregister_notifier(void)
294 * Internal board variants. At the moment we have only one 295 * Internal board variants. At the moment we have only one
295 */ 296 */
296 297
297static struct velocity_info_tbl chip_info_table[] = { 298static const struct velocity_info_tbl chip_info_table[] __devinitdata = {
298 {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 256, 1, 0x00FFFFFFUL}, 299 {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
299 {0, NULL} 300 { }
300}; 301};
301 302
302/* 303/*
@@ -304,10 +305,9 @@ static struct velocity_info_tbl chip_info_table[] = {
304 * device driver. Used for hotplug autoloading. 305 * device driver. Used for hotplug autoloading.
305 */ 306 */
306 307
307static struct pci_device_id velocity_id_table[] __devinitdata = { 308static const struct pci_device_id velocity_id_table[] __devinitdata = {
308 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X, 309 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) chip_info_table}, 310 { }
310 {0, }
311}; 311};
312 312
313MODULE_DEVICE_TABLE(pci, velocity_id_table); 313MODULE_DEVICE_TABLE(pci, velocity_id_table);
@@ -341,7 +341,7 @@ static char __devinit *get_chip_name(enum chip_type chip_id)
341static void __devexit velocity_remove1(struct pci_dev *pdev) 341static void __devexit velocity_remove1(struct pci_dev *pdev)
342{ 342{
343 struct net_device *dev = pci_get_drvdata(pdev); 343 struct net_device *dev = pci_get_drvdata(pdev);
344 struct velocity_info *vptr = dev->priv; 344 struct velocity_info *vptr = netdev_priv(dev);
345 345
346#ifdef CONFIG_PM 346#ifdef CONFIG_PM
347 unsigned long flags; 347 unsigned long flags;
@@ -686,21 +686,23 @@ static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_devi
686 static int first = 1; 686 static int first = 1;
687 struct net_device *dev; 687 struct net_device *dev;
688 int i; 688 int i;
689 struct velocity_info_tbl *info = (struct velocity_info_tbl *) ent->driver_data; 689 const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
690 struct velocity_info *vptr; 690 struct velocity_info *vptr;
691 struct mac_regs __iomem * regs; 691 struct mac_regs __iomem * regs;
692 int ret = -ENOMEM; 692 int ret = -ENOMEM;
693 693
694 /* FIXME: this driver, like almost all other ethernet drivers,
695 * can support more than MAX_UNITS.
696 */
694 if (velocity_nics >= MAX_UNITS) { 697 if (velocity_nics >= MAX_UNITS) {
695 printk(KERN_NOTICE VELOCITY_NAME ": already found %d NICs.\n", 698 dev_notice(&pdev->dev, "already found %d NICs.\n",
696 velocity_nics); 699 velocity_nics);
697 return -ENODEV; 700 return -ENODEV;
698 } 701 }
699 702
700 dev = alloc_etherdev(sizeof(struct velocity_info)); 703 dev = alloc_etherdev(sizeof(struct velocity_info));
701 704 if (!dev) {
702 if (dev == NULL) { 705 dev_err(&pdev->dev, "allocate net device failed.\n");
703 printk(KERN_ERR VELOCITY_NAME ": allocate net device failed.\n");
704 goto out; 706 goto out;
705 } 707 }
706 708
@@ -708,7 +710,7 @@ static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_devi
708 710
709 SET_MODULE_OWNER(dev); 711 SET_MODULE_OWNER(dev);
710 SET_NETDEV_DEV(dev, &pdev->dev); 712 SET_NETDEV_DEV(dev, &pdev->dev);
711 vptr = dev->priv; 713 vptr = netdev_priv(dev);
712 714
713 715
714 if (first) { 716 if (first) {
@@ -731,17 +733,17 @@ static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_devi
731 733
732 ret = velocity_get_pci_info(vptr, pdev); 734 ret = velocity_get_pci_info(vptr, pdev);
733 if (ret < 0) { 735 if (ret < 0) {
734 printk(KERN_ERR VELOCITY_NAME ": Failed to find PCI device.\n"); 736 /* error message already printed */
735 goto err_disable; 737 goto err_disable;
736 } 738 }
737 739
738 ret = pci_request_regions(pdev, VELOCITY_NAME); 740 ret = pci_request_regions(pdev, VELOCITY_NAME);
739 if (ret < 0) { 741 if (ret < 0) {
740 printk(KERN_ERR VELOCITY_NAME ": Failed to find PCI device.\n"); 742 dev_err(&pdev->dev, "No PCI resources.\n");
741 goto err_disable; 743 goto err_disable;
742 } 744 }
743 745
744 regs = ioremap(vptr->memaddr, vptr->io_size); 746 regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
745 if (regs == NULL) { 747 if (regs == NULL) {
746 ret = -EIO; 748 ret = -EIO;
747 goto err_release_res; 749 goto err_release_res;
@@ -859,13 +861,14 @@ static void __devinit velocity_print_info(struct velocity_info *vptr)
859 * discovered. 861 * discovered.
860 */ 862 */
861 863
862static void __devinit velocity_init_info(struct pci_dev *pdev, struct velocity_info *vptr, struct velocity_info_tbl *info) 864static void __devinit velocity_init_info(struct pci_dev *pdev,
865 struct velocity_info *vptr,
866 const struct velocity_info_tbl *info)
863{ 867{
864 memset(vptr, 0, sizeof(struct velocity_info)); 868 memset(vptr, 0, sizeof(struct velocity_info));
865 869
866 vptr->pdev = pdev; 870 vptr->pdev = pdev;
867 vptr->chip_id = info->chip_id; 871 vptr->chip_id = info->chip_id;
868 vptr->io_size = info->io_size;
869 vptr->num_txq = info->txqueue; 872 vptr->num_txq = info->txqueue;
870 vptr->multicast_limit = MCAM_SIZE; 873 vptr->multicast_limit = MCAM_SIZE;
871 spin_lock_init(&vptr->lock); 874 spin_lock_init(&vptr->lock);
@@ -883,8 +886,7 @@ static void __devinit velocity_init_info(struct pci_dev *pdev, struct velocity_i
883 886
884static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev) 887static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
885{ 888{
886 889 if (pci_read_config_byte(pdev, PCI_REVISION_ID, &vptr->rev_id) < 0)
887 if(pci_read_config_byte(pdev, PCI_REVISION_ID, &vptr->rev_id) < 0)
888 return -EIO; 890 return -EIO;
889 891
890 pci_set_master(pdev); 892 pci_set_master(pdev);
@@ -892,24 +894,20 @@ static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pc
892 vptr->ioaddr = pci_resource_start(pdev, 0); 894 vptr->ioaddr = pci_resource_start(pdev, 0);
893 vptr->memaddr = pci_resource_start(pdev, 1); 895 vptr->memaddr = pci_resource_start(pdev, 1);
894 896
895 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) 897 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
896 { 898 dev_err(&pdev->dev,
897 printk(KERN_ERR "%s: region #0 is not an I/O resource, aborting.\n", 899 "region #0 is not an I/O resource, aborting.\n");
898 pci_name(pdev));
899 return -EINVAL; 900 return -EINVAL;
900 } 901 }
901 902
902 if((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) 903 if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
903 { 904 dev_err(&pdev->dev,
904 printk(KERN_ERR "%s: region #1 is an I/O resource, aborting.\n", 905 "region #1 is an I/O resource, aborting.\n");
905 pci_name(pdev));
906 return -EINVAL; 906 return -EINVAL;
907 } 907 }
908 908
909 if(pci_resource_len(pdev, 1) < 256) 909 if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
910 { 910 dev_err(&pdev->dev, "region #1 is too small.\n");
911 printk(KERN_ERR "%s: region #1 is too small.\n",
912 pci_name(pdev));
913 return -EINVAL; 911 return -EINVAL;
914 } 912 }
915 vptr->pdev = pdev; 913 vptr->pdev = pdev;
@@ -1728,7 +1726,7 @@ static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_
1728 1726
1729static int velocity_open(struct net_device *dev) 1727static int velocity_open(struct net_device *dev)
1730{ 1728{
1731 struct velocity_info *vptr = dev->priv; 1729 struct velocity_info *vptr = netdev_priv(dev);
1732 int ret; 1730 int ret;
1733 1731
1734 vptr->rx_buf_sz = (dev->mtu <= 1504 ? PKT_BUF_SZ : dev->mtu + 32); 1732 vptr->rx_buf_sz = (dev->mtu <= 1504 ? PKT_BUF_SZ : dev->mtu + 32);
@@ -1785,7 +1783,7 @@ err_free_desc_rings:
1785 1783
1786static int velocity_change_mtu(struct net_device *dev, int new_mtu) 1784static int velocity_change_mtu(struct net_device *dev, int new_mtu)
1787{ 1785{
1788 struct velocity_info *vptr = dev->priv; 1786 struct velocity_info *vptr = netdev_priv(dev);
1789 unsigned long flags; 1787 unsigned long flags;
1790 int oldmtu = dev->mtu; 1788 int oldmtu = dev->mtu;
1791 int ret = 0; 1789 int ret = 0;
@@ -1861,7 +1859,7 @@ static void velocity_shutdown(struct velocity_info *vptr)
1861 1859
1862static int velocity_close(struct net_device *dev) 1860static int velocity_close(struct net_device *dev)
1863{ 1861{
1864 struct velocity_info *vptr = dev->priv; 1862 struct velocity_info *vptr = netdev_priv(dev);
1865 1863
1866 netif_stop_queue(dev); 1864 netif_stop_queue(dev);
1867 velocity_shutdown(vptr); 1865 velocity_shutdown(vptr);
@@ -1894,7 +1892,7 @@ static int velocity_close(struct net_device *dev)
1894 1892
1895static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) 1893static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
1896{ 1894{
1897 struct velocity_info *vptr = dev->priv; 1895 struct velocity_info *vptr = netdev_priv(dev);
1898 int qnum = 0; 1896 int qnum = 0;
1899 struct tx_desc *td_ptr; 1897 struct tx_desc *td_ptr;
1900 struct velocity_td_info *tdinfo; 1898 struct velocity_td_info *tdinfo;
@@ -2049,7 +2047,7 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
2049static int velocity_intr(int irq, void *dev_instance, struct pt_regs *regs) 2047static int velocity_intr(int irq, void *dev_instance, struct pt_regs *regs)
2050{ 2048{
2051 struct net_device *dev = dev_instance; 2049 struct net_device *dev = dev_instance;
2052 struct velocity_info *vptr = dev->priv; 2050 struct velocity_info *vptr = netdev_priv(dev);
2053 u32 isr_status; 2051 u32 isr_status;
2054 int max_count = 0; 2052 int max_count = 0;
2055 2053
@@ -2104,7 +2102,7 @@ static int velocity_intr(int irq, void *dev_instance, struct pt_regs *regs)
2104 2102
2105static void velocity_set_multi(struct net_device *dev) 2103static void velocity_set_multi(struct net_device *dev)
2106{ 2104{
2107 struct velocity_info *vptr = dev->priv; 2105 struct velocity_info *vptr = netdev_priv(dev);
2108 struct mac_regs __iomem * regs = vptr->mac_regs; 2106 struct mac_regs __iomem * regs = vptr->mac_regs;
2109 u8 rx_mode; 2107 u8 rx_mode;
2110 int i; 2108 int i;
@@ -2153,7 +2151,7 @@ static void velocity_set_multi(struct net_device *dev)
2153 2151
2154static struct net_device_stats *velocity_get_stats(struct net_device *dev) 2152static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2155{ 2153{
2156 struct velocity_info *vptr = dev->priv; 2154 struct velocity_info *vptr = netdev_priv(dev);
2157 2155
2158 /* If the hardware is down, don't touch MII */ 2156 /* If the hardware is down, don't touch MII */
2159 if(!netif_running(dev)) 2157 if(!netif_running(dev))
@@ -2196,7 +2194,7 @@ static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2196 2194
2197static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2195static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2198{ 2196{
2199 struct velocity_info *vptr = dev->priv; 2197 struct velocity_info *vptr = netdev_priv(dev);
2200 int ret; 2198 int ret;
2201 2199
2202 /* If we are asked for information and the device is power 2200 /* If we are asked for information and the device is power
@@ -2744,7 +2742,7 @@ static u32 check_connection_type(struct mac_regs __iomem * regs)
2744 2742
2745 if (PHYSR0 & PHYSR0_SPDG) 2743 if (PHYSR0 & PHYSR0_SPDG)
2746 status |= VELOCITY_SPEED_1000; 2744 status |= VELOCITY_SPEED_1000;
2747 if (PHYSR0 & PHYSR0_SPD10) 2745 else if (PHYSR0 & PHYSR0_SPD10)
2748 status |= VELOCITY_SPEED_10; 2746 status |= VELOCITY_SPEED_10;
2749 else 2747 else
2750 status |= VELOCITY_SPEED_100; 2748 status |= VELOCITY_SPEED_100;
@@ -2825,7 +2823,7 @@ static void enable_flow_control_ability(struct velocity_info *vptr)
2825 2823
2826static int velocity_ethtool_up(struct net_device *dev) 2824static int velocity_ethtool_up(struct net_device *dev)
2827{ 2825{
2828 struct velocity_info *vptr = dev->priv; 2826 struct velocity_info *vptr = netdev_priv(dev);
2829 if (!netif_running(dev)) 2827 if (!netif_running(dev))
2830 pci_set_power_state(vptr->pdev, PCI_D0); 2828 pci_set_power_state(vptr->pdev, PCI_D0);
2831 return 0; 2829 return 0;
@@ -2841,20 +2839,29 @@ static int velocity_ethtool_up(struct net_device *dev)
2841 2839
2842static void velocity_ethtool_down(struct net_device *dev) 2840static void velocity_ethtool_down(struct net_device *dev)
2843{ 2841{
2844 struct velocity_info *vptr = dev->priv; 2842 struct velocity_info *vptr = netdev_priv(dev);
2845 if (!netif_running(dev)) 2843 if (!netif_running(dev))
2846 pci_set_power_state(vptr->pdev, PCI_D3hot); 2844 pci_set_power_state(vptr->pdev, PCI_D3hot);
2847} 2845}
2848 2846
2849static int velocity_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2847static int velocity_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2850{ 2848{
2851 struct velocity_info *vptr = dev->priv; 2849 struct velocity_info *vptr = netdev_priv(dev);
2852 struct mac_regs __iomem * regs = vptr->mac_regs; 2850 struct mac_regs __iomem * regs = vptr->mac_regs;
2853 u32 status; 2851 u32 status;
2854 status = check_connection_type(vptr->mac_regs); 2852 status = check_connection_type(vptr->mac_regs);
2855 2853
2856 cmd->supported = SUPPORTED_TP | SUPPORTED_Autoneg | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full; 2854 cmd->supported = SUPPORTED_TP |
2857 if (status & VELOCITY_SPEED_100) 2855 SUPPORTED_Autoneg |
2856 SUPPORTED_10baseT_Half |
2857 SUPPORTED_10baseT_Full |
2858 SUPPORTED_100baseT_Half |
2859 SUPPORTED_100baseT_Full |
2860 SUPPORTED_1000baseT_Half |
2861 SUPPORTED_1000baseT_Full;
2862 if (status & VELOCITY_SPEED_1000)
2863 cmd->speed = SPEED_1000;
2864 else if (status & VELOCITY_SPEED_100)
2858 cmd->speed = SPEED_100; 2865 cmd->speed = SPEED_100;
2859 else 2866 else
2860 cmd->speed = SPEED_10; 2867 cmd->speed = SPEED_10;
@@ -2873,7 +2880,7 @@ static int velocity_get_settings(struct net_device *dev, struct ethtool_cmd *cmd
2873 2880
2874static int velocity_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2881static int velocity_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2875{ 2882{
2876 struct velocity_info *vptr = dev->priv; 2883 struct velocity_info *vptr = netdev_priv(dev);
2877 u32 curr_status; 2884 u32 curr_status;
2878 u32 new_status = 0; 2885 u32 new_status = 0;
2879 int ret = 0; 2886 int ret = 0;
@@ -2896,14 +2903,14 @@ static int velocity_set_settings(struct net_device *dev, struct ethtool_cmd *cmd
2896 2903
2897static u32 velocity_get_link(struct net_device *dev) 2904static u32 velocity_get_link(struct net_device *dev)
2898{ 2905{
2899 struct velocity_info *vptr = dev->priv; 2906 struct velocity_info *vptr = netdev_priv(dev);
2900 struct mac_regs __iomem * regs = vptr->mac_regs; 2907 struct mac_regs __iomem * regs = vptr->mac_regs;
2901 return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, &regs->PHYSR0) ? 0 : 1; 2908 return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, &regs->PHYSR0) ? 1 : 0;
2902} 2909}
2903 2910
2904static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2911static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2905{ 2912{
2906 struct velocity_info *vptr = dev->priv; 2913 struct velocity_info *vptr = netdev_priv(dev);
2907 strcpy(info->driver, VELOCITY_NAME); 2914 strcpy(info->driver, VELOCITY_NAME);
2908 strcpy(info->version, VELOCITY_VERSION); 2915 strcpy(info->version, VELOCITY_VERSION);
2909 strcpy(info->bus_info, pci_name(vptr->pdev)); 2916 strcpy(info->bus_info, pci_name(vptr->pdev));
@@ -2911,7 +2918,7 @@ static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo
2911 2918
2912static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2919static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2913{ 2920{
2914 struct velocity_info *vptr = dev->priv; 2921 struct velocity_info *vptr = netdev_priv(dev);
2915 wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP; 2922 wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
2916 wol->wolopts |= WAKE_MAGIC; 2923 wol->wolopts |= WAKE_MAGIC;
2917 /* 2924 /*
@@ -2927,7 +2934,7 @@ static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_woli
2927 2934
2928static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2935static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2929{ 2936{
2930 struct velocity_info *vptr = dev->priv; 2937 struct velocity_info *vptr = netdev_priv(dev);
2931 2938
2932 if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP))) 2939 if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
2933 return -EFAULT; 2940 return -EFAULT;
@@ -2992,7 +2999,7 @@ static struct ethtool_ops velocity_ethtool_ops = {
2992 2999
2993static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3000static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2994{ 3001{
2995 struct velocity_info *vptr = dev->priv; 3002 struct velocity_info *vptr = netdev_priv(dev);
2996 struct mac_regs __iomem * regs = vptr->mac_regs; 3003 struct mac_regs __iomem * regs = vptr->mac_regs;
2997 unsigned long flags; 3004 unsigned long flags;
2998 struct mii_ioctl_data *miidata = if_mii(ifr); 3005 struct mii_ioctl_data *miidata = if_mii(ifr);
diff --git a/drivers/net/via-velocity.h b/drivers/net/via-velocity.h
index f1b2640ebdc6..496c3d597444 100644
--- a/drivers/net/via-velocity.h
+++ b/drivers/net/via-velocity.h
@@ -31,6 +31,8 @@
31#define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver" 31#define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
32#define VELOCITY_VERSION "1.13" 32#define VELOCITY_VERSION "1.13"
33 33
34#define VELOCITY_IO_SIZE 256
35
34#define PKT_BUF_SZ 1540 36#define PKT_BUF_SZ 1540
35 37
36#define MAX_UNITS 8 38#define MAX_UNITS 8
@@ -1191,7 +1193,6 @@ enum chip_type {
1191struct velocity_info_tbl { 1193struct velocity_info_tbl {
1192 enum chip_type chip_id; 1194 enum chip_type chip_id;
1193 char *name; 1195 char *name;
1194 int io_size;
1195 int txqueue; 1196 int txqueue;
1196 u32 flags; 1197 u32 flags;
1197}; 1198};
@@ -1751,7 +1752,6 @@ struct velocity_info {
1751 struct mac_regs __iomem * mac_regs; 1752 struct mac_regs __iomem * mac_regs;
1752 unsigned long memaddr; 1753 unsigned long memaddr;
1753 unsigned long ioaddr; 1754 unsigned long ioaddr;
1754 u32 io_size;
1755 1755
1756 u8 rev_id; 1756 u8 rev_id;
1757 1757
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index b5328b0ff927..54b8e492ef97 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -134,18 +134,6 @@ config SEALEVEL_4021
134 The driver will be compiled as a module: the 134 The driver will be compiled as a module: the
135 module will be called sealevel. 135 module will be called sealevel.
136 136
137config SYNCLINK_SYNCPPP
138 tristate "SyncLink HDLC/SYNCPPP support"
139 depends on WAN
140 help
141 Enables HDLC/SYNCPPP support for the SyncLink WAN driver.
142
143 Normally the SyncLink WAN driver works with the main PPP driver
144 <file:drivers/net/ppp_generic.c> and pppd program.
145 HDLC/SYNCPPP support allows use of the Cisco HDLC/PPP driver
146 <file:drivers/net/wan/syncppp.c>. The SyncLink WAN driver (in
147 character devices) must also be enabled.
148
149# Generic HDLC 137# Generic HDLC
150config HDLC 138config HDLC
151 tristate "Generic HDLC layer" 139 tristate "Generic HDLC layer"
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
index 823c6d5ab90d..316ca6869d5e 100644
--- a/drivers/net/wan/Makefile
+++ b/drivers/net/wan/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_COSA) += syncppp.o cosa.o
28obj-$(CONFIG_FARSYNC) += syncppp.o farsync.o 28obj-$(CONFIG_FARSYNC) += syncppp.o farsync.o
29obj-$(CONFIG_DSCC4) += dscc4.o 29obj-$(CONFIG_DSCC4) += dscc4.o
30obj-$(CONFIG_LANMEDIA) += syncppp.o 30obj-$(CONFIG_LANMEDIA) += syncppp.o
31obj-$(CONFIG_SYNCLINK_SYNCPPP) += syncppp.o
32obj-$(CONFIG_X25_ASY) += x25_asy.o 31obj-$(CONFIG_X25_ASY) += x25_asy.o
33 32
34obj-$(CONFIG_LANMEDIA) += lmc/ 33obj-$(CONFIG_LANMEDIA) += lmc/
diff --git a/drivers/net/wan/c101.c b/drivers/net/wan/c101.c
index c92ac9fde083..435e91ec4620 100644
--- a/drivers/net/wan/c101.c
+++ b/drivers/net/wan/c101.c
@@ -116,27 +116,33 @@ static inline void openwin(card_t *card, u8 page)
116#include "hd6457x.c" 116#include "hd6457x.c"
117 117
118 118
119static inline void set_carrier(port_t *port)
120{
121 if (!sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD)
122 netif_carrier_on(port_to_dev(port));
123 else
124 netif_carrier_off(port_to_dev(port));
125}
126
127
119static void sca_msci_intr(port_t *port) 128static void sca_msci_intr(port_t *port)
120{ 129{
121 struct net_device *dev = port_to_dev(port); 130 u8 stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI ST1 status */
122 card_t* card = port_to_card(port);
123 u8 stat = sca_in(MSCI1_OFFSET + ST1, card); /* read MSCI ST1 status */
124 131
125 /* Reset MSCI TX underrun status bit */ 132 /* Reset MSCI TX underrun status bit */
126 sca_out(stat & ST1_UDRN, MSCI0_OFFSET + ST1, card); 133 sca_out(stat & ST1_UDRN, MSCI0_OFFSET + ST1, port);
127 134
128 if (stat & ST1_UDRN) { 135 if (stat & ST1_UDRN) {
129 struct net_device_stats *stats = hdlc_stats(dev); 136 struct net_device_stats *stats = hdlc_stats(port_to_dev(port));
130 stats->tx_errors++; /* TX Underrun error detected */ 137 stats->tx_errors++; /* TX Underrun error detected */
131 stats->tx_fifo_errors++; 138 stats->tx_fifo_errors++;
132 } 139 }
133 140
134 /* Reset MSCI CDCD status bit - uses ch#2 DCD input */ 141 /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
135 sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, card); 142 sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
136 143
137 if (stat & ST1_CDCD) 144 if (stat & ST1_CDCD)
138 hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD), 145 set_carrier(port);
139 dev);
140} 146}
141 147
142 148
@@ -190,8 +196,7 @@ static int c101_open(struct net_device *dev)
190 sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port); 196 sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
191 sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port); 197 sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
192 198
193 hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD), dev); 199 set_carrier(port);
194 printk(KERN_DEBUG "0x%X\n", sca_in(MSCI1_OFFSET + ST3, port));
195 200
196 /* enable MSCI1 CDCD interrupt */ 201 /* enable MSCI1 CDCD interrupt */
197 sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port); 202 sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
@@ -378,7 +383,7 @@ static int __init c101_run(unsigned long irq, unsigned long winbase)
378 } 383 }
379 384
380 sca_init_sync_port(card); /* Set up C101 memory */ 385 sca_init_sync_port(card); /* Set up C101 memory */
381 hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD), dev); 386 set_carrier(card);
382 387
383 printk(KERN_INFO "%s: Moxa C101 on IRQ%u," 388 printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
384 " using %u TX + %u RX packets rings\n", 389 " using %u TX + %u RX packets rings\n",
@@ -443,4 +448,5 @@ module_exit(c101_cleanup);
443MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 448MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
444MODULE_DESCRIPTION("Moxa C101 serial port driver"); 449MODULE_DESCRIPTION("Moxa C101 serial port driver");
445MODULE_LICENSE("GPL v2"); 450MODULE_LICENSE("GPL v2");
446module_param(hw, charp, 0444); /* hw=irq,ram:irq,... */ 451module_param(hw, charp, 0444);
452MODULE_PARM_DESC(hw, "irq,ram:irq,...");
diff --git a/drivers/net/wan/hd6457x.c b/drivers/net/wan/hd6457x.c
index d3743321a977..dce2bb317b82 100644
--- a/drivers/net/wan/hd6457x.c
+++ b/drivers/net/wan/hd6457x.c
@@ -168,6 +168,23 @@ static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
168} 168}
169 169
170 170
171static inline void sca_set_carrier(port_t *port)
172{
173 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
174#ifdef DEBUG_LINK
175 printk(KERN_DEBUG "%s: sca_set_carrier on\n",
176 port_to_dev(port)->name);
177#endif
178 netif_carrier_on(port_to_dev(port));
179 } else {
180#ifdef DEBUG_LINK
181 printk(KERN_DEBUG "%s: sca_set_carrier off\n",
182 port_to_dev(port)->name);
183#endif
184 netif_carrier_off(port_to_dev(port));
185 }
186}
187
171 188
172static void sca_init_sync_port(port_t *port) 189static void sca_init_sync_port(port_t *port)
173{ 190{
@@ -237,9 +254,7 @@ static void sca_init_sync_port(port_t *port)
237 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); 254 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
238 } 255 }
239 } 256 }
240 257 sca_set_carrier(port);
241 hdlc_set_carrier(!(sca_in(get_msci(port) + ST3, card) & ST3_DCD),
242 port_to_dev(port));
243} 258}
244 259
245 260
@@ -262,8 +277,7 @@ static inline void sca_msci_intr(port_t *port)
262 } 277 }
263 278
264 if (stat & ST1_CDCD) 279 if (stat & ST1_CDCD)
265 hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD), 280 sca_set_carrier(port);
266 port_to_dev(port));
267} 281}
268#endif 282#endif
269 283
@@ -566,7 +580,7 @@ static void sca_open(struct net_device *dev)
566 - all DMA interrupts 580 - all DMA interrupts
567*/ 581*/
568 582
569 hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD), dev); 583 sca_set_carrier(port);
570 584
571#ifdef __HD64570_H 585#ifdef __HD64570_H
572 /* MSCI TX INT and RX INT A IRQ enable */ 586 /* MSCI TX INT and RX INT A IRQ enable */
diff --git a/drivers/net/wan/hdlc_cisco.c b/drivers/net/wan/hdlc_cisco.c
index 1fd04662c4fc..f289daba0c7b 100644
--- a/drivers/net/wan/hdlc_cisco.c
+++ b/drivers/net/wan/hdlc_cisco.c
@@ -192,9 +192,7 @@ static int cisco_rx(struct sk_buff *skb)
192 "uptime %ud%uh%um%us)\n", 192 "uptime %ud%uh%um%us)\n",
193 dev->name, days, hrs, 193 dev->name, days, hrs,
194 min, sec); 194 min, sec);
195#if 0 195 netif_dormant_off(dev);
196 netif_carrier_on(dev);
197#endif
198 hdlc->state.cisco.up = 1; 196 hdlc->state.cisco.up = 1;
199 } 197 }
200 } 198 }
@@ -227,9 +225,7 @@ static void cisco_timer(unsigned long arg)
227 hdlc->state.cisco.settings.timeout * HZ)) { 225 hdlc->state.cisco.settings.timeout * HZ)) {
228 hdlc->state.cisco.up = 0; 226 hdlc->state.cisco.up = 0;
229 printk(KERN_INFO "%s: Link down\n", dev->name); 227 printk(KERN_INFO "%s: Link down\n", dev->name);
230#if 0 228 netif_dormant_on(dev);
231 netif_carrier_off(dev);
232#endif
233 } 229 }
234 230
235 cisco_keepalive_send(dev, CISCO_KEEPALIVE_REQ, 231 cisco_keepalive_send(dev, CISCO_KEEPALIVE_REQ,
@@ -265,10 +261,7 @@ static void cisco_stop(struct net_device *dev)
265{ 261{
266 hdlc_device *hdlc = dev_to_hdlc(dev); 262 hdlc_device *hdlc = dev_to_hdlc(dev);
267 del_timer_sync(&hdlc->state.cisco.timer); 263 del_timer_sync(&hdlc->state.cisco.timer);
268#if 0 264 netif_dormant_on(dev);
269 if (netif_carrier_ok(dev))
270 netif_carrier_off(dev);
271#endif
272 hdlc->state.cisco.up = 0; 265 hdlc->state.cisco.up = 0;
273 hdlc->state.cisco.request_sent = 0; 266 hdlc->state.cisco.request_sent = 0;
274} 267}
@@ -328,6 +321,7 @@ int hdlc_cisco_ioctl(struct net_device *dev, struct ifreq *ifr)
328 dev->type = ARPHRD_CISCO; 321 dev->type = ARPHRD_CISCO;
329 dev->flags = IFF_POINTOPOINT | IFF_NOARP; 322 dev->flags = IFF_POINTOPOINT | IFF_NOARP;
330 dev->addr_len = 0; 323 dev->addr_len = 0;
324 netif_dormant_on(dev);
331 return 0; 325 return 0;
332 } 326 }
333 327
diff --git a/drivers/net/wan/hdlc_fr.c b/drivers/net/wan/hdlc_fr.c
index 523afe17564e..7bb737bbdeb9 100644
--- a/drivers/net/wan/hdlc_fr.c
+++ b/drivers/net/wan/hdlc_fr.c
@@ -301,7 +301,7 @@ static int pvc_open(struct net_device *dev)
301 if (pvc->open_count++ == 0) { 301 if (pvc->open_count++ == 0) {
302 hdlc_device *hdlc = dev_to_hdlc(pvc->master); 302 hdlc_device *hdlc = dev_to_hdlc(pvc->master);
303 if (hdlc->state.fr.settings.lmi == LMI_NONE) 303 if (hdlc->state.fr.settings.lmi == LMI_NONE)
304 pvc->state.active = hdlc->carrier; 304 pvc->state.active = netif_carrier_ok(pvc->master);
305 305
306 pvc_carrier(pvc->state.active, pvc); 306 pvc_carrier(pvc->state.active, pvc);
307 hdlc->state.fr.dce_changed = 1; 307 hdlc->state.fr.dce_changed = 1;
@@ -545,11 +545,7 @@ static void fr_set_link_state(int reliable, struct net_device *dev)
545 545
546 hdlc->state.fr.reliable = reliable; 546 hdlc->state.fr.reliable = reliable;
547 if (reliable) { 547 if (reliable) {
548#if 0 548 netif_dormant_off(dev);
549 if (!netif_carrier_ok(dev))
550 netif_carrier_on(dev);
551#endif
552
553 hdlc->state.fr.n391cnt = 0; /* Request full status */ 549 hdlc->state.fr.n391cnt = 0; /* Request full status */
554 hdlc->state.fr.dce_changed = 1; 550 hdlc->state.fr.dce_changed = 1;
555 551
@@ -562,11 +558,7 @@ static void fr_set_link_state(int reliable, struct net_device *dev)
562 } 558 }
563 } 559 }
564 } else { 560 } else {
565#if 0 561 netif_dormant_on(dev);
566 if (netif_carrier_ok(dev))
567 netif_carrier_off(dev);
568#endif
569
570 while (pvc) { /* Deactivate all PVCs */ 562 while (pvc) { /* Deactivate all PVCs */
571 pvc_carrier(0, pvc); 563 pvc_carrier(0, pvc);
572 pvc->state.exist = pvc->state.active = 0; 564 pvc->state.exist = pvc->state.active = 0;
diff --git a/drivers/net/wan/hdlc_generic.c b/drivers/net/wan/hdlc_generic.c
index b7da55140fbd..04ca1f7b6424 100644
--- a/drivers/net/wan/hdlc_generic.c
+++ b/drivers/net/wan/hdlc_generic.c
@@ -34,10 +34,11 @@
34#include <linux/inetdevice.h> 34#include <linux/inetdevice.h>
35#include <linux/lapb.h> 35#include <linux/lapb.h>
36#include <linux/rtnetlink.h> 36#include <linux/rtnetlink.h>
37#include <linux/notifier.h>
37#include <linux/hdlc.h> 38#include <linux/hdlc.h>
38 39
39 40
40static const char* version = "HDLC support module revision 1.18"; 41static const char* version = "HDLC support module revision 1.19";
41 42
42#undef DEBUG_LINK 43#undef DEBUG_LINK
43 44
@@ -73,57 +74,51 @@ static int hdlc_rcv(struct sk_buff *skb, struct net_device *dev,
73 74
74 75
75 76
76static void __hdlc_set_carrier_on(struct net_device *dev) 77static inline void hdlc_proto_start(struct net_device *dev)
77{ 78{
78 hdlc_device *hdlc = dev_to_hdlc(dev); 79 hdlc_device *hdlc = dev_to_hdlc(dev);
79 if (hdlc->proto.start) 80 if (hdlc->proto.start)
80 return hdlc->proto.start(dev); 81 return hdlc->proto.start(dev);
81#if 0
82#ifdef DEBUG_LINK
83 if (netif_carrier_ok(dev))
84 printk(KERN_ERR "hdlc_set_carrier_on(): already on\n");
85#endif
86 netif_carrier_on(dev);
87#endif
88} 82}
89 83
90 84
91 85
92static void __hdlc_set_carrier_off(struct net_device *dev) 86static inline void hdlc_proto_stop(struct net_device *dev)
93{ 87{
94 hdlc_device *hdlc = dev_to_hdlc(dev); 88 hdlc_device *hdlc = dev_to_hdlc(dev);
95 if (hdlc->proto.stop) 89 if (hdlc->proto.stop)
96 return hdlc->proto.stop(dev); 90 return hdlc->proto.stop(dev);
97
98#if 0
99#ifdef DEBUG_LINK
100 if (!netif_carrier_ok(dev))
101 printk(KERN_ERR "hdlc_set_carrier_off(): already off\n");
102#endif
103 netif_carrier_off(dev);
104#endif
105} 91}
106 92
107 93
108 94
109void hdlc_set_carrier(int on, struct net_device *dev) 95static int hdlc_device_event(struct notifier_block *this, unsigned long event,
96 void *ptr)
110{ 97{
111 hdlc_device *hdlc = dev_to_hdlc(dev); 98 struct net_device *dev = ptr;
99 hdlc_device *hdlc;
112 unsigned long flags; 100 unsigned long flags;
113 on = on ? 1 : 0; 101 int on;
102
103 if (dev->get_stats != hdlc_get_stats)
104 return NOTIFY_DONE; /* not an HDLC device */
105
106 if (event != NETDEV_CHANGE)
107 return NOTIFY_DONE; /* Only interrested in carrier changes */
108
109 on = netif_carrier_ok(dev);
114 110
115#ifdef DEBUG_LINK 111#ifdef DEBUG_LINK
116 printk(KERN_DEBUG "hdlc_set_carrier %i\n", on); 112 printk(KERN_DEBUG "%s: hdlc_device_event NETDEV_CHANGE, carrier %i\n",
113 dev->name, on);
117#endif 114#endif
118 115
116 hdlc = dev_to_hdlc(dev);
119 spin_lock_irqsave(&hdlc->state_lock, flags); 117 spin_lock_irqsave(&hdlc->state_lock, flags);
120 118
121 if (hdlc->carrier == on) 119 if (hdlc->carrier == on)
122 goto carrier_exit; /* no change in DCD line level */ 120 goto carrier_exit; /* no change in DCD line level */
123 121
124#ifdef DEBUG_LINK
125 printk(KERN_INFO "%s: carrier %s\n", dev->name, on ? "ON" : "off");
126#endif
127 hdlc->carrier = on; 122 hdlc->carrier = on;
128 123
129 if (!hdlc->open) 124 if (!hdlc->open)
@@ -131,14 +126,15 @@ void hdlc_set_carrier(int on, struct net_device *dev)
131 126
132 if (hdlc->carrier) { 127 if (hdlc->carrier) {
133 printk(KERN_INFO "%s: Carrier detected\n", dev->name); 128 printk(KERN_INFO "%s: Carrier detected\n", dev->name);
134 __hdlc_set_carrier_on(dev); 129 hdlc_proto_start(dev);
135 } else { 130 } else {
136 printk(KERN_INFO "%s: Carrier lost\n", dev->name); 131 printk(KERN_INFO "%s: Carrier lost\n", dev->name);
137 __hdlc_set_carrier_off(dev); 132 hdlc_proto_stop(dev);
138 } 133 }
139 134
140carrier_exit: 135carrier_exit:
141 spin_unlock_irqrestore(&hdlc->state_lock, flags); 136 spin_unlock_irqrestore(&hdlc->state_lock, flags);
137 return NOTIFY_DONE;
142} 138}
143 139
144 140
@@ -165,7 +161,7 @@ int hdlc_open(struct net_device *dev)
165 161
166 if (hdlc->carrier) { 162 if (hdlc->carrier) {
167 printk(KERN_INFO "%s: Carrier detected\n", dev->name); 163 printk(KERN_INFO "%s: Carrier detected\n", dev->name);
168 __hdlc_set_carrier_on(dev); 164 hdlc_proto_start(dev);
169 } else 165 } else
170 printk(KERN_INFO "%s: No carrier\n", dev->name); 166 printk(KERN_INFO "%s: No carrier\n", dev->name);
171 167
@@ -190,7 +186,7 @@ void hdlc_close(struct net_device *dev)
190 186
191 hdlc->open = 0; 187 hdlc->open = 0;
192 if (hdlc->carrier) 188 if (hdlc->carrier)
193 __hdlc_set_carrier_off(dev); 189 hdlc_proto_stop(dev);
194 190
195 spin_unlock_irq(&hdlc->state_lock); 191 spin_unlock_irq(&hdlc->state_lock);
196 192
@@ -303,7 +299,6 @@ MODULE_LICENSE("GPL v2");
303 299
304EXPORT_SYMBOL(hdlc_open); 300EXPORT_SYMBOL(hdlc_open);
305EXPORT_SYMBOL(hdlc_close); 301EXPORT_SYMBOL(hdlc_close);
306EXPORT_SYMBOL(hdlc_set_carrier);
307EXPORT_SYMBOL(hdlc_ioctl); 302EXPORT_SYMBOL(hdlc_ioctl);
308EXPORT_SYMBOL(hdlc_setup); 303EXPORT_SYMBOL(hdlc_setup);
309EXPORT_SYMBOL(alloc_hdlcdev); 304EXPORT_SYMBOL(alloc_hdlcdev);
@@ -315,9 +310,18 @@ static struct packet_type hdlc_packet_type = {
315}; 310};
316 311
317 312
313static struct notifier_block hdlc_notifier = {
314 .notifier_call = hdlc_device_event,
315};
316
317
318static int __init hdlc_module_init(void) 318static int __init hdlc_module_init(void)
319{ 319{
320 int result;
321
320 printk(KERN_INFO "%s\n", version); 322 printk(KERN_INFO "%s\n", version);
323 if ((result = register_netdevice_notifier(&hdlc_notifier)) != 0)
324 return result;
321 dev_add_pack(&hdlc_packet_type); 325 dev_add_pack(&hdlc_packet_type);
322 return 0; 326 return 0;
323} 327}
@@ -327,6 +331,7 @@ static int __init hdlc_module_init(void)
327static void __exit hdlc_module_exit(void) 331static void __exit hdlc_module_exit(void)
328{ 332{
329 dev_remove_pack(&hdlc_packet_type); 333 dev_remove_pack(&hdlc_packet_type);
334 unregister_netdevice_notifier(&hdlc_notifier);
330} 335}
331 336
332 337
diff --git a/drivers/net/wan/hdlc_ppp.c b/drivers/net/wan/hdlc_ppp.c
index b81263eaede0..fbaab5bf71eb 100644
--- a/drivers/net/wan/hdlc_ppp.c
+++ b/drivers/net/wan/hdlc_ppp.c
@@ -107,6 +107,7 @@ int hdlc_ppp_ioctl(struct net_device *dev, struct ifreq *ifr)
107 dev->hard_header = NULL; 107 dev->hard_header = NULL;
108 dev->type = ARPHRD_PPP; 108 dev->type = ARPHRD_PPP;
109 dev->addr_len = 0; 109 dev->addr_len = 0;
110 netif_dormant_off(dev);
110 return 0; 111 return 0;
111 } 112 }
112 113
diff --git a/drivers/net/wan/hdlc_raw.c b/drivers/net/wan/hdlc_raw.c
index 9456d31cb1c1..f15aa6ba77f1 100644
--- a/drivers/net/wan/hdlc_raw.c
+++ b/drivers/net/wan/hdlc_raw.c
@@ -82,6 +82,7 @@ int hdlc_raw_ioctl(struct net_device *dev, struct ifreq *ifr)
82 dev->type = ARPHRD_RAWHDLC; 82 dev->type = ARPHRD_RAWHDLC;
83 dev->flags = IFF_POINTOPOINT | IFF_NOARP; 83 dev->flags = IFF_POINTOPOINT | IFF_NOARP;
84 dev->addr_len = 0; 84 dev->addr_len = 0;
85 netif_dormant_off(dev);
85 return 0; 86 return 0;
86 } 87 }
87 88
diff --git a/drivers/net/wan/hdlc_raw_eth.c b/drivers/net/wan/hdlc_raw_eth.c
index b1285cc8fee6..d1884987f94e 100644
--- a/drivers/net/wan/hdlc_raw_eth.c
+++ b/drivers/net/wan/hdlc_raw_eth.c
@@ -100,6 +100,7 @@ int hdlc_raw_eth_ioctl(struct net_device *dev, struct ifreq *ifr)
100 dev->tx_queue_len = old_qlen; 100 dev->tx_queue_len = old_qlen;
101 memcpy(dev->dev_addr, "\x00\x01", 2); 101 memcpy(dev->dev_addr, "\x00\x01", 2);
102 get_random_bytes(dev->dev_addr + 2, ETH_ALEN - 2); 102 get_random_bytes(dev->dev_addr + 2, ETH_ALEN - 2);
103 netif_dormant_off(dev);
103 return 0; 104 return 0;
104 } 105 }
105 106
diff --git a/drivers/net/wan/hdlc_x25.c b/drivers/net/wan/hdlc_x25.c
index 07e5eef1fe0f..a867fb411f89 100644
--- a/drivers/net/wan/hdlc_x25.c
+++ b/drivers/net/wan/hdlc_x25.c
@@ -212,6 +212,7 @@ int hdlc_x25_ioctl(struct net_device *dev, struct ifreq *ifr)
212 dev->hard_header = NULL; 212 dev->hard_header = NULL;
213 dev->type = ARPHRD_X25; 213 dev->type = ARPHRD_X25;
214 dev->addr_len = 0; 214 dev->addr_len = 0;
215 netif_dormant_off(dev);
215 return 0; 216 return 0;
216 } 217 }
217 218
diff --git a/drivers/net/wan/n2.c b/drivers/net/wan/n2.c
index e013b817cab8..dcf46add3adf 100644
--- a/drivers/net/wan/n2.c
+++ b/drivers/net/wan/n2.c
@@ -564,4 +564,5 @@ module_exit(n2_cleanup);
564MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 564MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
565MODULE_DESCRIPTION("RISCom/N2 serial port driver"); 565MODULE_DESCRIPTION("RISCom/N2 serial port driver");
566MODULE_LICENSE("GPL v2"); 566MODULE_LICENSE("GPL v2");
567module_param(hw, charp, 0444); /* hw=io,irq,ram,ports:io,irq,... */ 567module_param(hw, charp, 0444);
568MODULE_PARM_DESC(hw, "io,irq,ram,ports:io,irq,...");
diff --git a/drivers/net/wan/wanxl.c b/drivers/net/wan/wanxl.c
index d564224cdca9..b2031dfc4bb1 100644
--- a/drivers/net/wan/wanxl.c
+++ b/drivers/net/wan/wanxl.c
@@ -149,7 +149,10 @@ static inline void wanxl_cable_intr(port_t *port)
149 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n", 149 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n",
150 port->dev->name, pm, dte, cable, dsr, dcd); 150 port->dev->name, pm, dte, cable, dsr, dcd);
151 151
152 hdlc_set_carrier(value & STATUS_CABLE_DCD, port->dev); 152 if (value & STATUS_CABLE_DCD)
153 netif_carrier_on(port->dev);
154 else
155 netif_carrier_off(port->dev);
153} 156}
154 157
155 158
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 30ec235e6935..2e8ac995d56f 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -447,6 +447,7 @@ config AIRO_CS
447 tristate "Cisco/Aironet 34X/35X/4500/4800 PCMCIA cards" 447 tristate "Cisco/Aironet 34X/35X/4500/4800 PCMCIA cards"
448 depends on NET_RADIO && PCMCIA && (BROKEN || !M32R) 448 depends on NET_RADIO && PCMCIA && (BROKEN || !M32R)
449 select CRYPTO 449 select CRYPTO
450 select CRYPTO_AES
450 ---help--- 451 ---help---
451 This is the standard Linux driver to support Cisco/Aironet PCMCIA 452 This is the standard Linux driver to support Cisco/Aironet PCMCIA
452 802.11 wireless cards. This driver is the same as the Aironet 453 802.11 wireless cards. This driver is the same as the Aironet
@@ -550,6 +551,7 @@ config USB_ZD1201
550 551
551source "drivers/net/wireless/hostap/Kconfig" 552source "drivers/net/wireless/hostap/Kconfig"
552source "drivers/net/wireless/bcm43xx/Kconfig" 553source "drivers/net/wireless/bcm43xx/Kconfig"
554source "drivers/net/wireless/zd1211rw/Kconfig"
553 555
554# yes, this works even when no drivers are selected 556# yes, this works even when no drivers are selected
555config NET_WIRELESS 557config NET_WIRELESS
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 512603de309a..c613af17a159 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PRISM54) += prism54/
36 36
37obj-$(CONFIG_HOSTAP) += hostap/ 37obj-$(CONFIG_HOSTAP) += hostap/
38obj-$(CONFIG_BCM43XX) += bcm43xx/ 38obj-$(CONFIG_BCM43XX) += bcm43xx/
39obj-$(CONFIG_ZD1211RW) += zd1211rw/
39 40
40# 16-bit wireless PCMCIA client drivers 41# 16-bit wireless PCMCIA client drivers
41obj-$(CONFIG_PCMCIA_RAYCS) += ray_cs.o 42obj-$(CONFIG_PCMCIA_RAYCS) += ray_cs.o
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_main.c b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
index d8f5600578b4..df317c1e12a8 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_main.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
@@ -1547,7 +1547,7 @@ static void handle_irq_noise(struct bcm43xx_private *bcm)
1547 goto generate_new; 1547 goto generate_new;
1548 1548
1549 /* Get the noise samples. */ 1549 /* Get the noise samples. */
1550 assert(bcm->noisecalc.nr_samples <= 8); 1550 assert(bcm->noisecalc.nr_samples < 8);
1551 i = bcm->noisecalc.nr_samples; 1551 i = bcm->noisecalc.nr_samples;
1552 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1); 1552 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1553 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1); 1553 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
@@ -1885,6 +1885,15 @@ static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_re
1885 1885
1886 spin_lock(&bcm->irq_lock); 1886 spin_lock(&bcm->irq_lock);
1887 1887
1888 /* Only accept IRQs, if we are initialized properly.
1889 * This avoids an RX race while initializing.
1890 * We should probably not enable IRQs before we are initialized
1891 * completely, but some careful work is needed to fix this. I think it
1892 * is best to stay with this cheap workaround for now... .
1893 */
1894 if (unlikely(bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED))
1895 goto out;
1896
1888 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); 1897 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1889 if (reason == 0xffffffff) { 1898 if (reason == 0xffffffff) {
1890 /* irq not for us (shared irq) */ 1899 /* irq not for us (shared irq) */
@@ -1906,19 +1915,11 @@ static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_re
1906 1915
1907 bcm43xx_interrupt_ack(bcm, reason); 1916 bcm43xx_interrupt_ack(bcm, reason);
1908 1917
1909 /* Only accept IRQs, if we are initialized properly. 1918 /* disable all IRQs. They are enabled again in the bottom half. */
1910 * This avoids an RX race while initializing. 1919 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1911 * We should probably not enable IRQs before we are initialized 1920 /* save the reason code and call our bottom half. */
1912 * completely, but some careful work is needed to fix this. I think it 1921 bcm->irq_reason = reason;
1913 * is best to stay with this cheap workaround for now... . 1922 tasklet_schedule(&bcm->isr_tasklet);
1914 */
1915 if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)) {
1916 /* disable all IRQs. They are enabled again in the bottom half. */
1917 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1918 /* save the reason code and call our bottom half. */
1919 bcm->irq_reason = reason;
1920 tasklet_schedule(&bcm->isr_tasklet);
1921 }
1922 1923
1923out: 1924out:
1924 mmiowb(); 1925 mmiowb();
@@ -3698,6 +3699,10 @@ static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3698 secinfo->encrypt = sec->encrypt; 3699 secinfo->encrypt = sec->encrypt;
3699 dprintk(", .encrypt = %d", sec->encrypt); 3700 dprintk(", .encrypt = %d", sec->encrypt);
3700 } 3701 }
3702 if (sec->flags & SEC_AUTH_MODE) {
3703 secinfo->auth_mode = sec->auth_mode;
3704 dprintk(", .auth_mode = %d", sec->auth_mode);
3705 }
3701 dprintk("\n"); 3706 dprintk("\n");
3702 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED && 3707 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED &&
3703 !bcm->ieee->host_encrypt) { 3708 !bcm->ieee->host_encrypt) {
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_main.h b/drivers/net/wireless/bcm43xx/bcm43xx_main.h
index 30a202b258b5..116493671f88 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_main.h
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_main.h
@@ -112,30 +112,6 @@ int bcm43xx_channel_to_freq(struct bcm43xx_private *bcm,
112 return bcm43xx_channel_to_freq_bg(channel); 112 return bcm43xx_channel_to_freq_bg(channel);
113} 113}
114 114
115/* Lightweight function to check if a channel number is valid.
116 * Note that this does _NOT_ check for geographical restrictions!
117 */
118static inline
119int bcm43xx_is_valid_channel_a(u8 channel)
120{
121 return (channel >= IEEE80211_52GHZ_MIN_CHANNEL
122 && channel <= IEEE80211_52GHZ_MAX_CHANNEL);
123}
124static inline
125int bcm43xx_is_valid_channel_bg(u8 channel)
126{
127 return (channel >= IEEE80211_24GHZ_MIN_CHANNEL
128 && channel <= IEEE80211_24GHZ_MAX_CHANNEL);
129}
130static inline
131int bcm43xx_is_valid_channel(struct bcm43xx_private *bcm,
132 u8 channel)
133{
134 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
135 return bcm43xx_is_valid_channel_a(channel);
136 return bcm43xx_is_valid_channel_bg(channel);
137}
138
139void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf); 115void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf);
140void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf); 116void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf);
141 117
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_radio.c b/drivers/net/wireless/bcm43xx/bcm43xx_radio.c
index af5c0bff1696..bb9c484d7e19 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_radio.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_radio.c
@@ -1594,11 +1594,11 @@ int bcm43xx_radio_selectchannel(struct bcm43xx_private *bcm,
1594 u16 r8, tmp; 1594 u16 r8, tmp;
1595 u16 freq; 1595 u16 freq;
1596 1596
1597 if (!ieee80211_is_valid_channel(bcm->ieee, channel))
1598 return -EINVAL;
1597 if ((radio->manufact == 0x17F) && 1599 if ((radio->manufact == 0x17F) &&
1598 (radio->version == 0x2060) && 1600 (radio->version == 0x2060) &&
1599 (radio->revision == 1)) { 1601 (radio->revision == 1)) {
1600 if (channel > 200)
1601 return -EINVAL;
1602 freq = channel2freq_a(channel); 1602 freq = channel2freq_a(channel);
1603 1603
1604 r8 = bcm43xx_radio_read16(bcm, 0x0008); 1604 r8 = bcm43xx_radio_read16(bcm, 0x0008);
@@ -1651,9 +1651,6 @@ int bcm43xx_radio_selectchannel(struct bcm43xx_private *bcm,
1651 TODO(); //TODO: TSSI2dbm workaround 1651 TODO(); //TODO: TSSI2dbm workaround
1652 bcm43xx_phy_xmitpower(bcm);//FIXME correct? 1652 bcm43xx_phy_xmitpower(bcm);//FIXME correct?
1653 } else { 1653 } else {
1654 if ((channel < 1) || (channel > 14))
1655 return -EINVAL;
1656
1657 if (synthetic_pu_workaround) 1654 if (synthetic_pu_workaround)
1658 bcm43xx_synth_pu_workaround(bcm, channel); 1655 bcm43xx_synth_pu_workaround(bcm, channel);
1659 1656
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_wx.c b/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
index c35cb3a0777e..5c36e29efff7 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
@@ -119,7 +119,7 @@ static int bcm43xx_wx_set_channelfreq(struct net_device *net_dev,
119 channel = bcm43xx_freq_to_channel(bcm, data->freq.m); 119 channel = bcm43xx_freq_to_channel(bcm, data->freq.m);
120 freq = data->freq.m; 120 freq = data->freq.m;
121 } 121 }
122 if (!bcm43xx_is_valid_channel(bcm, channel)) 122 if (!ieee80211_is_valid_channel(bcm->ieee, channel))
123 goto out_unlock; 123 goto out_unlock;
124 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) { 124 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
125 //ieee80211softmac_disassoc(softmac, $REASON); 125 //ieee80211softmac_disassoc(softmac, $REASON);
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c b/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
index d8ece28c079f..6dbd855b3647 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
@@ -296,11 +296,14 @@ void bcm43xx_generate_txhdr(struct bcm43xx_private *bcm,
296 u16 control = 0; 296 u16 control = 0;
297 u16 wsec_rate = 0; 297 u16 wsec_rate = 0;
298 u16 encrypt_frame; 298 u16 encrypt_frame;
299 const u16 ftype = WLAN_FC_GET_TYPE(le16_to_cpu(wireless_header->frame_ctl));
300 const int is_mgt = (ftype == IEEE80211_FTYPE_MGMT);
299 301
300 /* Now construct the TX header. */ 302 /* Now construct the TX header. */
301 memset(txhdr, 0, sizeof(*txhdr)); 303 memset(txhdr, 0, sizeof(*txhdr));
302 304
303 bitrate = bcm->softmac->txrates.default_rate; 305 bitrate = ieee80211softmac_suggest_txrate(bcm->softmac,
306 is_multicast_ether_addr(wireless_header->addr1), is_mgt);
304 ofdm_modulation = !(ieee80211_is_cck_rate(bitrate)); 307 ofdm_modulation = !(ieee80211_is_cck_rate(bitrate));
305 fallback_bitrate = bcm43xx_calc_fallback_rate(bitrate); 308 fallback_bitrate = bcm43xx_calc_fallback_rate(bitrate);
306 fallback_ofdm_modulation = !(ieee80211_is_cck_rate(fallback_bitrate)); 309 fallback_ofdm_modulation = !(ieee80211_is_cck_rate(fallback_bitrate));
diff --git a/drivers/net/wireless/hostap/hostap_plx.c b/drivers/net/wireless/hostap/hostap_plx.c
index 49860fa61c30..6dfa041be66d 100644
--- a/drivers/net/wireless/hostap/hostap_plx.c
+++ b/drivers/net/wireless/hostap/hostap_plx.c
@@ -66,10 +66,12 @@ static struct pci_device_id prism2_plx_id_table[] __devinitdata = {
66 PLXDEV(0x10b7, 0x7770, "3Com AirConnect PCI 777A"), 66 PLXDEV(0x10b7, 0x7770, "3Com AirConnect PCI 777A"),
67 PLXDEV(0x111a, 0x1023, "Siemens SpeedStream SS1023"), 67 PLXDEV(0x111a, 0x1023, "Siemens SpeedStream SS1023"),
68 PLXDEV(0x126c, 0x8030, "Nortel emobility"), 68 PLXDEV(0x126c, 0x8030, "Nortel emobility"),
69 PLXDEV(0x1562, 0x0001, "Symbol LA-4123"),
69 PLXDEV(0x1385, 0x4100, "Netgear MA301"), 70 PLXDEV(0x1385, 0x4100, "Netgear MA301"),
70 PLXDEV(0x15e8, 0x0130, "National Datacomm NCP130 (PLX9052)"), 71 PLXDEV(0x15e8, 0x0130, "National Datacomm NCP130 (PLX9052)"),
71 PLXDEV(0x15e8, 0x0131, "National Datacomm NCP130 (TMD7160)"), 72 PLXDEV(0x15e8, 0x0131, "National Datacomm NCP130 (TMD7160)"),
72 PLXDEV(0x1638, 0x1100, "Eumitcom WL11000"), 73 PLXDEV(0x1638, 0x1100, "Eumitcom WL11000"),
74 PLXDEV(0x16ab, 0x1100, "Global Sun Tech GL24110P"),
73 PLXDEV(0x16ab, 0x1101, "Global Sun Tech GL24110P (?)"), 75 PLXDEV(0x16ab, 0x1101, "Global Sun Tech GL24110P (?)"),
74 PLXDEV(0x16ab, 0x1102, "Linksys WPC11 with WDT11"), 76 PLXDEV(0x16ab, 0x1102, "Linksys WPC11 with WDT11"),
75 PLXDEV(0x16ab, 0x1103, "Longshine 8031"), 77 PLXDEV(0x16ab, 0x1103, "Longshine 8031"),
diff --git a/drivers/net/wireless/orinoco.c b/drivers/net/wireless/orinoco.c
index d6ed5781b93a..317ace7f9aae 100644
--- a/drivers/net/wireless/orinoco.c
+++ b/drivers/net/wireless/orinoco.c
@@ -2875,7 +2875,7 @@ static int orinoco_ioctl_setiwencode(struct net_device *dev,
2875 if (orinoco_lock(priv, &flags) != 0) 2875 if (orinoco_lock(priv, &flags) != 0)
2876 return -EBUSY; 2876 return -EBUSY;
2877 2877
2878 if (erq->pointer) { 2878 if (erq->length > 0) {
2879 if ((index < 0) || (index >= ORINOCO_MAX_KEYS)) 2879 if ((index < 0) || (index >= ORINOCO_MAX_KEYS))
2880 index = priv->tx_key; 2880 index = priv->tx_key;
2881 2881
@@ -2918,7 +2918,7 @@ static int orinoco_ioctl_setiwencode(struct net_device *dev,
2918 if (erq->flags & IW_ENCODE_RESTRICTED) 2918 if (erq->flags & IW_ENCODE_RESTRICTED)
2919 restricted = 1; 2919 restricted = 1;
2920 2920
2921 if (erq->pointer) { 2921 if (erq->pointer && erq->length > 0) {
2922 priv->keys[index].len = cpu_to_le16(xlen); 2922 priv->keys[index].len = cpu_to_le16(xlen);
2923 memset(priv->keys[index].data, 0, 2923 memset(priv->keys[index].data, 0,
2924 sizeof(priv->keys[index].data)); 2924 sizeof(priv->keys[index].data));
diff --git a/drivers/net/wireless/spectrum_cs.c b/drivers/net/wireless/spectrum_cs.c
index 15465278c789..7f78b7801fb3 100644
--- a/drivers/net/wireless/spectrum_cs.c
+++ b/drivers/net/wireless/spectrum_cs.c
@@ -34,8 +34,6 @@
34 34
35#include "orinoco.h" 35#include "orinoco.h"
36 36
37static unsigned char *primsym;
38static unsigned char *secsym;
39static const char primary_fw_name[] = "symbol_sp24t_prim_fw"; 37static const char primary_fw_name[] = "symbol_sp24t_prim_fw";
40static const char secondary_fw_name[] = "symbol_sp24t_sec_fw"; 38static const char secondary_fw_name[] = "symbol_sp24t_sec_fw";
41 39
@@ -440,7 +438,7 @@ spectrum_load_blocks(hermes_t *hw, const struct dblock *first_block)
440 */ 438 */
441static int 439static int
442spectrum_dl_image(hermes_t *hw, struct pcmcia_device *link, 440spectrum_dl_image(hermes_t *hw, struct pcmcia_device *link,
443 const unsigned char *image) 441 const unsigned char *image, int secondary)
444{ 442{
445 int ret; 443 int ret;
446 const unsigned char *ptr; 444 const unsigned char *ptr;
@@ -455,7 +453,7 @@ spectrum_dl_image(hermes_t *hw, struct pcmcia_device *link,
455 first_block = (const struct dblock *) ptr; 453 first_block = (const struct dblock *) ptr;
456 454
457 /* Read the PDA */ 455 /* Read the PDA */
458 if (image != primsym) { 456 if (secondary) {
459 ret = spectrum_read_pda(hw, pda, sizeof(pda)); 457 ret = spectrum_read_pda(hw, pda, sizeof(pda));
460 if (ret) 458 if (ret)
461 return ret; 459 return ret;
@@ -472,7 +470,7 @@ spectrum_dl_image(hermes_t *hw, struct pcmcia_device *link,
472 return ret; 470 return ret;
473 471
474 /* Write the PDA to the adapter */ 472 /* Write the PDA to the adapter */
475 if (image != primsym) { 473 if (secondary) {
476 ret = spectrum_apply_pda(hw, first_block, pda); 474 ret = spectrum_apply_pda(hw, first_block, pda);
477 if (ret) 475 if (ret)
478 return ret; 476 return ret;
@@ -487,7 +485,7 @@ spectrum_dl_image(hermes_t *hw, struct pcmcia_device *link,
487 ret = hermes_init(hw); 485 ret = hermes_init(hw);
488 486
489 /* hermes_reset() should return 0 with the secondary firmware */ 487 /* hermes_reset() should return 0 with the secondary firmware */
490 if (image != primsym && ret != 0) 488 if (secondary && ret != 0)
491 return -ENODEV; 489 return -ENODEV;
492 490
493 /* And this should work with any firmware */ 491 /* And this should work with any firmware */
@@ -509,33 +507,30 @@ spectrum_dl_firmware(hermes_t *hw, struct pcmcia_device *link)
509 const struct firmware *fw_entry; 507 const struct firmware *fw_entry;
510 508
511 if (request_firmware(&fw_entry, primary_fw_name, 509 if (request_firmware(&fw_entry, primary_fw_name,
512 &handle_to_dev(link)) == 0) { 510 &handle_to_dev(link)) != 0) {
513 primsym = fw_entry->data;
514 } else {
515 printk(KERN_ERR PFX "Cannot find firmware: %s\n", 511 printk(KERN_ERR PFX "Cannot find firmware: %s\n",
516 primary_fw_name); 512 primary_fw_name);
517 return -ENOENT; 513 return -ENOENT;
518 } 514 }
519 515
520 if (request_firmware(&fw_entry, secondary_fw_name,
521 &handle_to_dev(link)) == 0) {
522 secsym = fw_entry->data;
523 } else {
524 printk(KERN_ERR PFX "Cannot find firmware: %s\n",
525 secondary_fw_name);
526 return -ENOENT;
527 }
528
529 /* Load primary firmware */ 516 /* Load primary firmware */
530 ret = spectrum_dl_image(hw, link, primsym); 517 ret = spectrum_dl_image(hw, link, fw_entry->data, 0);
518 release_firmware(fw_entry);
531 if (ret) { 519 if (ret) {
532 printk(KERN_ERR PFX "Primary firmware download failed\n"); 520 printk(KERN_ERR PFX "Primary firmware download failed\n");
533 return ret; 521 return ret;
534 } 522 }
535 523
536 /* Load secondary firmware */ 524 if (request_firmware(&fw_entry, secondary_fw_name,
537 ret = spectrum_dl_image(hw, link, secsym); 525 &handle_to_dev(link)) != 0) {
526 printk(KERN_ERR PFX "Cannot find firmware: %s\n",
527 secondary_fw_name);
528 return -ENOENT;
529 }
538 530
531 /* Load secondary firmware */
532 ret = spectrum_dl_image(hw, link, fw_entry->data, 1);
533 release_firmware(fw_entry);
539 if (ret) { 534 if (ret) {
540 printk(KERN_ERR PFX "Secondary firmware download failed\n"); 535 printk(KERN_ERR PFX "Secondary firmware download failed\n");
541 } 536 }
diff --git a/drivers/net/wireless/zd1201.c b/drivers/net/wireless/zd1201.c
index 662ecc8a33ff..c52e9bcf8d02 100644
--- a/drivers/net/wireless/zd1201.c
+++ b/drivers/net/wireless/zd1201.c
@@ -1820,6 +1820,8 @@ static int zd1201_probe(struct usb_interface *interface,
1820 zd->dev->name); 1820 zd->dev->name);
1821 1821
1822 usb_set_intfdata(interface, zd); 1822 usb_set_intfdata(interface, zd);
1823 zd1201_enable(zd); /* zd1201 likes to startup enabled, */
1824 zd1201_disable(zd); /* interfering with all the wifis in range */
1823 return 0; 1825 return 0;
1824 1826
1825err_net: 1827err_net:
diff --git a/drivers/net/wireless/zd1211rw/Kconfig b/drivers/net/wireless/zd1211rw/Kconfig
new file mode 100644
index 000000000000..66ed55bc5460
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/Kconfig
@@ -0,0 +1,19 @@
1config ZD1211RW
2 tristate "ZyDAS ZD1211/ZD1211B USB-wireless support"
3 depends on USB && IEEE80211 && IEEE80211_SOFTMAC && NET_RADIO && EXPERIMENTAL
4 select FW_LOADER
5 ---help---
6 This is an experimental driver for the ZyDAS ZD1211/ZD1211B wireless
7 chip, present in many USB-wireless adapters.
8
9 Device firmware is required alongside this driver. You can download the
10 firmware distribution from http://zd1211.ath.cx/get-firmware
11
12config ZD1211RW_DEBUG
13 bool "ZyDAS ZD1211 debugging"
14 depends on ZD1211RW
15 ---help---
16 ZD1211 debugging messages. Choosing Y will result in additional debug
17 messages being saved to your kernel logs, which may help debug any
18 problems.
19
diff --git a/drivers/net/wireless/zd1211rw/Makefile b/drivers/net/wireless/zd1211rw/Makefile
new file mode 100644
index 000000000000..500314fc74d2
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/Makefile
@@ -0,0 +1,11 @@
1obj-$(CONFIG_ZD1211RW) += zd1211rw.o
2
3zd1211rw-objs := zd_chip.o zd_ieee80211.o \
4 zd_mac.o zd_netdev.o \
5 zd_rf_al2230.o zd_rf_rf2959.o \
6 zd_rf.o zd_usb.o zd_util.o
7
8ifeq ($(CONFIG_ZD1211RW_DEBUG),y)
9EXTRA_CFLAGS += -DDEBUG
10endif
11
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c
new file mode 100644
index 000000000000..da9d06bdb818
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_chip.c
@@ -0,0 +1,1615 @@
1/* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18/* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25
26#include "zd_def.h"
27#include "zd_chip.h"
28#include "zd_ieee80211.h"
29#include "zd_mac.h"
30#include "zd_rf.h"
31#include "zd_util.h"
32
33void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36{
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41}
42
43void zd_chip_clear(struct zd_chip *chip)
44{
45 mutex_lock(&chip->mutex);
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_unlock(&chip->mutex);
49 mutex_destroy(&chip->mutex);
50 memset(chip, 0, sizeof(*chip));
51}
52
53static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
54{
55 return scnprintf(buffer, size, "%02x-%02x-%02x",
56 addr[0], addr[1], addr[2]);
57}
58
59/* Prints an identifier line, which will support debugging. */
60static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
61{
62 int i = 0;
63
64 i = scnprintf(buffer, size, "zd1211%s chip ",
65 chip->is_zd1211b ? "b" : "");
66 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
67 i += scnprintf(buffer+i, size-i, " ");
68 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c", chip->pa_type,
72 chip->patch_cck_gain ? 'g' : '-',
73 chip->patch_cr157 ? '7' : '-',
74 chip->patch_6m_band_edge ? '6' : '-');
75 return i;
76}
77
78static void print_id(struct zd_chip *chip)
79{
80 char buffer[80];
81
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
85}
86
87/* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
89 */
90int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
91 unsigned int count)
92{
93 int r;
94 int i;
95 zd_addr_t *a16 = (zd_addr_t *)NULL;
96 u16 *v16;
97 unsigned int count16;
98
99 if (count > USB_MAX_IOREAD32_COUNT)
100 return -EINVAL;
101
102 /* Allocate a single memory block for values and addresses. */
103 count16 = 2*count;
104 a16 = (zd_addr_t *)kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
105 GFP_NOFS);
106 if (!a16) {
107 dev_dbg_f(zd_chip_dev(chip),
108 "error ENOMEM in allocation of a16\n");
109 r = -ENOMEM;
110 goto out;
111 }
112 v16 = (u16 *)(a16 + count16);
113
114 for (i = 0; i < count; i++) {
115 int j = 2*i;
116 /* We read the high word always first. */
117 a16[j] = zd_inc_word(addr[i]);
118 a16[j+1] = addr[i];
119 }
120
121 r = zd_ioread16v_locked(chip, v16, a16, count16);
122 if (r) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error: zd_ioread16v_locked. Error number %d\n", r);
125 goto out;
126 }
127
128 for (i = 0; i < count; i++) {
129 int j = 2*i;
130 values[i] = (v16[j] << 16) | v16[j+1];
131 }
132
133out:
134 kfree((void *)a16);
135 return r;
136}
137
138int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
139 unsigned int count)
140{
141 int i, j, r;
142 struct zd_ioreq16 *ioreqs16;
143 unsigned int count16;
144
145 ZD_ASSERT(mutex_is_locked(&chip->mutex));
146
147 if (count == 0)
148 return 0;
149 if (count > USB_MAX_IOWRITE32_COUNT)
150 return -EINVAL;
151
152 /* Allocate a single memory block for values and addresses. */
153 count16 = 2*count;
154 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
155 if (!ioreqs16) {
156 r = -ENOMEM;
157 dev_dbg_f(zd_chip_dev(chip),
158 "error %d in ioreqs16 allocation\n", r);
159 goto out;
160 }
161
162 for (i = 0; i < count; i++) {
163 j = 2*i;
164 /* We write the high word always first. */
165 ioreqs16[j].value = ioreqs[i].value >> 16;
166 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
167 ioreqs16[j+1].value = ioreqs[i].value;
168 ioreqs16[j+1].addr = ioreqs[i].addr;
169 }
170
171 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
172#ifdef DEBUG
173 if (r) {
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in zd_usb_write16v\n", r);
176 }
177#endif /* DEBUG */
178out:
179 kfree(ioreqs16);
180 return r;
181}
182
183int zd_iowrite16a_locked(struct zd_chip *chip,
184 const struct zd_ioreq16 *ioreqs, unsigned int count)
185{
186 int r;
187 unsigned int i, j, t, max;
188
189 ZD_ASSERT(mutex_is_locked(&chip->mutex));
190 for (i = 0; i < count; i += j + t) {
191 t = 0;
192 max = count-i;
193 if (max > USB_MAX_IOWRITE16_COUNT)
194 max = USB_MAX_IOWRITE16_COUNT;
195 for (j = 0; j < max; j++) {
196 if (!ioreqs[i+j].addr) {
197 t = 1;
198 break;
199 }
200 }
201
202 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
203 if (r) {
204 dev_dbg_f(zd_chip_dev(chip),
205 "error zd_usb_iowrite16v. Error number %d\n",
206 r);
207 return r;
208 }
209 }
210
211 return 0;
212}
213
214/* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
217 */
218int zd_iowrite32a_locked(struct zd_chip *chip,
219 const struct zd_ioreq32 *ioreqs, unsigned int count)
220{
221 int r;
222 unsigned int i, j, t, max;
223
224 for (i = 0; i < count; i += j + t) {
225 t = 0;
226 max = count-i;
227 if (max > USB_MAX_IOWRITE32_COUNT)
228 max = USB_MAX_IOWRITE32_COUNT;
229 for (j = 0; j < max; j++) {
230 if (!ioreqs[i+j].addr) {
231 t = 1;
232 break;
233 }
234 }
235
236 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
237 if (r) {
238 dev_dbg_f(zd_chip_dev(chip),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r);
241 return r;
242 }
243 }
244
245 return 0;
246}
247
248int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
249{
250 int r;
251
252 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
253 mutex_lock(&chip->mutex);
254 r = zd_ioread16_locked(chip, value, addr);
255 mutex_unlock(&chip->mutex);
256 return r;
257}
258
259int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
260{
261 int r;
262
263 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
264 mutex_lock(&chip->mutex);
265 r = zd_ioread32_locked(chip, value, addr);
266 mutex_unlock(&chip->mutex);
267 return r;
268}
269
270int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
271{
272 int r;
273
274 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
275 mutex_lock(&chip->mutex);
276 r = zd_iowrite16_locked(chip, value, addr);
277 mutex_unlock(&chip->mutex);
278 return r;
279}
280
281int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
282{
283 int r;
284
285 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
286 mutex_lock(&chip->mutex);
287 r = zd_iowrite32_locked(chip, value, addr);
288 mutex_unlock(&chip->mutex);
289 return r;
290}
291
292int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
293 u32 *values, unsigned int count)
294{
295 int r;
296
297 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
298 mutex_lock(&chip->mutex);
299 r = zd_ioread32v_locked(chip, values, addresses, count);
300 mutex_unlock(&chip->mutex);
301 return r;
302}
303
304int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
305 unsigned int count)
306{
307 int r;
308
309 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
310 mutex_lock(&chip->mutex);
311 r = zd_iowrite32a_locked(chip, ioreqs, count);
312 mutex_unlock(&chip->mutex);
313 return r;
314}
315
316static int read_pod(struct zd_chip *chip, u8 *rf_type)
317{
318 int r;
319 u32 value;
320
321 ZD_ASSERT(mutex_is_locked(&chip->mutex));
322 r = zd_ioread32_locked(chip, &value, E2P_POD);
323 if (r)
324 goto error;
325 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
326
327 /* FIXME: AL2230 handling (Bit 7 in POD) */
328 *rf_type = value & 0x0f;
329 chip->pa_type = (value >> 16) & 0x0f;
330 chip->patch_cck_gain = (value >> 8) & 0x1;
331 chip->patch_cr157 = (value >> 13) & 0x1;
332 chip->patch_6m_band_edge = (value >> 21) & 0x1;
333
334 dev_dbg_f(zd_chip_dev(chip),
335 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
336 "patch 6M %d\n",
337 zd_rf_name(*rf_type), *rf_type,
338 chip->pa_type, chip->patch_cck_gain,
339 chip->patch_cr157, chip->patch_6m_band_edge);
340 return 0;
341error:
342 *rf_type = 0;
343 chip->pa_type = 0;
344 chip->patch_cck_gain = 0;
345 chip->patch_cr157 = 0;
346 chip->patch_6m_band_edge = 0;
347 return r;
348}
349
350static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
351 const zd_addr_t *addr)
352{
353 int r;
354 u32 parts[2];
355
356 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
357 if (r) {
358 dev_dbg_f(zd_chip_dev(chip),
359 "error: couldn't read e2p macs. Error number %d\n", r);
360 return r;
361 }
362
363 mac_addr[0] = parts[0];
364 mac_addr[1] = parts[0] >> 8;
365 mac_addr[2] = parts[0] >> 16;
366 mac_addr[3] = parts[0] >> 24;
367 mac_addr[4] = parts[1];
368 mac_addr[5] = parts[1] >> 8;
369
370 return 0;
371}
372
373static int read_e2p_mac_addr(struct zd_chip *chip)
374{
375 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
376
377 ZD_ASSERT(mutex_is_locked(&chip->mutex));
378 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
379}
380
381/* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
382 * CR_MAC_ADDR_P2 must be overwritten
383 */
384void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
385{
386 mutex_lock(&chip->mutex);
387 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
388 mutex_unlock(&chip->mutex);
389}
390
391static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
392{
393 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
394 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
395}
396
397int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
398{
399 int r;
400
401 dev_dbg_f(zd_chip_dev(chip), "\n");
402 mutex_lock(&chip->mutex);
403 r = read_mac_addr(chip, mac_addr);
404 mutex_unlock(&chip->mutex);
405 return r;
406}
407
408int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
409{
410 int r;
411 struct zd_ioreq32 reqs[2] = {
412 [0] = { .addr = CR_MAC_ADDR_P1 },
413 [1] = { .addr = CR_MAC_ADDR_P2 },
414 };
415
416 reqs[0].value = (mac_addr[3] << 24)
417 | (mac_addr[2] << 16)
418 | (mac_addr[1] << 8)
419 | mac_addr[0];
420 reqs[1].value = (mac_addr[5] << 8)
421 | mac_addr[4];
422
423 dev_dbg_f(zd_chip_dev(chip),
424 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
425
426 mutex_lock(&chip->mutex);
427 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
428#ifdef DEBUG
429 {
430 u8 tmp[ETH_ALEN];
431 read_mac_addr(chip, tmp);
432 }
433#endif /* DEBUG */
434 mutex_unlock(&chip->mutex);
435 return r;
436}
437
438int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
439{
440 int r;
441 u32 value;
442
443 mutex_lock(&chip->mutex);
444 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
445 mutex_unlock(&chip->mutex);
446 if (r)
447 return r;
448
449 *regdomain = value >> 16;
450 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
451
452 return 0;
453}
454
455static int read_values(struct zd_chip *chip, u8 *values, size_t count,
456 zd_addr_t e2p_addr, u32 guard)
457{
458 int r;
459 int i;
460 u32 v;
461
462 ZD_ASSERT(mutex_is_locked(&chip->mutex));
463 for (i = 0;;) {
464 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
465 if (r)
466 return r;
467 v -= guard;
468 if (i+4 < count) {
469 values[i++] = v;
470 values[i++] = v >> 8;
471 values[i++] = v >> 16;
472 values[i++] = v >> 24;
473 continue;
474 }
475 for (;i < count; i++)
476 values[i] = v >> (8*(i%3));
477 return 0;
478 }
479}
480
481static int read_pwr_cal_values(struct zd_chip *chip)
482{
483 return read_values(chip, chip->pwr_cal_values,
484 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
485 0);
486}
487
488static int read_pwr_int_values(struct zd_chip *chip)
489{
490 return read_values(chip, chip->pwr_int_values,
491 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
492 E2P_PWR_INT_GUARD);
493}
494
495static int read_ofdm_cal_values(struct zd_chip *chip)
496{
497 int r;
498 int i;
499 static const zd_addr_t addresses[] = {
500 E2P_36M_CAL_VALUE1,
501 E2P_48M_CAL_VALUE1,
502 E2P_54M_CAL_VALUE1,
503 };
504
505 for (i = 0; i < 3; i++) {
506 r = read_values(chip, chip->ofdm_cal_values[i],
507 E2P_CHANNEL_COUNT, addresses[i], 0);
508 if (r)
509 return r;
510 }
511 return 0;
512}
513
514static int read_cal_int_tables(struct zd_chip *chip)
515{
516 int r;
517
518 r = read_pwr_cal_values(chip);
519 if (r)
520 return r;
521 r = read_pwr_int_values(chip);
522 if (r)
523 return r;
524 r = read_ofdm_cal_values(chip);
525 if (r)
526 return r;
527 return 0;
528}
529
530/* phy means physical registers */
531int zd_chip_lock_phy_regs(struct zd_chip *chip)
532{
533 int r;
534 u32 tmp;
535
536 ZD_ASSERT(mutex_is_locked(&chip->mutex));
537 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
538 if (r) {
539 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
540 return r;
541 }
542
543 dev_dbg_f(zd_chip_dev(chip),
544 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
545 tmp &= ~UNLOCK_PHY_REGS;
546
547 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
548 if (r)
549 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
550 return r;
551}
552
553int zd_chip_unlock_phy_regs(struct zd_chip *chip)
554{
555 int r;
556 u32 tmp;
557
558 ZD_ASSERT(mutex_is_locked(&chip->mutex));
559 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
560 if (r) {
561 dev_err(zd_chip_dev(chip),
562 "error ioread32(CR_REG1): %d\n", r);
563 return r;
564 }
565
566 dev_dbg_f(zd_chip_dev(chip),
567 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
568 tmp |= UNLOCK_PHY_REGS;
569
570 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
571 if (r)
572 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
573 return r;
574}
575
576/* CR157 can be optionally patched by the EEPROM */
577static int patch_cr157(struct zd_chip *chip)
578{
579 int r;
580 u32 value;
581
582 if (!chip->patch_cr157)
583 return 0;
584
585 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
586 if (r)
587 return r;
588
589 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
590 return zd_iowrite32_locked(chip, value >> 8, CR157);
591}
592
593/*
594 * 6M band edge can be optionally overwritten for certain RF's
595 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
596 * bit (for AL2230, AL2230S)
597 */
598static int patch_6m_band_edge(struct zd_chip *chip, int channel)
599{
600 struct zd_ioreq16 ioreqs[] = {
601 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
602 { CR47, 0x1e },
603 };
604
605 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
606 return 0;
607
608 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
609 if (channel == 1 || channel == 11)
610 ioreqs[0].value = 0x12;
611
612 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
613 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
614}
615
616static int zd1211_hw_reset_phy(struct zd_chip *chip)
617{
618 static const struct zd_ioreq16 ioreqs[] = {
619 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
620 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
621 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
622 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
623 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
624 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
625 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
626 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
627 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
628 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
629 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
630 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
631 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
632 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
633 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
634 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
635 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
636 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
637 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
638 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
639 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
640 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
641 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
642 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
643 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
644 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
645 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
646 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
647 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
648 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
649 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
650 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
651 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
652 { },
653 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
654 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
655 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
656 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
657 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
658 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
659 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
660 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
661 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
662 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
663 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
664 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
665 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
666 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
667 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
668 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
669 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
670 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
671 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
672 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
673 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
674 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
675 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
676 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
677 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
678 /* Note: CR204 must lead the CR203 */
679 { CR204, 0x7d },
680 { },
681 { CR203, 0x30 },
682 };
683
684 int r, t;
685
686 dev_dbg_f(zd_chip_dev(chip), "\n");
687
688 r = zd_chip_lock_phy_regs(chip);
689 if (r)
690 goto out;
691
692 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
693 if (r)
694 goto unlock;
695
696 r = patch_cr157(chip);
697unlock:
698 t = zd_chip_unlock_phy_regs(chip);
699 if (t && !r)
700 r = t;
701out:
702 return r;
703}
704
705static int zd1211b_hw_reset_phy(struct zd_chip *chip)
706{
707 static const struct zd_ioreq16 ioreqs[] = {
708 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
709 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
710 { CR10, 0x81 },
711 /* power control { { CR11, 1 << 6 }, */
712 { CR11, 0x00 },
713 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
714 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
715 { CR18, 0x0a }, { CR19, 0x48 },
716 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
717 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
718 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
719 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
720 { CR30, 0x49 }, /* jointly decoder, no ASIC */
721 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
722 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
723 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
724 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
725 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
726 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
727 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
728 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
729 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
730 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
731 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
732 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
733 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
734 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
735 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
736 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
737 { CR94, 0x01 },
738 { CR95, 0x20 }, /* ZD1211B */
739 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
740 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
741 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
742 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
743 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
744 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
745 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
746 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
747 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
748 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
749 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
750 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
751 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
752 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
753 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
754 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
755 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
756 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
757 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
758 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
759 { CR170, 0xba }, { CR171, 0xba },
760 /* Note: CR204 must lead the CR203 */
761 { CR204, 0x7d },
762 {},
763 { CR203, 0x30 },
764 };
765
766 int r, t;
767
768 dev_dbg_f(zd_chip_dev(chip), "\n");
769
770 r = zd_chip_lock_phy_regs(chip);
771 if (r)
772 goto out;
773
774 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
775 if (r)
776 goto unlock;
777
778 r = patch_cr157(chip);
779unlock:
780 t = zd_chip_unlock_phy_regs(chip);
781 if (t && !r)
782 r = t;
783out:
784 return r;
785}
786
787static int hw_reset_phy(struct zd_chip *chip)
788{
789 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
790 zd1211_hw_reset_phy(chip);
791}
792
793static int zd1211_hw_init_hmac(struct zd_chip *chip)
794{
795 static const struct zd_ioreq32 ioreqs[] = {
796 { CR_ACK_TIMEOUT_EXT, 0x20 },
797 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
798 { CR_ZD1211_RETRY_MAX, 0x2 },
799 { CR_SNIFFER_ON, 0 },
800 { CR_RX_FILTER, STA_RX_FILTER },
801 { CR_GROUP_HASH_P1, 0x00 },
802 { CR_GROUP_HASH_P2, 0x80000000 },
803 { CR_REG1, 0xa4 },
804 { CR_ADDA_PWR_DWN, 0x7f },
805 { CR_BCN_PLCP_CFG, 0x00f00401 },
806 { CR_PHY_DELAY, 0x00 },
807 { CR_ACK_TIMEOUT_EXT, 0x80 },
808 { CR_ADDA_PWR_DWN, 0x00 },
809 { CR_ACK_TIME_80211, 0x100 },
810 { CR_IFS_VALUE, 0x547c032 },
811 { CR_RX_PE_DELAY, 0x70 },
812 { CR_PS_CTRL, 0x10000000 },
813 { CR_RTS_CTS_RATE, 0x02030203 },
814 { CR_RX_THRESHOLD, 0x000c0640 },
815 { CR_AFTER_PNP, 0x1 },
816 { CR_WEP_PROTECT, 0x114 },
817 };
818
819 int r;
820
821 dev_dbg_f(zd_chip_dev(chip), "\n");
822 ZD_ASSERT(mutex_is_locked(&chip->mutex));
823 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
824#ifdef DEBUG
825 if (r) {
826 dev_err(zd_chip_dev(chip),
827 "error in zd_iowrite32a_locked. Error number %d\n", r);
828 }
829#endif /* DEBUG */
830 return r;
831}
832
833static int zd1211b_hw_init_hmac(struct zd_chip *chip)
834{
835 static const struct zd_ioreq32 ioreqs[] = {
836 { CR_ACK_TIMEOUT_EXT, 0x20 },
837 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
838 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
839 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
840 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
841 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
842 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
843 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
844 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
845 { CR_ZD1211B_TXOP, 0x01800824 },
846 { CR_SNIFFER_ON, 0 },
847 { CR_RX_FILTER, STA_RX_FILTER },
848 { CR_GROUP_HASH_P1, 0x00 },
849 { CR_GROUP_HASH_P2, 0x80000000 },
850 { CR_REG1, 0xa4 },
851 { CR_ADDA_PWR_DWN, 0x7f },
852 { CR_BCN_PLCP_CFG, 0x00f00401 },
853 { CR_PHY_DELAY, 0x00 },
854 { CR_ACK_TIMEOUT_EXT, 0x80 },
855 { CR_ADDA_PWR_DWN, 0x00 },
856 { CR_ACK_TIME_80211, 0x100 },
857 { CR_IFS_VALUE, 0x547c032 },
858 { CR_RX_PE_DELAY, 0x70 },
859 { CR_PS_CTRL, 0x10000000 },
860 { CR_RTS_CTS_RATE, 0x02030203 },
861 { CR_RX_THRESHOLD, 0x000c0640 },
862 { CR_AFTER_PNP, 0x1 },
863 { CR_WEP_PROTECT, 0x114 },
864 };
865
866 int r;
867
868 dev_dbg_f(zd_chip_dev(chip), "\n");
869 ZD_ASSERT(mutex_is_locked(&chip->mutex));
870 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
871 if (r) {
872 dev_dbg_f(zd_chip_dev(chip),
873 "error in zd_iowrite32a_locked. Error number %d\n", r);
874 }
875 return r;
876}
877
878static int hw_init_hmac(struct zd_chip *chip)
879{
880 return chip->is_zd1211b ?
881 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
882}
883
884struct aw_pt_bi {
885 u32 atim_wnd_period;
886 u32 pre_tbtt;
887 u32 beacon_interval;
888};
889
890static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
891{
892 int r;
893 static const zd_addr_t aw_pt_bi_addr[] =
894 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
895 u32 values[3];
896
897 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
898 ARRAY_SIZE(aw_pt_bi_addr));
899 if (r) {
900 memset(s, 0, sizeof(*s));
901 return r;
902 }
903
904 s->atim_wnd_period = values[0];
905 s->pre_tbtt = values[1];
906 s->beacon_interval = values[2];
907 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
908 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
909 return 0;
910}
911
912static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
913{
914 struct zd_ioreq32 reqs[3];
915
916 if (s->beacon_interval <= 5)
917 s->beacon_interval = 5;
918 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
919 s->pre_tbtt = s->beacon_interval - 1;
920 if (s->atim_wnd_period >= s->pre_tbtt)
921 s->atim_wnd_period = s->pre_tbtt - 1;
922
923 reqs[0].addr = CR_ATIM_WND_PERIOD;
924 reqs[0].value = s->atim_wnd_period;
925 reqs[1].addr = CR_PRE_TBTT;
926 reqs[1].value = s->pre_tbtt;
927 reqs[2].addr = CR_BCN_INTERVAL;
928 reqs[2].value = s->beacon_interval;
929
930 dev_dbg_f(zd_chip_dev(chip),
931 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
932 s->beacon_interval);
933 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
934}
935
936
937static int set_beacon_interval(struct zd_chip *chip, u32 interval)
938{
939 int r;
940 struct aw_pt_bi s;
941
942 ZD_ASSERT(mutex_is_locked(&chip->mutex));
943 r = get_aw_pt_bi(chip, &s);
944 if (r)
945 return r;
946 s.beacon_interval = interval;
947 return set_aw_pt_bi(chip, &s);
948}
949
950int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
951{
952 int r;
953
954 mutex_lock(&chip->mutex);
955 r = set_beacon_interval(chip, interval);
956 mutex_unlock(&chip->mutex);
957 return r;
958}
959
960static int hw_init(struct zd_chip *chip)
961{
962 int r;
963
964 dev_dbg_f(zd_chip_dev(chip), "\n");
965 ZD_ASSERT(mutex_is_locked(&chip->mutex));
966 r = hw_reset_phy(chip);
967 if (r)
968 return r;
969
970 r = hw_init_hmac(chip);
971 if (r)
972 return r;
973 r = set_beacon_interval(chip, 100);
974 if (r)
975 return r;
976 return 0;
977}
978
979#ifdef DEBUG
980static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
981 const char *addr_string)
982{
983 int r;
984 u32 value;
985
986 r = zd_ioread32_locked(chip, &value, addr);
987 if (r) {
988 dev_dbg_f(zd_chip_dev(chip),
989 "error reading %s. Error number %d\n", addr_string, r);
990 return r;
991 }
992
993 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
994 addr_string, (unsigned int)value);
995 return 0;
996}
997
998static int test_init(struct zd_chip *chip)
999{
1000 int r;
1001
1002 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1003 if (r)
1004 return r;
1005 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1006 if (r)
1007 return r;
1008 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1009}
1010
1011static void dump_fw_registers(struct zd_chip *chip)
1012{
1013 static const zd_addr_t addr[4] = {
1014 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
1015 FW_LINK_STATUS
1016 };
1017
1018 int r;
1019 u16 values[4];
1020
1021 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1022 ARRAY_SIZE(addr));
1023 if (r) {
1024 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1025 r);
1026 return;
1027 }
1028
1029 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1030 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1031 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1032 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1033}
1034#endif /* DEBUG */
1035
1036static int print_fw_version(struct zd_chip *chip)
1037{
1038 int r;
1039 u16 version;
1040
1041 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1042 if (r)
1043 return r;
1044
1045 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1046 return 0;
1047}
1048
1049static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1050{
1051 u32 rates;
1052 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1053 /* This sets the mandatory rates, which only depend from the standard
1054 * that the device is supporting. Until further notice we should try
1055 * to support 802.11g also for full speed USB.
1056 */
1057 switch (std) {
1058 case IEEE80211B:
1059 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1060 break;
1061 case IEEE80211G:
1062 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1063 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1064 break;
1065 default:
1066 return -EINVAL;
1067 }
1068 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1069}
1070
1071int zd_chip_enable_hwint(struct zd_chip *chip)
1072{
1073 int r;
1074
1075 mutex_lock(&chip->mutex);
1076 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1077 mutex_unlock(&chip->mutex);
1078 return r;
1079}
1080
1081static int disable_hwint(struct zd_chip *chip)
1082{
1083 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1084}
1085
1086int zd_chip_disable_hwint(struct zd_chip *chip)
1087{
1088 int r;
1089
1090 mutex_lock(&chip->mutex);
1091 r = disable_hwint(chip);
1092 mutex_unlock(&chip->mutex);
1093 return r;
1094}
1095
1096int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1097{
1098 int r;
1099 u8 rf_type;
1100
1101 dev_dbg_f(zd_chip_dev(chip), "\n");
1102
1103 mutex_lock(&chip->mutex);
1104 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1105
1106#ifdef DEBUG
1107 r = test_init(chip);
1108 if (r)
1109 goto out;
1110#endif
1111 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1112 if (r)
1113 goto out;
1114
1115 r = zd_usb_init_hw(&chip->usb);
1116 if (r)
1117 goto out;
1118
1119 /* GPI is always disabled, also in the other driver.
1120 */
1121 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1122 if (r)
1123 goto out;
1124 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1125 if (r)
1126 goto out;
1127 /* Currently we support IEEE 802.11g for full and high speed USB.
1128 * It might be discussed, whether we should suppport pure b mode for
1129 * full speed USB.
1130 */
1131 r = set_mandatory_rates(chip, IEEE80211G);
1132 if (r)
1133 goto out;
1134 /* Disabling interrupts is certainly a smart thing here.
1135 */
1136 r = disable_hwint(chip);
1137 if (r)
1138 goto out;
1139 r = read_pod(chip, &rf_type);
1140 if (r)
1141 goto out;
1142 r = hw_init(chip);
1143 if (r)
1144 goto out;
1145 r = zd_rf_init_hw(&chip->rf, rf_type);
1146 if (r)
1147 goto out;
1148
1149 r = print_fw_version(chip);
1150 if (r)
1151 goto out;
1152
1153#ifdef DEBUG
1154 dump_fw_registers(chip);
1155 r = test_init(chip);
1156 if (r)
1157 goto out;
1158#endif /* DEBUG */
1159
1160 r = read_e2p_mac_addr(chip);
1161 if (r)
1162 goto out;
1163
1164 r = read_cal_int_tables(chip);
1165 if (r)
1166 goto out;
1167
1168 print_id(chip);
1169out:
1170 mutex_unlock(&chip->mutex);
1171 return r;
1172}
1173
1174static int update_pwr_int(struct zd_chip *chip, u8 channel)
1175{
1176 u8 value = chip->pwr_int_values[channel - 1];
1177 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1178 channel, value);
1179 return zd_iowrite32_locked(chip, value, CR31);
1180}
1181
1182static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1183{
1184 u8 value = chip->pwr_cal_values[channel-1];
1185 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1186 channel, value);
1187 return zd_iowrite32_locked(chip, value, CR68);
1188}
1189
1190static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1191{
1192 struct zd_ioreq32 ioreqs[3];
1193
1194 ioreqs[0].addr = CR67;
1195 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1196 ioreqs[1].addr = CR66;
1197 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1198 ioreqs[2].addr = CR65;
1199 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1200
1201 dev_dbg_f(zd_chip_dev(chip),
1202 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1203 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1204 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1205}
1206
1207static int update_channel_integration_and_calibration(struct zd_chip *chip,
1208 u8 channel)
1209{
1210 int r;
1211
1212 r = update_pwr_int(chip, channel);
1213 if (r)
1214 return r;
1215 if (chip->is_zd1211b) {
1216 static const struct zd_ioreq32 ioreqs[] = {
1217 { CR69, 0x28 },
1218 {},
1219 { CR69, 0x2a },
1220 };
1221
1222 r = update_ofdm_cal(chip, channel);
1223 if (r)
1224 return r;
1225 r = update_pwr_cal(chip, channel);
1226 if (r)
1227 return r;
1228 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1229 if (r)
1230 return r;
1231 }
1232
1233 return 0;
1234}
1235
1236/* The CCK baseband gain can be optionally patched by the EEPROM */
1237static int patch_cck_gain(struct zd_chip *chip)
1238{
1239 int r;
1240 u32 value;
1241
1242 if (!chip->patch_cck_gain)
1243 return 0;
1244
1245 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1246 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1247 if (r)
1248 return r;
1249 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1250 return zd_iowrite32_locked(chip, value & 0xff, CR47);
1251}
1252
1253int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1254{
1255 int r, t;
1256
1257 mutex_lock(&chip->mutex);
1258 r = zd_chip_lock_phy_regs(chip);
1259 if (r)
1260 goto out;
1261 r = zd_rf_set_channel(&chip->rf, channel);
1262 if (r)
1263 goto unlock;
1264 r = update_channel_integration_and_calibration(chip, channel);
1265 if (r)
1266 goto unlock;
1267 r = patch_cck_gain(chip);
1268 if (r)
1269 goto unlock;
1270 r = patch_6m_band_edge(chip, channel);
1271 if (r)
1272 goto unlock;
1273 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1274unlock:
1275 t = zd_chip_unlock_phy_regs(chip);
1276 if (t && !r)
1277 r = t;
1278out:
1279 mutex_unlock(&chip->mutex);
1280 return r;
1281}
1282
1283u8 zd_chip_get_channel(struct zd_chip *chip)
1284{
1285 u8 channel;
1286
1287 mutex_lock(&chip->mutex);
1288 channel = chip->rf.channel;
1289 mutex_unlock(&chip->mutex);
1290 return channel;
1291}
1292
1293static u16 led_mask(int led)
1294{
1295 switch (led) {
1296 case 1:
1297 return LED1;
1298 case 2:
1299 return LED2;
1300 default:
1301 return 0;
1302 }
1303}
1304
1305static int read_led_reg(struct zd_chip *chip, u16 *status)
1306{
1307 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1308 return zd_ioread16_locked(chip, status, CR_LED);
1309}
1310
1311static int write_led_reg(struct zd_chip *chip, u16 status)
1312{
1313 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1314 return zd_iowrite16_locked(chip, status, CR_LED);
1315}
1316
1317int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status)
1318{
1319 int r, ret;
1320 u16 mask = led_mask(led);
1321 u16 reg;
1322
1323 if (!mask)
1324 return -EINVAL;
1325 mutex_lock(&chip->mutex);
1326 r = read_led_reg(chip, &reg);
1327 if (r)
1328 return r;
1329 switch (status) {
1330 case LED_STATUS:
1331 return (reg & mask) ? LED_ON : LED_OFF;
1332 case LED_OFF:
1333 reg &= ~mask;
1334 ret = LED_OFF;
1335 break;
1336 case LED_FLIP:
1337 reg ^= mask;
1338 ret = (reg&mask) ? LED_ON : LED_OFF;
1339 break;
1340 case LED_ON:
1341 reg |= mask;
1342 ret = LED_ON;
1343 break;
1344 default:
1345 return -EINVAL;
1346 }
1347 r = write_led_reg(chip, reg);
1348 if (r) {
1349 ret = r;
1350 goto out;
1351 }
1352out:
1353 mutex_unlock(&chip->mutex);
1354 return r;
1355}
1356
1357int zd_chip_led_flip(struct zd_chip *chip, int led,
1358 const unsigned int *phases_msecs, unsigned int count)
1359{
1360 int i, r;
1361 enum led_status status;
1362
1363 r = zd_chip_led_status(chip, led, LED_STATUS);
1364 if (r)
1365 return r;
1366 status = r;
1367 for (i = 0; i < count; i++) {
1368 r = zd_chip_led_status(chip, led, LED_FLIP);
1369 if (r < 0)
1370 goto out;
1371 msleep(phases_msecs[i]);
1372 }
1373
1374out:
1375 zd_chip_led_status(chip, led, status);
1376 return r;
1377}
1378
1379int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1380{
1381 int r;
1382
1383 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1384 return -EINVAL;
1385
1386 mutex_lock(&chip->mutex);
1387 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1388 mutex_unlock(&chip->mutex);
1389 return r;
1390}
1391
1392static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1393{
1394 static const u16 constants[] = {
1395 715, 655, 585, 540, 470, 410, 360, 315,
1396 270, 235, 205, 175, 150, 125, 105, 85,
1397 65, 50, 40, 25, 15
1398 };
1399
1400 int i;
1401 u32 x;
1402
1403 /* It seems that their quality parameter is somehow per signal
1404 * and is now transferred per bit.
1405 */
1406 switch (rate) {
1407 case ZD_OFDM_RATE_6M:
1408 case ZD_OFDM_RATE_12M:
1409 case ZD_OFDM_RATE_24M:
1410 size *= 2;
1411 break;
1412 case ZD_OFDM_RATE_9M:
1413 case ZD_OFDM_RATE_18M:
1414 case ZD_OFDM_RATE_36M:
1415 case ZD_OFDM_RATE_54M:
1416 size *= 4;
1417 size /= 3;
1418 break;
1419 case ZD_OFDM_RATE_48M:
1420 size *= 3;
1421 size /= 2;
1422 break;
1423 default:
1424 return -EINVAL;
1425 }
1426
1427 x = (10000 * status_quality)/size;
1428 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1429 if (x > constants[i])
1430 break;
1431 }
1432
1433 return i;
1434}
1435
1436static unsigned int log10times100(unsigned int x)
1437{
1438 static const u8 log10[] = {
1439 0,
1440 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1441 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1442 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1443 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1444 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1445 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1446 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1447 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1448 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1449 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1450 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1451 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1452 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1453 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1454 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1455 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1456 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1457 223, 223, 223, 224, 224, 224, 224,
1458 };
1459
1460 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1461}
1462
1463enum {
1464 MAX_CCK_EVM_DB = 45,
1465};
1466
1467static int cck_evm_db(u8 status_quality)
1468{
1469 return (20 * log10times100(status_quality)) / 100;
1470}
1471
1472static int cck_snr_db(u8 status_quality)
1473{
1474 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1475 ZD_ASSERT(r >= 0);
1476 return r;
1477}
1478
1479static int rx_qual_db(const void *rx_frame, unsigned int size,
1480 const struct rx_status *status)
1481{
1482 return (status->frame_status&ZD_RX_OFDM) ?
1483 ofdm_qual_db(status->signal_quality_ofdm,
1484 zd_ofdm_plcp_header_rate(rx_frame),
1485 size) :
1486 cck_snr_db(status->signal_quality_cck);
1487}
1488
1489u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1490 const struct rx_status *status)
1491{
1492 int r = rx_qual_db(rx_frame, size, status);
1493 if (r < 0)
1494 r = 0;
1495 r = (r * 100) / 14;
1496 if (r > 100)
1497 r = 100;
1498 return r;
1499}
1500
1501u8 zd_rx_strength_percent(u8 rssi)
1502{
1503 int r = (rssi*100) / 30;
1504 if (r > 100)
1505 r = 100;
1506 return (u8) r;
1507}
1508
1509u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1510{
1511 static const u16 ofdm_rates[] = {
1512 [ZD_OFDM_RATE_6M] = 60,
1513 [ZD_OFDM_RATE_9M] = 90,
1514 [ZD_OFDM_RATE_12M] = 120,
1515 [ZD_OFDM_RATE_18M] = 180,
1516 [ZD_OFDM_RATE_24M] = 240,
1517 [ZD_OFDM_RATE_36M] = 360,
1518 [ZD_OFDM_RATE_48M] = 480,
1519 [ZD_OFDM_RATE_54M] = 540,
1520 };
1521 u16 rate;
1522 if (status->frame_status & ZD_RX_OFDM) {
1523 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1524 rate = ofdm_rates[ofdm_rate & 0xf];
1525 } else {
1526 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1527 switch (cck_rate) {
1528 case ZD_CCK_SIGNAL_1M:
1529 rate = 10;
1530 break;
1531 case ZD_CCK_SIGNAL_2M:
1532 rate = 20;
1533 break;
1534 case ZD_CCK_SIGNAL_5M5:
1535 rate = 55;
1536 break;
1537 case ZD_CCK_SIGNAL_11M:
1538 rate = 110;
1539 break;
1540 default:
1541 rate = 0;
1542 }
1543 }
1544
1545 return rate;
1546}
1547
1548int zd_chip_switch_radio_on(struct zd_chip *chip)
1549{
1550 int r;
1551
1552 mutex_lock(&chip->mutex);
1553 r = zd_switch_radio_on(&chip->rf);
1554 mutex_unlock(&chip->mutex);
1555 return r;
1556}
1557
1558int zd_chip_switch_radio_off(struct zd_chip *chip)
1559{
1560 int r;
1561
1562 mutex_lock(&chip->mutex);
1563 r = zd_switch_radio_off(&chip->rf);
1564 mutex_unlock(&chip->mutex);
1565 return r;
1566}
1567
1568int zd_chip_enable_int(struct zd_chip *chip)
1569{
1570 int r;
1571
1572 mutex_lock(&chip->mutex);
1573 r = zd_usb_enable_int(&chip->usb);
1574 mutex_unlock(&chip->mutex);
1575 return r;
1576}
1577
1578void zd_chip_disable_int(struct zd_chip *chip)
1579{
1580 mutex_lock(&chip->mutex);
1581 zd_usb_disable_int(&chip->usb);
1582 mutex_unlock(&chip->mutex);
1583}
1584
1585int zd_chip_enable_rx(struct zd_chip *chip)
1586{
1587 int r;
1588
1589 mutex_lock(&chip->mutex);
1590 r = zd_usb_enable_rx(&chip->usb);
1591 mutex_unlock(&chip->mutex);
1592 return r;
1593}
1594
1595void zd_chip_disable_rx(struct zd_chip *chip)
1596{
1597 mutex_lock(&chip->mutex);
1598 zd_usb_disable_rx(&chip->usb);
1599 mutex_unlock(&chip->mutex);
1600}
1601
1602int zd_rfwritev_locked(struct zd_chip *chip,
1603 const u32* values, unsigned int count, u8 bits)
1604{
1605 int r;
1606 unsigned int i;
1607
1608 for (i = 0; i < count; i++) {
1609 r = zd_rfwrite_locked(chip, values[i], bits);
1610 if (r)
1611 return r;
1612 }
1613
1614 return 0;
1615}
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.h b/drivers/net/wireless/zd1211rw/zd_chip.h
new file mode 100644
index 000000000000..069d2b467339
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_chip.h
@@ -0,0 +1,827 @@
1/* zd_chip.h
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_CHIP_H
19#define _ZD_CHIP_H
20
21#include "zd_types.h"
22#include "zd_rf.h"
23#include "zd_usb.h"
24
25/* Header for the Media Access Controller (MAC) and the Baseband Processor
26 * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and
27 * adds a processor for handling the USB protocol.
28 */
29
30/* 8-bit hardware registers */
31#define CR0 CTL_REG(0x0000)
32#define CR1 CTL_REG(0x0004)
33#define CR2 CTL_REG(0x0008)
34#define CR3 CTL_REG(0x000C)
35
36#define CR5 CTL_REG(0x0010)
37/* bit 5: if set short preamble used
38 * bit 6: filter band - Japan channel 14 on, else off
39 */
40#define CR6 CTL_REG(0x0014)
41#define CR7 CTL_REG(0x0018)
42#define CR8 CTL_REG(0x001C)
43
44#define CR4 CTL_REG(0x0020)
45
46#define CR9 CTL_REG(0x0024)
47/* bit 2: antenna switch (together with CR10) */
48#define CR10 CTL_REG(0x0028)
49/* bit 1: antenna switch (together with CR9)
50 * RF2959 controls with CR11 radion on and off
51 */
52#define CR11 CTL_REG(0x002C)
53/* bit 6: TX power control for OFDM
54 * RF2959 controls with CR10 radio on and off
55 */
56#define CR12 CTL_REG(0x0030)
57#define CR13 CTL_REG(0x0034)
58#define CR14 CTL_REG(0x0038)
59#define CR15 CTL_REG(0x003C)
60#define CR16 CTL_REG(0x0040)
61#define CR17 CTL_REG(0x0044)
62#define CR18 CTL_REG(0x0048)
63#define CR19 CTL_REG(0x004C)
64#define CR20 CTL_REG(0x0050)
65#define CR21 CTL_REG(0x0054)
66#define CR22 CTL_REG(0x0058)
67#define CR23 CTL_REG(0x005C)
68#define CR24 CTL_REG(0x0060) /* CCA threshold */
69#define CR25 CTL_REG(0x0064)
70#define CR26 CTL_REG(0x0068)
71#define CR27 CTL_REG(0x006C)
72#define CR28 CTL_REG(0x0070)
73#define CR29 CTL_REG(0x0074)
74#define CR30 CTL_REG(0x0078)
75#define CR31 CTL_REG(0x007C) /* TX power control for RF in CCK mode */
76#define CR32 CTL_REG(0x0080)
77#define CR33 CTL_REG(0x0084)
78#define CR34 CTL_REG(0x0088)
79#define CR35 CTL_REG(0x008C)
80#define CR36 CTL_REG(0x0090)
81#define CR37 CTL_REG(0x0094)
82#define CR38 CTL_REG(0x0098)
83#define CR39 CTL_REG(0x009C)
84#define CR40 CTL_REG(0x00A0)
85#define CR41 CTL_REG(0x00A4)
86#define CR42 CTL_REG(0x00A8)
87#define CR43 CTL_REG(0x00AC)
88#define CR44 CTL_REG(0x00B0)
89#define CR45 CTL_REG(0x00B4)
90#define CR46 CTL_REG(0x00B8)
91#define CR47 CTL_REG(0x00BC) /* CCK baseband gain
92 * (patch value might be in EEPROM)
93 */
94#define CR48 CTL_REG(0x00C0)
95#define CR49 CTL_REG(0x00C4)
96#define CR50 CTL_REG(0x00C8)
97#define CR51 CTL_REG(0x00CC) /* TX power control for RF in 6-36M modes */
98#define CR52 CTL_REG(0x00D0) /* TX power control for RF in 48M mode */
99#define CR53 CTL_REG(0x00D4) /* TX power control for RF in 54M mode */
100#define CR54 CTL_REG(0x00D8)
101#define CR55 CTL_REG(0x00DC)
102#define CR56 CTL_REG(0x00E0)
103#define CR57 CTL_REG(0x00E4)
104#define CR58 CTL_REG(0x00E8)
105#define CR59 CTL_REG(0x00EC)
106#define CR60 CTL_REG(0x00F0)
107#define CR61 CTL_REG(0x00F4)
108#define CR62 CTL_REG(0x00F8)
109#define CR63 CTL_REG(0x00FC)
110#define CR64 CTL_REG(0x0100)
111#define CR65 CTL_REG(0x0104) /* OFDM 54M calibration */
112#define CR66 CTL_REG(0x0108) /* OFDM 48M calibration */
113#define CR67 CTL_REG(0x010C) /* OFDM 36M calibration */
114#define CR68 CTL_REG(0x0110) /* CCK calibration */
115#define CR69 CTL_REG(0x0114)
116#define CR70 CTL_REG(0x0118)
117#define CR71 CTL_REG(0x011C)
118#define CR72 CTL_REG(0x0120)
119#define CR73 CTL_REG(0x0124)
120#define CR74 CTL_REG(0x0128)
121#define CR75 CTL_REG(0x012C)
122#define CR76 CTL_REG(0x0130)
123#define CR77 CTL_REG(0x0134)
124#define CR78 CTL_REG(0x0138)
125#define CR79 CTL_REG(0x013C)
126#define CR80 CTL_REG(0x0140)
127#define CR81 CTL_REG(0x0144)
128#define CR82 CTL_REG(0x0148)
129#define CR83 CTL_REG(0x014C)
130#define CR84 CTL_REG(0x0150)
131#define CR85 CTL_REG(0x0154)
132#define CR86 CTL_REG(0x0158)
133#define CR87 CTL_REG(0x015C)
134#define CR88 CTL_REG(0x0160)
135#define CR89 CTL_REG(0x0164)
136#define CR90 CTL_REG(0x0168)
137#define CR91 CTL_REG(0x016C)
138#define CR92 CTL_REG(0x0170)
139#define CR93 CTL_REG(0x0174)
140#define CR94 CTL_REG(0x0178)
141#define CR95 CTL_REG(0x017C)
142#define CR96 CTL_REG(0x0180)
143#define CR97 CTL_REG(0x0184)
144#define CR98 CTL_REG(0x0188)
145#define CR99 CTL_REG(0x018C)
146#define CR100 CTL_REG(0x0190)
147#define CR101 CTL_REG(0x0194)
148#define CR102 CTL_REG(0x0198)
149#define CR103 CTL_REG(0x019C)
150#define CR104 CTL_REG(0x01A0)
151#define CR105 CTL_REG(0x01A4)
152#define CR106 CTL_REG(0x01A8)
153#define CR107 CTL_REG(0x01AC)
154#define CR108 CTL_REG(0x01B0)
155#define CR109 CTL_REG(0x01B4)
156#define CR110 CTL_REG(0x01B8)
157#define CR111 CTL_REG(0x01BC)
158#define CR112 CTL_REG(0x01C0)
159#define CR113 CTL_REG(0x01C4)
160#define CR114 CTL_REG(0x01C8)
161#define CR115 CTL_REG(0x01CC)
162#define CR116 CTL_REG(0x01D0)
163#define CR117 CTL_REG(0x01D4)
164#define CR118 CTL_REG(0x01D8)
165#define CR119 CTL_REG(0x01DC)
166#define CR120 CTL_REG(0x01E0)
167#define CR121 CTL_REG(0x01E4)
168#define CR122 CTL_REG(0x01E8)
169#define CR123 CTL_REG(0x01EC)
170#define CR124 CTL_REG(0x01F0)
171#define CR125 CTL_REG(0x01F4)
172#define CR126 CTL_REG(0x01F8)
173#define CR127 CTL_REG(0x01FC)
174#define CR128 CTL_REG(0x0200)
175#define CR129 CTL_REG(0x0204)
176#define CR130 CTL_REG(0x0208)
177#define CR131 CTL_REG(0x020C)
178#define CR132 CTL_REG(0x0210)
179#define CR133 CTL_REG(0x0214)
180#define CR134 CTL_REG(0x0218)
181#define CR135 CTL_REG(0x021C)
182#define CR136 CTL_REG(0x0220)
183#define CR137 CTL_REG(0x0224)
184#define CR138 CTL_REG(0x0228)
185#define CR139 CTL_REG(0x022C)
186#define CR140 CTL_REG(0x0230)
187#define CR141 CTL_REG(0x0234)
188#define CR142 CTL_REG(0x0238)
189#define CR143 CTL_REG(0x023C)
190#define CR144 CTL_REG(0x0240)
191#define CR145 CTL_REG(0x0244)
192#define CR146 CTL_REG(0x0248)
193#define CR147 CTL_REG(0x024C)
194#define CR148 CTL_REG(0x0250)
195#define CR149 CTL_REG(0x0254)
196#define CR150 CTL_REG(0x0258)
197#define CR151 CTL_REG(0x025C)
198#define CR152 CTL_REG(0x0260)
199#define CR153 CTL_REG(0x0264)
200#define CR154 CTL_REG(0x0268)
201#define CR155 CTL_REG(0x026C)
202#define CR156 CTL_REG(0x0270)
203#define CR157 CTL_REG(0x0274)
204#define CR158 CTL_REG(0x0278)
205#define CR159 CTL_REG(0x027C)
206#define CR160 CTL_REG(0x0280)
207#define CR161 CTL_REG(0x0284)
208#define CR162 CTL_REG(0x0288)
209#define CR163 CTL_REG(0x028C)
210#define CR164 CTL_REG(0x0290)
211#define CR165 CTL_REG(0x0294)
212#define CR166 CTL_REG(0x0298)
213#define CR167 CTL_REG(0x029C)
214#define CR168 CTL_REG(0x02A0)
215#define CR169 CTL_REG(0x02A4)
216#define CR170 CTL_REG(0x02A8)
217#define CR171 CTL_REG(0x02AC)
218#define CR172 CTL_REG(0x02B0)
219#define CR173 CTL_REG(0x02B4)
220#define CR174 CTL_REG(0x02B8)
221#define CR175 CTL_REG(0x02BC)
222#define CR176 CTL_REG(0x02C0)
223#define CR177 CTL_REG(0x02C4)
224#define CR178 CTL_REG(0x02C8)
225#define CR179 CTL_REG(0x02CC)
226#define CR180 CTL_REG(0x02D0)
227#define CR181 CTL_REG(0x02D4)
228#define CR182 CTL_REG(0x02D8)
229#define CR183 CTL_REG(0x02DC)
230#define CR184 CTL_REG(0x02E0)
231#define CR185 CTL_REG(0x02E4)
232#define CR186 CTL_REG(0x02E8)
233#define CR187 CTL_REG(0x02EC)
234#define CR188 CTL_REG(0x02F0)
235#define CR189 CTL_REG(0x02F4)
236#define CR190 CTL_REG(0x02F8)
237#define CR191 CTL_REG(0x02FC)
238#define CR192 CTL_REG(0x0300)
239#define CR193 CTL_REG(0x0304)
240#define CR194 CTL_REG(0x0308)
241#define CR195 CTL_REG(0x030C)
242#define CR196 CTL_REG(0x0310)
243#define CR197 CTL_REG(0x0314)
244#define CR198 CTL_REG(0x0318)
245#define CR199 CTL_REG(0x031C)
246#define CR200 CTL_REG(0x0320)
247#define CR201 CTL_REG(0x0324)
248#define CR202 CTL_REG(0x0328)
249#define CR203 CTL_REG(0x032C) /* I2C bus template value & flash control */
250#define CR204 CTL_REG(0x0330)
251#define CR205 CTL_REG(0x0334)
252#define CR206 CTL_REG(0x0338)
253#define CR207 CTL_REG(0x033C)
254#define CR208 CTL_REG(0x0340)
255#define CR209 CTL_REG(0x0344)
256#define CR210 CTL_REG(0x0348)
257#define CR211 CTL_REG(0x034C)
258#define CR212 CTL_REG(0x0350)
259#define CR213 CTL_REG(0x0354)
260#define CR214 CTL_REG(0x0358)
261#define CR215 CTL_REG(0x035C)
262#define CR216 CTL_REG(0x0360)
263#define CR217 CTL_REG(0x0364)
264#define CR218 CTL_REG(0x0368)
265#define CR219 CTL_REG(0x036C)
266#define CR220 CTL_REG(0x0370)
267#define CR221 CTL_REG(0x0374)
268#define CR222 CTL_REG(0x0378)
269#define CR223 CTL_REG(0x037C)
270#define CR224 CTL_REG(0x0380)
271#define CR225 CTL_REG(0x0384)
272#define CR226 CTL_REG(0x0388)
273#define CR227 CTL_REG(0x038C)
274#define CR228 CTL_REG(0x0390)
275#define CR229 CTL_REG(0x0394)
276#define CR230 CTL_REG(0x0398)
277#define CR231 CTL_REG(0x039C)
278#define CR232 CTL_REG(0x03A0)
279#define CR233 CTL_REG(0x03A4)
280#define CR234 CTL_REG(0x03A8)
281#define CR235 CTL_REG(0x03AC)
282#define CR236 CTL_REG(0x03B0)
283
284#define CR240 CTL_REG(0x03C0)
285/* bit 7: host-controlled RF register writes
286 * CR241-CR245: for hardware controlled writing of RF bits, not needed for
287 * USB
288 */
289#define CR241 CTL_REG(0x03C4)
290#define CR242 CTL_REG(0x03C8)
291#define CR243 CTL_REG(0x03CC)
292#define CR244 CTL_REG(0x03D0)
293#define CR245 CTL_REG(0x03D4)
294
295#define CR251 CTL_REG(0x03EC) /* only used for activation and deactivation of
296 * Airoha RFs AL2230 and AL7230B
297 */
298#define CR252 CTL_REG(0x03F0)
299#define CR253 CTL_REG(0x03F4)
300#define CR254 CTL_REG(0x03F8)
301#define CR255 CTL_REG(0x03FC)
302
303#define CR_MAX_PHY_REG 255
304
305/* Taken from the ZYDAS driver, not all of them are relevant for the ZSD1211
306 * driver.
307 */
308
309#define CR_RF_IF_CLK CTL_REG(0x0400)
310#define CR_RF_IF_DATA CTL_REG(0x0404)
311#define CR_PE1_PE2 CTL_REG(0x0408)
312#define CR_PE2_DLY CTL_REG(0x040C)
313#define CR_LE1 CTL_REG(0x0410)
314#define CR_LE2 CTL_REG(0x0414)
315/* Seems to enable/disable GPI (General Purpose IO?) */
316#define CR_GPI_EN CTL_REG(0x0418)
317#define CR_RADIO_PD CTL_REG(0x042C)
318#define CR_RF2948_PD CTL_REG(0x042C)
319#define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C)
320#define CR_CONFIG_PHILIPS CTL_REG(0x0440)
321#define CR_SA2400_SER_AP CTL_REG(0x0444)
322#define CR_I2C_WRITE CTL_REG(0x0444)
323#define CR_SA2400_SER_RP CTL_REG(0x0448)
324#define CR_RADIO_PE CTL_REG(0x0458)
325#define CR_RST_BUS_MASTER CTL_REG(0x045C)
326#define CR_RFCFG CTL_REG(0x0464)
327#define CR_HSTSCHG CTL_REG(0x046C)
328#define CR_PHY_ON CTL_REG(0x0474)
329#define CR_RX_DELAY CTL_REG(0x0478)
330#define CR_RX_PE_DELAY CTL_REG(0x047C)
331#define CR_GPIO_1 CTL_REG(0x0490)
332#define CR_GPIO_2 CTL_REG(0x0494)
333#define CR_EncryBufMux CTL_REG(0x04A8)
334#define CR_PS_CTRL CTL_REG(0x0500)
335#define CR_ADDA_PWR_DWN CTL_REG(0x0504)
336#define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508)
337#define CR_MAC_PS_STATE CTL_REG(0x050C)
338
339#define CR_INTERRUPT CTL_REG(0x0510)
340#define INT_TX_COMPLETE 0x00000001
341#define INT_RX_COMPLETE 0x00000002
342#define INT_RETRY_FAIL 0x00000004
343#define INT_WAKEUP 0x00000008
344#define INT_DTIM_NOTIFY 0x00000020
345#define INT_CFG_NEXT_BCN 0x00000040
346#define INT_BUS_ABORT 0x00000080
347#define INT_TX_FIFO_READY 0x00000100
348#define INT_UART 0x00000200
349#define INT_TX_COMPLETE_EN 0x00010000
350#define INT_RX_COMPLETE_EN 0x00020000
351#define INT_RETRY_FAIL_EN 0x00040000
352#define INT_WAKEUP_EN 0x00080000
353#define INT_DTIM_NOTIFY_EN 0x00200000
354#define INT_CFG_NEXT_BCN_EN 0x00400000
355#define INT_BUS_ABORT_EN 0x00800000
356#define INT_TX_FIFO_READY_EN 0x01000000
357#define INT_UART_EN 0x02000000
358
359#define CR_TSF_LOW_PART CTL_REG(0x0514)
360#define CR_TSF_HIGH_PART CTL_REG(0x0518)
361
362/* Following three values are in time units (1024us)
363 * Following condition must be met:
364 * atim < tbtt < bcn
365 */
366#define CR_ATIM_WND_PERIOD CTL_REG(0x051C)
367#define CR_BCN_INTERVAL CTL_REG(0x0520)
368#define CR_PRE_TBTT CTL_REG(0x0524)
369/* in units of TU(1024us) */
370
371/* for UART support */
372#define CR_UART_RBR_THR_DLL CTL_REG(0x0540)
373#define CR_UART_DLM_IER CTL_REG(0x0544)
374#define CR_UART_IIR_FCR CTL_REG(0x0548)
375#define CR_UART_LCR CTL_REG(0x054c)
376#define CR_UART_MCR CTL_REG(0x0550)
377#define CR_UART_LSR CTL_REG(0x0554)
378#define CR_UART_MSR CTL_REG(0x0558)
379#define CR_UART_ECR CTL_REG(0x055c)
380#define CR_UART_STATUS CTL_REG(0x0560)
381
382#define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600)
383#define CR_PCI_TX_AddR_P2 CTL_REG(0x0604)
384#define CR_PCI_RX_AddR_P1 CTL_REG(0x0608)
385#define CR_PCI_RX_AddR_P2 CTL_REG(0x060C)
386
387/* must be overwritten if custom MAC address will be used */
388#define CR_MAC_ADDR_P1 CTL_REG(0x0610)
389#define CR_MAC_ADDR_P2 CTL_REG(0x0614)
390#define CR_BSSID_P1 CTL_REG(0x0618)
391#define CR_BSSID_P2 CTL_REG(0x061C)
392#define CR_BCN_PLCP_CFG CTL_REG(0x0620)
393#define CR_GROUP_HASH_P1 CTL_REG(0x0624)
394#define CR_GROUP_HASH_P2 CTL_REG(0x0628)
395#define CR_RX_TIMEOUT CTL_REG(0x062C)
396
397/* Basic rates supported by the BSS. When producing ACK or CTS messages, the
398 * device will use a rate in this table that is less than or equal to the rate
399 * of the incoming frame which prompted the response */
400#define CR_BASIC_RATE_TBL CTL_REG(0x0630)
401#define CR_RATE_1M 0x0001 /* 802.11b */
402#define CR_RATE_2M 0x0002 /* 802.11b */
403#define CR_RATE_5_5M 0x0004 /* 802.11b */
404#define CR_RATE_11M 0x0008 /* 802.11b */
405#define CR_RATE_6M 0x0100 /* 802.11g */
406#define CR_RATE_9M 0x0200 /* 802.11g */
407#define CR_RATE_12M 0x0400 /* 802.11g */
408#define CR_RATE_18M 0x0800 /* 802.11g */
409#define CR_RATE_24M 0x1000 /* 802.11g */
410#define CR_RATE_36M 0x2000 /* 802.11g */
411#define CR_RATE_48M 0x4000 /* 802.11g */
412#define CR_RATE_54M 0x8000 /* 802.11g */
413#define CR_RATES_80211G 0xff00
414#define CR_RATES_80211B 0x000f
415
416/* Mandatory rates required in the BSS. When producing ACK or CTS messages, if
417 * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will
418 * look for a rate in this table that is less than or equal to the rate of
419 * the incoming frame. */
420#define CR_MANDATORY_RATE_TBL CTL_REG(0x0634)
421#define CR_RTS_CTS_RATE CTL_REG(0x0638)
422
423#define CR_WEP_PROTECT CTL_REG(0x063C)
424#define CR_RX_THRESHOLD CTL_REG(0x0640)
425
426/* register for controlling the LEDS */
427#define CR_LED CTL_REG(0x0644)
428/* masks for controlling LEDs */
429#define LED1 0x0100
430#define LED2 0x0200
431
432/* Seems to indicate that the configuration is over.
433 */
434#define CR_AFTER_PNP CTL_REG(0x0648)
435#define CR_ACK_TIME_80211 CTL_REG(0x0658)
436
437#define CR_RX_OFFSET CTL_REG(0x065c)
438
439#define CR_PHY_DELAY CTL_REG(0x066C)
440#define CR_BCN_FIFO CTL_REG(0x0670)
441#define CR_SNIFFER_ON CTL_REG(0x0674)
442
443#define CR_ENCRYPTION_TYPE CTL_REG(0x0678)
444#define NO_WEP 0
445#define WEP64 1
446#define WEP128 5
447#define WEP256 6
448#define ENC_SNIFFER 8
449
450#define CR_ZD1211_RETRY_MAX CTL_REG(0x067C)
451
452#define CR_REG1 CTL_REG(0x0680)
453/* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical
454 * registers, so one could argue it is a LOCK bit. But calling it
455 * LOCK_PHY_REGS makes it confusing.
456 */
457#define UNLOCK_PHY_REGS 0x0080
458
459#define CR_DEVICE_STATE CTL_REG(0x0684)
460#define CR_UNDERRUN_CNT CTL_REG(0x0688)
461
462#define CR_RX_FILTER CTL_REG(0x068c)
463#define RX_FILTER_ASSOC_RESPONSE 0x0002
464#define RX_FILTER_REASSOC_RESPONSE 0x0008
465#define RX_FILTER_PROBE_RESPONSE 0x0020
466#define RX_FILTER_BEACON 0x0100
467#define RX_FILTER_DISASSOC 0x0400
468#define RX_FILTER_AUTH 0x0800
469#define AP_RX_FILTER 0x0400feff
470#define STA_RX_FILTER 0x0000ffff
471
472/* Monitor mode sets filter to 0xfffff */
473
474#define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690)
475#define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694)
476#define CR_IFS_VALUE CTL_REG(0x0698)
477#define CR_RX_TIME_OUT CTL_REG(0x069C)
478#define CR_TOTAL_RX_FRM CTL_REG(0x06A0)
479#define CR_CRC32_CNT CTL_REG(0x06A4)
480#define CR_CRC16_CNT CTL_REG(0x06A8)
481#define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC)
482#define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0)
483
484#define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC)
485
486#define CR_NAV_CNT CTL_REG(0x06C4)
487#define CR_NAV_CCA CTL_REG(0x06C8)
488#define CR_RETRY_CNT CTL_REG(0x06CC)
489
490#define CR_READ_TCB_ADDR CTL_REG(0x06E8)
491#define CR_READ_RFD_ADDR CTL_REG(0x06EC)
492#define CR_CWMIN_CWMAX CTL_REG(0x06F0)
493#define CR_TOTAL_TX_FRM CTL_REG(0x06F4)
494
495/* CAM: Continuous Access Mode (power management) */
496#define CR_CAM_MODE CTL_REG(0x0700)
497#define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704)
498#define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708)
499#define CR_CAM_ADDRESS CTL_REG(0x070C)
500#define CR_CAM_DATA CTL_REG(0x0710)
501
502#define CR_ROMDIR CTL_REG(0x0714)
503
504#define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714)
505#define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718)
506
507#define CR_WEPKEY0 CTL_REG(0x0720)
508#define CR_WEPKEY1 CTL_REG(0x0724)
509#define CR_WEPKEY2 CTL_REG(0x0728)
510#define CR_WEPKEY3 CTL_REG(0x072C)
511#define CR_WEPKEY4 CTL_REG(0x0730)
512#define CR_WEPKEY5 CTL_REG(0x0734)
513#define CR_WEPKEY6 CTL_REG(0x0738)
514#define CR_WEPKEY7 CTL_REG(0x073C)
515#define CR_WEPKEY8 CTL_REG(0x0740)
516#define CR_WEPKEY9 CTL_REG(0x0744)
517#define CR_WEPKEY10 CTL_REG(0x0748)
518#define CR_WEPKEY11 CTL_REG(0x074C)
519#define CR_WEPKEY12 CTL_REG(0x0750)
520#define CR_WEPKEY13 CTL_REG(0x0754)
521#define CR_WEPKEY14 CTL_REG(0x0758)
522#define CR_WEPKEY15 CTL_REG(0x075c)
523#define CR_TKIP_MODE CTL_REG(0x0760)
524
525#define CR_EEPROM_PROTECT0 CTL_REG(0x0758)
526#define CR_EEPROM_PROTECT1 CTL_REG(0x075C)
527
528#define CR_DBG_FIFO_RD CTL_REG(0x0800)
529#define CR_DBG_SELECT CTL_REG(0x0804)
530#define CR_FIFO_Length CTL_REG(0x0808)
531
532
533#define CR_RSSI_MGC CTL_REG(0x0810)
534
535#define CR_PON CTL_REG(0x0818)
536#define CR_RX_ON CTL_REG(0x081C)
537#define CR_TX_ON CTL_REG(0x0820)
538#define CR_CHIP_EN CTL_REG(0x0824)
539#define CR_LO_SW CTL_REG(0x0828)
540#define CR_TXRX_SW CTL_REG(0x082C)
541#define CR_S_MD CTL_REG(0x0830)
542
543#define CR_USB_DEBUG_PORT CTL_REG(0x0888)
544
545#define CR_ZD1211B_TX_PWR_CTL1 CTL_REG(0x0b00)
546#define CR_ZD1211B_TX_PWR_CTL2 CTL_REG(0x0b04)
547#define CR_ZD1211B_TX_PWR_CTL3 CTL_REG(0x0b08)
548#define CR_ZD1211B_TX_PWR_CTL4 CTL_REG(0x0b0c)
549#define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10)
550#define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14)
551#define CR_ZD1211B_TXOP CTL_REG(0x0b20)
552#define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28)
553
554#define CWIN_SIZE 0x007f043f
555
556
557#define HWINT_ENABLED 0x004f0000
558#define HWINT_DISABLED 0
559
560#define E2P_PWR_INT_GUARD 8
561#define E2P_CHANNEL_COUNT 14
562
563/* If you compare this addresses with the ZYDAS orignal driver, please notify
564 * that we use word mapping for the EEPROM.
565 */
566
567/*
568 * Upper 16 bit contains the regulatory domain.
569 */
570#define E2P_SUBID E2P_REG(0x00)
571#define E2P_POD E2P_REG(0x02)
572#define E2P_MAC_ADDR_P1 E2P_REG(0x04)
573#define E2P_MAC_ADDR_P2 E2P_REG(0x06)
574#define E2P_PWR_CAL_VALUE1 E2P_REG(0x08)
575#define E2P_PWR_CAL_VALUE2 E2P_REG(0x0a)
576#define E2P_PWR_CAL_VALUE3 E2P_REG(0x0c)
577#define E2P_PWR_CAL_VALUE4 E2P_REG(0x0e)
578#define E2P_PWR_INT_VALUE1 E2P_REG(0x10)
579#define E2P_PWR_INT_VALUE2 E2P_REG(0x12)
580#define E2P_PWR_INT_VALUE3 E2P_REG(0x14)
581#define E2P_PWR_INT_VALUE4 E2P_REG(0x16)
582
583/* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30)
584 * also only 11 channels. */
585#define E2P_ALLOWED_CHANNEL E2P_REG(0x18)
586
587#define E2P_PHY_REG E2P_REG(0x1a)
588#define E2P_DEVICE_VER E2P_REG(0x20)
589#define E2P_36M_CAL_VALUE1 E2P_REG(0x28)
590#define E2P_36M_CAL_VALUE2 E2P_REG(0x2a)
591#define E2P_36M_CAL_VALUE3 E2P_REG(0x2c)
592#define E2P_36M_CAL_VALUE4 E2P_REG(0x2e)
593#define E2P_11A_INT_VALUE1 E2P_REG(0x30)
594#define E2P_11A_INT_VALUE2 E2P_REG(0x32)
595#define E2P_11A_INT_VALUE3 E2P_REG(0x34)
596#define E2P_11A_INT_VALUE4 E2P_REG(0x36)
597#define E2P_48M_CAL_VALUE1 E2P_REG(0x38)
598#define E2P_48M_CAL_VALUE2 E2P_REG(0x3a)
599#define E2P_48M_CAL_VALUE3 E2P_REG(0x3c)
600#define E2P_48M_CAL_VALUE4 E2P_REG(0x3e)
601#define E2P_48M_INT_VALUE1 E2P_REG(0x40)
602#define E2P_48M_INT_VALUE2 E2P_REG(0x42)
603#define E2P_48M_INT_VALUE3 E2P_REG(0x44)
604#define E2P_48M_INT_VALUE4 E2P_REG(0x46)
605#define E2P_54M_CAL_VALUE1 E2P_REG(0x48) /* ??? */
606#define E2P_54M_CAL_VALUE2 E2P_REG(0x4a)
607#define E2P_54M_CAL_VALUE3 E2P_REG(0x4c)
608#define E2P_54M_CAL_VALUE4 E2P_REG(0x4e)
609#define E2P_54M_INT_VALUE1 E2P_REG(0x50)
610#define E2P_54M_INT_VALUE2 E2P_REG(0x52)
611#define E2P_54M_INT_VALUE3 E2P_REG(0x54)
612#define E2P_54M_INT_VALUE4 E2P_REG(0x56)
613
614/* All 16 bit values */
615#define FW_FIRMWARE_VER FW_REG(0)
616/* non-zero if USB high speed connection */
617#define FW_USB_SPEED FW_REG(1)
618#define FW_FIX_TX_RATE FW_REG(2)
619/* Seems to be able to control LEDs over the firmware */
620#define FW_LINK_STATUS FW_REG(3)
621#define FW_SOFT_RESET FW_REG(4)
622#define FW_FLASH_CHK FW_REG(5)
623
624enum {
625 CR_BASE_OFFSET = 0x9000,
626 FW_START_OFFSET = 0xee00,
627 FW_BASE_ADDR_OFFSET = FW_START_OFFSET + 0x1d,
628 EEPROM_START_OFFSET = 0xf800,
629 EEPROM_SIZE = 0x800, /* words */
630 LOAD_CODE_SIZE = 0xe, /* words */
631 LOAD_VECT_SIZE = 0x10000 - 0xfff7, /* words */
632 EEPROM_REGS_OFFSET = LOAD_CODE_SIZE + LOAD_VECT_SIZE,
633 E2P_BASE_OFFSET = EEPROM_START_OFFSET +
634 EEPROM_REGS_OFFSET,
635};
636
637#define FW_REG_TABLE_ADDR USB_ADDR(FW_START_OFFSET + 0x1d)
638
639enum {
640 /* indices for ofdm_cal_values */
641 OFDM_36M_INDEX = 0,
642 OFDM_48M_INDEX = 1,
643 OFDM_54M_INDEX = 2,
644};
645
646struct zd_chip {
647 struct zd_usb usb;
648 struct zd_rf rf;
649 struct mutex mutex;
650 u8 e2p_mac[ETH_ALEN];
651 /* EepSetPoint in the vendor driver */
652 u8 pwr_cal_values[E2P_CHANNEL_COUNT];
653 /* integration values in the vendor driver */
654 u8 pwr_int_values[E2P_CHANNEL_COUNT];
655 /* SetPointOFDM in the vendor driver */
656 u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT];
657 u8 pa_type:4, patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1,
658 is_zd1211b:1;
659};
660
661static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb)
662{
663 return container_of(usb, struct zd_chip, usb);
664}
665
666static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf)
667{
668 return container_of(rf, struct zd_chip, rf);
669}
670
671#define zd_chip_dev(chip) (&(chip)->usb.intf->dev)
672
673void zd_chip_init(struct zd_chip *chip,
674 struct net_device *netdev,
675 struct usb_interface *intf);
676void zd_chip_clear(struct zd_chip *chip);
677int zd_chip_init_hw(struct zd_chip *chip, u8 device_type);
678int zd_chip_reset(struct zd_chip *chip);
679
680static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values,
681 const zd_addr_t *addresses,
682 unsigned int count)
683{
684 ZD_ASSERT(mutex_is_locked(&chip->mutex));
685 return zd_usb_ioread16v(&chip->usb, values, addresses, count);
686}
687
688static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value,
689 const zd_addr_t addr)
690{
691 ZD_ASSERT(mutex_is_locked(&chip->mutex));
692 return zd_usb_ioread16(&chip->usb, value, addr);
693}
694
695int zd_ioread32v_locked(struct zd_chip *chip, u32 *values,
696 const zd_addr_t *addresses, unsigned int count);
697
698static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value,
699 const zd_addr_t addr)
700{
701 return zd_ioread32v_locked(chip, value, (const zd_addr_t *)&addr, 1);
702}
703
704static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value,
705 zd_addr_t addr)
706{
707 struct zd_ioreq16 ioreq;
708
709 ZD_ASSERT(mutex_is_locked(&chip->mutex));
710 ioreq.addr = addr;
711 ioreq.value = value;
712
713 return zd_usb_iowrite16v(&chip->usb, &ioreq, 1);
714}
715
716int zd_iowrite16a_locked(struct zd_chip *chip,
717 const struct zd_ioreq16 *ioreqs, unsigned int count);
718
719int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
720 unsigned int count);
721
722static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value,
723 zd_addr_t addr)
724{
725 struct zd_ioreq32 ioreq;
726
727 ioreq.addr = addr;
728 ioreq.value = value;
729
730 return _zd_iowrite32v_locked(chip, &ioreq, 1);
731}
732
733int zd_iowrite32a_locked(struct zd_chip *chip,
734 const struct zd_ioreq32 *ioreqs, unsigned int count);
735
736static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits)
737{
738 ZD_ASSERT(mutex_is_locked(&chip->mutex));
739 return zd_usb_rfwrite(&chip->usb, value, bits);
740}
741
742int zd_rfwritev_locked(struct zd_chip *chip,
743 const u32* values, unsigned int count, u8 bits);
744
745/* Locking functions for reading and writing registers.
746 * The different parameters are intentional.
747 */
748int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value);
749int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value);
750int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value);
751int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value);
752int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
753 u32 *values, unsigned int count);
754int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
755 unsigned int count);
756
757int zd_chip_set_channel(struct zd_chip *chip, u8 channel);
758static inline u8 _zd_chip_get_channel(struct zd_chip *chip)
759{
760 return chip->rf.channel;
761}
762u8 zd_chip_get_channel(struct zd_chip *chip);
763int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain);
764void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr);
765int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr);
766int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr);
767int zd_chip_switch_radio_on(struct zd_chip *chip);
768int zd_chip_switch_radio_off(struct zd_chip *chip);
769int zd_chip_enable_int(struct zd_chip *chip);
770void zd_chip_disable_int(struct zd_chip *chip);
771int zd_chip_enable_rx(struct zd_chip *chip);
772void zd_chip_disable_rx(struct zd_chip *chip);
773int zd_chip_enable_hwint(struct zd_chip *chip);
774int zd_chip_disable_hwint(struct zd_chip *chip);
775
776static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type)
777{
778 return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type);
779}
780
781static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type)
782{
783 return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type);
784}
785
786static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates)
787{
788 return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates);
789}
790
791int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates);
792
793static inline int zd_chip_set_rx_filter(struct zd_chip *chip, u32 filter)
794{
795 return zd_iowrite32(chip, CR_RX_FILTER, filter);
796}
797
798int zd_chip_lock_phy_regs(struct zd_chip *chip);
799int zd_chip_unlock_phy_regs(struct zd_chip *chip);
800
801enum led_status {
802 LED_OFF = 0,
803 LED_ON = 1,
804 LED_FLIP = 2,
805 LED_STATUS = 3,
806};
807
808int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status);
809int zd_chip_led_flip(struct zd_chip *chip, int led,
810 const unsigned int *phases_msecs, unsigned int count);
811
812int zd_set_beacon_interval(struct zd_chip *chip, u32 interval);
813
814static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval)
815{
816 return zd_ioread32(chip, CR_BCN_INTERVAL, interval);
817}
818
819struct rx_status;
820
821u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
822 const struct rx_status *status);
823u8 zd_rx_strength_percent(u8 rssi);
824
825u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status);
826
827#endif /* _ZD_CHIP_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_def.h b/drivers/net/wireless/zd1211rw/zd_def.h
new file mode 100644
index 000000000000..465906812fc4
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_def.h
@@ -0,0 +1,48 @@
1/* zd_def.h
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_DEF_H
19#define _ZD_DEF_H
20
21#include <linux/kernel.h>
22#include <linux/stringify.h>
23#include <linux/device.h>
24#include <linux/kernel.h>
25
26#define dev_printk_f(level, dev, fmt, args...) \
27 dev_printk(level, dev, "%s() " fmt, __func__, ##args)
28
29#ifdef DEBUG
30# define dev_dbg_f(dev, fmt, args...) \
31 dev_printk_f(KERN_DEBUG, dev, fmt, ## args)
32#else
33# define dev_dbg_f(dev, fmt, args...) do { (void)(dev); } while (0)
34#endif /* DEBUG */
35
36#ifdef DEBUG
37# define ZD_ASSERT(x) \
38do { \
39 if (!(x)) { \
40 pr_debug("%s:%d ASSERT %s VIOLATED!\n", \
41 __FILE__, __LINE__, __stringify(x)); \
42 } \
43} while (0)
44#else
45# define ZD_ASSERT(x) do { } while (0)
46#endif
47
48#endif /* _ZD_DEF_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_ieee80211.c b/drivers/net/wireless/zd1211rw/zd_ieee80211.c
new file mode 100644
index 000000000000..66905f7b61ff
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_ieee80211.c
@@ -0,0 +1,191 @@
1/* zd_ieee80211.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18/*
19 * A lot of this code is generic and should be moved into the upper layers
20 * at some point.
21 */
22
23#include <linux/errno.h>
24#include <linux/wireless.h>
25#include <linux/kernel.h>
26#include <net/ieee80211.h>
27
28#include "zd_def.h"
29#include "zd_ieee80211.h"
30#include "zd_mac.h"
31
32static const struct channel_range channel_ranges[] = {
33 [0] = { 0, 0},
34 [ZD_REGDOMAIN_FCC] = { 1, 12},
35 [ZD_REGDOMAIN_IC] = { 1, 12},
36 [ZD_REGDOMAIN_ETSI] = { 1, 14},
37 [ZD_REGDOMAIN_JAPAN] = { 1, 14},
38 [ZD_REGDOMAIN_SPAIN] = { 1, 14},
39 [ZD_REGDOMAIN_FRANCE] = { 1, 14},
40 [ZD_REGDOMAIN_JAPAN_ADD] = {14, 15},
41};
42
43const struct channel_range *zd_channel_range(u8 regdomain)
44{
45 if (regdomain >= ARRAY_SIZE(channel_ranges))
46 regdomain = 0;
47 return &channel_ranges[regdomain];
48}
49
50int zd_regdomain_supports_channel(u8 regdomain, u8 channel)
51{
52 const struct channel_range *range = zd_channel_range(regdomain);
53 return range->start <= channel && channel < range->end;
54}
55
56int zd_regdomain_supported(u8 regdomain)
57{
58 const struct channel_range *range = zd_channel_range(regdomain);
59 return range->start != 0;
60}
61
62/* Stores channel frequencies in MHz. */
63static const u16 channel_frequencies[] = {
64 2412, 2417, 2422, 2427, 2432, 2437, 2442, 2447,
65 2452, 2457, 2462, 2467, 2472, 2484,
66};
67
68#define NUM_CHANNELS ARRAY_SIZE(channel_frequencies)
69
70static int compute_freq(struct iw_freq *freq, u32 mhz, u32 hz)
71{
72 u32 factor;
73
74 freq->e = 0;
75 if (mhz >= 1000000000U) {
76 pr_debug("zd1211 mhz %u to large\n", mhz);
77 freq->m = 0;
78 return -EINVAL;
79 }
80
81 factor = 1000;
82 while (mhz >= factor) {
83
84 freq->e += 1;
85 factor *= 10;
86 }
87
88 factor /= 1000U;
89 freq->m = mhz * (1000000U/factor) + hz/factor;
90
91 return 0;
92}
93
94int zd_channel_to_freq(struct iw_freq *freq, u8 channel)
95{
96 if (channel > NUM_CHANNELS) {
97 freq->m = 0;
98 freq->e = 0;
99 return -EINVAL;
100 }
101 if (!channel) {
102 freq->m = 0;
103 freq->e = 0;
104 return -EINVAL;
105 }
106 return compute_freq(freq, channel_frequencies[channel-1], 0);
107}
108
109static int freq_to_mhz(const struct iw_freq *freq)
110{
111 u32 factor;
112 int e;
113
114 /* Such high frequencies are not supported. */
115 if (freq->e > 6)
116 return -EINVAL;
117
118 factor = 1;
119 for (e = freq->e; e > 0; --e) {
120 factor *= 10;
121 }
122 factor = 1000000U / factor;
123
124 if (freq->m % factor) {
125 return -EINVAL;
126 }
127
128 return freq->m / factor;
129}
130
131int zd_find_channel(u8 *channel, const struct iw_freq *freq)
132{
133 int i, r;
134 u32 mhz;
135
136 if (!(freq->flags & IW_FREQ_FIXED))
137 return 0;
138
139 if (freq->m < 1000) {
140 if (freq->m > NUM_CHANNELS || freq->m == 0)
141 return -EINVAL;
142 *channel = freq->m;
143 return 1;
144 }
145
146 r = freq_to_mhz(freq);
147 if (r < 0)
148 return r;
149 mhz = r;
150
151 for (i = 0; i < NUM_CHANNELS; i++) {
152 if (mhz == channel_frequencies[i]) {
153 *channel = i+1;
154 return 1;
155 }
156 }
157
158 return -EINVAL;
159}
160
161int zd_geo_init(struct ieee80211_device *ieee, u8 regdomain)
162{
163 struct ieee80211_geo geo;
164 const struct channel_range *range;
165 int i;
166 u8 channel;
167
168 dev_dbg(zd_mac_dev(zd_netdev_mac(ieee->dev)),
169 "regdomain %#04x\n", regdomain);
170
171 range = zd_channel_range(regdomain);
172 if (range->start == 0) {
173 dev_err(zd_mac_dev(zd_netdev_mac(ieee->dev)),
174 "zd1211 regdomain %#04x not supported\n",
175 regdomain);
176 return -EINVAL;
177 }
178
179 memset(&geo, 0, sizeof(geo));
180
181 for (i = 0, channel = range->start; channel < range->end; channel++) {
182 struct ieee80211_channel *chan = &geo.bg[i++];
183 chan->freq = channel_frequencies[channel - 1];
184 chan->channel = channel;
185 }
186
187 geo.bg_channels = i;
188 memcpy(geo.name, "XX ", 4);
189 ieee80211_set_geo(ieee, &geo);
190 return 0;
191}
diff --git a/drivers/net/wireless/zd1211rw/zd_ieee80211.h b/drivers/net/wireless/zd1211rw/zd_ieee80211.h
new file mode 100644
index 000000000000..36329890dfec
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_ieee80211.h
@@ -0,0 +1,85 @@
1#ifndef _ZD_IEEE80211_H
2#define _ZD_IEEE80211_H
3
4#include <net/ieee80211.h>
5#include "zd_types.h"
6
7/* Additional definitions from the standards.
8 */
9
10#define ZD_REGDOMAIN_FCC 0x10
11#define ZD_REGDOMAIN_IC 0x20
12#define ZD_REGDOMAIN_ETSI 0x30
13#define ZD_REGDOMAIN_SPAIN 0x31
14#define ZD_REGDOMAIN_FRANCE 0x32
15#define ZD_REGDOMAIN_JAPAN_ADD 0x40
16#define ZD_REGDOMAIN_JAPAN 0x41
17
18enum {
19 MIN_CHANNEL24 = 1,
20 MAX_CHANNEL24 = 14,
21};
22
23struct channel_range {
24 u8 start;
25 u8 end; /* exclusive (channel must be less than end) */
26};
27
28struct iw_freq;
29
30int zd_geo_init(struct ieee80211_device *ieee, u8 regdomain);
31
32const struct channel_range *zd_channel_range(u8 regdomain);
33int zd_regdomain_supports_channel(u8 regdomain, u8 channel);
34int zd_regdomain_supported(u8 regdomain);
35
36/* for 2.4 GHz band */
37int zd_channel_to_freq(struct iw_freq *freq, u8 channel);
38int zd_find_channel(u8 *channel, const struct iw_freq *freq);
39
40#define ZD_PLCP_SERVICE_LENGTH_EXTENSION 0x80
41
42struct ofdm_plcp_header {
43 u8 prefix[3];
44 __le16 service;
45} __attribute__((packed));
46
47static inline u8 zd_ofdm_plcp_header_rate(
48 const struct ofdm_plcp_header *header)
49{
50 return header->prefix[0] & 0xf;
51}
52
53#define ZD_OFDM_RATE_6M 0xb
54#define ZD_OFDM_RATE_9M 0xf
55#define ZD_OFDM_RATE_12M 0xa
56#define ZD_OFDM_RATE_18M 0xe
57#define ZD_OFDM_RATE_24M 0x9
58#define ZD_OFDM_RATE_36M 0xd
59#define ZD_OFDM_RATE_48M 0x8
60#define ZD_OFDM_RATE_54M 0xc
61
62struct cck_plcp_header {
63 u8 signal;
64 u8 service;
65 __le16 length;
66 __le16 crc16;
67} __attribute__((packed));
68
69static inline u8 zd_cck_plcp_header_rate(const struct cck_plcp_header *header)
70{
71 return header->signal;
72}
73
74#define ZD_CCK_SIGNAL_1M 0x0a
75#define ZD_CCK_SIGNAL_2M 0x14
76#define ZD_CCK_SIGNAL_5M5 0x37
77#define ZD_CCK_SIGNAL_11M 0x6e
78
79enum ieee80211_std {
80 IEEE80211B = 0x01,
81 IEEE80211A = 0x02,
82 IEEE80211G = 0x04,
83};
84
85#endif /* _ZD_IEEE80211_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c
new file mode 100644
index 000000000000..d6f3e02a0b54
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_mac.c
@@ -0,0 +1,1057 @@
1/* zd_mac.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/wireless.h>
21#include <linux/usb.h>
22#include <linux/jiffies.h>
23#include <net/ieee80211_radiotap.h>
24
25#include "zd_def.h"
26#include "zd_chip.h"
27#include "zd_mac.h"
28#include "zd_ieee80211.h"
29#include "zd_netdev.h"
30#include "zd_rf.h"
31#include "zd_util.h"
32
33static void ieee_init(struct ieee80211_device *ieee);
34static void softmac_init(struct ieee80211softmac_device *sm);
35
36int zd_mac_init(struct zd_mac *mac,
37 struct net_device *netdev,
38 struct usb_interface *intf)
39{
40 struct ieee80211_device *ieee = zd_netdev_ieee80211(netdev);
41
42 memset(mac, 0, sizeof(*mac));
43 spin_lock_init(&mac->lock);
44 mac->netdev = netdev;
45
46 ieee_init(ieee);
47 softmac_init(ieee80211_priv(netdev));
48 zd_chip_init(&mac->chip, netdev, intf);
49 return 0;
50}
51
52static int reset_channel(struct zd_mac *mac)
53{
54 int r;
55 unsigned long flags;
56 const struct channel_range *range;
57
58 spin_lock_irqsave(&mac->lock, flags);
59 range = zd_channel_range(mac->regdomain);
60 if (!range->start) {
61 r = -EINVAL;
62 goto out;
63 }
64 mac->requested_channel = range->start;
65 r = 0;
66out:
67 spin_unlock_irqrestore(&mac->lock, flags);
68 return r;
69}
70
71int zd_mac_init_hw(struct zd_mac *mac, u8 device_type)
72{
73 int r;
74 struct zd_chip *chip = &mac->chip;
75 u8 addr[ETH_ALEN];
76 u8 default_regdomain;
77
78 r = zd_chip_enable_int(chip);
79 if (r)
80 goto out;
81 r = zd_chip_init_hw(chip, device_type);
82 if (r)
83 goto disable_int;
84
85 zd_get_e2p_mac_addr(chip, addr);
86 r = zd_write_mac_addr(chip, addr);
87 if (r)
88 goto disable_int;
89 ZD_ASSERT(!irqs_disabled());
90 spin_lock_irq(&mac->lock);
91 memcpy(mac->netdev->dev_addr, addr, ETH_ALEN);
92 spin_unlock_irq(&mac->lock);
93
94 r = zd_read_regdomain(chip, &default_regdomain);
95 if (r)
96 goto disable_int;
97 if (!zd_regdomain_supported(default_regdomain)) {
98 dev_dbg_f(zd_mac_dev(mac),
99 "Regulatory Domain %#04x is not supported.\n",
100 default_regdomain);
101 r = -EINVAL;
102 goto disable_int;
103 }
104 spin_lock_irq(&mac->lock);
105 mac->regdomain = mac->default_regdomain = default_regdomain;
106 spin_unlock_irq(&mac->lock);
107 r = reset_channel(mac);
108 if (r)
109 goto disable_int;
110
111 /* We must inform the device that we are doing encryption/decryption in
112 * software at the moment. */
113 r = zd_set_encryption_type(chip, ENC_SNIFFER);
114 if (r)
115 goto disable_int;
116
117 r = zd_geo_init(zd_mac_to_ieee80211(mac), mac->regdomain);
118 if (r)
119 goto disable_int;
120
121 r = 0;
122disable_int:
123 zd_chip_disable_int(chip);
124out:
125 return r;
126}
127
128void zd_mac_clear(struct zd_mac *mac)
129{
130 /* Aquire the lock. */
131 spin_lock(&mac->lock);
132 spin_unlock(&mac->lock);
133 zd_chip_clear(&mac->chip);
134 memset(mac, 0, sizeof(*mac));
135}
136
137static int reset_mode(struct zd_mac *mac)
138{
139 struct ieee80211_device *ieee = zd_mac_to_ieee80211(mac);
140 struct zd_ioreq32 ioreqs[3] = {
141 { CR_RX_FILTER, STA_RX_FILTER },
142 { CR_SNIFFER_ON, 0U },
143 };
144
145 if (ieee->iw_mode == IW_MODE_MONITOR) {
146 ioreqs[0].value = 0xffffffff;
147 ioreqs[1].value = 0x1;
148 ioreqs[2].value = ENC_SNIFFER;
149 }
150
151 return zd_iowrite32a(&mac->chip, ioreqs, 3);
152}
153
154int zd_mac_open(struct net_device *netdev)
155{
156 struct zd_mac *mac = zd_netdev_mac(netdev);
157 struct zd_chip *chip = &mac->chip;
158 int r;
159
160 r = zd_chip_enable_int(chip);
161 if (r < 0)
162 goto out;
163
164 r = zd_chip_set_basic_rates(chip, CR_RATES_80211B | CR_RATES_80211G);
165 if (r < 0)
166 goto disable_int;
167 r = reset_mode(mac);
168 if (r)
169 goto disable_int;
170 r = zd_chip_switch_radio_on(chip);
171 if (r < 0)
172 goto disable_int;
173 r = zd_chip_set_channel(chip, mac->requested_channel);
174 if (r < 0)
175 goto disable_radio;
176 r = zd_chip_enable_rx(chip);
177 if (r < 0)
178 goto disable_radio;
179 r = zd_chip_enable_hwint(chip);
180 if (r < 0)
181 goto disable_rx;
182
183 ieee80211softmac_start(netdev);
184 return 0;
185disable_rx:
186 zd_chip_disable_rx(chip);
187disable_radio:
188 zd_chip_switch_radio_off(chip);
189disable_int:
190 zd_chip_disable_int(chip);
191out:
192 return r;
193}
194
195int zd_mac_stop(struct net_device *netdev)
196{
197 struct zd_mac *mac = zd_netdev_mac(netdev);
198 struct zd_chip *chip = &mac->chip;
199
200 netif_stop_queue(netdev);
201
202 /*
203 * The order here deliberately is a little different from the open()
204 * method, since we need to make sure there is no opportunity for RX
205 * frames to be processed by softmac after we have stopped it.
206 */
207
208 zd_chip_disable_rx(chip);
209 ieee80211softmac_stop(netdev);
210
211 zd_chip_disable_hwint(chip);
212 zd_chip_switch_radio_off(chip);
213 zd_chip_disable_int(chip);
214
215 return 0;
216}
217
218int zd_mac_set_mac_address(struct net_device *netdev, void *p)
219{
220 int r;
221 unsigned long flags;
222 struct sockaddr *addr = p;
223 struct zd_mac *mac = zd_netdev_mac(netdev);
224 struct zd_chip *chip = &mac->chip;
225
226 if (!is_valid_ether_addr(addr->sa_data))
227 return -EADDRNOTAVAIL;
228
229 dev_dbg_f(zd_mac_dev(mac),
230 "Setting MAC to " MAC_FMT "\n", MAC_ARG(addr->sa_data));
231
232 r = zd_write_mac_addr(chip, addr->sa_data);
233 if (r)
234 return r;
235
236 spin_lock_irqsave(&mac->lock, flags);
237 memcpy(netdev->dev_addr, addr->sa_data, ETH_ALEN);
238 spin_unlock_irqrestore(&mac->lock, flags);
239
240 return 0;
241}
242
243int zd_mac_set_regdomain(struct zd_mac *mac, u8 regdomain)
244{
245 int r;
246 u8 channel;
247
248 ZD_ASSERT(!irqs_disabled());
249 spin_lock_irq(&mac->lock);
250 if (regdomain == 0) {
251 regdomain = mac->default_regdomain;
252 }
253 if (!zd_regdomain_supported(regdomain)) {
254 spin_unlock_irq(&mac->lock);
255 return -EINVAL;
256 }
257 mac->regdomain = regdomain;
258 channel = mac->requested_channel;
259 spin_unlock_irq(&mac->lock);
260
261 r = zd_geo_init(zd_mac_to_ieee80211(mac), regdomain);
262 if (r)
263 return r;
264 if (!zd_regdomain_supports_channel(regdomain, channel)) {
265 r = reset_channel(mac);
266 if (r)
267 return r;
268 }
269
270 return 0;
271}
272
273u8 zd_mac_get_regdomain(struct zd_mac *mac)
274{
275 unsigned long flags;
276 u8 regdomain;
277
278 spin_lock_irqsave(&mac->lock, flags);
279 regdomain = mac->regdomain;
280 spin_unlock_irqrestore(&mac->lock, flags);
281 return regdomain;
282}
283
284static void set_channel(struct net_device *netdev, u8 channel)
285{
286 struct zd_mac *mac = zd_netdev_mac(netdev);
287
288 dev_dbg_f(zd_mac_dev(mac), "channel %d\n", channel);
289
290 zd_chip_set_channel(&mac->chip, channel);
291}
292
293/* TODO: Should not work in Managed mode. */
294int zd_mac_request_channel(struct zd_mac *mac, u8 channel)
295{
296 unsigned long lock_flags;
297 struct ieee80211_device *ieee = zd_mac_to_ieee80211(mac);
298
299 if (ieee->iw_mode == IW_MODE_INFRA)
300 return -EPERM;
301
302 spin_lock_irqsave(&mac->lock, lock_flags);
303 if (!zd_regdomain_supports_channel(mac->regdomain, channel)) {
304 spin_unlock_irqrestore(&mac->lock, lock_flags);
305 return -EINVAL;
306 }
307 mac->requested_channel = channel;
308 spin_unlock_irqrestore(&mac->lock, lock_flags);
309 if (netif_running(mac->netdev))
310 return zd_chip_set_channel(&mac->chip, channel);
311 else
312 return 0;
313}
314
315int zd_mac_get_channel(struct zd_mac *mac, u8 *channel, u8 *flags)
316{
317 struct ieee80211_device *ieee = zd_mac_to_ieee80211(mac);
318
319 *channel = zd_chip_get_channel(&mac->chip);
320 if (ieee->iw_mode != IW_MODE_INFRA) {
321 spin_lock_irq(&mac->lock);
322 *flags = *channel == mac->requested_channel ?
323 MAC_FIXED_CHANNEL : 0;
324 spin_unlock(&mac->lock);
325 } else {
326 *flags = 0;
327 }
328 dev_dbg_f(zd_mac_dev(mac), "channel %u flags %u\n", *channel, *flags);
329 return 0;
330}
331
332/* If wrong rate is given, we are falling back to the slowest rate: 1MBit/s */
333static u8 cs_typed_rate(u8 cs_rate)
334{
335 static const u8 typed_rates[16] = {
336 [ZD_CS_CCK_RATE_1M] = ZD_CS_CCK|ZD_CS_CCK_RATE_1M,
337 [ZD_CS_CCK_RATE_2M] = ZD_CS_CCK|ZD_CS_CCK_RATE_2M,
338 [ZD_CS_CCK_RATE_5_5M] = ZD_CS_CCK|ZD_CS_CCK_RATE_5_5M,
339 [ZD_CS_CCK_RATE_11M] = ZD_CS_CCK|ZD_CS_CCK_RATE_11M,
340 [ZD_OFDM_RATE_6M] = ZD_CS_OFDM|ZD_OFDM_RATE_6M,
341 [ZD_OFDM_RATE_9M] = ZD_CS_OFDM|ZD_OFDM_RATE_9M,
342 [ZD_OFDM_RATE_12M] = ZD_CS_OFDM|ZD_OFDM_RATE_12M,
343 [ZD_OFDM_RATE_18M] = ZD_CS_OFDM|ZD_OFDM_RATE_18M,
344 [ZD_OFDM_RATE_24M] = ZD_CS_OFDM|ZD_OFDM_RATE_24M,
345 [ZD_OFDM_RATE_36M] = ZD_CS_OFDM|ZD_OFDM_RATE_36M,
346 [ZD_OFDM_RATE_48M] = ZD_CS_OFDM|ZD_OFDM_RATE_48M,
347 [ZD_OFDM_RATE_54M] = ZD_CS_OFDM|ZD_OFDM_RATE_54M,
348 };
349
350 ZD_ASSERT(ZD_CS_RATE_MASK == 0x0f);
351 return typed_rates[cs_rate & ZD_CS_RATE_MASK];
352}
353
354/* Fallback to lowest rate, if rate is unknown. */
355static u8 rate_to_cs_rate(u8 rate)
356{
357 switch (rate) {
358 case IEEE80211_CCK_RATE_2MB:
359 return ZD_CS_CCK_RATE_2M;
360 case IEEE80211_CCK_RATE_5MB:
361 return ZD_CS_CCK_RATE_5_5M;
362 case IEEE80211_CCK_RATE_11MB:
363 return ZD_CS_CCK_RATE_11M;
364 case IEEE80211_OFDM_RATE_6MB:
365 return ZD_OFDM_RATE_6M;
366 case IEEE80211_OFDM_RATE_9MB:
367 return ZD_OFDM_RATE_9M;
368 case IEEE80211_OFDM_RATE_12MB:
369 return ZD_OFDM_RATE_12M;
370 case IEEE80211_OFDM_RATE_18MB:
371 return ZD_OFDM_RATE_18M;
372 case IEEE80211_OFDM_RATE_24MB:
373 return ZD_OFDM_RATE_24M;
374 case IEEE80211_OFDM_RATE_36MB:
375 return ZD_OFDM_RATE_36M;
376 case IEEE80211_OFDM_RATE_48MB:
377 return ZD_OFDM_RATE_48M;
378 case IEEE80211_OFDM_RATE_54MB:
379 return ZD_OFDM_RATE_54M;
380 }
381 return ZD_CS_CCK_RATE_1M;
382}
383
384int zd_mac_set_mode(struct zd_mac *mac, u32 mode)
385{
386 struct ieee80211_device *ieee;
387
388 switch (mode) {
389 case IW_MODE_AUTO:
390 case IW_MODE_ADHOC:
391 case IW_MODE_INFRA:
392 mac->netdev->type = ARPHRD_ETHER;
393 break;
394 case IW_MODE_MONITOR:
395 mac->netdev->type = ARPHRD_IEEE80211_RADIOTAP;
396 break;
397 default:
398 dev_dbg_f(zd_mac_dev(mac), "wrong mode %u\n", mode);
399 return -EINVAL;
400 }
401
402 ieee = zd_mac_to_ieee80211(mac);
403 ZD_ASSERT(!irqs_disabled());
404 spin_lock_irq(&ieee->lock);
405 ieee->iw_mode = mode;
406 spin_unlock_irq(&ieee->lock);
407
408 if (netif_running(mac->netdev))
409 return reset_mode(mac);
410
411 return 0;
412}
413
414int zd_mac_get_mode(struct zd_mac *mac, u32 *mode)
415{
416 unsigned long flags;
417 struct ieee80211_device *ieee;
418
419 ieee = zd_mac_to_ieee80211(mac);
420 spin_lock_irqsave(&ieee->lock, flags);
421 *mode = ieee->iw_mode;
422 spin_unlock_irqrestore(&ieee->lock, flags);
423 return 0;
424}
425
426int zd_mac_get_range(struct zd_mac *mac, struct iw_range *range)
427{
428 int i;
429 const struct channel_range *channel_range;
430 u8 regdomain;
431
432 memset(range, 0, sizeof(*range));
433
434 /* FIXME: Not so important and depends on the mode. For 802.11g
435 * usually this value is used. It seems to be that Bit/s number is
436 * given here.
437 */
438 range->throughput = 27 * 1000 * 1000;
439
440 range->max_qual.qual = 100;
441 range->max_qual.level = 100;
442
443 /* FIXME: Needs still to be tuned. */
444 range->avg_qual.qual = 71;
445 range->avg_qual.level = 80;
446
447 /* FIXME: depends on standard? */
448 range->min_rts = 256;
449 range->max_rts = 2346;
450
451 range->min_frag = MIN_FRAG_THRESHOLD;
452 range->max_frag = MAX_FRAG_THRESHOLD;
453
454 range->max_encoding_tokens = WEP_KEYS;
455 range->num_encoding_sizes = 2;
456 range->encoding_size[0] = 5;
457 range->encoding_size[1] = WEP_KEY_LEN;
458
459 range->we_version_compiled = WIRELESS_EXT;
460 range->we_version_source = 20;
461
462 ZD_ASSERT(!irqs_disabled());
463 spin_lock_irq(&mac->lock);
464 regdomain = mac->regdomain;
465 spin_unlock_irq(&mac->lock);
466 channel_range = zd_channel_range(regdomain);
467
468 range->num_channels = channel_range->end - channel_range->start;
469 range->old_num_channels = range->num_channels;
470 range->num_frequency = range->num_channels;
471 range->old_num_frequency = range->num_frequency;
472
473 for (i = 0; i < range->num_frequency; i++) {
474 struct iw_freq *freq = &range->freq[i];
475 freq->i = channel_range->start + i;
476 zd_channel_to_freq(freq, freq->i);
477 }
478
479 return 0;
480}
481
482static int zd_calc_tx_length_us(u8 *service, u8 cs_rate, u16 tx_length)
483{
484 static const u8 rate_divisor[] = {
485 [ZD_CS_CCK_RATE_1M] = 1,
486 [ZD_CS_CCK_RATE_2M] = 2,
487 [ZD_CS_CCK_RATE_5_5M] = 11, /* bits must be doubled */
488 [ZD_CS_CCK_RATE_11M] = 11,
489 [ZD_OFDM_RATE_6M] = 6,
490 [ZD_OFDM_RATE_9M] = 9,
491 [ZD_OFDM_RATE_12M] = 12,
492 [ZD_OFDM_RATE_18M] = 18,
493 [ZD_OFDM_RATE_24M] = 24,
494 [ZD_OFDM_RATE_36M] = 36,
495 [ZD_OFDM_RATE_48M] = 48,
496 [ZD_OFDM_RATE_54M] = 54,
497 };
498
499 u32 bits = (u32)tx_length * 8;
500 u32 divisor;
501
502 divisor = rate_divisor[cs_rate];
503 if (divisor == 0)
504 return -EINVAL;
505
506 switch (cs_rate) {
507 case ZD_CS_CCK_RATE_5_5M:
508 bits = (2*bits) + 10; /* round up to the next integer */
509 break;
510 case ZD_CS_CCK_RATE_11M:
511 if (service) {
512 u32 t = bits % 11;
513 *service &= ~ZD_PLCP_SERVICE_LENGTH_EXTENSION;
514 if (0 < t && t <= 3) {
515 *service |= ZD_PLCP_SERVICE_LENGTH_EXTENSION;
516 }
517 }
518 bits += 10; /* round up to the next integer */
519 break;
520 }
521
522 return bits/divisor;
523}
524
525enum {
526 R2M_SHORT_PREAMBLE = 0x01,
527 R2M_11A = 0x02,
528};
529
530static u8 cs_rate_to_modulation(u8 cs_rate, int flags)
531{
532 u8 modulation;
533
534 modulation = cs_typed_rate(cs_rate);
535 if (flags & R2M_SHORT_PREAMBLE) {
536 switch (ZD_CS_RATE(modulation)) {
537 case ZD_CS_CCK_RATE_2M:
538 case ZD_CS_CCK_RATE_5_5M:
539 case ZD_CS_CCK_RATE_11M:
540 modulation |= ZD_CS_CCK_PREA_SHORT;
541 return modulation;
542 }
543 }
544 if (flags & R2M_11A) {
545 if (ZD_CS_TYPE(modulation) == ZD_CS_OFDM)
546 modulation |= ZD_CS_OFDM_MODE_11A;
547 }
548 return modulation;
549}
550
551static void cs_set_modulation(struct zd_mac *mac, struct zd_ctrlset *cs,
552 struct ieee80211_hdr_4addr *hdr)
553{
554 struct ieee80211softmac_device *softmac = ieee80211_priv(mac->netdev);
555 u16 ftype = WLAN_FC_GET_TYPE(le16_to_cpu(hdr->frame_ctl));
556 u8 rate, cs_rate;
557 int is_mgt = (ftype == IEEE80211_FTYPE_MGMT) != 0;
558
559 /* FIXME: 802.11a? short preamble? */
560 rate = ieee80211softmac_suggest_txrate(softmac,
561 is_multicast_ether_addr(hdr->addr1), is_mgt);
562
563 cs_rate = rate_to_cs_rate(rate);
564 cs->modulation = cs_rate_to_modulation(cs_rate, 0);
565}
566
567static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs,
568 struct ieee80211_hdr_4addr *header)
569{
570 unsigned int tx_length = le16_to_cpu(cs->tx_length);
571 u16 fctl = le16_to_cpu(header->frame_ctl);
572 u16 ftype = WLAN_FC_GET_TYPE(fctl);
573 u16 stype = WLAN_FC_GET_STYPE(fctl);
574
575 /*
576 * CONTROL:
577 * - start at 0x00
578 * - if fragment 0, enable bit 0
579 * - if backoff needed, enable bit 0
580 * - if burst (backoff not needed) disable bit 0
581 * - if multicast, enable bit 1
582 * - if PS-POLL frame, enable bit 2
583 * - if in INDEPENDENT_BSS mode and zd1205_DestPowerSave, then enable
584 * bit 4 (FIXME: wtf)
585 * - if frag_len > RTS threshold, set bit 5 as long if it isnt
586 * multicast or mgt
587 * - if bit 5 is set, and we are in OFDM mode, unset bit 5 and set bit
588 * 7
589 */
590
591 cs->control = 0;
592
593 /* First fragment */
594 if (WLAN_GET_SEQ_FRAG(le16_to_cpu(header->seq_ctl)) == 0)
595 cs->control |= ZD_CS_NEED_RANDOM_BACKOFF;
596
597 /* Multicast */
598 if (is_multicast_ether_addr(header->addr1))
599 cs->control |= ZD_CS_MULTICAST;
600
601 /* PS-POLL */
602 if (stype == IEEE80211_STYPE_PSPOLL)
603 cs->control |= ZD_CS_PS_POLL_FRAME;
604
605 if (!is_multicast_ether_addr(header->addr1) &&
606 ftype != IEEE80211_FTYPE_MGMT &&
607 tx_length > zd_netdev_ieee80211(mac->netdev)->rts)
608 {
609 /* FIXME: check the logic */
610 if (ZD_CS_TYPE(cs->modulation) == ZD_CS_OFDM) {
611 /* 802.11g */
612 cs->control |= ZD_CS_SELF_CTS;
613 } else { /* 802.11b */
614 cs->control |= ZD_CS_RTS;
615 }
616 }
617
618 /* FIXME: Management frame? */
619}
620
621static int fill_ctrlset(struct zd_mac *mac,
622 struct ieee80211_txb *txb,
623 int frag_num)
624{
625 int r;
626 struct sk_buff *skb = txb->fragments[frag_num];
627 struct ieee80211_hdr_4addr *hdr =
628 (struct ieee80211_hdr_4addr *) skb->data;
629 unsigned int frag_len = skb->len + IEEE80211_FCS_LEN;
630 unsigned int next_frag_len;
631 unsigned int packet_length;
632 struct zd_ctrlset *cs = (struct zd_ctrlset *)
633 skb_push(skb, sizeof(struct zd_ctrlset));
634
635 if (frag_num+1 < txb->nr_frags) {
636 next_frag_len = txb->fragments[frag_num+1]->len +
637 IEEE80211_FCS_LEN;
638 } else {
639 next_frag_len = 0;
640 }
641 ZD_ASSERT(frag_len <= 0xffff);
642 ZD_ASSERT(next_frag_len <= 0xffff);
643
644 cs_set_modulation(mac, cs, hdr);
645
646 cs->tx_length = cpu_to_le16(frag_len);
647
648 cs_set_control(mac, cs, hdr);
649
650 packet_length = frag_len + sizeof(struct zd_ctrlset) + 10;
651 ZD_ASSERT(packet_length <= 0xffff);
652 /* ZD1211B: Computing the length difference this way, gives us
653 * flexibility to compute the packet length.
654 */
655 cs->packet_length = cpu_to_le16(mac->chip.is_zd1211b ?
656 packet_length - frag_len : packet_length);
657
658 /*
659 * CURRENT LENGTH:
660 * - transmit frame length in microseconds
661 * - seems to be derived from frame length
662 * - see Cal_Us_Service() in zdinlinef.h
663 * - if macp->bTxBurstEnable is enabled, then multiply by 4
664 * - bTxBurstEnable is never set in the vendor driver
665 *
666 * SERVICE:
667 * - "for PLCP configuration"
668 * - always 0 except in some situations at 802.11b 11M
669 * - see line 53 of zdinlinef.h
670 */
671 cs->service = 0;
672 r = zd_calc_tx_length_us(&cs->service, ZD_CS_RATE(cs->modulation),
673 le16_to_cpu(cs->tx_length));
674 if (r < 0)
675 return r;
676 cs->current_length = cpu_to_le16(r);
677
678 if (next_frag_len == 0) {
679 cs->next_frame_length = 0;
680 } else {
681 r = zd_calc_tx_length_us(NULL, ZD_CS_RATE(cs->modulation),
682 next_frag_len);
683 if (r < 0)
684 return r;
685 cs->next_frame_length = cpu_to_le16(r);
686 }
687
688 return 0;
689}
690
691static int zd_mac_tx(struct zd_mac *mac, struct ieee80211_txb *txb, int pri)
692{
693 int i, r;
694
695 for (i = 0; i < txb->nr_frags; i++) {
696 struct sk_buff *skb = txb->fragments[i];
697
698 r = fill_ctrlset(mac, txb, i);
699 if (r)
700 return r;
701 r = zd_usb_tx(&mac->chip.usb, skb->data, skb->len);
702 if (r)
703 return r;
704 }
705
706 /* FIXME: shouldn't this be handled by the upper layers? */
707 mac->netdev->trans_start = jiffies;
708
709 ieee80211_txb_free(txb);
710 return 0;
711}
712
713struct zd_rt_hdr {
714 struct ieee80211_radiotap_header rt_hdr;
715 u8 rt_flags;
716 u8 rt_rate;
717 u16 rt_channel;
718 u16 rt_chbitmask;
719} __attribute__((packed));
720
721static void fill_rt_header(void *buffer, struct zd_mac *mac,
722 const struct ieee80211_rx_stats *stats,
723 const struct rx_status *status)
724{
725 struct zd_rt_hdr *hdr = buffer;
726
727 hdr->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
728 hdr->rt_hdr.it_pad = 0;
729 hdr->rt_hdr.it_len = cpu_to_le16(sizeof(struct zd_rt_hdr));
730 hdr->rt_hdr.it_present = cpu_to_le32((1 << IEEE80211_RADIOTAP_FLAGS) |
731 (1 << IEEE80211_RADIOTAP_CHANNEL) |
732 (1 << IEEE80211_RADIOTAP_RATE));
733
734 hdr->rt_flags = 0;
735 if (status->decryption_type & (ZD_RX_WEP64|ZD_RX_WEP128|ZD_RX_WEP256))
736 hdr->rt_flags |= IEEE80211_RADIOTAP_F_WEP;
737
738 hdr->rt_rate = stats->rate / 5;
739
740 /* FIXME: 802.11a */
741 hdr->rt_channel = cpu_to_le16(ieee80211chan2mhz(
742 _zd_chip_get_channel(&mac->chip)));
743 hdr->rt_chbitmask = cpu_to_le16(IEEE80211_CHAN_2GHZ |
744 ((status->frame_status & ZD_RX_FRAME_MODULATION_MASK) ==
745 ZD_RX_OFDM ? IEEE80211_CHAN_OFDM : IEEE80211_CHAN_CCK));
746}
747
748/* Returns 1 if the data packet is for us and 0 otherwise. */
749static int is_data_packet_for_us(struct ieee80211_device *ieee,
750 struct ieee80211_hdr_4addr *hdr)
751{
752 struct net_device *netdev = ieee->dev;
753 u16 fc = le16_to_cpu(hdr->frame_ctl);
754
755 ZD_ASSERT(WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA);
756
757 switch (ieee->iw_mode) {
758 case IW_MODE_ADHOC:
759 if ((fc & (IEEE80211_FCTL_TODS|IEEE80211_FCTL_FROMDS)) != 0 ||
760 memcmp(hdr->addr3, ieee->bssid, ETH_ALEN) != 0)
761 return 0;
762 break;
763 case IW_MODE_AUTO:
764 case IW_MODE_INFRA:
765 if ((fc & (IEEE80211_FCTL_TODS|IEEE80211_FCTL_FROMDS)) !=
766 IEEE80211_FCTL_FROMDS ||
767 memcmp(hdr->addr2, ieee->bssid, ETH_ALEN) != 0)
768 return 0;
769 break;
770 default:
771 ZD_ASSERT(ieee->iw_mode != IW_MODE_MONITOR);
772 return 0;
773 }
774
775 return memcmp(hdr->addr1, netdev->dev_addr, ETH_ALEN) == 0 ||
776 is_multicast_ether_addr(hdr->addr1) ||
777 (netdev->flags & IFF_PROMISC);
778}
779
780/* Filters receiving packets. If it returns 1 send it to ieee80211_rx, if 0
781 * return. If an error is detected -EINVAL is returned. ieee80211_rx_mgt() is
782 * called here.
783 *
784 * It has been based on ieee80211_rx_any.
785 */
786static int filter_rx(struct ieee80211_device *ieee,
787 const u8 *buffer, unsigned int length,
788 struct ieee80211_rx_stats *stats)
789{
790 struct ieee80211_hdr_4addr *hdr;
791 u16 fc;
792
793 if (ieee->iw_mode == IW_MODE_MONITOR)
794 return 1;
795
796 hdr = (struct ieee80211_hdr_4addr *)buffer;
797 fc = le16_to_cpu(hdr->frame_ctl);
798 if ((fc & IEEE80211_FCTL_VERS) != 0)
799 return -EINVAL;
800
801 switch (WLAN_FC_GET_TYPE(fc)) {
802 case IEEE80211_FTYPE_MGMT:
803 if (length < sizeof(struct ieee80211_hdr_3addr))
804 return -EINVAL;
805 ieee80211_rx_mgt(ieee, hdr, stats);
806 return 0;
807 case IEEE80211_FTYPE_CTL:
808 /* Ignore invalid short buffers */
809 return 0;
810 case IEEE80211_FTYPE_DATA:
811 if (length < sizeof(struct ieee80211_hdr_3addr))
812 return -EINVAL;
813 return is_data_packet_for_us(ieee, hdr);
814 }
815
816 return -EINVAL;
817}
818
819static void update_qual_rssi(struct zd_mac *mac, u8 qual_percent, u8 rssi)
820{
821 unsigned long flags;
822
823 spin_lock_irqsave(&mac->lock, flags);
824 mac->qual_average = (7 * mac->qual_average + qual_percent) / 8;
825 mac->rssi_average = (7 * mac->rssi_average + rssi) / 8;
826 spin_unlock_irqrestore(&mac->lock, flags);
827}
828
829static int fill_rx_stats(struct ieee80211_rx_stats *stats,
830 const struct rx_status **pstatus,
831 struct zd_mac *mac,
832 const u8 *buffer, unsigned int length)
833{
834 const struct rx_status *status;
835
836 *pstatus = status = zd_tail(buffer, length, sizeof(struct rx_status));
837 if (status->frame_status & ZD_RX_ERROR) {
838 /* FIXME: update? */
839 return -EINVAL;
840 }
841 memset(stats, 0, sizeof(struct ieee80211_rx_stats));
842 stats->len = length - (ZD_PLCP_HEADER_SIZE + IEEE80211_FCS_LEN +
843 + sizeof(struct rx_status));
844 /* FIXME: 802.11a */
845 stats->freq = IEEE80211_24GHZ_BAND;
846 stats->received_channel = _zd_chip_get_channel(&mac->chip);
847 stats->rssi = zd_rx_strength_percent(status->signal_strength);
848 stats->signal = zd_rx_qual_percent(buffer,
849 length - sizeof(struct rx_status),
850 status);
851 stats->mask = IEEE80211_STATMASK_RSSI | IEEE80211_STATMASK_SIGNAL;
852 stats->rate = zd_rx_rate(buffer, status);
853 if (stats->rate)
854 stats->mask |= IEEE80211_STATMASK_RATE;
855
856 update_qual_rssi(mac, stats->signal, stats->rssi);
857 return 0;
858}
859
860int zd_mac_rx(struct zd_mac *mac, const u8 *buffer, unsigned int length)
861{
862 int r;
863 struct ieee80211_device *ieee = zd_mac_to_ieee80211(mac);
864 struct ieee80211_rx_stats stats;
865 const struct rx_status *status;
866 struct sk_buff *skb;
867
868 if (length < ZD_PLCP_HEADER_SIZE + IEEE80211_1ADDR_LEN +
869 IEEE80211_FCS_LEN + sizeof(struct rx_status))
870 return -EINVAL;
871
872 r = fill_rx_stats(&stats, &status, mac, buffer, length);
873 if (r)
874 return r;
875
876 length -= ZD_PLCP_HEADER_SIZE+IEEE80211_FCS_LEN+
877 sizeof(struct rx_status);
878 buffer += ZD_PLCP_HEADER_SIZE;
879
880 r = filter_rx(ieee, buffer, length, &stats);
881 if (r <= 0)
882 return r;
883
884 skb = dev_alloc_skb(sizeof(struct zd_rt_hdr) + length);
885 if (!skb)
886 return -ENOMEM;
887 if (ieee->iw_mode == IW_MODE_MONITOR)
888 fill_rt_header(skb_put(skb, sizeof(struct zd_rt_hdr)), mac,
889 &stats, status);
890 memcpy(skb_put(skb, length), buffer, length);
891
892 r = ieee80211_rx(ieee, skb, &stats);
893 if (!r) {
894 ZD_ASSERT(in_irq());
895 dev_kfree_skb_irq(skb);
896 }
897 return 0;
898}
899
900static int netdev_tx(struct ieee80211_txb *txb, struct net_device *netdev,
901 int pri)
902{
903 return zd_mac_tx(zd_netdev_mac(netdev), txb, pri);
904}
905
906static void set_security(struct net_device *netdev,
907 struct ieee80211_security *sec)
908{
909 struct ieee80211_device *ieee = zd_netdev_ieee80211(netdev);
910 struct ieee80211_security *secinfo = &ieee->sec;
911 int keyidx;
912
913 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)), "\n");
914
915 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
916 if (sec->flags & (1<<keyidx)) {
917 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
918 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
919 memcpy(secinfo->keys[keyidx], sec->keys[keyidx],
920 SCM_KEY_LEN);
921 }
922
923 if (sec->flags & SEC_ACTIVE_KEY) {
924 secinfo->active_key = sec->active_key;
925 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)),
926 " .active_key = %d\n", sec->active_key);
927 }
928 if (sec->flags & SEC_UNICAST_GROUP) {
929 secinfo->unicast_uses_group = sec->unicast_uses_group;
930 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)),
931 " .unicast_uses_group = %d\n",
932 sec->unicast_uses_group);
933 }
934 if (sec->flags & SEC_LEVEL) {
935 secinfo->level = sec->level;
936 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)),
937 " .level = %d\n", sec->level);
938 }
939 if (sec->flags & SEC_ENABLED) {
940 secinfo->enabled = sec->enabled;
941 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)),
942 " .enabled = %d\n", sec->enabled);
943 }
944 if (sec->flags & SEC_ENCRYPT) {
945 secinfo->encrypt = sec->encrypt;
946 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)),
947 " .encrypt = %d\n", sec->encrypt);
948 }
949 if (sec->flags & SEC_AUTH_MODE) {
950 secinfo->auth_mode = sec->auth_mode;
951 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)),
952 " .auth_mode = %d\n", sec->auth_mode);
953 }
954}
955
956static void ieee_init(struct ieee80211_device *ieee)
957{
958 ieee->mode = IEEE_B | IEEE_G;
959 ieee->freq_band = IEEE80211_24GHZ_BAND;
960 ieee->modulation = IEEE80211_OFDM_MODULATION | IEEE80211_CCK_MODULATION;
961 ieee->tx_headroom = sizeof(struct zd_ctrlset);
962 ieee->set_security = set_security;
963 ieee->hard_start_xmit = netdev_tx;
964
965 /* Software encryption/decryption for now */
966 ieee->host_build_iv = 0;
967 ieee->host_encrypt = 1;
968 ieee->host_decrypt = 1;
969
970 /* FIXME: default to managed mode, until ieee80211 and zd1211rw can
971 * correctly support AUTO */
972 ieee->iw_mode = IW_MODE_INFRA;
973}
974
975static void softmac_init(struct ieee80211softmac_device *sm)
976{
977 sm->set_channel = set_channel;
978}
979
980struct iw_statistics *zd_mac_get_wireless_stats(struct net_device *ndev)
981{
982 struct zd_mac *mac = zd_netdev_mac(ndev);
983 struct iw_statistics *iw_stats = &mac->iw_stats;
984
985 memset(iw_stats, 0, sizeof(struct iw_statistics));
986 /* We are not setting the status, because ieee->state is not updated
987 * at all and this driver doesn't track authentication state.
988 */
989 spin_lock_irq(&mac->lock);
990 iw_stats->qual.qual = mac->qual_average;
991 iw_stats->qual.level = mac->rssi_average;
992 iw_stats->qual.updated = IW_QUAL_QUAL_UPDATED|IW_QUAL_LEVEL_UPDATED|
993 IW_QUAL_NOISE_INVALID;
994 spin_unlock_irq(&mac->lock);
995 /* TODO: update counter */
996 return iw_stats;
997}
998
999#ifdef DEBUG
1000static const char* decryption_types[] = {
1001 [ZD_RX_NO_WEP] = "none",
1002 [ZD_RX_WEP64] = "WEP64",
1003 [ZD_RX_TKIP] = "TKIP",
1004 [ZD_RX_AES] = "AES",
1005 [ZD_RX_WEP128] = "WEP128",
1006 [ZD_RX_WEP256] = "WEP256",
1007};
1008
1009static const char *decryption_type_string(u8 type)
1010{
1011 const char *s;
1012
1013 if (type < ARRAY_SIZE(decryption_types)) {
1014 s = decryption_types[type];
1015 } else {
1016 s = NULL;
1017 }
1018 return s ? s : "unknown";
1019}
1020
1021static int is_ofdm(u8 frame_status)
1022{
1023 return (frame_status & ZD_RX_OFDM);
1024}
1025
1026void zd_dump_rx_status(const struct rx_status *status)
1027{
1028 const char* modulation;
1029 u8 quality;
1030
1031 if (is_ofdm(status->frame_status)) {
1032 modulation = "ofdm";
1033 quality = status->signal_quality_ofdm;
1034 } else {
1035 modulation = "cck";
1036 quality = status->signal_quality_cck;
1037 }
1038 pr_debug("rx status %s strength %#04x qual %#04x decryption %s\n",
1039 modulation, status->signal_strength, quality,
1040 decryption_type_string(status->decryption_type));
1041 if (status->frame_status & ZD_RX_ERROR) {
1042 pr_debug("rx error %s%s%s%s%s%s\n",
1043 (status->frame_status & ZD_RX_TIMEOUT_ERROR) ?
1044 "timeout " : "",
1045 (status->frame_status & ZD_RX_FIFO_OVERRUN_ERROR) ?
1046 "fifo " : "",
1047 (status->frame_status & ZD_RX_DECRYPTION_ERROR) ?
1048 "decryption " : "",
1049 (status->frame_status & ZD_RX_CRC32_ERROR) ?
1050 "crc32 " : "",
1051 (status->frame_status & ZD_RX_NO_ADDR1_MATCH_ERROR) ?
1052 "addr1 " : "",
1053 (status->frame_status & ZD_RX_CRC16_ERROR) ?
1054 "crc16" : "");
1055 }
1056}
1057#endif /* DEBUG */
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.h b/drivers/net/wireless/zd1211rw/zd_mac.h
new file mode 100644
index 000000000000..71e382c589ee
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_mac.h
@@ -0,0 +1,190 @@
1/* zd_mac.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_MAC_H
19#define _ZD_MAC_H
20
21#include <linux/wireless.h>
22#include <linux/kernel.h>
23#include <net/ieee80211.h>
24#include <net/ieee80211softmac.h>
25
26#include "zd_chip.h"
27#include "zd_netdev.h"
28
29struct zd_ctrlset {
30 u8 modulation;
31 __le16 tx_length;
32 u8 control;
33 /* stores only the difference to tx_length on ZD1211B */
34 __le16 packet_length;
35 __le16 current_length;
36 u8 service;
37 __le16 next_frame_length;
38} __attribute__((packed));
39
40#define ZD_CS_RESERVED_SIZE 25
41
42/* zd_crtlset field modulation */
43#define ZD_CS_RATE_MASK 0x0f
44#define ZD_CS_TYPE_MASK 0x10
45#define ZD_CS_RATE(modulation) ((modulation) & ZD_CS_RATE_MASK)
46#define ZD_CS_TYPE(modulation) ((modulation) & ZD_CS_TYPE_MASK)
47
48#define ZD_CS_CCK 0x00
49#define ZD_CS_OFDM 0x10
50
51#define ZD_CS_CCK_RATE_1M 0x00
52#define ZD_CS_CCK_RATE_2M 0x01
53#define ZD_CS_CCK_RATE_5_5M 0x02
54#define ZD_CS_CCK_RATE_11M 0x03
55/* The rates for OFDM are encoded as in the PLCP header. Use ZD_OFDM_RATE_*.
56 */
57
58/* bit 5 is preamble (when in CCK mode), or a/g selection (when in OFDM mode) */
59#define ZD_CS_CCK_PREA_LONG 0x00
60#define ZD_CS_CCK_PREA_SHORT 0x20
61#define ZD_CS_OFDM_MODE_11G 0x00
62#define ZD_CS_OFDM_MODE_11A 0x20
63
64/* zd_ctrlset control field */
65#define ZD_CS_NEED_RANDOM_BACKOFF 0x01
66#define ZD_CS_MULTICAST 0x02
67
68#define ZD_CS_FRAME_TYPE_MASK 0x0c
69#define ZD_CS_DATA_FRAME 0x00
70#define ZD_CS_PS_POLL_FRAME 0x04
71#define ZD_CS_MANAGEMENT_FRAME 0x08
72#define ZD_CS_NO_SEQUENCE_CTL_FRAME 0x0c
73
74#define ZD_CS_WAKE_DESTINATION 0x10
75#define ZD_CS_RTS 0x20
76#define ZD_CS_ENCRYPT 0x40
77#define ZD_CS_SELF_CTS 0x80
78
79/* Incoming frames are prepended by a PLCP header */
80#define ZD_PLCP_HEADER_SIZE 5
81
82struct rx_length_info {
83 __le16 length[3];
84 __le16 tag;
85} __attribute__((packed));
86
87#define RX_LENGTH_INFO_TAG 0x697e
88
89struct rx_status {
90 /* rssi */
91 u8 signal_strength;
92 u8 signal_quality_cck;
93 u8 signal_quality_ofdm;
94 u8 decryption_type;
95 u8 frame_status;
96} __attribute__((packed));
97
98/* rx_status field decryption_type */
99#define ZD_RX_NO_WEP 0
100#define ZD_RX_WEP64 1
101#define ZD_RX_TKIP 2
102#define ZD_RX_AES 4
103#define ZD_RX_WEP128 5
104#define ZD_RX_WEP256 6
105
106/* rx_status field frame_status */
107#define ZD_RX_FRAME_MODULATION_MASK 0x01
108#define ZD_RX_CCK 0x00
109#define ZD_RX_OFDM 0x01
110
111#define ZD_RX_TIMEOUT_ERROR 0x02
112#define ZD_RX_FIFO_OVERRUN_ERROR 0x04
113#define ZD_RX_DECRYPTION_ERROR 0x08
114#define ZD_RX_CRC32_ERROR 0x10
115#define ZD_RX_NO_ADDR1_MATCH_ERROR 0x20
116#define ZD_RX_CRC16_ERROR 0x40
117#define ZD_RX_ERROR 0x80
118
119enum mac_flags {
120 MAC_FIXED_CHANNEL = 0x01,
121};
122
123struct zd_mac {
124 struct net_device *netdev;
125 struct zd_chip chip;
126 spinlock_t lock;
127 /* Unlocked reading possible */
128 struct iw_statistics iw_stats;
129 u8 qual_average;
130 u8 rssi_average;
131 u8 regdomain;
132 u8 default_regdomain;
133 u8 requested_channel;
134};
135
136static inline struct ieee80211_device *zd_mac_to_ieee80211(struct zd_mac *mac)
137{
138 return zd_netdev_ieee80211(mac->netdev);
139}
140
141static inline struct zd_mac *zd_netdev_mac(struct net_device *netdev)
142{
143 return ieee80211softmac_priv(netdev);
144}
145
146static inline struct zd_mac *zd_chip_to_mac(struct zd_chip *chip)
147{
148 return container_of(chip, struct zd_mac, chip);
149}
150
151static inline struct zd_mac *zd_usb_to_mac(struct zd_usb *usb)
152{
153 return zd_chip_to_mac(zd_usb_to_chip(usb));
154}
155
156#define zd_mac_dev(mac) (zd_chip_dev(&(mac)->chip))
157
158int zd_mac_init(struct zd_mac *mac,
159 struct net_device *netdev,
160 struct usb_interface *intf);
161void zd_mac_clear(struct zd_mac *mac);
162
163int zd_mac_init_hw(struct zd_mac *mac, u8 device_type);
164
165int zd_mac_open(struct net_device *netdev);
166int zd_mac_stop(struct net_device *netdev);
167int zd_mac_set_mac_address(struct net_device *dev, void *p);
168
169int zd_mac_rx(struct zd_mac *mac, const u8 *buffer, unsigned int length);
170
171int zd_mac_set_regdomain(struct zd_mac *zd_mac, u8 regdomain);
172u8 zd_mac_get_regdomain(struct zd_mac *zd_mac);
173
174int zd_mac_request_channel(struct zd_mac *mac, u8 channel);
175int zd_mac_get_channel(struct zd_mac *mac, u8 *channel, u8 *flags);
176
177int zd_mac_set_mode(struct zd_mac *mac, u32 mode);
178int zd_mac_get_mode(struct zd_mac *mac, u32 *mode);
179
180int zd_mac_get_range(struct zd_mac *mac, struct iw_range *range);
181
182struct iw_statistics *zd_mac_get_wireless_stats(struct net_device *ndev);
183
184#ifdef DEBUG
185void zd_dump_rx_status(const struct rx_status *status);
186#else
187#define zd_dump_rx_status(status)
188#endif /* DEBUG */
189
190#endif /* _ZD_MAC_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_netdev.c b/drivers/net/wireless/zd1211rw/zd_netdev.c
new file mode 100644
index 000000000000..9df232c2c863
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_netdev.c
@@ -0,0 +1,267 @@
1/* zd_netdev.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/skbuff.h>
21#include <net/ieee80211.h>
22#include <net/ieee80211softmac.h>
23#include <net/ieee80211softmac_wx.h>
24#include <net/iw_handler.h>
25
26#include "zd_def.h"
27#include "zd_netdev.h"
28#include "zd_mac.h"
29#include "zd_ieee80211.h"
30
31/* Region 0 means reset regdomain to default. */
32static int zd_set_regdomain(struct net_device *netdev,
33 struct iw_request_info *info,
34 union iwreq_data *req, char *extra)
35{
36 const u8 *regdomain = (u8 *)req;
37 return zd_mac_set_regdomain(zd_netdev_mac(netdev), *regdomain);
38}
39
40static int zd_get_regdomain(struct net_device *netdev,
41 struct iw_request_info *info,
42 union iwreq_data *req, char *extra)
43{
44 u8 *regdomain = (u8 *)req;
45 if (!regdomain)
46 return -EINVAL;
47 *regdomain = zd_mac_get_regdomain(zd_netdev_mac(netdev));
48 return 0;
49}
50
51static const struct iw_priv_args zd_priv_args[] = {
52 {
53 .cmd = ZD_PRIV_SET_REGDOMAIN,
54 .set_args = IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1,
55 .name = "set_regdomain",
56 },
57 {
58 .cmd = ZD_PRIV_GET_REGDOMAIN,
59 .get_args = IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1,
60 .name = "get_regdomain",
61 },
62};
63
64#define PRIV_OFFSET(x) [(x)-SIOCIWFIRSTPRIV]
65
66static const iw_handler zd_priv_handler[] = {
67 PRIV_OFFSET(ZD_PRIV_SET_REGDOMAIN) = zd_set_regdomain,
68 PRIV_OFFSET(ZD_PRIV_GET_REGDOMAIN) = zd_get_regdomain,
69};
70
71static int iw_get_name(struct net_device *netdev,
72 struct iw_request_info *info,
73 union iwreq_data *req, char *extra)
74{
75 /* FIXME: check whether 802.11a will also supported, add also
76 * zd1211B, if we support it.
77 */
78 strlcpy(req->name, "802.11g zd1211", IFNAMSIZ);
79 return 0;
80}
81
82static int iw_set_freq(struct net_device *netdev,
83 struct iw_request_info *info,
84 union iwreq_data *req, char *extra)
85{
86 int r;
87 struct zd_mac *mac = zd_netdev_mac(netdev);
88 struct iw_freq *freq = &req->freq;
89 u8 channel;
90
91 r = zd_find_channel(&channel, freq);
92 if (r < 0)
93 return r;
94 r = zd_mac_request_channel(mac, channel);
95 return r;
96}
97
98static int iw_get_freq(struct net_device *netdev,
99 struct iw_request_info *info,
100 union iwreq_data *req, char *extra)
101{
102 int r;
103 struct zd_mac *mac = zd_netdev_mac(netdev);
104 struct iw_freq *freq = &req->freq;
105 u8 channel;
106 u8 flags;
107
108 r = zd_mac_get_channel(mac, &channel, &flags);
109 if (r)
110 return r;
111
112 freq->flags = (flags & MAC_FIXED_CHANNEL) ?
113 IW_FREQ_FIXED : IW_FREQ_AUTO;
114 dev_dbg_f(zd_mac_dev(mac), "channel %s\n",
115 (flags & MAC_FIXED_CHANNEL) ? "fixed" : "auto");
116 return zd_channel_to_freq(freq, channel);
117}
118
119static int iw_set_mode(struct net_device *netdev,
120 struct iw_request_info *info,
121 union iwreq_data *req, char *extra)
122{
123 return zd_mac_set_mode(zd_netdev_mac(netdev), req->mode);
124}
125
126static int iw_get_mode(struct net_device *netdev,
127 struct iw_request_info *info,
128 union iwreq_data *req, char *extra)
129{
130 return zd_mac_get_mode(zd_netdev_mac(netdev), &req->mode);
131}
132
133static int iw_get_range(struct net_device *netdev,
134 struct iw_request_info *info,
135 union iwreq_data *req, char *extra)
136{
137 struct iw_range *range = (struct iw_range *)extra;
138
139 dev_dbg_f(zd_mac_dev(zd_netdev_mac(netdev)), "\n");
140 req->data.length = sizeof(*range);
141 return zd_mac_get_range(zd_netdev_mac(netdev), range);
142}
143
144static int iw_set_encode(struct net_device *netdev,
145 struct iw_request_info *info,
146 union iwreq_data *data,
147 char *extra)
148{
149 return ieee80211_wx_set_encode(zd_netdev_ieee80211(netdev), info,
150 data, extra);
151}
152
153static int iw_get_encode(struct net_device *netdev,
154 struct iw_request_info *info,
155 union iwreq_data *data,
156 char *extra)
157{
158 return ieee80211_wx_get_encode(zd_netdev_ieee80211(netdev), info,
159 data, extra);
160}
161
162static int iw_set_encodeext(struct net_device *netdev,
163 struct iw_request_info *info,
164 union iwreq_data *data,
165 char *extra)
166{
167 return ieee80211_wx_set_encodeext(zd_netdev_ieee80211(netdev), info,
168 data, extra);
169}
170
171static int iw_get_encodeext(struct net_device *netdev,
172 struct iw_request_info *info,
173 union iwreq_data *data,
174 char *extra)
175{
176 return ieee80211_wx_get_encodeext(zd_netdev_ieee80211(netdev), info,
177 data, extra);
178}
179
180#define WX(x) [(x)-SIOCIWFIRST]
181
182static const iw_handler zd_standard_iw_handlers[] = {
183 WX(SIOCGIWNAME) = iw_get_name,
184 WX(SIOCSIWFREQ) = iw_set_freq,
185 WX(SIOCGIWFREQ) = iw_get_freq,
186 WX(SIOCSIWMODE) = iw_set_mode,
187 WX(SIOCGIWMODE) = iw_get_mode,
188 WX(SIOCGIWRANGE) = iw_get_range,
189 WX(SIOCSIWENCODE) = iw_set_encode,
190 WX(SIOCGIWENCODE) = iw_get_encode,
191 WX(SIOCSIWENCODEEXT) = iw_set_encodeext,
192 WX(SIOCGIWENCODEEXT) = iw_get_encodeext,
193 WX(SIOCSIWAUTH) = ieee80211_wx_set_auth,
194 WX(SIOCGIWAUTH) = ieee80211_wx_get_auth,
195 WX(SIOCSIWSCAN) = ieee80211softmac_wx_trigger_scan,
196 WX(SIOCGIWSCAN) = ieee80211softmac_wx_get_scan_results,
197 WX(SIOCSIWESSID) = ieee80211softmac_wx_set_essid,
198 WX(SIOCGIWESSID) = ieee80211softmac_wx_get_essid,
199 WX(SIOCSIWAP) = ieee80211softmac_wx_set_wap,
200 WX(SIOCGIWAP) = ieee80211softmac_wx_get_wap,
201 WX(SIOCSIWRATE) = ieee80211softmac_wx_set_rate,
202 WX(SIOCGIWRATE) = ieee80211softmac_wx_get_rate,
203 WX(SIOCSIWGENIE) = ieee80211softmac_wx_set_genie,
204 WX(SIOCGIWGENIE) = ieee80211softmac_wx_get_genie,
205 WX(SIOCSIWMLME) = ieee80211softmac_wx_set_mlme,
206};
207
208static const struct iw_handler_def iw_handler_def = {
209 .standard = zd_standard_iw_handlers,
210 .num_standard = ARRAY_SIZE(zd_standard_iw_handlers),
211 .private = zd_priv_handler,
212 .num_private = ARRAY_SIZE(zd_priv_handler),
213 .private_args = zd_priv_args,
214 .num_private_args = ARRAY_SIZE(zd_priv_args),
215 .get_wireless_stats = zd_mac_get_wireless_stats,
216};
217
218struct net_device *zd_netdev_alloc(struct usb_interface *intf)
219{
220 int r;
221 struct net_device *netdev;
222 struct zd_mac *mac;
223
224 netdev = alloc_ieee80211softmac(sizeof(struct zd_mac));
225 if (!netdev) {
226 dev_dbg_f(&intf->dev, "out of memory\n");
227 return NULL;
228 }
229
230 mac = zd_netdev_mac(netdev);
231 r = zd_mac_init(mac, netdev, intf);
232 if (r) {
233 usb_set_intfdata(intf, NULL);
234 free_ieee80211(netdev);
235 return NULL;
236 }
237
238 SET_MODULE_OWNER(netdev);
239 SET_NETDEV_DEV(netdev, &intf->dev);
240
241 dev_dbg_f(&intf->dev, "netdev->flags %#06hx\n", netdev->flags);
242 dev_dbg_f(&intf->dev, "netdev->features %#010lx\n", netdev->features);
243
244 netdev->open = zd_mac_open;
245 netdev->stop = zd_mac_stop;
246 /* netdev->get_stats = */
247 /* netdev->set_multicast_list = */
248 netdev->set_mac_address = zd_mac_set_mac_address;
249 netdev->wireless_handlers = &iw_handler_def;
250 /* netdev->ethtool_ops = */
251
252 return netdev;
253}
254
255void zd_netdev_free(struct net_device *netdev)
256{
257 if (!netdev)
258 return;
259
260 zd_mac_clear(zd_netdev_mac(netdev));
261 free_ieee80211(netdev);
262}
263
264void zd_netdev_disconnect(struct net_device *netdev)
265{
266 unregister_netdev(netdev);
267}
diff --git a/drivers/net/wireless/zd1211rw/zd_netdev.h b/drivers/net/wireless/zd1211rw/zd_netdev.h
new file mode 100644
index 000000000000..374a957073c1
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_netdev.h
@@ -0,0 +1,45 @@
1/* zd_netdev.h: Header for net device related functions.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_NETDEV_H
19#define _ZD_NETDEV_H
20
21#include <linux/usb.h>
22#include <linux/netdevice.h>
23#include <net/ieee80211.h>
24
25#define ZD_PRIV_SET_REGDOMAIN (SIOCIWFIRSTPRIV)
26#define ZD_PRIV_GET_REGDOMAIN (SIOCIWFIRSTPRIV+1)
27
28static inline struct ieee80211_device *zd_netdev_ieee80211(
29 struct net_device *ndev)
30{
31 return netdev_priv(ndev);
32}
33
34static inline struct net_device *zd_ieee80211_to_netdev(
35 struct ieee80211_device *ieee)
36{
37 return ieee->dev;
38}
39
40struct net_device *zd_netdev_alloc(struct usb_interface *intf);
41void zd_netdev_free(struct net_device *netdev);
42
43void zd_netdev_disconnect(struct net_device *netdev);
44
45#endif /* _ZD_NETDEV_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_rf.c b/drivers/net/wireless/zd1211rw/zd_rf.c
new file mode 100644
index 000000000000..d3770d2c61bc
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_rf.c
@@ -0,0 +1,151 @@
1/* zd_rf.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#include <linux/errno.h>
19#include <linux/string.h>
20
21#include "zd_def.h"
22#include "zd_rf.h"
23#include "zd_ieee80211.h"
24#include "zd_chip.h"
25
26static const char *rfs[] = {
27 [0] = "unknown RF0",
28 [1] = "unknown RF1",
29 [UW2451_RF] = "UW2451_RF",
30 [UCHIP_RF] = "UCHIP_RF",
31 [AL2230_RF] = "AL2230_RF",
32 [AL7230B_RF] = "AL7230B_RF",
33 [THETA_RF] = "THETA_RF",
34 [AL2210_RF] = "AL2210_RF",
35 [MAXIM_NEW_RF] = "MAXIM_NEW_RF",
36 [UW2453_RF] = "UW2453_RF",
37 [AL2230S_RF] = "AL2230S_RF",
38 [RALINK_RF] = "RALINK_RF",
39 [INTERSIL_RF] = "INTERSIL_RF",
40 [RF2959_RF] = "RF2959_RF",
41 [MAXIM_NEW2_RF] = "MAXIM_NEW2_RF",
42 [PHILIPS_RF] = "PHILIPS_RF",
43};
44
45const char *zd_rf_name(u8 type)
46{
47 if (type & 0xf0)
48 type = 0;
49 return rfs[type];
50}
51
52void zd_rf_init(struct zd_rf *rf)
53{
54 memset(rf, 0, sizeof(*rf));
55}
56
57void zd_rf_clear(struct zd_rf *rf)
58{
59 memset(rf, 0, sizeof(*rf));
60}
61
62int zd_rf_init_hw(struct zd_rf *rf, u8 type)
63{
64 int r, t;
65 struct zd_chip *chip = zd_rf_to_chip(rf);
66
67 ZD_ASSERT(mutex_is_locked(&chip->mutex));
68 switch (type) {
69 case RF2959_RF:
70 r = zd_rf_init_rf2959(rf);
71 if (r)
72 return r;
73 break;
74 case AL2230_RF:
75 r = zd_rf_init_al2230(rf);
76 if (r)
77 return r;
78 break;
79 default:
80 dev_err(zd_chip_dev(chip),
81 "RF %s %#x is not supported\n", zd_rf_name(type), type);
82 rf->type = 0;
83 return -ENODEV;
84 }
85
86 rf->type = type;
87
88 r = zd_chip_lock_phy_regs(chip);
89 if (r)
90 return r;
91 t = rf->init_hw(rf);
92 r = zd_chip_unlock_phy_regs(chip);
93 if (t)
94 r = t;
95 return r;
96}
97
98int zd_rf_scnprint_id(struct zd_rf *rf, char *buffer, size_t size)
99{
100 return scnprintf(buffer, size, "%s", zd_rf_name(rf->type));
101}
102
103int zd_rf_set_channel(struct zd_rf *rf, u8 channel)
104{
105 int r;
106
107 ZD_ASSERT(mutex_is_locked(&zd_rf_to_chip(rf)->mutex));
108 if (channel < MIN_CHANNEL24)
109 return -EINVAL;
110 if (channel > MAX_CHANNEL24)
111 return -EINVAL;
112 dev_dbg_f(zd_chip_dev(zd_rf_to_chip(rf)), "channel: %d\n", channel);
113
114 r = rf->set_channel(rf, channel);
115 if (r >= 0)
116 rf->channel = channel;
117 return r;
118}
119
120int zd_switch_radio_on(struct zd_rf *rf)
121{
122 int r, t;
123 struct zd_chip *chip = zd_rf_to_chip(rf);
124
125 ZD_ASSERT(mutex_is_locked(&chip->mutex));
126 r = zd_chip_lock_phy_regs(chip);
127 if (r)
128 return r;
129 t = rf->switch_radio_on(rf);
130 r = zd_chip_unlock_phy_regs(chip);
131 if (t)
132 r = t;
133 return r;
134}
135
136int zd_switch_radio_off(struct zd_rf *rf)
137{
138 int r, t;
139 struct zd_chip *chip = zd_rf_to_chip(rf);
140
141 /* TODO: move phy regs handling to zd_chip */
142 ZD_ASSERT(mutex_is_locked(&chip->mutex));
143 r = zd_chip_lock_phy_regs(chip);
144 if (r)
145 return r;
146 t = rf->switch_radio_off(rf);
147 r = zd_chip_unlock_phy_regs(chip);
148 if (t)
149 r = t;
150 return r;
151}
diff --git a/drivers/net/wireless/zd1211rw/zd_rf.h b/drivers/net/wireless/zd1211rw/zd_rf.h
new file mode 100644
index 000000000000..ea30f693fcc8
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_rf.h
@@ -0,0 +1,82 @@
1/* zd_rf.h
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_RF_H
19#define _ZD_RF_H
20
21#include "zd_types.h"
22
23#define UW2451_RF 0x2
24#define UCHIP_RF 0x3
25#define AL2230_RF 0x4
26#define AL7230B_RF 0x5 /* a,b,g */
27#define THETA_RF 0x6
28#define AL2210_RF 0x7
29#define MAXIM_NEW_RF 0x8
30#define UW2453_RF 0x9
31#define AL2230S_RF 0xa
32#define RALINK_RF 0xb
33#define INTERSIL_RF 0xc
34#define RF2959_RF 0xd
35#define MAXIM_NEW2_RF 0xe
36#define PHILIPS_RF 0xf
37
38#define RF_CHANNEL(ch) [(ch)-1]
39
40/* Provides functions of the RF transceiver. */
41
42enum {
43 RF_REG_BITS = 6,
44 RF_VALUE_BITS = 18,
45 RF_RV_BITS = RF_REG_BITS + RF_VALUE_BITS,
46};
47
48struct zd_rf {
49 u8 type;
50
51 u8 channel;
52 /*
53 * Whether this RF should patch the 6M band edge
54 * (assuming E2P_POD agrees)
55 */
56 u8 patch_6m_band_edge:1;
57
58 /* RF-specific functions */
59 int (*init_hw)(struct zd_rf *rf);
60 int (*set_channel)(struct zd_rf *rf, u8 channel);
61 int (*switch_radio_on)(struct zd_rf *rf);
62 int (*switch_radio_off)(struct zd_rf *rf);
63};
64
65const char *zd_rf_name(u8 type);
66void zd_rf_init(struct zd_rf *rf);
67void zd_rf_clear(struct zd_rf *rf);
68int zd_rf_init_hw(struct zd_rf *rf, u8 type);
69
70int zd_rf_scnprint_id(struct zd_rf *rf, char *buffer, size_t size);
71
72int zd_rf_set_channel(struct zd_rf *rf, u8 channel);
73
74int zd_switch_radio_on(struct zd_rf *rf);
75int zd_switch_radio_off(struct zd_rf *rf);
76
77/* Functions for individual RF chips */
78
79int zd_rf_init_rf2959(struct zd_rf *rf);
80int zd_rf_init_al2230(struct zd_rf *rf);
81
82#endif /* _ZD_RF_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_rf_al2230.c b/drivers/net/wireless/zd1211rw/zd_rf_al2230.c
new file mode 100644
index 000000000000..0948b25f660d
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_rf_al2230.c
@@ -0,0 +1,308 @@
1/* zd_rf_al2230.c: Functions for the AL2230 RF controller
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#include <linux/kernel.h>
19
20#include "zd_rf.h"
21#include "zd_usb.h"
22#include "zd_chip.h"
23
24static const u32 al2230_table[][3] = {
25 RF_CHANNEL( 1) = { 0x03f790, 0x033331, 0x00000d, },
26 RF_CHANNEL( 2) = { 0x03f790, 0x0b3331, 0x00000d, },
27 RF_CHANNEL( 3) = { 0x03e790, 0x033331, 0x00000d, },
28 RF_CHANNEL( 4) = { 0x03e790, 0x0b3331, 0x00000d, },
29 RF_CHANNEL( 5) = { 0x03f7a0, 0x033331, 0x00000d, },
30 RF_CHANNEL( 6) = { 0x03f7a0, 0x0b3331, 0x00000d, },
31 RF_CHANNEL( 7) = { 0x03e7a0, 0x033331, 0x00000d, },
32 RF_CHANNEL( 8) = { 0x03e7a0, 0x0b3331, 0x00000d, },
33 RF_CHANNEL( 9) = { 0x03f7b0, 0x033331, 0x00000d, },
34 RF_CHANNEL(10) = { 0x03f7b0, 0x0b3331, 0x00000d, },
35 RF_CHANNEL(11) = { 0x03e7b0, 0x033331, 0x00000d, },
36 RF_CHANNEL(12) = { 0x03e7b0, 0x0b3331, 0x00000d, },
37 RF_CHANNEL(13) = { 0x03f7c0, 0x033331, 0x00000d, },
38 RF_CHANNEL(14) = { 0x03e7c0, 0x066661, 0x00000d, },
39};
40
41static int zd1211_al2230_init_hw(struct zd_rf *rf)
42{
43 int r;
44 struct zd_chip *chip = zd_rf_to_chip(rf);
45
46 static const struct zd_ioreq16 ioreqs[] = {
47 { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 },
48 { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 },
49 { CR44, 0x33 }, { CR106, 0x2a }, { CR107, 0x1a },
50 { CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b },
51 { CR112, 0x2b }, { CR119, 0x0a }, { CR10, 0x89 },
52 /* for newest (3rd cut) AL2300 */
53 { CR17, 0x28 },
54 { CR26, 0x93 }, { CR34, 0x30 },
55 /* for newest (3rd cut) AL2300 */
56 { CR35, 0x3e },
57 { CR41, 0x24 }, { CR44, 0x32 },
58 /* for newest (3rd cut) AL2300 */
59 { CR46, 0x96 },
60 { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 },
61 { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
62 { CR92, 0x0a }, { CR99, 0x28 }, { CR100, 0x00 },
63 { CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 },
64 { CR107, 0x2a }, { CR109, 0x09 }, { CR110, 0x13 },
65 { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
66 { CR114, 0x27 },
67 /* for newest (3rd cut) AL2300 */
68 { CR115, 0x24 },
69 { CR116, 0x24 }, { CR117, 0xf4 }, { CR118, 0xfc },
70 { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 },
71 { CR122, 0xe0 }, { CR137, 0x88 }, { CR252, 0xff },
72 { CR253, 0xff },
73
74 /* These following happen separately in the vendor driver */
75 { },
76
77 /* shdnb(PLL_ON)=0 */
78 { CR251, 0x2f },
79 /* shdnb(PLL_ON)=1 */
80 { CR251, 0x3f },
81 { CR138, 0x28 }, { CR203, 0x06 },
82 };
83
84 static const u32 rv[] = {
85 /* Channel 1 */
86 0x03f790,
87 0x033331,
88 0x00000d,
89
90 0x0b3331,
91 0x03b812,
92 0x00fff3,
93 0x000da4,
94 0x0f4dc5, /* fix freq shift, 0x04edc5 */
95 0x0805b6,
96 0x011687,
97 0x000688,
98 0x0403b9, /* external control TX power (CR31) */
99 0x00dbba,
100 0x00099b,
101 0x0bdffc,
102 0x00000d,
103 0x00500f,
104
105 /* These writes happen separately in the vendor driver */
106 0x00d00f,
107 0x004c0f,
108 0x00540f,
109 0x00700f,
110 0x00500f,
111 };
112
113 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
114 if (r)
115 return r;
116
117 r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
118 if (r)
119 return r;
120
121 return 0;
122}
123
124static int zd1211b_al2230_init_hw(struct zd_rf *rf)
125{
126 int r;
127 struct zd_chip *chip = zd_rf_to_chip(rf);
128
129 static const struct zd_ioreq16 ioreqs1[] = {
130 { CR10, 0x89 }, { CR15, 0x20 },
131 { CR17, 0x2B }, /* for newest(3rd cut) AL2230 */
132 { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 },
133 { CR28, 0x3e }, { CR29, 0x00 },
134 { CR33, 0x28 }, /* 5621 */
135 { CR34, 0x30 },
136 { CR35, 0x3e }, /* for newest(3rd cut) AL2230 */
137 { CR41, 0x24 }, { CR44, 0x32 },
138 { CR46, 0x99 }, /* for newest(3rd cut) AL2230 */
139 { CR47, 0x1e },
140
141 /* ZD1211B 05.06.10 */
142 { CR48, 0x00 }, { CR49, 0x00 }, { CR51, 0x01 },
143 { CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 },
144 { CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 },
145 { CR69, 0x28 },
146
147 { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
148 { CR87, 0x0a }, { CR89, 0x04 },
149 { CR91, 0x00 }, /* 5621 */
150 { CR92, 0x0a },
151 { CR98, 0x8d }, /* 4804, for 1212 new algorithm */
152 { CR99, 0x00 }, /* 5621 */
153 { CR101, 0x13 }, { CR102, 0x27 },
154 { CR106, 0x24 }, /* for newest(3rd cut) AL2230 */
155 { CR107, 0x2a },
156 { CR109, 0x13 }, /* 4804, for 1212 new algorithm */
157 { CR110, 0x1f }, /* 4804, for 1212 new algorithm */
158 { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
159 { CR114, 0x27 },
160 { CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut) AL2230 */
161 { CR116, 0x24 },
162 { CR117, 0xfa }, /* for 1211b */
163 { CR118, 0xfa }, /* for 1211b */
164 { CR119, 0x10 },
165 { CR120, 0x4f },
166 { CR121, 0x6c }, /* for 1211b */
167 { CR122, 0xfc }, /* E0->FC at 4902 */
168 { CR123, 0x57 }, /* 5623 */
169 { CR125, 0xad }, /* 4804, for 1212 new algorithm */
170 { CR126, 0x6c }, /* 5614 */
171 { CR127, 0x03 }, /* 4804, for 1212 new algorithm */
172 { CR137, 0x50 }, /* 5614 */
173 { CR138, 0xa8 },
174 { CR144, 0xac }, /* 5621 */
175 { CR150, 0x0d }, { CR252, 0x00 }, { CR253, 0x00 },
176 };
177
178 static const u32 rv1[] = {
179 /* channel 1 */
180 0x03f790,
181 0x033331,
182 0x00000d,
183
184 0x0b3331,
185 0x03b812,
186 0x00fff3,
187 0x0005a4,
188 0x0f4dc5, /* fix freq shift 0x044dc5 */
189 0x0805b6,
190 0x0146c7,
191 0x000688,
192 0x0403b9, /* External control TX power (CR31) */
193 0x00dbba,
194 0x00099b,
195 0x0bdffc,
196 0x00000d,
197 0x00580f,
198 };
199
200 static const struct zd_ioreq16 ioreqs2[] = {
201 { CR47, 0x1e }, { CR_RFCFG, 0x03 },
202 };
203
204 static const u32 rv2[] = {
205 0x00880f,
206 0x00080f,
207 };
208
209 static const struct zd_ioreq16 ioreqs3[] = {
210 { CR_RFCFG, 0x00 }, { CR47, 0x1e }, { CR251, 0x7f },
211 };
212
213 static const u32 rv3[] = {
214 0x00d80f,
215 0x00780f,
216 0x00580f,
217 };
218
219 static const struct zd_ioreq16 ioreqs4[] = {
220 { CR138, 0x28 }, { CR203, 0x06 },
221 };
222
223 r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1));
224 if (r)
225 return r;
226 r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS);
227 if (r)
228 return r;
229 r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2));
230 if (r)
231 return r;
232 r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS);
233 if (r)
234 return r;
235 r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3));
236 if (r)
237 return r;
238 r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS);
239 if (r)
240 return r;
241 return zd_iowrite16a_locked(chip, ioreqs4, ARRAY_SIZE(ioreqs4));
242}
243
244static int al2230_set_channel(struct zd_rf *rf, u8 channel)
245{
246 int r;
247 const u32 *rv = al2230_table[channel-1];
248 struct zd_chip *chip = zd_rf_to_chip(rf);
249 static const struct zd_ioreq16 ioreqs[] = {
250 { CR138, 0x28 },
251 { CR203, 0x06 },
252 };
253
254 r = zd_rfwritev_locked(chip, rv, 3, RF_RV_BITS);
255 if (r)
256 return r;
257 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
258}
259
260static int zd1211_al2230_switch_radio_on(struct zd_rf *rf)
261{
262 struct zd_chip *chip = zd_rf_to_chip(rf);
263 static const struct zd_ioreq16 ioreqs[] = {
264 { CR11, 0x00 },
265 { CR251, 0x3f },
266 };
267
268 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
269}
270
271static int zd1211b_al2230_switch_radio_on(struct zd_rf *rf)
272{
273 struct zd_chip *chip = zd_rf_to_chip(rf);
274 static const struct zd_ioreq16 ioreqs[] = {
275 { CR11, 0x00 },
276 { CR251, 0x7f },
277 };
278
279 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
280}
281
282static int al2230_switch_radio_off(struct zd_rf *rf)
283{
284 struct zd_chip *chip = zd_rf_to_chip(rf);
285 static const struct zd_ioreq16 ioreqs[] = {
286 { CR11, 0x04 },
287 { CR251, 0x2f },
288 };
289
290 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
291}
292
293int zd_rf_init_al2230(struct zd_rf *rf)
294{
295 struct zd_chip *chip = zd_rf_to_chip(rf);
296
297 rf->set_channel = al2230_set_channel;
298 rf->switch_radio_off = al2230_switch_radio_off;
299 if (chip->is_zd1211b) {
300 rf->init_hw = zd1211b_al2230_init_hw;
301 rf->switch_radio_on = zd1211b_al2230_switch_radio_on;
302 } else {
303 rf->init_hw = zd1211_al2230_init_hw;
304 rf->switch_radio_on = zd1211_al2230_switch_radio_on;
305 }
306 rf->patch_6m_band_edge = 1;
307 return 0;
308}
diff --git a/drivers/net/wireless/zd1211rw/zd_rf_rf2959.c b/drivers/net/wireless/zd1211rw/zd_rf_rf2959.c
new file mode 100644
index 000000000000..58247271cc24
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_rf_rf2959.c
@@ -0,0 +1,279 @@
1/* zd_rf_rfmd.c: Functions for the RFMD RF controller
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#include <linux/kernel.h>
19
20#include "zd_rf.h"
21#include "zd_usb.h"
22#include "zd_chip.h"
23
24static u32 rf2959_table[][2] = {
25 RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
26 RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
27 RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
28 RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
29 RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
30 RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
31 RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
32 RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
33 RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
34 RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
35 RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
36 RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
37 RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
38 RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
39};
40
41#if 0
42static int bits(u32 rw, int from, int to)
43{
44 rw &= ~(0xffffffffU << (to+1));
45 rw >>= from;
46 return rw;
47}
48
49static int bit(u32 rw, int bit)
50{
51 return bits(rw, bit, bit);
52}
53
54static void dump_regwrite(u32 rw)
55{
56 int reg = bits(rw, 18, 22);
57 int rw_flag = bits(rw, 23, 23);
58 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
59
60 switch (reg) {
61 case 0:
62 PDEBUG("reg0 CFG1 ref_sel %d hybernate %d rf_vco_reg_en %d"
63 " if_vco_reg_en %d if_vga_en %d",
64 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
65 bit(rw, 0));
66 break;
67 case 1:
68 PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
69 " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
70 " ifloopc %d dac1 %d",
71 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
72 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
73 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
74 break;
75 case 2:
76 PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
77 bits(rw, 6, 17), bits(rw, 0, 5));
78 break;
79 case 3:
80 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
81 break;
82 case 4:
83 PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
84 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
85 break;
86 case 5:
87 PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
88 " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
89 " dac %d",
90 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
91 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
92 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
93 break;
94 case 6:
95 PDEBUG("reg6 RFPLL2 n %d num %d",
96 bits(rw, 6, 17), bits(rw, 0, 5));
97 break;
98 case 7:
99 PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
100 break;
101 case 8:
102 PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
103 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
104 break;
105 case 9:
106 PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
107 bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
108 bits(rw, 0, 2));
109 break;
110 case 10:
111 PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
112 " rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
113 " intbiasen %d tybypass %d",
114 bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
115 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
116 bit(rw, 1), bit(rw, 0));
117 break;
118 case 11:
119 PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
120 " tx_delay %d",
121 bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
122 bits(rw, 0, 2));
123 break;
124 case 12:
125 PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
126 bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
127 break;
128 case 13:
129 PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
130 " lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
131 " rf_biasvco %d",
132 bit(rw, 17), bit(rw, 16), bit(rw, 15),
133 bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
134 bits(rw, 0, 2));
135 break;
136 case 14:
137 PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
138 " tx_acal %d tx_pcal %d",
139 bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
140 bits(rw, 0, 3));
141 break;
142 }
143}
144#endif /* 0 */
145
146static int rf2959_init_hw(struct zd_rf *rf)
147{
148 int r;
149 struct zd_chip *chip = zd_rf_to_chip(rf);
150
151 static const struct zd_ioreq16 ioreqs[] = {
152 { CR2, 0x1E }, { CR9, 0x20 }, { CR10, 0x89 },
153 { CR11, 0x00 }, { CR15, 0xD0 }, { CR17, 0x68 },
154 { CR19, 0x4a }, { CR20, 0x0c }, { CR21, 0x0E },
155 { CR23, 0x48 },
156 /* normal size for cca threshold */
157 { CR24, 0x14 },
158 /* { CR24, 0x20 }, */
159 { CR26, 0x90 }, { CR27, 0x30 }, { CR29, 0x20 },
160 { CR31, 0xb2 }, { CR32, 0x43 }, { CR33, 0x28 },
161 { CR38, 0x30 }, { CR34, 0x0f }, { CR35, 0xF0 },
162 { CR41, 0x2a }, { CR46, 0x7F }, { CR47, 0x1E },
163 { CR51, 0xc5 }, { CR52, 0xc5 }, { CR53, 0xc5 },
164 { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
165 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
166 { CR85, 0x00 }, { CR86, 0x10 }, { CR87, 0x2A },
167 { CR88, 0x10 }, { CR89, 0x24 }, { CR90, 0x18 },
168 /* { CR91, 0x18 }, */
169 /* should solve continous CTS frame problems */
170 { CR91, 0x00 },
171 { CR92, 0x0a }, { CR93, 0x00 }, { CR94, 0x01 },
172 { CR95, 0x00 }, { CR96, 0x40 }, { CR97, 0x37 },
173 { CR98, 0x05 }, { CR99, 0x28 }, { CR100, 0x00 },
174 { CR101, 0x13 }, { CR102, 0x27 }, { CR103, 0x27 },
175 { CR104, 0x18 }, { CR105, 0x12 },
176 /* normal size */
177 { CR106, 0x1a },
178 /* { CR106, 0x22 }, */
179 { CR107, 0x24 }, { CR108, 0x0a }, { CR109, 0x13 },
180 { CR110, 0x2F }, { CR111, 0x27 }, { CR112, 0x27 },
181 { CR113, 0x27 }, { CR114, 0x27 }, { CR115, 0x40 },
182 { CR116, 0x40 }, { CR117, 0xF0 }, { CR118, 0xF0 },
183 { CR119, 0x16 },
184 /* no TX continuation */
185 { CR122, 0x00 },
186 /* { CR122, 0xff }, */
187 { CR127, 0x03 }, { CR131, 0x08 }, { CR138, 0x28 },
188 { CR148, 0x44 }, { CR150, 0x10 }, { CR169, 0xBB },
189 { CR170, 0xBB },
190 };
191
192 static const u32 rv[] = {
193 0x000007, /* REG0(CFG1) */
194 0x07dd43, /* REG1(IFPLL1) */
195 0x080959, /* REG2(IFPLL2) */
196 0x0e6666,
197 0x116a57, /* REG4 */
198 0x17dd43, /* REG5 */
199 0x1819f9, /* REG6 */
200 0x1e6666,
201 0x214554,
202 0x25e7fa,
203 0x27fffa,
204 /* The Zydas driver somehow forgets to set this value. It's
205 * only set for Japan. We are using internal power control
206 * for now.
207 */
208 0x294128, /* internal power */
209 /* 0x28252c, */ /* External control TX power */
210 /* CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M */
211 0x2c0000,
212 0x300000,
213 0x340000, /* REG13(0xD) */
214 0x381e0f, /* REG14(0xE) */
215 /* Bogus, RF2959's data sheet doesn't know register 27, which is
216 * actually referenced here. The commented 0x11 is 17.
217 */
218 0x6c180f, /* REG27(0x11) */
219 };
220
221 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
222 if (r)
223 return r;
224
225 return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
226}
227
228static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
229{
230 int i, r;
231 u32 *rv = rf2959_table[channel-1];
232 struct zd_chip *chip = zd_rf_to_chip(rf);
233
234 for (i = 0; i < 2; i++) {
235 r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
236 if (r)
237 return r;
238 }
239 return 0;
240}
241
242static int rf2959_switch_radio_on(struct zd_rf *rf)
243{
244 static const struct zd_ioreq16 ioreqs[] = {
245 { CR10, 0x89 },
246 { CR11, 0x00 },
247 };
248 struct zd_chip *chip = zd_rf_to_chip(rf);
249
250 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
251}
252
253static int rf2959_switch_radio_off(struct zd_rf *rf)
254{
255 static const struct zd_ioreq16 ioreqs[] = {
256 { CR10, 0x15 },
257 { CR11, 0x81 },
258 };
259 struct zd_chip *chip = zd_rf_to_chip(rf);
260
261 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
262}
263
264int zd_rf_init_rf2959(struct zd_rf *rf)
265{
266 struct zd_chip *chip = zd_rf_to_chip(rf);
267
268 if (chip->is_zd1211b) {
269 dev_err(zd_chip_dev(chip),
270 "RF2959 is currently not supported for ZD1211B"
271 " devices\n");
272 return -ENODEV;
273 }
274 rf->init_hw = rf2959_init_hw;
275 rf->set_channel = rf2959_set_channel;
276 rf->switch_radio_on = rf2959_switch_radio_on;
277 rf->switch_radio_off = rf2959_switch_radio_off;
278 return 0;
279}
diff --git a/drivers/net/wireless/zd1211rw/zd_types.h b/drivers/net/wireless/zd1211rw/zd_types.h
new file mode 100644
index 000000000000..0155a1584ed3
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_types.h
@@ -0,0 +1,71 @@
1/* zd_types.h
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_TYPES_H
19#define _ZD_TYPES_H
20
21#include <linux/types.h>
22
23/* We have three register spaces mapped into the overall USB address space of
24 * 64K words (16-bit values). There is the control register space of
25 * double-word registers, the eeprom register space and the firmware register
26 * space. The control register space is byte mapped, the others are word
27 * mapped.
28 *
29 * For that reason, we are using byte offsets for control registers and word
30 * offsets for everything else.
31 */
32
33typedef u32 __nocast zd_addr_t;
34
35enum {
36 ADDR_BASE_MASK = 0xff000000,
37 ADDR_OFFSET_MASK = 0x0000ffff,
38 ADDR_ZERO_MASK = 0x00ff0000,
39 NULL_BASE = 0x00000000,
40 USB_BASE = 0x01000000,
41 CR_BASE = 0x02000000,
42 CR_MAX_OFFSET = 0x0b30,
43 E2P_BASE = 0x03000000,
44 E2P_MAX_OFFSET = 0x007e,
45 FW_BASE = 0x04000000,
46 FW_MAX_OFFSET = 0x0005,
47};
48
49#define ZD_ADDR_BASE(addr) ((u32)(addr) & ADDR_BASE_MASK)
50#define ZD_OFFSET(addr) ((u32)(addr) & ADDR_OFFSET_MASK)
51
52#define ZD_ADDR(base, offset) \
53 ((zd_addr_t)(((base) & ADDR_BASE_MASK) | ((offset) & ADDR_OFFSET_MASK)))
54
55#define ZD_NULL_ADDR ((zd_addr_t)0)
56#define USB_REG(offset) ZD_ADDR(USB_BASE, offset) /* word addressing */
57#define CTL_REG(offset) ZD_ADDR(CR_BASE, offset) /* byte addressing */
58#define E2P_REG(offset) ZD_ADDR(E2P_BASE, offset) /* word addressing */
59#define FW_REG(offset) ZD_ADDR(FW_BASE, offset) /* word addressing */
60
61static inline zd_addr_t zd_inc_word(zd_addr_t addr)
62{
63 u32 base = ZD_ADDR_BASE(addr);
64 u32 offset = ZD_OFFSET(addr);
65
66 offset += base == CR_BASE ? 2 : 1;
67
68 return base | offset;
69}
70
71#endif /* _ZD_TYPES_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.c b/drivers/net/wireless/zd1211rw/zd_usb.c
new file mode 100644
index 000000000000..6320984126c7
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_usb.c
@@ -0,0 +1,1309 @@
1/* zd_usb.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#include <asm/unaligned.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/firmware.h>
22#include <linux/device.h>
23#include <linux/errno.h>
24#include <linux/skbuff.h>
25#include <linux/usb.h>
26#include <net/ieee80211.h>
27
28#include "zd_def.h"
29#include "zd_netdev.h"
30#include "zd_mac.h"
31#include "zd_usb.h"
32#include "zd_util.h"
33
34static struct usb_device_id usb_ids[] = {
35 /* ZD1211 */
36 { USB_DEVICE(0x0ace, 0x1211), .driver_info = DEVICE_ZD1211 },
37 { USB_DEVICE(0x07b8, 0x6001), .driver_info = DEVICE_ZD1211 },
38 { USB_DEVICE(0x126f, 0xa006), .driver_info = DEVICE_ZD1211 },
39 { USB_DEVICE(0x6891, 0xa727), .driver_info = DEVICE_ZD1211 },
40 { USB_DEVICE(0x0df6, 0x9071), .driver_info = DEVICE_ZD1211 },
41 { USB_DEVICE(0x157e, 0x300b), .driver_info = DEVICE_ZD1211 },
42 /* ZD1211B */
43 { USB_DEVICE(0x0ace, 0x1215), .driver_info = DEVICE_ZD1211B },
44 { USB_DEVICE(0x157e, 0x300d), .driver_info = DEVICE_ZD1211B },
45 {}
46};
47
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("USB driver for devices with the ZD1211 chip.");
50MODULE_AUTHOR("Ulrich Kunitz");
51MODULE_AUTHOR("Daniel Drake");
52MODULE_VERSION("1.0");
53MODULE_DEVICE_TABLE(usb, usb_ids);
54
55#define FW_ZD1211_PREFIX "zd1211/zd1211_"
56#define FW_ZD1211B_PREFIX "zd1211/zd1211b_"
57
58/* register address handling */
59
60#ifdef DEBUG
61static int check_addr(struct zd_usb *usb, zd_addr_t addr)
62{
63 u32 base = ZD_ADDR_BASE(addr);
64 u32 offset = ZD_OFFSET(addr);
65
66 if ((u32)addr & ADDR_ZERO_MASK)
67 goto invalid_address;
68 switch (base) {
69 case USB_BASE:
70 break;
71 case CR_BASE:
72 if (offset > CR_MAX_OFFSET) {
73 dev_dbg(zd_usb_dev(usb),
74 "CR offset %#010x larger than"
75 " CR_MAX_OFFSET %#10x\n",
76 offset, CR_MAX_OFFSET);
77 goto invalid_address;
78 }
79 if (offset & 1) {
80 dev_dbg(zd_usb_dev(usb),
81 "CR offset %#010x is not a multiple of 2\n",
82 offset);
83 goto invalid_address;
84 }
85 break;
86 case E2P_BASE:
87 if (offset > E2P_MAX_OFFSET) {
88 dev_dbg(zd_usb_dev(usb),
89 "E2P offset %#010x larger than"
90 " E2P_MAX_OFFSET %#010x\n",
91 offset, E2P_MAX_OFFSET);
92 goto invalid_address;
93 }
94 break;
95 case FW_BASE:
96 if (!usb->fw_base_offset) {
97 dev_dbg(zd_usb_dev(usb),
98 "ERROR: fw base offset has not been set\n");
99 return -EAGAIN;
100 }
101 if (offset > FW_MAX_OFFSET) {
102 dev_dbg(zd_usb_dev(usb),
103 "FW offset %#10x is larger than"
104 " FW_MAX_OFFSET %#010x\n",
105 offset, FW_MAX_OFFSET);
106 goto invalid_address;
107 }
108 break;
109 default:
110 dev_dbg(zd_usb_dev(usb),
111 "address has unsupported base %#010x\n", addr);
112 goto invalid_address;
113 }
114
115 return 0;
116invalid_address:
117 dev_dbg(zd_usb_dev(usb),
118 "ERROR: invalid address: %#010x\n", addr);
119 return -EINVAL;
120}
121#endif /* DEBUG */
122
123static u16 usb_addr(struct zd_usb *usb, zd_addr_t addr)
124{
125 u32 base;
126 u16 offset;
127
128 base = ZD_ADDR_BASE(addr);
129 offset = ZD_OFFSET(addr);
130
131 ZD_ASSERT(check_addr(usb, addr) == 0);
132
133 switch (base) {
134 case CR_BASE:
135 offset += CR_BASE_OFFSET;
136 break;
137 case E2P_BASE:
138 offset += E2P_BASE_OFFSET;
139 break;
140 case FW_BASE:
141 offset += usb->fw_base_offset;
142 break;
143 }
144
145 return offset;
146}
147
148/* USB device initialization */
149
150static int request_fw_file(
151 const struct firmware **fw, const char *name, struct device *device)
152{
153 int r;
154
155 dev_dbg_f(device, "fw name %s\n", name);
156
157 r = request_firmware(fw, name, device);
158 if (r)
159 dev_err(device,
160 "Could not load firmware file %s. Error number %d\n",
161 name, r);
162 return r;
163}
164
165static inline u16 get_bcdDevice(const struct usb_device *udev)
166{
167 return le16_to_cpu(udev->descriptor.bcdDevice);
168}
169
170enum upload_code_flags {
171 REBOOT = 1,
172};
173
174/* Ensures that MAX_TRANSFER_SIZE is even. */
175#define MAX_TRANSFER_SIZE (USB_MAX_TRANSFER_SIZE & ~1)
176
177static int upload_code(struct usb_device *udev,
178 const u8 *data, size_t size, u16 code_offset, int flags)
179{
180 u8 *p;
181 int r;
182
183 /* USB request blocks need "kmalloced" buffers.
184 */
185 p = kmalloc(MAX_TRANSFER_SIZE, GFP_KERNEL);
186 if (!p) {
187 dev_err(&udev->dev, "out of memory\n");
188 r = -ENOMEM;
189 goto error;
190 }
191
192 size &= ~1;
193 while (size > 0) {
194 size_t transfer_size = size <= MAX_TRANSFER_SIZE ?
195 size : MAX_TRANSFER_SIZE;
196
197 dev_dbg_f(&udev->dev, "transfer size %zu\n", transfer_size);
198
199 memcpy(p, data, transfer_size);
200 r = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
201 USB_REQ_FIRMWARE_DOWNLOAD,
202 USB_DIR_OUT | USB_TYPE_VENDOR,
203 code_offset, 0, p, transfer_size, 1000 /* ms */);
204 if (r < 0) {
205 dev_err(&udev->dev,
206 "USB control request for firmware upload"
207 " failed. Error number %d\n", r);
208 goto error;
209 }
210 transfer_size = r & ~1;
211
212 size -= transfer_size;
213 data += transfer_size;
214 code_offset += transfer_size/sizeof(u16);
215 }
216
217 if (flags & REBOOT) {
218 u8 ret;
219
220 r = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
221 USB_REQ_FIRMWARE_CONFIRM,
222 USB_DIR_IN | USB_TYPE_VENDOR,
223 0, 0, &ret, sizeof(ret), 5000 /* ms */);
224 if (r != sizeof(ret)) {
225 dev_err(&udev->dev,
226 "control request firmeware confirmation failed."
227 " Return value %d\n", r);
228 if (r >= 0)
229 r = -ENODEV;
230 goto error;
231 }
232 if (ret & 0x80) {
233 dev_err(&udev->dev,
234 "Internal error while downloading."
235 " Firmware confirm return value %#04x\n",
236 (unsigned int)ret);
237 r = -ENODEV;
238 goto error;
239 }
240 dev_dbg_f(&udev->dev, "firmware confirm return value %#04x\n",
241 (unsigned int)ret);
242 }
243
244 r = 0;
245error:
246 kfree(p);
247 return r;
248}
249
250static u16 get_word(const void *data, u16 offset)
251{
252 const __le16 *p = data;
253 return le16_to_cpu(p[offset]);
254}
255
256static char *get_fw_name(char *buffer, size_t size, u8 device_type,
257 const char* postfix)
258{
259 scnprintf(buffer, size, "%s%s",
260 device_type == DEVICE_ZD1211B ?
261 FW_ZD1211B_PREFIX : FW_ZD1211_PREFIX,
262 postfix);
263 return buffer;
264}
265
266static int upload_firmware(struct usb_device *udev, u8 device_type)
267{
268 int r;
269 u16 fw_bcdDevice;
270 u16 bcdDevice;
271 const struct firmware *ub_fw = NULL;
272 const struct firmware *uph_fw = NULL;
273 char fw_name[128];
274
275 bcdDevice = get_bcdDevice(udev);
276
277 r = request_fw_file(&ub_fw,
278 get_fw_name(fw_name, sizeof(fw_name), device_type, "ub"),
279 &udev->dev);
280 if (r)
281 goto error;
282
283 fw_bcdDevice = get_word(ub_fw->data, EEPROM_REGS_OFFSET);
284
285 /* FIXME: do we have any reason to perform the kludge that the vendor
286 * driver does when there is a version mismatch? (their driver uploads
287 * different firmwares and stuff)
288 */
289 if (fw_bcdDevice != bcdDevice) {
290 dev_info(&udev->dev,
291 "firmware device id %#06x and actual device id "
292 "%#06x differ, continuing anyway\n",
293 fw_bcdDevice, bcdDevice);
294 } else {
295 dev_dbg_f(&udev->dev,
296 "firmware device id %#06x is equal to the "
297 "actual device id\n", fw_bcdDevice);
298 }
299
300
301 r = request_fw_file(&uph_fw,
302 get_fw_name(fw_name, sizeof(fw_name), device_type, "uphr"),
303 &udev->dev);
304 if (r)
305 goto error;
306
307 r = upload_code(udev, uph_fw->data, uph_fw->size, FW_START_OFFSET,
308 REBOOT);
309 if (r) {
310 dev_err(&udev->dev,
311 "Could not upload firmware code uph. Error number %d\n",
312 r);
313 }
314
315 /* FALL-THROUGH */
316error:
317 release_firmware(ub_fw);
318 release_firmware(uph_fw);
319 return r;
320}
321
322static void disable_read_regs_int(struct zd_usb *usb)
323{
324 struct zd_usb_interrupt *intr = &usb->intr;
325
326 spin_lock(&intr->lock);
327 intr->read_regs_enabled = 0;
328 spin_unlock(&intr->lock);
329}
330
331#define urb_dev(urb) (&(urb)->dev->dev)
332
333static inline void handle_regs_int(struct urb *urb)
334{
335 struct zd_usb *usb = urb->context;
336 struct zd_usb_interrupt *intr = &usb->intr;
337 int len;
338
339 ZD_ASSERT(in_interrupt());
340 spin_lock(&intr->lock);
341
342 if (intr->read_regs_enabled) {
343 intr->read_regs.length = len = urb->actual_length;
344
345 if (len > sizeof(intr->read_regs.buffer))
346 len = sizeof(intr->read_regs.buffer);
347 memcpy(intr->read_regs.buffer, urb->transfer_buffer, len);
348 intr->read_regs_enabled = 0;
349 complete(&intr->read_regs.completion);
350 goto out;
351 }
352
353 dev_dbg_f(urb_dev(urb), "regs interrupt ignored\n");
354out:
355 spin_unlock(&intr->lock);
356}
357
358static inline void handle_retry_failed_int(struct urb *urb)
359{
360 dev_dbg_f(urb_dev(urb), "retry failed interrupt\n");
361}
362
363
364static void int_urb_complete(struct urb *urb, struct pt_regs *pt_regs)
365{
366 int r;
367 struct usb_int_header *hdr;
368
369 switch (urb->status) {
370 case 0:
371 break;
372 case -ESHUTDOWN:
373 case -EINVAL:
374 case -ENODEV:
375 case -ENOENT:
376 case -ECONNRESET:
377 case -EPIPE:
378 goto kfree;
379 default:
380 goto resubmit;
381 }
382
383 if (urb->actual_length < sizeof(hdr)) {
384 dev_dbg_f(urb_dev(urb), "error: urb %p to small\n", urb);
385 goto resubmit;
386 }
387
388 hdr = urb->transfer_buffer;
389 if (hdr->type != USB_INT_TYPE) {
390 dev_dbg_f(urb_dev(urb), "error: urb %p wrong type\n", urb);
391 goto resubmit;
392 }
393
394 switch (hdr->id) {
395 case USB_INT_ID_REGS:
396 handle_regs_int(urb);
397 break;
398 case USB_INT_ID_RETRY_FAILED:
399 handle_retry_failed_int(urb);
400 break;
401 default:
402 dev_dbg_f(urb_dev(urb), "error: urb %p unknown id %x\n", urb,
403 (unsigned int)hdr->id);
404 goto resubmit;
405 }
406
407resubmit:
408 r = usb_submit_urb(urb, GFP_ATOMIC);
409 if (r) {
410 dev_dbg_f(urb_dev(urb), "resubmit urb %p\n", urb);
411 goto kfree;
412 }
413 return;
414kfree:
415 kfree(urb->transfer_buffer);
416}
417
418static inline int int_urb_interval(struct usb_device *udev)
419{
420 switch (udev->speed) {
421 case USB_SPEED_HIGH:
422 return 4;
423 case USB_SPEED_LOW:
424 return 10;
425 case USB_SPEED_FULL:
426 default:
427 return 1;
428 }
429}
430
431static inline int usb_int_enabled(struct zd_usb *usb)
432{
433 unsigned long flags;
434 struct zd_usb_interrupt *intr = &usb->intr;
435 struct urb *urb;
436
437 spin_lock_irqsave(&intr->lock, flags);
438 urb = intr->urb;
439 spin_unlock_irqrestore(&intr->lock, flags);
440 return urb != NULL;
441}
442
443int zd_usb_enable_int(struct zd_usb *usb)
444{
445 int r;
446 struct usb_device *udev;
447 struct zd_usb_interrupt *intr = &usb->intr;
448 void *transfer_buffer = NULL;
449 struct urb *urb;
450
451 dev_dbg_f(zd_usb_dev(usb), "\n");
452
453 urb = usb_alloc_urb(0, GFP_NOFS);
454 if (!urb) {
455 r = -ENOMEM;
456 goto out;
457 }
458
459 ZD_ASSERT(!irqs_disabled());
460 spin_lock_irq(&intr->lock);
461 if (intr->urb) {
462 spin_unlock_irq(&intr->lock);
463 r = 0;
464 goto error_free_urb;
465 }
466 intr->urb = urb;
467 spin_unlock_irq(&intr->lock);
468
469 /* TODO: make it a DMA buffer */
470 r = -ENOMEM;
471 transfer_buffer = kmalloc(USB_MAX_EP_INT_BUFFER, GFP_NOFS);
472 if (!transfer_buffer) {
473 dev_dbg_f(zd_usb_dev(usb),
474 "couldn't allocate transfer_buffer\n");
475 goto error_set_urb_null;
476 }
477
478 udev = zd_usb_to_usbdev(usb);
479 usb_fill_int_urb(urb, udev, usb_rcvintpipe(udev, EP_INT_IN),
480 transfer_buffer, USB_MAX_EP_INT_BUFFER,
481 int_urb_complete, usb,
482 intr->interval);
483
484 dev_dbg_f(zd_usb_dev(usb), "submit urb %p\n", intr->urb);
485 r = usb_submit_urb(urb, GFP_NOFS);
486 if (r) {
487 dev_dbg_f(zd_usb_dev(usb),
488 "Couldn't submit urb. Error number %d\n", r);
489 goto error;
490 }
491
492 return 0;
493error:
494 kfree(transfer_buffer);
495error_set_urb_null:
496 spin_lock_irq(&intr->lock);
497 intr->urb = NULL;
498 spin_unlock_irq(&intr->lock);
499error_free_urb:
500 usb_free_urb(urb);
501out:
502 return r;
503}
504
505void zd_usb_disable_int(struct zd_usb *usb)
506{
507 unsigned long flags;
508 struct zd_usb_interrupt *intr = &usb->intr;
509 struct urb *urb;
510
511 spin_lock_irqsave(&intr->lock, flags);
512 urb = intr->urb;
513 if (!urb) {
514 spin_unlock_irqrestore(&intr->lock, flags);
515 return;
516 }
517 intr->urb = NULL;
518 spin_unlock_irqrestore(&intr->lock, flags);
519
520 usb_kill_urb(urb);
521 dev_dbg_f(zd_usb_dev(usb), "urb %p killed\n", urb);
522 usb_free_urb(urb);
523}
524
525static void handle_rx_packet(struct zd_usb *usb, const u8 *buffer,
526 unsigned int length)
527{
528 int i;
529 struct zd_mac *mac = zd_usb_to_mac(usb);
530 const struct rx_length_info *length_info;
531
532 if (length < sizeof(struct rx_length_info)) {
533 /* It's not a complete packet anyhow. */
534 return;
535 }
536 length_info = (struct rx_length_info *)
537 (buffer + length - sizeof(struct rx_length_info));
538
539 /* It might be that three frames are merged into a single URB
540 * transaction. We have to check for the length info tag.
541 *
542 * While testing we discovered that length_info might be unaligned,
543 * because if USB transactions are merged, the last packet will not
544 * be padded. Unaligned access might also happen if the length_info
545 * structure is not present.
546 */
547 if (get_unaligned(&length_info->tag) == cpu_to_le16(RX_LENGTH_INFO_TAG))
548 {
549 unsigned int l, k, n;
550 for (i = 0, l = 0;; i++) {
551 k = le16_to_cpu(get_unaligned(&length_info->length[i]));
552 n = l+k;
553 if (n > length)
554 return;
555 zd_mac_rx(mac, buffer+l, k);
556 if (i >= 2)
557 return;
558 l = (n+3) & ~3;
559 }
560 } else {
561 zd_mac_rx(mac, buffer, length);
562 }
563}
564
565static void rx_urb_complete(struct urb *urb, struct pt_regs *pt_regs)
566{
567 struct zd_usb *usb;
568 struct zd_usb_rx *rx;
569 const u8 *buffer;
570 unsigned int length;
571
572 switch (urb->status) {
573 case 0:
574 break;
575 case -ESHUTDOWN:
576 case -EINVAL:
577 case -ENODEV:
578 case -ENOENT:
579 case -ECONNRESET:
580 case -EPIPE:
581 return;
582 default:
583 dev_dbg_f(urb_dev(urb), "urb %p error %d\n", urb, urb->status);
584 goto resubmit;
585 }
586
587 buffer = urb->transfer_buffer;
588 length = urb->actual_length;
589 usb = urb->context;
590 rx = &usb->rx;
591
592 if (length%rx->usb_packet_size > rx->usb_packet_size-4) {
593 /* If there is an old first fragment, we don't care. */
594 dev_dbg_f(urb_dev(urb), "*** first fragment ***\n");
595 ZD_ASSERT(length <= ARRAY_SIZE(rx->fragment));
596 spin_lock(&rx->lock);
597 memcpy(rx->fragment, buffer, length);
598 rx->fragment_length = length;
599 spin_unlock(&rx->lock);
600 goto resubmit;
601 }
602
603 spin_lock(&rx->lock);
604 if (rx->fragment_length > 0) {
605 /* We are on a second fragment, we believe */
606 ZD_ASSERT(length + rx->fragment_length <=
607 ARRAY_SIZE(rx->fragment));
608 dev_dbg_f(urb_dev(urb), "*** second fragment ***\n");
609 memcpy(rx->fragment+rx->fragment_length, buffer, length);
610 handle_rx_packet(usb, rx->fragment,
611 rx->fragment_length + length);
612 rx->fragment_length = 0;
613 spin_unlock(&rx->lock);
614 } else {
615 spin_unlock(&rx->lock);
616 handle_rx_packet(usb, buffer, length);
617 }
618
619resubmit:
620 usb_submit_urb(urb, GFP_ATOMIC);
621}
622
623struct urb *alloc_urb(struct zd_usb *usb)
624{
625 struct usb_device *udev = zd_usb_to_usbdev(usb);
626 struct urb *urb;
627 void *buffer;
628
629 urb = usb_alloc_urb(0, GFP_NOFS);
630 if (!urb)
631 return NULL;
632 buffer = usb_buffer_alloc(udev, USB_MAX_RX_SIZE, GFP_NOFS,
633 &urb->transfer_dma);
634 if (!buffer) {
635 usb_free_urb(urb);
636 return NULL;
637 }
638
639 usb_fill_bulk_urb(urb, udev, usb_rcvbulkpipe(udev, EP_DATA_IN),
640 buffer, USB_MAX_RX_SIZE,
641 rx_urb_complete, usb);
642 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
643
644 return urb;
645}
646
647void free_urb(struct urb *urb)
648{
649 if (!urb)
650 return;
651 usb_buffer_free(urb->dev, urb->transfer_buffer_length,
652 urb->transfer_buffer, urb->transfer_dma);
653 usb_free_urb(urb);
654}
655
656int zd_usb_enable_rx(struct zd_usb *usb)
657{
658 int i, r;
659 struct zd_usb_rx *rx = &usb->rx;
660 struct urb **urbs;
661
662 dev_dbg_f(zd_usb_dev(usb), "\n");
663
664 r = -ENOMEM;
665 urbs = kcalloc(URBS_COUNT, sizeof(struct urb *), GFP_NOFS);
666 if (!urbs)
667 goto error;
668 for (i = 0; i < URBS_COUNT; i++) {
669 urbs[i] = alloc_urb(usb);
670 if (!urbs[i])
671 goto error;
672 }
673
674 ZD_ASSERT(!irqs_disabled());
675 spin_lock_irq(&rx->lock);
676 if (rx->urbs) {
677 spin_unlock_irq(&rx->lock);
678 r = 0;
679 goto error;
680 }
681 rx->urbs = urbs;
682 rx->urbs_count = URBS_COUNT;
683 spin_unlock_irq(&rx->lock);
684
685 for (i = 0; i < URBS_COUNT; i++) {
686 r = usb_submit_urb(urbs[i], GFP_NOFS);
687 if (r)
688 goto error_submit;
689 }
690
691 return 0;
692error_submit:
693 for (i = 0; i < URBS_COUNT; i++) {
694 usb_kill_urb(urbs[i]);
695 }
696 spin_lock_irq(&rx->lock);
697 rx->urbs = NULL;
698 rx->urbs_count = 0;
699 spin_unlock_irq(&rx->lock);
700error:
701 if (urbs) {
702 for (i = 0; i < URBS_COUNT; i++)
703 free_urb(urbs[i]);
704 }
705 return r;
706}
707
708void zd_usb_disable_rx(struct zd_usb *usb)
709{
710 int i;
711 unsigned long flags;
712 struct urb **urbs;
713 unsigned int count;
714 struct zd_usb_rx *rx = &usb->rx;
715
716 spin_lock_irqsave(&rx->lock, flags);
717 urbs = rx->urbs;
718 count = rx->urbs_count;
719 spin_unlock_irqrestore(&rx->lock, flags);
720 if (!urbs)
721 return;
722
723 for (i = 0; i < count; i++) {
724 usb_kill_urb(urbs[i]);
725 free_urb(urbs[i]);
726 }
727 kfree(urbs);
728
729 spin_lock_irqsave(&rx->lock, flags);
730 rx->urbs = NULL;
731 rx->urbs_count = 0;
732 spin_unlock_irqrestore(&rx->lock, flags);
733}
734
735static void tx_urb_complete(struct urb *urb, struct pt_regs *pt_regs)
736{
737 int r;
738
739 switch (urb->status) {
740 case 0:
741 break;
742 case -ESHUTDOWN:
743 case -EINVAL:
744 case -ENODEV:
745 case -ENOENT:
746 case -ECONNRESET:
747 case -EPIPE:
748 dev_dbg_f(urb_dev(urb), "urb %p error %d\n", urb, urb->status);
749 break;
750 default:
751 dev_dbg_f(urb_dev(urb), "urb %p error %d\n", urb, urb->status);
752 goto resubmit;
753 }
754free_urb:
755 usb_buffer_free(urb->dev, urb->transfer_buffer_length,
756 urb->transfer_buffer, urb->transfer_dma);
757 usb_free_urb(urb);
758 return;
759resubmit:
760 r = usb_submit_urb(urb, GFP_ATOMIC);
761 if (r) {
762 dev_dbg_f(urb_dev(urb), "error resubmit urb %p %d\n", urb, r);
763 goto free_urb;
764 }
765}
766
767/* Puts the frame on the USB endpoint. It doesn't wait for
768 * completion. The frame must contain the control set.
769 */
770int zd_usb_tx(struct zd_usb *usb, const u8 *frame, unsigned int length)
771{
772 int r;
773 struct usb_device *udev = zd_usb_to_usbdev(usb);
774 struct urb *urb;
775 void *buffer;
776
777 urb = usb_alloc_urb(0, GFP_ATOMIC);
778 if (!urb) {
779 r = -ENOMEM;
780 goto out;
781 }
782
783 buffer = usb_buffer_alloc(zd_usb_to_usbdev(usb), length, GFP_ATOMIC,
784 &urb->transfer_dma);
785 if (!buffer) {
786 r = -ENOMEM;
787 goto error_free_urb;
788 }
789 memcpy(buffer, frame, length);
790
791 usb_fill_bulk_urb(urb, udev, usb_sndbulkpipe(udev, EP_DATA_OUT),
792 buffer, length, tx_urb_complete, NULL);
793 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
794
795 r = usb_submit_urb(urb, GFP_ATOMIC);
796 if (r)
797 goto error;
798 return 0;
799error:
800 usb_buffer_free(zd_usb_to_usbdev(usb), length, buffer,
801 urb->transfer_dma);
802error_free_urb:
803 usb_free_urb(urb);
804out:
805 return r;
806}
807
808static inline void init_usb_interrupt(struct zd_usb *usb)
809{
810 struct zd_usb_interrupt *intr = &usb->intr;
811
812 spin_lock_init(&intr->lock);
813 intr->interval = int_urb_interval(zd_usb_to_usbdev(usb));
814 init_completion(&intr->read_regs.completion);
815 intr->read_regs.cr_int_addr = cpu_to_le16(usb_addr(usb, CR_INTERRUPT));
816}
817
818static inline void init_usb_rx(struct zd_usb *usb)
819{
820 struct zd_usb_rx *rx = &usb->rx;
821 spin_lock_init(&rx->lock);
822 if (interface_to_usbdev(usb->intf)->speed == USB_SPEED_HIGH) {
823 rx->usb_packet_size = 512;
824 } else {
825 rx->usb_packet_size = 64;
826 }
827 ZD_ASSERT(rx->fragment_length == 0);
828}
829
830static inline void init_usb_tx(struct zd_usb *usb)
831{
832 /* FIXME: at this point we will allocate a fixed number of urb's for
833 * use in a cyclic scheme */
834}
835
836void zd_usb_init(struct zd_usb *usb, struct net_device *netdev,
837 struct usb_interface *intf)
838{
839 memset(usb, 0, sizeof(*usb));
840 usb->intf = usb_get_intf(intf);
841 usb_set_intfdata(usb->intf, netdev);
842 init_usb_interrupt(usb);
843 init_usb_tx(usb);
844 init_usb_rx(usb);
845}
846
847int zd_usb_init_hw(struct zd_usb *usb)
848{
849 int r;
850 struct zd_chip *chip = zd_usb_to_chip(usb);
851
852 ZD_ASSERT(mutex_is_locked(&chip->mutex));
853 r = zd_ioread16_locked(chip, &usb->fw_base_offset,
854 USB_REG((u16)FW_BASE_ADDR_OFFSET));
855 if (r)
856 return r;
857 dev_dbg_f(zd_usb_dev(usb), "fw_base_offset: %#06hx\n",
858 usb->fw_base_offset);
859
860 return 0;
861}
862
863void zd_usb_clear(struct zd_usb *usb)
864{
865 usb_set_intfdata(usb->intf, NULL);
866 usb_put_intf(usb->intf);
867 memset(usb, 0, sizeof(*usb));
868 /* FIXME: usb_interrupt, usb_tx, usb_rx? */
869}
870
871static const char *speed(enum usb_device_speed speed)
872{
873 switch (speed) {
874 case USB_SPEED_LOW:
875 return "low";
876 case USB_SPEED_FULL:
877 return "full";
878 case USB_SPEED_HIGH:
879 return "high";
880 default:
881 return "unknown speed";
882 }
883}
884
885static int scnprint_id(struct usb_device *udev, char *buffer, size_t size)
886{
887 return scnprintf(buffer, size, "%04hx:%04hx v%04hx %s",
888 le16_to_cpu(udev->descriptor.idVendor),
889 le16_to_cpu(udev->descriptor.idProduct),
890 get_bcdDevice(udev),
891 speed(udev->speed));
892}
893
894int zd_usb_scnprint_id(struct zd_usb *usb, char *buffer, size_t size)
895{
896 struct usb_device *udev = interface_to_usbdev(usb->intf);
897 return scnprint_id(udev, buffer, size);
898}
899
900#ifdef DEBUG
901static void print_id(struct usb_device *udev)
902{
903 char buffer[40];
904
905 scnprint_id(udev, buffer, sizeof(buffer));
906 buffer[sizeof(buffer)-1] = 0;
907 dev_dbg_f(&udev->dev, "%s\n", buffer);
908}
909#else
910#define print_id(udev) do { } while (0)
911#endif
912
913static int probe(struct usb_interface *intf, const struct usb_device_id *id)
914{
915 int r;
916 struct usb_device *udev = interface_to_usbdev(intf);
917 struct net_device *netdev = NULL;
918
919 print_id(udev);
920
921 switch (udev->speed) {
922 case USB_SPEED_LOW:
923 case USB_SPEED_FULL:
924 case USB_SPEED_HIGH:
925 break;
926 default:
927 dev_dbg_f(&intf->dev, "Unknown USB speed\n");
928 r = -ENODEV;
929 goto error;
930 }
931
932 netdev = zd_netdev_alloc(intf);
933 if (netdev == NULL) {
934 r = -ENOMEM;
935 goto error;
936 }
937
938 r = upload_firmware(udev, id->driver_info);
939 if (r) {
940 dev_err(&intf->dev,
941 "couldn't load firmware. Error number %d\n", r);
942 goto error;
943 }
944
945 r = usb_reset_configuration(udev);
946 if (r) {
947 dev_dbg_f(&intf->dev,
948 "couldn't reset configuration. Error number %d\n", r);
949 goto error;
950 }
951
952 /* At this point the interrupt endpoint is not generally enabled. We
953 * save the USB bandwidth until the network device is opened. But
954 * notify that the initialization of the MAC will require the
955 * interrupts to be temporary enabled.
956 */
957 r = zd_mac_init_hw(zd_netdev_mac(netdev), id->driver_info);
958 if (r) {
959 dev_dbg_f(&intf->dev,
960 "couldn't initialize mac. Error number %d\n", r);
961 goto error;
962 }
963
964 r = register_netdev(netdev);
965 if (r) {
966 dev_dbg_f(&intf->dev,
967 "couldn't register netdev. Error number %d\n", r);
968 goto error;
969 }
970
971 dev_dbg_f(&intf->dev, "successful\n");
972 dev_info(&intf->dev,"%s\n", netdev->name);
973 return 0;
974error:
975 usb_reset_device(interface_to_usbdev(intf));
976 zd_netdev_free(netdev);
977 return r;
978}
979
980static void disconnect(struct usb_interface *intf)
981{
982 struct net_device *netdev = zd_intf_to_netdev(intf);
983 struct zd_mac *mac = zd_netdev_mac(netdev);
984 struct zd_usb *usb = &mac->chip.usb;
985
986 dev_dbg_f(zd_usb_dev(usb), "\n");
987
988 zd_netdev_disconnect(netdev);
989
990 /* Just in case something has gone wrong! */
991 zd_usb_disable_rx(usb);
992 zd_usb_disable_int(usb);
993
994 /* If the disconnect has been caused by a removal of the
995 * driver module, the reset allows reloading of the driver. If the
996 * reset will not be executed here, the upload of the firmware in the
997 * probe function caused by the reloading of the driver will fail.
998 */
999 usb_reset_device(interface_to_usbdev(intf));
1000
1001 /* If somebody still waits on this lock now, this is an error. */
1002 zd_netdev_free(netdev);
1003 dev_dbg(&intf->dev, "disconnected\n");
1004}
1005
1006static struct usb_driver driver = {
1007 .name = "zd1211rw",
1008 .id_table = usb_ids,
1009 .probe = probe,
1010 .disconnect = disconnect,
1011};
1012
1013static int __init usb_init(void)
1014{
1015 int r;
1016
1017 pr_debug("usb_init()\n");
1018
1019 r = usb_register(&driver);
1020 if (r) {
1021 printk(KERN_ERR "usb_register() failed. Error number %d\n", r);
1022 return r;
1023 }
1024
1025 pr_debug("zd1211rw initialized\n");
1026 return 0;
1027}
1028
1029static void __exit usb_exit(void)
1030{
1031 pr_debug("usb_exit()\n");
1032 usb_deregister(&driver);
1033}
1034
1035module_init(usb_init);
1036module_exit(usb_exit);
1037
1038static int usb_int_regs_length(unsigned int count)
1039{
1040 return sizeof(struct usb_int_regs) + count * sizeof(struct reg_data);
1041}
1042
1043static void prepare_read_regs_int(struct zd_usb *usb)
1044{
1045 struct zd_usb_interrupt *intr = &usb->intr;
1046
1047 spin_lock(&intr->lock);
1048 intr->read_regs_enabled = 1;
1049 INIT_COMPLETION(intr->read_regs.completion);
1050 spin_unlock(&intr->lock);
1051}
1052
1053static int get_results(struct zd_usb *usb, u16 *values,
1054 struct usb_req_read_regs *req, unsigned int count)
1055{
1056 int r;
1057 int i;
1058 struct zd_usb_interrupt *intr = &usb->intr;
1059 struct read_regs_int *rr = &intr->read_regs;
1060 struct usb_int_regs *regs = (struct usb_int_regs *)rr->buffer;
1061
1062 spin_lock(&intr->lock);
1063
1064 r = -EIO;
1065 /* The created block size seems to be larger than expected.
1066 * However results appear to be correct.
1067 */
1068 if (rr->length < usb_int_regs_length(count)) {
1069 dev_dbg_f(zd_usb_dev(usb),
1070 "error: actual length %d less than expected %d\n",
1071 rr->length, usb_int_regs_length(count));
1072 goto error_unlock;
1073 }
1074 if (rr->length > sizeof(rr->buffer)) {
1075 dev_dbg_f(zd_usb_dev(usb),
1076 "error: actual length %d exceeds buffer size %zu\n",
1077 rr->length, sizeof(rr->buffer));
1078 goto error_unlock;
1079 }
1080
1081 for (i = 0; i < count; i++) {
1082 struct reg_data *rd = &regs->regs[i];
1083 if (rd->addr != req->addr[i]) {
1084 dev_dbg_f(zd_usb_dev(usb),
1085 "rd[%d] addr %#06hx expected %#06hx\n", i,
1086 le16_to_cpu(rd->addr),
1087 le16_to_cpu(req->addr[i]));
1088 goto error_unlock;
1089 }
1090 values[i] = le16_to_cpu(rd->value);
1091 }
1092
1093 r = 0;
1094error_unlock:
1095 spin_unlock(&intr->lock);
1096 return r;
1097}
1098
1099int zd_usb_ioread16v(struct zd_usb *usb, u16 *values,
1100 const zd_addr_t *addresses, unsigned int count)
1101{
1102 int r;
1103 int i, req_len, actual_req_len;
1104 struct usb_device *udev;
1105 struct usb_req_read_regs *req = NULL;
1106 unsigned long timeout;
1107
1108 if (count < 1) {
1109 dev_dbg_f(zd_usb_dev(usb), "error: count is zero\n");
1110 return -EINVAL;
1111 }
1112 if (count > USB_MAX_IOREAD16_COUNT) {
1113 dev_dbg_f(zd_usb_dev(usb),
1114 "error: count %u exceeds possible max %u\n",
1115 count, USB_MAX_IOREAD16_COUNT);
1116 return -EINVAL;
1117 }
1118 if (in_atomic()) {
1119 dev_dbg_f(zd_usb_dev(usb),
1120 "error: io in atomic context not supported\n");
1121 return -EWOULDBLOCK;
1122 }
1123 if (!usb_int_enabled(usb)) {
1124 dev_dbg_f(zd_usb_dev(usb),
1125 "error: usb interrupt not enabled\n");
1126 return -EWOULDBLOCK;
1127 }
1128
1129 req_len = sizeof(struct usb_req_read_regs) + count * sizeof(__le16);
1130 req = kmalloc(req_len, GFP_NOFS);
1131 if (!req)
1132 return -ENOMEM;
1133 req->id = cpu_to_le16(USB_REQ_READ_REGS);
1134 for (i = 0; i < count; i++)
1135 req->addr[i] = cpu_to_le16(usb_addr(usb, addresses[i]));
1136
1137 udev = zd_usb_to_usbdev(usb);
1138 prepare_read_regs_int(usb);
1139 r = usb_bulk_msg(udev, usb_sndbulkpipe(udev, EP_REGS_OUT),
1140 req, req_len, &actual_req_len, 1000 /* ms */);
1141 if (r) {
1142 dev_dbg_f(zd_usb_dev(usb),
1143 "error in usb_bulk_msg(). Error number %d\n", r);
1144 goto error;
1145 }
1146 if (req_len != actual_req_len) {
1147 dev_dbg_f(zd_usb_dev(usb), "error in usb_bulk_msg()\n"
1148 " req_len %d != actual_req_len %d\n",
1149 req_len, actual_req_len);
1150 r = -EIO;
1151 goto error;
1152 }
1153
1154 timeout = wait_for_completion_timeout(&usb->intr.read_regs.completion,
1155 msecs_to_jiffies(1000));
1156 if (!timeout) {
1157 disable_read_regs_int(usb);
1158 dev_dbg_f(zd_usb_dev(usb), "read timed out\n");
1159 r = -ETIMEDOUT;
1160 goto error;
1161 }
1162
1163 r = get_results(usb, values, req, count);
1164error:
1165 kfree(req);
1166 return r;
1167}
1168
1169int zd_usb_iowrite16v(struct zd_usb *usb, const struct zd_ioreq16 *ioreqs,
1170 unsigned int count)
1171{
1172 int r;
1173 struct usb_device *udev;
1174 struct usb_req_write_regs *req = NULL;
1175 int i, req_len, actual_req_len;
1176
1177 if (count == 0)
1178 return 0;
1179 if (count > USB_MAX_IOWRITE16_COUNT) {
1180 dev_dbg_f(zd_usb_dev(usb),
1181 "error: count %u exceeds possible max %u\n",
1182 count, USB_MAX_IOWRITE16_COUNT);
1183 return -EINVAL;
1184 }
1185 if (in_atomic()) {
1186 dev_dbg_f(zd_usb_dev(usb),
1187 "error: io in atomic context not supported\n");
1188 return -EWOULDBLOCK;
1189 }
1190
1191 req_len = sizeof(struct usb_req_write_regs) +
1192 count * sizeof(struct reg_data);
1193 req = kmalloc(req_len, GFP_NOFS);
1194 if (!req)
1195 return -ENOMEM;
1196
1197 req->id = cpu_to_le16(USB_REQ_WRITE_REGS);
1198 for (i = 0; i < count; i++) {
1199 struct reg_data *rw = &req->reg_writes[i];
1200 rw->addr = cpu_to_le16(usb_addr(usb, ioreqs[i].addr));
1201 rw->value = cpu_to_le16(ioreqs[i].value);
1202 }
1203
1204 udev = zd_usb_to_usbdev(usb);
1205 r = usb_bulk_msg(udev, usb_sndbulkpipe(udev, EP_REGS_OUT),
1206 req, req_len, &actual_req_len, 1000 /* ms */);
1207 if (r) {
1208 dev_dbg_f(zd_usb_dev(usb),
1209 "error in usb_bulk_msg(). Error number %d\n", r);
1210 goto error;
1211 }
1212 if (req_len != actual_req_len) {
1213 dev_dbg_f(zd_usb_dev(usb),
1214 "error in usb_bulk_msg()"
1215 " req_len %d != actual_req_len %d\n",
1216 req_len, actual_req_len);
1217 r = -EIO;
1218 goto error;
1219 }
1220
1221 /* FALL-THROUGH with r == 0 */
1222error:
1223 kfree(req);
1224 return r;
1225}
1226
1227int zd_usb_rfwrite(struct zd_usb *usb, u32 value, u8 bits)
1228{
1229 int r;
1230 struct usb_device *udev;
1231 struct usb_req_rfwrite *req = NULL;
1232 int i, req_len, actual_req_len;
1233 u16 bit_value_template;
1234
1235 if (in_atomic()) {
1236 dev_dbg_f(zd_usb_dev(usb),
1237 "error: io in atomic context not supported\n");
1238 return -EWOULDBLOCK;
1239 }
1240 if (bits < USB_MIN_RFWRITE_BIT_COUNT) {
1241 dev_dbg_f(zd_usb_dev(usb),
1242 "error: bits %d are smaller than"
1243 " USB_MIN_RFWRITE_BIT_COUNT %d\n",
1244 bits, USB_MIN_RFWRITE_BIT_COUNT);
1245 return -EINVAL;
1246 }
1247 if (bits > USB_MAX_RFWRITE_BIT_COUNT) {
1248 dev_dbg_f(zd_usb_dev(usb),
1249 "error: bits %d exceed USB_MAX_RFWRITE_BIT_COUNT %d\n",
1250 bits, USB_MAX_RFWRITE_BIT_COUNT);
1251 return -EINVAL;
1252 }
1253#ifdef DEBUG
1254 if (value & (~0UL << bits)) {
1255 dev_dbg_f(zd_usb_dev(usb),
1256 "error: value %#09x has bits >= %d set\n",
1257 value, bits);
1258 return -EINVAL;
1259 }
1260#endif /* DEBUG */
1261
1262 dev_dbg_f(zd_usb_dev(usb), "value %#09x bits %d\n", value, bits);
1263
1264 r = zd_usb_ioread16(usb, &bit_value_template, CR203);
1265 if (r) {
1266 dev_dbg_f(zd_usb_dev(usb),
1267 "error %d: Couldn't read CR203\n", r);
1268 goto out;
1269 }
1270 bit_value_template &= ~(RF_IF_LE|RF_CLK|RF_DATA);
1271
1272 req_len = sizeof(struct usb_req_rfwrite) + bits * sizeof(__le16);
1273 req = kmalloc(req_len, GFP_NOFS);
1274 if (!req)
1275 return -ENOMEM;
1276
1277 req->id = cpu_to_le16(USB_REQ_WRITE_RF);
1278 /* 1: 3683a, but not used in ZYDAS driver */
1279 req->value = cpu_to_le16(2);
1280 req->bits = cpu_to_le16(bits);
1281
1282 for (i = 0; i < bits; i++) {
1283 u16 bv = bit_value_template;
1284 if (value & (1 << (bits-1-i)))
1285 bv |= RF_DATA;
1286 req->bit_values[i] = cpu_to_le16(bv);
1287 }
1288
1289 udev = zd_usb_to_usbdev(usb);
1290 r = usb_bulk_msg(udev, usb_sndbulkpipe(udev, EP_REGS_OUT),
1291 req, req_len, &actual_req_len, 1000 /* ms */);
1292 if (r) {
1293 dev_dbg_f(zd_usb_dev(usb),
1294 "error in usb_bulk_msg(). Error number %d\n", r);
1295 goto out;
1296 }
1297 if (req_len != actual_req_len) {
1298 dev_dbg_f(zd_usb_dev(usb), "error in usb_bulk_msg()"
1299 " req_len %d != actual_req_len %d\n",
1300 req_len, actual_req_len);
1301 r = -EIO;
1302 goto out;
1303 }
1304
1305 /* FALL-THROUGH with r == 0 */
1306out:
1307 kfree(req);
1308 return r;
1309}
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.h b/drivers/net/wireless/zd1211rw/zd_usb.h
new file mode 100644
index 000000000000..d6420283bd5a
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_usb.h
@@ -0,0 +1,240 @@
1/* zd_usb.h: Header for USB interface implemented by ZD1211 chip
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_USB_H
19#define _ZD_USB_H
20
21#include <linux/completion.h>
22#include <linux/netdevice.h>
23#include <linux/spinlock.h>
24#include <linux/skbuff.h>
25#include <linux/usb.h>
26
27#include "zd_def.h"
28#include "zd_types.h"
29
30enum devicetype {
31 DEVICE_ZD1211 = 0,
32 DEVICE_ZD1211B = 1,
33};
34
35enum endpoints {
36 EP_CTRL = 0,
37 EP_DATA_OUT = 1,
38 EP_DATA_IN = 2,
39 EP_INT_IN = 3,
40 EP_REGS_OUT = 4,
41};
42
43enum {
44 USB_MAX_TRANSFER_SIZE = 4096, /* bytes */
45 /* FIXME: The original driver uses this value. We have to check,
46 * whether the MAX_TRANSFER_SIZE is sufficient and this needs only be
47 * used if one combined frame is split over two USB transactions.
48 */
49 USB_MAX_RX_SIZE = 4800, /* bytes */
50 USB_MAX_IOWRITE16_COUNT = 15,
51 USB_MAX_IOWRITE32_COUNT = USB_MAX_IOWRITE16_COUNT/2,
52 USB_MAX_IOREAD16_COUNT = 15,
53 USB_MAX_IOREAD32_COUNT = USB_MAX_IOREAD16_COUNT/2,
54 USB_MIN_RFWRITE_BIT_COUNT = 16,
55 USB_MAX_RFWRITE_BIT_COUNT = 28,
56 USB_MAX_EP_INT_BUFFER = 64,
57 USB_ZD1211B_BCD_DEVICE = 0x4810,
58};
59
60enum control_requests {
61 USB_REQ_WRITE_REGS = 0x21,
62 USB_REQ_READ_REGS = 0x22,
63 USB_REQ_WRITE_RF = 0x23,
64 USB_REQ_PROG_FLASH = 0x24,
65 USB_REQ_EEPROM_START = 0x0128, /* ? request is a byte */
66 USB_REQ_EEPROM_MID = 0x28,
67 USB_REQ_EEPROM_END = 0x0228, /* ? request is a byte */
68 USB_REQ_FIRMWARE_DOWNLOAD = 0x30,
69 USB_REQ_FIRMWARE_CONFIRM = 0x31,
70 USB_REQ_FIRMWARE_READ_DATA = 0x32,
71};
72
73struct usb_req_read_regs {
74 __le16 id;
75 __le16 addr[0];
76} __attribute__((packed));
77
78struct reg_data {
79 __le16 addr;
80 __le16 value;
81} __attribute__((packed));
82
83struct usb_req_write_regs {
84 __le16 id;
85 struct reg_data reg_writes[0];
86} __attribute__((packed));
87
88enum {
89 RF_IF_LE = 0x02,
90 RF_CLK = 0x04,
91 RF_DATA = 0x08,
92};
93
94struct usb_req_rfwrite {
95 __le16 id;
96 __le16 value;
97 /* 1: 3683a */
98 /* 2: other (default) */
99 __le16 bits;
100 /* RF2595: 24 */
101 __le16 bit_values[0];
102 /* (CR203 & ~(RF_IF_LE | RF_CLK | RF_DATA)) | (bit ? RF_DATA : 0) */
103} __attribute__((packed));
104
105/* USB interrupt */
106
107enum usb_int_id {
108 USB_INT_TYPE = 0x01,
109 USB_INT_ID_REGS = 0x90,
110 USB_INT_ID_RETRY_FAILED = 0xa0,
111};
112
113enum usb_int_flags {
114 USB_INT_READ_REGS_EN = 0x01,
115};
116
117struct usb_int_header {
118 u8 type; /* must always be 1 */
119 u8 id;
120} __attribute__((packed));
121
122struct usb_int_regs {
123 struct usb_int_header hdr;
124 struct reg_data regs[0];
125} __attribute__((packed));
126
127struct usb_int_retry_fail {
128 struct usb_int_header hdr;
129 u8 new_rate;
130 u8 _dummy;
131 u8 addr[ETH_ALEN];
132 u8 ibss_wakeup_dest;
133} __attribute__((packed));
134
135struct read_regs_int {
136 struct completion completion;
137 /* Stores the USB int structure and contains the USB address of the
138 * first requested register before request.
139 */
140 u8 buffer[USB_MAX_EP_INT_BUFFER];
141 int length;
142 __le16 cr_int_addr;
143};
144
145struct zd_ioreq16 {
146 zd_addr_t addr;
147 u16 value;
148};
149
150struct zd_ioreq32 {
151 zd_addr_t addr;
152 u32 value;
153};
154
155struct zd_usb_interrupt {
156 struct read_regs_int read_regs;
157 spinlock_t lock;
158 struct urb *urb;
159 int interval;
160 u8 read_regs_enabled:1;
161};
162
163static inline struct usb_int_regs *get_read_regs(struct zd_usb_interrupt *intr)
164{
165 return (struct usb_int_regs *)intr->read_regs.buffer;
166}
167
168#define URBS_COUNT 5
169
170struct zd_usb_rx {
171 spinlock_t lock;
172 u8 fragment[2*USB_MAX_RX_SIZE];
173 unsigned int fragment_length;
174 unsigned int usb_packet_size;
175 struct urb **urbs;
176 int urbs_count;
177};
178
179struct zd_usb_tx {
180 spinlock_t lock;
181};
182
183/* Contains the usb parts. The structure doesn't require a lock, because intf
184 * and fw_base_offset, will not be changed after initialization.
185 */
186struct zd_usb {
187 struct zd_usb_interrupt intr;
188 struct zd_usb_rx rx;
189 struct zd_usb_tx tx;
190 struct usb_interface *intf;
191 u16 fw_base_offset;
192};
193
194#define zd_usb_dev(usb) (&usb->intf->dev)
195
196static inline struct usb_device *zd_usb_to_usbdev(struct zd_usb *usb)
197{
198 return interface_to_usbdev(usb->intf);
199}
200
201static inline struct net_device *zd_intf_to_netdev(struct usb_interface *intf)
202{
203 return usb_get_intfdata(intf);
204}
205
206static inline struct net_device *zd_usb_to_netdev(struct zd_usb *usb)
207{
208 return zd_intf_to_netdev(usb->intf);
209}
210
211void zd_usb_init(struct zd_usb *usb, struct net_device *netdev,
212 struct usb_interface *intf);
213int zd_usb_init_hw(struct zd_usb *usb);
214void zd_usb_clear(struct zd_usb *usb);
215
216int zd_usb_scnprint_id(struct zd_usb *usb, char *buffer, size_t size);
217
218int zd_usb_enable_int(struct zd_usb *usb);
219void zd_usb_disable_int(struct zd_usb *usb);
220
221int zd_usb_enable_rx(struct zd_usb *usb);
222void zd_usb_disable_rx(struct zd_usb *usb);
223
224int zd_usb_tx(struct zd_usb *usb, const u8 *frame, unsigned int length);
225
226int zd_usb_ioread16v(struct zd_usb *usb, u16 *values,
227 const zd_addr_t *addresses, unsigned int count);
228
229static inline int zd_usb_ioread16(struct zd_usb *usb, u16 *value,
230 const zd_addr_t addr)
231{
232 return zd_usb_ioread16v(usb, value, (const zd_addr_t *)&addr, 1);
233}
234
235int zd_usb_iowrite16v(struct zd_usb *usb, const struct zd_ioreq16 *ioreqs,
236 unsigned int count);
237
238int zd_usb_rfwrite(struct zd_usb *usb, u32 value, u8 bits);
239
240#endif /* _ZD_USB_H */
diff --git a/drivers/net/wireless/zd1211rw/zd_util.c b/drivers/net/wireless/zd1211rw/zd_util.c
new file mode 100644
index 000000000000..d20036c15d11
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_util.c
@@ -0,0 +1,82 @@
1/* zd_util.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 *
17 * Utility program
18 */
19
20#include "zd_def.h"
21#include "zd_util.h"
22
23#ifdef DEBUG
24static char hex(u8 v)
25{
26 v &= 0xf;
27 return (v < 10 ? '0' : 'a' - 10) + v;
28}
29
30static char hex_print(u8 c)
31{
32 return (0x20 <= c && c < 0x7f) ? c : '.';
33}
34
35static void dump_line(const u8 *bytes, size_t size)
36{
37 char c;
38 size_t i;
39
40 size = size <= 8 ? size : 8;
41 printk(KERN_DEBUG "zd1211 %p ", bytes);
42 for (i = 0; i < 8; i++) {
43 switch (i) {
44 case 1:
45 case 5:
46 c = '.';
47 break;
48 case 3:
49 c = ':';
50 break;
51 default:
52 c = ' ';
53 }
54 if (i < size) {
55 printk("%c%c%c", hex(bytes[i] >> 4), hex(bytes[i]), c);
56 } else {
57 printk(" %c", c);
58 }
59 }
60
61 for (i = 0; i < size; i++)
62 printk("%c", hex_print(bytes[i]));
63 printk("\n");
64}
65
66void zd_hexdump(const void *bytes, size_t size)
67{
68 size_t i = 0;
69
70 do {
71 dump_line((u8 *)bytes + i, size-i);
72 i += 8;
73 } while (i < size);
74}
75#endif /* DEBUG */
76
77void *zd_tail(const void *buffer, size_t buffer_size, size_t tail_size)
78{
79 if (buffer_size < tail_size)
80 return NULL;
81 return (u8 *)buffer + (buffer_size - tail_size);
82}
diff --git a/drivers/net/wireless/zd1211rw/zd_util.h b/drivers/net/wireless/zd1211rw/zd_util.h
new file mode 100644
index 000000000000..ce26f7adea92
--- /dev/null
+++ b/drivers/net/wireless/zd1211rw/zd_util.h
@@ -0,0 +1,29 @@
1/* zd_util.h
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef _ZD_UTIL_H
19#define _ZD_UTIL_H
20
21void *zd_tail(const void *buffer, size_t buffer_size, size_t tail_size);
22
23#ifdef DEBUG
24void zd_hexdump(const void *bytes, size_t size);
25#else
26#define zd_hexdump(bytes, size)
27#endif /* DEBUG */
28
29#endif /* _ZD_UTIL_H */
diff --git a/drivers/net/yellowfin.c b/drivers/net/yellowfin.c
index bbbf7e274a2a..8459a18254a4 100644
--- a/drivers/net/yellowfin.c
+++ b/drivers/net/yellowfin.c
@@ -19,37 +19,13 @@
19 19
20 Support and updates available at 20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html 21 http://www.scyld.com/network/yellowfin.html
22 [link no longer provides useful info -jgarzik]
22 23
23
24 Linux kernel changelog:
25 -----------------------
26
27 LK1.1.1 (jgarzik): Port to 2.4 kernel
28
29 LK1.1.2 (jgarzik):
30 * Merge in becker version 1.05
31
32 LK1.1.3 (jgarzik):
33 * Various cleanups
34 * Update yellowfin_timer to correctly calculate duplex.
35 (suggested by Manfred Spraul)
36
37 LK1.1.4 (val@nmt.edu):
38 * Fix three endian-ness bugs
39 * Support dual function SYM53C885E ethernet chip
40
41 LK1.1.5 (val@nmt.edu):
42 * Fix forced full-duplex bug I introduced
43
44 LK1.1.6 (val@nmt.edu):
45 * Only print warning on truly "oversized" packets
46 * Fix theoretical bug on gigabit cards - return to 1.1.3 behavior
47
48*/ 24*/
49 25
50#define DRV_NAME "yellowfin" 26#define DRV_NAME "yellowfin"
51#define DRV_VERSION "1.05+LK1.1.6" 27#define DRV_VERSION "2.0"
52#define DRV_RELDATE "Feb 11, 2002" 28#define DRV_RELDATE "Jun 27, 2006"
53 29
54#define PFX DRV_NAME ": " 30#define PFX DRV_NAME ": "
55 31
@@ -239,8 +215,11 @@ enum capability_flags {
239 HasMACAddrBug=32, /* Only on early revs. */ 215 HasMACAddrBug=32, /* Only on early revs. */
240 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */ 216 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
241}; 217};
218
242/* The PCI I/O space extent. */ 219/* The PCI I/O space extent. */
243#define YELLOWFIN_SIZE 0x100 220enum {
221 YELLOWFIN_SIZE = 0x100,
222};
244 223
245struct pci_id_info { 224struct pci_id_info {
246 const char *name; 225 const char *name;
@@ -248,16 +227,14 @@ struct pci_id_info {
248 int pci, pci_mask, subsystem, subsystem_mask; 227 int pci, pci_mask, subsystem, subsystem_mask;
249 int revision, revision_mask; /* Only 8 bits. */ 228 int revision, revision_mask; /* Only 8 bits. */
250 } id; 229 } id;
251 int io_size; /* Needed for I/O region check or ioremap(). */
252 int drv_flags; /* Driver use, intended as capability flags. */ 230 int drv_flags; /* Driver use, intended as capability flags. */
253}; 231};
254 232
255static const struct pci_id_info pci_id_tbl[] = { 233static const struct pci_id_info pci_id_tbl[] = {
256 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff}, 234 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
257 YELLOWFIN_SIZE,
258 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom}, 235 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
259 {"Symbios SYM83C885", { 0x07011000, 0xffffffff}, 236 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
260 YELLOWFIN_SIZE, HasMII | DontUseEeprom }, 237 HasMII | DontUseEeprom },
261 { } 238 { }
262}; 239};
263 240