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-rw-r--r--drivers/net/bnx2.c61
1 files changed, 37 insertions, 24 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index baad015b3d6d..52fe620e1a4c 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -3247,31 +3247,44 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3247 * before we issue a reset. */ 3247 * before we issue a reset. */
3248 val = REG_RD(bp, BNX2_MISC_ID); 3248 val = REG_RD(bp, BNX2_MISC_ID);
3249 3249
3250 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3250 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3251 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3251 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3252 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3252 REG_RD(bp, BNX2_MISC_COMMAND);
3253 udelay(5);
3253 3254
3254 /* Chip reset. */ 3255 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3255 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 3256 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3256 3257
3257 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || 3258 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3258 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3259 msleep(15);
3260 3259
3261 /* Reset takes approximate 30 usec */ 3260 } else {
3262 for (i = 0; i < 10; i++) { 3261 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3263 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); 3262 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3264 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3263 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3265 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3264
3266 break; 3265 /* Chip reset. */
3266 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3267
3268 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3269 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3270 current->state = TASK_UNINTERRUPTIBLE;
3271 schedule_timeout(HZ / 50);
3267 } 3272 }
3268 udelay(10);
3269 }
3270 3273
3271 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3274 /* Reset takes approximate 30 usec */
3272 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3275 for (i = 0; i < 10; i++) {
3273 printk(KERN_ERR PFX "Chip reset did not complete\n"); 3276 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3274 return -EBUSY; 3277 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3278 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3279 break;
3280 udelay(10);
3281 }
3282
3283 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3284 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3285 printk(KERN_ERR PFX "Chip reset did not complete\n");
3286 return -EBUSY;
3287 }
3275 } 3288 }
3276 3289
3277 /* Make sure byte swapping is properly configured. */ 3290 /* Make sure byte swapping is properly configured. */
@@ -3976,8 +3989,8 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3976 bp->tx_prod = NEXT_TX_BD(bp->tx_prod); 3989 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
3977 bp->tx_prod_bseq += pkt_size; 3990 bp->tx_prod_bseq += pkt_size;
3978 3991
3979 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod); 3992 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
3980 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); 3993 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
3981 3994
3982 udelay(100); 3995 udelay(100);
3983 3996
@@ -4529,8 +4542,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4529 prod = NEXT_TX_BD(prod); 4542 prod = NEXT_TX_BD(prod);
4530 bp->tx_prod_bseq += skb->len; 4543 bp->tx_prod_bseq += skb->len;
4531 4544
4532 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); 4545 REG_WR16(bp, bp->tx_bidx_addr, prod);
4533 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); 4546 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4534 4547
4535 mmiowb(); 4548 mmiowb();
4536 4549