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-rw-r--r--drivers/net/atlx/Makefile1
-rw-r--r--drivers/net/atlx/atl1.c (renamed from drivers/net/atlx/atl1_main.c)1544
-rw-r--r--drivers/net/atlx/atl1.h603
-rw-r--r--drivers/net/atlx/atl1_ethtool.c505
-rw-r--r--drivers/net/atlx/atl1_hw.c720
-rw-r--r--drivers/net/atlx/atl1_hw.h946
-rw-r--r--drivers/net/atlx/atl1_param.c203
-rw-r--r--drivers/net/atlx/atlx.c433
-rw-r--r--drivers/net/atlx/atlx.h506
9 files changed, 2751 insertions, 2710 deletions
diff --git a/drivers/net/atlx/Makefile b/drivers/net/atlx/Makefile
index a6b707e4e69e..ca45553a040d 100644
--- a/drivers/net/atlx/Makefile
+++ b/drivers/net/atlx/Makefile
@@ -1,2 +1 @@
1obj-$(CONFIG_ATL1) += atl1.o obj-$(CONFIG_ATL1) += atl1.o
2atl1-y += atl1_main.o atl1_hw.o atl1_ethtool.o atl1_param.o
diff --git a/drivers/net/atlx/atl1_main.c b/drivers/net/atlx/atl1.c
index 9200ee59d854..a84c97c75c75 100644
--- a/drivers/net/atlx/atl1_main.c
+++ b/drivers/net/atlx/atl1.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com> 3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com> 4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 * 5 *
6 * Derived from Intel e1000 driver 6 * Derived from Intel e1000 driver
@@ -50,51 +50,46 @@
50 * SMP torture testing 50 * SMP torture testing
51 */ 51 */
52 52
53#include <linux/types.h> 53#include <asm/atomic.h>
54#include <linux/netdevice.h> 54#include <asm/byteorder.h>
55#include <linux/pci.h> 55
56#include <linux/spinlock.h> 56#include <linux/compiler.h>
57#include <linux/slab.h> 57#include <linux/crc32.h>
58#include <linux/string.h> 58#include <linux/delay.h>
59#include <linux/skbuff.h> 59#include <linux/dma-mapping.h>
60#include <linux/etherdevice.h> 60#include <linux/etherdevice.h>
61#include <linux/if_vlan.h>
62#include <linux/if_ether.h>
63#include <linux/irqreturn.h>
64#include <linux/workqueue.h>
65#include <linux/timer.h>
66#include <linux/jiffies.h>
67#include <linux/hardirq.h> 61#include <linux/hardirq.h>
62#include <linux/if_ether.h>
63#include <linux/if_vlan.h>
64#include <linux/in.h>
68#include <linux/interrupt.h> 65#include <linux/interrupt.h>
66#include <linux/ip.h>
69#include <linux/irqflags.h> 67#include <linux/irqflags.h>
70#include <linux/dma-mapping.h> 68#include <linux/irqreturn.h>
69#include <linux/jiffies.h>
70#include <linux/mii.h>
71#include <linux/module.h>
72#include <linux/moduleparam.h>
71#include <linux/net.h> 73#include <linux/net.h>
74#include <linux/netdevice.h>
75#include <linux/pci.h>
76#include <linux/pci_ids.h>
72#include <linux/pm.h> 77#include <linux/pm.h>
73#include <linux/in.h> 78#include <linux/skbuff.h>
74#include <linux/ip.h> 79#include <linux/slab.h>
80#include <linux/spinlock.h>
81#include <linux/string.h>
75#include <linux/tcp.h> 82#include <linux/tcp.h>
76#include <linux/compiler.h> 83#include <linux/timer.h>
77#include <linux/delay.h> 84#include <linux/types.h>
78#include <linux/mii.h> 85#include <linux/workqueue.h>
79#include <net/checksum.h>
80 86
81#include <asm/atomic.h> 87#include <net/checksum.h>
82#include <asm/byteorder.h>
83 88
84#include "atl1.h" 89#include "atl1.h"
85 90
86#define DRIVER_VERSION "2.0.7" 91/* Temporary hack for merging atl1 and atl2 */
87 92#include "atlx.c"
88char atl1_driver_name[] = "atl1";
89static const char atl1_driver_string[] = "Attansic L1 Ethernet Network Driver";
90static const char atl1_copyright[] = "Copyright(c) 2005-2006 Attansic Corporation.";
91char atl1_driver_version[] = DRIVER_VERSION;
92
93MODULE_AUTHOR
94 ("Attansic Corporation <xiong_huang@attansic.com>, Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
95MODULE_DESCRIPTION("Attansic 1000M Ethernet Network Driver");
96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRIVER_VERSION);
98 93
99/* 94/*
100 * atl1_pci_tbl - PCI Device ID Table 95 * atl1_pci_tbl - PCI Device ID Table
@@ -104,7 +99,6 @@ static const struct pci_device_id atl1_pci_tbl[] = {
104 /* required last entry */ 99 /* required last entry */
105 {0,} 100 {0,}
106}; 101};
107
108MODULE_DEVICE_TABLE(pci, atl1_pci_tbl); 102MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
109 103
110/* 104/*
@@ -125,7 +119,7 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
125 119
126 adapter->wol = 0; 120 adapter->wol = 0;
127 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; 121 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
128 adapter->ict = 50000; /* 100ms */ 122 adapter->ict = 50000; /* 100ms */
129 adapter->link_speed = SPEED_0; /* hardware init */ 123 adapter->link_speed = SPEED_0; /* hardware init */
130 adapter->link_duplex = FULL_DUPLEX; 124 adapter->link_duplex = FULL_DUPLEX;
131 125
@@ -206,24 +200,6 @@ static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
206} 200}
207 201
208/* 202/*
209 * atl1_ioctl -
210 * @netdev:
211 * @ifreq:
212 * @cmd:
213 */
214static int atl1_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
215{
216 switch (cmd) {
217 case SIOCGMIIPHY:
218 case SIOCGMIIREG:
219 case SIOCSMIIREG:
220 return atl1_mii_ioctl(netdev, ifr, cmd);
221 default:
222 return -EOPNOTSUPP;
223 }
224}
225
226/*
227 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources 203 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
228 * @adapter: board private structure 204 * @adapter: board private structure
229 * 205 *
@@ -248,7 +224,8 @@ s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
248 rfd_ring->buffer_info = 224 rfd_ring->buffer_info =
249 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count); 225 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
250 226
251 /* real ring DMA buffer 227 /*
228 * real ring DMA buffer
252 * each ring/block may need up to 8 bytes for alignment, hence the 229 * each ring/block may need up to 8 bytes for alignment, hence the
253 * additional 40 bytes tacked onto the end. 230 * additional 40 bytes tacked onto the end.
254 */ 231 */
@@ -307,7 +284,7 @@ s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
307 ((u8 *) adapter->cmb.cmb + 284 ((u8 *) adapter->cmb.cmb +
308 (sizeof(struct coals_msg_block) + offset)); 285 (sizeof(struct coals_msg_block) + offset));
309 286
310 return ATL1_SUCCESS; 287 return 0;
311 288
312err_nomem: 289err_nomem:
313 kfree(tpd_ring->buffer_info); 290 kfree(tpd_ring->buffer_info);
@@ -481,31 +458,6 @@ static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
481 iowrite32(value, hw->hw_addr + REG_MAC_CTRL); 458 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
482} 459}
483 460
484/*
485 * atl1_set_mac - Change the Ethernet Address of the NIC
486 * @netdev: network interface device structure
487 * @p: pointer to an address structure
488 *
489 * Returns 0 on success, negative on failure
490 */
491static int atl1_set_mac(struct net_device *netdev, void *p)
492{
493 struct atl1_adapter *adapter = netdev_priv(netdev);
494 struct sockaddr *addr = p;
495
496 if (netif_running(netdev))
497 return -EBUSY;
498
499 if (!is_valid_ether_addr(addr->sa_data))
500 return -EADDRNOTAVAIL;
501
502 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
503 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
504
505 atl1_set_mac_addr(&adapter->hw);
506 return 0;
507}
508
509static u32 atl1_check_link(struct atl1_adapter *adapter) 461static u32 atl1_check_link(struct atl1_adapter *adapter)
510{ 462{
511 struct atl1_hw *hw = &adapter->hw; 463 struct atl1_hw *hw = &adapter->hw;
@@ -517,14 +469,16 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
517 /* MII_BMSR must read twice */ 469 /* MII_BMSR must read twice */
518 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 470 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
519 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 471 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
520 if (!(phy_data & BMSR_LSTATUS)) { /* link down */ 472 if (!(phy_data & BMSR_LSTATUS)) {
521 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 473 /* link down */
474 if (netif_carrier_ok(netdev)) {
475 /* old link state: Up */
522 dev_info(&adapter->pdev->dev, "link is down\n"); 476 dev_info(&adapter->pdev->dev, "link is down\n");
523 adapter->link_speed = SPEED_0; 477 adapter->link_speed = SPEED_0;
524 netif_carrier_off(netdev); 478 netif_carrier_off(netdev);
525 netif_stop_queue(netdev); 479 netif_stop_queue(netdev);
526 } 480 }
527 return ATL1_SUCCESS; 481 return 0;
528 } 482 }
529 483
530 /* Link Up */ 484 /* Link Up */
@@ -568,14 +522,15 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
568 adapter->link_duplex == FULL_DUPLEX ? 522 adapter->link_duplex == FULL_DUPLEX ?
569 "full duplex" : "half duplex"); 523 "full duplex" : "half duplex");
570 } 524 }
571 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 525 if (!netif_carrier_ok(netdev)) {
526 /* Link down -> Up */
572 netif_carrier_on(netdev); 527 netif_carrier_on(netdev);
573 netif_wake_queue(netdev); 528 netif_wake_queue(netdev);
574 } 529 }
575 return ATL1_SUCCESS; 530 return 0;
576 } 531 }
577 532
578 /* change orignal link status */ 533 /* change original link status */
579 if (netif_carrier_ok(netdev)) { 534 if (netif_carrier_ok(netdev)) {
580 adapter->link_speed = SPEED_0; 535 adapter->link_speed = SPEED_0;
581 netif_carrier_off(netdev); 536 netif_carrier_off(netdev);
@@ -596,12 +551,13 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
596 phy_data = 551 phy_data =
597 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 552 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
598 break; 553 break;
599 default: /* MEDIA_TYPE_10M_HALF: */ 554 default:
555 /* MEDIA_TYPE_10M_HALF: */
600 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 556 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
601 break; 557 break;
602 } 558 }
603 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 559 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
604 return ATL1_SUCCESS; 560 return 0;
605 } 561 }
606 562
607 /* auto-neg, insert timer to re-config phy */ 563 /* auto-neg, insert timer to re-config phy */
@@ -610,71 +566,7 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
610 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ); 566 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
611 } 567 }
612 568
613 return ATL1_SUCCESS; 569 return 0;
614}
615
616static void atl1_check_for_link(struct atl1_adapter *adapter)
617{
618 struct net_device *netdev = adapter->netdev;
619 u16 phy_data = 0;
620
621 spin_lock(&adapter->lock);
622 adapter->phy_timer_pending = false;
623 atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
624 atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
625 spin_unlock(&adapter->lock);
626
627 /* notify upper layer link down ASAP */
628 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
629 if (netif_carrier_ok(netdev)) { /* old link state: Up */
630 dev_info(&adapter->pdev->dev, "%s link is down\n",
631 netdev->name);
632 adapter->link_speed = SPEED_0;
633 netif_carrier_off(netdev);
634 netif_stop_queue(netdev);
635 }
636 }
637 schedule_work(&adapter->link_chg_task);
638}
639
640/*
641 * atl1_set_multi - Multicast and Promiscuous mode set
642 * @netdev: network interface device structure
643 *
644 * The set_multi entry point is called whenever the multicast address
645 * list or the network interface flags are updated. This routine is
646 * responsible for configuring the hardware for proper multicast,
647 * promiscuous mode, and all-multi behavior.
648 */
649static void atl1_set_multi(struct net_device *netdev)
650{
651 struct atl1_adapter *adapter = netdev_priv(netdev);
652 struct atl1_hw *hw = &adapter->hw;
653 struct dev_mc_list *mc_ptr;
654 u32 rctl;
655 u32 hash_value;
656
657 /* Check for Promiscuous and All Multicast modes */
658 rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
659 if (netdev->flags & IFF_PROMISC)
660 rctl |= MAC_CTRL_PROMIS_EN;
661 else if (netdev->flags & IFF_ALLMULTI) {
662 rctl |= MAC_CTRL_MC_ALL_EN;
663 rctl &= ~MAC_CTRL_PROMIS_EN;
664 } else
665 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
666
667 iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
668
669 /* clear the old settings from the multicast hash table */
670 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
671 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
672
673 /* compute mc addresses' hash value ,and put it into hash table */
674 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
675 hash_value = atl1_hash_mc_addr(hw, mc_ptr->dmi_addr);
676 atl1_hash_set(hw, hash_value);
677 }
678} 570}
679 571
680/* 572/*
@@ -974,37 +866,6 @@ static void atl1_via_workaround(struct atl1_adapter *adapter)
974 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); 866 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
975} 867}
976 868
977/*
978 * atl1_irq_enable - Enable default interrupt generation settings
979 * @adapter: board private structure
980 */
981static void atl1_irq_enable(struct atl1_adapter *adapter)
982{
983 iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
984 ioread32(adapter->hw.hw_addr + REG_IMR);
985}
986
987/*
988 * atl1_irq_disable - Mask off interrupt generation on the NIC
989 * @adapter: board private structure
990 */
991static void atl1_irq_disable(struct atl1_adapter *adapter)
992{
993 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
994 ioread32(adapter->hw.hw_addr + REG_IMR);
995 synchronize_irq(adapter->pdev->irq);
996}
997
998static void atl1_clear_phy_int(struct atl1_adapter *adapter)
999{
1000 u16 phy_data;
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&adapter->lock, flags);
1004 atl1_read_phy_reg(&adapter->hw, 19, &phy_data);
1005 spin_unlock_irqrestore(&adapter->lock, flags);
1006}
1007
1008static void atl1_inc_smb(struct atl1_adapter *adapter) 869static void atl1_inc_smb(struct atl1_adapter *adapter)
1009{ 870{
1010 struct stats_msg_block *smb = adapter->smb.smb; 871 struct stats_msg_block *smb = adapter->smb.smb;
@@ -1076,19 +937,6 @@ static void atl1_inc_smb(struct atl1_adapter *adapter)
1076 adapter->soft_stats.tx_carrier_errors; 937 adapter->soft_stats.tx_carrier_errors;
1077} 938}
1078 939
1079/*
1080 * atl1_get_stats - Get System Network Statistics
1081 * @netdev: network interface device structure
1082 *
1083 * Returns the address of the device statistics structure.
1084 * The statistics are actually updated from the timer callback.
1085 */
1086static struct net_device_stats *atl1_get_stats(struct net_device *netdev)
1087{
1088 struct atl1_adapter *adapter = netdev_priv(netdev);
1089 return &adapter->net_stats;
1090}
1091
1092static void atl1_update_mailbox(struct atl1_adapter *adapter) 940static void atl1_update_mailbox(struct atl1_adapter *adapter)
1093{ 941{
1094 unsigned long flags; 942 unsigned long flags;
@@ -1210,7 +1058,8 @@ static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1210 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); 1058 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1211 1059
1212 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN); 1060 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
1213 if (unlikely(!skb)) { /* Better luck next round */ 1061 if (unlikely(!skb)) {
1062 /* Better luck next round */
1214 adapter->net_stats.rx_dropped++; 1063 adapter->net_stats.rx_dropped++;
1215 break; 1064 break;
1216 } 1065 }
@@ -1519,7 +1368,8 @@ static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
1519 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use]; 1368 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
1520 if (unlikely(buffer_info->skb)) 1369 if (unlikely(buffer_info->skb))
1521 BUG(); 1370 BUG();
1522 buffer_info->skb = NULL; /* put skb in last TPD */ 1371 /* put skb in last TPD */
1372 buffer_info->skb = NULL;
1523 1373
1524 if (tcp_seg) { 1374 if (tcp_seg) {
1525 /* TSO/GSO */ 1375 /* TSO/GSO */
@@ -1779,7 +1629,7 @@ static irqreturn_t atl1_intr(int irq, void *data)
1779 adapter->cmb.cmb->int_stats = 0; 1629 adapter->cmb.cmb->int_stats = 0;
1780 1630
1781 if (status & ISR_GPHY) /* clear phy status */ 1631 if (status & ISR_GPHY) /* clear phy status */
1782 atl1_clear_phy_int(adapter); 1632 atlx_clear_phy_int(adapter);
1783 1633
1784 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 1634 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
1785 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); 1635 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
@@ -1866,23 +1716,12 @@ static void atl1_phy_config(unsigned long data)
1866 spin_lock_irqsave(&adapter->lock, flags); 1716 spin_lock_irqsave(&adapter->lock, flags);
1867 adapter->phy_timer_pending = false; 1717 adapter->phy_timer_pending = false;
1868 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1718 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1869 atl1_write_phy_reg(hw, MII_AT001_CR, hw->mii_1000t_ctrl_reg); 1719 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
1870 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); 1720 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
1871 spin_unlock_irqrestore(&adapter->lock, flags); 1721 spin_unlock_irqrestore(&adapter->lock, flags);
1872} 1722}
1873 1723
1874/* 1724/*
1875 * atl1_tx_timeout - Respond to a Tx Hang
1876 * @netdev: network interface device structure
1877 */
1878static void atl1_tx_timeout(struct net_device *netdev)
1879{
1880 struct atl1_adapter *adapter = netdev_priv(netdev);
1881 /* Do the reset outside of interrupt context */
1882 schedule_work(&adapter->tx_timeout_task);
1883}
1884
1885/*
1886 * Orphaned vendor comment left intact here: 1725 * Orphaned vendor comment left intact here:
1887 * <vendor comment> 1726 * <vendor comment>
1888 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT 1727 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
@@ -1904,58 +1743,11 @@ static void atl1_tx_timeout_task(struct work_struct *work)
1904 netif_device_attach(netdev); 1743 netif_device_attach(netdev);
1905} 1744}
1906 1745
1907/*
1908 * atl1_link_chg_task - deal with link change event Out of interrupt context
1909 */
1910static void atl1_link_chg_task(struct work_struct *work)
1911{
1912 struct atl1_adapter *adapter =
1913 container_of(work, struct atl1_adapter, link_chg_task);
1914 unsigned long flags;
1915
1916 spin_lock_irqsave(&adapter->lock, flags);
1917 atl1_check_link(adapter);
1918 spin_unlock_irqrestore(&adapter->lock, flags);
1919}
1920
1921static void atl1_vlan_rx_register(struct net_device *netdev,
1922 struct vlan_group *grp)
1923{
1924 struct atl1_adapter *adapter = netdev_priv(netdev);
1925 unsigned long flags;
1926 u32 ctrl;
1927
1928 spin_lock_irqsave(&adapter->lock, flags);
1929 /* atl1_irq_disable(adapter); */
1930 adapter->vlgrp = grp;
1931
1932 if (grp) {
1933 /* enable VLAN tag insert/strip */
1934 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1935 ctrl |= MAC_CTRL_RMV_VLAN;
1936 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1937 } else {
1938 /* disable VLAN tag insert/strip */
1939 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1940 ctrl &= ~MAC_CTRL_RMV_VLAN;
1941 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1942 }
1943
1944 /* atl1_irq_enable(adapter); */
1945 spin_unlock_irqrestore(&adapter->lock, flags);
1946}
1947
1948static void atl1_restore_vlan(struct atl1_adapter *adapter)
1949{
1950 atl1_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1951}
1952
1953int atl1_reset(struct atl1_adapter *adapter) 1746int atl1_reset(struct atl1_adapter *adapter)
1954{ 1747{
1955 int ret; 1748 int ret;
1956
1957 ret = atl1_reset_hw(&adapter->hw); 1749 ret = atl1_reset_hw(&adapter->hw);
1958 if (ret != ATL1_SUCCESS) 1750 if (ret)
1959 return ret; 1751 return ret;
1960 return atl1_init_hw(&adapter->hw); 1752 return atl1_init_hw(&adapter->hw);
1961} 1753}
@@ -1967,11 +1759,12 @@ s32 atl1_up(struct atl1_adapter *adapter)
1967 int irq_flags = IRQF_SAMPLE_RANDOM; 1759 int irq_flags = IRQF_SAMPLE_RANDOM;
1968 1760
1969 /* hardware has been reset, we need to reload some things */ 1761 /* hardware has been reset, we need to reload some things */
1970 atl1_set_multi(netdev); 1762 atlx_set_multi(netdev);
1971 atl1_init_ring_ptrs(adapter); 1763 atl1_init_ring_ptrs(adapter);
1972 atl1_restore_vlan(adapter); 1764 atlx_restore_vlan(adapter);
1973 err = atl1_alloc_rx_buffers(adapter); 1765 err = atl1_alloc_rx_buffers(adapter);
1974 if (unlikely(!err)) /* no RX BUFFER allocated */ 1766 if (unlikely(!err))
1767 /* no RX BUFFER allocated */
1975 return -ENOMEM; 1768 return -ENOMEM;
1976 1769
1977 if (unlikely(atl1_configure(adapter))) { 1770 if (unlikely(atl1_configure(adapter))) {
@@ -1992,7 +1785,7 @@ s32 atl1_up(struct atl1_adapter *adapter)
1992 goto err_up; 1785 goto err_up;
1993 1786
1994 mod_timer(&adapter->watchdog_timer, jiffies); 1787 mod_timer(&adapter->watchdog_timer, jiffies);
1995 atl1_irq_enable(adapter); 1788 atlx_irq_enable(adapter);
1996 atl1_check_link(adapter); 1789 atl1_check_link(adapter);
1997 return 0; 1790 return 0;
1998 1791
@@ -2011,7 +1804,7 @@ void atl1_down(struct atl1_adapter *adapter)
2011 del_timer_sync(&adapter->phy_config_timer); 1804 del_timer_sync(&adapter->phy_config_timer);
2012 adapter->phy_timer_pending = false; 1805 adapter->phy_timer_pending = false;
2013 1806
2014 atl1_irq_disable(adapter); 1807 atlx_irq_disable(adapter);
2015 free_irq(adapter->pdev->irq, netdev); 1808 free_irq(adapter->pdev->irq, netdev);
2016 pci_disable_msi(adapter->pdev); 1809 pci_disable_msi(adapter->pdev);
2017 atl1_reset_hw(&adapter->hw); 1810 atl1_reset_hw(&adapter->hw);
@@ -2094,7 +1887,7 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2094 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 1887 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2095 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 1888 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2096 if (ctrl & BMSR_LSTATUS) 1889 if (ctrl & BMSR_LSTATUS)
2097 wufc &= ~ATL1_WUFC_LNKC; 1890 wufc &= ~ATLX_WUFC_LNKC;
2098 1891
2099 /* reduce speed to 10/100M */ 1892 /* reduce speed to 10/100M */
2100 if (wufc) { 1893 if (wufc) {
@@ -2102,15 +1895,15 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2102 /* if resume, let driver to re- setup link */ 1895 /* if resume, let driver to re- setup link */
2103 hw->phy_configured = false; 1896 hw->phy_configured = false;
2104 atl1_set_mac_addr(hw); 1897 atl1_set_mac_addr(hw);
2105 atl1_set_multi(netdev); 1898 atlx_set_multi(netdev);
2106 1899
2107 ctrl = 0; 1900 ctrl = 0;
2108 /* turn on magic packet wol */ 1901 /* turn on magic packet wol */
2109 if (wufc & ATL1_WUFC_MAG) 1902 if (wufc & ATLX_WUFC_MAG)
2110 ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN; 1903 ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2111 1904
2112 /* turn on Link change WOL */ 1905 /* turn on Link change WOL */
2113 if (wufc & ATL1_WUFC_LNKC) 1906 if (wufc & ATLX_WUFC_LNKC)
2114 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1907 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2115 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 1908 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2116 1909
@@ -2118,13 +1911,13 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2118 ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL); 1911 ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
2119 ctrl &= ~MAC_CTRL_DBG; 1912 ctrl &= ~MAC_CTRL_DBG;
2120 ctrl &= ~MAC_CTRL_PROMIS_EN; 1913 ctrl &= ~MAC_CTRL_PROMIS_EN;
2121 if (wufc & ATL1_WUFC_MC) 1914 if (wufc & ATLX_WUFC_MC)
2122 ctrl |= MAC_CTRL_MC_ALL_EN; 1915 ctrl |= MAC_CTRL_MC_ALL_EN;
2123 else 1916 else
2124 ctrl &= ~MAC_CTRL_MC_ALL_EN; 1917 ctrl &= ~MAC_CTRL_MC_ALL_EN;
2125 1918
2126 /* turn on broadcast mode if wake on-BC is enabled */ 1919 /* turn on broadcast mode if wake on-BC is enabled */
2127 if (wufc & ATL1_WUFC_BC) 1920 if (wufc & ATLX_WUFC_BC)
2128 ctrl |= MAC_CTRL_BC_EN; 1921 ctrl |= MAC_CTRL_BC_EN;
2129 else 1922 else
2130 ctrl &= ~MAC_CTRL_BC_EN; 1923 ctrl &= ~MAC_CTRL_BC_EN;
@@ -2152,12 +1945,13 @@ static int atl1_resume(struct pci_dev *pdev)
2152{ 1945{
2153 struct net_device *netdev = pci_get_drvdata(pdev); 1946 struct net_device *netdev = pci_get_drvdata(pdev);
2154 struct atl1_adapter *adapter = netdev_priv(netdev); 1947 struct atl1_adapter *adapter = netdev_priv(netdev);
2155 u32 ret_val; 1948 u32 err;
2156 1949
2157 pci_set_power_state(pdev, 0); 1950 pci_set_power_state(pdev, PCI_D0);
2158 pci_restore_state(pdev); 1951 pci_restore_state(pdev);
2159 1952
2160 ret_val = pci_enable_device(pdev); 1953 /* FIXME: check and handle */
1954 err = pci_enable_device(pdev);
2161 pci_enable_wake(pdev, PCI_D3hot, 0); 1955 pci_enable_wake(pdev, PCI_D3hot, 0);
2162 pci_enable_wake(pdev, PCI_D3cold, 0); 1956 pci_enable_wake(pdev, PCI_D3cold, 0);
2163 1957
@@ -2224,14 +2018,16 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
2224 dev_err(&pdev->dev, "no usable DMA configuration\n"); 2018 dev_err(&pdev->dev, "no usable DMA configuration\n");
2225 goto err_dma; 2019 goto err_dma;
2226 } 2020 }
2227 /* Mark all PCI regions associated with PCI device 2021 /*
2022 * Mark all PCI regions associated with PCI device
2228 * pdev as being reserved by owner atl1_driver_name 2023 * pdev as being reserved by owner atl1_driver_name
2229 */ 2024 */
2230 err = pci_request_regions(pdev, atl1_driver_name); 2025 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2231 if (err) 2026 if (err)
2232 goto err_request_regions; 2027 goto err_request_regions;
2233 2028
2234 /* Enables bus-mastering on the device and calls 2029 /*
2030 * Enables bus-mastering on the device and calls
2235 * pcibios_set_master to do the needed arch specific settings 2031 * pcibios_set_master to do the needed arch specific settings
2236 */ 2032 */
2237 pci_set_master(pdev); 2033 pci_set_master(pdev);
@@ -2257,7 +2053,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
2257 /* get device revision number */ 2053 /* get device revision number */
2258 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + 2054 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2259 (REG_MASTER_CTRL + 2)); 2055 (REG_MASTER_CTRL + 2));
2260 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION); 2056 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
2261 2057
2262 /* set default ring resource counts */ 2058 /* set default ring resource counts */
2263 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD; 2059 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
@@ -2272,17 +2068,17 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
2272 netdev->open = &atl1_open; 2068 netdev->open = &atl1_open;
2273 netdev->stop = &atl1_close; 2069 netdev->stop = &atl1_close;
2274 netdev->hard_start_xmit = &atl1_xmit_frame; 2070 netdev->hard_start_xmit = &atl1_xmit_frame;
2275 netdev->get_stats = &atl1_get_stats; 2071 netdev->get_stats = &atlx_get_stats;
2276 netdev->set_multicast_list = &atl1_set_multi; 2072 netdev->set_multicast_list = &atlx_set_multi;
2277 netdev->set_mac_address = &atl1_set_mac; 2073 netdev->set_mac_address = &atl1_set_mac;
2278 netdev->change_mtu = &atl1_change_mtu; 2074 netdev->change_mtu = &atl1_change_mtu;
2279 netdev->do_ioctl = &atl1_ioctl; 2075 netdev->do_ioctl = &atlx_ioctl;
2280 netdev->tx_timeout = &atl1_tx_timeout; 2076 netdev->tx_timeout = &atlx_tx_timeout;
2281 netdev->watchdog_timeo = 5 * HZ; 2077 netdev->watchdog_timeo = 5 * HZ;
2282#ifdef CONFIG_NET_POLL_CONTROLLER 2078#ifdef CONFIG_NET_POLL_CONTROLLER
2283 netdev->poll_controller = atl1_poll_controller; 2079 netdev->poll_controller = atl1_poll_controller;
2284#endif 2080#endif
2285 netdev->vlan_rx_register = atl1_vlan_rx_register; 2081 netdev->vlan_rx_register = atlx_vlan_rx_register;
2286 2082
2287 netdev->ethtool_ops = &atl1_ethtool_ops; 2083 netdev->ethtool_ops = &atl1_ethtool_ops;
2288 adapter->bd_number = cards_found; 2084 adapter->bd_number = cards_found;
@@ -2312,7 +2108,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
2312 /* atl1_pcie_patch(adapter); */ 2108 /* atl1_pcie_patch(adapter); */
2313 2109
2314 /* really reset GPHY core */ 2110 /* really reset GPHY core */
2315 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE); 2111 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
2316 2112
2317 /* 2113 /*
2318 * reset the controller to 2114 * reset the controller to
@@ -2357,7 +2153,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
2357 2153
2358 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task); 2154 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
2359 2155
2360 INIT_WORK(&adapter->link_chg_task, atl1_link_chg_task); 2156 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
2361 2157
2362 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task); 2158 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
2363 2159
@@ -2400,7 +2196,8 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
2400 2196
2401 adapter = netdev_priv(netdev); 2197 adapter = netdev_priv(netdev);
2402 2198
2403 /* Some atl1 boards lack persistent storage for their MAC, and get it 2199 /*
2200 * Some atl1 boards lack persistent storage for their MAC, and get it
2404 * from the BIOS during POST. If we've been messing with the MAC 2201 * from the BIOS during POST. If we've been messing with the MAC
2405 * address, we need to save the permanent one. 2202 * address, we need to save the permanent one.
2406 */ 2203 */
@@ -2410,7 +2207,7 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
2410 atl1_set_mac_addr(&adapter->hw); 2207 atl1_set_mac_addr(&adapter->hw);
2411 } 2208 }
2412 2209
2413 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE); 2210 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
2414 unregister_netdev(netdev); 2211 unregister_netdev(netdev);
2415 pci_iounmap(pdev, adapter->hw.hw_addr); 2212 pci_iounmap(pdev, adapter->hw.hw_addr);
2416 pci_release_regions(pdev); 2213 pci_release_regions(pdev);
@@ -2419,7 +2216,7 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
2419} 2216}
2420 2217
2421static struct pci_driver atl1_driver = { 2218static struct pci_driver atl1_driver = {
2422 .name = atl1_driver_name, 2219 .name = ATLX_DRIVER_NAME,
2423 .id_table = atl1_pci_tbl, 2220 .id_table = atl1_pci_tbl,
2424 .probe = atl1_probe, 2221 .probe = atl1_probe,
2425 .remove = __devexit_p(atl1_remove), 2222 .remove = __devexit_p(atl1_remove),
@@ -2451,3 +2248,1170 @@ static int __init atl1_init_module(void)
2451 2248
2452module_init(atl1_init_module); 2249module_init(atl1_init_module);
2453module_exit(atl1_exit_module); 2250module_exit(atl1_exit_module);
2251
2252struct atl1_stats {
2253 char stat_string[ETH_GSTRING_LEN];
2254 int sizeof_stat;
2255 int stat_offset;
2256};
2257
2258#define ATL1_STAT(m) \
2259 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
2260
2261static struct atl1_stats atl1_gstrings_stats[] = {
2262 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
2263 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
2264 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
2265 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
2266 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
2267 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
2268 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
2269 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
2270 {"multicast", ATL1_STAT(soft_stats.multicast)},
2271 {"collisions", ATL1_STAT(soft_stats.collisions)},
2272 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
2273 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
2274 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
2275 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
2276 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
2277 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
2278 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
2279 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
2280 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
2281 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
2282 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
2283 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
2284 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
2285 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
2286 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
2287 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
2288 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
2289 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
2290 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
2291 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
2292 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
2293};
2294
2295static void atl1_get_ethtool_stats(struct net_device *netdev,
2296 struct ethtool_stats *stats, u64 *data)
2297{
2298 struct atl1_adapter *adapter = netdev_priv(netdev);
2299 int i;
2300 char *p;
2301
2302 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
2303 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
2304 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
2305 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2306 }
2307
2308}
2309
2310static int atl1_get_sset_count(struct net_device *netdev, int sset)
2311{
2312 switch (sset) {
2313 case ETH_SS_STATS:
2314 return ARRAY_SIZE(atl1_gstrings_stats);
2315 default:
2316 return -EOPNOTSUPP;
2317 }
2318}
2319
2320static int atl1_get_settings(struct net_device *netdev,
2321 struct ethtool_cmd *ecmd)
2322{
2323 struct atl1_adapter *adapter = netdev_priv(netdev);
2324 struct atl1_hw *hw = &adapter->hw;
2325
2326 ecmd->supported = (SUPPORTED_10baseT_Half |
2327 SUPPORTED_10baseT_Full |
2328 SUPPORTED_100baseT_Half |
2329 SUPPORTED_100baseT_Full |
2330 SUPPORTED_1000baseT_Full |
2331 SUPPORTED_Autoneg | SUPPORTED_TP);
2332 ecmd->advertising = ADVERTISED_TP;
2333 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
2334 hw->media_type == MEDIA_TYPE_1000M_FULL) {
2335 ecmd->advertising |= ADVERTISED_Autoneg;
2336 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
2337 ecmd->advertising |= ADVERTISED_Autoneg;
2338 ecmd->advertising |=
2339 (ADVERTISED_10baseT_Half |
2340 ADVERTISED_10baseT_Full |
2341 ADVERTISED_100baseT_Half |
2342 ADVERTISED_100baseT_Full |
2343 ADVERTISED_1000baseT_Full);
2344 } else
2345 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
2346 }
2347 ecmd->port = PORT_TP;
2348 ecmd->phy_address = 0;
2349 ecmd->transceiver = XCVR_INTERNAL;
2350
2351 if (netif_carrier_ok(adapter->netdev)) {
2352 u16 link_speed, link_duplex;
2353 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
2354 ecmd->speed = link_speed;
2355 if (link_duplex == FULL_DUPLEX)
2356 ecmd->duplex = DUPLEX_FULL;
2357 else
2358 ecmd->duplex = DUPLEX_HALF;
2359 } else {
2360 ecmd->speed = -1;
2361 ecmd->duplex = -1;
2362 }
2363 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
2364 hw->media_type == MEDIA_TYPE_1000M_FULL)
2365 ecmd->autoneg = AUTONEG_ENABLE;
2366 else
2367 ecmd->autoneg = AUTONEG_DISABLE;
2368
2369 return 0;
2370}
2371
2372static int atl1_set_settings(struct net_device *netdev,
2373 struct ethtool_cmd *ecmd)
2374{
2375 struct atl1_adapter *adapter = netdev_priv(netdev);
2376 struct atl1_hw *hw = &adapter->hw;
2377 u16 phy_data;
2378 int ret_val = 0;
2379 u16 old_media_type = hw->media_type;
2380
2381 if (netif_running(adapter->netdev)) {
2382 dev_dbg(&adapter->pdev->dev, "ethtool shutting down adapter\n");
2383 atl1_down(adapter);
2384 }
2385
2386 if (ecmd->autoneg == AUTONEG_ENABLE)
2387 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
2388 else {
2389 if (ecmd->speed == SPEED_1000) {
2390 if (ecmd->duplex != DUPLEX_FULL) {
2391 dev_warn(&adapter->pdev->dev,
2392 "can't force to 1000M half duplex\n");
2393 ret_val = -EINVAL;
2394 goto exit_sset;
2395 }
2396 hw->media_type = MEDIA_TYPE_1000M_FULL;
2397 } else if (ecmd->speed == SPEED_100) {
2398 if (ecmd->duplex == DUPLEX_FULL)
2399 hw->media_type = MEDIA_TYPE_100M_FULL;
2400 else
2401 hw->media_type = MEDIA_TYPE_100M_HALF;
2402 } else {
2403 if (ecmd->duplex == DUPLEX_FULL)
2404 hw->media_type = MEDIA_TYPE_10M_FULL;
2405 else
2406 hw->media_type = MEDIA_TYPE_10M_HALF;
2407 }
2408 }
2409 switch (hw->media_type) {
2410 case MEDIA_TYPE_AUTO_SENSOR:
2411 ecmd->advertising =
2412 ADVERTISED_10baseT_Half |
2413 ADVERTISED_10baseT_Full |
2414 ADVERTISED_100baseT_Half |
2415 ADVERTISED_100baseT_Full |
2416 ADVERTISED_1000baseT_Full |
2417 ADVERTISED_Autoneg | ADVERTISED_TP;
2418 break;
2419 case MEDIA_TYPE_1000M_FULL:
2420 ecmd->advertising =
2421 ADVERTISED_1000baseT_Full |
2422 ADVERTISED_Autoneg | ADVERTISED_TP;
2423 break;
2424 default:
2425 ecmd->advertising = 0;
2426 break;
2427 }
2428 if (atl1_phy_setup_autoneg_adv(hw)) {
2429 ret_val = -EINVAL;
2430 dev_warn(&adapter->pdev->dev,
2431 "invalid ethtool speed/duplex setting\n");
2432 goto exit_sset;
2433 }
2434 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
2435 hw->media_type == MEDIA_TYPE_1000M_FULL)
2436 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
2437 else {
2438 switch (hw->media_type) {
2439 case MEDIA_TYPE_100M_FULL:
2440 phy_data =
2441 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
2442 MII_CR_RESET;
2443 break;
2444 case MEDIA_TYPE_100M_HALF:
2445 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
2446 break;
2447 case MEDIA_TYPE_10M_FULL:
2448 phy_data =
2449 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
2450 break;
2451 default:
2452 /* MEDIA_TYPE_10M_HALF: */
2453 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
2454 break;
2455 }
2456 }
2457 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
2458exit_sset:
2459 if (ret_val)
2460 hw->media_type = old_media_type;
2461
2462 if (netif_running(adapter->netdev)) {
2463 dev_dbg(&adapter->pdev->dev, "ethtool starting adapter\n");
2464 atl1_up(adapter);
2465 } else if (!ret_val) {
2466 dev_dbg(&adapter->pdev->dev, "ethtool resetting adapter\n");
2467 atl1_reset(adapter);
2468 }
2469 return ret_val;
2470}
2471
2472static void atl1_get_drvinfo(struct net_device *netdev,
2473 struct ethtool_drvinfo *drvinfo)
2474{
2475 struct atl1_adapter *adapter = netdev_priv(netdev);
2476
2477 strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
2478 strncpy(drvinfo->version, ATLX_DRIVER_VERSION,
2479 sizeof(drvinfo->version));
2480 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2481 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
2482 sizeof(drvinfo->bus_info));
2483 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
2484}
2485
2486static void atl1_get_wol(struct net_device *netdev,
2487 struct ethtool_wolinfo *wol)
2488{
2489 struct atl1_adapter *adapter = netdev_priv(netdev);
2490
2491 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
2492 wol->wolopts = 0;
2493 if (adapter->wol & ATLX_WUFC_EX)
2494 wol->wolopts |= WAKE_UCAST;
2495 if (adapter->wol & ATLX_WUFC_MC)
2496 wol->wolopts |= WAKE_MCAST;
2497 if (adapter->wol & ATLX_WUFC_BC)
2498 wol->wolopts |= WAKE_BCAST;
2499 if (adapter->wol & ATLX_WUFC_MAG)
2500 wol->wolopts |= WAKE_MAGIC;
2501 return;
2502}
2503
2504static int atl1_set_wol(struct net_device *netdev,
2505 struct ethtool_wolinfo *wol)
2506{
2507 struct atl1_adapter *adapter = netdev_priv(netdev);
2508
2509 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2510 return -EOPNOTSUPP;
2511 adapter->wol = 0;
2512 if (wol->wolopts & WAKE_UCAST)
2513 adapter->wol |= ATLX_WUFC_EX;
2514 if (wol->wolopts & WAKE_MCAST)
2515 adapter->wol |= ATLX_WUFC_MC;
2516 if (wol->wolopts & WAKE_BCAST)
2517 adapter->wol |= ATLX_WUFC_BC;
2518 if (wol->wolopts & WAKE_MAGIC)
2519 adapter->wol |= ATLX_WUFC_MAG;
2520 return 0;
2521}
2522
2523static void atl1_get_ringparam(struct net_device *netdev,
2524 struct ethtool_ringparam *ring)
2525{
2526 struct atl1_adapter *adapter = netdev_priv(netdev);
2527 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
2528 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
2529
2530 ring->rx_max_pending = ATL1_MAX_RFD;
2531 ring->tx_max_pending = ATL1_MAX_TPD;
2532 ring->rx_mini_max_pending = 0;
2533 ring->rx_jumbo_max_pending = 0;
2534 ring->rx_pending = rxdr->count;
2535 ring->tx_pending = txdr->count;
2536 ring->rx_mini_pending = 0;
2537 ring->rx_jumbo_pending = 0;
2538}
2539
2540static int atl1_set_ringparam(struct net_device *netdev,
2541 struct ethtool_ringparam *ring)
2542{
2543 struct atl1_adapter *adapter = netdev_priv(netdev);
2544 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
2545 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
2546 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
2547
2548 struct atl1_tpd_ring tpd_old, tpd_new;
2549 struct atl1_rfd_ring rfd_old, rfd_new;
2550 struct atl1_rrd_ring rrd_old, rrd_new;
2551 struct atl1_ring_header rhdr_old, rhdr_new;
2552 int err;
2553
2554 tpd_old = adapter->tpd_ring;
2555 rfd_old = adapter->rfd_ring;
2556 rrd_old = adapter->rrd_ring;
2557 rhdr_old = adapter->ring_header;
2558
2559 if (netif_running(adapter->netdev))
2560 atl1_down(adapter);
2561
2562 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
2563 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
2564 rfdr->count;
2565 rfdr->count = (rfdr->count + 3) & ~3;
2566 rrdr->count = rfdr->count;
2567
2568 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
2569 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
2570 tpdr->count;
2571 tpdr->count = (tpdr->count + 3) & ~3;
2572
2573 if (netif_running(adapter->netdev)) {
2574 /* try to get new resources before deleting old */
2575 err = atl1_setup_ring_resources(adapter);
2576 if (err)
2577 goto err_setup_ring;
2578
2579 /*
2580 * save the new, restore the old in order to free it,
2581 * then restore the new back again
2582 */
2583
2584 rfd_new = adapter->rfd_ring;
2585 rrd_new = adapter->rrd_ring;
2586 tpd_new = adapter->tpd_ring;
2587 rhdr_new = adapter->ring_header;
2588 adapter->rfd_ring = rfd_old;
2589 adapter->rrd_ring = rrd_old;
2590 adapter->tpd_ring = tpd_old;
2591 adapter->ring_header = rhdr_old;
2592 atl1_free_ring_resources(adapter);
2593 adapter->rfd_ring = rfd_new;
2594 adapter->rrd_ring = rrd_new;
2595 adapter->tpd_ring = tpd_new;
2596 adapter->ring_header = rhdr_new;
2597
2598 err = atl1_up(adapter);
2599 if (err)
2600 return err;
2601 }
2602 return 0;
2603
2604err_setup_ring:
2605 adapter->rfd_ring = rfd_old;
2606 adapter->rrd_ring = rrd_old;
2607 adapter->tpd_ring = tpd_old;
2608 adapter->ring_header = rhdr_old;
2609 atl1_up(adapter);
2610 return err;
2611}
2612
2613static void atl1_get_pauseparam(struct net_device *netdev,
2614 struct ethtool_pauseparam *epause)
2615{
2616 struct atl1_adapter *adapter = netdev_priv(netdev);
2617 struct atl1_hw *hw = &adapter->hw;
2618
2619 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
2620 hw->media_type == MEDIA_TYPE_1000M_FULL) {
2621 epause->autoneg = AUTONEG_ENABLE;
2622 } else {
2623 epause->autoneg = AUTONEG_DISABLE;
2624 }
2625 epause->rx_pause = 1;
2626 epause->tx_pause = 1;
2627}
2628
2629static int atl1_set_pauseparam(struct net_device *netdev,
2630 struct ethtool_pauseparam *epause)
2631{
2632 struct atl1_adapter *adapter = netdev_priv(netdev);
2633 struct atl1_hw *hw = &adapter->hw;
2634
2635 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
2636 hw->media_type == MEDIA_TYPE_1000M_FULL) {
2637 epause->autoneg = AUTONEG_ENABLE;
2638 } else {
2639 epause->autoneg = AUTONEG_DISABLE;
2640 }
2641
2642 epause->rx_pause = 1;
2643 epause->tx_pause = 1;
2644
2645 return 0;
2646}
2647
2648/* FIXME: is this right? -- CHS */
2649static u32 atl1_get_rx_csum(struct net_device *netdev)
2650{
2651 return 1;
2652}
2653
2654static void atl1_get_strings(struct net_device *netdev, u32 stringset,
2655 u8 *data)
2656{
2657 u8 *p = data;
2658 int i;
2659
2660 switch (stringset) {
2661 case ETH_SS_STATS:
2662 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
2663 memcpy(p, atl1_gstrings_stats[i].stat_string,
2664 ETH_GSTRING_LEN);
2665 p += ETH_GSTRING_LEN;
2666 }
2667 break;
2668 }
2669}
2670
2671static int atl1_nway_reset(struct net_device *netdev)
2672{
2673 struct atl1_adapter *adapter = netdev_priv(netdev);
2674 struct atl1_hw *hw = &adapter->hw;
2675
2676 if (netif_running(netdev)) {
2677 u16 phy_data;
2678 atl1_down(adapter);
2679
2680 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
2681 hw->media_type == MEDIA_TYPE_1000M_FULL) {
2682 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
2683 } else {
2684 switch (hw->media_type) {
2685 case MEDIA_TYPE_100M_FULL:
2686 phy_data = MII_CR_FULL_DUPLEX |
2687 MII_CR_SPEED_100 | MII_CR_RESET;
2688 break;
2689 case MEDIA_TYPE_100M_HALF:
2690 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
2691 break;
2692 case MEDIA_TYPE_10M_FULL:
2693 phy_data = MII_CR_FULL_DUPLEX |
2694 MII_CR_SPEED_10 | MII_CR_RESET;
2695 break;
2696 default:
2697 /* MEDIA_TYPE_10M_HALF */
2698 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
2699 }
2700 }
2701 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
2702 atl1_up(adapter);
2703 }
2704 return 0;
2705}
2706
2707const struct ethtool_ops atl1_ethtool_ops = {
2708 .get_settings = atl1_get_settings,
2709 .set_settings = atl1_set_settings,
2710 .get_drvinfo = atl1_get_drvinfo,
2711 .get_wol = atl1_get_wol,
2712 .set_wol = atl1_set_wol,
2713 .get_ringparam = atl1_get_ringparam,
2714 .set_ringparam = atl1_set_ringparam,
2715 .get_pauseparam = atl1_get_pauseparam,
2716 .set_pauseparam = atl1_set_pauseparam,
2717 .get_rx_csum = atl1_get_rx_csum,
2718 .set_tx_csum = ethtool_op_set_tx_hw_csum,
2719 .get_link = ethtool_op_get_link,
2720 .set_sg = ethtool_op_set_sg,
2721 .get_strings = atl1_get_strings,
2722 .nway_reset = atl1_nway_reset,
2723 .get_ethtool_stats = atl1_get_ethtool_stats,
2724 .get_sset_count = atl1_get_sset_count,
2725 .set_tso = ethtool_op_set_tso,
2726};
2727
2728/*
2729 * Reset the transmit and receive units; mask and clear all interrupts.
2730 * hw - Struct containing variables accessed by shared code
2731 * return : 0 or idle status (if error)
2732 */
2733s32 atl1_reset_hw(struct atl1_hw *hw)
2734{
2735 struct pci_dev *pdev = hw->back->pdev;
2736 u32 icr;
2737 int i;
2738
2739 /*
2740 * Clear Interrupt mask to stop board from generating
2741 * interrupts & Clear any pending interrupt events
2742 */
2743 /*
2744 * iowrite32(0, hw->hw_addr + REG_IMR);
2745 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
2746 */
2747
2748 /*
2749 * Issue Soft Reset to the MAC. This will reset the chip's
2750 * transmit, receive, DMA. It will not effect
2751 * the current PCI configuration. The global reset bit is self-
2752 * clearing, and should clear within a microsecond.
2753 */
2754 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
2755 ioread32(hw->hw_addr + REG_MASTER_CTRL);
2756
2757 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
2758 ioread16(hw->hw_addr + REG_PHY_ENABLE);
2759
2760 /* delay about 1ms */
2761 msleep(1);
2762
2763 /* Wait at least 10ms for All module to be Idle */
2764 for (i = 0; i < 10; i++) {
2765 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
2766 if (!icr)
2767 break;
2768 /* delay 1 ms */
2769 msleep(1);
2770 /* FIXME: still the right way to do this? */
2771 cpu_relax();
2772 }
2773
2774 if (icr) {
2775 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
2776 return icr;
2777 }
2778
2779 return 0;
2780}
2781
2782/* function about EEPROM
2783 *
2784 * check_eeprom_exist
2785 * return 0 if eeprom exist
2786 */
2787static int atl1_check_eeprom_exist(struct atl1_hw *hw)
2788{
2789 u32 value;
2790 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
2791 if (value & SPI_FLASH_CTRL_EN_VPD) {
2792 value &= ~SPI_FLASH_CTRL_EN_VPD;
2793 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
2794 }
2795
2796 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
2797 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2798}
2799
2800static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
2801{
2802 int i;
2803 u32 control;
2804
2805 if (offset & 3)
2806 /* address do not align */
2807 return false;
2808
2809 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
2810 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2811 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
2812 ioread32(hw->hw_addr + REG_VPD_CAP);
2813
2814 for (i = 0; i < 10; i++) {
2815 msleep(2);
2816 control = ioread32(hw->hw_addr + REG_VPD_CAP);
2817 if (control & VPD_CAP_VPD_FLAG)
2818 break;
2819 }
2820 if (control & VPD_CAP_VPD_FLAG) {
2821 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
2822 return true;
2823 }
2824 /* timeout */
2825 return false;
2826}
2827
2828/*
2829 * Reads the value from a PHY register
2830 * hw - Struct containing variables accessed by shared code
2831 * reg_addr - address of the PHY register to read
2832 */
2833s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
2834{
2835 u32 val;
2836 int i;
2837
2838 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2839 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
2840 MDIO_CLK_SEL_SHIFT;
2841 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
2842 ioread32(hw->hw_addr + REG_MDIO_CTRL);
2843
2844 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2845 udelay(2);
2846 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
2847 if (!(val & (MDIO_START | MDIO_BUSY)))
2848 break;
2849 }
2850 if (!(val & (MDIO_START | MDIO_BUSY))) {
2851 *phy_data = (u16) val;
2852 return 0;
2853 }
2854 return ATLX_ERR_PHY;
2855}
2856
2857#define CUSTOM_SPI_CS_SETUP 2
2858#define CUSTOM_SPI_CLK_HI 2
2859#define CUSTOM_SPI_CLK_LO 2
2860#define CUSTOM_SPI_CS_HOLD 2
2861#define CUSTOM_SPI_CS_HI 3
2862
2863static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
2864{
2865 int i;
2866 u32 value;
2867
2868 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
2869 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
2870
2871 value = SPI_FLASH_CTRL_WAIT_READY |
2872 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2873 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
2874 SPI_FLASH_CTRL_CLK_HI_MASK) <<
2875 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
2876 SPI_FLASH_CTRL_CLK_LO_MASK) <<
2877 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
2878 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2879 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
2880 SPI_FLASH_CTRL_CS_HI_MASK) <<
2881 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
2882 SPI_FLASH_CTRL_INS_SHIFT;
2883
2884 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
2885
2886 value |= SPI_FLASH_CTRL_START;
2887 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
2888 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
2889
2890 for (i = 0; i < 10; i++) {
2891 msleep(1);
2892 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
2893 if (!(value & SPI_FLASH_CTRL_START))
2894 break;
2895 }
2896
2897 if (value & SPI_FLASH_CTRL_START)
2898 return false;
2899
2900 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
2901
2902 return true;
2903}
2904
2905/*
2906 * get_permanent_address
2907 * return 0 if get valid mac address,
2908 */
2909static int atl1_get_permanent_address(struct atl1_hw *hw)
2910{
2911 u32 addr[2];
2912 u32 i, control;
2913 u16 reg;
2914 u8 eth_addr[ETH_ALEN];
2915 bool key_valid;
2916
2917 if (is_valid_ether_addr(hw->perm_mac_addr))
2918 return 0;
2919
2920 /* init */
2921 addr[0] = addr[1] = 0;
2922
2923 if (!atl1_check_eeprom_exist(hw)) {
2924 reg = 0;
2925 key_valid = false;
2926 /* Read out all EEPROM content */
2927 i = 0;
2928 while (1) {
2929 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
2930 if (key_valid) {
2931 if (reg == REG_MAC_STA_ADDR)
2932 addr[0] = control;
2933 else if (reg == (REG_MAC_STA_ADDR + 4))
2934 addr[1] = control;
2935 key_valid = false;
2936 } else if ((control & 0xff) == 0x5A) {
2937 key_valid = true;
2938 reg = (u16) (control >> 16);
2939 } else
2940 break;
2941 } else
2942 /* read error */
2943 break;
2944 i += 4;
2945 }
2946
2947 *(u32 *) &eth_addr[2] = swab32(addr[0]);
2948 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
2949 if (is_valid_ether_addr(eth_addr)) {
2950 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
2951 return 0;
2952 }
2953 return 1;
2954 }
2955
2956 /* see if SPI FLAGS exist ? */
2957 addr[0] = addr[1] = 0;
2958 reg = 0;
2959 key_valid = false;
2960 i = 0;
2961 while (1) {
2962 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
2963 if (key_valid) {
2964 if (reg == REG_MAC_STA_ADDR)
2965 addr[0] = control;
2966 else if (reg == (REG_MAC_STA_ADDR + 4))
2967 addr[1] = control;
2968 key_valid = false;
2969 } else if ((control & 0xff) == 0x5A) {
2970 key_valid = true;
2971 reg = (u16) (control >> 16);
2972 } else
2973 /* data end */
2974 break;
2975 } else
2976 /* read error */
2977 break;
2978 i += 4;
2979 }
2980
2981 *(u32 *) &eth_addr[2] = swab32(addr[0]);
2982 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
2983 if (is_valid_ether_addr(eth_addr)) {
2984 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
2985 return 0;
2986 }
2987
2988 /*
2989 * On some motherboards, the MAC address is written by the
2990 * BIOS directly to the MAC register during POST, and is
2991 * not stored in eeprom. If all else thus far has failed
2992 * to fetch the permanent MAC address, try reading it directly.
2993 */
2994 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
2995 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
2996 *(u32 *) &eth_addr[2] = swab32(addr[0]);
2997 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
2998 if (is_valid_ether_addr(eth_addr)) {
2999 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
3000 return 0;
3001 }
3002
3003 return 1;
3004}
3005
3006/*
3007 * Reads the adapter's MAC address from the EEPROM
3008 * hw - Struct containing variables accessed by shared code
3009 */
3010s32 atl1_read_mac_addr(struct atl1_hw *hw)
3011{
3012 u16 i;
3013
3014 if (atl1_get_permanent_address(hw))
3015 random_ether_addr(hw->perm_mac_addr);
3016
3017 for (i = 0; i < ETH_ALEN; i++)
3018 hw->mac_addr[i] = hw->perm_mac_addr[i];
3019 return 0;
3020}
3021
3022/*
3023 * Hashes an address to determine its location in the multicast table
3024 * hw - Struct containing variables accessed by shared code
3025 * mc_addr - the multicast address to hash
3026 *
3027 * atl1_hash_mc_addr
3028 * purpose
3029 * set hash value for a multicast address
3030 * hash calcu processing :
3031 * 1. calcu 32bit CRC for multicast address
3032 * 2. reverse crc with MSB to LSB
3033 */
3034u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
3035{
3036 u32 crc32, value = 0;
3037 int i;
3038
3039 crc32 = ether_crc_le(6, mc_addr);
3040 for (i = 0; i < 32; i++)
3041 value |= (((crc32 >> i) & 1) << (31 - i));
3042
3043 return value;
3044}
3045
3046/*
3047 * Sets the bit in the multicast table corresponding to the hash value.
3048 * hw - Struct containing variables accessed by shared code
3049 * hash_value - Multicast address hash value
3050 */
3051void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
3052{
3053 u32 hash_bit, hash_reg;
3054 u32 mta;
3055
3056 /*
3057 * The HASH Table is a register array of 2 32-bit registers.
3058 * It is treated like an array of 64 bits. We want to set
3059 * bit BitArray[hash_value]. So we figure out what register
3060 * the bit is in, read it, OR in the new bit, then write
3061 * back the new value. The register is determined by the
3062 * upper 7 bits of the hash value and the bit within that
3063 * register are determined by the lower 5 bits of the value.
3064 */
3065 hash_reg = (hash_value >> 31) & 0x1;
3066 hash_bit = (hash_value >> 26) & 0x1F;
3067 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
3068 mta |= (1 << hash_bit);
3069 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
3070}
3071
3072/*
3073 * Writes a value to a PHY register
3074 * hw - Struct containing variables accessed by shared code
3075 * reg_addr - address of the PHY register to write
3076 * data - data to write to the PHY
3077 */
3078s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
3079{
3080 int i;
3081 u32 val;
3082
3083 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
3084 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
3085 MDIO_SUP_PREAMBLE |
3086 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
3087 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
3088 ioread32(hw->hw_addr + REG_MDIO_CTRL);
3089
3090 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
3091 udelay(2);
3092 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
3093 if (!(val & (MDIO_START | MDIO_BUSY)))
3094 break;
3095 }
3096
3097 if (!(val & (MDIO_START | MDIO_BUSY)))
3098 return 0;
3099
3100 return ATLX_ERR_PHY;
3101}
3102
3103/*
3104 * Make L001's PHY out of Power Saving State (bug)
3105 * hw - Struct containing variables accessed by shared code
3106 * when power on, L001's PHY always on Power saving State
3107 * (Gigabit Link forbidden)
3108 */
3109static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
3110{
3111 s32 ret;
3112 ret = atl1_write_phy_reg(hw, 29, 0x0029);
3113 if (ret)
3114 return ret;
3115 return atl1_write_phy_reg(hw, 30, 0);
3116}
3117
3118/*
3119 *TODO: do something or get rid of this
3120 */
3121s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
3122{
3123/* s32 ret_val;
3124 * u16 phy_data;
3125 */
3126
3127/*
3128 ret_val = atl1_write_phy_reg(hw, ...);
3129 ret_val = atl1_write_phy_reg(hw, ...);
3130 ....
3131*/
3132 return 0;
3133}
3134
3135/*
3136 * Resets the PHY and make all config validate
3137 * hw - Struct containing variables accessed by shared code
3138 *
3139 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
3140 */
3141static s32 atl1_phy_reset(struct atl1_hw *hw)
3142{
3143 struct pci_dev *pdev = hw->back->pdev;
3144 s32 ret_val;
3145 u16 phy_data;
3146
3147 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3148 hw->media_type == MEDIA_TYPE_1000M_FULL)
3149 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3150 else {
3151 switch (hw->media_type) {
3152 case MEDIA_TYPE_100M_FULL:
3153 phy_data =
3154 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3155 MII_CR_RESET;
3156 break;
3157 case MEDIA_TYPE_100M_HALF:
3158 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3159 break;
3160 case MEDIA_TYPE_10M_FULL:
3161 phy_data =
3162 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3163 break;
3164 default:
3165 /* MEDIA_TYPE_10M_HALF: */
3166 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3167 break;
3168 }
3169 }
3170
3171 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3172 if (ret_val) {
3173 u32 val;
3174 int i;
3175 /* pcie serdes link may be down! */
3176 dev_dbg(&pdev->dev, "pcie phy link down\n");
3177
3178 for (i = 0; i < 25; i++) {
3179 msleep(1);
3180 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
3181 if (!(val & (MDIO_START | MDIO_BUSY)))
3182 break;
3183 }
3184
3185 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
3186 dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
3187 return ret_val;
3188 }
3189 }
3190 return 0;
3191}
3192
3193/*
3194 * Configures PHY autoneg and flow control advertisement settings
3195 * hw - Struct containing variables accessed by shared code
3196 */
3197s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
3198{
3199 s32 ret_val;
3200 s16 mii_autoneg_adv_reg;
3201 s16 mii_1000t_ctrl_reg;
3202
3203 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3204 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
3205
3206 /* Read the MII 1000Base-T Control Register (Address 9). */
3207 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
3208
3209 /*
3210 * First we clear all the 10/100 mb speed bits in the Auto-Neg
3211 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3212 * the 1000Base-T Control Register (Address 9).
3213 */
3214 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
3215 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
3216
3217 /*
3218 * Need to parse media_type and set up
3219 * the appropriate PHY registers.
3220 */
3221 switch (hw->media_type) {
3222 case MEDIA_TYPE_AUTO_SENSOR:
3223 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
3224 MII_AR_10T_FD_CAPS |
3225 MII_AR_100TX_HD_CAPS |
3226 MII_AR_100TX_FD_CAPS);
3227 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
3228 break;
3229
3230 case MEDIA_TYPE_1000M_FULL:
3231 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
3232 break;
3233
3234 case MEDIA_TYPE_100M_FULL:
3235 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
3236 break;
3237
3238 case MEDIA_TYPE_100M_HALF:
3239 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
3240 break;
3241
3242 case MEDIA_TYPE_10M_FULL:
3243 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
3244 break;
3245
3246 default:
3247 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
3248 break;
3249 }
3250
3251 /* flow control fixed to enable all */
3252 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
3253
3254 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
3255 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
3256
3257 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
3258 if (ret_val)
3259 return ret_val;
3260
3261 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
3262 if (ret_val)
3263 return ret_val;
3264
3265 return 0;
3266}
3267
3268/*
3269 * Configures link settings.
3270 * hw - Struct containing variables accessed by shared code
3271 * Assumes the hardware has previously been reset and the
3272 * transmitter and receiver are not enabled.
3273 */
3274static s32 atl1_setup_link(struct atl1_hw *hw)
3275{
3276 struct pci_dev *pdev = hw->back->pdev;
3277 s32 ret_val;
3278
3279 /*
3280 * Options:
3281 * PHY will advertise value(s) parsed from
3282 * autoneg_advertised and fc
3283 * no matter what autoneg is , We will not wait link result.
3284 */
3285 ret_val = atl1_phy_setup_autoneg_adv(hw);
3286 if (ret_val) {
3287 dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
3288 return ret_val;
3289 }
3290 /* SW.Reset , En-Auto-Neg if needed */
3291 ret_val = atl1_phy_reset(hw);
3292 if (ret_val) {
3293 dev_dbg(&pdev->dev, "error resetting phy\n");
3294 return ret_val;
3295 }
3296 hw->phy_configured = true;
3297 return ret_val;
3298}
3299
3300static void atl1_init_flash_opcode(struct atl1_hw *hw)
3301{
3302 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
3303 /* Atmel */
3304 hw->flash_vendor = 0;
3305
3306 /* Init OP table */
3307 iowrite8(flash_table[hw->flash_vendor].cmd_program,
3308 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
3309 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
3310 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
3311 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
3312 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
3313 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
3314 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
3315 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
3316 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
3317 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
3318 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
3319 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
3320 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
3321 iowrite8(flash_table[hw->flash_vendor].cmd_read,
3322 hw->hw_addr + REG_SPI_FLASH_OP_READ);
3323}
3324
3325/*
3326 * Performs basic configuration of the adapter.
3327 * hw - Struct containing variables accessed by shared code
3328 * Assumes that the controller has previously been reset and is in a
3329 * post-reset uninitialized state. Initializes multicast table,
3330 * and Calls routines to setup link
3331 * Leaves the transmit and receive units disabled and uninitialized.
3332 */
3333s32 atl1_init_hw(struct atl1_hw *hw)
3334{
3335 u32 ret_val = 0;
3336
3337 /* Zero out the Multicast HASH table */
3338 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
3339 /* clear the old settings from the multicast hash table */
3340 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
3341
3342 atl1_init_flash_opcode(hw);
3343
3344 if (!hw->phy_configured) {
3345 /* enable GPHY LinkChange Interrrupt */
3346 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
3347 if (ret_val)
3348 return ret_val;
3349 /* make PHY out of power-saving state */
3350 ret_val = atl1_phy_leave_power_saving(hw);
3351 if (ret_val)
3352 return ret_val;
3353 /* Call a subroutine to configure the link */
3354 ret_val = atl1_setup_link(hw);
3355 }
3356 return ret_val;
3357}
3358
3359/*
3360 * Detects the current speed and duplex settings of the hardware.
3361 * hw - Struct containing variables accessed by shared code
3362 * speed - Speed of the connection
3363 * duplex - Duplex setting of the connection
3364 */
3365s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
3366{
3367 struct pci_dev *pdev = hw->back->pdev;
3368 s32 ret_val;
3369 u16 phy_data;
3370
3371 /* ; --- Read PHY Specific Status Register (17) */
3372 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
3373 if (ret_val)
3374 return ret_val;
3375
3376 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
3377 return ATLX_ERR_PHY_RES;
3378
3379 switch (phy_data & MII_ATLX_PSSR_SPEED) {
3380 case MII_ATLX_PSSR_1000MBS:
3381 *speed = SPEED_1000;
3382 break;
3383 case MII_ATLX_PSSR_100MBS:
3384 *speed = SPEED_100;
3385 break;
3386 case MII_ATLX_PSSR_10MBS:
3387 *speed = SPEED_10;
3388 break;
3389 default:
3390 dev_dbg(&pdev->dev, "error getting speed\n");
3391 return ATLX_ERR_PHY_SPEED;
3392 break;
3393 }
3394 if (phy_data & MII_ATLX_PSSR_DPLX)
3395 *duplex = FULL_DUPLEX;
3396 else
3397 *duplex = HALF_DUPLEX;
3398
3399 return 0;
3400}
3401
3402void atl1_set_mac_addr(struct atl1_hw *hw)
3403{
3404 u32 value;
3405 /*
3406 * 00-0B-6A-F6-00-DC
3407 * 0: 6AF600DC 1: 000B
3408 * low dword
3409 */
3410 value = (((u32) hw->mac_addr[2]) << 24) |
3411 (((u32) hw->mac_addr[3]) << 16) |
3412 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
3413 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
3414 /* high dword */
3415 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
3416 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
3417}
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index ff4765f6c3de..538948d5a184 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com> 3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com> 4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 * 5 *
6 * Derived from Intel e1000 driver 6 * Derived from Intel e1000 driver
@@ -21,26 +21,559 @@
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */ 22 */
23 23
24#ifndef _ATL1_H_ 24#ifndef ATL1_H
25#define _ATL1_H_ 25#define ATL1_H
26 26
27#include <linux/types.h> 27#include <linux/compiler.h>
28#include <linux/ethtool.h>
28#include <linux/if_vlan.h> 29#include <linux/if_vlan.h>
30#include <linux/mii.h>
31#include <linux/module.h>
32#include <linux/skbuff.h>
33#include <linux/spinlock.h>
34#include <linux/timer.h>
35#include <linux/types.h>
36#include <linux/workqueue.h>
37
38#include "atlx.h"
39
40#define ATLX_DRIVER_NAME "atl1"
29 41
30#include "atl1_hw.h" 42MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
43
44#define atlx_adapter atl1_adapter
45#define atlx_check_for_link atl1_check_for_link
46#define atlx_check_link atl1_check_link
47#define atlx_hash_mc_addr atl1_hash_mc_addr
48#define atlx_hash_set atl1_hash_set
49#define atlx_hw atl1_hw
50#define atlx_mii_ioctl atl1_mii_ioctl
51#define atlx_read_phy_reg atl1_read_phy_reg
52#define atlx_set_mac atl1_set_mac
53#define atlx_set_mac_addr atl1_set_mac_addr
54
55struct atl1_adapter;
56struct atl1_hw;
31 57
32/* function prototypes needed by multiple files */ 58/* function prototypes needed by multiple files */
59s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
60s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
61s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
62s32 atl1_read_mac_addr(struct atl1_hw *hw);
63s32 atl1_init_hw(struct atl1_hw *hw);
64s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
65s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
66u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
67void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
68s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
69void atl1_set_mac_addr(struct atl1_hw *hw);
70s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
71s32 atl1_reset_hw(struct atl1_hw *hw);
72void atl1_check_options(struct atl1_adapter *adapter);
73static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
74 int cmd);
75static u32 atl1_check_link(struct atl1_adapter *adapter);
33s32 atl1_up(struct atl1_adapter *adapter); 76s32 atl1_up(struct atl1_adapter *adapter);
34void atl1_down(struct atl1_adapter *adapter); 77void atl1_down(struct atl1_adapter *adapter);
35int atl1_reset(struct atl1_adapter *adapter); 78int atl1_reset(struct atl1_adapter *adapter);
36s32 atl1_setup_ring_resources(struct atl1_adapter *adapter);
37void atl1_free_ring_resources(struct atl1_adapter *adapter);
38 79
39extern char atl1_driver_name[];
40extern char atl1_driver_version[];
41extern const struct ethtool_ops atl1_ethtool_ops; 80extern const struct ethtool_ops atl1_ethtool_ops;
42 81
43struct atl1_adapter; 82/* hardware definitions specific to L1 */
83
84/* Block IDLE Status Register */
85#define IDLE_STATUS_RXMAC 0x1
86#define IDLE_STATUS_TXMAC 0x2
87#define IDLE_STATUS_RXQ 0x4
88#define IDLE_STATUS_TXQ 0x8
89#define IDLE_STATUS_DMAR 0x10
90#define IDLE_STATUS_DMAW 0x20
91#define IDLE_STATUS_SMB 0x40
92#define IDLE_STATUS_CMB 0x80
93
94/* MDIO Control Register */
95#define MDIO_WAIT_TIMES 30
96
97/* MAC Control Register */
98#define MAC_CTRL_TX_PAUSE 0x10000
99#define MAC_CTRL_SCNT 0x20000
100#define MAC_CTRL_SRST_TX 0x40000
101#define MAC_CTRL_TX_SIMURST 0x80000
102#define MAC_CTRL_SPEED_SHIFT 20
103#define MAC_CTRL_SPEED_MASK 0x300000
104#define MAC_CTRL_SPEED_1000 0x2
105#define MAC_CTRL_SPEED_10_100 0x1
106#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
107#define MAC_CTRL_TX_HUGE 0x800000
108#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
109#define MAC_CTRL_DBG 0x8000000
110
111/* Wake-On-Lan control register */
112#define WOL_CLK_SWITCH_EN 0x8000
113#define WOL_PT5_EN 0x200000
114#define WOL_PT6_EN 0x400000
115#define WOL_PT5_MATCH 0x8000000
116#define WOL_PT6_MATCH 0x10000000
117
118/* WOL Length ( 2 DWORD ) */
119#define REG_WOL_PATTERN_LEN 0x14A4
120#define WOL_PT_LEN_MASK 0x7F
121#define WOL_PT0_LEN_SHIFT 0
122#define WOL_PT1_LEN_SHIFT 8
123#define WOL_PT2_LEN_SHIFT 16
124#define WOL_PT3_LEN_SHIFT 24
125#define WOL_PT4_LEN_SHIFT 0
126#define WOL_PT5_LEN_SHIFT 8
127#define WOL_PT6_LEN_SHIFT 16
128
129/* Internal SRAM Partition Registers, low 32 bits */
130#define REG_SRAM_RFD_LEN 0x1504
131#define REG_SRAM_RRD_ADDR 0x1508
132#define REG_SRAM_RRD_LEN 0x150C
133#define REG_SRAM_TPD_ADDR 0x1510
134#define REG_SRAM_TPD_LEN 0x1514
135#define REG_SRAM_TRD_ADDR 0x1518
136#define REG_SRAM_TRD_LEN 0x151C
137#define REG_SRAM_RXF_ADDR 0x1520
138#define REG_SRAM_RXF_LEN 0x1524
139#define REG_SRAM_TXF_ADDR 0x1528
140#define REG_SRAM_TXF_LEN 0x152C
141#define REG_SRAM_TCPH_PATH_ADDR 0x1530
142#define SRAM_TCPH_ADDR_MASK 0xFFF
143#define SRAM_TCPH_ADDR_SHIFT 0
144#define SRAM_PATH_ADDR_MASK 0xFFF
145#define SRAM_PATH_ADDR_SHIFT 16
146
147/* Load Ptr Register */
148#define REG_LOAD_PTR 0x1534
149
150/* Descriptor Control registers, low 32 bits */
151#define REG_DESC_RFD_ADDR_LO 0x1544
152#define REG_DESC_RRD_ADDR_LO 0x1548
153#define REG_DESC_TPD_ADDR_LO 0x154C
154#define REG_DESC_CMB_ADDR_LO 0x1550
155#define REG_DESC_SMB_ADDR_LO 0x1554
156#define REG_DESC_RFD_RRD_RING_SIZE 0x1558
157#define DESC_RFD_RING_SIZE_MASK 0x7FF
158#define DESC_RFD_RING_SIZE_SHIFT 0
159#define DESC_RRD_RING_SIZE_MASK 0x7FF
160#define DESC_RRD_RING_SIZE_SHIFT 16
161#define REG_DESC_TPD_RING_SIZE 0x155C
162#define DESC_TPD_RING_SIZE_MASK 0x3FF
163#define DESC_TPD_RING_SIZE_SHIFT 0
164
165/* TXQ Control Register */
166#define REG_TXQ_CTRL 0x1580
167#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
168#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
169#define TXQ_CTRL_EN 0x20
170#define TXQ_CTRL_ENH_MODE 0x40
171#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
172#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
173#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
174#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
175
176/* Jumbo packet Threshold for task offload */
177#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
178#define TX_JUMBO_TASK_TH_MASK 0x7FF
179#define TX_JUMBO_TASK_TH_SHIFT 0
180#define TX_TPD_MIN_IPG_MASK 0x1F
181#define TX_TPD_MIN_IPG_SHIFT 16
182
183/* RXQ Control Register */
184#define REG_RXQ_CTRL 0x15A0
185#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
186#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
187#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
188#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
189#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
190#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
191#define RXQ_CTRL_CUT_THRU_EN 0x40000000
192#define RXQ_CTRL_EN 0x80000000
193
194/* Rx jumbo packet threshold and rrd retirement timer */
195#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
196#define RXQ_JMBOSZ_TH_MASK 0x7FF
197#define RXQ_JMBOSZ_TH_SHIFT 0
198#define RXQ_JMBO_LKAH_MASK 0xF
199#define RXQ_JMBO_LKAH_SHIFT 11
200#define RXQ_RRD_TIMER_MASK 0xFFFF
201#define RXQ_RRD_TIMER_SHIFT 16
202
203/* RFD flow control register */
204#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
205#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
206#define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
207#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
208#define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
209
210/* RRD flow control register */
211#define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
212#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
213#define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
214#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
215#define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
216
217/* DMA Engine Control Register */
218#define REG_DMA_CTRL 0x15C0
219#define DMA_CTRL_DMAR_IN_ORDER 0x1
220#define DMA_CTRL_DMAR_ENH_ORDER 0x2
221#define DMA_CTRL_DMAR_OUT_ORDER 0x4
222#define DMA_CTRL_RCB_VALUE 0x8
223#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
224#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
225#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
226#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
227#define DMA_CTRL_DMAR_EN 0x400
228#define DMA_CTRL_DMAW_EN 0x800
229
230/* CMB/SMB Control Register */
231#define REG_CSMB_CTRL 0x15D0
232#define CSMB_CTRL_CMB_NOW 1
233#define CSMB_CTRL_SMB_NOW 2
234#define CSMB_CTRL_CMB_EN 4
235#define CSMB_CTRL_SMB_EN 8
236
237/* CMB DMA Write Threshold Register */
238#define REG_CMB_WRITE_TH 0x15D4
239#define CMB_RRD_TH_SHIFT 0
240#define CMB_RRD_TH_MASK 0x7FF
241#define CMB_TPD_TH_SHIFT 16
242#define CMB_TPD_TH_MASK 0x7FF
243
244/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
245#define REG_CMB_WRITE_TIMER 0x15D8
246#define CMB_RX_TM_SHIFT 0
247#define CMB_RX_TM_MASK 0xFFFF
248#define CMB_TX_TM_SHIFT 16
249#define CMB_TX_TM_MASK 0xFFFF
250
251/* Number of packet received since last CMB write */
252#define REG_CMB_RX_PKT_CNT 0x15DC
253
254/* Number of packet transmitted since last CMB write */
255#define REG_CMB_TX_PKT_CNT 0x15E0
256
257/* SMB auto DMA timer register */
258#define REG_SMB_TIMER 0x15E4
259
260/* Mailbox Register */
261#define REG_MAILBOX 0x15F0
262#define MB_RFD_PROD_INDX_SHIFT 0
263#define MB_RFD_PROD_INDX_MASK 0x7FF
264#define MB_RRD_CONS_INDX_SHIFT 11
265#define MB_RRD_CONS_INDX_MASK 0x7FF
266#define MB_TPD_PROD_INDX_SHIFT 22
267#define MB_TPD_PROD_INDX_MASK 0x3FF
268
269/* Interrupt Status Register */
270#define ISR_SMB 0x1
271#define ISR_TIMER 0x2
272#define ISR_MANUAL 0x4
273#define ISR_RXF_OV 0x8
274#define ISR_RFD_UNRUN 0x10
275#define ISR_RRD_OV 0x20
276#define ISR_TXF_UNRUN 0x40
277#define ISR_LINK 0x80
278#define ISR_HOST_RFD_UNRUN 0x100
279#define ISR_HOST_RRD_OV 0x200
280#define ISR_DMAR_TO_RST 0x400
281#define ISR_DMAW_TO_RST 0x800
282#define ISR_GPHY 0x1000
283#define ISR_RX_PKT 0x10000
284#define ISR_TX_PKT 0x20000
285#define ISR_TX_DMA 0x40000
286#define ISR_RX_DMA 0x80000
287#define ISR_CMB_RX 0x100000
288#define ISR_CMB_TX 0x200000
289#define ISR_MAC_RX 0x400000
290#define ISR_MAC_TX 0x800000
291#define ISR_DIS_SMB 0x20000000
292#define ISR_DIS_DMA 0x40000000
293
294/* Normal Interrupt mask */
295#define IMR_NORMAL_MASK (\
296 ISR_SMB |\
297 ISR_GPHY |\
298 ISR_PHY_LINKDOWN|\
299 ISR_DMAR_TO_RST |\
300 ISR_DMAW_TO_RST |\
301 ISR_CMB_TX |\
302 ISR_CMB_RX)
303
304/* Debug Interrupt Mask (enable all interrupt) */
305#define IMR_DEBUG_MASK (\
306 ISR_SMB |\
307 ISR_TIMER |\
308 ISR_MANUAL |\
309 ISR_RXF_OV |\
310 ISR_RFD_UNRUN |\
311 ISR_RRD_OV |\
312 ISR_TXF_UNRUN |\
313 ISR_LINK |\
314 ISR_CMB_TX |\
315 ISR_CMB_RX |\
316 ISR_RX_PKT |\
317 ISR_TX_PKT |\
318 ISR_MAC_RX |\
319 ISR_MAC_TX)
320
321#define MEDIA_TYPE_1000M_FULL 1
322#define MEDIA_TYPE_100M_FULL 2
323#define MEDIA_TYPE_100M_HALF 3
324#define MEDIA_TYPE_10M_FULL 4
325#define MEDIA_TYPE_10M_HALF 5
326
327#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
328
329#define MAX_JUMBO_FRAME_SIZE 10240
330
331#define ATL1_EEDUMP_LEN 48
332
333/* Statistics counters collected by the MAC */
334struct stats_msg_block {
335 /* rx */
336 u32 rx_ok; /* good RX packets */
337 u32 rx_bcast; /* good RX broadcast packets */
338 u32 rx_mcast; /* good RX multicast packets */
339 u32 rx_pause; /* RX pause frames */
340 u32 rx_ctrl; /* RX control packets other than pause frames */
341 u32 rx_fcs_err; /* RX packets with bad FCS */
342 u32 rx_len_err; /* RX packets with length != actual size */
343 u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
344 u32 rx_runt; /* RX packets < 64 bytes with good FCS */
345 u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
346 u32 rx_sz_64; /* 64 byte RX packets */
347 u32 rx_sz_65_127;
348 u32 rx_sz_128_255;
349 u32 rx_sz_256_511;
350 u32 rx_sz_512_1023;
351 u32 rx_sz_1024_1518;
352 u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
353 u32 rx_sz_ov; /* truncated RX packets > MTU */
354 u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
355 u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
356 u32 rx_align_err; /* alignment errors */
357 u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
358 u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
359 u32 rx_err_addr; /* packets dropped due to address filtering */
360
361 /* tx */
362 u32 tx_ok; /* good TX packets */
363 u32 tx_bcast; /* good TX broadcast packets */
364 u32 tx_mcast; /* good TX multicast packets */
365 u32 tx_pause; /* TX pause frames */
366 u32 tx_exc_defer; /* TX packets deferred excessively */
367 u32 tx_ctrl; /* TX control frames, excluding pause frames */
368 u32 tx_defer; /* TX packets deferred */
369 u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
370 u32 tx_sz_64; /* 64 byte TX packets */
371 u32 tx_sz_65_127;
372 u32 tx_sz_128_255;
373 u32 tx_sz_256_511;
374 u32 tx_sz_512_1023;
375 u32 tx_sz_1024_1518;
376 u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
377 u32 tx_1_col; /* packets TX after a single collision */
378 u32 tx_2_col; /* packets TX after multiple collisions */
379 u32 tx_late_col; /* TX packets with late collisions */
380 u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
381 u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
382 * or TRD FIFO underrun */
383 u32 tx_rd_eop; /* reads beyond the EOP into the next frame
384 * when TRD was not written timely */
385 u32 tx_len_err; /* TX packets where length != actual size */
386 u32 tx_trunc; /* TX packets truncated due to size > MTU */
387 u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
388 u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
389 u32 smb_updated; /* 1: SMB Updated. This is used by software to
390 * indicate the statistics update. Software
391 * should clear this bit after retrieving the
392 * statistics information. */
393};
394
395/* Coalescing Message Block */
396struct coals_msg_block {
397 u32 int_stats; /* interrupt status */
398 u16 rrd_prod_idx; /* TRD Producer Index. */
399 u16 rfd_cons_idx; /* RFD Consumer Index. */
400 u16 update; /* Selene sets this bit every time it DMAs the
401 * CMB to host memory. Software should clear
402 * this bit when CMB info is processed. */
403 u16 tpd_cons_idx; /* TPD Consumer Index. */
404};
405
406/* RRD descriptor */
407struct rx_return_desc {
408 u8 num_buf; /* Number of RFD buffers used by the received packet */
409 u8 resved;
410 u16 buf_indx; /* RFD Index of the first buffer */
411 union {
412 u32 valid;
413 struct {
414 u16 rx_chksum;
415 u16 pkt_size;
416 } xsum_sz;
417 } xsz;
418
419 u16 pkt_flg; /* Packet flags */
420 u16 err_flg; /* Error flags */
421 u16 resved2;
422 u16 vlan_tag; /* VLAN TAG */
423};
424
425#define PACKET_FLAG_ETH_TYPE 0x0080
426#define PACKET_FLAG_VLAN_INS 0x0100
427#define PACKET_FLAG_ERR 0x0200
428#define PACKET_FLAG_IPV4 0x0400
429#define PACKET_FLAG_UDP 0x0800
430#define PACKET_FLAG_TCP 0x1000
431#define PACKET_FLAG_BCAST 0x2000
432#define PACKET_FLAG_MCAST 0x4000
433#define PACKET_FLAG_PAUSE 0x8000
434
435#define ERR_FLAG_CRC 0x0001
436#define ERR_FLAG_CODE 0x0002
437#define ERR_FLAG_DRIBBLE 0x0004
438#define ERR_FLAG_RUNT 0x0008
439#define ERR_FLAG_OV 0x0010
440#define ERR_FLAG_TRUNC 0x0020
441#define ERR_FLAG_IP_CHKSUM 0x0040
442#define ERR_FLAG_L4_CHKSUM 0x0080
443#define ERR_FLAG_LEN 0x0100
444#define ERR_FLAG_DES_ADDR 0x0200
445
446/* RFD descriptor */
447struct rx_free_desc {
448 __le64 buffer_addr; /* Address of the descriptor's data buffer */
449 __le16 buf_len; /* Size of the receive buffer in host memory */
450 u16 coalese; /* Update consumer index to host after the
451 * reception of this frame */
452 /* __attribute__ ((packed)) is required */
453} __attribute__ ((packed));
454
455/* tsopu defines */
456#define TSO_PARAM_BUFLEN_MASK 0x3FFF
457#define TSO_PARAM_BUFLEN_SHIFT 0
458#define TSO_PARAM_DMAINT_MASK 0x0001
459#define TSO_PARAM_DMAINT_SHIFT 14
460#define TSO_PARAM_PKTNT_MASK 0x0001
461#define TSO_PARAM_PKTINT_SHIFT 15
462#define TSO_PARAM_VLANTAG_MASK 0xFFFF
463#define TSO_PARAM_VLAN_SHIFT 16
464
465/* tsopl defines */
466#define TSO_PARAM_EOP_MASK 0x0001
467#define TSO_PARAM_EOP_SHIFT 0
468#define TSO_PARAM_COALESCE_MASK 0x0001
469#define TSO_PARAM_COALESCE_SHIFT 1
470#define TSO_PARAM_INSVLAG_MASK 0x0001
471#define TSO_PARAM_INSVLAG_SHIFT 2
472#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
473#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
474#define TSO_PARAM_SEGMENT_MASK 0x0001
475#define TSO_PARAM_SEGMENT_SHIFT 4
476#define TSO_PARAM_IPCKSUM_MASK 0x0001
477#define TSO_PARAM_IPCKSUM_SHIFT 5
478#define TSO_PARAM_TCPCKSUM_MASK 0x0001
479#define TSO_PARAM_TCPCKSUM_SHIFT 6
480#define TSO_PARAM_UDPCKSUM_MASK 0x0001
481#define TSO_PARAM_UDPCKSUM_SHIFT 7
482#define TSO_PARAM_VLANTAGGED_MASK 0x0001
483#define TSO_PARAM_VLANTAGGED_SHIFT 8
484#define TSO_PARAM_ETHTYPE_MASK 0x0001
485#define TSO_PARAM_ETHTYPE_SHIFT 9
486#define TSO_PARAM_IPHL_MASK 0x000F
487#define TSO_PARAM_IPHL_SHIFT 10
488#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
489#define TSO_PARAM_TCPHDRLEN_SHIFT 14
490#define TSO_PARAM_HDRFLAG_MASK 0x0001
491#define TSO_PARAM_HDRFLAG_SHIFT 18
492#define TSO_PARAM_MSS_MASK 0x1FFF
493#define TSO_PARAM_MSS_SHIFT 19
494
495/* csumpu defines */
496#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
497#define CSUM_PARAM_BUFLEN_SHIFT 0
498#define CSUM_PARAM_DMAINT_MASK 0x0001
499#define CSUM_PARAM_DMAINT_SHIFT 14
500#define CSUM_PARAM_PKTINT_MASK 0x0001
501#define CSUM_PARAM_PKTINT_SHIFT 15
502#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
503#define CSUM_PARAM_VALAN_SHIFT 16
504
505/* csumpl defines*/
506#define CSUM_PARAM_EOP_MASK 0x0001
507#define CSUM_PARAM_EOP_SHIFT 0
508#define CSUM_PARAM_COALESCE_MASK 0x0001
509#define CSUM_PARAM_COALESCE_SHIFT 1
510#define CSUM_PARAM_INSVLAG_MASK 0x0001
511#define CSUM_PARAM_INSVLAG_SHIFT 2
512#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
513#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
514#define CSUM_PARAM_SEGMENT_MASK 0x0001
515#define CSUM_PARAM_SEGMENT_SHIFT 4
516#define CSUM_PARAM_IPCKSUM_MASK 0x0001
517#define CSUM_PARAM_IPCKSUM_SHIFT 5
518#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
519#define CSUM_PARAM_TCPCKSUM_SHIFT 6
520#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
521#define CSUM_PARAM_UDPCKSUM_SHIFT 7
522#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
523#define CSUM_PARAM_VLANTAGGED_SHIFT 8
524#define CSUM_PARAM_ETHTYPE_MASK 0x0001
525#define CSUM_PARAM_ETHTYPE_SHIFT 9
526#define CSUM_PARAM_IPHL_MASK 0x000F
527#define CSUM_PARAM_IPHL_SHIFT 10
528#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
529#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
530#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
531#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
532
533/* TPD descriptor */
534struct tso_param {
535 /* The order of these declarations is important -- don't change it */
536 u32 tsopu; /* tso_param upper word */
537 u32 tsopl; /* tso_param lower word */
538};
539
540struct csum_param {
541 /* The order of these declarations is important -- don't change it */
542 u32 csumpu; /* csum_param upper word */
543 u32 csumpl; /* csum_param lower word */
544};
545
546union tpd_descr {
547 u64 data;
548 struct csum_param csum;
549 struct tso_param tso;
550};
551
552struct tx_packet_desc {
553 __le64 buffer_addr;
554 union tpd_descr desc;
555};
556
557/* DMA Order Settings */
558enum atl1_dma_order {
559 atl1_dma_ord_in = 1,
560 atl1_dma_ord_enh = 2,
561 atl1_dma_ord_out = 4
562};
563
564enum atl1_dma_rcb {
565 atl1_rcb_64 = 0,
566 atl1_rcb_128 = 1
567};
568
569enum atl1_dma_req_block {
570 atl1_dma_req_128 = 0,
571 atl1_dma_req_256 = 1,
572 atl1_dma_req_512 = 2,
573 atl1_dma_req_1024 = 3,
574 atl1_dma_req_2048 = 4,
575 atl1_dma_req_4096 = 5
576};
44 577
45#define ATL1_MAX_INTR 3 578#define ATL1_MAX_INTR 3
46#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */ 579#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
@@ -58,19 +591,6 @@ struct atl1_adapter;
58#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc) 591#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
59 592
60/* 593/*
61 * This detached comment is preserved for documentation purposes only.
62 * It was originally attached to some code that got deleted, but seems
63 * important enough to keep around...
64 *
65 * <begin detached comment>
66 * Some workarounds require millisecond delays and are run during interrupt
67 * context. Most notably, when establishing link, the phy may need tweaking
68 * but cannot process phy register reads/writes faster than millisecond
69 * intervals...and we establish link due to a "link status change" interrupt.
70 * <end detached comment>
71 */
72
73/*
74 * atl1_ring_header represents a single, contiguous block of DMA space 594 * atl1_ring_header represents a single, contiguous block of DMA space
75 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two 595 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
76 * message blocks (cmb, smb) described below 596 * message blocks (cmb, smb) described below
@@ -156,20 +676,15 @@ struct atl1_sft_stats {
156 u64 tx_aborted_errors; 676 u64 tx_aborted_errors;
157 u64 tx_window_errors; 677 u64 tx_window_errors;
158 u64 tx_carrier_errors; 678 u64 tx_carrier_errors;
159 u64 tx_pause; /* num pause packets transmitted. */ 679 u64 tx_pause; /* TX pause frames */
160 u64 excecol; /* num tx packets w/ excessive collisions. */ 680 u64 excecol; /* TX packets w/ excessive collisions */
161 u64 deffer; /* num tx packets deferred */ 681 u64 deffer; /* TX packets deferred */
162 u64 scc; /* num packets subsequently transmitted 682 u64 scc; /* packets TX after a single collision */
163 * successfully w/ single prior collision. */ 683 u64 mcc; /* packets TX after multiple collisions */
164 u64 mcc; /* num packets subsequently transmitted 684 u64 latecol; /* TX packets w/ late collisions */
165 * successfully w/ multiple prior collisions. */ 685 u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
166 u64 latecol; /* num tx packets w/ late collisions. */ 686 * or TRD FIFO underrun */
167 u64 tx_underun; /* num tx packets aborted due to transmit 687 u64 tx_trunc; /* TX packets truncated due to size > MTU */
168 * FIFO underrun, or TRD FIFO underrun */
169 u64 tx_trunc; /* num tx packets truncated due to size
170 * exceeding MTU, regardless whether truncated
171 * by the chip or not. (The name doesn't really
172 * reflect the meaning in this case.) */
173 u64 rx_pause; /* num Pause packets received. */ 688 u64 rx_pause; /* num Pause packets received. */
174 u64 rx_rrd_ov; 689 u64 rx_rrd_ov;
175 u64 rx_trunc; 690 u64 rx_trunc;
@@ -184,8 +699,7 @@ struct atl1_hw {
184 enum atl1_dma_req_block dmar_block; 699 enum atl1_dma_req_block dmar_block;
185 enum atl1_dma_req_block dmaw_block; 700 enum atl1_dma_req_block dmaw_block;
186 u8 preamble_len; 701 u8 preamble_len;
187 u8 max_retry; /* Retransmission maximum, after which the 702 u8 max_retry;
188 * packet will be discarded */
189 u8 jam_ipg; /* IPG to start JAM for collision based flow 703 u8 jam_ipg; /* IPG to start JAM for collision based flow
190 * control in half-duplex mode. In units of 704 * control in half-duplex mode. In units of
191 * 8-bit time */ 705 * 8-bit time */
@@ -271,16 +785,15 @@ struct atl1_adapter {
271 u64 hw_csum_err; 785 u64 hw_csum_err;
272 u64 hw_csum_good; 786 u64 hw_csum_good;
273 787
274 u16 imt; /* interrupt moderator timer (2us resolution */ 788 u16 imt; /* interrupt moderator timer (2us resolution) */
275 u16 ict; /* interrupt clear timer (2us resolution */ 789 u16 ict; /* interrupt clear timer (2us resolution */
276 struct mii_if_info mii; /* MII interface info */ 790 struct mii_if_info mii; /* MII interface info */
277 791
278 /* structs defined in atl1_hw.h */ 792 u32 bd_number; /* board number */
279 u32 bd_number; /* board number */
280 bool pci_using_64; 793 bool pci_using_64;
281 struct atl1_hw hw; 794 struct atl1_hw hw;
282 struct atl1_smb smb; 795 struct atl1_smb smb;
283 struct atl1_cmb cmb; 796 struct atl1_cmb cmb;
284}; 797};
285 798
286#endif /* _ATL1_H_ */ 799#endif /* ATL1_H */
diff --git a/drivers/net/atlx/atl1_ethtool.c b/drivers/net/atlx/atl1_ethtool.c
deleted file mode 100644
index 68a83be843ab..000000000000
--- a/drivers/net/atlx/atl1_ethtool.c
+++ /dev/null
@@ -1,505 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/ethtool.h>
27#include <linux/netdevice.h>
28#include <linux/mii.h>
29#include <asm/uaccess.h>
30
31#include "atl1.h"
32
33struct atl1_stats {
34 char stat_string[ETH_GSTRING_LEN];
35 int sizeof_stat;
36 int stat_offset;
37};
38
39#define ATL1_STAT(m) sizeof(((struct atl1_adapter *)0)->m), \
40 offsetof(struct atl1_adapter, m)
41
42static struct atl1_stats atl1_gstrings_stats[] = {
43 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
44 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
45 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
46 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
47 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
48 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
49 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
50 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
51 {"multicast", ATL1_STAT(soft_stats.multicast)},
52 {"collisions", ATL1_STAT(soft_stats.collisions)},
53 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
54 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
55 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
56 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
57 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
58 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
59 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
60 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
61 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
62 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
63 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
64 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
65 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
66 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
67 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
68 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
69 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
70 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
71 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
72 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
73 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
74};
75
76static void atl1_get_ethtool_stats(struct net_device *netdev,
77 struct ethtool_stats *stats, u64 *data)
78{
79 struct atl1_adapter *adapter = netdev_priv(netdev);
80 int i;
81 char *p;
82
83 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
84 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
85 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
86 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
87 }
88
89}
90
91static int atl1_get_sset_count(struct net_device *netdev, int sset)
92{
93 switch (sset) {
94 case ETH_SS_STATS:
95 return ARRAY_SIZE(atl1_gstrings_stats);
96 default:
97 return -EOPNOTSUPP;
98 }
99}
100
101static int atl1_get_settings(struct net_device *netdev,
102 struct ethtool_cmd *ecmd)
103{
104 struct atl1_adapter *adapter = netdev_priv(netdev);
105 struct atl1_hw *hw = &adapter->hw;
106
107 ecmd->supported = (SUPPORTED_10baseT_Half |
108 SUPPORTED_10baseT_Full |
109 SUPPORTED_100baseT_Half |
110 SUPPORTED_100baseT_Full |
111 SUPPORTED_1000baseT_Full |
112 SUPPORTED_Autoneg | SUPPORTED_TP);
113 ecmd->advertising = ADVERTISED_TP;
114 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
115 hw->media_type == MEDIA_TYPE_1000M_FULL) {
116 ecmd->advertising |= ADVERTISED_Autoneg;
117 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
118 ecmd->advertising |= ADVERTISED_Autoneg;
119 ecmd->advertising |=
120 (ADVERTISED_10baseT_Half |
121 ADVERTISED_10baseT_Full |
122 ADVERTISED_100baseT_Half |
123 ADVERTISED_100baseT_Full |
124 ADVERTISED_1000baseT_Full);
125 }
126 else
127 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
128 }
129 ecmd->port = PORT_TP;
130 ecmd->phy_address = 0;
131 ecmd->transceiver = XCVR_INTERNAL;
132
133 if (netif_carrier_ok(adapter->netdev)) {
134 u16 link_speed, link_duplex;
135 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
136 ecmd->speed = link_speed;
137 if (link_duplex == FULL_DUPLEX)
138 ecmd->duplex = DUPLEX_FULL;
139 else
140 ecmd->duplex = DUPLEX_HALF;
141 } else {
142 ecmd->speed = -1;
143 ecmd->duplex = -1;
144 }
145 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
146 hw->media_type == MEDIA_TYPE_1000M_FULL)
147 ecmd->autoneg = AUTONEG_ENABLE;
148 else
149 ecmd->autoneg = AUTONEG_DISABLE;
150
151 return 0;
152}
153
154static int atl1_set_settings(struct net_device *netdev,
155 struct ethtool_cmd *ecmd)
156{
157 struct atl1_adapter *adapter = netdev_priv(netdev);
158 struct atl1_hw *hw = &adapter->hw;
159 u16 phy_data;
160 int ret_val = 0;
161 u16 old_media_type = hw->media_type;
162
163 if (netif_running(adapter->netdev)) {
164 dev_dbg(&adapter->pdev->dev, "ethtool shutting down adapter\n");
165 atl1_down(adapter);
166 }
167
168 if (ecmd->autoneg == AUTONEG_ENABLE)
169 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
170 else {
171 if (ecmd->speed == SPEED_1000) {
172 if (ecmd->duplex != DUPLEX_FULL) {
173 dev_warn(&adapter->pdev->dev,
174 "can't force to 1000M half duplex\n");
175 ret_val = -EINVAL;
176 goto exit_sset;
177 }
178 hw->media_type = MEDIA_TYPE_1000M_FULL;
179 } else if (ecmd->speed == SPEED_100) {
180 if (ecmd->duplex == DUPLEX_FULL) {
181 hw->media_type = MEDIA_TYPE_100M_FULL;
182 } else
183 hw->media_type = MEDIA_TYPE_100M_HALF;
184 } else {
185 if (ecmd->duplex == DUPLEX_FULL)
186 hw->media_type = MEDIA_TYPE_10M_FULL;
187 else
188 hw->media_type = MEDIA_TYPE_10M_HALF;
189 }
190 }
191 switch (hw->media_type) {
192 case MEDIA_TYPE_AUTO_SENSOR:
193 ecmd->advertising =
194 ADVERTISED_10baseT_Half |
195 ADVERTISED_10baseT_Full |
196 ADVERTISED_100baseT_Half |
197 ADVERTISED_100baseT_Full |
198 ADVERTISED_1000baseT_Full |
199 ADVERTISED_Autoneg | ADVERTISED_TP;
200 break;
201 case MEDIA_TYPE_1000M_FULL:
202 ecmd->advertising =
203 ADVERTISED_1000baseT_Full |
204 ADVERTISED_Autoneg | ADVERTISED_TP;
205 break;
206 default:
207 ecmd->advertising = 0;
208 break;
209 }
210 if (atl1_phy_setup_autoneg_adv(hw)) {
211 ret_val = -EINVAL;
212 dev_warn(&adapter->pdev->dev,
213 "invalid ethtool speed/duplex setting\n");
214 goto exit_sset;
215 }
216 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
217 hw->media_type == MEDIA_TYPE_1000M_FULL)
218 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
219 else {
220 switch (hw->media_type) {
221 case MEDIA_TYPE_100M_FULL:
222 phy_data =
223 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
224 MII_CR_RESET;
225 break;
226 case MEDIA_TYPE_100M_HALF:
227 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
228 break;
229 case MEDIA_TYPE_10M_FULL:
230 phy_data =
231 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
232 break;
233 default: /* MEDIA_TYPE_10M_HALF: */
234 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
235 break;
236 }
237 }
238 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
239exit_sset:
240 if (ret_val)
241 hw->media_type = old_media_type;
242
243 if (netif_running(adapter->netdev)) {
244 dev_dbg(&adapter->pdev->dev, "ethtool starting adapter\n");
245 atl1_up(adapter);
246 } else if (!ret_val) {
247 dev_dbg(&adapter->pdev->dev, "ethtool resetting adapter\n");
248 atl1_reset(adapter);
249 }
250 return ret_val;
251}
252
253static void atl1_get_drvinfo(struct net_device *netdev,
254 struct ethtool_drvinfo *drvinfo)
255{
256 struct atl1_adapter *adapter = netdev_priv(netdev);
257
258 strncpy(drvinfo->driver, atl1_driver_name, sizeof(drvinfo->driver));
259 strncpy(drvinfo->version, atl1_driver_version,
260 sizeof(drvinfo->version));
261 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
262 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
263 sizeof(drvinfo->bus_info));
264 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
265}
266
267static void atl1_get_wol(struct net_device *netdev,
268 struct ethtool_wolinfo *wol)
269{
270 struct atl1_adapter *adapter = netdev_priv(netdev);
271
272 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
273 wol->wolopts = 0;
274 if (adapter->wol & ATL1_WUFC_EX)
275 wol->wolopts |= WAKE_UCAST;
276 if (adapter->wol & ATL1_WUFC_MC)
277 wol->wolopts |= WAKE_MCAST;
278 if (adapter->wol & ATL1_WUFC_BC)
279 wol->wolopts |= WAKE_BCAST;
280 if (adapter->wol & ATL1_WUFC_MAG)
281 wol->wolopts |= WAKE_MAGIC;
282 return;
283}
284
285static int atl1_set_wol(struct net_device *netdev,
286 struct ethtool_wolinfo *wol)
287{
288 struct atl1_adapter *adapter = netdev_priv(netdev);
289
290 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
291 return -EOPNOTSUPP;
292 adapter->wol = 0;
293 if (wol->wolopts & WAKE_UCAST)
294 adapter->wol |= ATL1_WUFC_EX;
295 if (wol->wolopts & WAKE_MCAST)
296 adapter->wol |= ATL1_WUFC_MC;
297 if (wol->wolopts & WAKE_BCAST)
298 adapter->wol |= ATL1_WUFC_BC;
299 if (wol->wolopts & WAKE_MAGIC)
300 adapter->wol |= ATL1_WUFC_MAG;
301 return 0;
302}
303
304static void atl1_get_ringparam(struct net_device *netdev,
305 struct ethtool_ringparam *ring)
306{
307 struct atl1_adapter *adapter = netdev_priv(netdev);
308 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
309 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
310
311 ring->rx_max_pending = ATL1_MAX_RFD;
312 ring->tx_max_pending = ATL1_MAX_TPD;
313 ring->rx_mini_max_pending = 0;
314 ring->rx_jumbo_max_pending = 0;
315 ring->rx_pending = rxdr->count;
316 ring->tx_pending = txdr->count;
317 ring->rx_mini_pending = 0;
318 ring->rx_jumbo_pending = 0;
319}
320
321static int atl1_set_ringparam(struct net_device *netdev,
322 struct ethtool_ringparam *ring)
323{
324 struct atl1_adapter *adapter = netdev_priv(netdev);
325 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
326 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
327 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
328
329 struct atl1_tpd_ring tpd_old, tpd_new;
330 struct atl1_rfd_ring rfd_old, rfd_new;
331 struct atl1_rrd_ring rrd_old, rrd_new;
332 struct atl1_ring_header rhdr_old, rhdr_new;
333 int err;
334
335 tpd_old = adapter->tpd_ring;
336 rfd_old = adapter->rfd_ring;
337 rrd_old = adapter->rrd_ring;
338 rhdr_old = adapter->ring_header;
339
340 if (netif_running(adapter->netdev))
341 atl1_down(adapter);
342
343 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
344 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
345 rfdr->count;
346 rfdr->count = (rfdr->count + 3) & ~3;
347 rrdr->count = rfdr->count;
348
349 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
350 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
351 tpdr->count;
352 tpdr->count = (tpdr->count + 3) & ~3;
353
354 if (netif_running(adapter->netdev)) {
355 /* try to get new resources before deleting old */
356 err = atl1_setup_ring_resources(adapter);
357 if (err)
358 goto err_setup_ring;
359
360 /*
361 * save the new, restore the old in order to free it,
362 * then restore the new back again
363 */
364
365 rfd_new = adapter->rfd_ring;
366 rrd_new = adapter->rrd_ring;
367 tpd_new = adapter->tpd_ring;
368 rhdr_new = adapter->ring_header;
369 adapter->rfd_ring = rfd_old;
370 adapter->rrd_ring = rrd_old;
371 adapter->tpd_ring = tpd_old;
372 adapter->ring_header = rhdr_old;
373 atl1_free_ring_resources(adapter);
374 adapter->rfd_ring = rfd_new;
375 adapter->rrd_ring = rrd_new;
376 adapter->tpd_ring = tpd_new;
377 adapter->ring_header = rhdr_new;
378
379 err = atl1_up(adapter);
380 if (err)
381 return err;
382 }
383 return 0;
384
385err_setup_ring:
386 adapter->rfd_ring = rfd_old;
387 adapter->rrd_ring = rrd_old;
388 adapter->tpd_ring = tpd_old;
389 adapter->ring_header = rhdr_old;
390 atl1_up(adapter);
391 return err;
392}
393
394static void atl1_get_pauseparam(struct net_device *netdev,
395 struct ethtool_pauseparam *epause)
396{
397 struct atl1_adapter *adapter = netdev_priv(netdev);
398 struct atl1_hw *hw = &adapter->hw;
399
400 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
401 hw->media_type == MEDIA_TYPE_1000M_FULL) {
402 epause->autoneg = AUTONEG_ENABLE;
403 } else {
404 epause->autoneg = AUTONEG_DISABLE;
405 }
406 epause->rx_pause = 1;
407 epause->tx_pause = 1;
408}
409
410static int atl1_set_pauseparam(struct net_device *netdev,
411 struct ethtool_pauseparam *epause)
412{
413 struct atl1_adapter *adapter = netdev_priv(netdev);
414 struct atl1_hw *hw = &adapter->hw;
415
416 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
417 hw->media_type == MEDIA_TYPE_1000M_FULL) {
418 epause->autoneg = AUTONEG_ENABLE;
419 } else {
420 epause->autoneg = AUTONEG_DISABLE;
421 }
422
423 epause->rx_pause = 1;
424 epause->tx_pause = 1;
425
426 return 0;
427}
428
429static u32 atl1_get_rx_csum(struct net_device *netdev)
430{
431 return 1;
432}
433
434static void atl1_get_strings(struct net_device *netdev, u32 stringset,
435 u8 *data)
436{
437 u8 *p = data;
438 int i;
439
440 switch (stringset) {
441 case ETH_SS_STATS:
442 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
443 memcpy(p, atl1_gstrings_stats[i].stat_string,
444 ETH_GSTRING_LEN);
445 p += ETH_GSTRING_LEN;
446 }
447 break;
448 }
449}
450
451static int atl1_nway_reset(struct net_device *netdev)
452{
453 struct atl1_adapter *adapter = netdev_priv(netdev);
454 struct atl1_hw *hw = &adapter->hw;
455
456 if (netif_running(netdev)) {
457 u16 phy_data;
458 atl1_down(adapter);
459
460 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
461 hw->media_type == MEDIA_TYPE_1000M_FULL) {
462 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
463 } else {
464 switch (hw->media_type) {
465 case MEDIA_TYPE_100M_FULL:
466 phy_data = MII_CR_FULL_DUPLEX |
467 MII_CR_SPEED_100 | MII_CR_RESET;
468 break;
469 case MEDIA_TYPE_100M_HALF:
470 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
471 break;
472 case MEDIA_TYPE_10M_FULL:
473 phy_data = MII_CR_FULL_DUPLEX |
474 MII_CR_SPEED_10 | MII_CR_RESET;
475 break;
476 default: /* MEDIA_TYPE_10M_HALF */
477 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
478 }
479 }
480 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
481 atl1_up(adapter);
482 }
483 return 0;
484}
485
486const struct ethtool_ops atl1_ethtool_ops = {
487 .get_settings = atl1_get_settings,
488 .set_settings = atl1_set_settings,
489 .get_drvinfo = atl1_get_drvinfo,
490 .get_wol = atl1_get_wol,
491 .set_wol = atl1_set_wol,
492 .get_ringparam = atl1_get_ringparam,
493 .set_ringparam = atl1_set_ringparam,
494 .get_pauseparam = atl1_get_pauseparam,
495 .set_pauseparam = atl1_set_pauseparam,
496 .get_rx_csum = atl1_get_rx_csum,
497 .set_tx_csum = ethtool_op_set_tx_hw_csum,
498 .get_link = ethtool_op_get_link,
499 .set_sg = ethtool_op_set_sg,
500 .get_strings = atl1_get_strings,
501 .nway_reset = atl1_nway_reset,
502 .get_ethtool_stats = atl1_get_ethtool_stats,
503 .get_sset_count = atl1_get_sset_count,
504 .set_tso = ethtool_op_set_tso,
505};
diff --git a/drivers/net/atlx/atl1_hw.c b/drivers/net/atlx/atl1_hw.c
deleted file mode 100644
index 9d3bd22e3a82..000000000000
--- a/drivers/net/atlx/atl1_hw.c
+++ /dev/null
@@ -1,720 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/if_vlan.h>
28#include <linux/etherdevice.h>
29#include <linux/crc32.h>
30#include <asm/byteorder.h>
31
32#include "atl1.h"
33
34/*
35 * Reset the transmit and receive units; mask and clear all interrupts.
36 * hw - Struct containing variables accessed by shared code
37 * return : ATL1_SUCCESS or idle status (if error)
38 */
39s32 atl1_reset_hw(struct atl1_hw *hw)
40{
41 struct pci_dev *pdev = hw->back->pdev;
42 u32 icr;
43 int i;
44
45 /*
46 * Clear Interrupt mask to stop board from generating
47 * interrupts & Clear any pending interrupt events
48 */
49 /*
50 * iowrite32(0, hw->hw_addr + REG_IMR);
51 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
52 */
53
54 /*
55 * Issue Soft Reset to the MAC. This will reset the chip's
56 * transmit, receive, DMA. It will not effect
57 * the current PCI configuration. The global reset bit is self-
58 * clearing, and should clear within a microsecond.
59 */
60 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
61 ioread32(hw->hw_addr + REG_MASTER_CTRL);
62
63 iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
64 ioread16(hw->hw_addr + REG_GPHY_ENABLE);
65
66 msleep(1); /* delay about 1ms */
67
68 /* Wait at least 10ms for All module to be Idle */
69 for (i = 0; i < 10; i++) {
70 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
71 if (!icr)
72 break;
73 msleep(1); /* delay 1 ms */
74 cpu_relax(); /* FIXME: is this still the right way to do this? */
75 }
76
77 if (icr) {
78 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
79 return icr;
80 }
81
82 return ATL1_SUCCESS;
83}
84
85/* function about EEPROM
86 *
87 * check_eeprom_exist
88 * return 0 if eeprom exist
89 */
90static int atl1_check_eeprom_exist(struct atl1_hw *hw)
91{
92 u32 value;
93 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
94 if (value & SPI_FLASH_CTRL_EN_VPD) {
95 value &= ~SPI_FLASH_CTRL_EN_VPD;
96 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
97 }
98
99 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
100 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
101}
102
103static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
104{
105 int i;
106 u32 control;
107
108 if (offset & 3)
109 return false; /* address do not align */
110
111 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
112 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
113 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
114 ioread32(hw->hw_addr + REG_VPD_CAP);
115
116 for (i = 0; i < 10; i++) {
117 msleep(2);
118 control = ioread32(hw->hw_addr + REG_VPD_CAP);
119 if (control & VPD_CAP_VPD_FLAG)
120 break;
121 }
122 if (control & VPD_CAP_VPD_FLAG) {
123 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
124 return true;
125 }
126 return false; /* timeout */
127}
128
129/*
130 * Reads the value from a PHY register
131 * hw - Struct containing variables accessed by shared code
132 * reg_addr - address of the PHY register to read
133 */
134s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
135{
136 u32 val;
137 int i;
138
139 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
140 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
141 MDIO_CLK_SEL_SHIFT;
142 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
143 ioread32(hw->hw_addr + REG_MDIO_CTRL);
144
145 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
146 udelay(2);
147 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
148 if (!(val & (MDIO_START | MDIO_BUSY)))
149 break;
150 }
151 if (!(val & (MDIO_START | MDIO_BUSY))) {
152 *phy_data = (u16) val;
153 return ATL1_SUCCESS;
154 }
155 return ATL1_ERR_PHY;
156}
157
158#define CUSTOM_SPI_CS_SETUP 2
159#define CUSTOM_SPI_CLK_HI 2
160#define CUSTOM_SPI_CLK_LO 2
161#define CUSTOM_SPI_CS_HOLD 2
162#define CUSTOM_SPI_CS_HI 3
163
164static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
165{
166 int i;
167 u32 value;
168
169 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
170 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
171
172 value = SPI_FLASH_CTRL_WAIT_READY |
173 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
174 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
175 SPI_FLASH_CTRL_CLK_HI_MASK) <<
176 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
177 SPI_FLASH_CTRL_CLK_LO_MASK) <<
178 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
179 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
180 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
181 SPI_FLASH_CTRL_CS_HI_MASK) <<
182 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
183 SPI_FLASH_CTRL_INS_SHIFT;
184
185 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
186
187 value |= SPI_FLASH_CTRL_START;
188 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
189 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
190
191 for (i = 0; i < 10; i++) {
192 msleep(1); /* 1ms */
193 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
194 if (!(value & SPI_FLASH_CTRL_START))
195 break;
196 }
197
198 if (value & SPI_FLASH_CTRL_START)
199 return false;
200
201 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
202
203 return true;
204}
205
206/*
207 * get_permanent_address
208 * return 0 if get valid mac address,
209 */
210static int atl1_get_permanent_address(struct atl1_hw *hw)
211{
212 u32 addr[2];
213 u32 i, control;
214 u16 reg;
215 u8 eth_addr[ETH_ALEN];
216 bool key_valid;
217
218 if (is_valid_ether_addr(hw->perm_mac_addr))
219 return 0;
220
221 /* init */
222 addr[0] = addr[1] = 0;
223
224 if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
225 reg = 0;
226 key_valid = false;
227 /* Read out all EEPROM content */
228 i = 0;
229 while (1) {
230 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
231 if (key_valid) {
232 if (reg == REG_MAC_STA_ADDR)
233 addr[0] = control;
234 else if (reg == (REG_MAC_STA_ADDR + 4))
235 addr[1] = control;
236 key_valid = false;
237 } else if ((control & 0xff) == 0x5A) {
238 key_valid = true;
239 reg = (u16) (control >> 16);
240 } else
241 break; /* assume data end while encount an invalid KEYWORD */
242 } else
243 break; /* read error */
244 i += 4;
245 }
246
247 *(u32 *) &eth_addr[2] = swab32(addr[0]);
248 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
249 if (is_valid_ether_addr(eth_addr)) {
250 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
251 return 0;
252 }
253 return 1;
254 }
255
256 /* see if SPI FLAGS exist ? */
257 addr[0] = addr[1] = 0;
258 reg = 0;
259 key_valid = false;
260 i = 0;
261 while (1) {
262 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
263 if (key_valid) {
264 if (reg == REG_MAC_STA_ADDR)
265 addr[0] = control;
266 else if (reg == (REG_MAC_STA_ADDR + 4))
267 addr[1] = control;
268 key_valid = false;
269 } else if ((control & 0xff) == 0x5A) {
270 key_valid = true;
271 reg = (u16) (control >> 16);
272 } else
273 break; /* data end */
274 } else
275 break; /* read error */
276 i += 4;
277 }
278
279 *(u32 *) &eth_addr[2] = swab32(addr[0]);
280 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
281 if (is_valid_ether_addr(eth_addr)) {
282 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
283 return 0;
284 }
285
286 /*
287 * On some motherboards, the MAC address is written by the
288 * BIOS directly to the MAC register during POST, and is
289 * not stored in eeprom. If all else thus far has failed
290 * to fetch the permanent MAC address, try reading it directly.
291 */
292 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
293 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
294 *(u32 *) &eth_addr[2] = swab32(addr[0]);
295 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
296 if (is_valid_ether_addr(eth_addr)) {
297 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
298 return 0;
299 }
300
301 return 1;
302}
303
304/*
305 * Reads the adapter's MAC address from the EEPROM
306 * hw - Struct containing variables accessed by shared code
307 */
308s32 atl1_read_mac_addr(struct atl1_hw *hw)
309{
310 u16 i;
311
312 if (atl1_get_permanent_address(hw))
313 random_ether_addr(hw->perm_mac_addr);
314
315 for (i = 0; i < ETH_ALEN; i++)
316 hw->mac_addr[i] = hw->perm_mac_addr[i];
317 return ATL1_SUCCESS;
318}
319
320/*
321 * Hashes an address to determine its location in the multicast table
322 * hw - Struct containing variables accessed by shared code
323 * mc_addr - the multicast address to hash
324 *
325 * atl1_hash_mc_addr
326 * purpose
327 * set hash value for a multicast address
328 * hash calcu processing :
329 * 1. calcu 32bit CRC for multicast address
330 * 2. reverse crc with MSB to LSB
331 */
332u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
333{
334 u32 crc32, value = 0;
335 int i;
336
337 crc32 = ether_crc_le(6, mc_addr);
338 for (i = 0; i < 32; i++)
339 value |= (((crc32 >> i) & 1) << (31 - i));
340
341 return value;
342}
343
344/*
345 * Sets the bit in the multicast table corresponding to the hash value.
346 * hw - Struct containing variables accessed by shared code
347 * hash_value - Multicast address hash value
348 */
349void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
350{
351 u32 hash_bit, hash_reg;
352 u32 mta;
353
354 /*
355 * The HASH Table is a register array of 2 32-bit registers.
356 * It is treated like an array of 64 bits. We want to set
357 * bit BitArray[hash_value]. So we figure out what register
358 * the bit is in, read it, OR in the new bit, then write
359 * back the new value. The register is determined by the
360 * upper 7 bits of the hash value and the bit within that
361 * register are determined by the lower 5 bits of the value.
362 */
363 hash_reg = (hash_value >> 31) & 0x1;
364 hash_bit = (hash_value >> 26) & 0x1F;
365 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
366 mta |= (1 << hash_bit);
367 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
368}
369
370/*
371 * Writes a value to a PHY register
372 * hw - Struct containing variables accessed by shared code
373 * reg_addr - address of the PHY register to write
374 * data - data to write to the PHY
375 */
376s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
377{
378 int i;
379 u32 val;
380
381 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
382 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
383 MDIO_SUP_PREAMBLE |
384 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
385 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
386 ioread32(hw->hw_addr + REG_MDIO_CTRL);
387
388 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
389 udelay(2);
390 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
391 if (!(val & (MDIO_START | MDIO_BUSY)))
392 break;
393 }
394
395 if (!(val & (MDIO_START | MDIO_BUSY)))
396 return ATL1_SUCCESS;
397
398 return ATL1_ERR_PHY;
399}
400
401/*
402 * Make L001's PHY out of Power Saving State (bug)
403 * hw - Struct containing variables accessed by shared code
404 * when power on, L001's PHY always on Power saving State
405 * (Gigabit Link forbidden)
406 */
407static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
408{
409 s32 ret;
410 ret = atl1_write_phy_reg(hw, 29, 0x0029);
411 if (ret)
412 return ret;
413 return atl1_write_phy_reg(hw, 30, 0);
414}
415
416/*
417 *TODO: do something or get rid of this
418 */
419s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
420{
421/* s32 ret_val;
422 * u16 phy_data;
423 */
424
425/*
426 ret_val = atl1_write_phy_reg(hw, ...);
427 ret_val = atl1_write_phy_reg(hw, ...);
428 ....
429*/
430 return ATL1_SUCCESS;
431}
432
433/*
434 * Resets the PHY and make all config validate
435 * hw - Struct containing variables accessed by shared code
436 *
437 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
438 */
439static s32 atl1_phy_reset(struct atl1_hw *hw)
440{
441 struct pci_dev *pdev = hw->back->pdev;
442 s32 ret_val;
443 u16 phy_data;
444
445 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
446 hw->media_type == MEDIA_TYPE_1000M_FULL)
447 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
448 else {
449 switch (hw->media_type) {
450 case MEDIA_TYPE_100M_FULL:
451 phy_data =
452 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
453 MII_CR_RESET;
454 break;
455 case MEDIA_TYPE_100M_HALF:
456 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
457 break;
458 case MEDIA_TYPE_10M_FULL:
459 phy_data =
460 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
461 break;
462 default: /* MEDIA_TYPE_10M_HALF: */
463 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
464 break;
465 }
466 }
467
468 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
469 if (ret_val) {
470 u32 val;
471 int i;
472 /* pcie serdes link may be down! */
473 dev_dbg(&pdev->dev, "pcie phy link down\n");
474
475 for (i = 0; i < 25; i++) {
476 msleep(1);
477 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
478 if (!(val & (MDIO_START | MDIO_BUSY)))
479 break;
480 }
481
482 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
483 dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
484 return ret_val;
485 }
486 }
487 return ATL1_SUCCESS;
488}
489
490/*
491 * Configures PHY autoneg and flow control advertisement settings
492 * hw - Struct containing variables accessed by shared code
493 */
494s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
495{
496 s32 ret_val;
497 s16 mii_autoneg_adv_reg;
498 s16 mii_1000t_ctrl_reg;
499
500 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
501 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
502
503 /* Read the MII 1000Base-T Control Register (Address 9). */
504 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
505
506 /*
507 * First we clear all the 10/100 mb speed bits in the Auto-Neg
508 * Advertisement Register (Address 4) and the 1000 mb speed bits in
509 * the 1000Base-T Control Register (Address 9).
510 */
511 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
512 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
513
514 /*
515 * Need to parse media_type and set up
516 * the appropriate PHY registers.
517 */
518 switch (hw->media_type) {
519 case MEDIA_TYPE_AUTO_SENSOR:
520 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
521 MII_AR_10T_FD_CAPS |
522 MII_AR_100TX_HD_CAPS |
523 MII_AR_100TX_FD_CAPS);
524 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
525 break;
526
527 case MEDIA_TYPE_1000M_FULL:
528 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
529 break;
530
531 case MEDIA_TYPE_100M_FULL:
532 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
533 break;
534
535 case MEDIA_TYPE_100M_HALF:
536 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
537 break;
538
539 case MEDIA_TYPE_10M_FULL:
540 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
541 break;
542
543 default:
544 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
545 break;
546 }
547
548 /* flow control fixed to enable all */
549 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
550
551 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
552 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
553
554 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
555 if (ret_val)
556 return ret_val;
557
558 ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
559 if (ret_val)
560 return ret_val;
561
562 return ATL1_SUCCESS;
563}
564
565/*
566 * Configures link settings.
567 * hw - Struct containing variables accessed by shared code
568 * Assumes the hardware has previously been reset and the
569 * transmitter and receiver are not enabled.
570 */
571static s32 atl1_setup_link(struct atl1_hw *hw)
572{
573 struct pci_dev *pdev = hw->back->pdev;
574 s32 ret_val;
575
576 /*
577 * Options:
578 * PHY will advertise value(s) parsed from
579 * autoneg_advertised and fc
580 * no matter what autoneg is , We will not wait link result.
581 */
582 ret_val = atl1_phy_setup_autoneg_adv(hw);
583 if (ret_val) {
584 dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
585 return ret_val;
586 }
587 /* SW.Reset , En-Auto-Neg if needed */
588 ret_val = atl1_phy_reset(hw);
589 if (ret_val) {
590 dev_dbg(&pdev->dev, "error resetting phy\n");
591 return ret_val;
592 }
593 hw->phy_configured = true;
594 return ret_val;
595}
596
597static struct atl1_spi_flash_dev flash_table[] = {
598/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
599 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
600 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
601 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
602};
603
604static void atl1_init_flash_opcode(struct atl1_hw *hw)
605{
606 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
607 hw->flash_vendor = 0; /* ATMEL */
608
609 /* Init OP table */
610 iowrite8(flash_table[hw->flash_vendor].cmd_program,
611 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
612 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
613 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
614 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
615 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
616 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
617 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
618 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
619 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
620 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
621 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
622 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
623 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
624 iowrite8(flash_table[hw->flash_vendor].cmd_read,
625 hw->hw_addr + REG_SPI_FLASH_OP_READ);
626}
627
628/*
629 * Performs basic configuration of the adapter.
630 * hw - Struct containing variables accessed by shared code
631 * Assumes that the controller has previously been reset and is in a
632 * post-reset uninitialized state. Initializes multicast table,
633 * and Calls routines to setup link
634 * Leaves the transmit and receive units disabled and uninitialized.
635 */
636s32 atl1_init_hw(struct atl1_hw *hw)
637{
638 u32 ret_val = 0;
639
640 /* Zero out the Multicast HASH table */
641 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
642 /* clear the old settings from the multicast hash table */
643 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
644
645 atl1_init_flash_opcode(hw);
646
647 if (!hw->phy_configured) {
648 /* enable GPHY LinkChange Interrrupt */
649 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
650 if (ret_val)
651 return ret_val;
652 /* make PHY out of power-saving state */
653 ret_val = atl1_phy_leave_power_saving(hw);
654 if (ret_val)
655 return ret_val;
656 /* Call a subroutine to configure the link */
657 ret_val = atl1_setup_link(hw);
658 }
659 return ret_val;
660}
661
662/*
663 * Detects the current speed and duplex settings of the hardware.
664 * hw - Struct containing variables accessed by shared code
665 * speed - Speed of the connection
666 * duplex - Duplex setting of the connection
667 */
668s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
669{
670 struct pci_dev *pdev = hw->back->pdev;
671 s32 ret_val;
672 u16 phy_data;
673
674 /* ; --- Read PHY Specific Status Register (17) */
675 ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
676 if (ret_val)
677 return ret_val;
678
679 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
680 return ATL1_ERR_PHY_RES;
681
682 switch (phy_data & MII_AT001_PSSR_SPEED) {
683 case MII_AT001_PSSR_1000MBS:
684 *speed = SPEED_1000;
685 break;
686 case MII_AT001_PSSR_100MBS:
687 *speed = SPEED_100;
688 break;
689 case MII_AT001_PSSR_10MBS:
690 *speed = SPEED_10;
691 break;
692 default:
693 dev_dbg(&pdev->dev, "error getting speed\n");
694 return ATL1_ERR_PHY_SPEED;
695 break;
696 }
697 if (phy_data & MII_AT001_PSSR_DPLX)
698 *duplex = FULL_DUPLEX;
699 else
700 *duplex = HALF_DUPLEX;
701
702 return ATL1_SUCCESS;
703}
704
705void atl1_set_mac_addr(struct atl1_hw *hw)
706{
707 u32 value;
708 /*
709 * 00-0B-6A-F6-00-DC
710 * 0: 6AF600DC 1: 000B
711 * low dword
712 */
713 value = (((u32) hw->mac_addr[2]) << 24) |
714 (((u32) hw->mac_addr[3]) << 16) |
715 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
716 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
717 /* high dword */
718 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
719 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
720}
diff --git a/drivers/net/atlx/atl1_hw.h b/drivers/net/atlx/atl1_hw.h
deleted file mode 100644
index 939aa0f53f6e..000000000000
--- a/drivers/net/atlx/atl1_hw.h
+++ /dev/null
@@ -1,946 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * There are a lot of defines in here that are unused and/or have cryptic
24 * names. Please leave them alone, as they're the closest thing we have
25 * to a spec from Attansic at present. *ahem* -- CHS
26 */
27
28#ifndef _ATL1_HW_H_
29#define _ATL1_HW_H_
30
31#include <linux/types.h>
32#include <linux/mii.h>
33
34struct atl1_adapter;
35struct atl1_hw;
36
37/* function prototypes needed by multiple files */
38s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
39s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
40s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
41s32 atl1_read_mac_addr(struct atl1_hw *hw);
42s32 atl1_init_hw(struct atl1_hw *hw);
43s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
44s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
45u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
46void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
47s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
48void atl1_set_mac_addr(struct atl1_hw *hw);
49s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
50s32 atl1_reset_hw(struct atl1_hw *hw);
51void atl1_check_options(struct atl1_adapter *adapter);
52
53/* register definitions */
54#define REG_PCIE_CAP_LIST 0x58
55
56#define REG_VPD_CAP 0x6C
57#define VPD_CAP_ID_MASK 0xff
58#define VPD_CAP_ID_SHIFT 0
59#define VPD_CAP_NEXT_PTR_MASK 0xFF
60#define VPD_CAP_NEXT_PTR_SHIFT 8
61#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
62#define VPD_CAP_VPD_ADDR_SHIFT 16
63#define VPD_CAP_VPD_FLAG 0x80000000
64
65#define REG_VPD_DATA 0x70
66
67#define REG_SPI_FLASH_CTRL 0x200
68#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
69#define SPI_FLASH_CTRL_STS_WEN 0x2
70#define SPI_FLASH_CTRL_STS_WPEN 0x80
71#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
72#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
73#define SPI_FLASH_CTRL_INS_MASK 0x7
74#define SPI_FLASH_CTRL_INS_SHIFT 8
75#define SPI_FLASH_CTRL_START 0x800
76#define SPI_FLASH_CTRL_EN_VPD 0x2000
77#define SPI_FLASH_CTRL_LDSTART 0x8000
78#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
79#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
80#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
81#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
82#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
83#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
84#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
85#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
86#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
87#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
88#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
89#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
90#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
91
92#define REG_SPI_ADDR 0x204
93
94#define REG_SPI_DATA 0x208
95
96#define REG_SPI_FLASH_CONFIG 0x20C
97#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
98#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
99#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
100#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
101#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
102
103#define REG_SPI_FLASH_OP_PROGRAM 0x210
104#define REG_SPI_FLASH_OP_SC_ERASE 0x211
105#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
106#define REG_SPI_FLASH_OP_RDID 0x213
107#define REG_SPI_FLASH_OP_WREN 0x214
108#define REG_SPI_FLASH_OP_RDSR 0x215
109#define REG_SPI_FLASH_OP_WRSR 0x216
110#define REG_SPI_FLASH_OP_READ 0x217
111
112#define REG_TWSI_CTRL 0x218
113#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
114#define TWSI_CTRL_LD_OFFSET_SHIFT 0
115#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
116#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
117#define TWSI_CTRL_SW_LDSTART 0x800
118#define TWSI_CTRL_HW_LDSTART 0x1000
119#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
120#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
121#define TWSI_CTRL_LD_EXIST 0x400000
122#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
123#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
124#define TWSI_CTRL_FREQ_SEL_100K 0
125#define TWSI_CTRL_FREQ_SEL_200K 1
126#define TWSI_CTRL_FREQ_SEL_300K 2
127#define TWSI_CTRL_FREQ_SEL_400K 3
128#define TWSI_CTRL_SMB_SLV_ADDR
129#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
130#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
131
132#define REG_PCIE_DEV_MISC_CTRL 0x21C
133#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
134#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
135#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
136#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
137#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
138
139/* Selene Master Control Register */
140#define REG_MASTER_CTRL 0x1400
141#define MASTER_CTRL_SOFT_RST 0x1
142#define MASTER_CTRL_MTIMER_EN 0x2
143#define MASTER_CTRL_ITIMER_EN 0x4
144#define MASTER_CTRL_MANUAL_INT 0x8
145#define MASTER_CTRL_REV_NUM_SHIFT 16
146#define MASTER_CTRL_REV_NUM_MASK 0xff
147#define MASTER_CTRL_DEV_ID_SHIFT 24
148#define MASTER_CTRL_DEV_ID_MASK 0xff
149
150/* Timer Initial Value Register */
151#define REG_MANUAL_TIMER_INIT 0x1404
152
153/* IRQ ModeratorTimer Initial Value Register */
154#define REG_IRQ_MODU_TIMER_INIT 0x1408
155
156#define REG_GPHY_ENABLE 0x140C
157
158/* IRQ Anti-Lost Timer Initial Value Register */
159#define REG_CMBDISDMA_TIMER 0x140E
160
161/* Block IDLE Status Register */
162#define REG_IDLE_STATUS 0x1410
163#define IDLE_STATUS_RXMAC 1
164#define IDLE_STATUS_TXMAC 2
165#define IDLE_STATUS_RXQ 4
166#define IDLE_STATUS_TXQ 8
167#define IDLE_STATUS_DMAR 0x10
168#define IDLE_STATUS_DMAW 0x20
169#define IDLE_STATUS_SMB 0x40
170#define IDLE_STATUS_CMB 0x80
171
172/* MDIO Control Register */
173#define REG_MDIO_CTRL 0x1414
174#define MDIO_DATA_MASK 0xffff
175#define MDIO_DATA_SHIFT 0
176#define MDIO_REG_ADDR_MASK 0x1f
177#define MDIO_REG_ADDR_SHIFT 16
178#define MDIO_RW 0x200000
179#define MDIO_SUP_PREAMBLE 0x400000
180#define MDIO_START 0x800000
181#define MDIO_CLK_SEL_SHIFT 24
182#define MDIO_CLK_25_4 0
183#define MDIO_CLK_25_6 2
184#define MDIO_CLK_25_8 3
185#define MDIO_CLK_25_10 4
186#define MDIO_CLK_25_14 5
187#define MDIO_CLK_25_20 6
188#define MDIO_CLK_25_28 7
189#define MDIO_BUSY 0x8000000
190#define MDIO_WAIT_TIMES 30
191
192/* MII PHY Status Register */
193#define REG_PHY_STATUS 0x1418
194
195/* BIST Control and Status Register0 (for the Packet Memory) */
196#define REG_BIST0_CTRL 0x141c
197#define BIST0_NOW 0x1
198#define BIST0_SRAM_FAIL 0x2
199#define BIST0_FUSE_FLAG 0x4
200#define REG_BIST1_CTRL 0x1420
201#define BIST1_NOW 0x1
202#define BIST1_SRAM_FAIL 0x2
203#define BIST1_FUSE_FLAG 0x4
204
205/* MAC Control Register */
206#define REG_MAC_CTRL 0x1480
207#define MAC_CTRL_TX_EN 1
208#define MAC_CTRL_RX_EN 2
209#define MAC_CTRL_TX_FLOW 4
210#define MAC_CTRL_RX_FLOW 8
211#define MAC_CTRL_LOOPBACK 0x10
212#define MAC_CTRL_DUPLX 0x20
213#define MAC_CTRL_ADD_CRC 0x40
214#define MAC_CTRL_PAD 0x80
215#define MAC_CTRL_LENCHK 0x100
216#define MAC_CTRL_HUGE_EN 0x200
217#define MAC_CTRL_PRMLEN_SHIFT 10
218#define MAC_CTRL_PRMLEN_MASK 0xf
219#define MAC_CTRL_RMV_VLAN 0x4000
220#define MAC_CTRL_PROMIS_EN 0x8000
221#define MAC_CTRL_TX_PAUSE 0x10000
222#define MAC_CTRL_SCNT 0x20000
223#define MAC_CTRL_SRST_TX 0x40000
224#define MAC_CTRL_TX_SIMURST 0x80000
225#define MAC_CTRL_SPEED_SHIFT 20
226#define MAC_CTRL_SPEED_MASK 0x300000
227#define MAC_CTRL_SPEED_1000 2
228#define MAC_CTRL_SPEED_10_100 1
229#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
230#define MAC_CTRL_TX_HUGE 0x800000
231#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
232#define MAC_CTRL_MC_ALL_EN 0x2000000
233#define MAC_CTRL_BC_EN 0x4000000
234#define MAC_CTRL_DBG 0x8000000
235
236/* MAC IPG/IFG Control Register */
237#define REG_MAC_IPG_IFG 0x1484
238#define MAC_IPG_IFG_IPGT_SHIFT 0
239#define MAC_IPG_IFG_IPGT_MASK 0x7f
240#define MAC_IPG_IFG_MIFG_SHIFT 8
241#define MAC_IPG_IFG_MIFG_MASK 0xff
242#define MAC_IPG_IFG_IPGR1_SHIFT 16
243#define MAC_IPG_IFG_IPGR1_MASK 0x7f
244#define MAC_IPG_IFG_IPGR2_SHIFT 24
245#define MAC_IPG_IFG_IPGR2_MASK 0x7f
246
247/* MAC STATION ADDRESS */
248#define REG_MAC_STA_ADDR 0x1488
249
250/* Hash table for multicast address */
251#define REG_RX_HASH_TABLE 0x1490
252
253/* MAC Half-Duplex Control Register */
254#define REG_MAC_HALF_DUPLX_CTRL 0x1498
255#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
256#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
257#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
258#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
259#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
260#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
261#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
262#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
263#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
264#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
265#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
266#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
267
268/* Maximum Frame Length Control Register */
269#define REG_MTU 0x149c
270
271/* Wake-On-Lan control register */
272#define REG_WOL_CTRL 0x14a0
273#define WOL_PATTERN_EN 0x00000001
274#define WOL_PATTERN_PME_EN 0x00000002
275#define WOL_MAGIC_EN 0x00000004
276#define WOL_MAGIC_PME_EN 0x00000008
277#define WOL_LINK_CHG_EN 0x00000010
278#define WOL_LINK_CHG_PME_EN 0x00000020
279#define WOL_PATTERN_ST 0x00000100
280#define WOL_MAGIC_ST 0x00000200
281#define WOL_LINKCHG_ST 0x00000400
282#define WOL_CLK_SWITCH_EN 0x00008000
283#define WOL_PT0_EN 0x00010000
284#define WOL_PT1_EN 0x00020000
285#define WOL_PT2_EN 0x00040000
286#define WOL_PT3_EN 0x00080000
287#define WOL_PT4_EN 0x00100000
288#define WOL_PT5_EN 0x00200000
289#define WOL_PT6_EN 0x00400000
290
291/* WOL Length ( 2 DWORD ) */
292#define REG_WOL_PATTERN_LEN 0x14a4
293#define WOL_PT_LEN_MASK 0x7f
294#define WOL_PT0_LEN_SHIFT 0
295#define WOL_PT1_LEN_SHIFT 8
296#define WOL_PT2_LEN_SHIFT 16
297#define WOL_PT3_LEN_SHIFT 24
298#define WOL_PT4_LEN_SHIFT 0
299#define WOL_PT5_LEN_SHIFT 8
300#define WOL_PT6_LEN_SHIFT 16
301
302/* Internal SRAM Partition Register */
303#define REG_SRAM_RFD_ADDR 0x1500
304#define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
305#define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
306#define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
307#define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
308#define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
309#define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
310#define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
311#define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
312#define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
313#define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
314#define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
315#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
316#define SRAM_TCPH_ADDR_MASK 0x0fff
317#define SRAM_TCPH_ADDR_SHIFT 0
318#define SRAM_PATH_ADDR_MASK 0x0fff
319#define SRAM_PATH_ADDR_SHIFT 16
320
321/* Load Ptr Register */
322#define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
323
324/* Descriptor Control register */
325#define REG_DESC_BASE_ADDR_HI 0x1540
326#define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
327#define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
328#define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
329#define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
330#define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
331#define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
332#define DESC_RFD_RING_SIZE_MASK 0x7ff
333#define DESC_RFD_RING_SIZE_SHIFT 0
334#define DESC_RRD_RING_SIZE_MASK 0x7ff
335#define DESC_RRD_RING_SIZE_SHIFT 16
336#define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
337#define DESC_TPD_RING_SIZE_MASK 0x3ff
338#define DESC_TPD_RING_SIZE_SHIFT 0
339
340/* TXQ Control Register */
341#define REG_TXQ_CTRL 0x1580
342#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
343#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
344#define TXQ_CTRL_EN 0x20
345#define TXQ_CTRL_ENH_MODE 0x40
346#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
347#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
348#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
349#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
350
351/* Jumbo packet Threshold for task offload */
352#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
353#define TX_JUMBO_TASK_TH_MASK 0x7ff
354#define TX_JUMBO_TASK_TH_SHIFT 0
355#define TX_TPD_MIN_IPG_MASK 0x1f
356#define TX_TPD_MIN_IPG_SHIFT 16
357
358/* RXQ Control Register */
359#define REG_RXQ_CTRL 0x15a0
360#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
361#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
362#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
363#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
364#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
365#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
366#define RXQ_CTRL_CUT_THRU_EN 0x40000000
367#define RXQ_CTRL_EN 0x80000000
368
369/* Rx jumbo packet threshold and rrd retirement timer */
370#define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
371#define RXQ_JMBOSZ_TH_MASK 0x7ff
372#define RXQ_JMBOSZ_TH_SHIFT 0
373#define RXQ_JMBO_LKAH_MASK 0xf
374#define RXQ_JMBO_LKAH_SHIFT 11
375#define RXQ_RRD_TIMER_MASK 0xffff
376#define RXQ_RRD_TIMER_SHIFT 16
377
378/* RFD flow control register */
379#define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
380#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
381#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
382#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
383#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
384
385/* RRD flow control register */
386#define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
387#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
388#define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
389#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
390#define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
391
392/* DMA Engine Control Register */
393#define REG_DMA_CTRL 0x15c0
394#define DMA_CTRL_DMAR_IN_ORDER 0x1
395#define DMA_CTRL_DMAR_ENH_ORDER 0x2
396#define DMA_CTRL_DMAR_OUT_ORDER 0x4
397#define DMA_CTRL_RCB_VALUE 0x8
398#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
399#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
400#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
401#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
402#define DMA_CTRL_DMAR_EN 0x400
403#define DMA_CTRL_DMAW_EN 0x800
404
405/* CMB/SMB Control Register */
406#define REG_CSMB_CTRL 0x15d0
407#define CSMB_CTRL_CMB_NOW 1
408#define CSMB_CTRL_SMB_NOW 2
409#define CSMB_CTRL_CMB_EN 4
410#define CSMB_CTRL_SMB_EN 8
411
412/* CMB DMA Write Threshold Register */
413#define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
414#define CMB_RRD_TH_SHIFT 0
415#define CMB_RRD_TH_MASK 0x7ff
416#define CMB_TPD_TH_SHIFT 16
417#define CMB_TPD_TH_MASK 0x7ff
418
419/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
420#define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
421#define CMB_RX_TM_SHIFT 0
422#define CMB_RX_TM_MASK 0xffff
423#define CMB_TX_TM_SHIFT 16
424#define CMB_TX_TM_MASK 0xffff
425
426/* Number of packet received since last CMB write */
427#define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
428
429/* Number of packet transmitted since last CMB write */
430#define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
431
432/* SMB auto DMA timer register */
433#define REG_SMB_TIMER (REG_CSMB_CTRL+20)
434
435/* Mailbox Register */
436#define REG_MAILBOX 0x15f0
437#define MB_RFD_PROD_INDX_SHIFT 0
438#define MB_RFD_PROD_INDX_MASK 0x7ff
439#define MB_RRD_CONS_INDX_SHIFT 11
440#define MB_RRD_CONS_INDX_MASK 0x7ff
441#define MB_TPD_PROD_INDX_SHIFT 22
442#define MB_TPD_PROD_INDX_MASK 0x3ff
443
444/* Interrupt Status Register */
445#define REG_ISR 0x1600
446#define ISR_SMB 1
447#define ISR_TIMER 2
448#define ISR_MANUAL 4
449#define ISR_RXF_OV 8
450#define ISR_RFD_UNRUN 0x10
451#define ISR_RRD_OV 0x20
452#define ISR_TXF_UNRUN 0x40
453#define ISR_LINK 0x80
454#define ISR_HOST_RFD_UNRUN 0x100
455#define ISR_HOST_RRD_OV 0x200
456#define ISR_DMAR_TO_RST 0x400
457#define ISR_DMAW_TO_RST 0x800
458#define ISR_GPHY 0x1000
459#define ISR_RX_PKT 0x10000
460#define ISR_TX_PKT 0x20000
461#define ISR_TX_DMA 0x40000
462#define ISR_RX_DMA 0x80000
463#define ISR_CMB_RX 0x100000
464#define ISR_CMB_TX 0x200000
465#define ISR_MAC_RX 0x400000
466#define ISR_MAC_TX 0x800000
467#define ISR_UR_DETECTED 0x1000000
468#define ISR_FERR_DETECTED 0x2000000
469#define ISR_NFERR_DETECTED 0x4000000
470#define ISR_CERR_DETECTED 0x8000000
471#define ISR_PHY_LINKDOWN 0x10000000
472#define ISR_DIS_SMB 0x20000000
473#define ISR_DIS_DMA 0x40000000
474#define ISR_DIS_INT 0x80000000
475
476/* Interrupt Mask Register */
477#define REG_IMR 0x1604
478
479/* Normal Interrupt mask */
480#define IMR_NORMAL_MASK (\
481 ISR_SMB |\
482 ISR_GPHY |\
483 ISR_PHY_LINKDOWN|\
484 ISR_DMAR_TO_RST |\
485 ISR_DMAW_TO_RST |\
486 ISR_CMB_TX |\
487 ISR_CMB_RX )
488
489/* Debug Interrupt Mask (enable all interrupt) */
490#define IMR_DEBUG_MASK (\
491 ISR_SMB |\
492 ISR_TIMER |\
493 ISR_MANUAL |\
494 ISR_RXF_OV |\
495 ISR_RFD_UNRUN |\
496 ISR_RRD_OV |\
497 ISR_TXF_UNRUN |\
498 ISR_LINK |\
499 ISR_CMB_TX |\
500 ISR_CMB_RX |\
501 ISR_RX_PKT |\
502 ISR_TX_PKT |\
503 ISR_MAC_RX |\
504 ISR_MAC_TX )
505
506/* Interrupt Status Register */
507#define REG_RFD_RRD_IDX 0x1800
508#define REG_TPD_IDX 0x1804
509
510/* MII definition */
511/* PHY Common Register */
512#define MII_AT001_CR 0x09
513#define MII_AT001_SR 0x0A
514#define MII_AT001_ESR 0x0F
515#define MII_AT001_PSCR 0x10
516#define MII_AT001_PSSR 0x11
517
518/* PHY Control Register */
519#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
520#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
521#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
522#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
523#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
524#define MII_CR_POWER_DOWN 0x0800 /* Power down */
525#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
526#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
527#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
528#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
529#define MII_CR_SPEED_MASK 0x2040
530#define MII_CR_SPEED_1000 0x0040
531#define MII_CR_SPEED_100 0x2000
532#define MII_CR_SPEED_10 0x0000
533
534/* PHY Status Register */
535#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
536#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
537#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
538#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
539#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
540#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
541#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
542#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
543#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
544#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
545#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
546#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
547#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
548#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
549#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
550
551/* Link partner ability register. */
552#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
553#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
554#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
555#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
556#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
557#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
558#define MII_LPA_PAUSE 0x0400 /* PAUSE */
559#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
560#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
561#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
562#define MII_LPA_NPAGE 0x8000 /* Next page bit */
563
564/* Autoneg Advertisement Register */
565#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
566#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
567#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
568#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
569#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
570#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
571#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
572#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
573#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
574#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
575#define MII_AR_SPEED_MASK 0x01E0
576#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
577
578/* 1000BASE-T Control Register */
579#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
580#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
581#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */
582#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */
583#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
584#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
585#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
586#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
587#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
588#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
589#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
590#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
591
592/* 1000BASE-T Status Register */
593#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
594#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
595#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
596#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
597#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
598#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
599#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
600#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
601
602/* Extended Status Register */
603#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
604#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
605#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
606#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
607
608/* AT001 PHY Specific Control Register */
609#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
610#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
611#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
612#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
613#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */
614#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */
615#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
616#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
617#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */
618#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
619#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
620#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
621#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
622#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
623#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
624#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
625#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
626
627/* AT001 PHY Specific Status Register */
628#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
629#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
630#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
631#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
632#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
633#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
634
635/* PCI Command Register Bit Definitions */
636#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
637#define CMD_IO_SPACE 0x0001
638#define CMD_MEMORY_SPACE 0x0002
639#define CMD_BUS_MASTER 0x0004
640
641/* Wake Up Filter Control */
642#define ATL1_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
643#define ATL1_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
644#define ATL1_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
645#define ATL1_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
646#define ATL1_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
647
648/* Error Codes */
649#define ATL1_SUCCESS 0
650#define ATL1_ERR_EEPROM 1
651#define ATL1_ERR_PHY 2
652#define ATL1_ERR_CONFIG 3
653#define ATL1_ERR_PARAM 4
654#define ATL1_ERR_MAC_TYPE 5
655#define ATL1_ERR_PHY_TYPE 6
656#define ATL1_ERR_PHY_SPEED 7
657#define ATL1_ERR_PHY_RES 8
658
659#define SPEED_0 0xffff
660#define SPEED_10 10
661#define SPEED_100 100
662#define SPEED_1000 1000
663#define HALF_DUPLEX 1
664#define FULL_DUPLEX 2
665
666#define MEDIA_TYPE_AUTO_SENSOR 0
667#define MEDIA_TYPE_1000M_FULL 1
668#define MEDIA_TYPE_100M_FULL 2
669#define MEDIA_TYPE_100M_HALF 3
670#define MEDIA_TYPE_10M_FULL 4
671#define MEDIA_TYPE_10M_HALF 5
672
673#define ADVERTISE_10_HALF 0x0001
674#define ADVERTISE_10_FULL 0x0002
675#define ADVERTISE_100_HALF 0x0004
676#define ADVERTISE_100_FULL 0x0008
677#define ADVERTISE_1000_HALF 0x0010
678#define ADVERTISE_1000_FULL 0x0020
679#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
680#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
681#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
682
683#define MAX_JUMBO_FRAME_SIZE 0x2800
684
685#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
686#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
687
688/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
689#define EEPROM_SUM 0xBABA
690
691#define ATL1_EEDUMP_LEN 48
692
693/* Statistics counters collected by the MAC */
694struct stats_msg_block {
695 /* rx */
696 u32 rx_ok; /* The number of good packet received. */
697 u32 rx_bcast; /* The number of good broadcast packet received. */
698 u32 rx_mcast; /* The number of good multicast packet received. */
699 u32 rx_pause; /* The number of Pause packet received. */
700 u32 rx_ctrl; /* The number of Control packet received other than Pause frame. */
701 u32 rx_fcs_err; /* The number of packets with bad FCS. */
702 u32 rx_len_err; /* The number of packets with mismatch of length field and actual size. */
703 u32 rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
704 u32 rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
705 u32 rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
706 u32 rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
707 u32 rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
708 u32 rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
709 u32 rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
710 u32 rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
711 u32 rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
712 u32 rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
713 u32 rx_sz_ov; /* The number of good and bad packets received that are more than MTU size šC truncated by Selene. */
714 u32 rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
715 u32 rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
716 u32 rx_align_err; /* Alignment Error */
717 u32 rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
718 u32 rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
719 u32 rx_err_addr; /* The number of packets dropped due to address filtering. */
720
721 /* tx */
722 u32 tx_ok; /* The number of good packet transmitted. */
723 u32 tx_bcast; /* The number of good broadcast packet transmitted. */
724 u32 tx_mcast; /* The number of good multicast packet transmitted. */
725 u32 tx_pause; /* The number of Pause packet transmitted. */
726 u32 tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
727 u32 tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
728 u32 tx_defer; /* The number of packets transmitted that is deferred. */
729 u32 tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
730 u32 tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
731 u32 tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
732 u32 tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
733 u32 tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
734 u32 tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
735 u32 tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
736 u32 tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
737 u32 tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
738 u32 tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
739 u32 tx_late_col; /* The number of packets transmitted with late collisions. */
740 u32 tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
741 u32 tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
742 u32 tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
743 u32 tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
744 u32 tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
745 u32 tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
746 u32 tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
747 u32 smb_updated; /* 1: SMB Updated. This is used by software as the indication of the statistics update.
748 * Software should clear this bit as soon as retrieving the statistics information. */
749};
750
751/* Coalescing Message Block */
752struct coals_msg_block {
753 u32 int_stats; /* interrupt status */
754 u16 rrd_prod_idx; /* TRD Producer Index. */
755 u16 rfd_cons_idx; /* RFD Consumer Index. */
756 u16 update; /* Selene sets this bit every time it DMA the CMB to host memory.
757 * Software supposes to clear this bit when CMB information is processed. */
758 u16 tpd_cons_idx; /* TPD Consumer Index. */
759};
760
761/* RRD descriptor */
762struct rx_return_desc {
763 u8 num_buf; /* Number of RFD buffers used by the received packet */
764 u8 resved;
765 u16 buf_indx; /* RFD Index of the first buffer */
766 union {
767 u32 valid;
768 struct {
769 u16 rx_chksum;
770 u16 pkt_size;
771 } xsum_sz;
772 } xsz;
773
774 u16 pkt_flg; /* Packet flags */
775 u16 err_flg; /* Error flags */
776 u16 resved2;
777 u16 vlan_tag; /* VLAN TAG */
778};
779
780#define PACKET_FLAG_ETH_TYPE 0x0080
781#define PACKET_FLAG_VLAN_INS 0x0100
782#define PACKET_FLAG_ERR 0x0200
783#define PACKET_FLAG_IPV4 0x0400
784#define PACKET_FLAG_UDP 0x0800
785#define PACKET_FLAG_TCP 0x1000
786#define PACKET_FLAG_BCAST 0x2000
787#define PACKET_FLAG_MCAST 0x4000
788#define PACKET_FLAG_PAUSE 0x8000
789
790#define ERR_FLAG_CRC 0x0001
791#define ERR_FLAG_CODE 0x0002
792#define ERR_FLAG_DRIBBLE 0x0004
793#define ERR_FLAG_RUNT 0x0008
794#define ERR_FLAG_OV 0x0010
795#define ERR_FLAG_TRUNC 0x0020
796#define ERR_FLAG_IP_CHKSUM 0x0040
797#define ERR_FLAG_L4_CHKSUM 0x0080
798#define ERR_FLAG_LEN 0x0100
799#define ERR_FLAG_DES_ADDR 0x0200
800
801/* RFD descriptor */
802struct rx_free_desc {
803 __le64 buffer_addr; /* Address of the descriptor's data buffer */
804 __le16 buf_len; /* Size of the receive buffer in host memory, in byte */
805 u16 coalese; /* Update consumer index to host after the reception of this frame */
806 /* __attribute__ ((packed)) is required */
807} __attribute__ ((packed));
808
809/* tsopu defines */
810#define TSO_PARAM_BUFLEN_MASK 0x3FFF
811#define TSO_PARAM_BUFLEN_SHIFT 0
812#define TSO_PARAM_DMAINT_MASK 0x0001
813#define TSO_PARAM_DMAINT_SHIFT 14
814#define TSO_PARAM_PKTNT_MASK 0x0001
815#define TSO_PARAM_PKTINT_SHIFT 15
816#define TSO_PARAM_VLANTAG_MASK 0xFFFF
817#define TSO_PARAM_VLAN_SHIFT 16
818
819/* tsopl defines */
820#define TSO_PARAM_EOP_MASK 0x0001
821#define TSO_PARAM_EOP_SHIFT 0
822#define TSO_PARAM_COALESCE_MASK 0x0001
823#define TSO_PARAM_COALESCE_SHIFT 1
824#define TSO_PARAM_INSVLAG_MASK 0x0001
825#define TSO_PARAM_INSVLAG_SHIFT 2
826#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
827#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
828#define TSO_PARAM_SEGMENT_MASK 0x0001
829#define TSO_PARAM_SEGMENT_SHIFT 4
830#define TSO_PARAM_IPCKSUM_MASK 0x0001
831#define TSO_PARAM_IPCKSUM_SHIFT 5
832#define TSO_PARAM_TCPCKSUM_MASK 0x0001
833#define TSO_PARAM_TCPCKSUM_SHIFT 6
834#define TSO_PARAM_UDPCKSUM_MASK 0x0001
835#define TSO_PARAM_UDPCKSUM_SHIFT 7
836#define TSO_PARAM_VLANTAGGED_MASK 0x0001
837#define TSO_PARAM_VLANTAGGED_SHIFT 8
838#define TSO_PARAM_ETHTYPE_MASK 0x0001
839#define TSO_PARAM_ETHTYPE_SHIFT 9
840#define TSO_PARAM_IPHL_MASK 0x000F
841#define TSO_PARAM_IPHL_SHIFT 10
842#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
843#define TSO_PARAM_TCPHDRLEN_SHIFT 14
844#define TSO_PARAM_HDRFLAG_MASK 0x0001
845#define TSO_PARAM_HDRFLAG_SHIFT 18
846#define TSO_PARAM_MSS_MASK 0x1FFF
847#define TSO_PARAM_MSS_SHIFT 19
848
849/* csumpu defines */
850#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
851#define CSUM_PARAM_BUFLEN_SHIFT 0
852#define CSUM_PARAM_DMAINT_MASK 0x0001
853#define CSUM_PARAM_DMAINT_SHIFT 14
854#define CSUM_PARAM_PKTINT_MASK 0x0001
855#define CSUM_PARAM_PKTINT_SHIFT 15
856#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
857#define CSUM_PARAM_VALAN_SHIFT 16
858
859/* csumpl defines*/
860#define CSUM_PARAM_EOP_MASK 0x0001
861#define CSUM_PARAM_EOP_SHIFT 0
862#define CSUM_PARAM_COALESCE_MASK 0x0001
863#define CSUM_PARAM_COALESCE_SHIFT 1
864#define CSUM_PARAM_INSVLAG_MASK 0x0001
865#define CSUM_PARAM_INSVLAG_SHIFT 2
866#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
867#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
868#define CSUM_PARAM_SEGMENT_MASK 0x0001
869#define CSUM_PARAM_SEGMENT_SHIFT 4
870#define CSUM_PARAM_IPCKSUM_MASK 0x0001
871#define CSUM_PARAM_IPCKSUM_SHIFT 5
872#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
873#define CSUM_PARAM_TCPCKSUM_SHIFT 6
874#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
875#define CSUM_PARAM_UDPCKSUM_SHIFT 7
876#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
877#define CSUM_PARAM_VLANTAGGED_SHIFT 8
878#define CSUM_PARAM_ETHTYPE_MASK 0x0001
879#define CSUM_PARAM_ETHTYPE_SHIFT 9
880#define CSUM_PARAM_IPHL_MASK 0x000F
881#define CSUM_PARAM_IPHL_SHIFT 10
882#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
883#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
884#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
885#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
886
887/* TPD descriptor */
888struct tso_param {
889 /* The order of these declarations is important -- don't change it */
890 u32 tsopu; /* tso_param upper word */
891 u32 tsopl; /* tso_param lower word */
892};
893
894struct csum_param {
895 /* The order of these declarations is important -- don't change it */
896 u32 csumpu; /* csum_param upper word */
897 u32 csumpl; /* csum_param lower word */
898};
899
900union tpd_descr {
901 u64 data;
902 struct csum_param csum;
903 struct tso_param tso;
904};
905
906struct tx_packet_desc {
907 __le64 buffer_addr;
908 union tpd_descr desc;
909};
910
911/* DMA Order Settings */
912enum atl1_dma_order {
913 atl1_dma_ord_in = 1,
914 atl1_dma_ord_enh = 2,
915 atl1_dma_ord_out = 4
916};
917
918enum atl1_dma_rcb {
919 atl1_rcb_64 = 0,
920 atl1_rcb_128 = 1
921};
922
923enum atl1_dma_req_block {
924 atl1_dma_req_128 = 0,
925 atl1_dma_req_256 = 1,
926 atl1_dma_req_512 = 2,
927 atl1_dma_req_1024 = 3,
928 atl1_dma_req_2048 = 4,
929 atl1_dma_req_4096 = 5
930};
931
932struct atl1_spi_flash_dev {
933 const char *manu_name; /* manufacturer id */
934 /* op-code */
935 u8 cmd_wrsr;
936 u8 cmd_read;
937 u8 cmd_program;
938 u8 cmd_wren;
939 u8 cmd_wrdi;
940 u8 cmd_rdsr;
941 u8 cmd_rdid;
942 u8 cmd_sector_erase;
943 u8 cmd_chip_erase;
944};
945
946#endif /* _ATL1_HW_H_ */
diff --git a/drivers/net/atlx/atl1_param.c b/drivers/net/atlx/atl1_param.c
deleted file mode 100644
index 4246bb9bd50e..000000000000
--- a/drivers/net/atlx/atl1_param.c
+++ /dev/null
@@ -1,203 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include "atl1.h"
28
29/*
30 * This is the only thing that needs to be changed to adjust the
31 * maximum number of ports that the driver can manage.
32 */
33#define ATL1_MAX_NIC 4
34
35#define OPTION_UNSET -1
36#define OPTION_DISABLED 0
37#define OPTION_ENABLED 1
38
39#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
40
41/*
42 * Interrupt Moderate Timer in units of 2 us
43 *
44 * Valid Range: 10-65535
45 *
46 * Default Value: 100 (200us)
47 */
48static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
49static int num_int_mod_timer = 0;
50module_param_array_named(int_mod_timer, int_mod_timer, int, &num_int_mod_timer, 0);
51MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
52
53/*
54 * flash_vendor
55 *
56 * Valid Range: 0-2
57 *
58 * 0 - Atmel
59 * 1 - SST
60 * 2 - ST
61 *
62 * Default Value: 0
63 */
64static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
65static int num_flash_vendor = 0;
66module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
67MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
68
69#define DEFAULT_INT_MOD_CNT 100 /* 200us */
70#define MAX_INT_MOD_CNT 65000
71#define MIN_INT_MOD_CNT 50
72
73#define FLASH_VENDOR_DEFAULT 0
74#define FLASH_VENDOR_MIN 0
75#define FLASH_VENDOR_MAX 2
76
77struct atl1_option {
78 enum { enable_option, range_option, list_option } type;
79 char *name;
80 char *err;
81 int def;
82 union {
83 struct { /* range_option info */
84 int min;
85 int max;
86 } r;
87 struct { /* list_option info */
88 int nr;
89 struct atl1_opt_list {
90 int i;
91 char *str;
92 } *p;
93 } l;
94 } arg;
95};
96
97static int __devinit atl1_validate_option(int *value, struct atl1_option *opt, struct pci_dev *pdev)
98{
99 if (*value == OPTION_UNSET) {
100 *value = opt->def;
101 return 0;
102 }
103
104 switch (opt->type) {
105 case enable_option:
106 switch (*value) {
107 case OPTION_ENABLED:
108 dev_info(&pdev->dev, "%s enabled\n", opt->name);
109 return 0;
110 case OPTION_DISABLED:
111 dev_info(&pdev->dev, "%s disabled\n", opt->name);
112 return 0;
113 }
114 break;
115 case range_option:
116 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
117 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
118 *value);
119 return 0;
120 }
121 break;
122 case list_option:{
123 int i;
124 struct atl1_opt_list *ent;
125
126 for (i = 0; i < opt->arg.l.nr; i++) {
127 ent = &opt->arg.l.p[i];
128 if (*value == ent->i) {
129 if (ent->str[0] != '\0')
130 dev_info(&pdev->dev, "%s\n",
131 ent->str);
132 return 0;
133 }
134 }
135 }
136 break;
137
138 default:
139 break;
140 }
141
142 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
143 opt->name, *value, opt->err);
144 *value = opt->def;
145 return -1;
146}
147
148/*
149 * atl1_check_options - Range Checking for Command Line Parameters
150 * @adapter: board private structure
151 *
152 * This routine checks all command line parameters for valid user
153 * input. If an invalid value is given, or if no user specified
154 * value exists, a default value is used. The final value is stored
155 * in a variable in the adapter structure.
156 */
157void __devinit atl1_check_options(struct atl1_adapter *adapter)
158{
159 struct pci_dev *pdev = adapter->pdev;
160 int bd = adapter->bd_number;
161 if (bd >= ATL1_MAX_NIC) {
162 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
163 dev_notice(&pdev->dev, "using defaults for all values\n");
164 }
165 { /* Interrupt Moderate Timer */
166 struct atl1_option opt = {
167 .type = range_option,
168 .name = "Interrupt Moderator Timer",
169 .err = "using default of "
170 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
171 .def = DEFAULT_INT_MOD_CNT,
172 .arg = {.r =
173 {.min = MIN_INT_MOD_CNT,.max = MAX_INT_MOD_CNT}}
174 };
175 int val;
176 if (num_int_mod_timer > bd) {
177 val = int_mod_timer[bd];
178 atl1_validate_option(&val, &opt, pdev);
179 adapter->imt = (u16) val;
180 } else
181 adapter->imt = (u16) (opt.def);
182 }
183
184 { /* Flash Vendor */
185 struct atl1_option opt = {
186 .type = range_option,
187 .name = "SPI Flash Vendor",
188 .err = "using default of "
189 __MODULE_STRING(FLASH_VENDOR_DEFAULT),
190 .def = DEFAULT_INT_MOD_CNT,
191 .arg = {.r =
192 {.min = FLASH_VENDOR_MIN,.max =
193 FLASH_VENDOR_MAX}}
194 };
195 int val;
196 if (num_flash_vendor > bd) {
197 val = flash_vendor[bd];
198 atl1_validate_option(&val, &opt, pdev);
199 adapter->hw.flash_vendor = (u8) val;
200 } else
201 adapter->hw.flash_vendor = (u8) (opt.def);
202 }
203}
diff --git a/drivers/net/atlx/atlx.c b/drivers/net/atlx/atlx.c
new file mode 100644
index 000000000000..4186326d1b94
--- /dev/null
+++ b/drivers/net/atlx/atlx.c
@@ -0,0 +1,433 @@
1/* atlx.c -- common functions for Attansic network drivers
2 *
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
6 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
7 *
8 * Derived from Intel e1000 driver
9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */
25
26/* Including this file like a header is a temporary hack, I promise. -- CHS */
27#ifndef ATLX_C
28#define ATLX_C
29
30#include <linux/device.h>
31#include <linux/errno.h>
32#include <linux/etherdevice.h>
33#include <linux/if.h>
34#include <linux/netdevice.h>
35#include <linux/socket.h>
36#include <linux/sockios.h>
37#include <linux/spinlock.h>
38#include <linux/string.h>
39#include <linux/types.h>
40#include <linux/workqueue.h>
41
42#include "atlx.h"
43
44static struct atlx_spi_flash_dev flash_table[] = {
45/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SEC_ERS CHIP_ERS */
46 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
47 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
48 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
49};
50
51static int atlx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
52{
53 switch (cmd) {
54 case SIOCGMIIPHY:
55 case SIOCGMIIREG:
56 case SIOCSMIIREG:
57 return atlx_mii_ioctl(netdev, ifr, cmd);
58 default:
59 return -EOPNOTSUPP;
60 }
61}
62
63/*
64 * atlx_set_mac - Change the Ethernet Address of the NIC
65 * @netdev: network interface device structure
66 * @p: pointer to an address structure
67 *
68 * Returns 0 on success, negative on failure
69 */
70static int atlx_set_mac(struct net_device *netdev, void *p)
71{
72 struct atlx_adapter *adapter = netdev_priv(netdev);
73 struct sockaddr *addr = p;
74
75 if (netif_running(netdev))
76 return -EBUSY;
77
78 if (!is_valid_ether_addr(addr->sa_data))
79 return -EADDRNOTAVAIL;
80
81 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
82 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
83
84 atlx_set_mac_addr(&adapter->hw);
85 return 0;
86}
87
88static void atlx_check_for_link(struct atlx_adapter *adapter)
89{
90 struct net_device *netdev = adapter->netdev;
91 u16 phy_data = 0;
92
93 spin_lock(&adapter->lock);
94 adapter->phy_timer_pending = false;
95 atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
96 atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
97 spin_unlock(&adapter->lock);
98
99 /* notify upper layer link down ASAP */
100 if (!(phy_data & BMSR_LSTATUS)) {
101 /* Link Down */
102 if (netif_carrier_ok(netdev)) {
103 /* old link state: Up */
104 dev_info(&adapter->pdev->dev, "%s link is down\n",
105 netdev->name);
106 adapter->link_speed = SPEED_0;
107 netif_carrier_off(netdev);
108 netif_stop_queue(netdev);
109 }
110 }
111 schedule_work(&adapter->link_chg_task);
112}
113
114/*
115 * atlx_set_multi - Multicast and Promiscuous mode set
116 * @netdev: network interface device structure
117 *
118 * The set_multi entry point is called whenever the multicast address
119 * list or the network interface flags are updated. This routine is
120 * responsible for configuring the hardware for proper multicast,
121 * promiscuous mode, and all-multi behavior.
122 */
123static void atlx_set_multi(struct net_device *netdev)
124{
125 struct atlx_adapter *adapter = netdev_priv(netdev);
126 struct atlx_hw *hw = &adapter->hw;
127 struct dev_mc_list *mc_ptr;
128 u32 rctl;
129 u32 hash_value;
130
131 /* Check for Promiscuous and All Multicast modes */
132 rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
133 if (netdev->flags & IFF_PROMISC)
134 rctl |= MAC_CTRL_PROMIS_EN;
135 else if (netdev->flags & IFF_ALLMULTI) {
136 rctl |= MAC_CTRL_MC_ALL_EN;
137 rctl &= ~MAC_CTRL_PROMIS_EN;
138 } else
139 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
140
141 iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
142
143 /* clear the old settings from the multicast hash table */
144 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
145 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
146
147 /* compute mc addresses' hash value ,and put it into hash table */
148 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
149 hash_value = atlx_hash_mc_addr(hw, mc_ptr->dmi_addr);
150 atlx_hash_set(hw, hash_value);
151 }
152}
153
154/*
155 * atlx_irq_enable - Enable default interrupt generation settings
156 * @adapter: board private structure
157 */
158static void atlx_irq_enable(struct atlx_adapter *adapter)
159{
160 iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
161 ioread32(adapter->hw.hw_addr + REG_IMR);
162}
163
164/*
165 * atlx_irq_disable - Mask off interrupt generation on the NIC
166 * @adapter: board private structure
167 */
168static void atlx_irq_disable(struct atlx_adapter *adapter)
169{
170 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
171 ioread32(adapter->hw.hw_addr + REG_IMR);
172 synchronize_irq(adapter->pdev->irq);
173}
174
175static void atlx_clear_phy_int(struct atlx_adapter *adapter)
176{
177 u16 phy_data;
178 unsigned long flags;
179
180 spin_lock_irqsave(&adapter->lock, flags);
181 atlx_read_phy_reg(&adapter->hw, 19, &phy_data);
182 spin_unlock_irqrestore(&adapter->lock, flags);
183}
184
185/*
186 * atlx_get_stats - Get System Network Statistics
187 * @netdev: network interface device structure
188 *
189 * Returns the address of the device statistics structure.
190 * The statistics are actually updated from the timer callback.
191 */
192static struct net_device_stats *atlx_get_stats(struct net_device *netdev)
193{
194 struct atlx_adapter *adapter = netdev_priv(netdev);
195 return &adapter->net_stats;
196}
197
198/*
199 * atlx_tx_timeout - Respond to a Tx Hang
200 * @netdev: network interface device structure
201 */
202static void atlx_tx_timeout(struct net_device *netdev)
203{
204 struct atlx_adapter *adapter = netdev_priv(netdev);
205 /* Do the reset outside of interrupt context */
206 schedule_work(&adapter->tx_timeout_task);
207}
208
209/*
210 * atlx_link_chg_task - deal with link change event Out of interrupt context
211 */
212static void atlx_link_chg_task(struct work_struct *work)
213{
214 struct atlx_adapter *adapter;
215 unsigned long flags;
216
217 adapter = container_of(work, struct atlx_adapter, link_chg_task);
218
219 spin_lock_irqsave(&adapter->lock, flags);
220 atlx_check_link(adapter);
221 spin_unlock_irqrestore(&adapter->lock, flags);
222}
223
224static void atlx_vlan_rx_register(struct net_device *netdev,
225 struct vlan_group *grp)
226{
227 struct atlx_adapter *adapter = netdev_priv(netdev);
228 unsigned long flags;
229 u32 ctrl;
230
231 spin_lock_irqsave(&adapter->lock, flags);
232 /* atlx_irq_disable(adapter); FIXME: confirm/remove */
233 adapter->vlgrp = grp;
234
235 if (grp) {
236 /* enable VLAN tag insert/strip */
237 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
238 ctrl |= MAC_CTRL_RMV_VLAN;
239 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
240 } else {
241 /* disable VLAN tag insert/strip */
242 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
243 ctrl &= ~MAC_CTRL_RMV_VLAN;
244 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
245 }
246
247 /* atlx_irq_enable(adapter); FIXME */
248 spin_unlock_irqrestore(&adapter->lock, flags);
249}
250
251static void atlx_restore_vlan(struct atlx_adapter *adapter)
252{
253 atlx_vlan_rx_register(adapter->netdev, adapter->vlgrp);
254}
255
256/*
257 * This is the only thing that needs to be changed to adjust the
258 * maximum number of ports that the driver can manage.
259 */
260#define ATL1_MAX_NIC 4
261
262#define OPTION_UNSET -1
263#define OPTION_DISABLED 0
264#define OPTION_ENABLED 1
265
266#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
267
268/*
269 * Interrupt Moderate Timer in units of 2 us
270 *
271 * Valid Range: 10-65535
272 *
273 * Default Value: 100 (200us)
274 */
275static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
276static int num_int_mod_timer;
277module_param_array_named(int_mod_timer, int_mod_timer, int,
278 &num_int_mod_timer, 0);
279MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
280
281/*
282 * flash_vendor
283 *
284 * Valid Range: 0-2
285 *
286 * 0 - Atmel
287 * 1 - SST
288 * 2 - ST
289 *
290 * Default Value: 0
291 */
292static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
293static int num_flash_vendor;
294module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
295MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
296
297#define DEFAULT_INT_MOD_CNT 100 /* 200us */
298#define MAX_INT_MOD_CNT 65000
299#define MIN_INT_MOD_CNT 50
300
301#define FLASH_VENDOR_DEFAULT 0
302#define FLASH_VENDOR_MIN 0
303#define FLASH_VENDOR_MAX 2
304
305struct atl1_option {
306 enum { enable_option, range_option, list_option } type;
307 char *name;
308 char *err;
309 int def;
310 union {
311 struct { /* range_option info */
312 int min;
313 int max;
314 } r;
315 struct { /* list_option info */
316 int nr;
317 struct atl1_opt_list {
318 int i;
319 char *str;
320 } *p;
321 } l;
322 } arg;
323};
324
325static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
326 struct pci_dev *pdev)
327{
328 if (*value == OPTION_UNSET) {
329 *value = opt->def;
330 return 0;
331 }
332
333 switch (opt->type) {
334 case enable_option:
335 switch (*value) {
336 case OPTION_ENABLED:
337 dev_info(&pdev->dev, "%s enabled\n", opt->name);
338 return 0;
339 case OPTION_DISABLED:
340 dev_info(&pdev->dev, "%s disabled\n", opt->name);
341 return 0;
342 }
343 break;
344 case range_option:
345 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
346 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
347 *value);
348 return 0;
349 }
350 break;
351 case list_option:{
352 int i;
353 struct atl1_opt_list *ent;
354
355 for (i = 0; i < opt->arg.l.nr; i++) {
356 ent = &opt->arg.l.p[i];
357 if (*value == ent->i) {
358 if (ent->str[0] != '\0')
359 dev_info(&pdev->dev, "%s\n",
360 ent->str);
361 return 0;
362 }
363 }
364 }
365 break;
366
367 default:
368 break;
369 }
370
371 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
372 opt->name, *value, opt->err);
373 *value = opt->def;
374 return -1;
375}
376
377/*
378 * atl1_check_options - Range Checking for Command Line Parameters
379 * @adapter: board private structure
380 *
381 * This routine checks all command line parameters for valid user
382 * input. If an invalid value is given, or if no user specified
383 * value exists, a default value is used. The final value is stored
384 * in a variable in the adapter structure.
385 */
386void __devinit atl1_check_options(struct atl1_adapter *adapter)
387{
388 struct pci_dev *pdev = adapter->pdev;
389 int bd = adapter->bd_number;
390 if (bd >= ATL1_MAX_NIC) {
391 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
392 dev_notice(&pdev->dev, "using defaults for all values\n");
393 }
394 { /* Interrupt Moderate Timer */
395 struct atl1_option opt = {
396 .type = range_option,
397 .name = "Interrupt Moderator Timer",
398 .err = "using default of "
399 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
400 .def = DEFAULT_INT_MOD_CNT,
401 .arg = {.r = {.min = MIN_INT_MOD_CNT,
402 .max = MAX_INT_MOD_CNT} }
403 };
404 int val;
405 if (num_int_mod_timer > bd) {
406 val = int_mod_timer[bd];
407 atl1_validate_option(&val, &opt, pdev);
408 adapter->imt = (u16) val;
409 } else
410 adapter->imt = (u16) (opt.def);
411 }
412
413 { /* Flash Vendor */
414 struct atl1_option opt = {
415 .type = range_option,
416 .name = "SPI Flash Vendor",
417 .err = "using default of "
418 __MODULE_STRING(FLASH_VENDOR_DEFAULT),
419 .def = DEFAULT_INT_MOD_CNT,
420 .arg = {.r = {.min = FLASH_VENDOR_MIN,
421 .max = FLASH_VENDOR_MAX} }
422 };
423 int val;
424 if (num_flash_vendor > bd) {
425 val = flash_vendor[bd];
426 atl1_validate_option(&val, &opt, pdev);
427 adapter->hw.flash_vendor = (u8) val;
428 } else
429 adapter->hw.flash_vendor = (u8) (opt.def);
430 }
431}
432
433#endif /* ATLX_C */
diff --git a/drivers/net/atlx/atlx.h b/drivers/net/atlx/atlx.h
new file mode 100644
index 000000000000..3be7c09734d4
--- /dev/null
+++ b/drivers/net/atlx/atlx.h
@@ -0,0 +1,506 @@
1/* atlx_hw.h -- common hardware definitions for Attansic network drivers
2 *
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
6 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
7 *
8 * Derived from Intel e1000 driver
9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */
25
26#ifndef ATLX_H
27#define ATLX_H
28
29#include <linux/module.h>
30#include <linux/types.h>
31
32#define ATLX_DRIVER_VERSION "2.1.1"
33MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
34 Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
35MODULE_LICENSE("GPL");
36MODULE_VERSION(ATLX_DRIVER_VERSION);
37
38#define ATLX_ERR_PHY 2
39#define ATLX_ERR_PHY_SPEED 7
40#define ATLX_ERR_PHY_RES 8
41
42#define SPEED_0 0xffff
43#define SPEED_10 10
44#define SPEED_100 100
45#define SPEED_1000 1000
46#define HALF_DUPLEX 1
47#define FULL_DUPLEX 2
48
49#define MEDIA_TYPE_AUTO_SENSOR 0
50
51/* register definitions */
52#define REG_PM_CTRLSTAT 0x44
53
54#define REG_PCIE_CAP_LIST 0x58
55
56#define REG_VPD_CAP 0x6C
57#define VPD_CAP_ID_MASK 0xFF
58#define VPD_CAP_ID_SHIFT 0
59#define VPD_CAP_NEXT_PTR_MASK 0xFF
60#define VPD_CAP_NEXT_PTR_SHIFT 8
61#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
62#define VPD_CAP_VPD_ADDR_SHIFT 16
63#define VPD_CAP_VPD_FLAG 0x80000000
64
65#define REG_VPD_DATA 0x70
66
67#define REG_SPI_FLASH_CTRL 0x200
68#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
69#define SPI_FLASH_CTRL_STS_WEN 0x2
70#define SPI_FLASH_CTRL_STS_WPEN 0x80
71#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
72#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
73#define SPI_FLASH_CTRL_INS_MASK 0x7
74#define SPI_FLASH_CTRL_INS_SHIFT 8
75#define SPI_FLASH_CTRL_START 0x800
76#define SPI_FLASH_CTRL_EN_VPD 0x2000
77#define SPI_FLASH_CTRL_LDSTART 0x8000
78#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
79#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
80#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
81#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
82#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
83#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
84#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
85#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
86#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
87#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
88#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
89#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
90#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
91
92#define REG_SPI_ADDR 0x204
93
94#define REG_SPI_DATA 0x208
95
96#define REG_SPI_FLASH_CONFIG 0x20C
97#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
98#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
99#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
100#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
101#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
102
103#define REG_SPI_FLASH_OP_PROGRAM 0x210
104#define REG_SPI_FLASH_OP_SC_ERASE 0x211
105#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
106#define REG_SPI_FLASH_OP_RDID 0x213
107#define REG_SPI_FLASH_OP_WREN 0x214
108#define REG_SPI_FLASH_OP_RDSR 0x215
109#define REG_SPI_FLASH_OP_WRSR 0x216
110#define REG_SPI_FLASH_OP_READ 0x217
111
112#define REG_TWSI_CTRL 0x218
113#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
114#define TWSI_CTRL_LD_OFFSET_SHIFT 0
115#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
116#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
117#define TWSI_CTRL_SW_LDSTART 0x800
118#define TWSI_CTRL_HW_LDSTART 0x1000
119#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
120#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
121#define TWSI_CTRL_LD_EXIST 0x400000
122#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
123#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
124#define TWSI_CTRL_FREQ_SEL_100K 0
125#define TWSI_CTRL_FREQ_SEL_200K 1
126#define TWSI_CTRL_FREQ_SEL_300K 2
127#define TWSI_CTRL_FREQ_SEL_400K 3
128#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */
129#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
130#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
131
132#define REG_PCIE_DEV_MISC_CTRL 0x21C
133#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
134#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
135#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
136#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
137#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
138
139#define REG_PCIE_PHYMISC 0x1000
140#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
141
142#define REG_PCIE_DLL_TX_CTRL1 0x1104
143#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400
144#define PCIE_DLL_TX_CTRL1_DEF 0x568
145
146#define REG_LTSSM_TEST_MODE 0x12FC
147#define LTSSM_TEST_MODE_DEF 0x6500
148
149/* Master Control Register */
150#define REG_MASTER_CTRL 0x1400
151#define MASTER_CTRL_SOFT_RST 0x1
152#define MASTER_CTRL_MTIMER_EN 0x2
153#define MASTER_CTRL_ITIMER_EN 0x4
154#define MASTER_CTRL_MANUAL_INT 0x8
155#define MASTER_CTRL_REV_NUM_SHIFT 16
156#define MASTER_CTRL_REV_NUM_MASK 0xFF
157#define MASTER_CTRL_DEV_ID_SHIFT 24
158#define MASTER_CTRL_DEV_ID_MASK 0xFF
159
160/* Timer Initial Value Register */
161#define REG_MANUAL_TIMER_INIT 0x1404
162
163/* IRQ Moderator Timer Initial Value Register */
164#define REG_IRQ_MODU_TIMER_INIT 0x1408
165
166#define REG_PHY_ENABLE 0x140C
167
168/* IRQ Anti-Lost Timer Initial Value Register */
169#define REG_CMBDISDMA_TIMER 0x140E
170
171/* Block IDLE Status Register */
172#define REG_IDLE_STATUS 0x1410
173
174/* MDIO Control Register */
175#define REG_MDIO_CTRL 0x1414
176#define MDIO_DATA_MASK 0xFFFF
177#define MDIO_DATA_SHIFT 0
178#define MDIO_REG_ADDR_MASK 0x1F
179#define MDIO_REG_ADDR_SHIFT 16
180#define MDIO_RW 0x200000
181#define MDIO_SUP_PREAMBLE 0x400000
182#define MDIO_START 0x800000
183#define MDIO_CLK_SEL_SHIFT 24
184#define MDIO_CLK_25_4 0
185#define MDIO_CLK_25_6 2
186#define MDIO_CLK_25_8 3
187#define MDIO_CLK_25_10 4
188#define MDIO_CLK_25_14 5
189#define MDIO_CLK_25_20 6
190#define MDIO_CLK_25_28 7
191#define MDIO_BUSY 0x8000000
192
193/* MII PHY Status Register */
194#define REG_PHY_STATUS 0x1418
195
196/* BIST Control and Status Register0 (for the Packet Memory) */
197#define REG_BIST0_CTRL 0x141C
198#define BIST0_NOW 0x1
199#define BIST0_SRAM_FAIL 0x2
200#define BIST0_FUSE_FLAG 0x4
201#define REG_BIST1_CTRL 0x1420
202#define BIST1_NOW 0x1
203#define BIST1_SRAM_FAIL 0x2
204#define BIST1_FUSE_FLAG 0x4
205
206/* SerDes Lock Detect Control and Status Register */
207#define REG_SERDES_LOCK 0x1424
208#define SERDES_LOCK_DETECT 1
209#define SERDES_LOCK_DETECT_EN 2
210
211/* MAC Control Register */
212#define REG_MAC_CTRL 0x1480
213#define MAC_CTRL_TX_EN 1
214#define MAC_CTRL_RX_EN 2
215#define MAC_CTRL_TX_FLOW 4
216#define MAC_CTRL_RX_FLOW 8
217#define MAC_CTRL_LOOPBACK 0x10
218#define MAC_CTRL_DUPLX 0x20
219#define MAC_CTRL_ADD_CRC 0x40
220#define MAC_CTRL_PAD 0x80
221#define MAC_CTRL_LENCHK 0x100
222#define MAC_CTRL_HUGE_EN 0x200
223#define MAC_CTRL_PRMLEN_SHIFT 10
224#define MAC_CTRL_PRMLEN_MASK 0xF
225#define MAC_CTRL_RMV_VLAN 0x4000
226#define MAC_CTRL_PROMIS_EN 0x8000
227#define MAC_CTRL_MC_ALL_EN 0x2000000
228#define MAC_CTRL_BC_EN 0x4000000
229
230/* MAC IPG/IFG Control Register */
231#define REG_MAC_IPG_IFG 0x1484
232#define MAC_IPG_IFG_IPGT_SHIFT 0
233#define MAC_IPG_IFG_IPGT_MASK 0x7F
234#define MAC_IPG_IFG_MIFG_SHIFT 8
235#define MAC_IPG_IFG_MIFG_MASK 0xFF
236#define MAC_IPG_IFG_IPGR1_SHIFT 16
237#define MAC_IPG_IFG_IPGR1_MASK 0x7F
238#define MAC_IPG_IFG_IPGR2_SHIFT 24
239#define MAC_IPG_IFG_IPGR2_MASK 0x7F
240
241/* MAC STATION ADDRESS */
242#define REG_MAC_STA_ADDR 0x1488
243
244/* Hash table for multicast address */
245#define REG_RX_HASH_TABLE 0x1490
246
247/* MAC Half-Duplex Control Register */
248#define REG_MAC_HALF_DUPLX_CTRL 0x1498
249#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
250#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF
251#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
252#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF
253#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
254#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
255#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
256#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
257#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
258#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF
259#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
260#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF
261
262/* Maximum Frame Length Control Register */
263#define REG_MTU 0x149C
264
265/* Wake-On-Lan control register */
266#define REG_WOL_CTRL 0x14A0
267#define WOL_PATTERN_EN 0x1
268#define WOL_PATTERN_PME_EN 0x2
269#define WOL_MAGIC_EN 0x4
270#define WOL_MAGIC_PME_EN 0x8
271#define WOL_LINK_CHG_EN 0x10
272#define WOL_LINK_CHG_PME_EN 0x20
273#define WOL_PATTERN_ST 0x100
274#define WOL_MAGIC_ST 0x200
275#define WOL_LINKCHG_ST 0x400
276#define WOL_PT0_EN 0x10000
277#define WOL_PT1_EN 0x20000
278#define WOL_PT2_EN 0x40000
279#define WOL_PT3_EN 0x80000
280#define WOL_PT4_EN 0x100000
281#define WOL_PT0_MATCH 0x1000000
282#define WOL_PT1_MATCH 0x2000000
283#define WOL_PT2_MATCH 0x4000000
284#define WOL_PT3_MATCH 0x8000000
285#define WOL_PT4_MATCH 0x10000000
286
287/* Internal SRAM Partition Register, high 32 bits */
288#define REG_SRAM_RFD_ADDR 0x1500
289
290/* Descriptor Control register, high 32 bits */
291#define REG_DESC_BASE_ADDR_HI 0x1540
292
293/* Interrupt Status Register */
294#define REG_ISR 0x1600
295#define ISR_UR_DETECTED 0x1000000
296#define ISR_FERR_DETECTED 0x2000000
297#define ISR_NFERR_DETECTED 0x4000000
298#define ISR_CERR_DETECTED 0x8000000
299#define ISR_PHY_LINKDOWN 0x10000000
300#define ISR_DIS_INT 0x80000000
301
302/* Interrupt Mask Register */
303#define REG_IMR 0x1604
304
305#define REG_RFD_RRD_IDX 0x1800
306#define REG_TPD_IDX 0x1804
307
308/* MII definitions */
309
310/* PHY Common Register */
311#define MII_ATLX_CR 0x09
312#define MII_ATLX_SR 0x0A
313#define MII_ATLX_ESR 0x0F
314#define MII_ATLX_PSCR 0x10
315#define MII_ATLX_PSSR 0x11
316
317/* PHY Control Register */
318#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
319 * 00=10
320 */
321#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
322#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
323#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
324#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
325#define MII_CR_POWER_DOWN 0x0800 /* Power down */
326#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
327#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
328 * 00=10
329 */
330#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
331#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
332#define MII_CR_SPEED_MASK 0x2040
333#define MII_CR_SPEED_1000 0x0040
334#define MII_CR_SPEED_100 0x2000
335#define MII_CR_SPEED_10 0x0000
336
337/* PHY Status Register */
338#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */
339#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
340#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
341#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
342#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
343#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
344#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
345#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */
346#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
347#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
348#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
349#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
350#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
351#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
352#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
353
354/* Link partner ability register */
355#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
356#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
357#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
358#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
359#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
360#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
361#define MII_LPA_PAUSE 0x0400 /* PAUSE */
362#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
363#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
364#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
365#define MII_LPA_NPAGE 0x8000 /* Next page bit */
366
367/* Autoneg Advertisement Register */
368#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */
369#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
370#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
371#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
372#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
373#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
374#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
375#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */
376#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
377#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */
378#define MII_AR_SPEED_MASK 0x01E0
379#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
380
381/* 1000BASE-T Control Register */
382#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */
383#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */
384#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device,
385 * 0=DTE device */
386#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master,
387 * 0=Configure PHY as Slave */
388#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config,
389 * 0=Auto Master/Slave config
390 */
391#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
392#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
393#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */
394#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */
395#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */
396#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300
397#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300
398
399/* 1000BASE-T Status Register */
400#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
401#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
402#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
403#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
404#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master
405 * 0=Slave
406 */
407#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config
408 * fault */
409#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
410#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
411
412/* Extended Status Register */
413#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
414#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
415#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
416#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
417
418/* ATLX PHY Specific Control Register */
419#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */
420#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */
421#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
422#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008
423#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low
424 * 0=CLK125 toggling
425 */
426#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5,
427 * Manual MDI configuration
428 */
429#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
430#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover
431 * 100BASE-TX/10BASE-T: MDI
432 * Mode */
433#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
434 * all speeds.
435 */
436#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended
437 * 10BASE-T distance
438 * (Lower 10BASE-T RX
439 * Threshold)
440 * 0=Normal 10BASE-T RX
441 * Threshold
442 */
443#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in
444 * 100BASE-TX
445 * 0=MII interface in
446 * 100BASE-TX
447 */
448#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */
449#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
450#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
451#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1
452#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5
453#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
454
455/* ATLX PHY Specific Status Register */
456#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
457#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
458#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
459#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */
460#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
461#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
462
463/* PCI Command Register Bit Definitions */
464#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
465#define CMD_IO_SPACE 0x0001
466#define CMD_MEMORY_SPACE 0x0002
467#define CMD_BUS_MASTER 0x0004
468
469/* Wake Up Filter Control */
470#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
471#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
472#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
473#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
474#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
475
476#define ADVERTISE_10_HALF 0x0001
477#define ADVERTISE_10_FULL 0x0002
478#define ADVERTISE_100_HALF 0x0004
479#define ADVERTISE_100_FULL 0x0008
480#define ADVERTISE_1000_HALF 0x0010
481#define ADVERTISE_1000_FULL 0x0020
482#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
483#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
484
485#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
486#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
487
488/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */
489#define EEPROM_SUM 0xBABA
490#define NODE_ADDRESS_SIZE 6
491
492struct atlx_spi_flash_dev {
493 const char *manu_name; /* manufacturer id */
494 /* op-code */
495 u8 cmd_wrsr;
496 u8 cmd_read;
497 u8 cmd_program;
498 u8 cmd_wren;
499 u8 cmd_wrdi;
500 u8 cmd_rdsr;
501 u8 cmd_rdid;
502 u8 cmd_sector_erase;
503 u8 cmd_chip_erase;
504};
505
506#endif /* ATLX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 17:37:53 -0500