diff options
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/jme.c | 51 | ||||
-rw-r--r-- | drivers/net/jme.h | 30 |
2 files changed, 63 insertions, 18 deletions
diff --git a/drivers/net/jme.c b/drivers/net/jme.c index f292df557544..635f616fd974 100644 --- a/drivers/net/jme.c +++ b/drivers/net/jme.c | |||
@@ -190,7 +190,7 @@ jme_reset_mac_processor(struct jme_adapter *jme) | |||
190 | else | 190 | else |
191 | gpreg0 = GPREG0_DEFAULT; | 191 | gpreg0 = GPREG0_DEFAULT; |
192 | jwrite32(jme, JME_GPREG0, gpreg0); | 192 | jwrite32(jme, JME_GPREG0, gpreg0); |
193 | jwrite32(jme, JME_GPREG1, 0); | 193 | jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT); |
194 | } | 194 | } |
195 | 195 | ||
196 | static inline void | 196 | static inline void |
@@ -365,7 +365,7 @@ static int | |||
365 | jme_check_link(struct net_device *netdev, int testonly) | 365 | jme_check_link(struct net_device *netdev, int testonly) |
366 | { | 366 | { |
367 | struct jme_adapter *jme = netdev_priv(netdev); | 367 | struct jme_adapter *jme = netdev_priv(netdev); |
368 | u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr; | 368 | u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1; |
369 | char linkmsg[64]; | 369 | char linkmsg[64]; |
370 | int rc = 0; | 370 | int rc = 0; |
371 | 371 | ||
@@ -437,37 +437,22 @@ jme_check_link(struct net_device *netdev, int testonly) | |||
437 | case PHY_LINK_SPEED_10M: | 437 | case PHY_LINK_SPEED_10M: |
438 | ghc |= GHC_SPEED_10M; | 438 | ghc |= GHC_SPEED_10M; |
439 | strcat(linkmsg, "10 Mbps, "); | 439 | strcat(linkmsg, "10 Mbps, "); |
440 | if (is_buggy250(jme->pdev->device, jme->chiprev)) | ||
441 | jme_set_phyfifoa(jme); | ||
442 | break; | 440 | break; |
443 | case PHY_LINK_SPEED_100M: | 441 | case PHY_LINK_SPEED_100M: |
444 | ghc |= GHC_SPEED_100M; | 442 | ghc |= GHC_SPEED_100M; |
445 | strcat(linkmsg, "100 Mbps, "); | 443 | strcat(linkmsg, "100 Mbps, "); |
446 | if (is_buggy250(jme->pdev->device, jme->chiprev)) | ||
447 | jme_set_phyfifob(jme); | ||
448 | break; | 444 | break; |
449 | case PHY_LINK_SPEED_1000M: | 445 | case PHY_LINK_SPEED_1000M: |
450 | ghc |= GHC_SPEED_1000M; | 446 | ghc |= GHC_SPEED_1000M; |
451 | strcat(linkmsg, "1000 Mbps, "); | 447 | strcat(linkmsg, "1000 Mbps, "); |
452 | if (is_buggy250(jme->pdev->device, jme->chiprev)) | ||
453 | jme_set_phyfifoa(jme); | ||
454 | break; | 448 | break; |
455 | default: | 449 | default: |
456 | break; | 450 | break; |
457 | } | 451 | } |
458 | ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0; | ||
459 | |||
460 | strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ? | ||
461 | "Full-Duplex, " : | ||
462 | "Half-Duplex, "); | ||
463 | |||
464 | if (phylink & PHY_LINK_MDI_STAT) | ||
465 | strcat(linkmsg, "MDI-X"); | ||
466 | else | ||
467 | strcat(linkmsg, "MDI"); | ||
468 | 452 | ||
469 | if (phylink & PHY_LINK_DUPLEX) { | 453 | if (phylink & PHY_LINK_DUPLEX) { |
470 | jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT); | 454 | jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT); |
455 | ghc |= GHC_DPX; | ||
471 | } else { | 456 | } else { |
472 | jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT | | 457 | jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT | |
473 | TXMCS_BACKOFF | | 458 | TXMCS_BACKOFF | |
@@ -478,6 +463,36 @@ jme_check_link(struct net_device *netdev, int testonly) | |||
478 | TXTRHD_TXREN | | 463 | TXTRHD_TXREN | |
479 | ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL)); | 464 | ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL)); |
480 | } | 465 | } |
466 | strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ? | ||
467 | "Full-Duplex, " : | ||
468 | "Half-Duplex, "); | ||
469 | |||
470 | if (phylink & PHY_LINK_MDI_STAT) | ||
471 | strcat(linkmsg, "MDI-X"); | ||
472 | else | ||
473 | strcat(linkmsg, "MDI"); | ||
474 | |||
475 | gpreg1 = GPREG1_DEFAULT; | ||
476 | if (is_buggy250(jme->pdev->device, jme->chiprev)) { | ||
477 | if (!(phylink & PHY_LINK_DUPLEX)) | ||
478 | gpreg1 |= GPREG1_HALFMODEPATCH; | ||
479 | switch (phylink & PHY_LINK_SPEED_MASK) { | ||
480 | case PHY_LINK_SPEED_10M: | ||
481 | jme_set_phyfifoa(jme); | ||
482 | gpreg1 |= GPREG1_RSSPATCH; | ||
483 | break; | ||
484 | case PHY_LINK_SPEED_100M: | ||
485 | jme_set_phyfifob(jme); | ||
486 | gpreg1 |= GPREG1_RSSPATCH; | ||
487 | break; | ||
488 | case PHY_LINK_SPEED_1000M: | ||
489 | jme_set_phyfifoa(jme); | ||
490 | break; | ||
491 | default: | ||
492 | break; | ||
493 | } | ||
494 | } | ||
495 | jwrite32(jme, JME_GPREG1, gpreg1); | ||
481 | 496 | ||
482 | jme->reg_ghc = ghc; | 497 | jme->reg_ghc = ghc; |
483 | jwrite32(jme, JME_GHC, ghc); | 498 | jwrite32(jme, JME_GHC, ghc); |
diff --git a/drivers/net/jme.h b/drivers/net/jme.h index b29688431a6d..9fdf20a9a820 100644 --- a/drivers/net/jme.h +++ b/drivers/net/jme.h | |||
@@ -964,6 +964,36 @@ enum jme_gpreg0_vals { | |||
964 | }; | 964 | }; |
965 | 965 | ||
966 | /* | 966 | /* |
967 | * General Purpose REG-1 | ||
968 | * Note: All theses bits defined here are for | ||
969 | * Chip mode revision 0x11 only | ||
970 | */ | ||
971 | enum jme_gpreg1_masks { | ||
972 | GPREG1_INTRDELAYUNIT = 0x00000018, | ||
973 | GPREG1_INTRDELAYENABLE = 0x00000007, | ||
974 | }; | ||
975 | |||
976 | enum jme_gpreg1_vals { | ||
977 | GPREG1_RSSPATCH = 0x00000040, | ||
978 | GPREG1_HALFMODEPATCH = 0x00000020, | ||
979 | |||
980 | GPREG1_INTDLYUNIT_16NS = 0x00000000, | ||
981 | GPREG1_INTDLYUNIT_256NS = 0x00000008, | ||
982 | GPREG1_INTDLYUNIT_1US = 0x00000010, | ||
983 | GPREG1_INTDLYUNIT_16US = 0x00000018, | ||
984 | |||
985 | GPREG1_INTDLYEN_1U = 0x00000001, | ||
986 | GPREG1_INTDLYEN_2U = 0x00000002, | ||
987 | GPREG1_INTDLYEN_3U = 0x00000003, | ||
988 | GPREG1_INTDLYEN_4U = 0x00000004, | ||
989 | GPREG1_INTDLYEN_5U = 0x00000005, | ||
990 | GPREG1_INTDLYEN_6U = 0x00000006, | ||
991 | GPREG1_INTDLYEN_7U = 0x00000007, | ||
992 | |||
993 | GPREG1_DEFAULT = 0x00000000, | ||
994 | }; | ||
995 | |||
996 | /* | ||
967 | * Interrupt Status Bits | 997 | * Interrupt Status Bits |
968 | */ | 998 | */ |
969 | enum jme_interrupt_bits { | 999 | enum jme_interrupt_bits { |