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-rw-r--r--drivers/net/bnx2.c217
-rw-r--r--drivers/net/bnx2.h63
2 files changed, 252 insertions, 28 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 11d252318221..671393a18469 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -41,6 +41,8 @@ typedef enum {
41 NC370I, 41 NC370I,
42 BCM5706S, 42 BCM5706S,
43 NC370F, 43 NC370F,
44 BCM5708,
45 BCM5708S,
44} board_t; 46} board_t;
45 47
46/* indexed by board_t, above */ 48/* indexed by board_t, above */
@@ -52,6 +54,8 @@ static struct {
52 { "HP NC370i Multifunction Gigabit Server Adapter" }, 54 { "HP NC370i Multifunction Gigabit Server Adapter" },
53 { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 55 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54 { "HP NC370F Multifunction Gigabit Server Adapter" }, 56 { "HP NC370F Multifunction Gigabit Server Adapter" },
57 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
55 }; 59 };
56 60
57static struct pci_device_id bnx2_pci_tbl[] = { 61static struct pci_device_id bnx2_pci_tbl[] = {
@@ -61,10 +65,14 @@ static struct pci_device_id bnx2_pci_tbl[] = {
61 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, 65 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, 67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
68 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 70 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
65 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, 71 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 72 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, 73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
74 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
68 { 0, } 76 { 0, }
69}; 77};
70 78
@@ -430,6 +438,18 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
430 return; 438 return;
431 } 439 }
432 440
441 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
442 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
443 u32 val;
444
445 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
446 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
447 bp->flow_ctrl |= FLOW_CTRL_TX;
448 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
449 bp->flow_ctrl |= FLOW_CTRL_RX;
450 return;
451 }
452
433 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); 453 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
434 bnx2_read_phy(bp, MII_LPA, &remote_adv); 454 bnx2_read_phy(bp, MII_LPA, &remote_adv);
435 455
@@ -476,7 +496,36 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
476} 496}
477 497
478static int 498static int
479bnx2_serdes_linkup(struct bnx2 *bp) 499bnx2_5708s_linkup(struct bnx2 *bp)
500{
501 u32 val;
502
503 bp->link_up = 1;
504 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
505 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
506 case BCM5708S_1000X_STAT1_SPEED_10:
507 bp->line_speed = SPEED_10;
508 break;
509 case BCM5708S_1000X_STAT1_SPEED_100:
510 bp->line_speed = SPEED_100;
511 break;
512 case BCM5708S_1000X_STAT1_SPEED_1G:
513 bp->line_speed = SPEED_1000;
514 break;
515 case BCM5708S_1000X_STAT1_SPEED_2G5:
516 bp->line_speed = SPEED_2500;
517 break;
518 }
519 if (val & BCM5708S_1000X_STAT1_FD)
520 bp->duplex = DUPLEX_FULL;
521 else
522 bp->duplex = DUPLEX_HALF;
523
524 return 0;
525}
526
527static int
528bnx2_5706s_linkup(struct bnx2 *bp)
480{ 529{
481 u32 bmcr, local_adv, remote_adv, common; 530 u32 bmcr, local_adv, remote_adv, common;
482 531
@@ -593,13 +642,27 @@ bnx2_set_mac_link(struct bnx2 *bp)
593 val = REG_RD(bp, BNX2_EMAC_MODE); 642 val = REG_RD(bp, BNX2_EMAC_MODE);
594 643
595 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 644 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
596 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK); 645 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
646 BNX2_EMAC_MODE_25G);
597 647
598 if (bp->link_up) { 648 if (bp->link_up) {
599 if (bp->line_speed != SPEED_1000) 649 switch (bp->line_speed) {
600 val |= BNX2_EMAC_MODE_PORT_MII; 650 case SPEED_10:
601 else 651 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
602 val |= BNX2_EMAC_MODE_PORT_GMII; 652 val |= BNX2_EMAC_MODE_PORT_MII_10;
653 break;
654 }
655 /* fall through */
656 case SPEED_100:
657 val |= BNX2_EMAC_MODE_PORT_MII;
658 break;
659 case SPEED_2500:
660 val |= BNX2_EMAC_MODE_25G;
661 /* fall through */
662 case SPEED_1000:
663 val |= BNX2_EMAC_MODE_PORT_GMII;
664 break;
665 }
603 } 666 }
604 else { 667 else {
605 val |= BNX2_EMAC_MODE_PORT_GMII; 668 val |= BNX2_EMAC_MODE_PORT_GMII;
@@ -662,7 +725,10 @@ bnx2_set_link(struct bnx2 *bp)
662 bp->link_up = 1; 725 bp->link_up = 1;
663 726
664 if (bp->phy_flags & PHY_SERDES_FLAG) { 727 if (bp->phy_flags & PHY_SERDES_FLAG) {
665 bnx2_serdes_linkup(bp); 728 if (CHIP_NUM(bp) == CHIP_NUM_5706)
729 bnx2_5706s_linkup(bp);
730 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
731 bnx2_5708s_linkup(bp);
666 } 732 }
667 else { 733 else {
668 bnx2_copper_linkup(bp); 734 bnx2_copper_linkup(bp);
@@ -755,39 +821,61 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp)
755static int 821static int
756bnx2_setup_serdes_phy(struct bnx2 *bp) 822bnx2_setup_serdes_phy(struct bnx2 *bp)
757{ 823{
758 u32 adv, bmcr; 824 u32 adv, bmcr, up1;
759 u32 new_adv = 0; 825 u32 new_adv = 0;
760 826
761 if (!(bp->autoneg & AUTONEG_SPEED)) { 827 if (!(bp->autoneg & AUTONEG_SPEED)) {
762 u32 new_bmcr; 828 u32 new_bmcr;
829 int force_link_down = 0;
830
831 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
832 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
833 if (up1 & BCM5708S_UP1_2G5) {
834 up1 &= ~BCM5708S_UP1_2G5;
835 bnx2_write_phy(bp, BCM5708S_UP1, up1);
836 force_link_down = 1;
837 }
838 }
839
840 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
841 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
763 842
764 bnx2_read_phy(bp, MII_BMCR, &bmcr); 843 bnx2_read_phy(bp, MII_BMCR, &bmcr);
765 new_bmcr = bmcr & ~BMCR_ANENABLE; 844 new_bmcr = bmcr & ~BMCR_ANENABLE;
766 new_bmcr |= BMCR_SPEED1000; 845 new_bmcr |= BMCR_SPEED1000;
767 if (bp->req_duplex == DUPLEX_FULL) { 846 if (bp->req_duplex == DUPLEX_FULL) {
847 adv |= ADVERTISE_1000XFULL;
768 new_bmcr |= BMCR_FULLDPLX; 848 new_bmcr |= BMCR_FULLDPLX;
769 } 849 }
770 else { 850 else {
851 adv |= ADVERTISE_1000XHALF;
771 new_bmcr &= ~BMCR_FULLDPLX; 852 new_bmcr &= ~BMCR_FULLDPLX;
772 } 853 }
773 if (new_bmcr != bmcr) { 854 if ((new_bmcr != bmcr) || (force_link_down)) {
774 /* Force a link down visible on the other side */ 855 /* Force a link down visible on the other side */
775 if (bp->link_up) { 856 if (bp->link_up) {
776 bnx2_read_phy(bp, MII_ADVERTISE, &adv); 857 bnx2_write_phy(bp, MII_ADVERTISE, adv &
777 adv &= ~(ADVERTISE_1000XFULL | 858 ~(ADVERTISE_1000XFULL |
778 ADVERTISE_1000XHALF); 859 ADVERTISE_1000XHALF));
779 bnx2_write_phy(bp, MII_ADVERTISE, adv);
780 bnx2_write_phy(bp, MII_BMCR, bmcr | 860 bnx2_write_phy(bp, MII_BMCR, bmcr |
781 BMCR_ANRESTART | BMCR_ANENABLE); 861 BMCR_ANRESTART | BMCR_ANENABLE);
782 862
783 bp->link_up = 0; 863 bp->link_up = 0;
784 netif_carrier_off(bp->dev); 864 netif_carrier_off(bp->dev);
865 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
785 } 866 }
867 bnx2_write_phy(bp, MII_ADVERTISE, adv);
786 bnx2_write_phy(bp, MII_BMCR, new_bmcr); 868 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
787 } 869 }
788 return 0; 870 return 0;
789 } 871 }
790 872
873 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
874 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
875 up1 |= BCM5708S_UP1_2G5;
876 bnx2_write_phy(bp, BCM5708S_UP1, up1);
877 }
878
791 if (bp->advertising & ADVERTISED_1000baseT_Full) 879 if (bp->advertising & ADVERTISED_1000baseT_Full)
792 new_adv |= ADVERTISE_1000XFULL; 880 new_adv |= ADVERTISE_1000XFULL;
793 881
@@ -952,7 +1040,60 @@ bnx2_setup_phy(struct bnx2 *bp)
952} 1040}
953 1041
954static int 1042static int
955bnx2_init_serdes_phy(struct bnx2 *bp) 1043bnx2_init_5708s_phy(struct bnx2 *bp)
1044{
1045 u32 val;
1046
1047 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1048 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1049 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1050
1051 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1052 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1053 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1054
1055 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1056 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1057 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1058
1059 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1060 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1061 val |= BCM5708S_UP1_2G5;
1062 bnx2_write_phy(bp, BCM5708S_UP1, val);
1063 }
1064
1065 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1066 (CHIP_ID(bp) == CHIP_ID_5708_B0)) {
1067 /* increase tx signal amplitude */
1068 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1069 BCM5708S_BLK_ADDR_TX_MISC);
1070 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1071 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1072 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1073 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1074 }
1075
1076 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_CONFIG) &
1077 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1078
1079 if (val) {
1080 u32 is_backplane;
1081
1082 is_backplane = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
1083 BNX2_SHARED_HW_CFG_CONFIG);
1084 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1085 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1086 BCM5708S_BLK_ADDR_TX_MISC);
1087 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1088 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1089 BCM5708S_BLK_ADDR_DIG);
1090 }
1091 }
1092 return 0;
1093}
1094
1095static int
1096bnx2_init_5706s_phy(struct bnx2 *bp)
956{ 1097{
957 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; 1098 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
958 1099
@@ -990,6 +1131,8 @@ bnx2_init_serdes_phy(struct bnx2 *bp)
990static int 1131static int
991bnx2_init_copper_phy(struct bnx2 *bp) 1132bnx2_init_copper_phy(struct bnx2 *bp)
992{ 1133{
1134 u32 val;
1135
993 bp->phy_flags |= PHY_CRC_FIX_FLAG; 1136 bp->phy_flags |= PHY_CRC_FIX_FLAG;
994 1137
995 if (bp->phy_flags & PHY_CRC_FIX_FLAG) { 1138 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
@@ -1004,8 +1147,6 @@ bnx2_init_copper_phy(struct bnx2 *bp)
1004 } 1147 }
1005 1148
1006 if (bp->dev->mtu > 1500) { 1149 if (bp->dev->mtu > 1500) {
1007 u32 val;
1008
1009 /* Set extended packet length bit */ 1150 /* Set extended packet length bit */
1010 bnx2_write_phy(bp, 0x18, 0x7); 1151 bnx2_write_phy(bp, 0x18, 0x7);
1011 bnx2_read_phy(bp, 0x18, &val); 1152 bnx2_read_phy(bp, 0x18, &val);
@@ -1015,8 +1156,6 @@ bnx2_init_copper_phy(struct bnx2 *bp)
1015 bnx2_write_phy(bp, 0x10, val | 0x1); 1156 bnx2_write_phy(bp, 0x10, val | 0x1);
1016 } 1157 }
1017 else { 1158 else {
1018 u32 val;
1019
1020 bnx2_write_phy(bp, 0x18, 0x7); 1159 bnx2_write_phy(bp, 0x18, 0x7);
1021 bnx2_read_phy(bp, 0x18, &val); 1160 bnx2_read_phy(bp, 0x18, &val);
1022 bnx2_write_phy(bp, 0x18, val & ~0x4007); 1161 bnx2_write_phy(bp, 0x18, val & ~0x4007);
@@ -1025,6 +1164,10 @@ bnx2_init_copper_phy(struct bnx2 *bp)
1025 bnx2_write_phy(bp, 0x10, val & ~0x1); 1164 bnx2_write_phy(bp, 0x10, val & ~0x1);
1026 } 1165 }
1027 1166
1167 /* ethernet@wirespeed */
1168 bnx2_write_phy(bp, 0x18, 0x7007);
1169 bnx2_read_phy(bp, 0x18, &val);
1170 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1028 return 0; 1171 return 0;
1029} 1172}
1030 1173
@@ -1048,7 +1191,10 @@ bnx2_init_phy(struct bnx2 *bp)
1048 bp->phy_id |= val & 0xffff; 1191 bp->phy_id |= val & 0xffff;
1049 1192
1050 if (bp->phy_flags & PHY_SERDES_FLAG) { 1193 if (bp->phy_flags & PHY_SERDES_FLAG) {
1051 rc = bnx2_init_serdes_phy(bp); 1194 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1195 rc = bnx2_init_5706s_phy(bp);
1196 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1197 rc = bnx2_init_5708s_phy(bp);
1052 } 1198 }
1053 else { 1199 else {
1054 rc = bnx2_init_copper_phy(bp); 1200 rc = bnx2_init_copper_phy(bp);
@@ -3234,7 +3380,7 @@ bnx2_test_registers(struct bnx2 *bp)
3234 { 0x1408, 0, 0x01c00800, 0x00000000 }, 3380 { 0x1408, 0, 0x01c00800, 0x00000000 },
3235 { 0x149c, 0, 0x8000ffff, 0x00000000 }, 3381 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3236 { 0x14a8, 0, 0x00000000, 0x000001ff }, 3382 { 0x14a8, 0, 0x00000000, 0x000001ff },
3237 { 0x14ac, 0, 0x4fffffff, 0x10000000 }, 3383 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3238 { 0x14b0, 0, 0x00000002, 0x00000001 }, 3384 { 0x14b0, 0, 0x00000002, 0x00000001 },
3239 { 0x14b8, 0, 0x00000000, 0x00000000 }, 3385 { 0x14b8, 0, 0x00000000, 0x00000000 },
3240 { 0x14c0, 0, 0x00000000, 0x00000009 }, 3386 { 0x14c0, 0, 0x00000000, 0x00000009 },
@@ -3577,7 +3723,7 @@ bnx2_test_memory(struct bnx2 *bp)
3577 u32 len; 3723 u32 len;
3578 } mem_tbl[] = { 3724 } mem_tbl[] = {
3579 { 0x60000, 0x4000 }, 3725 { 0x60000, 0x4000 },
3580 { 0xa0000, 0x4000 }, 3726 { 0xa0000, 0x3000 },
3581 { 0xe0000, 0x4000 }, 3727 { 0xe0000, 0x4000 },
3582 { 0x120000, 0x4000 }, 3728 { 0x120000, 0x4000 },
3583 { 0x1a0000, 0x4000 }, 3729 { 0x1a0000, 0x4000 },
@@ -4264,7 +4410,8 @@ bnx2_get_stats(struct net_device *dev)
4264 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions + 4410 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4265 stats_blk->stat_Dot3StatsLateCollisions); 4411 stats_blk->stat_Dot3StatsLateCollisions);
4266 4412
4267 if (CHIP_NUM(bp) == CHIP_NUM_5706) 4413 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4414 (CHIP_ID(bp) == CHIP_ID_5708_A0))
4268 net_stats->tx_carrier_errors = 0; 4415 net_stats->tx_carrier_errors = 0;
4269 else { 4416 else {
4270 net_stats->tx_carrier_errors = 4417 net_stats->tx_carrier_errors =
@@ -4814,6 +4961,14 @@ static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4814 4,4,4,4,4, 4961 4,4,4,4,4,
4815}; 4962};
4816 4963
4964static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
4965 8,0,8,8,8,8,8,8,8,8,
4966 4,4,4,4,4,4,4,4,4,4,
4967 4,4,4,4,4,4,4,4,4,4,
4968 4,4,4,4,4,4,4,4,4,4,
4969 4,4,4,4,4,
4970};
4971
4817#define BNX2_NUM_TESTS 6 4972#define BNX2_NUM_TESTS 6
4818 4973
4819static struct { 4974static struct {
@@ -4922,8 +5077,13 @@ bnx2_get_ethtool_stats(struct net_device *dev,
4922 return; 5077 return;
4923 } 5078 }
4924 5079
4925 if (CHIP_NUM(bp) == CHIP_NUM_5706) 5080 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5081 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5082 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5083 (CHIP_ID(bp) == CHIP_ID_5708_A0))
4926 stats_len_arr = bnx2_5706_stats_len_arr; 5084 stats_len_arr = bnx2_5706_stats_len_arr;
5085 else
5086 stats_len_arr = bnx2_5708_stats_len_arr;
4927 5087
4928 for (i = 0; i < BNX2_NUM_STATS; i++) { 5088 for (i = 0; i < BNX2_NUM_STATS; i++) {
4929 if (stats_len_arr[i] == 0) { 5089 if (stats_len_arr[i] == 0) {
@@ -5205,8 +5365,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5205 5365
5206 bp->chip_id = REG_RD(bp, BNX2_MISC_ID); 5366 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5207 5367
5208 bp->phy_addr = 1;
5209
5210 /* Get bus information. */ 5368 /* Get bus information. */
5211 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); 5369 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5212 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { 5370 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
@@ -5316,10 +5474,19 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5316 bp->timer_interval = HZ; 5474 bp->timer_interval = HZ;
5317 bp->current_interval = HZ; 5475 bp->current_interval = HZ;
5318 5476
5477 bp->phy_addr = 1;
5478
5319 /* Disable WOL support if we are running on a SERDES chip. */ 5479 /* Disable WOL support if we are running on a SERDES chip. */
5320 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) { 5480 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5321 bp->phy_flags |= PHY_SERDES_FLAG; 5481 bp->phy_flags |= PHY_SERDES_FLAG;
5322 bp->flags |= NO_WOL_FLAG; 5482 bp->flags |= NO_WOL_FLAG;
5483 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5484 bp->phy_addr = 2;
5485 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5486 BNX2_SHARED_HW_CFG_CONFIG);
5487 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5488 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5489 }
5323 } 5490 }
5324 5491
5325 if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 5492 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 62857b6a6ee4..c0e88f850493 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -1449,8 +1449,9 @@ struct l2_fhdr {
1449#define BNX2_EMAC_MODE_PORT_NONE (0L<<2) 1449#define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
1450#define BNX2_EMAC_MODE_PORT_MII (1L<<2) 1450#define BNX2_EMAC_MODE_PORT_MII (1L<<2)
1451#define BNX2_EMAC_MODE_PORT_GMII (2L<<2) 1451#define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
1452#define BNX2_EMAC_MODE_PORT_UNDEF (3L<<2) 1452#define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2)
1453#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4) 1453#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
1454#define BNX2_EMAC_MODE_25G (1L<<5)
1454#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 1455#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
1455#define BNX2_EMAC_MODE_TX_BURST (1L<<8) 1456#define BNX2_EMAC_MODE_TX_BURST (1L<<8)
1456#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 1457#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
@@ -3724,6 +3725,53 @@ struct l2_fhdr {
3724#define PHY_ID(id) ((id) & 0xfffffff0) 3725#define PHY_ID(id) ((id) & 0xfffffff0)
3725#define PHY_REV_ID(id) ((id) & 0xf) 3726#define PHY_REV_ID(id) ((id) & 0xf)
3726 3727
3728/* 5708 Serdes PHY registers */
3729
3730#define BCM5708S_UP1 0xb
3731
3732#define BCM5708S_UP1_2G5 0x1
3733
3734#define BCM5708S_BLK_ADDR 0x1f
3735
3736#define BCM5708S_BLK_ADDR_DIG 0x0000
3737#define BCM5708S_BLK_ADDR_DIG3 0x0002
3738#define BCM5708S_BLK_ADDR_TX_MISC 0x0005
3739
3740/* Digital Block */
3741#define BCM5708S_1000X_CTL1 0x10
3742
3743#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
3744#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
3745
3746#define BCM5708S_1000X_CTL2 0x11
3747
3748#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
3749
3750#define BCM5708S_1000X_STAT1 0x14
3751
3752#define BCM5708S_1000X_STAT1_SGMII 0x0001
3753#define BCM5708S_1000X_STAT1_LINK 0x0002
3754#define BCM5708S_1000X_STAT1_FD 0x0004
3755#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
3756#define BCM5708S_1000X_STAT1_SPEED_10 0x0000
3757#define BCM5708S_1000X_STAT1_SPEED_100 0x0008
3758#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
3759#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
3760#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
3761#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
3762
3763/* Digital3 Block */
3764#define BCM5708S_DIG_3_0 0x10
3765
3766#define BCM5708S_DIG_3_0_USE_IEEE 0x0001
3767
3768/* Tx/Misc Block */
3769#define BCM5708S_TX_ACTL1 0x15
3770
3771#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
3772
3773#define BCM5708S_TX_ACTL3 0x17
3774
3727#define MIN_ETHERNET_PACKET_SIZE 60 3775#define MIN_ETHERNET_PACKET_SIZE 60
3728#define MAX_ETHERNET_PACKET_SIZE 1514 3776#define MAX_ETHERNET_PACKET_SIZE 1514
3729#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 3777#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
@@ -3893,6 +3941,7 @@ struct bnx2 {
3893#define PHY_SERDES_FLAG 1 3941#define PHY_SERDES_FLAG 1
3894#define PHY_CRC_FIX_FLAG 2 3942#define PHY_CRC_FIX_FLAG 2
3895#define PHY_PARALLEL_DETECT_FLAG 4 3943#define PHY_PARALLEL_DETECT_FLAG 4
3944#define PHY_2_5G_CAPABLE_FLAG 8
3896#define PHY_INT_MODE_MASK_FLAG 0x300 3945#define PHY_INT_MODE_MASK_FLAG 0x300
3897#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 3946#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
3898#define PHY_INT_MODE_LINK_READY_FLAG 0x200 3947#define PHY_INT_MODE_LINK_READY_FLAG 0x200
@@ -3901,6 +3950,7 @@ struct bnx2 {
3901 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 3950 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
3902#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) 3951#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
3903#define CHIP_NUM_5706 0x57060000 3952#define CHIP_NUM_5706 0x57060000
3953#define CHIP_NUM_5708 0x57080000
3904 3954
3905#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) 3955#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
3906#define CHIP_REV_Ax 0x00000000 3956#define CHIP_REV_Ax 0x00000000
@@ -3913,6 +3963,9 @@ struct bnx2 {
3913#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) 3963#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
3914#define CHIP_ID_5706_A0 0x57060000 3964#define CHIP_ID_5706_A0 0x57060000
3915#define CHIP_ID_5706_A1 0x57060010 3965#define CHIP_ID_5706_A1 0x57060010
3966#define CHIP_ID_5706_A2 0x57060020
3967#define CHIP_ID_5708_A0 0x57080000
3968#define CHIP_ID_5708_B0 0x57081000
3916 3969
3917#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf) 3970#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
3918 3971
@@ -4132,12 +4185,12 @@ struct fw_info {
4132#define BNX2_LINK_STATUS 0x0000000c 4185#define BNX2_LINK_STATUS 0x0000000c
4133 4186
4134#define BNX2_DRV_PULSE_MB 0x00000010 4187#define BNX2_DRV_PULSE_MB 0x00000010
4135#define BNX2_DRV_PULSE_SEQ_MASK 0x0000ffff 4188#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
4136 4189
4137/* Indicate to the firmware not to go into the 4190/* Indicate to the firmware not to go into the
4138 * OS absent when it is not getting driver pulse. 4191 * OS absent when it is not getting driver pulse.
4139 * This is used for debugging. */ 4192 * This is used for debugging. */
4140#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00010000 4193#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
4141 4194
4142#define BNX2_DEV_INFO_SIGNATURE 0x00000020 4195#define BNX2_DEV_INFO_SIGNATURE 0x00000020
4143#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900 4196#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
@@ -4160,6 +4213,8 @@ struct fw_info {
4160#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1 4213#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
4161#define BNX2_SHARED_HW_CFG_PHY_COPPER 0 4214#define BNX2_SHARED_HW_CFG_PHY_COPPER 0
4162#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2 4215#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
4216#define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
4217#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
4163#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 4218#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
4164#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300 4219#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
4165#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0 4220#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
@@ -4173,9 +4228,11 @@ struct fw_info {
4173 4228
4174#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054 4229#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
4175#define BNX2_PORT_HW_CFG_CONFIG 0x00000058 4230#define BNX2_PORT_HW_CFG_CONFIG 0x00000058
4231#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
4176#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 4232#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
4177#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 4233#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
4178#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 4234#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
4235#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
4179 4236
4180#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 4237#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
4181#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 4238#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 16:19:19 -0500