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-rw-r--r--drivers/net/davinci_emac.c12
-rw-r--r--drivers/net/fec.h12
-rw-r--r--drivers/net/igb/e1000_82575.c4
-rw-r--r--drivers/net/r6040.c9
4 files changed, 26 insertions, 11 deletions
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 2df8fb0af701..12fd446f9895 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -1820,11 +1820,19 @@ static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1820 struct device *emac_dev = &priv->ndev->dev; 1820 struct device *emac_dev = &priv->ndev->dev;
1821 struct sockaddr *sa = addr; 1821 struct sockaddr *sa = addr;
1822 1822
1823 if (!is_valid_ether_addr(sa->sa_data))
1824 return -EINVAL;
1825
1823 /* Store mac addr in priv and rx channel and set it in EMAC hw */ 1826 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1824 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1827 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1825 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1826 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); 1828 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1827 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr); 1829
1830 /* If the interface is down - rxch is NULL. */
1831 /* MAC address is configured only after the interface is enabled. */
1832 if (netif_running(ndev)) {
1833 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1834 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1835 }
1828 1836
1829 if (netif_msg_drv(priv)) 1837 if (netif_msg_drv(priv))
1830 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", 1838 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
diff --git a/drivers/net/fec.h b/drivers/net/fec.h
index 30b7dd671336..cc47f3f057c7 100644
--- a/drivers/net/fec.h
+++ b/drivers/net/fec.h
@@ -46,12 +46,12 @@
46 46
47#else 47#else
48 48
49#define FEC_ECNTRL; 0x000 /* Ethernet control reg */ 49#define FEC_ECNTRL 0x000 /* Ethernet control reg */
50#define FEC_IEVENT; 0x004 /* Interrupt even reg */ 50#define FEC_IEVENT 0x004 /* Interrupt even reg */
51#define FEC_IMASK; 0x008 /* Interrupt mask reg */ 51#define FEC_IMASK 0x008 /* Interrupt mask reg */
52#define FEC_IVEC; 0x00c /* Interrupt vec status reg */ 52#define FEC_IVEC 0x00c /* Interrupt vec status reg */
53#define FEC_R_DES_ACTIVE; 0x010 /* Receive descriptor reg */ 53#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
54#define FEC_X_DES_ACTIVE; 0x01c /* Transmit descriptor reg */ 54#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
55#define FEC_MII_DATA 0x040 /* MII manage frame reg */ 55#define FEC_MII_DATA 0x040 /* MII manage frame reg */
56#define FEC_MII_SPEED 0x044 /* MII speed control reg */ 56#define FEC_MII_SPEED 0x044 /* MII speed control reg */
57#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 57#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index efd9be214885..ac28dd5a4fd1 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -190,6 +190,10 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
190 phy->ops.write_reg = igb_write_phy_reg_igp; 190 phy->ops.write_reg = igb_write_phy_reg_igp;
191 } 191 }
192 192
193 /* set lan id */
194 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
195 E1000_STATUS_FUNC_SHIFT;
196
193 /* Set phy->phy_addr and phy->id. */ 197 /* Set phy->phy_addr and phy->id. */
194 ret_val = igb_get_phy_id_82575(hw); 198 ret_val = igb_get_phy_id_82575(hw);
195 if (ret_val) 199 if (ret_val)
diff --git a/drivers/net/r6040.c b/drivers/net/r6040.c
index ed63d23a6452..961b5397a531 100644
--- a/drivers/net/r6040.c
+++ b/drivers/net/r6040.c
@@ -49,8 +49,8 @@
49#include <asm/processor.h> 49#include <asm/processor.h>
50 50
51#define DRV_NAME "r6040" 51#define DRV_NAME "r6040"
52#define DRV_VERSION "0.23" 52#define DRV_VERSION "0.24"
53#define DRV_RELDATE "05May2009" 53#define DRV_RELDATE "08Jul2009"
54 54
55/* PHY CHIP Address */ 55/* PHY CHIP Address */
56#define PHY1_ADDR 1 /* For MAC1 */ 56#define PHY1_ADDR 1 /* For MAC1 */
@@ -704,8 +704,11 @@ static irqreturn_t r6040_interrupt(int irq, void *dev_id)
704 /* Read MISR status and clear */ 704 /* Read MISR status and clear */
705 status = ioread16(ioaddr + MISR); 705 status = ioread16(ioaddr + MISR);
706 706
707 if (status == 0x0000 || status == 0xffff) 707 if (status == 0x0000 || status == 0xffff) {
708 /* Restore RDC MAC interrupt */
709 iowrite16(misr, ioaddr + MIER);
708 return IRQ_NONE; 710 return IRQ_NONE;
711 }
709 712
710 /* RX interrupt request */ 713 /* RX interrupt request */
711 if (status & RX_INTS) { 714 if (status & RX_INTS) {