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-rw-r--r--drivers/net/cxgb3/common.h7
-rw-r--r--drivers/net/cxgb3/cxgb3_main.c16
-rw-r--r--drivers/net/cxgb3/cxgb3_offload.c14
-rw-r--r--drivers/net/cxgb3/regs.h6
-rw-r--r--drivers/net/cxgb3/xgmac.c107
-rw-r--r--drivers/net/myri10ge/myri10ge.c37
-rw-r--r--drivers/net/sc92031.c20
-rw-r--r--drivers/net/skge.c93
-rw-r--r--drivers/net/sky2.c12
-rw-r--r--drivers/net/tg3.c6
10 files changed, 208 insertions, 110 deletions
diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
index 97128d88eaef..8d1379633698 100644
--- a/drivers/net/cxgb3/common.h
+++ b/drivers/net/cxgb3/common.h
@@ -478,8 +478,11 @@ struct cmac {
478 struct adapter *adapter; 478 struct adapter *adapter;
479 unsigned int offset; 479 unsigned int offset;
480 unsigned int nucast; /* # of address filters for unicast MACs */ 480 unsigned int nucast; /* # of address filters for unicast MACs */
481 unsigned int tcnt; 481 unsigned int tx_tcnt;
482 unsigned int xcnt; 482 unsigned int tx_xcnt;
483 u64 tx_mcnt;
484 unsigned int rx_xcnt;
485 u64 rx_mcnt;
483 unsigned int toggle_cnt; 486 unsigned int toggle_cnt;
484 unsigned int txen; 487 unsigned int txen;
485 struct mac_stats stats; 488 struct mac_stats stats;
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index 26240fd5e768..67b4b219d927 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -194,15 +194,13 @@ void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
194 194
195 if (link_stat != netif_carrier_ok(dev)) { 195 if (link_stat != netif_carrier_ok(dev)) {
196 if (link_stat) { 196 if (link_stat) {
197 t3_set_reg_field(adapter, 197 t3_mac_enable(mac, MAC_DIRECTION_RX);
198 A_XGM_TXFIFO_CFG + mac->offset,
199 F_ENDROPPKT, 0);
200 netif_carrier_on(dev); 198 netif_carrier_on(dev);
201 } else { 199 } else {
202 netif_carrier_off(dev); 200 netif_carrier_off(dev);
203 t3_set_reg_field(adapter, 201 pi->phy.ops->power_down(&pi->phy, 1);
204 A_XGM_TXFIFO_CFG + mac->offset, 202 t3_mac_disable(mac, MAC_DIRECTION_RX);
205 F_ENDROPPKT, F_ENDROPPKT); 203 t3_link_start(&pi->phy, mac, &pi->link_config);
206 } 204 }
207 205
208 link_report(dev); 206 link_report(dev);
@@ -772,6 +770,8 @@ static int cxgb_up(struct adapter *adap)
772 if (err) 770 if (err)
773 goto out; 771 goto out;
774 772
773 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
774
775 err = setup_sge_qsets(adap); 775 err = setup_sge_qsets(adap);
776 if (err) 776 if (err)
777 goto out; 777 goto out;
@@ -2119,7 +2119,9 @@ static void check_t3b2_mac(struct adapter *adapter)
2119{ 2119{
2120 int i; 2120 int i;
2121 2121
2122 rtnl_lock(); /* synchronize with ifdown */ 2122 if (!rtnl_trylock()) /* synchronize with ifdown */
2123 return;
2124
2123 for_each_port(adapter, i) { 2125 for_each_port(adapter, i) {
2124 struct net_device *dev = adapter->port[i]; 2126 struct net_device *dev = adapter->port[i];
2125 struct port_info *p = netdev_priv(dev); 2127 struct port_info *p = netdev_priv(dev);
diff --git a/drivers/net/cxgb3/cxgb3_offload.c b/drivers/net/cxgb3/cxgb3_offload.c
index eed7a48e3111..48649244673e 100644
--- a/drivers/net/cxgb3/cxgb3_offload.c
+++ b/drivers/net/cxgb3/cxgb3_offload.c
@@ -743,17 +743,6 @@ static int do_act_establish(struct t3cdev *dev, struct sk_buff *skb)
743 } 743 }
744} 744}
745 745
746static int do_set_tcb_rpl(struct t3cdev *dev, struct sk_buff *skb)
747{
748 struct cpl_set_tcb_rpl *rpl = cplhdr(skb);
749
750 if (rpl->status != CPL_ERR_NONE)
751 printk(KERN_ERR
752 "Unexpected SET_TCB_RPL status %u for tid %u\n",
753 rpl->status, GET_TID(rpl));
754 return CPL_RET_BUF_DONE;
755}
756
757static int do_trace(struct t3cdev *dev, struct sk_buff *skb) 746static int do_trace(struct t3cdev *dev, struct sk_buff *skb)
758{ 747{
759 struct cpl_trace_pkt *p = cplhdr(skb); 748 struct cpl_trace_pkt *p = cplhdr(skb);
@@ -1215,7 +1204,8 @@ void __init cxgb3_offload_init(void)
1215 t3_register_cpl_handler(CPL_CLOSE_CON_RPL, do_hwtid_rpl); 1204 t3_register_cpl_handler(CPL_CLOSE_CON_RPL, do_hwtid_rpl);
1216 t3_register_cpl_handler(CPL_ABORT_REQ_RSS, do_abort_req_rss); 1205 t3_register_cpl_handler(CPL_ABORT_REQ_RSS, do_abort_req_rss);
1217 t3_register_cpl_handler(CPL_ACT_ESTABLISH, do_act_establish); 1206 t3_register_cpl_handler(CPL_ACT_ESTABLISH, do_act_establish);
1218 t3_register_cpl_handler(CPL_SET_TCB_RPL, do_set_tcb_rpl); 1207 t3_register_cpl_handler(CPL_SET_TCB_RPL, do_hwtid_rpl);
1208 t3_register_cpl_handler(CPL_GET_TCB_RPL, do_hwtid_rpl);
1219 t3_register_cpl_handler(CPL_RDMA_TERMINATE, do_term); 1209 t3_register_cpl_handler(CPL_RDMA_TERMINATE, do_term);
1220 t3_register_cpl_handler(CPL_RDMA_EC_STATUS, do_hwtid_rpl); 1210 t3_register_cpl_handler(CPL_RDMA_EC_STATUS, do_hwtid_rpl);
1221 t3_register_cpl_handler(CPL_TRACE_PKT, do_trace); 1211 t3_register_cpl_handler(CPL_TRACE_PKT, do_trace);
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
index f8be41c5a081..e5a553410e24 100644
--- a/drivers/net/cxgb3/regs.h
+++ b/drivers/net/cxgb3/regs.h
@@ -1234,9 +1234,15 @@
1234 1234
1235#define A_ULPRX_ISCSI_TAGMASK 0x514 1235#define A_ULPRX_ISCSI_TAGMASK 0x514
1236 1236
1237#define S_HPZ0 0
1238#define M_HPZ0 0xf
1239#define V_HPZ0(x) ((x) << S_HPZ0)
1240#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1241
1237#define A_ULPRX_TDDP_LLIMIT 0x51c 1242#define A_ULPRX_TDDP_LLIMIT 0x51c
1238 1243
1239#define A_ULPRX_TDDP_ULIMIT 0x520 1244#define A_ULPRX_TDDP_ULIMIT 0x520
1245#define A_ULPRX_TDDP_PSZ 0x528
1240 1246
1241#define A_ULPRX_STAG_LLIMIT 0x52c 1247#define A_ULPRX_STAG_LLIMIT 0x52c
1242 1248
diff --git a/drivers/net/cxgb3/xgmac.c b/drivers/net/cxgb3/xgmac.c
index 94aaff005a35..a506792f9575 100644
--- a/drivers/net/cxgb3/xgmac.c
+++ b/drivers/net/cxgb3/xgmac.c
@@ -367,7 +367,8 @@ int t3_mac_enable(struct cmac *mac, int which)
367 int idx = macidx(mac); 367 int idx = macidx(mac);
368 struct adapter *adap = mac->adapter; 368 struct adapter *adap = mac->adapter;
369 unsigned int oft = mac->offset; 369 unsigned int oft = mac->offset;
370 370 struct mac_stats *s = &mac->stats;
371
371 if (which & MAC_DIRECTION_TX) { 372 if (which & MAC_DIRECTION_TX) {
372 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); 373 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
373 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); 374 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
@@ -376,10 +377,16 @@ int t3_mac_enable(struct cmac *mac, int which)
376 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx); 377 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
377 378
378 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx); 379 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
379 mac->tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, 380 mac->tx_mcnt = s->tx_frames;
380 A_TP_PIO_DATA))); 381 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
381 mac->xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, 382 A_TP_PIO_DATA)));
382 A_XGM_TX_SPI4_SOP_EOP_CNT))); 383 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
384 A_XGM_TX_SPI4_SOP_EOP_CNT +
385 oft)));
386 mac->rx_mcnt = s->rx_frames;
387 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
388 A_XGM_RX_SPI4_SOP_EOP_CNT +
389 oft)));
383 mac->txen = F_TXEN; 390 mac->txen = F_TXEN;
384 mac->toggle_cnt = 0; 391 mac->toggle_cnt = 0;
385 } 392 }
@@ -392,6 +399,7 @@ int t3_mac_disable(struct cmac *mac, int which)
392{ 399{
393 int idx = macidx(mac); 400 int idx = macidx(mac);
394 struct adapter *adap = mac->adapter; 401 struct adapter *adap = mac->adapter;
402 int val;
395 403
396 if (which & MAC_DIRECTION_TX) { 404 if (which & MAC_DIRECTION_TX) {
397 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); 405 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
@@ -401,44 +409,89 @@ int t3_mac_disable(struct cmac *mac, int which)
401 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx); 409 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
402 mac->txen = 0; 410 mac->txen = 0;
403 } 411 }
404 if (which & MAC_DIRECTION_RX) 412 if (which & MAC_DIRECTION_RX) {
413 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
414 F_PCS_RESET_, 0);
415 msleep(100);
405 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0); 416 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
417 val = F_MAC_RESET_;
418 if (is_10G(adap))
419 val |= F_PCS_RESET_;
420 else if (uses_xaui(adap))
421 val |= F_PCS_RESET_ | F_XG2G_RESET_;
422 else
423 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
424 t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val);
425 }
406 return 0; 426 return 0;
407} 427}
408 428
409int t3b2_mac_watchdog_task(struct cmac *mac) 429int t3b2_mac_watchdog_task(struct cmac *mac)
410{ 430{
411 struct adapter *adap = mac->adapter; 431 struct adapter *adap = mac->adapter;
412 unsigned int tcnt, xcnt; 432 struct mac_stats *s = &mac->stats;
433 unsigned int tx_tcnt, tx_xcnt;
434 unsigned int tx_mcnt = s->tx_frames;
435 unsigned int rx_mcnt = s->rx_frames;
436 unsigned int rx_xcnt;
413 int status; 437 int status;
414 438
415 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + macidx(mac)); 439 if (tx_mcnt == mac->tx_mcnt) {
416 tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, A_TP_PIO_DATA))); 440 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
417 xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, 441 A_XGM_TX_SPI4_SOP_EOP_CNT +
418 A_XGM_TX_SPI4_SOP_EOP_CNT + 442 mac->offset)));
419 mac->offset))); 443 if (tx_xcnt == 0) {
420 444 t3_write_reg(adap, A_TP_PIO_ADDR,
421 if (tcnt != mac->tcnt && xcnt == 0 && mac->xcnt == 0) { 445 A_TP_TX_DROP_CNT_CH0 + macidx(mac));
422 if (mac->toggle_cnt > 4) { 446 tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
423 t3b2_mac_reset(mac); 447 A_TP_PIO_DATA)));
448 } else {
424 mac->toggle_cnt = 0; 449 mac->toggle_cnt = 0;
450 return 0;
451 }
452 } else {
453 mac->toggle_cnt = 0;
454 return 0;
455 }
456
457 if (((tx_tcnt != mac->tx_tcnt) &&
458 (tx_xcnt == 0) && (mac->tx_xcnt == 0)) ||
459 ((mac->tx_mcnt == tx_mcnt) &&
460 (tx_xcnt != 0) && (mac->tx_xcnt != 0))) {
461 if (mac->toggle_cnt > 4)
425 status = 2; 462 status = 2;
426 } else { 463 else
427 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
428 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);
429 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset,
430 mac->txen);
431 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);
432 mac->toggle_cnt++;
433 status = 1; 464 status = 1;
434 }
435 } else { 465 } else {
436 mac->toggle_cnt = 0; 466 mac->toggle_cnt = 0;
437 status = 0; 467 return 0;
438 } 468 }
439 mac->tcnt = tcnt;
440 mac->xcnt = xcnt;
441 469
470 if (rx_mcnt != mac->rx_mcnt)
471 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
472 A_XGM_RX_SPI4_SOP_EOP_CNT +
473 mac->offset)));
474 else
475 return 0;
476
477 if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0)
478 status = 2;
479
480 mac->tx_tcnt = tx_tcnt;
481 mac->tx_xcnt = tx_xcnt;
482 mac->tx_mcnt = s->tx_frames;
483 mac->rx_xcnt = rx_xcnt;
484 mac->rx_mcnt = s->rx_frames;
485 if (status == 1) {
486 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
487 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
488 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
489 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
490 mac->toggle_cnt++;
491 } else if (status == 2) {
492 t3b2_mac_reset(mac);
493 mac->toggle_cnt = 0;
494 }
442 return status; 495 return status;
443} 496}
444 497
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index c216e6a5d235..f8efe0e70a6b 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -71,7 +71,7 @@
71#include "myri10ge_mcp.h" 71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h" 72#include "myri10ge_mcp_gen_header.h"
73 73
74#define MYRI10GE_VERSION_STR "1.3.0-1.227" 74#define MYRI10GE_VERSION_STR "1.3.0-1.233"
75 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); 76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com"); 77MODULE_AUTHOR("Maintainer: help@myri.com");
@@ -900,19 +900,9 @@ myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
900 /* try to refill entire ring */ 900 /* try to refill entire ring */
901 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) { 901 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
902 idx = rx->fill_cnt & rx->mask; 902 idx = rx->fill_cnt & rx->mask;
903 903 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
904 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
905 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
906 /* we can use part of previous page */ 904 /* we can use part of previous page */
907 get_page(rx->page); 905 get_page(rx->page);
908#if MYRI10GE_ALLOC_SIZE > 4096
909 /* Firmware cannot cross 4K boundary.. */
910 if ((rx->page_offset >> 12) !=
911 ((rx->page_offset + bytes - 1) >> 12)) {
912 rx->page_offset =
913 (rx->page_offset + bytes) & ~4095;
914 }
915#endif
916 } else { 906 } else {
917 /* we need a new page */ 907 /* we need a new page */
918 page = 908 page =
@@ -941,6 +931,13 @@ myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
941 931
942 /* start next packet on a cacheline boundary */ 932 /* start next packet on a cacheline boundary */
943 rx->page_offset += SKB_DATA_ALIGN(bytes); 933 rx->page_offset += SKB_DATA_ALIGN(bytes);
934
935#if MYRI10GE_ALLOC_SIZE > 4096
936 /* don't cross a 4KB boundary */
937 if ((rx->page_offset >> 12) !=
938 ((rx->page_offset + bytes - 1) >> 12))
939 rx->page_offset = (rx->page_offset + 4096) & ~4095;
940#endif
944 rx->fill_cnt++; 941 rx->fill_cnt++;
945 942
946 /* copy 8 descriptors to the firmware at a time */ 943 /* copy 8 descriptors to the firmware at a time */
@@ -2490,6 +2487,10 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2490 2487
2491#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7 2488#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2492#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa 2489#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
2490#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1 0x3510
2491#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4 0x351b
2492#define PCI_DEVICE_ID_INTEL_E3000_PCIE 0x2779
2493#define PCI_DEVICE_ID_INTEL_E3010_PCIE 0x277a
2493#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140 2494#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
2494#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142 2495#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
2495 2496
@@ -2529,6 +2530,18 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2529 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 2530 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
2530 && bridge->device <= 2531 && bridge->device <=
2531 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST) 2532 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
2533 /* All Intel E3000/E3010 PCIE ports */
2534 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2535 && (bridge->device ==
2536 PCI_DEVICE_ID_INTEL_E3000_PCIE
2537 || bridge->device ==
2538 PCI_DEVICE_ID_INTEL_E3010_PCIE))
2539 /* All Intel 6310/6311/6321ESB PCIE ports */
2540 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2541 && bridge->device >=
2542 PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1
2543 && bridge->device <=
2544 PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)
2532 /* All Intel E5000 PCIE ports */ 2545 /* All Intel E5000 PCIE ports */
2533 || (bridge->vendor == PCI_VENDOR_ID_INTEL 2546 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2534 && bridge->device >= 2547 && bridge->device >=
diff --git a/drivers/net/sc92031.c b/drivers/net/sc92031.c
index 4a926f20b6ea..c32c21af3fdd 100644
--- a/drivers/net/sc92031.c
+++ b/drivers/net/sc92031.c
@@ -964,7 +964,7 @@ static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
964 goto out; 964 goto out;
965 } 965 }
966 966
967 spin_lock_bh(&priv->lock); 967 spin_lock(&priv->lock);
968 968
969 if (unlikely(!netif_carrier_ok(dev))) { 969 if (unlikely(!netif_carrier_ok(dev))) {
970 err = -ENOLINK; 970 err = -ENOLINK;
@@ -1005,7 +1005,7 @@ static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
1005 netif_stop_queue(dev); 1005 netif_stop_queue(dev);
1006 1006
1007out_unlock: 1007out_unlock:
1008 spin_unlock_bh(&priv->lock); 1008 spin_unlock(&priv->lock);
1009 1009
1010out: 1010out:
1011 dev_kfree_skb(skb); 1011 dev_kfree_skb(skb);
@@ -1042,12 +1042,12 @@ static int sc92031_open(struct net_device *dev)
1042 priv->pm_config = 0; 1042 priv->pm_config = 0;
1043 1043
1044 /* Interrupts already disabled by sc92031_stop or sc92031_probe */ 1044 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1045 spin_lock(&priv->lock); 1045 spin_lock_bh(&priv->lock);
1046 1046
1047 _sc92031_reset(dev); 1047 _sc92031_reset(dev);
1048 mmiowb(); 1048 mmiowb();
1049 1049
1050 spin_unlock(&priv->lock); 1050 spin_unlock_bh(&priv->lock);
1051 sc92031_enable_interrupts(dev); 1051 sc92031_enable_interrupts(dev);
1052 1052
1053 if (netif_carrier_ok(dev)) 1053 if (netif_carrier_ok(dev))
@@ -1077,13 +1077,13 @@ static int sc92031_stop(struct net_device *dev)
1077 /* Disable interrupts, stop Tx and Rx. */ 1077 /* Disable interrupts, stop Tx and Rx. */
1078 sc92031_disable_interrupts(dev); 1078 sc92031_disable_interrupts(dev);
1079 1079
1080 spin_lock(&priv->lock); 1080 spin_lock_bh(&priv->lock);
1081 1081
1082 _sc92031_disable_tx_rx(dev); 1082 _sc92031_disable_tx_rx(dev);
1083 _sc92031_tx_clear(dev); 1083 _sc92031_tx_clear(dev);
1084 mmiowb(); 1084 mmiowb();
1085 1085
1086 spin_unlock(&priv->lock); 1086 spin_unlock_bh(&priv->lock);
1087 1087
1088 free_irq(pdev->irq, dev); 1088 free_irq(pdev->irq, dev);
1089 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs, 1089 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
@@ -1539,13 +1539,13 @@ static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1539 /* Disable interrupts, stop Tx and Rx. */ 1539 /* Disable interrupts, stop Tx and Rx. */
1540 sc92031_disable_interrupts(dev); 1540 sc92031_disable_interrupts(dev);
1541 1541
1542 spin_lock(&priv->lock); 1542 spin_lock_bh(&priv->lock);
1543 1543
1544 _sc92031_disable_tx_rx(dev); 1544 _sc92031_disable_tx_rx(dev);
1545 _sc92031_tx_clear(dev); 1545 _sc92031_tx_clear(dev);
1546 mmiowb(); 1546 mmiowb();
1547 1547
1548 spin_unlock(&priv->lock); 1548 spin_unlock_bh(&priv->lock);
1549 1549
1550out: 1550out:
1551 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1551 pci_set_power_state(pdev, pci_choose_state(pdev, state));
@@ -1565,12 +1565,12 @@ static int sc92031_resume(struct pci_dev *pdev)
1565 goto out; 1565 goto out;
1566 1566
1567 /* Interrupts already disabled by sc92031_suspend */ 1567 /* Interrupts already disabled by sc92031_suspend */
1568 spin_lock(&priv->lock); 1568 spin_lock_bh(&priv->lock);
1569 1569
1570 _sc92031_reset(dev); 1570 _sc92031_reset(dev);
1571 mmiowb(); 1571 mmiowb();
1572 1572
1573 spin_unlock(&priv->lock); 1573 spin_unlock_bh(&priv->lock);
1574 sc92031_enable_interrupts(dev); 1574 sc92031_enable_interrupts(dev);
1575 1575
1576 netif_device_attach(dev); 1576 netif_device_attach(dev);
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 39c6677dff5e..d476a3cc2e94 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -163,27 +163,46 @@ static void skge_wol_init(struct skge_port *skge)
163{ 163{
164 struct skge_hw *hw = skge->hw; 164 struct skge_hw *hw = skge->hw;
165 int port = skge->port; 165 int port = skge->port;
166 enum pause_control save_mode; 166 u16 ctrl;
167 u32 ctrl;
168 167
169 /* Bring hardware out of reset */
170 skge_write16(hw, B0_CTST, CS_RST_CLR); 168 skge_write16(hw, B0_CTST, CS_RST_CLR);
171 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 169 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
172 170
173 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 171 /* Turn on Vaux */
174 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 172 skge_write8(hw, B0_POWER_CTRL,
173 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
175 174
176 /* Force to 10/100 skge_reset will re-enable on resume */ 175 /* WA code for COMA mode -- clear PHY reset */
177 save_mode = skge->flow_control; 176 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
178 skge->flow_control = FLOW_MODE_SYMMETRIC; 177 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
178 u32 reg = skge_read32(hw, B2_GP_IO);
179 reg |= GP_DIR_9;
180 reg &= ~GP_IO_9;
181 skge_write32(hw, B2_GP_IO, reg);
182 }
179 183
180 ctrl = skge->advertising; 184 skge_write32(hw, SK_REG(port, GPHY_CTRL),
181 skge->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 185 GPC_DIS_SLEEP |
186 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
187 GPC_ANEG_1 | GPC_RST_SET);
182 188
183 skge_phy_reset(skge); 189 skge_write32(hw, SK_REG(port, GPHY_CTRL),
190 GPC_DIS_SLEEP |
191 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
192 GPC_ANEG_1 | GPC_RST_CLR);
193
194 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
195
196 /* Force to 10/100 skge_reset will re-enable on resume */
197 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
198 PHY_AN_100FULL | PHY_AN_100HALF |
199 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
200 /* no 1000 HD/FD */
201 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
202 gm_phy_write(hw, port, PHY_MARV_CTRL,
203 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
204 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
184 205
185 skge->flow_control = save_mode;
186 skge->advertising = ctrl;
187 206
188 /* Set GMAC to no flow control and auto update for speed/duplex */ 207 /* Set GMAC to no flow control and auto update for speed/duplex */
189 gma_write16(hw, port, GM_GP_CTRL, 208 gma_write16(hw, port, GM_GP_CTRL,
@@ -227,12 +246,10 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
227 struct skge_port *skge = netdev_priv(dev); 246 struct skge_port *skge = netdev_priv(dev);
228 struct skge_hw *hw = skge->hw; 247 struct skge_hw *hw = skge->hw;
229 248
230 if (wol->wolopts & wol_supported(hw)) 249 if (wol->wolopts & ~wol_supported(hw))
231 return -EOPNOTSUPP; 250 return -EOPNOTSUPP;
232 251
233 skge->wol = wol->wolopts; 252 skge->wol = wol->wolopts;
234 if (!netif_running(dev))
235 skge_wol_init(skge);
236 return 0; 253 return 0;
237} 254}
238 255
@@ -2535,10 +2552,12 @@ static int skge_down(struct net_device *dev)
2535 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); 2552 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2536 2553
2537 netif_stop_queue(dev); 2554 netif_stop_queue(dev);
2555
2538 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC) 2556 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2539 del_timer_sync(&skge->link_timer); 2557 del_timer_sync(&skge->link_timer);
2540 2558
2541 netif_poll_disable(dev); 2559 netif_poll_disable(dev);
2560 netif_carrier_off(dev);
2542 2561
2543 spin_lock_irq(&hw->hw_lock); 2562 spin_lock_irq(&hw->hw_lock);
2544 hw->intr_mask &= ~portmask[port]; 2563 hw->intr_mask &= ~portmask[port];
@@ -3765,21 +3784,6 @@ static void __devexit skge_remove(struct pci_dev *pdev)
3765} 3784}
3766 3785
3767#ifdef CONFIG_PM 3786#ifdef CONFIG_PM
3768static int vaux_avail(struct pci_dev *pdev)
3769{
3770 int pm_cap;
3771
3772 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3773 if (pm_cap) {
3774 u16 ctl;
3775 pci_read_config_word(pdev, pm_cap + PCI_PM_PMC, &ctl);
3776 if (ctl & PCI_PM_CAP_AUX_POWER)
3777 return 1;
3778 }
3779 return 0;
3780}
3781
3782
3783static int skge_suspend(struct pci_dev *pdev, pm_message_t state) 3787static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3784{ 3788{
3785 struct skge_hw *hw = pci_get_drvdata(pdev); 3789 struct skge_hw *hw = pci_get_drvdata(pdev);
@@ -3801,10 +3805,6 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3801 wol |= skge->wol; 3805 wol |= skge->wol;
3802 } 3806 }
3803 3807
3804 if (wol && vaux_avail(pdev))
3805 skge_write8(hw, B0_POWER_CTRL,
3806 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
3807
3808 skge_write32(hw, B0_IMSK, 0); 3808 skge_write32(hw, B0_IMSK, 0);
3809 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); 3809 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3810 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 3810 pci_set_power_state(pdev, pci_choose_state(pdev, state));
@@ -3850,6 +3850,28 @@ out:
3850} 3850}
3851#endif 3851#endif
3852 3852
3853static void skge_shutdown(struct pci_dev *pdev)
3854{
3855 struct skge_hw *hw = pci_get_drvdata(pdev);
3856 int i, wol = 0;
3857
3858 for (i = 0; i < hw->ports; i++) {
3859 struct net_device *dev = hw->dev[i];
3860 struct skge_port *skge = netdev_priv(dev);
3861
3862 if (skge->wol)
3863 skge_wol_init(skge);
3864 wol |= skge->wol;
3865 }
3866
3867 pci_enable_wake(pdev, PCI_D3hot, wol);
3868 pci_enable_wake(pdev, PCI_D3cold, wol);
3869
3870 pci_disable_device(pdev);
3871 pci_set_power_state(pdev, PCI_D3hot);
3872
3873}
3874
3853static struct pci_driver skge_driver = { 3875static struct pci_driver skge_driver = {
3854 .name = DRV_NAME, 3876 .name = DRV_NAME,
3855 .id_table = skge_id_table, 3877 .id_table = skge_id_table,
@@ -3859,6 +3881,7 @@ static struct pci_driver skge_driver = {
3859 .suspend = skge_suspend, 3881 .suspend = skge_suspend,
3860 .resume = skge_resume, 3882 .resume = skge_resume,
3861#endif 3883#endif
3884 .shutdown = skge_shutdown,
3862}; 3885};
3863 3886
3864static int __init skge_init_module(void) 3887static int __init skge_init_module(void)
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index ab0ab92583fe..4a009b7b1777 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -510,9 +510,9 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
510 ledover &= ~PHY_M_LED_MO_RX; 510 ledover &= ~PHY_M_LED_MO_RX;
511 } 511 }
512 512
513 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) { 513 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
514 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
514 /* apply fixes in PHY AFE */ 515 /* apply fixes in PHY AFE */
515 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
517 517
518 /* increase differential signal amplitude in 10BASE-T */ 518 /* increase differential signal amplitude in 10BASE-T */
@@ -524,7 +524,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
524 gm_phy_write(hw, port, 0x17, 0x2002); 524 gm_phy_write(hw, port, 0x17, 0x2002);
525 525
526 /* set page register to 0 */ 526 /* set page register to 0 */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
528 } else if (hw->chip_id != CHIP_ID_YUKON_EX) { 528 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
529 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 529 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
530 530
@@ -1561,6 +1561,7 @@ static int sky2_down(struct net_device *dev)
1561 1561
1562 /* Stop more packets from being queued */ 1562 /* Stop more packets from being queued */
1563 netif_stop_queue(dev); 1563 netif_stop_queue(dev);
1564 netif_carrier_off(dev);
1564 1565
1565 /* Disable port IRQ */ 1566 /* Disable port IRQ */
1566 imask = sky2_read32(hw, B0_IMSK); 1567 imask = sky2_read32(hw, B0_IMSK);
@@ -3769,6 +3770,11 @@ static int sky2_resume(struct pci_dev *pdev)
3769 goto out; 3770 goto out;
3770 3771
3771 pci_enable_wake(pdev, PCI_D0, 0); 3772 pci_enable_wake(pdev, PCI_D0, 0);
3773
3774 /* Re-enable all clocks */
3775 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3776 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3777
3772 sky2_reset(hw); 3778 sky2_reset(hw);
3773 3779
3774 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 3780 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 0acee9f324e9..256969e1300c 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4834,8 +4834,10 @@ static int tg3_chip_reset(struct tg3 *tp)
4834 * sharing or irqpoll. 4834 * sharing or irqpoll.
4835 */ 4835 */
4836 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; 4836 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4837 tp->hw_status->status = 0; 4837 if (tp->hw_status) {
4838 tp->hw_status->status_tag = 0; 4838 tp->hw_status->status = 0;
4839 tp->hw_status->status_tag = 0;
4840 }
4839 tp->last_tag = 0; 4841 tp->last_tag = 0;
4840 smp_mb(); 4842 smp_mb();
4841 synchronize_irq(tp->pdev->irq); 4843 synchronize_irq(tp->pdev->irq);