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-rw-r--r--drivers/net/forcedeth.c312
-rw-r--r--drivers/net/hamradio/dmascc.c1
-rw-r--r--drivers/net/hamradio/scc.c1
-rw-r--r--drivers/net/hamradio/yam.c1
-rw-r--r--drivers/net/mv643xx_eth.c2
-rw-r--r--drivers/net/tg3.c82
-rw-r--r--drivers/net/tg3.h1
-rw-r--r--drivers/net/via-rhine.c6
8 files changed, 293 insertions, 113 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 9788b1ef2e7d..f7235c9bc421 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -106,6 +106,7 @@
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings. 106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support. 107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. 108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 110 *
110 * Known bugs: 111 * Known bugs:
111 * We suspect that on some hardware no TX done interrupts are generated. 112 * We suspect that on some hardware no TX done interrupts are generated.
@@ -117,7 +118,7 @@
117 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 118 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
118 * superfluous timer interrupts from the nic. 119 * superfluous timer interrupts from the nic.
119 */ 120 */
120#define FORCEDETH_VERSION "0.53" 121#define FORCEDETH_VERSION "0.54"
121#define DRV_NAME "forcedeth" 122#define DRV_NAME "forcedeth"
122 123
123#include <linux/module.h> 124#include <linux/module.h>
@@ -710,6 +711,72 @@ static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
710 } 711 }
711} 712}
712 713
714static int using_multi_irqs(struct net_device *dev)
715{
716 struct fe_priv *np = get_nvpriv(dev);
717
718 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
719 ((np->msi_flags & NV_MSI_X_ENABLED) &&
720 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
721 return 0;
722 else
723 return 1;
724}
725
726static void nv_enable_irq(struct net_device *dev)
727{
728 struct fe_priv *np = get_nvpriv(dev);
729
730 if (!using_multi_irqs(dev)) {
731 if (np->msi_flags & NV_MSI_X_ENABLED)
732 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
733 else
734 enable_irq(dev->irq);
735 } else {
736 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
737 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
738 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
739 }
740}
741
742static void nv_disable_irq(struct net_device *dev)
743{
744 struct fe_priv *np = get_nvpriv(dev);
745
746 if (!using_multi_irqs(dev)) {
747 if (np->msi_flags & NV_MSI_X_ENABLED)
748 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
749 else
750 disable_irq(dev->irq);
751 } else {
752 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
753 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
754 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
755 }
756}
757
758/* In MSIX mode, a write to irqmask behaves as XOR */
759static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
760{
761 u8 __iomem *base = get_hwbase(dev);
762
763 writel(mask, base + NvRegIrqMask);
764}
765
766static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
767{
768 struct fe_priv *np = get_nvpriv(dev);
769 u8 __iomem *base = get_hwbase(dev);
770
771 if (np->msi_flags & NV_MSI_X_ENABLED) {
772 writel(mask, base + NvRegIrqMask);
773 } else {
774 if (np->msi_flags & NV_MSI_ENABLED)
775 writel(0, base + NvRegMSIIrqMask);
776 writel(0, base + NvRegIrqMask);
777 }
778}
779
713#define MII_READ (-1) 780#define MII_READ (-1)
714/* mii_rw: read/write a register on the PHY. 781/* mii_rw: read/write a register on the PHY.
715 * 782 *
@@ -1019,24 +1086,25 @@ static void nv_do_rx_refill(unsigned long data)
1019 struct net_device *dev = (struct net_device *) data; 1086 struct net_device *dev = (struct net_device *) data;
1020 struct fe_priv *np = netdev_priv(dev); 1087 struct fe_priv *np = netdev_priv(dev);
1021 1088
1022 1089 if (!using_multi_irqs(dev)) {
1023 if (!(np->msi_flags & NV_MSI_X_ENABLED) || 1090 if (np->msi_flags & NV_MSI_X_ENABLED)
1024 ((np->msi_flags & NV_MSI_X_ENABLED) && 1091 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1025 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { 1092 else
1026 disable_irq(dev->irq); 1093 disable_irq(dev->irq);
1027 } else { 1094 } else {
1028 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); 1095 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1029 } 1096 }
1030 if (nv_alloc_rx(dev)) { 1097 if (nv_alloc_rx(dev)) {
1031 spin_lock(&np->lock); 1098 spin_lock_irq(&np->lock);
1032 if (!np->in_shutdown) 1099 if (!np->in_shutdown)
1033 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); 1100 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1034 spin_unlock(&np->lock); 1101 spin_unlock_irq(&np->lock);
1035 } 1102 }
1036 if (!(np->msi_flags & NV_MSI_X_ENABLED) || 1103 if (!using_multi_irqs(dev)) {
1037 ((np->msi_flags & NV_MSI_X_ENABLED) && 1104 if (np->msi_flags & NV_MSI_X_ENABLED)
1038 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { 1105 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1039 enable_irq(dev->irq); 1106 else
1107 enable_irq(dev->irq);
1040 } else { 1108 } else {
1041 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); 1109 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1042 } 1110 }
@@ -1668,15 +1736,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
1668 * guessed, there is probably a simpler approach. 1736 * guessed, there is probably a simpler approach.
1669 * Changing the MTU is a rare event, it shouldn't matter. 1737 * Changing the MTU is a rare event, it shouldn't matter.
1670 */ 1738 */
1671 if (!(np->msi_flags & NV_MSI_X_ENABLED) || 1739 nv_disable_irq(dev);
1672 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1673 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
1674 disable_irq(dev->irq);
1675 } else {
1676 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1677 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1678 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1679 }
1680 spin_lock_bh(&dev->xmit_lock); 1740 spin_lock_bh(&dev->xmit_lock);
1681 spin_lock(&np->lock); 1741 spin_lock(&np->lock);
1682 /* stop engines */ 1742 /* stop engines */
@@ -1709,15 +1769,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
1709 nv_start_tx(dev); 1769 nv_start_tx(dev);
1710 spin_unlock(&np->lock); 1770 spin_unlock(&np->lock);
1711 spin_unlock_bh(&dev->xmit_lock); 1771 spin_unlock_bh(&dev->xmit_lock);
1712 if (!(np->msi_flags & NV_MSI_X_ENABLED) || 1772 nv_enable_irq(dev);
1713 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1714 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
1715 enable_irq(dev->irq);
1716 } else {
1717 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1718 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1719 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1720 }
1721 } 1773 }
1722 return 0; 1774 return 0;
1723} 1775}
@@ -2108,16 +2160,16 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2108 if (!(events & np->irqmask)) 2160 if (!(events & np->irqmask))
2109 break; 2161 break;
2110 2162
2111 spin_lock(&np->lock); 2163 spin_lock_irq(&np->lock);
2112 nv_tx_done(dev); 2164 nv_tx_done(dev);
2113 spin_unlock(&np->lock); 2165 spin_unlock_irq(&np->lock);
2114 2166
2115 if (events & (NVREG_IRQ_TX_ERR)) { 2167 if (events & (NVREG_IRQ_TX_ERR)) {
2116 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", 2168 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2117 dev->name, events); 2169 dev->name, events);
2118 } 2170 }
2119 if (i > max_interrupt_work) { 2171 if (i > max_interrupt_work) {
2120 spin_lock(&np->lock); 2172 spin_lock_irq(&np->lock);
2121 /* disable interrupts on the nic */ 2173 /* disable interrupts on the nic */
2122 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); 2174 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2123 pci_push(base); 2175 pci_push(base);
@@ -2127,7 +2179,7 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2127 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); 2179 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2128 } 2180 }
2129 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); 2181 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2130 spin_unlock(&np->lock); 2182 spin_unlock_irq(&np->lock);
2131 break; 2183 break;
2132 } 2184 }
2133 2185
@@ -2157,14 +2209,14 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2157 2209
2158 nv_rx_process(dev); 2210 nv_rx_process(dev);
2159 if (nv_alloc_rx(dev)) { 2211 if (nv_alloc_rx(dev)) {
2160 spin_lock(&np->lock); 2212 spin_lock_irq(&np->lock);
2161 if (!np->in_shutdown) 2213 if (!np->in_shutdown)
2162 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); 2214 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2163 spin_unlock(&np->lock); 2215 spin_unlock_irq(&np->lock);
2164 } 2216 }
2165 2217
2166 if (i > max_interrupt_work) { 2218 if (i > max_interrupt_work) {
2167 spin_lock(&np->lock); 2219 spin_lock_irq(&np->lock);
2168 /* disable interrupts on the nic */ 2220 /* disable interrupts on the nic */
2169 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); 2221 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2170 pci_push(base); 2222 pci_push(base);
@@ -2174,7 +2226,7 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2174 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); 2226 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2175 } 2227 }
2176 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); 2228 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2177 spin_unlock(&np->lock); 2229 spin_unlock_irq(&np->lock);
2178 break; 2230 break;
2179 } 2231 }
2180 2232
@@ -2203,14 +2255,14 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2203 break; 2255 break;
2204 2256
2205 if (events & NVREG_IRQ_LINK) { 2257 if (events & NVREG_IRQ_LINK) {
2206 spin_lock(&np->lock); 2258 spin_lock_irq(&np->lock);
2207 nv_link_irq(dev); 2259 nv_link_irq(dev);
2208 spin_unlock(&np->lock); 2260 spin_unlock_irq(&np->lock);
2209 } 2261 }
2210 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { 2262 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2211 spin_lock(&np->lock); 2263 spin_lock_irq(&np->lock);
2212 nv_linkchange(dev); 2264 nv_linkchange(dev);
2213 spin_unlock(&np->lock); 2265 spin_unlock_irq(&np->lock);
2214 np->link_timeout = jiffies + LINK_TIMEOUT; 2266 np->link_timeout = jiffies + LINK_TIMEOUT;
2215 } 2267 }
2216 if (events & (NVREG_IRQ_UNKNOWN)) { 2268 if (events & (NVREG_IRQ_UNKNOWN)) {
@@ -2218,7 +2270,7 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2218 dev->name, events); 2270 dev->name, events);
2219 } 2271 }
2220 if (i > max_interrupt_work) { 2272 if (i > max_interrupt_work) {
2221 spin_lock(&np->lock); 2273 spin_lock_irq(&np->lock);
2222 /* disable interrupts on the nic */ 2274 /* disable interrupts on the nic */
2223 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); 2275 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2224 pci_push(base); 2276 pci_push(base);
@@ -2228,7 +2280,7 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2228 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); 2280 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2229 } 2281 }
2230 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); 2282 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2231 spin_unlock(&np->lock); 2283 spin_unlock_irq(&np->lock);
2232 break; 2284 break;
2233 } 2285 }
2234 2286
@@ -2251,10 +2303,11 @@ static void nv_do_nic_poll(unsigned long data)
2251 * nv_nic_irq because that may decide to do otherwise 2303 * nv_nic_irq because that may decide to do otherwise
2252 */ 2304 */
2253 2305
2254 if (!(np->msi_flags & NV_MSI_X_ENABLED) || 2306 if (!using_multi_irqs(dev)) {
2255 ((np->msi_flags & NV_MSI_X_ENABLED) && 2307 if (np->msi_flags & NV_MSI_X_ENABLED)
2256 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { 2308 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2257 disable_irq(dev->irq); 2309 else
2310 disable_irq(dev->irq);
2258 mask = np->irqmask; 2311 mask = np->irqmask;
2259 } else { 2312 } else {
2260 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { 2313 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
@@ -2277,11 +2330,12 @@ static void nv_do_nic_poll(unsigned long data)
2277 writel(mask, base + NvRegIrqMask); 2330 writel(mask, base + NvRegIrqMask);
2278 pci_push(base); 2331 pci_push(base);
2279 2332
2280 if (!(np->msi_flags & NV_MSI_X_ENABLED) || 2333 if (!using_multi_irqs(dev)) {
2281 ((np->msi_flags & NV_MSI_X_ENABLED) &&
2282 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
2283 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL); 2334 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
2284 enable_irq(dev->irq); 2335 if (np->msi_flags & NV_MSI_X_ENABLED)
2336 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2337 else
2338 enable_irq(dev->irq);
2285 } else { 2339 } else {
2286 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { 2340 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2287 nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL); 2341 nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL);
@@ -2628,6 +2682,113 @@ static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2628 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); 2682 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2629} 2683}
2630 2684
2685static int nv_request_irq(struct net_device *dev)
2686{
2687 struct fe_priv *np = get_nvpriv(dev);
2688 u8 __iomem *base = get_hwbase(dev);
2689 int ret = 1;
2690 int i;
2691
2692 if (np->msi_flags & NV_MSI_X_CAPABLE) {
2693 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2694 np->msi_x_entry[i].entry = i;
2695 }
2696 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2697 np->msi_flags |= NV_MSI_X_ENABLED;
2698 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
2699 /* Request irq for rx handling */
2700 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) {
2701 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2702 pci_disable_msix(np->pci_dev);
2703 np->msi_flags &= ~NV_MSI_X_ENABLED;
2704 goto out_err;
2705 }
2706 /* Request irq for tx handling */
2707 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) {
2708 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2709 pci_disable_msix(np->pci_dev);
2710 np->msi_flags &= ~NV_MSI_X_ENABLED;
2711 goto out_free_rx;
2712 }
2713 /* Request irq for link and timer handling */
2714 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) {
2715 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2716 pci_disable_msix(np->pci_dev);
2717 np->msi_flags &= ~NV_MSI_X_ENABLED;
2718 goto out_free_tx;
2719 }
2720 /* map interrupts to their respective vector */
2721 writel(0, base + NvRegMSIXMap0);
2722 writel(0, base + NvRegMSIXMap1);
2723 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2724 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2725 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2726 } else {
2727 /* Request irq for all interrupts */
2728 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
2729 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2730 pci_disable_msix(np->pci_dev);
2731 np->msi_flags &= ~NV_MSI_X_ENABLED;
2732 goto out_err;
2733 }
2734
2735 /* map interrupts to vector 0 */
2736 writel(0, base + NvRegMSIXMap0);
2737 writel(0, base + NvRegMSIXMap1);
2738 }
2739 }
2740 }
2741 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2742 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2743 np->msi_flags |= NV_MSI_ENABLED;
2744 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
2745 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2746 pci_disable_msi(np->pci_dev);
2747 np->msi_flags &= ~NV_MSI_ENABLED;
2748 goto out_err;
2749 }
2750
2751 /* map interrupts to vector 0 */
2752 writel(0, base + NvRegMSIMap0);
2753 writel(0, base + NvRegMSIMap1);
2754 /* enable msi vector 0 */
2755 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2756 }
2757 }
2758 if (ret != 0) {
2759 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0)
2760 goto out_err;
2761 }
2762
2763 return 0;
2764out_free_tx:
2765 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2766out_free_rx:
2767 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2768out_err:
2769 return 1;
2770}
2771
2772static void nv_free_irq(struct net_device *dev)
2773{
2774 struct fe_priv *np = get_nvpriv(dev);
2775 int i;
2776
2777 if (np->msi_flags & NV_MSI_X_ENABLED) {
2778 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2779 free_irq(np->msi_x_entry[i].vector, dev);
2780 }
2781 pci_disable_msix(np->pci_dev);
2782 np->msi_flags &= ~NV_MSI_X_ENABLED;
2783 } else {
2784 free_irq(np->pci_dev->irq, dev);
2785 if (np->msi_flags & NV_MSI_ENABLED) {
2786 pci_disable_msi(np->pci_dev);
2787 np->msi_flags &= ~NV_MSI_ENABLED;
2788 }
2789 }
2790}
2791
2631static int nv_open(struct net_device *dev) 2792static int nv_open(struct net_device *dev)
2632{ 2793{
2633 struct fe_priv *np = netdev_priv(dev); 2794 struct fe_priv *np = netdev_priv(dev);
@@ -2720,12 +2881,16 @@ static int nv_open(struct net_device *dev)
2720 udelay(10); 2881 udelay(10);
2721 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); 2882 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2722 2883
2723 writel(0, base + NvRegIrqMask); 2884 nv_disable_hw_interrupts(dev, np->irqmask);
2724 pci_push(base); 2885 pci_push(base);
2725 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); 2886 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2726 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); 2887 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2727 pci_push(base); 2888 pci_push(base);
2728 2889
2890 if (nv_request_irq(dev)) {
2891 goto out_drain;
2892 }
2893
2729 if (np->msi_flags & NV_MSI_X_CAPABLE) { 2894 if (np->msi_flags & NV_MSI_X_CAPABLE) {
2730 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { 2895 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2731 np->msi_x_entry[i].entry = i; 2896 np->msi_x_entry[i].entry = i;
@@ -2799,7 +2964,7 @@ static int nv_open(struct net_device *dev)
2799 } 2964 }
2800 2965
2801 /* ask for interrupts */ 2966 /* ask for interrupts */
2802 writel(np->irqmask, base + NvRegIrqMask); 2967 nv_enable_hw_interrupts(dev, np->irqmask);
2803 2968
2804 spin_lock_irq(&np->lock); 2969 spin_lock_irq(&np->lock);
2805 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); 2970 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
@@ -2843,7 +3008,6 @@ static int nv_close(struct net_device *dev)
2843{ 3008{
2844 struct fe_priv *np = netdev_priv(dev); 3009 struct fe_priv *np = netdev_priv(dev);
2845 u8 __iomem *base; 3010 u8 __iomem *base;
2846 int i;
2847 3011
2848 spin_lock_irq(&np->lock); 3012 spin_lock_irq(&np->lock);
2849 np->in_shutdown = 1; 3013 np->in_shutdown = 1;
@@ -2861,31 +3025,13 @@ static int nv_close(struct net_device *dev)
2861 3025
2862 /* disable interrupts on the nic or we will lock up */ 3026 /* disable interrupts on the nic or we will lock up */
2863 base = get_hwbase(dev); 3027 base = get_hwbase(dev);
2864 if (np->msi_flags & NV_MSI_X_ENABLED) { 3028 nv_disable_hw_interrupts(dev, np->irqmask);
2865 writel(np->irqmask, base + NvRegIrqMask);
2866 } else {
2867 if (np->msi_flags & NV_MSI_ENABLED)
2868 writel(0, base + NvRegMSIIrqMask);
2869 writel(0, base + NvRegIrqMask);
2870 }
2871 pci_push(base); 3029 pci_push(base);
2872 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); 3030 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2873 3031
2874 spin_unlock_irq(&np->lock); 3032 spin_unlock_irq(&np->lock);
2875 3033
2876 if (np->msi_flags & NV_MSI_X_ENABLED) { 3034 nv_free_irq(dev);
2877 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2878 free_irq(np->msi_x_entry[i].vector, dev);
2879 }
2880 pci_disable_msix(np->pci_dev);
2881 np->msi_flags &= ~NV_MSI_X_ENABLED;
2882 } else {
2883 free_irq(np->pci_dev->irq, dev);
2884 if (np->msi_flags & NV_MSI_ENABLED) {
2885 pci_disable_msi(np->pci_dev);
2886 np->msi_flags &= ~NV_MSI_ENABLED;
2887 }
2888 }
2889 3035
2890 drain_ring(dev); 3036 drain_ring(dev);
2891 3037
@@ -2974,20 +3120,18 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
2974 if (id->driver_data & DEV_HAS_HIGH_DMA) { 3120 if (id->driver_data & DEV_HAS_HIGH_DMA) {
2975 /* packet format 3: supports 40-bit addressing */ 3121 /* packet format 3: supports 40-bit addressing */
2976 np->desc_ver = DESC_VER_3; 3122 np->desc_ver = DESC_VER_3;
3123 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2977 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) { 3124 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
2978 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", 3125 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2979 pci_name(pci_dev)); 3126 pci_name(pci_dev));
2980 } else { 3127 } else {
2981 if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) { 3128 dev->features |= NETIF_F_HIGHDMA;
2982 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n", 3129 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
2983 pci_name(pci_dev)); 3130 }
2984 goto out_relreg; 3131 if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2985 } else { 3132 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
2986 dev->features |= NETIF_F_HIGHDMA; 3133 pci_name(pci_dev));
2987 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
2988 }
2989 } 3134 }
2990 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2991 } else if (id->driver_data & DEV_HAS_LARGEDESC) { 3135 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2992 /* packet format 2: supports jumbo frames */ 3136 /* packet format 2: supports jumbo frames */
2993 np->desc_ver = DESC_VER_2; 3137 np->desc_ver = DESC_VER_2;
diff --git a/drivers/net/hamradio/dmascc.c b/drivers/net/hamradio/dmascc.c
index 79a8fbcf5f93..0d5fccc984bb 100644
--- a/drivers/net/hamradio/dmascc.c
+++ b/drivers/net/hamradio/dmascc.c
@@ -582,7 +582,6 @@ static int __init setup_adapter(int card_base, int type, int n)
582 INIT_WORK(&priv->rx_work, rx_bh, priv); 582 INIT_WORK(&priv->rx_work, rx_bh, priv);
583 dev->priv = priv; 583 dev->priv = priv;
584 sprintf(dev->name, "dmascc%i", 2 * n + i); 584 sprintf(dev->name, "dmascc%i", 2 * n + i);
585 SET_MODULE_OWNER(dev);
586 dev->base_addr = card_base; 585 dev->base_addr = card_base;
587 dev->irq = irq; 586 dev->irq = irq;
588 dev->open = scc_open; 587 dev->open = scc_open;
diff --git a/drivers/net/hamradio/scc.c b/drivers/net/hamradio/scc.c
index 6ace0e914fd1..5927784df3f9 100644
--- a/drivers/net/hamradio/scc.c
+++ b/drivers/net/hamradio/scc.c
@@ -1550,7 +1550,6 @@ static unsigned char ax25_nocall[AX25_ADDR_LEN] =
1550 1550
1551static void scc_net_setup(struct net_device *dev) 1551static void scc_net_setup(struct net_device *dev)
1552{ 1552{
1553 SET_MODULE_OWNER(dev);
1554 dev->tx_queue_len = 16; /* should be enough... */ 1553 dev->tx_queue_len = 16; /* should be enough... */
1555 1554
1556 dev->open = scc_net_open; 1555 dev->open = scc_net_open;
diff --git a/drivers/net/hamradio/yam.c b/drivers/net/hamradio/yam.c
index fe22479eb202..b49884048caa 100644
--- a/drivers/net/hamradio/yam.c
+++ b/drivers/net/hamradio/yam.c
@@ -1098,7 +1098,6 @@ static void yam_setup(struct net_device *dev)
1098 1098
1099 dev->base_addr = yp->iobase; 1099 dev->base_addr = yp->iobase;
1100 dev->irq = yp->irq; 1100 dev->irq = yp->irq;
1101 SET_MODULE_OWNER(dev);
1102 1101
1103 dev->open = yam_open; 1102 dev->open = yam_open;
1104 dev->stop = yam_close; 1103 dev->stop = yam_close;
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index ea62a3e7d586..411f4d809c47 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -1419,6 +1419,8 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
1419 mv643xx_eth_update_pscr(dev, &cmd); 1419 mv643xx_eth_update_pscr(dev, &cmd);
1420 mv643xx_set_settings(dev, &cmd); 1420 mv643xx_set_settings(dev, &cmd);
1421 1421
1422 SET_MODULE_OWNER(dev);
1423 SET_NETDEV_DEV(dev, &pdev->dev);
1422 err = register_netdev(dev); 1424 err = register_netdev(dev);
1423 if (err) 1425 if (err)
1424 goto out; 1426 goto out;
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 73e271e59c6a..beeb612be98f 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -69,8 +69,8 @@
69 69
70#define DRV_MODULE_NAME "tg3" 70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": " 71#define PFX DRV_MODULE_NAME ": "
72#define DRV_MODULE_VERSION "3.56" 72#define DRV_MODULE_VERSION "3.57"
73#define DRV_MODULE_RELDATE "Apr 1, 2006" 73#define DRV_MODULE_RELDATE "Apr 28, 2006"
74 74
75#define TG3_DEF_MAC_MODE 0 75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0 76#define TG3_DEF_RX_MODE 0
@@ -974,6 +974,8 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
974 return err; 974 return err;
975} 975}
976 976
977static void tg3_link_report(struct tg3 *);
978
977/* This will reset the tigon3 PHY if there is no valid 979/* This will reset the tigon3 PHY if there is no valid
978 * link unless the FORCE argument is non-zero. 980 * link unless the FORCE argument is non-zero.
979 */ 981 */
@@ -987,6 +989,11 @@ static int tg3_phy_reset(struct tg3 *tp)
987 if (err != 0) 989 if (err != 0)
988 return -EBUSY; 990 return -EBUSY;
989 991
992 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
993 netif_carrier_off(tp->dev);
994 tg3_link_report(tp);
995 }
996
990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || 997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || 998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { 999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
@@ -1023,6 +1030,12 @@ out:
1023 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); 1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1024 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1031 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1025 } 1032 }
1033 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1035 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1036 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1037 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1038 }
1026 /* Set Extended packet length bit (bit 14) on all chips that */ 1039 /* Set Extended packet length bit (bit 14) on all chips that */
1027 /* support jumbo frames */ 1040 /* support jumbo frames */
1028 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 1041 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
@@ -3531,7 +3544,7 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3531 return IRQ_RETVAL(0); 3544 return IRQ_RETVAL(0);
3532} 3545}
3533 3546
3534static int tg3_init_hw(struct tg3 *); 3547static int tg3_init_hw(struct tg3 *, int);
3535static int tg3_halt(struct tg3 *, int, int); 3548static int tg3_halt(struct tg3 *, int, int);
3536 3549
3537#ifdef CONFIG_NET_POLL_CONTROLLER 3550#ifdef CONFIG_NET_POLL_CONTROLLER
@@ -3567,7 +3580,7 @@ static void tg3_reset_task(void *_data)
3567 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; 3580 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3568 3581
3569 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); 3582 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3570 tg3_init_hw(tp); 3583 tg3_init_hw(tp, 1);
3571 3584
3572 tg3_netif_start(tp); 3585 tg3_netif_start(tp);
3573 3586
@@ -4042,7 +4055,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4042 4055
4043 tg3_set_mtu(dev, tp, new_mtu); 4056 tg3_set_mtu(dev, tp, new_mtu);
4044 4057
4045 tg3_init_hw(tp); 4058 tg3_init_hw(tp, 0);
4046 4059
4047 tg3_netif_start(tp); 4060 tg3_netif_start(tp);
4048 4061
@@ -5719,9 +5732,23 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
5719 if (!netif_running(dev)) 5732 if (!netif_running(dev))
5720 return 0; 5733 return 0;
5721 5734
5722 spin_lock_bh(&tp->lock); 5735 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5723 __tg3_set_mac_addr(tp); 5736 /* Reset chip so that ASF can re-init any MAC addresses it
5724 spin_unlock_bh(&tp->lock); 5737 * needs.
5738 */
5739 tg3_netif_stop(tp);
5740 tg3_full_lock(tp, 1);
5741
5742 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5743 tg3_init_hw(tp, 0);
5744
5745 tg3_netif_start(tp);
5746 tg3_full_unlock(tp);
5747 } else {
5748 spin_lock_bh(&tp->lock);
5749 __tg3_set_mac_addr(tp);
5750 spin_unlock_bh(&tp->lock);
5751 }
5725 5752
5726 return 0; 5753 return 0;
5727} 5754}
@@ -5771,7 +5798,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5771} 5798}
5772 5799
5773/* tp->lock is held. */ 5800/* tp->lock is held. */
5774static int tg3_reset_hw(struct tg3 *tp) 5801static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5775{ 5802{
5776 u32 val, rdmac_mode; 5803 u32 val, rdmac_mode;
5777 int i, err, limit; 5804 int i, err, limit;
@@ -5786,7 +5813,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5786 tg3_abort_hw(tp, 1); 5813 tg3_abort_hw(tp, 1);
5787 } 5814 }
5788 5815
5789 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) 5816 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy)
5790 tg3_phy_reset(tp); 5817 tg3_phy_reset(tp);
5791 5818
5792 err = tg3_chip_reset(tp); 5819 err = tg3_chip_reset(tp);
@@ -6327,7 +6354,7 @@ static int tg3_reset_hw(struct tg3 *tp)
6327 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 6354 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6328 } 6355 }
6329 6356
6330 err = tg3_setup_phy(tp, 1); 6357 err = tg3_setup_phy(tp, reset_phy);
6331 if (err) 6358 if (err)
6332 return err; 6359 return err;
6333 6360
@@ -6400,7 +6427,7 @@ static int tg3_reset_hw(struct tg3 *tp)
6400/* Called at device open time to get the chip ready for 6427/* Called at device open time to get the chip ready for
6401 * packet processing. Invoked with tp->lock held. 6428 * packet processing. Invoked with tp->lock held.
6402 */ 6429 */
6403static int tg3_init_hw(struct tg3 *tp) 6430static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6404{ 6431{
6405 int err; 6432 int err;
6406 6433
@@ -6413,7 +6440,7 @@ static int tg3_init_hw(struct tg3 *tp)
6413 6440
6414 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); 6441 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6415 6442
6416 err = tg3_reset_hw(tp); 6443 err = tg3_reset_hw(tp, reset_phy);
6417 6444
6418out: 6445out:
6419 return err; 6446 return err;
@@ -6683,7 +6710,7 @@ static int tg3_test_msi(struct tg3 *tp)
6683 tg3_full_lock(tp, 1); 6710 tg3_full_lock(tp, 1);
6684 6711
6685 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 6712 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6686 err = tg3_init_hw(tp); 6713 err = tg3_init_hw(tp, 1);
6687 6714
6688 tg3_full_unlock(tp); 6715 tg3_full_unlock(tp);
6689 6716
@@ -6748,7 +6775,7 @@ static int tg3_open(struct net_device *dev)
6748 6775
6749 tg3_full_lock(tp, 0); 6776 tg3_full_lock(tp, 0);
6750 6777
6751 err = tg3_init_hw(tp); 6778 err = tg3_init_hw(tp, 1);
6752 if (err) { 6779 if (err) {
6753 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 6780 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6754 tg3_free_rings(tp); 6781 tg3_free_rings(tp);
@@ -7839,7 +7866,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
7839 7866
7840 if (netif_running(dev)) { 7867 if (netif_running(dev)) {
7841 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 7868 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7842 tg3_init_hw(tp); 7869 tg3_init_hw(tp, 1);
7843 tg3_netif_start(tp); 7870 tg3_netif_start(tp);
7844 } 7871 }
7845 7872
@@ -7884,7 +7911,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
7884 7911
7885 if (netif_running(dev)) { 7912 if (netif_running(dev)) {
7886 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 7913 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7887 tg3_init_hw(tp); 7914 tg3_init_hw(tp, 1);
7888 tg3_netif_start(tp); 7915 tg3_netif_start(tp);
7889 } 7916 }
7890 7917
@@ -8522,7 +8549,7 @@ static int tg3_test_loopback(struct tg3 *tp)
8522 if (!netif_running(tp->dev)) 8549 if (!netif_running(tp->dev))
8523 return TG3_LOOPBACK_FAILED; 8550 return TG3_LOOPBACK_FAILED;
8524 8551
8525 tg3_reset_hw(tp); 8552 tg3_reset_hw(tp, 1);
8526 8553
8527 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) 8554 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8528 err |= TG3_MAC_LOOPBACK_FAILED; 8555 err |= TG3_MAC_LOOPBACK_FAILED;
@@ -8596,7 +8623,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8596 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 8623 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8597 if (netif_running(dev)) { 8624 if (netif_running(dev)) {
8598 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 8625 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8599 tg3_init_hw(tp); 8626 tg3_init_hw(tp, 1);
8600 tg3_netif_start(tp); 8627 tg3_netif_start(tp);
8601 } 8628 }
8602 8629
@@ -9377,7 +9404,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9377 9404
9378 if ((page_off == 0) || (i == 0)) 9405 if ((page_off == 0) || (i == 0))
9379 nvram_cmd |= NVRAM_CMD_FIRST; 9406 nvram_cmd |= NVRAM_CMD_FIRST;
9380 else if (page_off == (tp->nvram_pagesize - 4)) 9407 if (page_off == (tp->nvram_pagesize - 4))
9381 nvram_cmd |= NVRAM_CMD_LAST; 9408 nvram_cmd |= NVRAM_CMD_LAST;
9382 9409
9383 if (i == (len - 4)) 9410 if (i == (len - 4))
@@ -10353,10 +10380,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10353 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) 10380 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10354 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; 10381 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10355 10382
10356 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 10383 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10357 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) && 10384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10358 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)) 10385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10359 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 10386 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10387 else
10388 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10389 }
10360 10390
10361 tp->coalesce_mode = 0; 10391 tp->coalesce_mode = 0;
10362 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && 10392 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
@@ -11569,7 +11599,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11569 tg3_full_lock(tp, 0); 11599 tg3_full_lock(tp, 0);
11570 11600
11571 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 11601 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11572 tg3_init_hw(tp); 11602 tg3_init_hw(tp, 1);
11573 11603
11574 tp->timer.expires = jiffies + tp->timer_offset; 11604 tp->timer.expires = jiffies + tp->timer_offset;
11575 add_timer(&tp->timer); 11605 add_timer(&tp->timer);
@@ -11603,7 +11633,7 @@ static int tg3_resume(struct pci_dev *pdev)
11603 tg3_full_lock(tp, 0); 11633 tg3_full_lock(tp, 0);
11604 11634
11605 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 11635 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11606 tg3_init_hw(tp); 11636 tg3_init_hw(tp, 1);
11607 11637
11608 tp->timer.expires = jiffies + tp->timer_offset; 11638 tp->timer.expires = jiffies + tp->timer_offset;
11609 add_timer(&tp->timer); 11639 add_timer(&tp->timer);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 8c8b987d1250..0e29b885d449 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2215,6 +2215,7 @@ struct tg3 {
2215#define TG3_FLG2_HW_TSO_2 0x08000000 2215#define TG3_FLG2_HW_TSO_2 0x08000000
2216#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2) 2216#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2217#define TG3_FLG2_1SHOT_MSI 0x10000000 2217#define TG3_FLG2_1SHOT_MSI 0x10000000
2218#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2218 2219
2219 u32 split_mode_max_reqs; 2220 u32 split_mode_max_reqs;
2220#define SPLIT_MODE_5704_MAX_REQ 3 2221#define SPLIT_MODE_5704_MAX_REQ 3
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c
index 6a23964c1317..a6dc53b4250d 100644
--- a/drivers/net/via-rhine.c
+++ b/drivers/net/via-rhine.c
@@ -129,6 +129,7 @@
129 - Massive clean-up 129 - Massive clean-up
130 - Rewrite PHY, media handling (remove options, full_duplex, backoff) 130 - Rewrite PHY, media handling (remove options, full_duplex, backoff)
131 - Fix Tx engine race for good 131 - Fix Tx engine race for good
132 - Craig Brind: Zero padded aligned buffers for short packets.
132 133
133*/ 134*/
134 135
@@ -1326,7 +1327,12 @@ static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1326 rp->stats.tx_dropped++; 1327 rp->stats.tx_dropped++;
1327 return 0; 1328 return 0;
1328 } 1329 }
1330
1331 /* Padding is not copied and so must be redone. */
1329 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]); 1332 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1333 if (skb->len < ETH_ZLEN)
1334 memset(rp->tx_buf[entry] + skb->len, 0,
1335 ETH_ZLEN - skb->len);
1330 rp->tx_skbuff_dma[entry] = 0; 1336 rp->tx_skbuff_dma[entry] = 0;
1331 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma + 1337 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1332 (rp->tx_buf[entry] - 1338 (rp->tx_buf[entry] -
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 12:56:40 -0500