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-rw-r--r--drivers/net/tg3.c30
-rw-r--r--drivers/net/tg3.h3
2 files changed, 20 insertions, 13 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b01f6a07e5e7..9188a9b3ba2e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -90,7 +90,7 @@
90/* hardware minimum and maximum for a single frame's data payload */ 90/* hardware minimum and maximum for a single frame's data payload */
91#define TG3_MIN_MTU 60 91#define TG3_MIN_MTU 60
92#define TG3_MAX_MTU(tp) \ 92#define TG3_MAX_MTU(tp) \
93 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500) 93 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
94 94
95/* These numbers seem to be hard coded in the NIC firmware somehow. 95/* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place 96 * You can't change the ring sizes, but you can change where you place
@@ -914,7 +914,7 @@ out:
914 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 914 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
915 /* Cannot do read-modify-write on 5401 */ 915 /* Cannot do read-modify-write on 5401 */
916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); 916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
917 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 917 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
918 u32 phy_reg; 918 u32 phy_reg;
919 919
920 /* Set bit 14 with read-modify-write to preserve other bits */ 920 /* Set bit 14 with read-modify-write to preserve other bits */
@@ -926,7 +926,7 @@ out:
926 /* Set phy register 0x10 bit 0 to high fifo elasticity to support 926 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
927 * jumbo frames transmission. 927 * jumbo frames transmission.
928 */ 928 */
929 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 929 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
930 u32 phy_reg; 930 u32 phy_reg;
931 931
932 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) 932 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -3444,9 +3444,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3444 dev->mtu = new_mtu; 3444 dev->mtu = new_mtu;
3445 3445
3446 if (new_mtu > ETH_DATA_LEN) 3446 if (new_mtu > ETH_DATA_LEN)
3447 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; 3447 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3448 else 3448 else
3449 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE; 3449 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
3450} 3450}
3451 3451
3452static int tg3_change_mtu(struct net_device *dev, int new_mtu) 3452static int tg3_change_mtu(struct net_device *dev, int new_mtu)
@@ -3588,7 +3588,7 @@ static void tg3_init_rings(struct tg3 *tp)
3588 (i << RXD_OPAQUE_INDEX_SHIFT)); 3588 (i << RXD_OPAQUE_INDEX_SHIFT));
3589 } 3589 }
3590 3590
3591 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { 3591 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3592 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { 3592 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3593 struct tg3_rx_buffer_desc *rxd; 3593 struct tg3_rx_buffer_desc *rxd;
3594 3594
@@ -3609,7 +3609,7 @@ static void tg3_init_rings(struct tg3 *tp)
3609 break; 3609 break;
3610 } 3610 }
3611 3611
3612 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { 3612 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3613 for (i = 0; i < tp->rx_jumbo_pending; i++) { 3613 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3614 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO, 3614 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3615 -1, i) < 0) 3615 -1, i) < 0)
@@ -5277,7 +5277,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5277 } 5277 }
5278#endif 5278#endif
5279 5279
5280 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) { 5280 if (tp->dev->mtu <= ETH_DATA_LEN) {
5281 tw32(BUFMGR_MB_RDMA_LOW_WATER, 5281 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5282 tp->bufmgr_config.mbuf_read_dma_low_water); 5282 tp->bufmgr_config.mbuf_read_dma_low_water);
5283 tw32(BUFMGR_MB_MACRX_LOW_WATER, 5283 tw32(BUFMGR_MB_MACRX_LOW_WATER,
@@ -5352,7 +5352,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5352 /* Setup replenish threshold. */ 5352 /* Setup replenish threshold. */
5353 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); 5353 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5354 5354
5355 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { 5355 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5356 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 5356 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5357 ((u64) tp->rx_jumbo_mapping >> 32)); 5357 ((u64) tp->rx_jumbo_mapping >> 32));
5358 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 5358 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
@@ -5413,7 +5413,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5413 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, 5413 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5414 tp->rx_std_ptr); 5414 tp->rx_std_ptr);
5415 5415
5416 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ? 5416 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
5417 tp->rx_jumbo_pending : 0; 5417 tp->rx_jumbo_pending : 0;
5418 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 5418 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5419 tp->rx_jumbo_ptr); 5419 tp->rx_jumbo_ptr);
@@ -8991,6 +8991,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8991 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 8991 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8992 tp->tg3_flags2 |= TG3_FLG2_HW_TSO; 8992 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8993 8993
8994 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
8995 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
8996 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
8997 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
8998
8994 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0) 8999 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8995 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 9000 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8996 9001
@@ -9117,8 +9122,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
9117 /* Derive initial jumbo mode from MTU assigned in 9122 /* Derive initial jumbo mode from MTU assigned in
9118 * ether_setup() via the alloc_etherdev() call 9123 * ether_setup() via the alloc_etherdev() call
9119 */ 9124 */
9120 if (tp->dev->mtu > ETH_DATA_LEN) 9125 if (tp->dev->mtu > ETH_DATA_LEN &&
9121 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; 9126 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
9127 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
9122 9128
9123 /* Determine WakeOnLan speed to use. */ 9129 /* Determine WakeOnLan speed to use. */
9124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 9130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 46fa105fce83..7cb2eefa7aad 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2125,7 +2125,7 @@ struct tg3 {
2125#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000 2125#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
2126#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000 2126#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
2127#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 2127#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2128#define TG3_FLAG_JUMBO_ENABLE 0x00800000 2128#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2129#define TG3_FLAG_10_100_ONLY 0x01000000 2129#define TG3_FLAG_10_100_ONLY 0x01000000
2130#define TG3_FLAG_PAUSE_AUTONEG 0x02000000 2130#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2131#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 2131#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
@@ -2155,6 +2155,7 @@ struct tg3 {
2155#define TG3_FLG2_5750_PLUS 0x00080000 2155#define TG3_FLG2_5750_PLUS 0x00080000
2156#define TG3_FLG2_PROTECTED_NVRAM 0x00100000 2156#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
2157#define TG3_FLG2_USING_MSI 0x00200000 2157#define TG3_FLG2_USING_MSI 0x00200000
2158#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
2158 2159
2159 u32 split_mode_max_reqs; 2160 u32 split_mode_max_reqs;
2160#define SPLIT_MODE_5704_MAX_REQ 3 2161#define SPLIT_MODE_5704_MAX_REQ 3