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-rw-r--r--drivers/net/3c501.c1
-rw-r--r--drivers/net/3c59x.c2
-rw-r--r--drivers/net/8139cp.c2
-rw-r--r--drivers/net/8139too.c2
-rw-r--r--drivers/net/8390.c10
-rw-r--r--drivers/net/Kconfig33
-rw-r--r--drivers/net/Makefile11
-rw-r--r--drivers/net/acenic.c2
-rw-r--r--drivers/net/amd8111e.c2
-rw-r--r--drivers/net/arcnet/com20020-pci.c2
-rw-r--r--drivers/net/b44.c2
-rw-r--r--drivers/net/bnx2.c2
-rw-r--r--drivers/net/cassini.c2
-rw-r--r--drivers/net/chelsio/cxgb2.c2
-rw-r--r--drivers/net/defxx.c2
-rw-r--r--drivers/net/dl2k.c2
-rw-r--r--drivers/net/dm9000.c4
-rw-r--r--drivers/net/e100.c30
-rw-r--r--drivers/net/e1000/e1000.h6
-rw-r--r--drivers/net/e1000/e1000_ethtool.c257
-rw-r--r--drivers/net/e1000/e1000_hw.c1077
-rw-r--r--drivers/net/e1000/e1000_hw.h26
-rw-r--r--drivers/net/e1000/e1000_main.c154
-rw-r--r--drivers/net/e1000/e1000_param.c161
-rw-r--r--drivers/net/eepro100.c2
-rw-r--r--drivers/net/epic100.c2
-rw-r--r--drivers/net/fealnx.c2
-rw-r--r--drivers/net/forcedeth.c560
-rw-r--r--drivers/net/hp100.c1
-rw-r--r--drivers/net/irda/mcs7780.c1
-rw-r--r--drivers/net/irda/w83977af_ir.c1
-rw-r--r--drivers/net/ixgb/ixgb.h5
-rw-r--r--drivers/net/ixgb/ixgb_ethtool.c6
-rw-r--r--drivers/net/ixgb/ixgb_hw.c11
-rw-r--r--drivers/net/ixgb/ixgb_ids.h1
-rw-r--r--drivers/net/ixgb/ixgb_main.c152
-rw-r--r--drivers/net/myri10ge/myri10ge.c228
-rw-r--r--drivers/net/myri10ge/myri10ge_mcp.h47
-rw-r--r--drivers/net/natsemi.c2
-rw-r--r--drivers/net/ne2k-pci.c2
-rw-r--r--drivers/net/netx-eth.c1
-rw-r--r--drivers/net/ns83820.c2
-rw-r--r--drivers/net/pci-skeleton.c2
-rw-r--r--drivers/net/pcmcia/axnet_cs.c3
-rw-r--r--drivers/net/pcmcia/pcnet_cs.c15
-rw-r--r--drivers/net/pcnet32.c2
-rw-r--r--drivers/net/phy/smsc.c1
-rw-r--r--drivers/net/phy/vitesse.c1
-rw-r--r--drivers/net/qla3xxx.c3537
-rw-r--r--drivers/net/qla3xxx.h1194
-rw-r--r--drivers/net/r8169.c2
-rw-r--r--drivers/net/rrunner.c2
-rw-r--r--drivers/net/s2io.c2
-rw-r--r--drivers/net/saa9730.c2
-rw-r--r--drivers/net/sis190.c2
-rw-r--r--drivers/net/sis900.c3
-rw-r--r--drivers/net/sk98lin/skge.c2
-rw-r--r--drivers/net/skfp/skfddi.c2
-rw-r--r--drivers/net/skge.c204
-rw-r--r--drivers/net/skge.h1
-rw-r--r--drivers/net/sky2.c188
-rw-r--r--drivers/net/sky2.h3
-rw-r--r--drivers/net/slhc.c28
-rw-r--r--drivers/net/smc911x.c2
-rw-r--r--drivers/net/starfire.c2
-rw-r--r--drivers/net/sundance.c15
-rw-r--r--drivers/net/sungem.c2
-rw-r--r--drivers/net/tc35815.c2
-rw-r--r--drivers/net/tg3.c2
-rw-r--r--drivers/net/tokenring/3c359.c2
-rw-r--r--drivers/net/tokenring/lanstreamer.c2
-rw-r--r--drivers/net/tulip/21142.c6
-rw-r--r--drivers/net/tulip/de2104x.c18
-rw-r--r--drivers/net/tulip/de4x5.c2
-rw-r--r--drivers/net/tulip/dmfe.c2
-rw-r--r--drivers/net/tulip/eeprom.c2
-rw-r--r--drivers/net/tulip/interrupt.c2
-rw-r--r--drivers/net/tulip/media.c2
-rw-r--r--drivers/net/tulip/pnic.c2
-rw-r--r--drivers/net/tulip/pnic2.c2
-rw-r--r--drivers/net/tulip/timer.c16
-rw-r--r--drivers/net/tulip/tulip.h36
-rw-r--r--drivers/net/tulip/tulip_core.c94
-rw-r--r--drivers/net/tulip/uli526x.c12
-rw-r--r--drivers/net/tulip/winbond-840.c82
-rw-r--r--drivers/net/tulip/xircom_tulip_cb.c2
-rw-r--r--drivers/net/typhoon.c2
-rw-r--r--drivers/net/via-rhine.c2
-rw-r--r--drivers/net/via-velocity.c2
-rw-r--r--drivers/net/via-velocity.h19
-rw-r--r--drivers/net/wan/cycx_main.c1
-rw-r--r--drivers/net/wan/dlci.c1
-rw-r--r--drivers/net/wan/dscc4.c2
-rw-r--r--drivers/net/wan/farsync.c2
-rw-r--r--drivers/net/wan/lmc/lmc_main.c2
-rw-r--r--drivers/net/wan/pc300_drv.c2
-rw-r--r--drivers/net/wan/pci200syn.c2
-rw-r--r--drivers/net/wan/sdla.c1
-rw-r--r--drivers/net/wan/wanxl.c2
-rw-r--r--drivers/net/wireless/atmel_pci.c2
-rw-r--r--drivers/net/wireless/ipw2100.c2
-rw-r--r--drivers/net/wireless/ipw2200.c2
-rw-r--r--drivers/net/wireless/orinoco_nortel.c2
-rw-r--r--drivers/net/wireless/orinoco_pci.c2
-rw-r--r--drivers/net/wireless/orinoco_plx.c2
-rw-r--r--drivers/net/wireless/orinoco_tmd.c2
-rw-r--r--drivers/net/wireless/prism54/islpci_hotplug.c2
-rw-r--r--drivers/net/yellowfin.c2
108 files changed, 6829 insertions, 1554 deletions
diff --git a/drivers/net/3c501.c b/drivers/net/3c501.c
index 07136ec423bd..d7b115a35962 100644
--- a/drivers/net/3c501.c
+++ b/drivers/net/3c501.c
@@ -120,7 +120,6 @@ static const char version[] =
120#include <linux/slab.h> 120#include <linux/slab.h>
121#include <linux/string.h> 121#include <linux/string.h>
122#include <linux/errno.h> 122#include <linux/errno.h>
123#include <linux/config.h> /* for CONFIG_IP_MULTICAST */
124#include <linux/spinlock.h> 123#include <linux/spinlock.h>
125#include <linux/ethtool.h> 124#include <linux/ethtool.h>
126#include <linux/delay.h> 125#include <linux/delay.h>
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c
index 80e8ca013e44..7c23813bb097 100644
--- a/drivers/net/3c59x.c
+++ b/drivers/net/3c59x.c
@@ -3169,7 +3169,7 @@ static int __init vortex_init(void)
3169{ 3169{
3170 int pci_rc, eisa_rc; 3170 int pci_rc, eisa_rc;
3171 3171
3172 pci_rc = pci_module_init(&vortex_driver); 3172 pci_rc = pci_register_driver(&vortex_driver);
3173 eisa_rc = vortex_eisa_init(); 3173 eisa_rc = vortex_eisa_init();
3174 3174
3175 if (pci_rc == 0) 3175 if (pci_rc == 0)
diff --git a/drivers/net/8139cp.c b/drivers/net/8139cp.c
index 1428bb7715af..4c2e76326c4a 100644
--- a/drivers/net/8139cp.c
+++ b/drivers/net/8139cp.c
@@ -2098,7 +2098,7 @@ static int __init cp_init (void)
2098#ifdef MODULE 2098#ifdef MODULE
2099 printk("%s", version); 2099 printk("%s", version);
2100#endif 2100#endif
2101 return pci_module_init (&cp_driver); 2101 return pci_register_driver(&cp_driver);
2102} 2102}
2103 2103
2104static void __exit cp_exit (void) 2104static void __exit cp_exit (void)
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index e4f4eaff7679..2a707747ed8e 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -2629,7 +2629,7 @@ static int __init rtl8139_init_module (void)
2629 printk (KERN_INFO RTL8139_DRIVER_NAME "\n"); 2629 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2630#endif 2630#endif
2631 2631
2632 return pci_module_init (&rtl8139_pci_driver); 2632 return pci_register_driver(&rtl8139_pci_driver);
2633} 2633}
2634 2634
2635 2635
diff --git a/drivers/net/8390.c b/drivers/net/8390.c
index d2935ae39814..3eb7048684a6 100644
--- a/drivers/net/8390.c
+++ b/drivers/net/8390.c
@@ -299,7 +299,7 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
299 * Slow phase with lock held. 299 * Slow phase with lock held.
300 */ 300 */
301 301
302 disable_irq_nosync(dev->irq); 302 disable_irq_nosync_lockdep(dev->irq);
303 303
304 spin_lock(&ei_local->page_lock); 304 spin_lock(&ei_local->page_lock);
305 305
@@ -338,7 +338,7 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
338 netif_stop_queue(dev); 338 netif_stop_queue(dev);
339 outb_p(ENISR_ALL, e8390_base + EN0_IMR); 339 outb_p(ENISR_ALL, e8390_base + EN0_IMR);
340 spin_unlock(&ei_local->page_lock); 340 spin_unlock(&ei_local->page_lock);
341 enable_irq(dev->irq); 341 enable_irq_lockdep(dev->irq);
342 ei_local->stat.tx_errors++; 342 ei_local->stat.tx_errors++;
343 return 1; 343 return 1;
344 } 344 }
@@ -379,7 +379,7 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
379 outb_p(ENISR_ALL, e8390_base + EN0_IMR); 379 outb_p(ENISR_ALL, e8390_base + EN0_IMR);
380 380
381 spin_unlock(&ei_local->page_lock); 381 spin_unlock(&ei_local->page_lock);
382 enable_irq(dev->irq); 382 enable_irq_lockdep(dev->irq);
383 383
384 dev_kfree_skb (skb); 384 dev_kfree_skb (skb);
385 ei_local->stat.tx_bytes += send_length; 385 ei_local->stat.tx_bytes += send_length;
@@ -505,9 +505,9 @@ irqreturn_t ei_interrupt(int irq, void *dev_id, struct pt_regs * regs)
505#ifdef CONFIG_NET_POLL_CONTROLLER 505#ifdef CONFIG_NET_POLL_CONTROLLER
506void ei_poll(struct net_device *dev) 506void ei_poll(struct net_device *dev)
507{ 507{
508 disable_irq(dev->irq); 508 disable_irq_lockdep(dev->irq);
509 ei_interrupt(dev->irq, dev, NULL); 509 ei_interrupt(dev->irq, dev, NULL);
510 enable_irq(dev->irq); 510 enable_irq_lockdep(dev->irq);
511} 511}
512#endif 512#endif
513 513
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index a2bd8119270e..de4f9e1f2ca5 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1411,6 +1411,22 @@ config FORCEDETH
1411 <file:Documentation/networking/net-modules.txt>. The module will be 1411 <file:Documentation/networking/net-modules.txt>. The module will be
1412 called forcedeth. 1412 called forcedeth.
1413 1413
1414config FORCEDETH_NAPI
1415 bool "Use Rx and Tx Polling (NAPI) (EXPERIMENTAL)"
1416 depends on FORCEDETH && EXPERIMENTAL
1417 help
1418 NAPI is a new driver API designed to reduce CPU and interrupt load
1419 when the driver is receiving lots of packets from the card. It is
1420 still somewhat experimental and thus not yet enabled by default.
1421
1422 If your estimated Rx load is 10kpps or more, or if the card will be
1423 deployed on potentially unfriendly networks (e.g. in a firewall),
1424 then say Y here.
1425
1426 See <file:Documentation/networking/NAPI_HOWTO.txt> for more
1427 information.
1428
1429 If in doubt, say N.
1414 1430
1415config CS89x0 1431config CS89x0
1416 tristate "CS89x0 support" 1432 tristate "CS89x0 support"
@@ -2290,6 +2306,15 @@ config MV643XX_ETH_2
2290 This enables support for Port 2 of the Marvell MV643XX Gigabit 2306 This enables support for Port 2 of the Marvell MV643XX Gigabit
2291 Ethernet. 2307 Ethernet.
2292 2308
2309config QLA3XXX
2310 tristate "QLogic QLA3XXX Network Driver Support"
2311 depends on PCI
2312 help
2313 This driver supports QLogic ISP3XXX gigabit Ethernet cards.
2314
2315 To compile this driver as a module, choose M here: the module
2316 will be called qla3xxx.
2317
2293endmenu 2318endmenu
2294 2319
2295# 2320#
@@ -2550,6 +2575,7 @@ config PLIP
2550 2575
2551config PPP 2576config PPP
2552 tristate "PPP (point-to-point protocol) support" 2577 tristate "PPP (point-to-point protocol) support"
2578 select SLHC
2553 ---help--- 2579 ---help---
2554 PPP (Point to Point Protocol) is a newer and better SLIP. It serves 2580 PPP (Point to Point Protocol) is a newer and better SLIP. It serves
2555 the same purpose: sending Internet traffic over telephone (and other 2581 the same purpose: sending Internet traffic over telephone (and other
@@ -2730,6 +2756,7 @@ config SLIP
2730config SLIP_COMPRESSED 2756config SLIP_COMPRESSED
2731 bool "CSLIP compressed headers" 2757 bool "CSLIP compressed headers"
2732 depends on SLIP 2758 depends on SLIP
2759 select SLHC
2733 ---help--- 2760 ---help---
2734 This protocol is faster than SLIP because it uses compression on the 2761 This protocol is faster than SLIP because it uses compression on the
2735 TCP/IP headers (not on the data itself), but it has to be supported 2762 TCP/IP headers (not on the data itself), but it has to be supported
@@ -2742,6 +2769,12 @@ config SLIP_COMPRESSED
2742 <http://www.tldp.org/docs.html#howto>, explains how to configure 2769 <http://www.tldp.org/docs.html#howto>, explains how to configure
2743 CSLIP. This won't enlarge your kernel. 2770 CSLIP. This won't enlarge your kernel.
2744 2771
2772config SLHC
2773 tristate
2774 help
2775 This option enables Van Jacobsen serial line header compression
2776 routines.
2777
2745config SLIP_SMART 2778config SLIP_SMART
2746 bool "Keepalive and linefill" 2779 bool "Keepalive and linefill"
2747 depends on SLIP 2780 depends on SLIP
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 8427bf9dec9d..6ff17649c0fc 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -2,10 +2,6 @@
2# Makefile for the Linux network (ethercard) device drivers. 2# Makefile for the Linux network (ethercard) device drivers.
3# 3#
4 4
5ifeq ($(CONFIG_ISDN_PPP),y)
6 obj-$(CONFIG_ISDN) += slhc.o
7endif
8
9obj-$(CONFIG_E1000) += e1000/ 5obj-$(CONFIG_E1000) += e1000/
10obj-$(CONFIG_IBM_EMAC) += ibm_emac/ 6obj-$(CONFIG_IBM_EMAC) += ibm_emac/
11obj-$(CONFIG_IXGB) += ixgb/ 7obj-$(CONFIG_IXGB) += ixgb/
@@ -113,8 +109,9 @@ obj-$(CONFIG_FORCEDETH) += forcedeth.o
113obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o 109obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o
114 110
115obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o 111obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
112obj-$(CONFIG_QLA3XXX) += qla3xxx.o
116 113
117obj-$(CONFIG_PPP) += ppp_generic.o slhc.o 114obj-$(CONFIG_PPP) += ppp_generic.o
118obj-$(CONFIG_PPP_ASYNC) += ppp_async.o 115obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
119obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o 116obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o
120obj-$(CONFIG_PPP_DEFLATE) += ppp_deflate.o 117obj-$(CONFIG_PPP_DEFLATE) += ppp_deflate.o
@@ -123,9 +120,7 @@ obj-$(CONFIG_PPP_MPPE) += ppp_mppe.o
123obj-$(CONFIG_PPPOE) += pppox.o pppoe.o 120obj-$(CONFIG_PPPOE) += pppox.o pppoe.o
124 121
125obj-$(CONFIG_SLIP) += slip.o 122obj-$(CONFIG_SLIP) += slip.o
126ifeq ($(CONFIG_SLIP_COMPRESSED),y) 123obj-$(CONFIG_SLHC) += slhc.o
127 obj-$(CONFIG_SLIP) += slhc.o
128endif
129 124
130obj-$(CONFIG_DUMMY) += dummy.o 125obj-$(CONFIG_DUMMY) += dummy.o
131obj-$(CONFIG_IFB) += ifb.o 126obj-$(CONFIG_IFB) += ifb.o
diff --git a/drivers/net/acenic.c b/drivers/net/acenic.c
index 1c01e9b3d07c..c0f3574b470b 100644
--- a/drivers/net/acenic.c
+++ b/drivers/net/acenic.c
@@ -725,7 +725,7 @@ static struct pci_driver acenic_pci_driver = {
725 725
726static int __init acenic_init(void) 726static int __init acenic_init(void)
727{ 727{
728 return pci_module_init(&acenic_pci_driver); 728 return pci_register_driver(&acenic_pci_driver);
729} 729}
730 730
731static void __exit acenic_exit(void) 731static void __exit acenic_exit(void)
diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c
index ed322a76980d..2ef8e554263b 100644
--- a/drivers/net/amd8111e.c
+++ b/drivers/net/amd8111e.c
@@ -2158,7 +2158,7 @@ static struct pci_driver amd8111e_driver = {
2158 2158
2159static int __init amd8111e_init(void) 2159static int __init amd8111e_init(void)
2160{ 2160{
2161 return pci_module_init(&amd8111e_driver); 2161 return pci_register_driver(&amd8111e_driver);
2162} 2162}
2163 2163
2164static void __exit amd8111e_cleanup(void) 2164static void __exit amd8111e_cleanup(void)
diff --git a/drivers/net/arcnet/com20020-pci.c b/drivers/net/arcnet/com20020-pci.c
index 979a33df0a8c..fc256c197cd6 100644
--- a/drivers/net/arcnet/com20020-pci.c
+++ b/drivers/net/arcnet/com20020-pci.c
@@ -177,7 +177,7 @@ static struct pci_driver com20020pci_driver = {
177static int __init com20020pci_init(void) 177static int __init com20020pci_init(void)
178{ 178{
179 BUGLVL(D_NORMAL) printk(VERSION); 179 BUGLVL(D_NORMAL) printk(VERSION);
180 return pci_module_init(&com20020pci_driver); 180 return pci_register_driver(&com20020pci_driver);
181} 181}
182 182
183static void __exit com20020pci_cleanup(void) 183static void __exit com20020pci_cleanup(void)
diff --git a/drivers/net/b44.c b/drivers/net/b44.c
index bea0fc0ede2f..17eb2912971d 100644
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -2354,7 +2354,7 @@ static int __init b44_init(void)
2354 dma_desc_align_mask = ~(dma_desc_align_size - 1); 2354 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2355 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc)); 2355 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2356 2356
2357 return pci_module_init(&b44_driver); 2357 return pci_register_driver(&b44_driver);
2358} 2358}
2359 2359
2360static void __exit b44_cleanup(void) 2360static void __exit b44_cleanup(void)
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 652eb05a6c2d..654b903985cd 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -6016,7 +6016,7 @@ static struct pci_driver bnx2_pci_driver = {
6016 6016
6017static int __init bnx2_init(void) 6017static int __init bnx2_init(void)
6018{ 6018{
6019 return pci_module_init(&bnx2_pci_driver); 6019 return pci_register_driver(&bnx2_pci_driver);
6020} 6020}
6021 6021
6022static void __exit bnx2_cleanup(void) 6022static void __exit bnx2_cleanup(void)
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index a31544ccb3c4..26040abfef62 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -5245,7 +5245,7 @@ static int __init cas_init(void)
5245 else 5245 else
5246 link_transition_timeout = 0; 5246 link_transition_timeout = 0;
5247 5247
5248 return pci_module_init(&cas_driver); 5248 return pci_register_driver(&cas_driver);
5249} 5249}
5250 5250
5251static void __exit cas_cleanup(void) 5251static void __exit cas_cleanup(void)
diff --git a/drivers/net/chelsio/cxgb2.c b/drivers/net/chelsio/cxgb2.c
index e67872433e92..b6de184e4699 100644
--- a/drivers/net/chelsio/cxgb2.c
+++ b/drivers/net/chelsio/cxgb2.c
@@ -1243,7 +1243,7 @@ static struct pci_driver driver = {
1243 1243
1244static int __init t1_init_module(void) 1244static int __init t1_init_module(void)
1245{ 1245{
1246 return pci_module_init(&driver); 1246 return pci_register_driver(&driver);
1247} 1247}
1248 1248
1249static void __exit t1_cleanup_module(void) 1249static void __exit t1_cleanup_module(void)
diff --git a/drivers/net/defxx.c b/drivers/net/defxx.c
index 91cc8cbdd440..7d06dedbfb26 100644
--- a/drivers/net/defxx.c
+++ b/drivers/net/defxx.c
@@ -3444,7 +3444,7 @@ static int __init dfx_init(void)
3444{ 3444{
3445 int rc_pci, rc_eisa; 3445 int rc_pci, rc_eisa;
3446 3446
3447 rc_pci = pci_module_init(&dfx_driver); 3447 rc_pci = pci_register_driver(&dfx_driver);
3448 if (rc_pci >= 0) dfx_have_pci = 1; 3448 if (rc_pci >= 0) dfx_have_pci = 1;
3449 3449
3450 rc_eisa = dfx_eisa_init(); 3450 rc_eisa = dfx_eisa_init();
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c
index 402961e68c89..a572c2970564 100644
--- a/drivers/net/dl2k.c
+++ b/drivers/net/dl2k.c
@@ -1815,7 +1815,7 @@ static struct pci_driver rio_driver = {
1815static int __init 1815static int __init
1816rio_init (void) 1816rio_init (void)
1817{ 1817{
1818 return pci_module_init (&rio_driver); 1818 return pci_register_driver(&rio_driver);
1819} 1819}
1820 1820
1821static void __exit 1821static void __exit
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 3d76fa144c4f..a860ebbbf815 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -377,8 +377,8 @@ dm9000_release_board(struct platform_device *pdev, struct board_info *db)
377 kfree(db->data_req); 377 kfree(db->data_req);
378 } 378 }
379 379
380 if (db->addr_res != NULL) { 380 if (db->addr_req != NULL) {
381 release_resource(db->addr_res); 381 release_resource(db->addr_req);
382 kfree(db->addr_req); 382 kfree(db->addr_req);
383 } 383 }
384} 384}
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index ce850f1078b5..47d970896a5c 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -158,10 +158,10 @@
158 158
159 159
160#define DRV_NAME "e100" 160#define DRV_NAME "e100"
161#define DRV_EXT "-NAPI" 161#define DRV_EXT "-NAPI"
162#define DRV_VERSION "3.5.10-k2"DRV_EXT 162#define DRV_VERSION "3.5.16-k2"DRV_EXT
163#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" 163#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
164#define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation" 164#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
165#define PFX DRV_NAME ": " 165#define PFX DRV_NAME ": "
166 166
167#define E100_WATCHDOG_PERIOD (2 * HZ) 167#define E100_WATCHDOG_PERIOD (2 * HZ)
@@ -1395,15 +1395,11 @@ static int e100_phy_init(struct nic *nic)
1395 } 1395 }
1396 1396
1397 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) && 1397 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1398 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000))) { 1398 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1399 /* enable/disable MDI/MDI-X auto-switching. 1399 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1400 MDI/MDI-X auto-switching is disabled for 82551ER/QM chips */ 1400 /* enable/disable MDI/MDI-X auto-switching. */
1401 if((nic->mac == mac_82551_E) || (nic->mac == mac_82551_F) || 1401 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1402 (nic->mac == mac_82551_10) || (nic->mii.force_media) || 1402 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1403 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))
1404 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 0);
1405 else
1406 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, NCONFIG_AUTO_SWITCH);
1407 } 1403 }
1408 1404
1409 return 0; 1405 return 0;
@@ -1767,11 +1763,10 @@ static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1767#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN) 1763#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1768static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx) 1764static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1769{ 1765{
1770 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN))) 1766 if(!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1771 return -ENOMEM; 1767 return -ENOMEM;
1772 1768
1773 /* Align, init, and map the RFD. */ 1769 /* Align, init, and map the RFD. */
1774 rx->skb->dev = nic->netdev;
1775 skb_reserve(rx->skb, NET_IP_ALIGN); 1770 skb_reserve(rx->skb, NET_IP_ALIGN);
1776 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd)); 1771 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1777 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data, 1772 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
@@ -2147,7 +2142,7 @@ static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2147 2142
2148 e100_start_receiver(nic, NULL); 2143 e100_start_receiver(nic, NULL);
2149 2144
2150 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) { 2145 if(!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2151 err = -ENOMEM; 2146 err = -ENOMEM;
2152 goto err_loopback_none; 2147 goto err_loopback_none;
2153 } 2148 }
@@ -2799,6 +2794,7 @@ static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel
2799 /* Detach; put netif into state similar to hotplug unplug. */ 2794 /* Detach; put netif into state similar to hotplug unplug. */
2800 netif_poll_enable(netdev); 2795 netif_poll_enable(netdev);
2801 netif_device_detach(netdev); 2796 netif_device_detach(netdev);
2797 pci_disable_device(pdev);
2802 2798
2803 /* Request a slot reset. */ 2799 /* Request a slot reset. */
2804 return PCI_ERS_RESULT_NEED_RESET; 2800 return PCI_ERS_RESULT_NEED_RESET;
@@ -2877,7 +2873,7 @@ static int __init e100_init_module(void)
2877 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION); 2873 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2878 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT); 2874 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2879 } 2875 }
2880 return pci_module_init(&e100_driver); 2876 return pci_register_driver(&e100_driver);
2881} 2877}
2882 2878
2883static void __exit e100_cleanup_module(void) 2879static void __exit e100_cleanup_module(void)
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index d304297c496c..98afa9c2057e 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -242,12 +242,10 @@ struct e1000_adapter {
242 struct timer_list watchdog_timer; 242 struct timer_list watchdog_timer;
243 struct timer_list phy_info_timer; 243 struct timer_list phy_info_timer;
244 struct vlan_group *vlgrp; 244 struct vlan_group *vlgrp;
245 uint16_t mng_vlan_id; 245 uint16_t mng_vlan_id;
246 uint32_t bd_number; 246 uint32_t bd_number;
247 uint32_t rx_buffer_len; 247 uint32_t rx_buffer_len;
248 uint32_t part_num;
249 uint32_t wol; 248 uint32_t wol;
250 uint32_t ksp3_port_a;
251 uint32_t smartspeed; 249 uint32_t smartspeed;
252 uint32_t en_mng_pt; 250 uint32_t en_mng_pt;
253 uint16_t link_speed; 251 uint16_t link_speed;
@@ -342,7 +340,9 @@ struct e1000_adapter {
342 boolean_t tso_force; 340 boolean_t tso_force;
343#endif 341#endif
344 boolean_t smart_power_down; /* phy smart power down */ 342 boolean_t smart_power_down; /* phy smart power down */
343 boolean_t quad_port_a;
345 unsigned long flags; 344 unsigned long flags;
345 uint32_t eeprom_wol;
346}; 346};
347 347
348enum e1000_state_t { 348enum e1000_state_t {
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 88a82ba88f57..3fccffdb27b5 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -183,6 +183,9 @@ e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
183 return -EINVAL; 183 return -EINVAL;
184 } 184 }
185 185
186 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
187 msleep(1);
188
186 if (ecmd->autoneg == AUTONEG_ENABLE) { 189 if (ecmd->autoneg == AUTONEG_ENABLE) {
187 hw->autoneg = 1; 190 hw->autoneg = 1;
188 if (hw->media_type == e1000_media_type_fiber) 191 if (hw->media_type == e1000_media_type_fiber)
@@ -199,16 +202,20 @@ e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
199 ADVERTISED_TP; 202 ADVERTISED_TP;
200 ecmd->advertising = hw->autoneg_advertised; 203 ecmd->advertising = hw->autoneg_advertised;
201 } else 204 } else
202 if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) 205 if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
206 clear_bit(__E1000_RESETTING, &adapter->flags);
203 return -EINVAL; 207 return -EINVAL;
208 }
204 209
205 /* reset the link */ 210 /* reset the link */
206 211
207 if (netif_running(adapter->netdev)) 212 if (netif_running(adapter->netdev)) {
208 e1000_reinit_locked(adapter); 213 e1000_down(adapter);
209 else 214 e1000_up(adapter);
215 } else
210 e1000_reset(adapter); 216 e1000_reset(adapter);
211 217
218 clear_bit(__E1000_RESETTING, &adapter->flags);
212 return 0; 219 return 0;
213} 220}
214 221
@@ -238,9 +245,13 @@ e1000_set_pauseparam(struct net_device *netdev,
238{ 245{
239 struct e1000_adapter *adapter = netdev_priv(netdev); 246 struct e1000_adapter *adapter = netdev_priv(netdev);
240 struct e1000_hw *hw = &adapter->hw; 247 struct e1000_hw *hw = &adapter->hw;
248 int retval = 0;
241 249
242 adapter->fc_autoneg = pause->autoneg; 250 adapter->fc_autoneg = pause->autoneg;
243 251
252 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
253 msleep(1);
254
244 if (pause->rx_pause && pause->tx_pause) 255 if (pause->rx_pause && pause->tx_pause)
245 hw->fc = e1000_fc_full; 256 hw->fc = e1000_fc_full;
246 else if (pause->rx_pause && !pause->tx_pause) 257 else if (pause->rx_pause && !pause->tx_pause)
@@ -253,15 +264,17 @@ e1000_set_pauseparam(struct net_device *netdev,
253 hw->original_fc = hw->fc; 264 hw->original_fc = hw->fc;
254 265
255 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 266 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
256 if (netif_running(adapter->netdev)) 267 if (netif_running(adapter->netdev)) {
257 e1000_reinit_locked(adapter); 268 e1000_down(adapter);
258 else 269 e1000_up(adapter);
270 } else
259 e1000_reset(adapter); 271 e1000_reset(adapter);
260 } else 272 } else
261 return ((hw->media_type == e1000_media_type_fiber) ? 273 retval = ((hw->media_type == e1000_media_type_fiber) ?
262 e1000_setup_link(hw) : e1000_force_mac_fc(hw)); 274 e1000_setup_link(hw) : e1000_force_mac_fc(hw));
263 275
264 return 0; 276 clear_bit(__E1000_RESETTING, &adapter->flags);
277 return retval;
265} 278}
266 279
267static uint32_t 280static uint32_t
@@ -415,12 +428,12 @@ e1000_get_regs(struct net_device *netdev,
415 regs_buff[23] = regs_buff[18]; /* mdix mode */ 428 regs_buff[23] = regs_buff[18]; /* mdix mode */
416 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0); 429 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
417 } else { 430 } else {
418 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 431 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
419 regs_buff[13] = (uint32_t)phy_data; /* cable length */ 432 regs_buff[13] = (uint32_t)phy_data; /* cable length */
420 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 433 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
421 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 434 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
422 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 435 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
423 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 436 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
424 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */ 437 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */
425 regs_buff[18] = regs_buff[13]; /* cable polarity */ 438 regs_buff[18] = regs_buff[13]; /* cable polarity */
426 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 439 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
@@ -696,7 +709,6 @@ e1000_set_ringparam(struct net_device *netdev,
696 } 709 }
697 710
698 clear_bit(__E1000_RESETTING, &adapter->flags); 711 clear_bit(__E1000_RESETTING, &adapter->flags);
699
700 return 0; 712 return 0;
701err_setup_tx: 713err_setup_tx:
702 e1000_free_all_rx_resources(adapter); 714 e1000_free_all_rx_resources(adapter);
@@ -881,16 +893,17 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
881 893
882 *data = 0; 894 *data = 0;
883 895
896 /* NOTE: we don't test MSI interrupts here, yet */
884 /* Hook up test interrupt handler just for this test */ 897 /* Hook up test interrupt handler just for this test */
885 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, 898 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED,
886 netdev->name, netdev)) { 899 netdev->name, netdev))
887 shared_int = FALSE; 900 shared_int = FALSE;
888 } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, 901 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
889 netdev->name, netdev)){ 902 netdev->name, netdev)) {
890 *data = 1; 903 *data = 1;
891 return -1; 904 return -1;
892 } 905 }
893 DPRINTK(PROBE,INFO, "testing %s interrupt\n", 906 DPRINTK(HW, INFO, "testing %s interrupt\n",
894 (shared_int ? "shared" : "unshared")); 907 (shared_int ? "shared" : "unshared"));
895 908
896 /* Disable all the interrupts */ 909 /* Disable all the interrupts */
@@ -1256,11 +1269,10 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1256 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140); 1269 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140);
1257 /* autoneg off */ 1270 /* autoneg off */
1258 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140); 1271 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140);
1259 } else if (adapter->hw.phy_type == e1000_phy_gg82563) { 1272 } else if (adapter->hw.phy_type == e1000_phy_gg82563)
1260 e1000_write_phy_reg(&adapter->hw, 1273 e1000_write_phy_reg(&adapter->hw,
1261 GG82563_PHY_KMRN_MODE_CTRL, 1274 GG82563_PHY_KMRN_MODE_CTRL,
1262 0x1CC); 1275 0x1CC);
1263 }
1264 1276
1265 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL); 1277 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1266 1278
@@ -1288,9 +1300,9 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1288 } 1300 }
1289 1301
1290 if (adapter->hw.media_type == e1000_media_type_copper && 1302 if (adapter->hw.media_type == e1000_media_type_copper &&
1291 adapter->hw.phy_type == e1000_phy_m88) { 1303 adapter->hw.phy_type == e1000_phy_m88)
1292 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1304 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1293 } else { 1305 else {
1294 /* Set the ILOS bit on the fiber Nic is half 1306 /* Set the ILOS bit on the fiber Nic is half
1295 * duplex link is detected. */ 1307 * duplex link is detected. */
1296 stat_reg = E1000_READ_REG(&adapter->hw, STATUS); 1308 stat_reg = E1000_READ_REG(&adapter->hw, STATUS);
@@ -1426,11 +1438,10 @@ e1000_loopback_cleanup(struct e1000_adapter *adapter)
1426 case e1000_82546_rev_3: 1438 case e1000_82546_rev_3:
1427 default: 1439 default:
1428 hw->autoneg = TRUE; 1440 hw->autoneg = TRUE;
1429 if (hw->phy_type == e1000_phy_gg82563) { 1441 if (hw->phy_type == e1000_phy_gg82563)
1430 e1000_write_phy_reg(hw, 1442 e1000_write_phy_reg(hw,
1431 GG82563_PHY_KMRN_MODE_CTRL, 1443 GG82563_PHY_KMRN_MODE_CTRL,
1432 0x180); 1444 0x180);
1433 }
1434 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); 1445 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1435 if (phy_reg & MII_CR_LOOPBACK) { 1446 if (phy_reg & MII_CR_LOOPBACK) {
1436 phy_reg &= ~MII_CR_LOOPBACK; 1447 phy_reg &= ~MII_CR_LOOPBACK;
@@ -1590,6 +1601,8 @@ e1000_diag_test_count(struct net_device *netdev)
1590 return E1000_TEST_LEN; 1601 return E1000_TEST_LEN;
1591} 1602}
1592 1603
1604extern void e1000_power_up_phy(struct e1000_adapter *);
1605
1593static void 1606static void
1594e1000_diag_test(struct net_device *netdev, 1607e1000_diag_test(struct net_device *netdev,
1595 struct ethtool_test *eth_test, uint64_t *data) 1608 struct ethtool_test *eth_test, uint64_t *data)
@@ -1606,6 +1619,8 @@ e1000_diag_test(struct net_device *netdev,
1606 uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex; 1619 uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex;
1607 uint8_t autoneg = adapter->hw.autoneg; 1620 uint8_t autoneg = adapter->hw.autoneg;
1608 1621
1622 DPRINTK(HW, INFO, "offline testing starting\n");
1623
1609 /* Link test performed before hardware reset so autoneg doesn't 1624 /* Link test performed before hardware reset so autoneg doesn't
1610 * interfere with test result */ 1625 * interfere with test result */
1611 if (e1000_link_test(adapter, &data[4])) 1626 if (e1000_link_test(adapter, &data[4]))
@@ -1629,6 +1644,8 @@ e1000_diag_test(struct net_device *netdev,
1629 eth_test->flags |= ETH_TEST_FL_FAILED; 1644 eth_test->flags |= ETH_TEST_FL_FAILED;
1630 1645
1631 e1000_reset(adapter); 1646 e1000_reset(adapter);
1647 /* make sure the phy is powered up */
1648 e1000_power_up_phy(adapter);
1632 if (e1000_loopback_test(adapter, &data[3])) 1649 if (e1000_loopback_test(adapter, &data[3]))
1633 eth_test->flags |= ETH_TEST_FL_FAILED; 1650 eth_test->flags |= ETH_TEST_FL_FAILED;
1634 1651
@@ -1642,6 +1659,7 @@ e1000_diag_test(struct net_device *netdev,
1642 if (if_running) 1659 if (if_running)
1643 dev_open(netdev); 1660 dev_open(netdev);
1644 } else { 1661 } else {
1662 DPRINTK(HW, INFO, "online testing starting\n");
1645 /* Online tests */ 1663 /* Online tests */
1646 if (e1000_link_test(adapter, &data[4])) 1664 if (e1000_link_test(adapter, &data[4]))
1647 eth_test->flags |= ETH_TEST_FL_FAILED; 1665 eth_test->flags |= ETH_TEST_FL_FAILED;
@@ -1657,14 +1675,12 @@ e1000_diag_test(struct net_device *netdev,
1657 msleep_interruptible(4 * 1000); 1675 msleep_interruptible(4 * 1000);
1658} 1676}
1659 1677
1660static void 1678static int e1000_wol_exclusion(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
1661e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1662{ 1679{
1663 struct e1000_adapter *adapter = netdev_priv(netdev);
1664 struct e1000_hw *hw = &adapter->hw; 1680 struct e1000_hw *hw = &adapter->hw;
1681 int retval = 1; /* fail by default */
1665 1682
1666 switch (adapter->hw.device_id) { 1683 switch (hw->device_id) {
1667 case E1000_DEV_ID_82542:
1668 case E1000_DEV_ID_82543GC_FIBER: 1684 case E1000_DEV_ID_82543GC_FIBER:
1669 case E1000_DEV_ID_82543GC_COPPER: 1685 case E1000_DEV_ID_82543GC_COPPER:
1670 case E1000_DEV_ID_82544EI_FIBER: 1686 case E1000_DEV_ID_82544EI_FIBER:
@@ -1672,52 +1688,87 @@ e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1672 case E1000_DEV_ID_82545EM_FIBER: 1688 case E1000_DEV_ID_82545EM_FIBER:
1673 case E1000_DEV_ID_82545EM_COPPER: 1689 case E1000_DEV_ID_82545EM_COPPER:
1674 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1690 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1691 case E1000_DEV_ID_82546GB_PCIE:
1692 /* these don't support WoL at all */
1675 wol->supported = 0; 1693 wol->supported = 0;
1676 wol->wolopts = 0; 1694 break;
1677 return;
1678
1679 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1680 /* device id 10B5 port-A supports wol */
1681 if (!adapter->ksp3_port_a) {
1682 wol->supported = 0;
1683 return;
1684 }
1685 /* KSP3 does not suppport UCAST wake-ups for any interface */
1686 wol->supported = WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
1687
1688 if (adapter->wol & E1000_WUFC_EX)
1689 DPRINTK(DRV, ERR, "Interface does not support "
1690 "directed (unicast) frame wake-up packets\n");
1691 wol->wolopts = 0;
1692 goto do_defaults;
1693
1694 case E1000_DEV_ID_82546EB_FIBER: 1695 case E1000_DEV_ID_82546EB_FIBER:
1695 case E1000_DEV_ID_82546GB_FIBER: 1696 case E1000_DEV_ID_82546GB_FIBER:
1696 case E1000_DEV_ID_82571EB_FIBER: 1697 case E1000_DEV_ID_82571EB_FIBER:
1697 /* Wake events only supported on port A for dual fiber */ 1698 case E1000_DEV_ID_82571EB_SERDES:
1699 case E1000_DEV_ID_82571EB_COPPER:
1700 /* Wake events not supported on port B */
1698 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) { 1701 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
1699 wol->supported = 0; 1702 wol->supported = 0;
1700 wol->wolopts = 0; 1703 break;
1701 return;
1702 } 1704 }
1703 /* Fall Through */ 1705 /* return success for non excluded adapter ports */
1704 1706 retval = 0;
1707 break;
1708 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1709 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1710 /* quad port adapters only support WoL on port A */
1711 if (!adapter->quad_port_a) {
1712 wol->supported = 0;
1713 break;
1714 }
1715 /* return success for non excluded adapter ports */
1716 retval = 0;
1717 break;
1705 default: 1718 default:
1706 wol->supported = WAKE_UCAST | WAKE_MCAST | 1719 /* dual port cards only support WoL on port A from now on
1707 WAKE_BCAST | WAKE_MAGIC; 1720 * unless it was enabled in the eeprom for port B
1708 wol->wolopts = 0; 1721 * so exclude FUNC_1 ports from having WoL enabled */
1722 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1 &&
1723 !adapter->eeprom_wol) {
1724 wol->supported = 0;
1725 break;
1726 }
1709 1727
1710do_defaults: 1728 retval = 0;
1711 if (adapter->wol & E1000_WUFC_EX) 1729 }
1712 wol->wolopts |= WAKE_UCAST; 1730
1713 if (adapter->wol & E1000_WUFC_MC) 1731 return retval;
1714 wol->wolopts |= WAKE_MCAST; 1732}
1715 if (adapter->wol & E1000_WUFC_BC) 1733
1716 wol->wolopts |= WAKE_BCAST; 1734static void
1717 if (adapter->wol & E1000_WUFC_MAG) 1735e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1718 wol->wolopts |= WAKE_MAGIC; 1736{
1737 struct e1000_adapter *adapter = netdev_priv(netdev);
1738
1739 wol->supported = WAKE_UCAST | WAKE_MCAST |
1740 WAKE_BCAST | WAKE_MAGIC;
1741 wol->wolopts = 0;
1742
1743 /* this function will set ->supported = 0 and return 1 if wol is not
1744 * supported by this hardware */
1745 if (e1000_wol_exclusion(adapter, wol))
1719 return; 1746 return;
1747
1748 /* apply any specific unsupported masks here */
1749 switch (adapter->hw.device_id) {
1750 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1751 /* KSP3 does not suppport UCAST wake-ups */
1752 wol->supported &= ~WAKE_UCAST;
1753
1754 if (adapter->wol & E1000_WUFC_EX)
1755 DPRINTK(DRV, ERR, "Interface does not support "
1756 "directed (unicast) frame wake-up packets\n");
1757 break;
1758 default:
1759 break;
1720 } 1760 }
1761
1762 if (adapter->wol & E1000_WUFC_EX)
1763 wol->wolopts |= WAKE_UCAST;
1764 if (adapter->wol & E1000_WUFC_MC)
1765 wol->wolopts |= WAKE_MCAST;
1766 if (adapter->wol & E1000_WUFC_BC)
1767 wol->wolopts |= WAKE_BCAST;
1768 if (adapter->wol & E1000_WUFC_MAG)
1769 wol->wolopts |= WAKE_MAGIC;
1770
1771 return;
1721} 1772}
1722 1773
1723static int 1774static int
@@ -1726,51 +1777,35 @@ e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1726 struct e1000_adapter *adapter = netdev_priv(netdev); 1777 struct e1000_adapter *adapter = netdev_priv(netdev);
1727 struct e1000_hw *hw = &adapter->hw; 1778 struct e1000_hw *hw = &adapter->hw;
1728 1779
1729 switch (adapter->hw.device_id) { 1780 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1730 case E1000_DEV_ID_82542: 1781 return -EOPNOTSUPP;
1731 case E1000_DEV_ID_82543GC_FIBER: 1782
1732 case E1000_DEV_ID_82543GC_COPPER: 1783 if (e1000_wol_exclusion(adapter, wol))
1733 case E1000_DEV_ID_82544EI_FIBER:
1734 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1735 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1736 case E1000_DEV_ID_82545EM_FIBER:
1737 case E1000_DEV_ID_82545EM_COPPER:
1738 return wol->wolopts ? -EOPNOTSUPP : 0; 1784 return wol->wolopts ? -EOPNOTSUPP : 0;
1739 1785
1786 switch (hw->device_id) {
1740 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1787 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1741 /* device id 10B5 port-A supports wol */
1742 if (!adapter->ksp3_port_a)
1743 return wol->wolopts ? -EOPNOTSUPP : 0;
1744
1745 if (wol->wolopts & WAKE_UCAST) { 1788 if (wol->wolopts & WAKE_UCAST) {
1746 DPRINTK(DRV, ERR, "Interface does not support " 1789 DPRINTK(DRV, ERR, "Interface does not support "
1747 "directed (unicast) frame wake-up packets\n"); 1790 "directed (unicast) frame wake-up packets\n");
1748 return -EOPNOTSUPP; 1791 return -EOPNOTSUPP;
1749 } 1792 }
1750 1793 break;
1751 case E1000_DEV_ID_82546EB_FIBER:
1752 case E1000_DEV_ID_82546GB_FIBER:
1753 case E1000_DEV_ID_82571EB_FIBER:
1754 /* Wake events only supported on port A for dual fiber */
1755 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1756 return wol->wolopts ? -EOPNOTSUPP : 0;
1757 /* Fall Through */
1758
1759 default: 1794 default:
1760 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 1795 break;
1761 return -EOPNOTSUPP; 1796 }
1762 1797
1763 adapter->wol = 0; 1798 /* these settings will always override what we currently have */
1799 adapter->wol = 0;
1764 1800
1765 if (wol->wolopts & WAKE_UCAST) 1801 if (wol->wolopts & WAKE_UCAST)
1766 adapter->wol |= E1000_WUFC_EX; 1802 adapter->wol |= E1000_WUFC_EX;
1767 if (wol->wolopts & WAKE_MCAST) 1803 if (wol->wolopts & WAKE_MCAST)
1768 adapter->wol |= E1000_WUFC_MC; 1804 adapter->wol |= E1000_WUFC_MC;
1769 if (wol->wolopts & WAKE_BCAST) 1805 if (wol->wolopts & WAKE_BCAST)
1770 adapter->wol |= E1000_WUFC_BC; 1806 adapter->wol |= E1000_WUFC_BC;
1771 if (wol->wolopts & WAKE_MAGIC) 1807 if (wol->wolopts & WAKE_MAGIC)
1772 adapter->wol |= E1000_WUFC_MAG; 1808 adapter->wol |= E1000_WUFC_MAG;
1773 }
1774 1809
1775 return 0; 1810 return 0;
1776} 1811}
@@ -1895,8 +1930,8 @@ static struct ethtool_ops e1000_ethtool_ops = {
1895 .get_regs = e1000_get_regs, 1930 .get_regs = e1000_get_regs,
1896 .get_wol = e1000_get_wol, 1931 .get_wol = e1000_get_wol,
1897 .set_wol = e1000_set_wol, 1932 .set_wol = e1000_set_wol,
1898 .get_msglevel = e1000_get_msglevel, 1933 .get_msglevel = e1000_get_msglevel,
1899 .set_msglevel = e1000_set_msglevel, 1934 .set_msglevel = e1000_set_msglevel,
1900 .nway_reset = e1000_nway_reset, 1935 .nway_reset = e1000_nway_reset,
1901 .get_link = ethtool_op_get_link, 1936 .get_link = ethtool_op_get_link,
1902 .get_eeprom_len = e1000_get_eeprom_len, 1937 .get_eeprom_len = e1000_get_eeprom_len,
@@ -1904,17 +1939,17 @@ static struct ethtool_ops e1000_ethtool_ops = {
1904 .set_eeprom = e1000_set_eeprom, 1939 .set_eeprom = e1000_set_eeprom,
1905 .get_ringparam = e1000_get_ringparam, 1940 .get_ringparam = e1000_get_ringparam,
1906 .set_ringparam = e1000_set_ringparam, 1941 .set_ringparam = e1000_set_ringparam,
1907 .get_pauseparam = e1000_get_pauseparam, 1942 .get_pauseparam = e1000_get_pauseparam,
1908 .set_pauseparam = e1000_set_pauseparam, 1943 .set_pauseparam = e1000_set_pauseparam,
1909 .get_rx_csum = e1000_get_rx_csum, 1944 .get_rx_csum = e1000_get_rx_csum,
1910 .set_rx_csum = e1000_set_rx_csum, 1945 .set_rx_csum = e1000_set_rx_csum,
1911 .get_tx_csum = e1000_get_tx_csum, 1946 .get_tx_csum = e1000_get_tx_csum,
1912 .set_tx_csum = e1000_set_tx_csum, 1947 .set_tx_csum = e1000_set_tx_csum,
1913 .get_sg = ethtool_op_get_sg, 1948 .get_sg = ethtool_op_get_sg,
1914 .set_sg = ethtool_op_set_sg, 1949 .set_sg = ethtool_op_set_sg,
1915#ifdef NETIF_F_TSO 1950#ifdef NETIF_F_TSO
1916 .get_tso = ethtool_op_get_tso, 1951 .get_tso = ethtool_op_get_tso,
1917 .set_tso = e1000_set_tso, 1952 .set_tso = e1000_set_tso,
1918#endif 1953#endif
1919 .self_test_count = e1000_diag_test_count, 1954 .self_test_count = e1000_diag_test_count,
1920 .self_test = e1000_diag_test, 1955 .self_test = e1000_diag_test,
@@ -1922,7 +1957,7 @@ static struct ethtool_ops e1000_ethtool_ops = {
1922 .phys_id = e1000_phys_id, 1957 .phys_id = e1000_phys_id,
1923 .get_stats_count = e1000_get_stats_count, 1958 .get_stats_count = e1000_get_stats_count,
1924 .get_ethtool_stats = e1000_get_ethtool_stats, 1959 .get_ethtool_stats = e1000_get_ethtool_stats,
1925 .get_perm_addr = ethtool_op_get_perm_addr, 1960 .get_perm_addr = ethtool_op_get_perm_addr,
1926}; 1961};
1927 1962
1928void e1000_set_ethtool_ops(struct net_device *netdev) 1963void e1000_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index b3b919116e0f..a6f8f4fce701 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -31,6 +31,7 @@
31 * Shared functions for accessing and configuring the MAC 31 * Shared functions for accessing and configuring the MAC
32 */ 32 */
33 33
34
34#include "e1000_hw.h" 35#include "e1000_hw.h"
35 36
36static int32_t e1000_set_phy_type(struct e1000_hw *hw); 37static int32_t e1000_set_phy_type(struct e1000_hw *hw);
@@ -166,10 +167,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
166{ 167{
167 DEBUGFUNC("e1000_set_phy_type"); 168 DEBUGFUNC("e1000_set_phy_type");
168 169
169 if(hw->mac_type == e1000_undefined) 170 if (hw->mac_type == e1000_undefined)
170 return -E1000_ERR_PHY_TYPE; 171 return -E1000_ERR_PHY_TYPE;
171 172
172 switch(hw->phy_id) { 173 switch (hw->phy_id) {
173 case M88E1000_E_PHY_ID: 174 case M88E1000_E_PHY_ID:
174 case M88E1000_I_PHY_ID: 175 case M88E1000_I_PHY_ID:
175 case M88E1011_I_PHY_ID: 176 case M88E1011_I_PHY_ID:
@@ -177,10 +178,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
177 hw->phy_type = e1000_phy_m88; 178 hw->phy_type = e1000_phy_m88;
178 break; 179 break;
179 case IGP01E1000_I_PHY_ID: 180 case IGP01E1000_I_PHY_ID:
180 if(hw->mac_type == e1000_82541 || 181 if (hw->mac_type == e1000_82541 ||
181 hw->mac_type == e1000_82541_rev_2 || 182 hw->mac_type == e1000_82541_rev_2 ||
182 hw->mac_type == e1000_82547 || 183 hw->mac_type == e1000_82547 ||
183 hw->mac_type == e1000_82547_rev_2) { 184 hw->mac_type == e1000_82547_rev_2) {
184 hw->phy_type = e1000_phy_igp; 185 hw->phy_type = e1000_phy_igp;
185 break; 186 break;
186 } 187 }
@@ -207,6 +208,7 @@ e1000_set_phy_type(struct e1000_hw *hw)
207 return E1000_SUCCESS; 208 return E1000_SUCCESS;
208} 209}
209 210
211
210/****************************************************************************** 212/******************************************************************************
211 * IGP phy init script - initializes the GbE PHY 213 * IGP phy init script - initializes the GbE PHY
212 * 214 *
@@ -220,7 +222,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
220 222
221 DEBUGFUNC("e1000_phy_init_script"); 223 DEBUGFUNC("e1000_phy_init_script");
222 224
223 if(hw->phy_init_script) { 225 if (hw->phy_init_script) {
224 msec_delay(20); 226 msec_delay(20);
225 227
226 /* Save off the current value of register 0x2F5B to be restored at 228 /* Save off the current value of register 0x2F5B to be restored at
@@ -236,7 +238,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
236 238
237 msec_delay(5); 239 msec_delay(5);
238 240
239 switch(hw->mac_type) { 241 switch (hw->mac_type) {
240 case e1000_82541: 242 case e1000_82541:
241 case e1000_82547: 243 case e1000_82547:
242 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 244 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
@@ -273,22 +275,22 @@ e1000_phy_init_script(struct e1000_hw *hw)
273 /* Now enable the transmitter */ 275 /* Now enable the transmitter */
274 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 276 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
275 277
276 if(hw->mac_type == e1000_82547) { 278 if (hw->mac_type == e1000_82547) {
277 uint16_t fused, fine, coarse; 279 uint16_t fused, fine, coarse;
278 280
279 /* Move to analog registers page */ 281 /* Move to analog registers page */
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 282 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
281 283
282 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 284 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
283 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); 285 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
284 286
285 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 287 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
286 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 288 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
287 289
288 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 290 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
289 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 291 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
290 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 292 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
291 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 293 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
292 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 294 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
293 295
294 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 296 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
@@ -387,6 +389,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
387 case E1000_DEV_ID_82571EB_COPPER: 389 case E1000_DEV_ID_82571EB_COPPER:
388 case E1000_DEV_ID_82571EB_FIBER: 390 case E1000_DEV_ID_82571EB_FIBER:
389 case E1000_DEV_ID_82571EB_SERDES: 391 case E1000_DEV_ID_82571EB_SERDES:
392 case E1000_DEV_ID_82571EB_QUAD_COPPER:
390 hw->mac_type = e1000_82571; 393 hw->mac_type = e1000_82571;
391 break; 394 break;
392 case E1000_DEV_ID_82572EI_COPPER: 395 case E1000_DEV_ID_82572EI_COPPER:
@@ -418,7 +421,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
418 return -E1000_ERR_MAC_TYPE; 421 return -E1000_ERR_MAC_TYPE;
419 } 422 }
420 423
421 switch(hw->mac_type) { 424 switch (hw->mac_type) {
422 case e1000_ich8lan: 425 case e1000_ich8lan:
423 hw->swfwhw_semaphore_present = TRUE; 426 hw->swfwhw_semaphore_present = TRUE;
424 hw->asf_firmware_present = TRUE; 427 hw->asf_firmware_present = TRUE;
@@ -456,7 +459,7 @@ e1000_set_media_type(struct e1000_hw *hw)
456 459
457 DEBUGFUNC("e1000_set_media_type"); 460 DEBUGFUNC("e1000_set_media_type");
458 461
459 if(hw->mac_type != e1000_82543) { 462 if (hw->mac_type != e1000_82543) {
460 /* tbi_compatibility is only valid on 82543 */ 463 /* tbi_compatibility is only valid on 82543 */
461 hw->tbi_compatibility_en = FALSE; 464 hw->tbi_compatibility_en = FALSE;
462 } 465 }
@@ -516,16 +519,16 @@ e1000_reset_hw(struct e1000_hw *hw)
516 DEBUGFUNC("e1000_reset_hw"); 519 DEBUGFUNC("e1000_reset_hw");
517 520
518 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 521 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
519 if(hw->mac_type == e1000_82542_rev2_0) { 522 if (hw->mac_type == e1000_82542_rev2_0) {
520 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 523 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
521 e1000_pci_clear_mwi(hw); 524 e1000_pci_clear_mwi(hw);
522 } 525 }
523 526
524 if(hw->bus_type == e1000_bus_type_pci_express) { 527 if (hw->bus_type == e1000_bus_type_pci_express) {
525 /* Prevent the PCI-E bus from sticking if there is no TLP connection 528 /* Prevent the PCI-E bus from sticking if there is no TLP connection
526 * on the last TLP read/write transaction when MAC is reset. 529 * on the last TLP read/write transaction when MAC is reset.
527 */ 530 */
528 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { 531 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
529 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 532 DEBUGOUT("PCI-E Master disable polling has failed.\n");
530 } 533 }
531 } 534 }
@@ -553,14 +556,14 @@ e1000_reset_hw(struct e1000_hw *hw)
553 ctrl = E1000_READ_REG(hw, CTRL); 556 ctrl = E1000_READ_REG(hw, CTRL);
554 557
555 /* Must reset the PHY before resetting the MAC */ 558 /* Must reset the PHY before resetting the MAC */
556 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 559 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
557 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 560 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
558 msec_delay(5); 561 msec_delay(5);
559 } 562 }
560 563
561 /* Must acquire the MDIO ownership before MAC reset. 564 /* Must acquire the MDIO ownership before MAC reset.
562 * Ownership defaults to firmware after a reset. */ 565 * Ownership defaults to firmware after a reset. */
563 if(hw->mac_type == e1000_82573) { 566 if (hw->mac_type == e1000_82573) {
564 timeout = 10; 567 timeout = 10;
565 568
566 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 569 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
@@ -570,14 +573,14 @@ e1000_reset_hw(struct e1000_hw *hw)
570 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 573 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
571 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 574 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
572 575
573 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 576 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
574 break; 577 break;
575 else 578 else
576 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 579 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
577 580
578 msec_delay(2); 581 msec_delay(2);
579 timeout--; 582 timeout--;
580 } while(timeout); 583 } while (timeout);
581 } 584 }
582 585
583 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 586 /* Workaround for ICH8 bit corruption issue in FIFO memory */
@@ -595,7 +598,7 @@ e1000_reset_hw(struct e1000_hw *hw)
595 */ 598 */
596 DEBUGOUT("Issuing a global reset to MAC\n"); 599 DEBUGOUT("Issuing a global reset to MAC\n");
597 600
598 switch(hw->mac_type) { 601 switch (hw->mac_type) {
599 case e1000_82544: 602 case e1000_82544:
600 case e1000_82540: 603 case e1000_82540:
601 case e1000_82545: 604 case e1000_82545:
@@ -634,7 +637,7 @@ e1000_reset_hw(struct e1000_hw *hw)
634 * device. Later controllers reload the EEPROM automatically, so just wait 637 * device. Later controllers reload the EEPROM automatically, so just wait
635 * for reload to complete. 638 * for reload to complete.
636 */ 639 */
637 switch(hw->mac_type) { 640 switch (hw->mac_type) {
638 case e1000_82542_rev2_0: 641 case e1000_82542_rev2_0:
639 case e1000_82542_rev2_1: 642 case e1000_82542_rev2_1:
640 case e1000_82543: 643 case e1000_82543:
@@ -669,7 +672,7 @@ e1000_reset_hw(struct e1000_hw *hw)
669 case e1000_ich8lan: 672 case e1000_ich8lan:
670 case e1000_80003es2lan: 673 case e1000_80003es2lan:
671 ret_val = e1000_get_auto_rd_done(hw); 674 ret_val = e1000_get_auto_rd_done(hw);
672 if(ret_val) 675 if (ret_val)
673 /* We don't want to continue accessing MAC registers. */ 676 /* We don't want to continue accessing MAC registers. */
674 return ret_val; 677 return ret_val;
675 break; 678 break;
@@ -680,13 +683,13 @@ e1000_reset_hw(struct e1000_hw *hw)
680 } 683 }
681 684
682 /* Disable HW ARPs on ASF enabled adapters */ 685 /* Disable HW ARPs on ASF enabled adapters */
683 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { 686 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
684 manc = E1000_READ_REG(hw, MANC); 687 manc = E1000_READ_REG(hw, MANC);
685 manc &= ~(E1000_MANC_ARP_EN); 688 manc &= ~(E1000_MANC_ARP_EN);
686 E1000_WRITE_REG(hw, MANC, manc); 689 E1000_WRITE_REG(hw, MANC, manc);
687 } 690 }
688 691
689 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 692 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
690 e1000_phy_init_script(hw); 693 e1000_phy_init_script(hw);
691 694
692 /* Configure activity LED after PHY reset */ 695 /* Configure activity LED after PHY reset */
@@ -704,8 +707,8 @@ e1000_reset_hw(struct e1000_hw *hw)
704 icr = E1000_READ_REG(hw, ICR); 707 icr = E1000_READ_REG(hw, ICR);
705 708
706 /* If MWI was previously enabled, reenable it. */ 709 /* If MWI was previously enabled, reenable it. */
707 if(hw->mac_type == e1000_82542_rev2_0) { 710 if (hw->mac_type == e1000_82542_rev2_0) {
708 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 711 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
709 e1000_pci_set_mwi(hw); 712 e1000_pci_set_mwi(hw);
710 } 713 }
711 714
@@ -745,9 +748,20 @@ e1000_init_hw(struct e1000_hw *hw)
745 748
746 DEBUGFUNC("e1000_init_hw"); 749 DEBUGFUNC("e1000_init_hw");
747 750
751 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
752 if (hw->mac_type == e1000_ich8lan) {
753 reg_data = E1000_READ_REG(hw, TARC0);
754 reg_data |= 0x30000000;
755 E1000_WRITE_REG(hw, TARC0, reg_data);
756
757 reg_data = E1000_READ_REG(hw, STATUS);
758 reg_data &= ~0x80000000;
759 E1000_WRITE_REG(hw, STATUS, reg_data);
760 }
761
748 /* Initialize Identification LED */ 762 /* Initialize Identification LED */
749 ret_val = e1000_id_led_init(hw); 763 ret_val = e1000_id_led_init(hw);
750 if(ret_val) { 764 if (ret_val) {
751 DEBUGOUT("Error Initializing Identification LED\n"); 765 DEBUGOUT("Error Initializing Identification LED\n");
752 return ret_val; 766 return ret_val;
753 } 767 }
@@ -765,7 +779,7 @@ e1000_init_hw(struct e1000_hw *hw)
765 } 779 }
766 780
767 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 781 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
768 if(hw->mac_type == e1000_82542_rev2_0) { 782 if (hw->mac_type == e1000_82542_rev2_0) {
769 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 783 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
770 e1000_pci_clear_mwi(hw); 784 e1000_pci_clear_mwi(hw);
771 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 785 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
@@ -779,11 +793,11 @@ e1000_init_hw(struct e1000_hw *hw)
779 e1000_init_rx_addrs(hw); 793 e1000_init_rx_addrs(hw);
780 794
781 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 795 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
782 if(hw->mac_type == e1000_82542_rev2_0) { 796 if (hw->mac_type == e1000_82542_rev2_0) {
783 E1000_WRITE_REG(hw, RCTL, 0); 797 E1000_WRITE_REG(hw, RCTL, 0);
784 E1000_WRITE_FLUSH(hw); 798 E1000_WRITE_FLUSH(hw);
785 msec_delay(1); 799 msec_delay(1);
786 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 800 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
787 e1000_pci_set_mwi(hw); 801 e1000_pci_set_mwi(hw);
788 } 802 }
789 803
@@ -792,7 +806,7 @@ e1000_init_hw(struct e1000_hw *hw)
792 mta_size = E1000_MC_TBL_SIZE; 806 mta_size = E1000_MC_TBL_SIZE;
793 if (hw->mac_type == e1000_ich8lan) 807 if (hw->mac_type == e1000_ich8lan)
794 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 808 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
795 for(i = 0; i < mta_size; i++) { 809 for (i = 0; i < mta_size; i++) {
796 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 810 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
797 /* use write flush to prevent Memory Write Block (MWB) from 811 /* use write flush to prevent Memory Write Block (MWB) from
798 * occuring when accessing our register space */ 812 * occuring when accessing our register space */
@@ -804,18 +818,18 @@ e1000_init_hw(struct e1000_hw *hw)
804 * gives equal priority to transmits and receives. Valid only on 818 * gives equal priority to transmits and receives. Valid only on
805 * 82542 and 82543 silicon. 819 * 82542 and 82543 silicon.
806 */ 820 */
807 if(hw->dma_fairness && hw->mac_type <= e1000_82543) { 821 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
808 ctrl = E1000_READ_REG(hw, CTRL); 822 ctrl = E1000_READ_REG(hw, CTRL);
809 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 823 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
810 } 824 }
811 825
812 switch(hw->mac_type) { 826 switch (hw->mac_type) {
813 case e1000_82545_rev_3: 827 case e1000_82545_rev_3:
814 case e1000_82546_rev_3: 828 case e1000_82546_rev_3:
815 break; 829 break;
816 default: 830 default:
817 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 831 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
818 if(hw->bus_type == e1000_bus_type_pcix) { 832 if (hw->bus_type == e1000_bus_type_pcix) {
819 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 833 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
820 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 834 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
821 &pcix_stat_hi_word); 835 &pcix_stat_hi_word);
@@ -823,9 +837,9 @@ e1000_init_hw(struct e1000_hw *hw)
823 PCIX_COMMAND_MMRBC_SHIFT; 837 PCIX_COMMAND_MMRBC_SHIFT;
824 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 838 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
825 PCIX_STATUS_HI_MMRBC_SHIFT; 839 PCIX_STATUS_HI_MMRBC_SHIFT;
826 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 840 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
827 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 841 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
828 if(cmd_mmrbc > stat_mmrbc) { 842 if (cmd_mmrbc > stat_mmrbc) {
829 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 843 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
830 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 844 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
831 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 845 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
@@ -843,7 +857,7 @@ e1000_init_hw(struct e1000_hw *hw)
843 ret_val = e1000_setup_link(hw); 857 ret_val = e1000_setup_link(hw);
844 858
845 /* Set the transmit descriptor write-back policy */ 859 /* Set the transmit descriptor write-back policy */
846 if(hw->mac_type > e1000_82544) { 860 if (hw->mac_type > e1000_82544) {
847 ctrl = E1000_READ_REG(hw, TXDCTL); 861 ctrl = E1000_READ_REG(hw, TXDCTL);
848 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 862 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
849 switch (hw->mac_type) { 863 switch (hw->mac_type) {
@@ -894,14 +908,13 @@ e1000_init_hw(struct e1000_hw *hw)
894 case e1000_ich8lan: 908 case e1000_ich8lan:
895 ctrl = E1000_READ_REG(hw, TXDCTL1); 909 ctrl = E1000_READ_REG(hw, TXDCTL1);
896 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 910 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
897 if(hw->mac_type >= e1000_82571) 911 if (hw->mac_type >= e1000_82571)
898 ctrl |= E1000_TXDCTL_COUNT_DESC; 912 ctrl |= E1000_TXDCTL_COUNT_DESC;
899 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 913 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
900 break; 914 break;
901 } 915 }
902 916
903 917
904
905 if (hw->mac_type == e1000_82573) { 918 if (hw->mac_type == e1000_82573) {
906 uint32_t gcr = E1000_READ_REG(hw, GCR); 919 uint32_t gcr = E1000_READ_REG(hw, GCR);
907 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 920 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
@@ -945,10 +958,10 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
945 958
946 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 959 DEBUGFUNC("e1000_adjust_serdes_amplitude");
947 960
948 if(hw->media_type != e1000_media_type_internal_serdes) 961 if (hw->media_type != e1000_media_type_internal_serdes)
949 return E1000_SUCCESS; 962 return E1000_SUCCESS;
950 963
951 switch(hw->mac_type) { 964 switch (hw->mac_type) {
952 case e1000_82545_rev_3: 965 case e1000_82545_rev_3:
953 case e1000_82546_rev_3: 966 case e1000_82546_rev_3:
954 break; 967 break;
@@ -961,11 +974,11 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
961 return ret_val; 974 return ret_val;
962 } 975 }
963 976
964 if(eeprom_data != EEPROM_RESERVED_WORD) { 977 if (eeprom_data != EEPROM_RESERVED_WORD) {
965 /* Adjust SERDES output amplitude only. */ 978 /* Adjust SERDES output amplitude only. */
966 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 979 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
967 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 980 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
968 if(ret_val) 981 if (ret_val)
969 return ret_val; 982 return ret_val;
970 } 983 }
971 984
@@ -1033,10 +1046,10 @@ e1000_setup_link(struct e1000_hw *hw)
1033 * in case we get disconnected and then reconnected into a different 1046 * in case we get disconnected and then reconnected into a different
1034 * hub or switch with different Flow Control capabilities. 1047 * hub or switch with different Flow Control capabilities.
1035 */ 1048 */
1036 if(hw->mac_type == e1000_82542_rev2_0) 1049 if (hw->mac_type == e1000_82542_rev2_0)
1037 hw->fc &= (~e1000_fc_tx_pause); 1050 hw->fc &= (~e1000_fc_tx_pause);
1038 1051
1039 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1052 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1040 hw->fc &= (~e1000_fc_rx_pause); 1053 hw->fc &= (~e1000_fc_rx_pause);
1041 1054
1042 hw->original_fc = hw->fc; 1055 hw->original_fc = hw->fc;
@@ -1051,12 +1064,12 @@ e1000_setup_link(struct e1000_hw *hw)
1051 * or e1000_phy_setup() is called. 1064 * or e1000_phy_setup() is called.
1052 */ 1065 */
1053 if (hw->mac_type == e1000_82543) { 1066 if (hw->mac_type == e1000_82543) {
1054 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1067 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1055 1, &eeprom_data); 1068 1, &eeprom_data);
1056 if (ret_val) { 1069 if (ret_val) {
1057 DEBUGOUT("EEPROM Read Error\n"); 1070 DEBUGOUT("EEPROM Read Error\n");
1058 return -E1000_ERR_EEPROM; 1071 return -E1000_ERR_EEPROM;
1059 } 1072 }
1060 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1073 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1061 SWDPIO__EXT_SHIFT); 1074 SWDPIO__EXT_SHIFT);
1062 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1075 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
@@ -1089,14 +1102,14 @@ e1000_setup_link(struct e1000_hw *hw)
1089 * ability to transmit pause frames in not enabled, then these 1102 * ability to transmit pause frames in not enabled, then these
1090 * registers will be set to 0. 1103 * registers will be set to 0.
1091 */ 1104 */
1092 if(!(hw->fc & e1000_fc_tx_pause)) { 1105 if (!(hw->fc & e1000_fc_tx_pause)) {
1093 E1000_WRITE_REG(hw, FCRTL, 0); 1106 E1000_WRITE_REG(hw, FCRTL, 0);
1094 E1000_WRITE_REG(hw, FCRTH, 0); 1107 E1000_WRITE_REG(hw, FCRTH, 0);
1095 } else { 1108 } else {
1096 /* We need to set up the Receive Threshold high and low water marks 1109 /* We need to set up the Receive Threshold high and low water marks
1097 * as well as (optionally) enabling the transmission of XON frames. 1110 * as well as (optionally) enabling the transmission of XON frames.
1098 */ 1111 */
1099 if(hw->fc_send_xon) { 1112 if (hw->fc_send_xon) {
1100 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1113 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1101 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1114 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1102 } else { 1115 } else {
@@ -1143,11 +1156,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1143 * the EEPROM. 1156 * the EEPROM.
1144 */ 1157 */
1145 ctrl = E1000_READ_REG(hw, CTRL); 1158 ctrl = E1000_READ_REG(hw, CTRL);
1146 if(hw->media_type == e1000_media_type_fiber) 1159 if (hw->media_type == e1000_media_type_fiber)
1147 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 1160 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1148 1161
1149 ret_val = e1000_adjust_serdes_amplitude(hw); 1162 ret_val = e1000_adjust_serdes_amplitude(hw);
1150 if(ret_val) 1163 if (ret_val)
1151 return ret_val; 1164 return ret_val;
1152 1165
1153 /* Take the link out of reset */ 1166 /* Take the link out of reset */
@@ -1155,7 +1168,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1155 1168
1156 /* Adjust VCO speed to improve BER performance */ 1169 /* Adjust VCO speed to improve BER performance */
1157 ret_val = e1000_set_vco_speed(hw); 1170 ret_val = e1000_set_vco_speed(hw);
1158 if(ret_val) 1171 if (ret_val)
1159 return ret_val; 1172 return ret_val;
1160 1173
1161 e1000_config_collision_dist(hw); 1174 e1000_config_collision_dist(hw);
@@ -1226,15 +1239,15 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1226 * less than 500 milliseconds even if the other end is doing it in SW). 1239 * less than 500 milliseconds even if the other end is doing it in SW).
1227 * For internal serdes, we just assume a signal is present, then poll. 1240 * For internal serdes, we just assume a signal is present, then poll.
1228 */ 1241 */
1229 if(hw->media_type == e1000_media_type_internal_serdes || 1242 if (hw->media_type == e1000_media_type_internal_serdes ||
1230 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1243 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1231 DEBUGOUT("Looking for Link\n"); 1244 DEBUGOUT("Looking for Link\n");
1232 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1245 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1233 msec_delay(10); 1246 msec_delay(10);
1234 status = E1000_READ_REG(hw, STATUS); 1247 status = E1000_READ_REG(hw, STATUS);
1235 if(status & E1000_STATUS_LU) break; 1248 if (status & E1000_STATUS_LU) break;
1236 } 1249 }
1237 if(i == (LINK_UP_TIMEOUT / 10)) { 1250 if (i == (LINK_UP_TIMEOUT / 10)) {
1238 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1251 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1239 hw->autoneg_failed = 1; 1252 hw->autoneg_failed = 1;
1240 /* AutoNeg failed to achieve a link, so we'll call 1253 /* AutoNeg failed to achieve a link, so we'll call
@@ -1243,7 +1256,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1243 * non-autonegotiating link partners. 1256 * non-autonegotiating link partners.
1244 */ 1257 */
1245 ret_val = e1000_check_for_link(hw); 1258 ret_val = e1000_check_for_link(hw);
1246 if(ret_val) { 1259 if (ret_val) {
1247 DEBUGOUT("Error while checking for link\n"); 1260 DEBUGOUT("Error while checking for link\n");
1248 return ret_val; 1261 return ret_val;
1249 } 1262 }
@@ -1277,7 +1290,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1277 * the PHY speed and duplex configuration is. In addition, we need to 1290 * the PHY speed and duplex configuration is. In addition, we need to
1278 * perform a hardware reset on the PHY to take it out of reset. 1291 * perform a hardware reset on the PHY to take it out of reset.
1279 */ 1292 */
1280 if(hw->mac_type > e1000_82543) { 1293 if (hw->mac_type > e1000_82543) {
1281 ctrl |= E1000_CTRL_SLU; 1294 ctrl |= E1000_CTRL_SLU;
1282 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1295 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1283 E1000_WRITE_REG(hw, CTRL, ctrl); 1296 E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -1285,13 +1298,13 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1285 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1298 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1286 E1000_WRITE_REG(hw, CTRL, ctrl); 1299 E1000_WRITE_REG(hw, CTRL, ctrl);
1287 ret_val = e1000_phy_hw_reset(hw); 1300 ret_val = e1000_phy_hw_reset(hw);
1288 if(ret_val) 1301 if (ret_val)
1289 return ret_val; 1302 return ret_val;
1290 } 1303 }
1291 1304
1292 /* Make sure we have a valid PHY */ 1305 /* Make sure we have a valid PHY */
1293 ret_val = e1000_detect_gig_phy(hw); 1306 ret_val = e1000_detect_gig_phy(hw);
1294 if(ret_val) { 1307 if (ret_val) {
1295 DEBUGOUT("Error, did not detect valid phy.\n"); 1308 DEBUGOUT("Error, did not detect valid phy.\n");
1296 return ret_val; 1309 return ret_val;
1297 } 1310 }
@@ -1299,19 +1312,19 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1299 1312
1300 /* Set PHY to class A mode (if necessary) */ 1313 /* Set PHY to class A mode (if necessary) */
1301 ret_val = e1000_set_phy_mode(hw); 1314 ret_val = e1000_set_phy_mode(hw);
1302 if(ret_val) 1315 if (ret_val)
1303 return ret_val; 1316 return ret_val;
1304 1317
1305 if((hw->mac_type == e1000_82545_rev_3) || 1318 if ((hw->mac_type == e1000_82545_rev_3) ||
1306 (hw->mac_type == e1000_82546_rev_3)) { 1319 (hw->mac_type == e1000_82546_rev_3)) {
1307 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1320 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1308 phy_data |= 0x00000008; 1321 phy_data |= 0x00000008;
1309 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1322 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1310 } 1323 }
1311 1324
1312 if(hw->mac_type <= e1000_82543 || 1325 if (hw->mac_type <= e1000_82543 ||
1313 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1326 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1314 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1327 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1315 hw->phy_reset_disable = FALSE; 1328 hw->phy_reset_disable = FALSE;
1316 1329
1317 return E1000_SUCCESS; 1330 return E1000_SUCCESS;
@@ -1341,7 +1354,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1341 return ret_val; 1354 return ret_val;
1342 } 1355 }
1343 1356
1344 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1357 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1345 msec_delay(15); 1358 msec_delay(15);
1346 if (hw->mac_type != e1000_ich8lan) { 1359 if (hw->mac_type != e1000_ich8lan) {
1347 /* Configure activity LED after PHY reset */ 1360 /* Configure activity LED after PHY reset */
@@ -1351,11 +1364,14 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1351 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1364 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1352 } 1365 }
1353 1366
1354 /* disable lplu d3 during driver init */ 1367 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1355 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1368 if (hw->phy_type == e1000_phy_igp) {
1356 if (ret_val) { 1369 /* disable lplu d3 during driver init */
1357 DEBUGOUT("Error Disabling LPLU D3\n"); 1370 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1358 return ret_val; 1371 if (ret_val) {
1372 DEBUGOUT("Error Disabling LPLU D3\n");
1373 return ret_val;
1374 }
1359 } 1375 }
1360 1376
1361 /* disable lplu d0 during driver init */ 1377 /* disable lplu d0 during driver init */
@@ -1393,45 +1409,45 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1393 } 1409 }
1394 } 1410 }
1395 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1411 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1396 if(ret_val) 1412 if (ret_val)
1397 return ret_val; 1413 return ret_val;
1398 1414
1399 /* set auto-master slave resolution settings */ 1415 /* set auto-master slave resolution settings */
1400 if(hw->autoneg) { 1416 if (hw->autoneg) {
1401 e1000_ms_type phy_ms_setting = hw->master_slave; 1417 e1000_ms_type phy_ms_setting = hw->master_slave;
1402 1418
1403 if(hw->ffe_config_state == e1000_ffe_config_active) 1419 if (hw->ffe_config_state == e1000_ffe_config_active)
1404 hw->ffe_config_state = e1000_ffe_config_enabled; 1420 hw->ffe_config_state = e1000_ffe_config_enabled;
1405 1421
1406 if(hw->dsp_config_state == e1000_dsp_config_activated) 1422 if (hw->dsp_config_state == e1000_dsp_config_activated)
1407 hw->dsp_config_state = e1000_dsp_config_enabled; 1423 hw->dsp_config_state = e1000_dsp_config_enabled;
1408 1424
1409 /* when autonegotiation advertisment is only 1000Mbps then we 1425 /* when autonegotiation advertisment is only 1000Mbps then we
1410 * should disable SmartSpeed and enable Auto MasterSlave 1426 * should disable SmartSpeed and enable Auto MasterSlave
1411 * resolution as hardware default. */ 1427 * resolution as hardware default. */
1412 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1428 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1413 /* Disable SmartSpeed */ 1429 /* Disable SmartSpeed */
1414 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 1430 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1415 if(ret_val) 1431 &phy_data);
1432 if (ret_val)
1416 return ret_val; 1433 return ret_val;
1417 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1434 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1418 ret_val = e1000_write_phy_reg(hw, 1435 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1419 IGP01E1000_PHY_PORT_CONFIG, 1436 phy_data);
1420 phy_data); 1437 if (ret_val)
1421 if(ret_val)
1422 return ret_val; 1438 return ret_val;
1423 /* Set auto Master/Slave resolution process */ 1439 /* Set auto Master/Slave resolution process */
1424 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1440 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1425 if(ret_val) 1441 if (ret_val)
1426 return ret_val; 1442 return ret_val;
1427 phy_data &= ~CR_1000T_MS_ENABLE; 1443 phy_data &= ~CR_1000T_MS_ENABLE;
1428 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1444 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1429 if(ret_val) 1445 if (ret_val)
1430 return ret_val; 1446 return ret_val;
1431 } 1447 }
1432 1448
1433 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1449 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1434 if(ret_val) 1450 if (ret_val)
1435 return ret_val; 1451 return ret_val;
1436 1452
1437 /* load defaults for future use */ 1453 /* load defaults for future use */
@@ -1455,7 +1471,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1455 break; 1471 break;
1456 } 1472 }
1457 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1473 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1458 if(ret_val) 1474 if (ret_val)
1459 return ret_val; 1475 return ret_val;
1460 } 1476 }
1461 1477
@@ -1476,12 +1492,12 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1476 1492
1477 DEBUGFUNC("e1000_copper_link_ggp_setup"); 1493 DEBUGFUNC("e1000_copper_link_ggp_setup");
1478 1494
1479 if(!hw->phy_reset_disable) { 1495 if (!hw->phy_reset_disable) {
1480 1496
1481 /* Enable CRS on TX for half-duplex operation. */ 1497 /* Enable CRS on TX for half-duplex operation. */
1482 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1498 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1483 &phy_data); 1499 &phy_data);
1484 if(ret_val) 1500 if (ret_val)
1485 return ret_val; 1501 return ret_val;
1486 1502
1487 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1503 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -1490,7 +1506,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1490 1506
1491 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1507 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1492 phy_data); 1508 phy_data);
1493 if(ret_val) 1509 if (ret_val)
1494 return ret_val; 1510 return ret_val;
1495 1511
1496 /* Options: 1512 /* Options:
@@ -1501,7 +1517,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1501 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1517 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1502 */ 1518 */
1503 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); 1519 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1504 if(ret_val) 1520 if (ret_val)
1505 return ret_val; 1521 return ret_val;
1506 1522
1507 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1523 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
@@ -1526,11 +1542,11 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1526 * 1 - Enabled 1542 * 1 - Enabled
1527 */ 1543 */
1528 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1544 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1529 if(hw->disable_polarity_correction == 1) 1545 if (hw->disable_polarity_correction == 1)
1530 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1546 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1531 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 1547 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1532 1548
1533 if(ret_val) 1549 if (ret_val)
1534 return ret_val; 1550 return ret_val;
1535 1551
1536 /* SW Reset the PHY so all changes take effect */ 1552 /* SW Reset the PHY so all changes take effect */
@@ -1586,9 +1602,9 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1586 return ret_val; 1602 return ret_val;
1587 1603
1588 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1604 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1589
1590 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1605 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1591 phy_data); 1606 phy_data);
1607
1592 if (ret_val) 1608 if (ret_val)
1593 return ret_val; 1609 return ret_val;
1594 } 1610 }
@@ -1623,12 +1639,12 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1623 1639
1624 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1640 DEBUGFUNC("e1000_copper_link_mgp_setup");
1625 1641
1626 if(hw->phy_reset_disable) 1642 if (hw->phy_reset_disable)
1627 return E1000_SUCCESS; 1643 return E1000_SUCCESS;
1628 1644
1629 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1645 /* Enable CRS on TX. This must be set for half-duplex operation. */
1630 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1646 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1631 if(ret_val) 1647 if (ret_val)
1632 return ret_val; 1648 return ret_val;
1633 1649
1634 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1650 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
@@ -1665,7 +1681,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1665 * 1 - Enabled 1681 * 1 - Enabled
1666 */ 1682 */
1667 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1683 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1668 if(hw->disable_polarity_correction == 1) 1684 if (hw->disable_polarity_correction == 1)
1669 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1685 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1670 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1686 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1671 if (ret_val) 1687 if (ret_val)
@@ -1705,7 +1721,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1705 1721
1706 /* SW Reset the PHY so all changes take effect */ 1722 /* SW Reset the PHY so all changes take effect */
1707 ret_val = e1000_phy_reset(hw); 1723 ret_val = e1000_phy_reset(hw);
1708 if(ret_val) { 1724 if (ret_val) {
1709 DEBUGOUT("Error Resetting the PHY\n"); 1725 DEBUGOUT("Error Resetting the PHY\n");
1710 return ret_val; 1726 return ret_val;
1711 } 1727 }
@@ -1735,7 +1751,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1735 /* If autoneg_advertised is zero, we assume it was not defaulted 1751 /* If autoneg_advertised is zero, we assume it was not defaulted
1736 * by the calling code so we set to advertise full capability. 1752 * by the calling code so we set to advertise full capability.
1737 */ 1753 */
1738 if(hw->autoneg_advertised == 0) 1754 if (hw->autoneg_advertised == 0)
1739 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1755 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1740 1756
1741 /* IFE phy only supports 10/100 */ 1757 /* IFE phy only supports 10/100 */
@@ -1744,7 +1760,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1744 1760
1745 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1761 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1746 ret_val = e1000_phy_setup_autoneg(hw); 1762 ret_val = e1000_phy_setup_autoneg(hw);
1747 if(ret_val) { 1763 if (ret_val) {
1748 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1764 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1749 return ret_val; 1765 return ret_val;
1750 } 1766 }
@@ -1754,20 +1770,20 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1754 * the Auto Neg Restart bit in the PHY control register. 1770 * the Auto Neg Restart bit in the PHY control register.
1755 */ 1771 */
1756 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1772 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1757 if(ret_val) 1773 if (ret_val)
1758 return ret_val; 1774 return ret_val;
1759 1775
1760 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1776 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1761 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1777 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1762 if(ret_val) 1778 if (ret_val)
1763 return ret_val; 1779 return ret_val;
1764 1780
1765 /* Does the user want to wait for Auto-Neg to complete here, or 1781 /* Does the user want to wait for Auto-Neg to complete here, or
1766 * check at a later time (for example, callback routine). 1782 * check at a later time (for example, callback routine).
1767 */ 1783 */
1768 if(hw->wait_autoneg_complete) { 1784 if (hw->wait_autoneg_complete) {
1769 ret_val = e1000_wait_autoneg(hw); 1785 ret_val = e1000_wait_autoneg(hw);
1770 if(ret_val) { 1786 if (ret_val) {
1771 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1787 DEBUGOUT("Error while waiting for autoneg to complete\n");
1772 return ret_val; 1788 return ret_val;
1773 } 1789 }
@@ -1778,7 +1794,6 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1778 return E1000_SUCCESS; 1794 return E1000_SUCCESS;
1779} 1795}
1780 1796
1781
1782/****************************************************************************** 1797/******************************************************************************
1783* Config the MAC and the PHY after link is up. 1798* Config the MAC and the PHY after link is up.
1784* 1) Set up the MAC to the current PHY speed/duplex 1799* 1) Set up the MAC to the current PHY speed/duplex
@@ -1797,25 +1812,25 @@ e1000_copper_link_postconfig(struct e1000_hw *hw)
1797 int32_t ret_val; 1812 int32_t ret_val;
1798 DEBUGFUNC("e1000_copper_link_postconfig"); 1813 DEBUGFUNC("e1000_copper_link_postconfig");
1799 1814
1800 if(hw->mac_type >= e1000_82544) { 1815 if (hw->mac_type >= e1000_82544) {
1801 e1000_config_collision_dist(hw); 1816 e1000_config_collision_dist(hw);
1802 } else { 1817 } else {
1803 ret_val = e1000_config_mac_to_phy(hw); 1818 ret_val = e1000_config_mac_to_phy(hw);
1804 if(ret_val) { 1819 if (ret_val) {
1805 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1820 DEBUGOUT("Error configuring MAC to PHY settings\n");
1806 return ret_val; 1821 return ret_val;
1807 } 1822 }
1808 } 1823 }
1809 ret_val = e1000_config_fc_after_link_up(hw); 1824 ret_val = e1000_config_fc_after_link_up(hw);
1810 if(ret_val) { 1825 if (ret_val) {
1811 DEBUGOUT("Error Configuring Flow Control\n"); 1826 DEBUGOUT("Error Configuring Flow Control\n");
1812 return ret_val; 1827 return ret_val;
1813 } 1828 }
1814 1829
1815 /* Config DSP to improve Giga link quality */ 1830 /* Config DSP to improve Giga link quality */
1816 if(hw->phy_type == e1000_phy_igp) { 1831 if (hw->phy_type == e1000_phy_igp) {
1817 ret_val = e1000_config_dsp_after_link_change(hw, TRUE); 1832 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1818 if(ret_val) { 1833 if (ret_val) {
1819 DEBUGOUT("Error Configuring DSP after link up\n"); 1834 DEBUGOUT("Error Configuring DSP after link up\n");
1820 return ret_val; 1835 return ret_val;
1821 } 1836 }
@@ -1861,7 +1876,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1861 1876
1862 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1877 /* Check if it is a valid PHY and set PHY mode if necessary. */
1863 ret_val = e1000_copper_link_preconfig(hw); 1878 ret_val = e1000_copper_link_preconfig(hw);
1864 if(ret_val) 1879 if (ret_val)
1865 return ret_val; 1880 return ret_val;
1866 1881
1867 switch (hw->mac_type) { 1882 switch (hw->mac_type) {
@@ -1882,30 +1897,30 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1882 hw->phy_type == e1000_phy_igp_3 || 1897 hw->phy_type == e1000_phy_igp_3 ||
1883 hw->phy_type == e1000_phy_igp_2) { 1898 hw->phy_type == e1000_phy_igp_2) {
1884 ret_val = e1000_copper_link_igp_setup(hw); 1899 ret_val = e1000_copper_link_igp_setup(hw);
1885 if(ret_val) 1900 if (ret_val)
1886 return ret_val; 1901 return ret_val;
1887 } else if (hw->phy_type == e1000_phy_m88) { 1902 } else if (hw->phy_type == e1000_phy_m88) {
1888 ret_val = e1000_copper_link_mgp_setup(hw); 1903 ret_val = e1000_copper_link_mgp_setup(hw);
1889 if(ret_val) 1904 if (ret_val)
1890 return ret_val; 1905 return ret_val;
1891 } else if (hw->phy_type == e1000_phy_gg82563) { 1906 } else if (hw->phy_type == e1000_phy_gg82563) {
1892 ret_val = e1000_copper_link_ggp_setup(hw); 1907 ret_val = e1000_copper_link_ggp_setup(hw);
1893 if(ret_val) 1908 if (ret_val)
1894 return ret_val; 1909 return ret_val;
1895 } 1910 }
1896 1911
1897 if(hw->autoneg) { 1912 if (hw->autoneg) {
1898 /* Setup autoneg and flow control advertisement 1913 /* Setup autoneg and flow control advertisement
1899 * and perform autonegotiation */ 1914 * and perform autonegotiation */
1900 ret_val = e1000_copper_link_autoneg(hw); 1915 ret_val = e1000_copper_link_autoneg(hw);
1901 if(ret_val) 1916 if (ret_val)
1902 return ret_val; 1917 return ret_val;
1903 } else { 1918 } else {
1904 /* PHY will be set to 10H, 10F, 100H,or 100F 1919 /* PHY will be set to 10H, 10F, 100H,or 100F
1905 * depending on value from forced_speed_duplex. */ 1920 * depending on value from forced_speed_duplex. */
1906 DEBUGOUT("Forcing speed and duplex\n"); 1921 DEBUGOUT("Forcing speed and duplex\n");
1907 ret_val = e1000_phy_force_speed_duplex(hw); 1922 ret_val = e1000_phy_force_speed_duplex(hw);
1908 if(ret_val) { 1923 if (ret_val) {
1909 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1924 DEBUGOUT("Error Forcing Speed and Duplex\n");
1910 return ret_val; 1925 return ret_val;
1911 } 1926 }
@@ -1914,18 +1929,18 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1914 /* Check link status. Wait up to 100 microseconds for link to become 1929 /* Check link status. Wait up to 100 microseconds for link to become
1915 * valid. 1930 * valid.
1916 */ 1931 */
1917 for(i = 0; i < 10; i++) { 1932 for (i = 0; i < 10; i++) {
1918 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1933 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1919 if(ret_val) 1934 if (ret_val)
1920 return ret_val; 1935 return ret_val;
1921 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1936 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1922 if(ret_val) 1937 if (ret_val)
1923 return ret_val; 1938 return ret_val;
1924 1939
1925 if(phy_data & MII_SR_LINK_STATUS) { 1940 if (phy_data & MII_SR_LINK_STATUS) {
1926 /* Config the MAC and PHY after link is up */ 1941 /* Config the MAC and PHY after link is up */
1927 ret_val = e1000_copper_link_postconfig(hw); 1942 ret_val = e1000_copper_link_postconfig(hw);
1928 if(ret_val) 1943 if (ret_val)
1929 return ret_val; 1944 return ret_val;
1930 1945
1931 DEBUGOUT("Valid link established!!!\n"); 1946 DEBUGOUT("Valid link established!!!\n");
@@ -2027,7 +2042,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2027 2042
2028 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2043 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2029 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2044 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2030 if(ret_val) 2045 if (ret_val)
2031 return ret_val; 2046 return ret_val;
2032 2047
2033 if (hw->phy_type != e1000_phy_ife) { 2048 if (hw->phy_type != e1000_phy_ife) {
@@ -2055,36 +2070,36 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2055 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2070 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2056 2071
2057 /* Do we want to advertise 10 Mb Half Duplex? */ 2072 /* Do we want to advertise 10 Mb Half Duplex? */
2058 if(hw->autoneg_advertised & ADVERTISE_10_HALF) { 2073 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2059 DEBUGOUT("Advertise 10mb Half duplex\n"); 2074 DEBUGOUT("Advertise 10mb Half duplex\n");
2060 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2075 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2061 } 2076 }
2062 2077
2063 /* Do we want to advertise 10 Mb Full Duplex? */ 2078 /* Do we want to advertise 10 Mb Full Duplex? */
2064 if(hw->autoneg_advertised & ADVERTISE_10_FULL) { 2079 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2065 DEBUGOUT("Advertise 10mb Full duplex\n"); 2080 DEBUGOUT("Advertise 10mb Full duplex\n");
2066 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2081 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2067 } 2082 }
2068 2083
2069 /* Do we want to advertise 100 Mb Half Duplex? */ 2084 /* Do we want to advertise 100 Mb Half Duplex? */
2070 if(hw->autoneg_advertised & ADVERTISE_100_HALF) { 2085 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2071 DEBUGOUT("Advertise 100mb Half duplex\n"); 2086 DEBUGOUT("Advertise 100mb Half duplex\n");
2072 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2087 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2073 } 2088 }
2074 2089
2075 /* Do we want to advertise 100 Mb Full Duplex? */ 2090 /* Do we want to advertise 100 Mb Full Duplex? */
2076 if(hw->autoneg_advertised & ADVERTISE_100_FULL) { 2091 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2077 DEBUGOUT("Advertise 100mb Full duplex\n"); 2092 DEBUGOUT("Advertise 100mb Full duplex\n");
2078 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2093 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2079 } 2094 }
2080 2095
2081 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2096 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2082 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2097 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2083 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 2098 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2084 } 2099 }
2085 2100
2086 /* Do we want to advertise 1000 Mb Full Duplex? */ 2101 /* Do we want to advertise 1000 Mb Full Duplex? */
2087 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2102 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2088 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2103 DEBUGOUT("Advertise 1000mb Full duplex\n");
2089 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2104 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2090 if (hw->phy_type == e1000_phy_ife) { 2105 if (hw->phy_type == e1000_phy_ife) {
@@ -2146,7 +2161,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2146 } 2161 }
2147 2162
2148 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2163 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2149 if(ret_val) 2164 if (ret_val)
2150 return ret_val; 2165 return ret_val;
2151 2166
2152 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2167 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
@@ -2194,7 +2209,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2194 2209
2195 /* Read the MII Control Register. */ 2210 /* Read the MII Control Register. */
2196 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2211 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2197 if(ret_val) 2212 if (ret_val)
2198 return ret_val; 2213 return ret_val;
2199 2214
2200 /* We need to disable autoneg in order to force link and duplex. */ 2215 /* We need to disable autoneg in order to force link and duplex. */
@@ -2202,8 +2217,8 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2202 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2217 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2203 2218
2204 /* Are we forcing Full or Half Duplex? */ 2219 /* Are we forcing Full or Half Duplex? */
2205 if(hw->forced_speed_duplex == e1000_100_full || 2220 if (hw->forced_speed_duplex == e1000_100_full ||
2206 hw->forced_speed_duplex == e1000_10_full) { 2221 hw->forced_speed_duplex == e1000_10_full) {
2207 /* We want to force full duplex so we SET the full duplex bits in the 2222 /* We want to force full duplex so we SET the full duplex bits in the
2208 * Device and MII Control Registers. 2223 * Device and MII Control Registers.
2209 */ 2224 */
@@ -2220,7 +2235,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2220 } 2235 }
2221 2236
2222 /* Are we forcing 100Mbps??? */ 2237 /* Are we forcing 100Mbps??? */
2223 if(hw->forced_speed_duplex == e1000_100_full || 2238 if (hw->forced_speed_duplex == e1000_100_full ||
2224 hw->forced_speed_duplex == e1000_100_half) { 2239 hw->forced_speed_duplex == e1000_100_half) {
2225 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 2240 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2226 ctrl |= E1000_CTRL_SPD_100; 2241 ctrl |= E1000_CTRL_SPD_100;
@@ -2243,7 +2258,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2243 if ((hw->phy_type == e1000_phy_m88) || 2258 if ((hw->phy_type == e1000_phy_m88) ||
2244 (hw->phy_type == e1000_phy_gg82563)) { 2259 (hw->phy_type == e1000_phy_gg82563)) {
2245 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2260 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2246 if(ret_val) 2261 if (ret_val)
2247 return ret_val; 2262 return ret_val;
2248 2263
2249 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 2264 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
@@ -2251,7 +2266,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2251 */ 2266 */
2252 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2267 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2253 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2268 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2254 if(ret_val) 2269 if (ret_val)
2255 return ret_val; 2270 return ret_val;
2256 2271
2257 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 2272 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
@@ -2275,20 +2290,20 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2275 * forced whenever speed or duplex are forced. 2290 * forced whenever speed or duplex are forced.
2276 */ 2291 */
2277 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2292 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2278 if(ret_val) 2293 if (ret_val)
2279 return ret_val; 2294 return ret_val;
2280 2295
2281 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2296 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2282 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2297 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2283 2298
2284 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2299 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2285 if(ret_val) 2300 if (ret_val)
2286 return ret_val; 2301 return ret_val;
2287 } 2302 }
2288 2303
2289 /* Write back the modified PHY MII control register. */ 2304 /* Write back the modified PHY MII control register. */
2290 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 2305 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2291 if(ret_val) 2306 if (ret_val)
2292 return ret_val; 2307 return ret_val;
2293 2308
2294 udelay(1); 2309 udelay(1);
@@ -2300,50 +2315,50 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2300 * only if the user has set wait_autoneg_complete to 1, which is 2315 * only if the user has set wait_autoneg_complete to 1, which is
2301 * the default. 2316 * the default.
2302 */ 2317 */
2303 if(hw->wait_autoneg_complete) { 2318 if (hw->wait_autoneg_complete) {
2304 /* We will wait for autoneg to complete. */ 2319 /* We will wait for autoneg to complete. */
2305 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 2320 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2306 mii_status_reg = 0; 2321 mii_status_reg = 0;
2307 2322
2308 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2323 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2309 for(i = PHY_FORCE_TIME; i > 0; i--) { 2324 for (i = PHY_FORCE_TIME; i > 0; i--) {
2310 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2325 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2311 * to be set. 2326 * to be set.
2312 */ 2327 */
2313 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2328 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2314 if(ret_val) 2329 if (ret_val)
2315 return ret_val; 2330 return ret_val;
2316 2331
2317 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2332 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2318 if(ret_val) 2333 if (ret_val)
2319 return ret_val; 2334 return ret_val;
2320 2335
2321 if(mii_status_reg & MII_SR_LINK_STATUS) break; 2336 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2322 msec_delay(100); 2337 msec_delay(100);
2323 } 2338 }
2324 if((i == 0) && 2339 if ((i == 0) &&
2325 ((hw->phy_type == e1000_phy_m88) || 2340 ((hw->phy_type == e1000_phy_m88) ||
2326 (hw->phy_type == e1000_phy_gg82563))) { 2341 (hw->phy_type == e1000_phy_gg82563))) {
2327 /* We didn't get link. Reset the DSP and wait again for link. */ 2342 /* We didn't get link. Reset the DSP and wait again for link. */
2328 ret_val = e1000_phy_reset_dsp(hw); 2343 ret_val = e1000_phy_reset_dsp(hw);
2329 if(ret_val) { 2344 if (ret_val) {
2330 DEBUGOUT("Error Resetting PHY DSP\n"); 2345 DEBUGOUT("Error Resetting PHY DSP\n");
2331 return ret_val; 2346 return ret_val;
2332 } 2347 }
2333 } 2348 }
2334 /* This loop will early-out if the link condition has been met. */ 2349 /* This loop will early-out if the link condition has been met. */
2335 for(i = PHY_FORCE_TIME; i > 0; i--) { 2350 for (i = PHY_FORCE_TIME; i > 0; i--) {
2336 if(mii_status_reg & MII_SR_LINK_STATUS) break; 2351 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2337 msec_delay(100); 2352 msec_delay(100);
2338 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2353 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2339 * to be set. 2354 * to be set.
2340 */ 2355 */
2341 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2356 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2342 if(ret_val) 2357 if (ret_val)
2343 return ret_val; 2358 return ret_val;
2344 2359
2345 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2360 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2346 if(ret_val) 2361 if (ret_val)
2347 return ret_val; 2362 return ret_val;
2348 } 2363 }
2349 } 2364 }
@@ -2354,32 +2369,31 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2354 * defaults back to a 2.5MHz clock when the PHY is reset. 2369 * defaults back to a 2.5MHz clock when the PHY is reset.
2355 */ 2370 */
2356 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2371 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2357 if(ret_val) 2372 if (ret_val)
2358 return ret_val; 2373 return ret_val;
2359 2374
2360 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2375 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2361 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2376 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2362 if(ret_val) 2377 if (ret_val)
2363 return ret_val; 2378 return ret_val;
2364 2379
2365 /* In addition, because of the s/w reset above, we need to enable CRS on 2380 /* In addition, because of the s/w reset above, we need to enable CRS on
2366 * TX. This must be set for both full and half duplex operation. 2381 * TX. This must be set for both full and half duplex operation.
2367 */ 2382 */
2368 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2383 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2369 if(ret_val) 2384 if (ret_val)
2370 return ret_val; 2385 return ret_val;
2371 2386
2372 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2387 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2373 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2388 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2374 if(ret_val) 2389 if (ret_val)
2375 return ret_val; 2390 return ret_val;
2376 2391
2377 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2392 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2378 (!hw->autoneg) && 2393 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2379 (hw->forced_speed_duplex == e1000_10_full || 2394 hw->forced_speed_duplex == e1000_10_half)) {
2380 hw->forced_speed_duplex == e1000_10_half)) {
2381 ret_val = e1000_polarity_reversal_workaround(hw); 2395 ret_val = e1000_polarity_reversal_workaround(hw);
2382 if(ret_val) 2396 if (ret_val)
2383 return ret_val; 2397 return ret_val;
2384 } 2398 }
2385 } else if (hw->phy_type == e1000_phy_gg82563) { 2399 } else if (hw->phy_type == e1000_phy_gg82563) {
@@ -2470,10 +2484,10 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2470 * registers depending on negotiated values. 2484 * registers depending on negotiated values.
2471 */ 2485 */
2472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2473 if(ret_val) 2487 if (ret_val)
2474 return ret_val; 2488 return ret_val;
2475 2489
2476 if(phy_data & M88E1000_PSSR_DPLX) 2490 if (phy_data & M88E1000_PSSR_DPLX)
2477 ctrl |= E1000_CTRL_FD; 2491 ctrl |= E1000_CTRL_FD;
2478 else 2492 else
2479 ctrl &= ~E1000_CTRL_FD; 2493 ctrl &= ~E1000_CTRL_FD;
@@ -2483,9 +2497,9 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2483 /* Set up speed in the Device Control register depending on 2497 /* Set up speed in the Device Control register depending on
2484 * negotiated values. 2498 * negotiated values.
2485 */ 2499 */
2486 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 2500 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2487 ctrl |= E1000_CTRL_SPD_1000; 2501 ctrl |= E1000_CTRL_SPD_1000;
2488 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 2502 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2489 ctrl |= E1000_CTRL_SPD_100; 2503 ctrl |= E1000_CTRL_SPD_100;
2490 2504
2491 /* Write the configured values back to the Device Control Reg. */ 2505 /* Write the configured values back to the Device Control Reg. */
@@ -2553,7 +2567,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2553 } 2567 }
2554 2568
2555 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2569 /* Disable TX Flow Control for 82542 (rev 2.0) */
2556 if(hw->mac_type == e1000_82542_rev2_0) 2570 if (hw->mac_type == e1000_82542_rev2_0)
2557 ctrl &= (~E1000_CTRL_TFCE); 2571 ctrl &= (~E1000_CTRL_TFCE);
2558 2572
2559 E1000_WRITE_REG(hw, CTRL, ctrl); 2573 E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -2587,11 +2601,12 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2587 * so we had to force link. In this case, we need to force the 2601 * so we had to force link. In this case, we need to force the
2588 * configuration of the MAC to match the "fc" parameter. 2602 * configuration of the MAC to match the "fc" parameter.
2589 */ 2603 */
2590 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || 2604 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2591 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || 2605 ((hw->media_type == e1000_media_type_internal_serdes) &&
2592 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { 2606 (hw->autoneg_failed)) ||
2607 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2593 ret_val = e1000_force_mac_fc(hw); 2608 ret_val = e1000_force_mac_fc(hw);
2594 if(ret_val) { 2609 if (ret_val) {
2595 DEBUGOUT("Error forcing flow control settings\n"); 2610 DEBUGOUT("Error forcing flow control settings\n");
2596 return ret_val; 2611 return ret_val;
2597 } 2612 }
@@ -2602,19 +2617,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2602 * has completed, and if so, how the PHY and link partner has 2617 * has completed, and if so, how the PHY and link partner has
2603 * flow control configured. 2618 * flow control configured.
2604 */ 2619 */
2605 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2620 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2606 /* Read the MII Status Register and check to see if AutoNeg 2621 /* Read the MII Status Register and check to see if AutoNeg
2607 * has completed. We read this twice because this reg has 2622 * has completed. We read this twice because this reg has
2608 * some "sticky" (latched) bits. 2623 * some "sticky" (latched) bits.
2609 */ 2624 */
2610 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2625 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2611 if(ret_val) 2626 if (ret_val)
2612 return ret_val; 2627 return ret_val;
2613 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2628 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2614 if(ret_val) 2629 if (ret_val)
2615 return ret_val; 2630 return ret_val;
2616 2631
2617 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2632 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2618 /* The AutoNeg process has completed, so we now need to 2633 /* The AutoNeg process has completed, so we now need to
2619 * read both the Auto Negotiation Advertisement Register 2634 * read both the Auto Negotiation Advertisement Register
2620 * (Address 4) and the Auto_Negotiation Base Page Ability 2635 * (Address 4) and the Auto_Negotiation Base Page Ability
@@ -2623,11 +2638,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2623 */ 2638 */
2624 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2639 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2625 &mii_nway_adv_reg); 2640 &mii_nway_adv_reg);
2626 if(ret_val) 2641 if (ret_val)
2627 return ret_val; 2642 return ret_val;
2628 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2643 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2629 &mii_nway_lp_ability_reg); 2644 &mii_nway_lp_ability_reg);
2630 if(ret_val) 2645 if (ret_val)
2631 return ret_val; 2646 return ret_val;
2632 2647
2633 /* Two bits in the Auto Negotiation Advertisement Register 2648 /* Two bits in the Auto Negotiation Advertisement Register
@@ -2664,15 +2679,15 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2664 * 1 | DC | 1 | DC | e1000_fc_full 2679 * 1 | DC | 1 | DC | e1000_fc_full
2665 * 2680 *
2666 */ 2681 */
2667 if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2682 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2668 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2683 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2669 /* Now we need to check if the user selected RX ONLY 2684 /* Now we need to check if the user selected RX ONLY
2670 * of pause frames. In this case, we had to advertise 2685 * of pause frames. In this case, we had to advertise
2671 * FULL flow control because we could not advertise RX 2686 * FULL flow control because we could not advertise RX
2672 * ONLY. Hence, we must now check to see if we need to 2687 * ONLY. Hence, we must now check to see if we need to
2673 * turn OFF the TRANSMISSION of PAUSE frames. 2688 * turn OFF the TRANSMISSION of PAUSE frames.
2674 */ 2689 */
2675 if(hw->original_fc == e1000_fc_full) { 2690 if (hw->original_fc == e1000_fc_full) {
2676 hw->fc = e1000_fc_full; 2691 hw->fc = e1000_fc_full;
2677 DEBUGOUT("Flow Control = FULL.\n"); 2692 DEBUGOUT("Flow Control = FULL.\n");
2678 } else { 2693 } else {
@@ -2688,10 +2703,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2688 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 2703 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2689 * 2704 *
2690 */ 2705 */
2691 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2706 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2692 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2693 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2708 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2694 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2695 hw->fc = e1000_fc_tx_pause; 2710 hw->fc = e1000_fc_tx_pause;
2696 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2711 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2697 } 2712 }
@@ -2703,10 +2718,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2703 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 2718 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2704 * 2719 *
2705 */ 2720 */
2706 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2721 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2722 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2708 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2723 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2724 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2710 hw->fc = e1000_fc_rx_pause; 2725 hw->fc = e1000_fc_rx_pause;
2711 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2726 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2712 } 2727 }
@@ -2730,9 +2745,9 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2730 * be asked to delay transmission of packets than asking 2745 * be asked to delay transmission of packets than asking
2731 * our link partner to pause transmission of frames. 2746 * our link partner to pause transmission of frames.
2732 */ 2747 */
2733 else if((hw->original_fc == e1000_fc_none || 2748 else if ((hw->original_fc == e1000_fc_none ||
2734 hw->original_fc == e1000_fc_tx_pause) || 2749 hw->original_fc == e1000_fc_tx_pause) ||
2735 hw->fc_strict_ieee) { 2750 hw->fc_strict_ieee) {
2736 hw->fc = e1000_fc_none; 2751 hw->fc = e1000_fc_none;
2737 DEBUGOUT("Flow Control = NONE.\n"); 2752 DEBUGOUT("Flow Control = NONE.\n");
2738 } else { 2753 } else {
@@ -2745,19 +2760,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2745 * enabled per IEEE 802.3 spec. 2760 * enabled per IEEE 802.3 spec.
2746 */ 2761 */
2747 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2762 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2748 if(ret_val) { 2763 if (ret_val) {
2749 DEBUGOUT("Error getting link speed and duplex\n"); 2764 DEBUGOUT("Error getting link speed and duplex\n");
2750 return ret_val; 2765 return ret_val;
2751 } 2766 }
2752 2767
2753 if(duplex == HALF_DUPLEX) 2768 if (duplex == HALF_DUPLEX)
2754 hw->fc = e1000_fc_none; 2769 hw->fc = e1000_fc_none;
2755 2770
2756 /* Now we call a subroutine to actually force the MAC 2771 /* Now we call a subroutine to actually force the MAC
2757 * controller to use the correct flow control settings. 2772 * controller to use the correct flow control settings.
2758 */ 2773 */
2759 ret_val = e1000_force_mac_fc(hw); 2774 ret_val = e1000_force_mac_fc(hw);
2760 if(ret_val) { 2775 if (ret_val) {
2761 DEBUGOUT("Error forcing flow control settings\n"); 2776 DEBUGOUT("Error forcing flow control settings\n");
2762 return ret_val; 2777 return ret_val;
2763 } 2778 }
@@ -2796,13 +2811,13 @@ e1000_check_for_link(struct e1000_hw *hw)
2796 * set when the optics detect a signal. On older adapters, it will be 2811 * set when the optics detect a signal. On older adapters, it will be
2797 * cleared when there is a signal. This applies to fiber media only. 2812 * cleared when there is a signal. This applies to fiber media only.
2798 */ 2813 */
2799 if((hw->media_type == e1000_media_type_fiber) || 2814 if ((hw->media_type == e1000_media_type_fiber) ||
2800 (hw->media_type == e1000_media_type_internal_serdes)) { 2815 (hw->media_type == e1000_media_type_internal_serdes)) {
2801 rxcw = E1000_READ_REG(hw, RXCW); 2816 rxcw = E1000_READ_REG(hw, RXCW);
2802 2817
2803 if(hw->media_type == e1000_media_type_fiber) { 2818 if (hw->media_type == e1000_media_type_fiber) {
2804 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2819 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2805 if(status & E1000_STATUS_LU) 2820 if (status & E1000_STATUS_LU)
2806 hw->get_link_status = FALSE; 2821 hw->get_link_status = FALSE;
2807 } 2822 }
2808 } 2823 }
@@ -2813,20 +2828,20 @@ e1000_check_for_link(struct e1000_hw *hw)
2813 * receive a Link Status Change interrupt or we have Rx Sequence 2828 * receive a Link Status Change interrupt or we have Rx Sequence
2814 * Errors. 2829 * Errors.
2815 */ 2830 */
2816 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2831 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2817 /* First we want to see if the MII Status Register reports 2832 /* First we want to see if the MII Status Register reports
2818 * link. If so, then we want to get the current speed/duplex 2833 * link. If so, then we want to get the current speed/duplex
2819 * of the PHY. 2834 * of the PHY.
2820 * Read the register twice since the link bit is sticky. 2835 * Read the register twice since the link bit is sticky.
2821 */ 2836 */
2822 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2837 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2823 if(ret_val) 2838 if (ret_val)
2824 return ret_val; 2839 return ret_val;
2825 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2826 if(ret_val) 2841 if (ret_val)
2827 return ret_val; 2842 return ret_val;
2828 2843
2829 if(phy_data & MII_SR_LINK_STATUS) { 2844 if (phy_data & MII_SR_LINK_STATUS) {
2830 hw->get_link_status = FALSE; 2845 hw->get_link_status = FALSE;
2831 /* Check if there was DownShift, must be checked immediately after 2846 /* Check if there was DownShift, must be checked immediately after
2832 * link-up */ 2847 * link-up */
@@ -2840,10 +2855,10 @@ e1000_check_for_link(struct e1000_hw *hw)
2840 * happen due to the execution of this workaround. 2855 * happen due to the execution of this workaround.
2841 */ 2856 */
2842 2857
2843 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2858 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2844 (!hw->autoneg) && 2859 (!hw->autoneg) &&
2845 (hw->forced_speed_duplex == e1000_10_full || 2860 (hw->forced_speed_duplex == e1000_10_full ||
2846 hw->forced_speed_duplex == e1000_10_half)) { 2861 hw->forced_speed_duplex == e1000_10_half)) {
2847 E1000_WRITE_REG(hw, IMC, 0xffffffff); 2862 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2848 ret_val = e1000_polarity_reversal_workaround(hw); 2863 ret_val = e1000_polarity_reversal_workaround(hw);
2849 icr = E1000_READ_REG(hw, ICR); 2864 icr = E1000_READ_REG(hw, ICR);
@@ -2860,7 +2875,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2860 /* If we are forcing speed/duplex, then we simply return since 2875 /* If we are forcing speed/duplex, then we simply return since
2861 * we have already determined whether we have link or not. 2876 * we have already determined whether we have link or not.
2862 */ 2877 */
2863 if(!hw->autoneg) return -E1000_ERR_CONFIG; 2878 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2864 2879
2865 /* optimize the dsp settings for the igp phy */ 2880 /* optimize the dsp settings for the igp phy */
2866 e1000_config_dsp_after_link_change(hw, TRUE); 2881 e1000_config_dsp_after_link_change(hw, TRUE);
@@ -2873,11 +2888,11 @@ e1000_check_for_link(struct e1000_hw *hw)
2873 * speed/duplex on the MAC to the current PHY speed/duplex 2888 * speed/duplex on the MAC to the current PHY speed/duplex
2874 * settings. 2889 * settings.
2875 */ 2890 */
2876 if(hw->mac_type >= e1000_82544) 2891 if (hw->mac_type >= e1000_82544)
2877 e1000_config_collision_dist(hw); 2892 e1000_config_collision_dist(hw);
2878 else { 2893 else {
2879 ret_val = e1000_config_mac_to_phy(hw); 2894 ret_val = e1000_config_mac_to_phy(hw);
2880 if(ret_val) { 2895 if (ret_val) {
2881 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2896 DEBUGOUT("Error configuring MAC to PHY settings\n");
2882 return ret_val; 2897 return ret_val;
2883 } 2898 }
@@ -2888,7 +2903,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2888 * have had to re-autoneg with a different link partner. 2903 * have had to re-autoneg with a different link partner.
2889 */ 2904 */
2890 ret_val = e1000_config_fc_after_link_up(hw); 2905 ret_val = e1000_config_fc_after_link_up(hw);
2891 if(ret_val) { 2906 if (ret_val) {
2892 DEBUGOUT("Error configuring flow control\n"); 2907 DEBUGOUT("Error configuring flow control\n");
2893 return ret_val; 2908 return ret_val;
2894 } 2909 }
@@ -2900,7 +2915,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2900 * at gigabit speed, then TBI compatibility is not needed. If we are 2915 * at gigabit speed, then TBI compatibility is not needed. If we are
2901 * at gigabit speed, we turn on TBI compatibility. 2916 * at gigabit speed, we turn on TBI compatibility.
2902 */ 2917 */
2903 if(hw->tbi_compatibility_en) { 2918 if (hw->tbi_compatibility_en) {
2904 uint16_t speed, duplex; 2919 uint16_t speed, duplex;
2905 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2920 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2906 if (ret_val) { 2921 if (ret_val) {
@@ -2911,7 +2926,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2911 /* If link speed is not set to gigabit speed, we do not need 2926 /* If link speed is not set to gigabit speed, we do not need
2912 * to enable TBI compatibility. 2927 * to enable TBI compatibility.
2913 */ 2928 */
2914 if(hw->tbi_compatibility_on) { 2929 if (hw->tbi_compatibility_on) {
2915 /* If we previously were in the mode, turn it off. */ 2930 /* If we previously were in the mode, turn it off. */
2916 rctl = E1000_READ_REG(hw, RCTL); 2931 rctl = E1000_READ_REG(hw, RCTL);
2917 rctl &= ~E1000_RCTL_SBP; 2932 rctl &= ~E1000_RCTL_SBP;
@@ -2924,7 +2939,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2924 * packets. Some frames have an additional byte on the end and 2939 * packets. Some frames have an additional byte on the end and
2925 * will look like CRC errors to to the hardware. 2940 * will look like CRC errors to to the hardware.
2926 */ 2941 */
2927 if(!hw->tbi_compatibility_on) { 2942 if (!hw->tbi_compatibility_on) {
2928 hw->tbi_compatibility_on = TRUE; 2943 hw->tbi_compatibility_on = TRUE;
2929 rctl = E1000_READ_REG(hw, RCTL); 2944 rctl = E1000_READ_REG(hw, RCTL);
2930 rctl |= E1000_RCTL_SBP; 2945 rctl |= E1000_RCTL_SBP;
@@ -2940,12 +2955,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2940 * auto-negotiation time to complete, in case the cable was just plugged 2955 * auto-negotiation time to complete, in case the cable was just plugged
2941 * in. The autoneg_failed flag does this. 2956 * in. The autoneg_failed flag does this.
2942 */ 2957 */
2943 else if((((hw->media_type == e1000_media_type_fiber) && 2958 else if ((((hw->media_type == e1000_media_type_fiber) &&
2944 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 2959 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2945 (hw->media_type == e1000_media_type_internal_serdes)) && 2960 (hw->media_type == e1000_media_type_internal_serdes)) &&
2946 (!(status & E1000_STATUS_LU)) && 2961 (!(status & E1000_STATUS_LU)) &&
2947 (!(rxcw & E1000_RXCW_C))) { 2962 (!(rxcw & E1000_RXCW_C))) {
2948 if(hw->autoneg_failed == 0) { 2963 if (hw->autoneg_failed == 0) {
2949 hw->autoneg_failed = 1; 2964 hw->autoneg_failed = 1;
2950 return 0; 2965 return 0;
2951 } 2966 }
@@ -2961,7 +2976,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2961 2976
2962 /* Configure Flow Control after forcing link up. */ 2977 /* Configure Flow Control after forcing link up. */
2963 ret_val = e1000_config_fc_after_link_up(hw); 2978 ret_val = e1000_config_fc_after_link_up(hw);
2964 if(ret_val) { 2979 if (ret_val) {
2965 DEBUGOUT("Error configuring flow control\n"); 2980 DEBUGOUT("Error configuring flow control\n");
2966 return ret_val; 2981 return ret_val;
2967 } 2982 }
@@ -2971,9 +2986,9 @@ e1000_check_for_link(struct e1000_hw *hw)
2971 * Device Control register in an attempt to auto-negotiate with our link 2986 * Device Control register in an attempt to auto-negotiate with our link
2972 * partner. 2987 * partner.
2973 */ 2988 */
2974 else if(((hw->media_type == e1000_media_type_fiber) || 2989 else if (((hw->media_type == e1000_media_type_fiber) ||
2975 (hw->media_type == e1000_media_type_internal_serdes)) && 2990 (hw->media_type == e1000_media_type_internal_serdes)) &&
2976 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2991 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2977 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2992 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2978 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2993 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2979 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2994 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
@@ -2983,12 +2998,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2983 /* If we force link for non-auto-negotiation switch, check link status 2998 /* If we force link for non-auto-negotiation switch, check link status
2984 * based on MAC synchronization for internal serdes media type. 2999 * based on MAC synchronization for internal serdes media type.
2985 */ 3000 */
2986 else if((hw->media_type == e1000_media_type_internal_serdes) && 3001 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
2987 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3002 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2988 /* SYNCH bit and IV bit are sticky. */ 3003 /* SYNCH bit and IV bit are sticky. */
2989 udelay(10); 3004 udelay(10);
2990 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3005 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2991 if(!(rxcw & E1000_RXCW_IV)) { 3006 if (!(rxcw & E1000_RXCW_IV)) {
2992 hw->serdes_link_down = FALSE; 3007 hw->serdes_link_down = FALSE;
2993 DEBUGOUT("SERDES: Link is up.\n"); 3008 DEBUGOUT("SERDES: Link is up.\n");
2994 } 3009 }
@@ -2997,8 +3012,8 @@ e1000_check_for_link(struct e1000_hw *hw)
2997 DEBUGOUT("SERDES: Link is down.\n"); 3012 DEBUGOUT("SERDES: Link is down.\n");
2998 } 3013 }
2999 } 3014 }
3000 if((hw->media_type == e1000_media_type_internal_serdes) && 3015 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3001 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3016 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3002 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); 3017 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3003 } 3018 }
3004 return E1000_SUCCESS; 3019 return E1000_SUCCESS;
@@ -3022,12 +3037,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3022 3037
3023 DEBUGFUNC("e1000_get_speed_and_duplex"); 3038 DEBUGFUNC("e1000_get_speed_and_duplex");
3024 3039
3025 if(hw->mac_type >= e1000_82543) { 3040 if (hw->mac_type >= e1000_82543) {
3026 status = E1000_READ_REG(hw, STATUS); 3041 status = E1000_READ_REG(hw, STATUS);
3027 if(status & E1000_STATUS_SPEED_1000) { 3042 if (status & E1000_STATUS_SPEED_1000) {
3028 *speed = SPEED_1000; 3043 *speed = SPEED_1000;
3029 DEBUGOUT("1000 Mbs, "); 3044 DEBUGOUT("1000 Mbs, ");
3030 } else if(status & E1000_STATUS_SPEED_100) { 3045 } else if (status & E1000_STATUS_SPEED_100) {
3031 *speed = SPEED_100; 3046 *speed = SPEED_100;
3032 DEBUGOUT("100 Mbs, "); 3047 DEBUGOUT("100 Mbs, ");
3033 } else { 3048 } else {
@@ -3035,7 +3050,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3035 DEBUGOUT("10 Mbs, "); 3050 DEBUGOUT("10 Mbs, ");
3036 } 3051 }
3037 3052
3038 if(status & E1000_STATUS_FD) { 3053 if (status & E1000_STATUS_FD) {
3039 *duplex = FULL_DUPLEX; 3054 *duplex = FULL_DUPLEX;
3040 DEBUGOUT("Full Duplex\n"); 3055 DEBUGOUT("Full Duplex\n");
3041 } else { 3056 } else {
@@ -3052,18 +3067,18 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3052 * if it is operating at half duplex. Here we set the duplex settings to 3067 * if it is operating at half duplex. Here we set the duplex settings to
3053 * match the duplex in the link partner's capabilities. 3068 * match the duplex in the link partner's capabilities.
3054 */ 3069 */
3055 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3070 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3056 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3071 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3057 if(ret_val) 3072 if (ret_val)
3058 return ret_val; 3073 return ret_val;
3059 3074
3060 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3075 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3061 *duplex = HALF_DUPLEX; 3076 *duplex = HALF_DUPLEX;
3062 else { 3077 else {
3063 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 3078 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3064 if(ret_val) 3079 if (ret_val)
3065 return ret_val; 3080 return ret_val;
3066 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 3081 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3067 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3082 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3068 *duplex = HALF_DUPLEX; 3083 *duplex = HALF_DUPLEX;
3069 } 3084 }
@@ -3104,17 +3119,17 @@ e1000_wait_autoneg(struct e1000_hw *hw)
3104 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3119 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3105 3120
3106 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3121 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3107 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3122 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3108 /* Read the MII Status Register and wait for Auto-Neg 3123 /* Read the MII Status Register and wait for Auto-Neg
3109 * Complete bit to be set. 3124 * Complete bit to be set.
3110 */ 3125 */
3111 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3126 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3112 if(ret_val) 3127 if (ret_val)
3113 return ret_val; 3128 return ret_val;
3114 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3115 if(ret_val) 3130 if (ret_val)
3116 return ret_val; 3131 return ret_val;
3117 if(phy_data & MII_SR_AUTONEG_COMPLETE) { 3132 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3118 return E1000_SUCCESS; 3133 return E1000_SUCCESS;
3119 } 3134 }
3120 msec_delay(100); 3135 msec_delay(100);
@@ -3187,14 +3202,16 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3187 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3202 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3188 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3203 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3189 3204
3190 while(mask) { 3205 while (mask) {
3191 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3206 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3192 * then raising and lowering the Management Data Clock. A "0" is 3207 * then raising and lowering the Management Data Clock. A "0" is
3193 * shifted out to the PHY by setting the MDIO bit to "0" and then 3208 * shifted out to the PHY by setting the MDIO bit to "0" and then
3194 * raising and lowering the clock. 3209 * raising and lowering the clock.
3195 */ 3210 */
3196 if(data & mask) ctrl |= E1000_CTRL_MDIO; 3211 if (data & mask)
3197 else ctrl &= ~E1000_CTRL_MDIO; 3212 ctrl |= E1000_CTRL_MDIO;
3213 else
3214 ctrl &= ~E1000_CTRL_MDIO;
3198 3215
3199 E1000_WRITE_REG(hw, CTRL, ctrl); 3216 E1000_WRITE_REG(hw, CTRL, ctrl);
3200 E1000_WRITE_FLUSH(hw); 3217 E1000_WRITE_FLUSH(hw);
@@ -3245,12 +3262,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3245 e1000_raise_mdi_clk(hw, &ctrl); 3262 e1000_raise_mdi_clk(hw, &ctrl);
3246 e1000_lower_mdi_clk(hw, &ctrl); 3263 e1000_lower_mdi_clk(hw, &ctrl);
3247 3264
3248 for(data = 0, i = 0; i < 16; i++) { 3265 for (data = 0, i = 0; i < 16; i++) {
3249 data = data << 1; 3266 data = data << 1;
3250 e1000_raise_mdi_clk(hw, &ctrl); 3267 e1000_raise_mdi_clk(hw, &ctrl);
3251 ctrl = E1000_READ_REG(hw, CTRL); 3268 ctrl = E1000_READ_REG(hw, CTRL);
3252 /* Check to see if we shifted in a "1". */ 3269 /* Check to see if we shifted in a "1". */
3253 if(ctrl & E1000_CTRL_MDIO) data |= 1; 3270 if (ctrl & E1000_CTRL_MDIO)
3271 data |= 1;
3254 e1000_lower_mdi_clk(hw, &ctrl); 3272 e1000_lower_mdi_clk(hw, &ctrl);
3255 } 3273 }
3256 3274
@@ -3276,7 +3294,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3276 if (!hw->swfw_sync_present) 3294 if (!hw->swfw_sync_present)
3277 return e1000_get_hw_eeprom_semaphore(hw); 3295 return e1000_get_hw_eeprom_semaphore(hw);
3278 3296
3279 while(timeout) { 3297 while (timeout) {
3280 if (e1000_get_hw_eeprom_semaphore(hw)) 3298 if (e1000_get_hw_eeprom_semaphore(hw))
3281 return -E1000_ERR_SWFW_SYNC; 3299 return -E1000_ERR_SWFW_SYNC;
3282 3300
@@ -3365,7 +3383,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3365 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3383 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3366 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3384 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3367 (uint16_t)reg_addr); 3385 (uint16_t)reg_addr);
3368 if(ret_val) { 3386 if (ret_val) {
3369 e1000_swfw_sync_release(hw, swfw); 3387 e1000_swfw_sync_release(hw, swfw);
3370 return ret_val; 3388 return ret_val;
3371 } 3389 }
@@ -3410,12 +3428,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
3410 3428
3411 DEBUGFUNC("e1000_read_phy_reg_ex"); 3429 DEBUGFUNC("e1000_read_phy_reg_ex");
3412 3430
3413 if(reg_addr > MAX_PHY_REG_ADDRESS) { 3431 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3414 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3432 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3415 return -E1000_ERR_PARAM; 3433 return -E1000_ERR_PARAM;
3416 } 3434 }
3417 3435
3418 if(hw->mac_type > e1000_82543) { 3436 if (hw->mac_type > e1000_82543) {
3419 /* Set up Op-code, Phy Address, and register address in the MDI 3437 /* Set up Op-code, Phy Address, and register address in the MDI
3420 * Control register. The MAC will take care of interfacing with the 3438 * Control register. The MAC will take care of interfacing with the
3421 * PHY to retrieve the desired data. 3439 * PHY to retrieve the desired data.
@@ -3427,16 +3445,16 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
3427 E1000_WRITE_REG(hw, MDIC, mdic); 3445 E1000_WRITE_REG(hw, MDIC, mdic);
3428 3446
3429 /* Poll the ready bit to see if the MDI read completed */ 3447 /* Poll the ready bit to see if the MDI read completed */
3430 for(i = 0; i < 64; i++) { 3448 for (i = 0; i < 64; i++) {
3431 udelay(50); 3449 udelay(50);
3432 mdic = E1000_READ_REG(hw, MDIC); 3450 mdic = E1000_READ_REG(hw, MDIC);
3433 if(mdic & E1000_MDIC_READY) break; 3451 if (mdic & E1000_MDIC_READY) break;
3434 } 3452 }
3435 if(!(mdic & E1000_MDIC_READY)) { 3453 if (!(mdic & E1000_MDIC_READY)) {
3436 DEBUGOUT("MDI Read did not complete\n"); 3454 DEBUGOUT("MDI Read did not complete\n");
3437 return -E1000_ERR_PHY; 3455 return -E1000_ERR_PHY;
3438 } 3456 }
3439 if(mdic & E1000_MDIC_ERROR) { 3457 if (mdic & E1000_MDIC_ERROR) {
3440 DEBUGOUT("MDI Error\n"); 3458 DEBUGOUT("MDI Error\n");
3441 return -E1000_ERR_PHY; 3459 return -E1000_ERR_PHY;
3442 } 3460 }
@@ -3505,7 +3523,7 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3505 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3523 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3506 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3524 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3507 (uint16_t)reg_addr); 3525 (uint16_t)reg_addr);
3508 if(ret_val) { 3526 if (ret_val) {
3509 e1000_swfw_sync_release(hw, swfw); 3527 e1000_swfw_sync_release(hw, swfw);
3510 return ret_val; 3528 return ret_val;
3511 } 3529 }
@@ -3550,12 +3568,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3550 3568
3551 DEBUGFUNC("e1000_write_phy_reg_ex"); 3569 DEBUGFUNC("e1000_write_phy_reg_ex");
3552 3570
3553 if(reg_addr > MAX_PHY_REG_ADDRESS) { 3571 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3554 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3572 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3555 return -E1000_ERR_PARAM; 3573 return -E1000_ERR_PARAM;
3556 } 3574 }
3557 3575
3558 if(hw->mac_type > e1000_82543) { 3576 if (hw->mac_type > e1000_82543) {
3559 /* Set up Op-code, Phy Address, register address, and data intended 3577 /* Set up Op-code, Phy Address, register address, and data intended
3560 * for the PHY register in the MDI Control register. The MAC will take 3578 * for the PHY register in the MDI Control register. The MAC will take
3561 * care of interfacing with the PHY to send the desired data. 3579 * care of interfacing with the PHY to send the desired data.
@@ -3568,12 +3586,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3568 E1000_WRITE_REG(hw, MDIC, mdic); 3586 E1000_WRITE_REG(hw, MDIC, mdic);
3569 3587
3570 /* Poll the ready bit to see if the MDI read completed */ 3588 /* Poll the ready bit to see if the MDI read completed */
3571 for(i = 0; i < 640; i++) { 3589 for (i = 0; i < 641; i++) {
3572 udelay(5); 3590 udelay(5);
3573 mdic = E1000_READ_REG(hw, MDIC); 3591 mdic = E1000_READ_REG(hw, MDIC);
3574 if(mdic & E1000_MDIC_READY) break; 3592 if (mdic & E1000_MDIC_READY) break;
3575 } 3593 }
3576 if(!(mdic & E1000_MDIC_READY)) { 3594 if (!(mdic & E1000_MDIC_READY)) {
3577 DEBUGOUT("MDI Write did not complete\n"); 3595 DEBUGOUT("MDI Write did not complete\n");
3578 return -E1000_ERR_PHY; 3596 return -E1000_ERR_PHY;
3579 } 3597 }
@@ -3685,7 +3703,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3685 3703
3686 DEBUGOUT("Resetting Phy...\n"); 3704 DEBUGOUT("Resetting Phy...\n");
3687 3705
3688 if(hw->mac_type > e1000_82543) { 3706 if (hw->mac_type > e1000_82543) {
3689 if ((hw->mac_type == e1000_80003es2lan) && 3707 if ((hw->mac_type == e1000_80003es2lan) &&
3690 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3708 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3691 swfw = E1000_SWFW_PHY1_SM; 3709 swfw = E1000_SWFW_PHY1_SM;
@@ -3733,7 +3751,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3733 } 3751 }
3734 udelay(150); 3752 udelay(150);
3735 3753
3736 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3754 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3737 /* Configure activity LED after PHY reset */ 3755 /* Configure activity LED after PHY reset */
3738 led_ctrl = E1000_READ_REG(hw, LEDCTL); 3756 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3739 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3757 led_ctrl &= IGP_ACTIVITY_LED_MASK;
@@ -3743,14 +3761,13 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3743 3761
3744 /* Wait for FW to finish PHY configuration. */ 3762 /* Wait for FW to finish PHY configuration. */
3745 ret_val = e1000_get_phy_cfg_done(hw); 3763 ret_val = e1000_get_phy_cfg_done(hw);
3764 if (ret_val != E1000_SUCCESS)
3765 return ret_val;
3746 e1000_release_software_semaphore(hw); 3766 e1000_release_software_semaphore(hw);
3747 3767
3748 if ((hw->mac_type == e1000_ich8lan) && 3768 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3749 (hw->phy_type == e1000_phy_igp_3)) { 3769 ret_val = e1000_init_lcd_from_nvm(hw);
3750 ret_val = e1000_init_lcd_from_nvm(hw); 3770
3751 if (ret_val)
3752 return ret_val;
3753 }
3754 return ret_val; 3771 return ret_val;
3755} 3772}
3756 3773
@@ -3781,25 +3798,25 @@ e1000_phy_reset(struct e1000_hw *hw)
3781 case e1000_82572: 3798 case e1000_82572:
3782 case e1000_ich8lan: 3799 case e1000_ich8lan:
3783 ret_val = e1000_phy_hw_reset(hw); 3800 ret_val = e1000_phy_hw_reset(hw);
3784 if(ret_val) 3801 if (ret_val)
3785 return ret_val; 3802 return ret_val;
3786 3803
3787 break; 3804 break;
3788 default: 3805 default:
3789 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3806 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3790 if(ret_val) 3807 if (ret_val)
3791 return ret_val; 3808 return ret_val;
3792 3809
3793 phy_data |= MII_CR_RESET; 3810 phy_data |= MII_CR_RESET;
3794 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3811 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3795 if(ret_val) 3812 if (ret_val)
3796 return ret_val; 3813 return ret_val;
3797 3814
3798 udelay(1); 3815 udelay(1);
3799 break; 3816 break;
3800 } 3817 }
3801 3818
3802 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 3819 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3803 e1000_phy_init_script(hw); 3820 e1000_phy_init_script(hw);
3804 3821
3805 return E1000_SUCCESS; 3822 return E1000_SUCCESS;
@@ -3877,8 +3894,8 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3877 if (hw->kmrn_lock_loss_workaround_disabled) 3894 if (hw->kmrn_lock_loss_workaround_disabled)
3878 return E1000_SUCCESS; 3895 return E1000_SUCCESS;
3879 3896
3880 /* Make sure link is up before proceeding. If not just return. 3897 /* Make sure link is up before proceeding. If not just return.
3881 * Attempting this while link is negotiating fouls up link 3898 * Attempting this while link is negotiating fouled up link
3882 * stability */ 3899 * stability */
3883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3884 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3901 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
@@ -3955,34 +3972,34 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3955 hw->phy_id = (uint32_t) (phy_id_high << 16); 3972 hw->phy_id = (uint32_t) (phy_id_high << 16);
3956 udelay(20); 3973 udelay(20);
3957 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3974 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3958 if(ret_val) 3975 if (ret_val)
3959 return ret_val; 3976 return ret_val;
3960 3977
3961 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 3978 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3962 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 3979 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3963 3980
3964 switch(hw->mac_type) { 3981 switch (hw->mac_type) {
3965 case e1000_82543: 3982 case e1000_82543:
3966 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; 3983 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3967 break; 3984 break;
3968 case e1000_82544: 3985 case e1000_82544:
3969 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; 3986 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3970 break; 3987 break;
3971 case e1000_82540: 3988 case e1000_82540:
3972 case e1000_82545: 3989 case e1000_82545:
3973 case e1000_82545_rev_3: 3990 case e1000_82545_rev_3:
3974 case e1000_82546: 3991 case e1000_82546:
3975 case e1000_82546_rev_3: 3992 case e1000_82546_rev_3:
3976 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; 3993 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3977 break; 3994 break;
3978 case e1000_82541: 3995 case e1000_82541:
3979 case e1000_82541_rev_2: 3996 case e1000_82541_rev_2:
3980 case e1000_82547: 3997 case e1000_82547:
3981 case e1000_82547_rev_2: 3998 case e1000_82547_rev_2:
3982 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3999 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3983 break; 4000 break;
3984 case e1000_82573: 4001 case e1000_82573:
3985 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; 4002 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3986 break; 4003 break;
3987 case e1000_80003es2lan: 4004 case e1000_80003es2lan:
3988 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 4005 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
@@ -4021,14 +4038,14 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
4021 do { 4038 do {
4022 if (hw->phy_type != e1000_phy_gg82563) { 4039 if (hw->phy_type != e1000_phy_gg82563) {
4023 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 4040 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4024 if(ret_val) break; 4041 if (ret_val) break;
4025 } 4042 }
4026 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 4043 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4027 if(ret_val) break; 4044 if (ret_val) break;
4028 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 4045 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4029 if(ret_val) break; 4046 if (ret_val) break;
4030 ret_val = E1000_SUCCESS; 4047 ret_val = E1000_SUCCESS;
4031 } while(0); 4048 } while (0);
4032 4049
4033 return ret_val; 4050 return ret_val;
4034} 4051}
@@ -4060,23 +4077,23 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4060 4077
4061 /* Check polarity status */ 4078 /* Check polarity status */
4062 ret_val = e1000_check_polarity(hw, &polarity); 4079 ret_val = e1000_check_polarity(hw, &polarity);
4063 if(ret_val) 4080 if (ret_val)
4064 return ret_val; 4081 return ret_val;
4065 4082
4066 phy_info->cable_polarity = polarity; 4083 phy_info->cable_polarity = polarity;
4067 4084
4068 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 4085 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4069 if(ret_val) 4086 if (ret_val)
4070 return ret_val; 4087 return ret_val;
4071 4088
4072 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> 4089 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
4073 IGP01E1000_PSSR_MDIX_SHIFT; 4090 IGP01E1000_PSSR_MDIX_SHIFT;
4074 4091
4075 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4092 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4076 IGP01E1000_PSSR_SPEED_1000MBPS) { 4093 IGP01E1000_PSSR_SPEED_1000MBPS) {
4077 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 4094 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4078 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4095 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4079 if(ret_val) 4096 if (ret_val)
4080 return ret_val; 4097 return ret_val;
4081 4098
4082 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4099 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4086,19 +4103,19 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4086 4103
4087 /* Get cable length */ 4104 /* Get cable length */
4088 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 4105 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4089 if(ret_val) 4106 if (ret_val)
4090 return ret_val; 4107 return ret_val;
4091 4108
4092 /* Translate to old method */ 4109 /* Translate to old method */
4093 average = (max_length + min_length) / 2; 4110 average = (max_length + min_length) / 2;
4094 4111
4095 if(average <= e1000_igp_cable_length_50) 4112 if (average <= e1000_igp_cable_length_50)
4096 phy_info->cable_length = e1000_cable_length_50; 4113 phy_info->cable_length = e1000_cable_length_50;
4097 else if(average <= e1000_igp_cable_length_80) 4114 else if (average <= e1000_igp_cable_length_80)
4098 phy_info->cable_length = e1000_cable_length_50_80; 4115 phy_info->cable_length = e1000_cable_length_50_80;
4099 else if(average <= e1000_igp_cable_length_110) 4116 else if (average <= e1000_igp_cable_length_110)
4100 phy_info->cable_length = e1000_cable_length_80_110; 4117 phy_info->cable_length = e1000_cable_length_80_110;
4101 else if(average <= e1000_igp_cable_length_140) 4118 else if (average <= e1000_igp_cable_length_140)
4102 phy_info->cable_length = e1000_cable_length_110_140; 4119 phy_info->cable_length = e1000_cable_length_110_140;
4103 else 4120 else
4104 phy_info->cable_length = e1000_cable_length_140; 4121 phy_info->cable_length = e1000_cable_length_140;
@@ -4174,7 +4191,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4174 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 4191 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4175 4192
4176 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 4193 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4177 if(ret_val) 4194 if (ret_val)
4178 return ret_val; 4195 return ret_val;
4179 4196
4180 phy_info->extended_10bt_distance = 4197 phy_info->extended_10bt_distance =
@@ -4186,12 +4203,12 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4186 4203
4187 /* Check polarity status */ 4204 /* Check polarity status */
4188 ret_val = e1000_check_polarity(hw, &polarity); 4205 ret_val = e1000_check_polarity(hw, &polarity);
4189 if(ret_val) 4206 if (ret_val)
4190 return ret_val; 4207 return ret_val;
4191 phy_info->cable_polarity = polarity; 4208 phy_info->cable_polarity = polarity;
4192 4209
4193 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 4210 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4194 if(ret_val) 4211 if (ret_val)
4195 return ret_val; 4212 return ret_val;
4196 4213
4197 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> 4214 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
@@ -4214,7 +4231,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4214 } 4231 }
4215 4232
4216 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4233 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4217 if(ret_val) 4234 if (ret_val)
4218 return ret_val; 4235 return ret_val;
4219 4236
4220 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4237 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4251,20 +4268,20 @@ e1000_phy_get_info(struct e1000_hw *hw,
4251 phy_info->local_rx = e1000_1000t_rx_status_undefined; 4268 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4252 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 4269 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4253 4270
4254 if(hw->media_type != e1000_media_type_copper) { 4271 if (hw->media_type != e1000_media_type_copper) {
4255 DEBUGOUT("PHY info is only valid for copper media\n"); 4272 DEBUGOUT("PHY info is only valid for copper media\n");
4256 return -E1000_ERR_CONFIG; 4273 return -E1000_ERR_CONFIG;
4257 } 4274 }
4258 4275
4259 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4276 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4260 if(ret_val) 4277 if (ret_val)
4261 return ret_val; 4278 return ret_val;
4262 4279
4263 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4280 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4264 if(ret_val) 4281 if (ret_val)
4265 return ret_val; 4282 return ret_val;
4266 4283
4267 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 4284 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4268 DEBUGOUT("PHY info is only valid if link is up\n"); 4285 DEBUGOUT("PHY info is only valid if link is up\n");
4269 return -E1000_ERR_CONFIG; 4286 return -E1000_ERR_CONFIG;
4270 } 4287 }
@@ -4284,7 +4301,7 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
4284{ 4301{
4285 DEBUGFUNC("e1000_validate_mdi_settings"); 4302 DEBUGFUNC("e1000_validate_mdi_settings");
4286 4303
4287 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 4304 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4288 DEBUGOUT("Invalid MDI setting detected\n"); 4305 DEBUGOUT("Invalid MDI setting detected\n");
4289 hw->mdix = 1; 4306 hw->mdix = 1;
4290 return -E1000_ERR_CONFIG; 4307 return -E1000_ERR_CONFIG;
@@ -4331,7 +4348,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4331 eeprom->type = e1000_eeprom_microwire; 4348 eeprom->type = e1000_eeprom_microwire;
4332 eeprom->opcode_bits = 3; 4349 eeprom->opcode_bits = 3;
4333 eeprom->delay_usec = 50; 4350 eeprom->delay_usec = 50;
4334 if(eecd & E1000_EECD_SIZE) { 4351 if (eecd & E1000_EECD_SIZE) {
4335 eeprom->word_size = 256; 4352 eeprom->word_size = 256;
4336 eeprom->address_bits = 8; 4353 eeprom->address_bits = 8;
4337 } else { 4354 } else {
@@ -4399,7 +4416,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4399 } 4416 }
4400 eeprom->use_eerd = TRUE; 4417 eeprom->use_eerd = TRUE;
4401 eeprom->use_eewr = TRUE; 4418 eeprom->use_eewr = TRUE;
4402 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 4419 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4403 eeprom->type = e1000_eeprom_flash; 4420 eeprom->type = e1000_eeprom_flash;
4404 eeprom->word_size = 2048; 4421 eeprom->word_size = 2048;
4405 4422
@@ -4460,17 +4477,17 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4460 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 4477 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4461 * 32KB (incremented by powers of 2). 4478 * 32KB (incremented by powers of 2).
4462 */ 4479 */
4463 if(hw->mac_type <= e1000_82547_rev_2) { 4480 if (hw->mac_type <= e1000_82547_rev_2) {
4464 /* Set to default value for initial eeprom read. */ 4481 /* Set to default value for initial eeprom read. */
4465 eeprom->word_size = 64; 4482 eeprom->word_size = 64;
4466 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 4483 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4467 if(ret_val) 4484 if (ret_val)
4468 return ret_val; 4485 return ret_val;
4469 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 4486 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4470 /* 256B eeprom size was not supported in earlier hardware, so we 4487 /* 256B eeprom size was not supported in earlier hardware, so we
4471 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 4488 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4472 * is never the result used in the shifting logic below. */ 4489 * is never the result used in the shifting logic below. */
4473 if(eeprom_size) 4490 if (eeprom_size)
4474 eeprom_size++; 4491 eeprom_size++;
4475 } else { 4492 } else {
4476 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> 4493 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
@@ -4555,7 +4572,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4555 */ 4572 */
4556 eecd &= ~E1000_EECD_DI; 4573 eecd &= ~E1000_EECD_DI;
4557 4574
4558 if(data & mask) 4575 if (data & mask)
4559 eecd |= E1000_EECD_DI; 4576 eecd |= E1000_EECD_DI;
4560 4577
4561 E1000_WRITE_REG(hw, EECD, eecd); 4578 E1000_WRITE_REG(hw, EECD, eecd);
@@ -4568,7 +4585,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4568 4585
4569 mask = mask >> 1; 4586 mask = mask >> 1;
4570 4587
4571 } while(mask); 4588 } while (mask);
4572 4589
4573 /* We leave the "DI" bit set to "0" when we leave this routine. */ 4590 /* We leave the "DI" bit set to "0" when we leave this routine. */
4574 eecd &= ~E1000_EECD_DI; 4591 eecd &= ~E1000_EECD_DI;
@@ -4600,14 +4617,14 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4600 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 4617 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4601 data = 0; 4618 data = 0;
4602 4619
4603 for(i = 0; i < count; i++) { 4620 for (i = 0; i < count; i++) {
4604 data = data << 1; 4621 data = data << 1;
4605 e1000_raise_ee_clk(hw, &eecd); 4622 e1000_raise_ee_clk(hw, &eecd);
4606 4623
4607 eecd = E1000_READ_REG(hw, EECD); 4624 eecd = E1000_READ_REG(hw, EECD);
4608 4625
4609 eecd &= ~(E1000_EECD_DI); 4626 eecd &= ~(E1000_EECD_DI);
4610 if(eecd & E1000_EECD_DO) 4627 if (eecd & E1000_EECD_DO)
4611 data |= 1; 4628 data |= 1;
4612 4629
4613 e1000_lower_ee_clk(hw, &eecd); 4630 e1000_lower_ee_clk(hw, &eecd);
@@ -4638,17 +4655,17 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
4638 4655
4639 if (hw->mac_type != e1000_82573) { 4656 if (hw->mac_type != e1000_82573) {
4640 /* Request EEPROM Access */ 4657 /* Request EEPROM Access */
4641 if(hw->mac_type > e1000_82544) { 4658 if (hw->mac_type > e1000_82544) {
4642 eecd |= E1000_EECD_REQ; 4659 eecd |= E1000_EECD_REQ;
4643 E1000_WRITE_REG(hw, EECD, eecd); 4660 E1000_WRITE_REG(hw, EECD, eecd);
4644 eecd = E1000_READ_REG(hw, EECD); 4661 eecd = E1000_READ_REG(hw, EECD);
4645 while((!(eecd & E1000_EECD_GNT)) && 4662 while ((!(eecd & E1000_EECD_GNT)) &&
4646 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 4663 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4647 i++; 4664 i++;
4648 udelay(5); 4665 udelay(5);
4649 eecd = E1000_READ_REG(hw, EECD); 4666 eecd = E1000_READ_REG(hw, EECD);
4650 } 4667 }
4651 if(!(eecd & E1000_EECD_GNT)) { 4668 if (!(eecd & E1000_EECD_GNT)) {
4652 eecd &= ~E1000_EECD_REQ; 4669 eecd &= ~E1000_EECD_REQ;
4653 E1000_WRITE_REG(hw, EECD, eecd); 4670 E1000_WRITE_REG(hw, EECD, eecd);
4654 DEBUGOUT("Could not acquire EEPROM grant\n"); 4671 DEBUGOUT("Could not acquire EEPROM grant\n");
@@ -4691,7 +4708,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4691 4708
4692 eecd = E1000_READ_REG(hw, EECD); 4709 eecd = E1000_READ_REG(hw, EECD);
4693 4710
4694 if(eeprom->type == e1000_eeprom_microwire) { 4711 if (eeprom->type == e1000_eeprom_microwire) {
4695 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4712 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4696 E1000_WRITE_REG(hw, EECD, eecd); 4713 E1000_WRITE_REG(hw, EECD, eecd);
4697 E1000_WRITE_FLUSH(hw); 4714 E1000_WRITE_FLUSH(hw);
@@ -4714,7 +4731,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4714 E1000_WRITE_REG(hw, EECD, eecd); 4731 E1000_WRITE_REG(hw, EECD, eecd);
4715 E1000_WRITE_FLUSH(hw); 4732 E1000_WRITE_FLUSH(hw);
4716 udelay(eeprom->delay_usec); 4733 udelay(eeprom->delay_usec);
4717 } else if(eeprom->type == e1000_eeprom_spi) { 4734 } else if (eeprom->type == e1000_eeprom_spi) {
4718 /* Toggle CS to flush commands */ 4735 /* Toggle CS to flush commands */
4719 eecd |= E1000_EECD_CS; 4736 eecd |= E1000_EECD_CS;
4720 E1000_WRITE_REG(hw, EECD, eecd); 4737 E1000_WRITE_REG(hw, EECD, eecd);
@@ -4748,7 +4765,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4748 E1000_WRITE_REG(hw, EECD, eecd); 4765 E1000_WRITE_REG(hw, EECD, eecd);
4749 4766
4750 udelay(hw->eeprom.delay_usec); 4767 udelay(hw->eeprom.delay_usec);
4751 } else if(hw->eeprom.type == e1000_eeprom_microwire) { 4768 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4752 /* cleanup eeprom */ 4769 /* cleanup eeprom */
4753 4770
4754 /* CS on Microwire is active-high */ 4771 /* CS on Microwire is active-high */
@@ -4770,7 +4787,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4770 } 4787 }
4771 4788
4772 /* Stop requesting EEPROM access */ 4789 /* Stop requesting EEPROM access */
4773 if(hw->mac_type > e1000_82544) { 4790 if (hw->mac_type > e1000_82544) {
4774 eecd &= ~E1000_EECD_REQ; 4791 eecd &= ~E1000_EECD_REQ;
4775 E1000_WRITE_REG(hw, EECD, eecd); 4792 E1000_WRITE_REG(hw, EECD, eecd);
4776 } 4793 }
@@ -4808,12 +4825,12 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4808 retry_count += 5; 4825 retry_count += 5;
4809 4826
4810 e1000_standby_eeprom(hw); 4827 e1000_standby_eeprom(hw);
4811 } while(retry_count < EEPROM_MAX_RETRY_SPI); 4828 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4812 4829
4813 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 4830 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4814 * only 0-5mSec on 5V devices) 4831 * only 0-5mSec on 5V devices)
4815 */ 4832 */
4816 if(retry_count >= EEPROM_MAX_RETRY_SPI) { 4833 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4817 DEBUGOUT("SPI EEPROM Status error\n"); 4834 DEBUGOUT("SPI EEPROM Status error\n");
4818 return -E1000_ERR_EEPROM; 4835 return -E1000_ERR_EEPROM;
4819 } 4836 }
@@ -4844,7 +4861,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4844 /* A check for invalid values: offset too large, too many words, and not 4861 /* A check for invalid values: offset too large, too many words, and not
4845 * enough words. 4862 * enough words.
4846 */ 4863 */
4847 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4864 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4848 (words == 0)) { 4865 (words == 0)) {
4849 DEBUGOUT("\"words\" parameter out of bounds\n"); 4866 DEBUGOUT("\"words\" parameter out of bounds\n");
4850 return -E1000_ERR_EEPROM; 4867 return -E1000_ERR_EEPROM;
@@ -4852,7 +4869,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4852 4869
4853 /* FLASH reads without acquiring the semaphore are safe */ 4870 /* FLASH reads without acquiring the semaphore are safe */
4854 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 4871 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4855 hw->eeprom.use_eerd == FALSE) { 4872 hw->eeprom.use_eerd == FALSE) {
4856 switch (hw->mac_type) { 4873 switch (hw->mac_type) {
4857 case e1000_80003es2lan: 4874 case e1000_80003es2lan:
4858 break; 4875 break;
@@ -4879,7 +4896,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4879 uint16_t word_in; 4896 uint16_t word_in;
4880 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4897 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4881 4898
4882 if(e1000_spi_eeprom_ready(hw)) { 4899 if (e1000_spi_eeprom_ready(hw)) {
4883 e1000_release_eeprom(hw); 4900 e1000_release_eeprom(hw);
4884 return -E1000_ERR_EEPROM; 4901 return -E1000_ERR_EEPROM;
4885 } 4902 }
@@ -4887,7 +4904,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4887 e1000_standby_eeprom(hw); 4904 e1000_standby_eeprom(hw);
4888 4905
4889 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 4906 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4890 if((eeprom->address_bits == 8) && (offset >= 128)) 4907 if ((eeprom->address_bits == 8) && (offset >= 128))
4891 read_opcode |= EEPROM_A8_OPCODE_SPI; 4908 read_opcode |= EEPROM_A8_OPCODE_SPI;
4892 4909
4893 /* Send the READ command (opcode + addr) */ 4910 /* Send the READ command (opcode + addr) */
@@ -4903,7 +4920,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4903 word_in = e1000_shift_in_ee_bits(hw, 16); 4920 word_in = e1000_shift_in_ee_bits(hw, 16);
4904 data[i] = (word_in >> 8) | (word_in << 8); 4921 data[i] = (word_in >> 8) | (word_in << 8);
4905 } 4922 }
4906 } else if(eeprom->type == e1000_eeprom_microwire) { 4923 } else if (eeprom->type == e1000_eeprom_microwire) {
4907 for (i = 0; i < words; i++) { 4924 for (i = 0; i < words; i++) {
4908 /* Send the READ command (opcode + addr) */ 4925 /* Send the READ command (opcode + addr) */
4909 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 4926 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
@@ -4948,7 +4965,7 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
4948 E1000_WRITE_REG(hw, EERD, eerd); 4965 E1000_WRITE_REG(hw, EERD, eerd);
4949 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 4966 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4950 4967
4951 if(error) { 4968 if (error) {
4952 break; 4969 break;
4953 } 4970 }
4954 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); 4971 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
@@ -4985,7 +5002,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
4985 E1000_EEPROM_RW_REG_START; 5002 E1000_EEPROM_RW_REG_START;
4986 5003
4987 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5004 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4988 if(error) { 5005 if (error) {
4989 break; 5006 break;
4990 } 5007 }
4991 5008
@@ -4993,7 +5010,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
4993 5010
4994 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5011 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4995 5012
4996 if(error) { 5013 if (error) {
4997 break; 5014 break;
4998 } 5015 }
4999 } 5016 }
@@ -5014,13 +5031,13 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5014 uint32_t i, reg = 0; 5031 uint32_t i, reg = 0;
5015 int32_t done = E1000_ERR_EEPROM; 5032 int32_t done = E1000_ERR_EEPROM;
5016 5033
5017 for(i = 0; i < attempts; i++) { 5034 for (i = 0; i < attempts; i++) {
5018 if(eerd == E1000_EEPROM_POLL_READ) 5035 if (eerd == E1000_EEPROM_POLL_READ)
5019 reg = E1000_READ_REG(hw, EERD); 5036 reg = E1000_READ_REG(hw, EERD);
5020 else 5037 else
5021 reg = E1000_READ_REG(hw, EEWR); 5038 reg = E1000_READ_REG(hw, EEWR);
5022 5039
5023 if(reg & E1000_EEPROM_RW_REG_DONE) { 5040 if (reg & E1000_EEPROM_RW_REG_DONE) {
5024 done = E1000_SUCCESS; 5041 done = E1000_SUCCESS;
5025 break; 5042 break;
5026 } 5043 }
@@ -5052,7 +5069,7 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5052 eecd = ((eecd >> 15) & 0x03); 5069 eecd = ((eecd >> 15) & 0x03);
5053 5070
5054 /* If both bits are set, device is Flash type */ 5071 /* If both bits are set, device is Flash type */
5055 if(eecd == 0x03) { 5072 if (eecd == 0x03) {
5056 return FALSE; 5073 return FALSE;
5057 } 5074 }
5058 } 5075 }
@@ -5117,7 +5134,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5117 checksum += eeprom_data; 5134 checksum += eeprom_data;
5118 } 5135 }
5119 5136
5120 if(checksum == (uint16_t) EEPROM_SUM) 5137 if (checksum == (uint16_t) EEPROM_SUM)
5121 return E1000_SUCCESS; 5138 return E1000_SUCCESS;
5122 else { 5139 else {
5123 DEBUGOUT("EEPROM Checksum Invalid\n"); 5140 DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -5142,15 +5159,15 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5142 5159
5143 DEBUGFUNC("e1000_update_eeprom_checksum"); 5160 DEBUGFUNC("e1000_update_eeprom_checksum");
5144 5161
5145 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { 5162 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5146 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5163 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5147 DEBUGOUT("EEPROM Read Error\n"); 5164 DEBUGOUT("EEPROM Read Error\n");
5148 return -E1000_ERR_EEPROM; 5165 return -E1000_ERR_EEPROM;
5149 } 5166 }
5150 checksum += eeprom_data; 5167 checksum += eeprom_data;
5151 } 5168 }
5152 checksum = (uint16_t) EEPROM_SUM - checksum; 5169 checksum = (uint16_t) EEPROM_SUM - checksum;
5153 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5170 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5154 DEBUGOUT("EEPROM Write Error\n"); 5171 DEBUGOUT("EEPROM Write Error\n");
5155 return -E1000_ERR_EEPROM; 5172 return -E1000_ERR_EEPROM;
5156 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5173 } else if (hw->eeprom.type == e1000_eeprom_flash) {
@@ -5192,14 +5209,14 @@ e1000_write_eeprom(struct e1000_hw *hw,
5192 /* A check for invalid values: offset too large, too many words, and not 5209 /* A check for invalid values: offset too large, too many words, and not
5193 * enough words. 5210 * enough words.
5194 */ 5211 */
5195 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 5212 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5196 (words == 0)) { 5213 (words == 0)) {
5197 DEBUGOUT("\"words\" parameter out of bounds\n"); 5214 DEBUGOUT("\"words\" parameter out of bounds\n");
5198 return -E1000_ERR_EEPROM; 5215 return -E1000_ERR_EEPROM;
5199 } 5216 }
5200 5217
5201 /* 82573 writes only through eewr */ 5218 /* 82573 writes only through eewr */
5202 if(eeprom->use_eewr == TRUE) 5219 if (eeprom->use_eewr == TRUE)
5203 return e1000_write_eeprom_eewr(hw, offset, words, data); 5220 return e1000_write_eeprom_eewr(hw, offset, words, data);
5204 5221
5205 if (eeprom->type == e1000_eeprom_ich8) 5222 if (eeprom->type == e1000_eeprom_ich8)
@@ -5209,7 +5226,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
5209 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5226 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5210 return -E1000_ERR_EEPROM; 5227 return -E1000_ERR_EEPROM;
5211 5228
5212 if(eeprom->type == e1000_eeprom_microwire) { 5229 if (eeprom->type == e1000_eeprom_microwire) {
5213 status = e1000_write_eeprom_microwire(hw, offset, words, data); 5230 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5214 } else { 5231 } else {
5215 status = e1000_write_eeprom_spi(hw, offset, words, data); 5232 status = e1000_write_eeprom_spi(hw, offset, words, data);
@@ -5245,7 +5262,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5245 while (widx < words) { 5262 while (widx < words) {
5246 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 5263 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5247 5264
5248 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 5265 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5249 5266
5250 e1000_standby_eeprom(hw); 5267 e1000_standby_eeprom(hw);
5251 5268
@@ -5256,7 +5273,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5256 e1000_standby_eeprom(hw); 5273 e1000_standby_eeprom(hw);
5257 5274
5258 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 5275 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5259 if((eeprom->address_bits == 8) && (offset >= 128)) 5276 if ((eeprom->address_bits == 8) && (offset >= 128))
5260 write_opcode |= EEPROM_A8_OPCODE_SPI; 5277 write_opcode |= EEPROM_A8_OPCODE_SPI;
5261 5278
5262 /* Send the Write command (8-bit opcode + addr) */ 5279 /* Send the Write command (8-bit opcode + addr) */
@@ -5278,7 +5295,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5278 * operation, while the smaller eeproms are capable of an 8-byte 5295 * operation, while the smaller eeproms are capable of an 8-byte
5279 * PAGE WRITE operation. Break the inner loop to pass new address 5296 * PAGE WRITE operation. Break the inner loop to pass new address
5280 */ 5297 */
5281 if((((offset + widx)*2) % eeprom->page_size) == 0) { 5298 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5282 e1000_standby_eeprom(hw); 5299 e1000_standby_eeprom(hw);
5283 break; 5300 break;
5284 } 5301 }
@@ -5344,12 +5361,12 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5344 * signal that the command has been completed by raising the DO signal. 5361 * signal that the command has been completed by raising the DO signal.
5345 * If DO does not go high in 10 milliseconds, then error out. 5362 * If DO does not go high in 10 milliseconds, then error out.
5346 */ 5363 */
5347 for(i = 0; i < 200; i++) { 5364 for (i = 0; i < 200; i++) {
5348 eecd = E1000_READ_REG(hw, EECD); 5365 eecd = E1000_READ_REG(hw, EECD);
5349 if(eecd & E1000_EECD_DO) break; 5366 if (eecd & E1000_EECD_DO) break;
5350 udelay(50); 5367 udelay(50);
5351 } 5368 }
5352 if(i == 200) { 5369 if (i == 200) {
5353 DEBUGOUT("EEPROM Write did not complete\n"); 5370 DEBUGOUT("EEPROM Write did not complete\n");
5354 return -E1000_ERR_EEPROM; 5371 return -E1000_ERR_EEPROM;
5355 } 5372 }
@@ -5540,40 +5557,6 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5540} 5557}
5541 5558
5542/****************************************************************************** 5559/******************************************************************************
5543 * Reads the adapter's part number from the EEPROM
5544 *
5545 * hw - Struct containing variables accessed by shared code
5546 * part_num - Adapter's part number
5547 *****************************************************************************/
5548int32_t
5549e1000_read_part_num(struct e1000_hw *hw,
5550 uint32_t *part_num)
5551{
5552 uint16_t offset = EEPROM_PBA_BYTE_1;
5553 uint16_t eeprom_data;
5554
5555 DEBUGFUNC("e1000_read_part_num");
5556
5557 /* Get word 0 from EEPROM */
5558 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5559 DEBUGOUT("EEPROM Read Error\n");
5560 return -E1000_ERR_EEPROM;
5561 }
5562 /* Save word 0 in upper half of part_num */
5563 *part_num = (uint32_t) (eeprom_data << 16);
5564
5565 /* Get word 1 from EEPROM */
5566 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5567 DEBUGOUT("EEPROM Read Error\n");
5568 return -E1000_ERR_EEPROM;
5569 }
5570 /* Save word 1 in lower half of part_num */
5571 *part_num |= eeprom_data;
5572
5573 return E1000_SUCCESS;
5574}
5575
5576/******************************************************************************
5577 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 5560 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5578 * second function of dual function devices 5561 * second function of dual function devices
5579 * 5562 *
@@ -5587,9 +5570,9 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5587 5570
5588 DEBUGFUNC("e1000_read_mac_addr"); 5571 DEBUGFUNC("e1000_read_mac_addr");
5589 5572
5590 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 5573 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5591 offset = i >> 1; 5574 offset = i >> 1;
5592 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 5575 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5593 DEBUGOUT("EEPROM Read Error\n"); 5576 DEBUGOUT("EEPROM Read Error\n");
5594 return -E1000_ERR_EEPROM; 5577 return -E1000_ERR_EEPROM;
5595 } 5578 }
@@ -5604,12 +5587,12 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5604 case e1000_82546_rev_3: 5587 case e1000_82546_rev_3:
5605 case e1000_82571: 5588 case e1000_82571:
5606 case e1000_80003es2lan: 5589 case e1000_80003es2lan:
5607 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 5590 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5608 hw->perm_mac_addr[5] ^= 0x01; 5591 hw->perm_mac_addr[5] ^= 0x01;
5609 break; 5592 break;
5610 } 5593 }
5611 5594
5612 for(i = 0; i < NODE_ADDRESS_SIZE; i++) 5595 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5613 hw->mac_addr[i] = hw->perm_mac_addr[i]; 5596 hw->mac_addr[i] = hw->perm_mac_addr[i];
5614 return E1000_SUCCESS; 5597 return E1000_SUCCESS;
5615} 5598}
@@ -5648,7 +5631,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5648 5631
5649 /* Zero out the other 15 receive addresses. */ 5632 /* Zero out the other 15 receive addresses. */
5650 DEBUGOUT("Clearing RAR[1-15]\n"); 5633 DEBUGOUT("Clearing RAR[1-15]\n");
5651 for(i = 1; i < rar_num; i++) { 5634 for (i = 1; i < rar_num; i++) {
5652 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5635 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5653 E1000_WRITE_FLUSH(hw); 5636 E1000_WRITE_FLUSH(hw);
5654 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5637 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5699,7 +5682,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5699 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5682 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5700 num_rar_entry -= 1; 5683 num_rar_entry -= 1;
5701 5684
5702 for(i = rar_used_count; i < num_rar_entry; i++) { 5685 for (i = rar_used_count; i < num_rar_entry; i++) {
5703 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5686 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5704 E1000_WRITE_FLUSH(hw); 5687 E1000_WRITE_FLUSH(hw);
5705 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5688 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5711,13 +5694,13 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5711 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5694 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5712 if (hw->mac_type == e1000_ich8lan) 5695 if (hw->mac_type == e1000_ich8lan)
5713 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 5696 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5714 for(i = 0; i < num_mta_entry; i++) { 5697 for (i = 0; i < num_mta_entry; i++) {
5715 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5698 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5716 E1000_WRITE_FLUSH(hw); 5699 E1000_WRITE_FLUSH(hw);
5717 } 5700 }
5718 5701
5719 /* Add the new addresses */ 5702 /* Add the new addresses */
5720 for(i = 0; i < mc_addr_count; i++) { 5703 for (i = 0; i < mc_addr_count; i++) {
5721 DEBUGOUT(" Adding the multicast addresses:\n"); 5704 DEBUGOUT(" Adding the multicast addresses:\n");
5722 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 5705 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5723 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 5706 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
@@ -5849,7 +5832,7 @@ e1000_mta_set(struct e1000_hw *hw,
5849 * in the MTA, save off the previous entry before writing and 5832 * in the MTA, save off the previous entry before writing and
5850 * restore the old value after writing. 5833 * restore the old value after writing.
5851 */ 5834 */
5852 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5835 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5853 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5836 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5854 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5837 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5855 E1000_WRITE_FLUSH(hw); 5838 E1000_WRITE_FLUSH(hw);
@@ -5999,7 +5982,7 @@ e1000_id_led_init(struct e1000_hw * hw)
5999 5982
6000 DEBUGFUNC("e1000_id_led_init"); 5983 DEBUGFUNC("e1000_id_led_init");
6001 5984
6002 if(hw->mac_type < e1000_82540) { 5985 if (hw->mac_type < e1000_82540) {
6003 /* Nothing to do */ 5986 /* Nothing to do */
6004 return E1000_SUCCESS; 5987 return E1000_SUCCESS;
6005 } 5988 }
@@ -6009,7 +5992,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6009 hw->ledctl_mode1 = hw->ledctl_default; 5992 hw->ledctl_mode1 = hw->ledctl_default;
6010 hw->ledctl_mode2 = hw->ledctl_default; 5993 hw->ledctl_mode2 = hw->ledctl_default;
6011 5994
6012 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 5995 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6013 DEBUGOUT("EEPROM Read Error\n"); 5996 DEBUGOUT("EEPROM Read Error\n");
6014 return -E1000_ERR_EEPROM; 5997 return -E1000_ERR_EEPROM;
6015 } 5998 }
@@ -6026,7 +6009,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6026 } 6009 }
6027 for (i = 0; i < 4; i++) { 6010 for (i = 0; i < 4; i++) {
6028 temp = (eeprom_data >> (i << 2)) & led_mask; 6011 temp = (eeprom_data >> (i << 2)) & led_mask;
6029 switch(temp) { 6012 switch (temp) {
6030 case ID_LED_ON1_DEF2: 6013 case ID_LED_ON1_DEF2:
6031 case ID_LED_ON1_ON2: 6014 case ID_LED_ON1_ON2:
6032 case ID_LED_ON1_OFF2: 6015 case ID_LED_ON1_OFF2:
@@ -6043,7 +6026,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6043 /* Do nothing */ 6026 /* Do nothing */
6044 break; 6027 break;
6045 } 6028 }
6046 switch(temp) { 6029 switch (temp) {
6047 case ID_LED_DEF1_ON2: 6030 case ID_LED_DEF1_ON2:
6048 case ID_LED_ON1_ON2: 6031 case ID_LED_ON1_ON2:
6049 case ID_LED_OFF1_ON2: 6032 case ID_LED_OFF1_ON2:
@@ -6077,7 +6060,7 @@ e1000_setup_led(struct e1000_hw *hw)
6077 6060
6078 DEBUGFUNC("e1000_setup_led"); 6061 DEBUGFUNC("e1000_setup_led");
6079 6062
6080 switch(hw->mac_type) { 6063 switch (hw->mac_type) {
6081 case e1000_82542_rev2_0: 6064 case e1000_82542_rev2_0:
6082 case e1000_82542_rev2_1: 6065 case e1000_82542_rev2_1:
6083 case e1000_82543: 6066 case e1000_82543:
@@ -6091,16 +6074,16 @@ e1000_setup_led(struct e1000_hw *hw)
6091 /* Turn off PHY Smart Power Down (if enabled) */ 6074 /* Turn off PHY Smart Power Down (if enabled) */
6092 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 6075 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6093 &hw->phy_spd_default); 6076 &hw->phy_spd_default);
6094 if(ret_val) 6077 if (ret_val)
6095 return ret_val; 6078 return ret_val;
6096 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6079 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6097 (uint16_t)(hw->phy_spd_default & 6080 (uint16_t)(hw->phy_spd_default &
6098 ~IGP01E1000_GMII_SPD)); 6081 ~IGP01E1000_GMII_SPD));
6099 if(ret_val) 6082 if (ret_val)
6100 return ret_val; 6083 return ret_val;
6101 /* Fall Through */ 6084 /* Fall Through */
6102 default: 6085 default:
6103 if(hw->media_type == e1000_media_type_fiber) { 6086 if (hw->media_type == e1000_media_type_fiber) {
6104 ledctl = E1000_READ_REG(hw, LEDCTL); 6087 ledctl = E1000_READ_REG(hw, LEDCTL);
6105 /* Save current LEDCTL settings */ 6088 /* Save current LEDCTL settings */
6106 hw->ledctl_default = ledctl; 6089 hw->ledctl_default = ledctl;
@@ -6111,7 +6094,7 @@ e1000_setup_led(struct e1000_hw *hw)
6111 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 6094 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6112 E1000_LEDCTL_LED0_MODE_SHIFT); 6095 E1000_LEDCTL_LED0_MODE_SHIFT);
6113 E1000_WRITE_REG(hw, LEDCTL, ledctl); 6096 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6114 } else if(hw->media_type == e1000_media_type_copper) 6097 } else if (hw->media_type == e1000_media_type_copper)
6115 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6098 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6116 break; 6099 break;
6117 } 6100 }
@@ -6119,6 +6102,7 @@ e1000_setup_led(struct e1000_hw *hw)
6119 return E1000_SUCCESS; 6102 return E1000_SUCCESS;
6120} 6103}
6121 6104
6105
6122/****************************************************************************** 6106/******************************************************************************
6123 * Used on 82571 and later Si that has LED blink bits. 6107 * Used on 82571 and later Si that has LED blink bits.
6124 * Callers must use their own timer and should have already called 6108 * Callers must use their own timer and should have already called
@@ -6169,7 +6153,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
6169 6153
6170 DEBUGFUNC("e1000_cleanup_led"); 6154 DEBUGFUNC("e1000_cleanup_led");
6171 6155
6172 switch(hw->mac_type) { 6156 switch (hw->mac_type) {
6173 case e1000_82542_rev2_0: 6157 case e1000_82542_rev2_0:
6174 case e1000_82542_rev2_1: 6158 case e1000_82542_rev2_1:
6175 case e1000_82543: 6159 case e1000_82543:
@@ -6183,7 +6167,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
6183 /* Turn on PHY Smart Power Down (if previously enabled) */ 6167 /* Turn on PHY Smart Power Down (if previously enabled) */
6184 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6168 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6185 hw->phy_spd_default); 6169 hw->phy_spd_default);
6186 if(ret_val) 6170 if (ret_val)
6187 return ret_val; 6171 return ret_val;
6188 /* Fall Through */ 6172 /* Fall Through */
6189 default: 6173 default:
@@ -6211,7 +6195,7 @@ e1000_led_on(struct e1000_hw *hw)
6211 6195
6212 DEBUGFUNC("e1000_led_on"); 6196 DEBUGFUNC("e1000_led_on");
6213 6197
6214 switch(hw->mac_type) { 6198 switch (hw->mac_type) {
6215 case e1000_82542_rev2_0: 6199 case e1000_82542_rev2_0:
6216 case e1000_82542_rev2_1: 6200 case e1000_82542_rev2_1:
6217 case e1000_82543: 6201 case e1000_82543:
@@ -6220,7 +6204,7 @@ e1000_led_on(struct e1000_hw *hw)
6220 ctrl |= E1000_CTRL_SWDPIO0; 6204 ctrl |= E1000_CTRL_SWDPIO0;
6221 break; 6205 break;
6222 case e1000_82544: 6206 case e1000_82544:
6223 if(hw->media_type == e1000_media_type_fiber) { 6207 if (hw->media_type == e1000_media_type_fiber) {
6224 /* Set SW Defineable Pin 0 to turn on the LED */ 6208 /* Set SW Defineable Pin 0 to turn on the LED */
6225 ctrl |= E1000_CTRL_SWDPIN0; 6209 ctrl |= E1000_CTRL_SWDPIN0;
6226 ctrl |= E1000_CTRL_SWDPIO0; 6210 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6231,7 +6215,7 @@ e1000_led_on(struct e1000_hw *hw)
6231 } 6215 }
6232 break; 6216 break;
6233 default: 6217 default:
6234 if(hw->media_type == e1000_media_type_fiber) { 6218 if (hw->media_type == e1000_media_type_fiber) {
6235 /* Clear SW Defineable Pin 0 to turn on the LED */ 6219 /* Clear SW Defineable Pin 0 to turn on the LED */
6236 ctrl &= ~E1000_CTRL_SWDPIN0; 6220 ctrl &= ~E1000_CTRL_SWDPIN0;
6237 ctrl |= E1000_CTRL_SWDPIO0; 6221 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6262,7 +6246,7 @@ e1000_led_off(struct e1000_hw *hw)
6262 6246
6263 DEBUGFUNC("e1000_led_off"); 6247 DEBUGFUNC("e1000_led_off");
6264 6248
6265 switch(hw->mac_type) { 6249 switch (hw->mac_type) {
6266 case e1000_82542_rev2_0: 6250 case e1000_82542_rev2_0:
6267 case e1000_82542_rev2_1: 6251 case e1000_82542_rev2_1:
6268 case e1000_82543: 6252 case e1000_82543:
@@ -6271,7 +6255,7 @@ e1000_led_off(struct e1000_hw *hw)
6271 ctrl |= E1000_CTRL_SWDPIO0; 6255 ctrl |= E1000_CTRL_SWDPIO0;
6272 break; 6256 break;
6273 case e1000_82544: 6257 case e1000_82544:
6274 if(hw->media_type == e1000_media_type_fiber) { 6258 if (hw->media_type == e1000_media_type_fiber) {
6275 /* Clear SW Defineable Pin 0 to turn off the LED */ 6259 /* Clear SW Defineable Pin 0 to turn off the LED */
6276 ctrl &= ~E1000_CTRL_SWDPIN0; 6260 ctrl &= ~E1000_CTRL_SWDPIN0;
6277 ctrl |= E1000_CTRL_SWDPIO0; 6261 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6282,7 +6266,7 @@ e1000_led_off(struct e1000_hw *hw)
6282 } 6266 }
6283 break; 6267 break;
6284 default: 6268 default:
6285 if(hw->media_type == e1000_media_type_fiber) { 6269 if (hw->media_type == e1000_media_type_fiber) {
6286 /* Set SW Defineable Pin 0 to turn off the LED */ 6270 /* Set SW Defineable Pin 0 to turn off the LED */
6287 ctrl |= E1000_CTRL_SWDPIN0; 6271 ctrl |= E1000_CTRL_SWDPIN0;
6288 ctrl |= E1000_CTRL_SWDPIO0; 6272 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6306,7 +6290,7 @@ e1000_led_off(struct e1000_hw *hw)
6306 * 6290 *
6307 * hw - Struct containing variables accessed by shared code 6291 * hw - Struct containing variables accessed by shared code
6308 *****************************************************************************/ 6292 *****************************************************************************/
6309static void 6293void
6310e1000_clear_hw_cntrs(struct e1000_hw *hw) 6294e1000_clear_hw_cntrs(struct e1000_hw *hw)
6311{ 6295{
6312 volatile uint32_t temp; 6296 volatile uint32_t temp;
@@ -6369,7 +6353,7 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
6369 temp = E1000_READ_REG(hw, MPTC); 6353 temp = E1000_READ_REG(hw, MPTC);
6370 temp = E1000_READ_REG(hw, BPTC); 6354 temp = E1000_READ_REG(hw, BPTC);
6371 6355
6372 if(hw->mac_type < e1000_82543) return; 6356 if (hw->mac_type < e1000_82543) return;
6373 6357
6374 temp = E1000_READ_REG(hw, ALGNERRC); 6358 temp = E1000_READ_REG(hw, ALGNERRC);
6375 temp = E1000_READ_REG(hw, RXERRC); 6359 temp = E1000_READ_REG(hw, RXERRC);
@@ -6378,13 +6362,13 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
6378 temp = E1000_READ_REG(hw, TSCTC); 6362 temp = E1000_READ_REG(hw, TSCTC);
6379 temp = E1000_READ_REG(hw, TSCTFC); 6363 temp = E1000_READ_REG(hw, TSCTFC);
6380 6364
6381 if(hw->mac_type <= e1000_82544) return; 6365 if (hw->mac_type <= e1000_82544) return;
6382 6366
6383 temp = E1000_READ_REG(hw, MGTPRC); 6367 temp = E1000_READ_REG(hw, MGTPRC);
6384 temp = E1000_READ_REG(hw, MGTPDC); 6368 temp = E1000_READ_REG(hw, MGTPDC);
6385 temp = E1000_READ_REG(hw, MGTPTC); 6369 temp = E1000_READ_REG(hw, MGTPTC);
6386 6370
6387 if(hw->mac_type <= e1000_82547_rev_2) return; 6371 if (hw->mac_type <= e1000_82547_rev_2) return;
6388 6372
6389 temp = E1000_READ_REG(hw, IAC); 6373 temp = E1000_READ_REG(hw, IAC);
6390 temp = E1000_READ_REG(hw, ICRXOC); 6374 temp = E1000_READ_REG(hw, ICRXOC);
@@ -6415,8 +6399,8 @@ e1000_reset_adaptive(struct e1000_hw *hw)
6415{ 6399{
6416 DEBUGFUNC("e1000_reset_adaptive"); 6400 DEBUGFUNC("e1000_reset_adaptive");
6417 6401
6418 if(hw->adaptive_ifs) { 6402 if (hw->adaptive_ifs) {
6419 if(!hw->ifs_params_forced) { 6403 if (!hw->ifs_params_forced) {
6420 hw->current_ifs_val = 0; 6404 hw->current_ifs_val = 0;
6421 hw->ifs_min_val = IFS_MIN; 6405 hw->ifs_min_val = IFS_MIN;
6422 hw->ifs_max_val = IFS_MAX; 6406 hw->ifs_max_val = IFS_MAX;
@@ -6443,12 +6427,12 @@ e1000_update_adaptive(struct e1000_hw *hw)
6443{ 6427{
6444 DEBUGFUNC("e1000_update_adaptive"); 6428 DEBUGFUNC("e1000_update_adaptive");
6445 6429
6446 if(hw->adaptive_ifs) { 6430 if (hw->adaptive_ifs) {
6447 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { 6431 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6448 if(hw->tx_packet_delta > MIN_NUM_XMITS) { 6432 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6449 hw->in_ifs_mode = TRUE; 6433 hw->in_ifs_mode = TRUE;
6450 if(hw->current_ifs_val < hw->ifs_max_val) { 6434 if (hw->current_ifs_val < hw->ifs_max_val) {
6451 if(hw->current_ifs_val == 0) 6435 if (hw->current_ifs_val == 0)
6452 hw->current_ifs_val = hw->ifs_min_val; 6436 hw->current_ifs_val = hw->ifs_min_val;
6453 else 6437 else
6454 hw->current_ifs_val += hw->ifs_step_size; 6438 hw->current_ifs_val += hw->ifs_step_size;
@@ -6456,7 +6440,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
6456 } 6440 }
6457 } 6441 }
6458 } else { 6442 } else {
6459 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 6443 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6460 hw->current_ifs_val = 0; 6444 hw->current_ifs_val = 0;
6461 hw->in_ifs_mode = FALSE; 6445 hw->in_ifs_mode = FALSE;
6462 E1000_WRITE_REG(hw, AIT, 0); 6446 E1000_WRITE_REG(hw, AIT, 0);
@@ -6503,46 +6487,46 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6503 * This could be simplified if all environments supported 6487 * This could be simplified if all environments supported
6504 * 64-bit integers. 6488 * 64-bit integers.
6505 */ 6489 */
6506 if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) 6490 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6507 stats->gorch++; 6491 stats->gorch++;
6508 /* Is this a broadcast or multicast? Check broadcast first, 6492 /* Is this a broadcast or multicast? Check broadcast first,
6509 * since the test for a multicast frame will test positive on 6493 * since the test for a multicast frame will test positive on
6510 * a broadcast frame. 6494 * a broadcast frame.
6511 */ 6495 */
6512 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 6496 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6513 /* Broadcast packet */ 6497 /* Broadcast packet */
6514 stats->bprc++; 6498 stats->bprc++;
6515 else if(*mac_addr & 0x01) 6499 else if (*mac_addr & 0x01)
6516 /* Multicast packet */ 6500 /* Multicast packet */
6517 stats->mprc++; 6501 stats->mprc++;
6518 6502
6519 if(frame_len == hw->max_frame_size) { 6503 if (frame_len == hw->max_frame_size) {
6520 /* In this case, the hardware has overcounted the number of 6504 /* In this case, the hardware has overcounted the number of
6521 * oversize frames. 6505 * oversize frames.
6522 */ 6506 */
6523 if(stats->roc > 0) 6507 if (stats->roc > 0)
6524 stats->roc--; 6508 stats->roc--;
6525 } 6509 }
6526 6510
6527 /* Adjust the bin counters when the extra byte put the frame in the 6511 /* Adjust the bin counters when the extra byte put the frame in the
6528 * wrong bin. Remember that the frame_len was adjusted above. 6512 * wrong bin. Remember that the frame_len was adjusted above.
6529 */ 6513 */
6530 if(frame_len == 64) { 6514 if (frame_len == 64) {
6531 stats->prc64++; 6515 stats->prc64++;
6532 stats->prc127--; 6516 stats->prc127--;
6533 } else if(frame_len == 127) { 6517 } else if (frame_len == 127) {
6534 stats->prc127++; 6518 stats->prc127++;
6535 stats->prc255--; 6519 stats->prc255--;
6536 } else if(frame_len == 255) { 6520 } else if (frame_len == 255) {
6537 stats->prc255++; 6521 stats->prc255++;
6538 stats->prc511--; 6522 stats->prc511--;
6539 } else if(frame_len == 511) { 6523 } else if (frame_len == 511) {
6540 stats->prc511++; 6524 stats->prc511++;
6541 stats->prc1023--; 6525 stats->prc1023--;
6542 } else if(frame_len == 1023) { 6526 } else if (frame_len == 1023) {
6543 stats->prc1023++; 6527 stats->prc1023++;
6544 stats->prc1522--; 6528 stats->prc1522--;
6545 } else if(frame_len == 1522) { 6529 } else if (frame_len == 1522) {
6546 stats->prc1522++; 6530 stats->prc1522++;
6547 } 6531 }
6548} 6532}
@@ -6582,10 +6566,10 @@ e1000_get_bus_info(struct e1000_hw *hw)
6582 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 6566 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6583 e1000_bus_type_pcix : e1000_bus_type_pci; 6567 e1000_bus_type_pcix : e1000_bus_type_pci;
6584 6568
6585 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 6569 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6586 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 6570 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6587 e1000_bus_speed_66 : e1000_bus_speed_120; 6571 e1000_bus_speed_66 : e1000_bus_speed_120;
6588 } else if(hw->bus_type == e1000_bus_type_pci) { 6572 } else if (hw->bus_type == e1000_bus_type_pci) {
6589 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 6573 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6590 e1000_bus_speed_66 : e1000_bus_speed_33; 6574 e1000_bus_speed_66 : e1000_bus_speed_33;
6591 } else { 6575 } else {
@@ -6680,11 +6664,11 @@ e1000_get_cable_length(struct e1000_hw *hw,
6680 *min_length = *max_length = 0; 6664 *min_length = *max_length = 0;
6681 6665
6682 /* Use old method for Phy older than IGP */ 6666 /* Use old method for Phy older than IGP */
6683 if(hw->phy_type == e1000_phy_m88) { 6667 if (hw->phy_type == e1000_phy_m88) {
6684 6668
6685 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6669 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6686 &phy_data); 6670 &phy_data);
6687 if(ret_val) 6671 if (ret_val)
6688 return ret_val; 6672 return ret_val;
6689 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 6673 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6690 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 6674 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
@@ -6743,7 +6727,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
6743 return -E1000_ERR_PHY; 6727 return -E1000_ERR_PHY;
6744 break; 6728 break;
6745 } 6729 }
6746 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6730 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6747 uint16_t cur_agc_value; 6731 uint16_t cur_agc_value;
6748 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 6732 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6749 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6733 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
@@ -6752,10 +6736,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6752 IGP01E1000_PHY_AGC_C, 6736 IGP01E1000_PHY_AGC_C,
6753 IGP01E1000_PHY_AGC_D}; 6737 IGP01E1000_PHY_AGC_D};
6754 /* Read the AGC registers for all channels */ 6738 /* Read the AGC registers for all channels */
6755 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6739 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6756 6740
6757 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 6741 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6758 if(ret_val) 6742 if (ret_val)
6759 return ret_val; 6743 return ret_val;
6760 6744
6761 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6745 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
@@ -6805,7 +6789,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
6805 if (ret_val) 6789 if (ret_val)
6806 return ret_val; 6790 return ret_val;
6807 6791
6808 /* Getting bits 15:9, which represent the combination of course and 6792 /* Getting bits 15:9, which represent the combination of course and
6809 * fine gain values. The result is a number that can be put into 6793 * fine gain values. The result is a number that can be put into
6810 * the lookup table to obtain the approximate cable length. */ 6794 * the lookup table to obtain the approximate cable length. */
6811 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6795 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
@@ -6870,7 +6854,7 @@ e1000_check_polarity(struct e1000_hw *hw,
6870 /* return the Polarity bit in the Status register. */ 6854 /* return the Polarity bit in the Status register. */
6871 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6855 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6872 &phy_data); 6856 &phy_data);
6873 if(ret_val) 6857 if (ret_val)
6874 return ret_val; 6858 return ret_val;
6875 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6859 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6876 M88E1000_PSSR_REV_POLARITY_SHIFT; 6860 M88E1000_PSSR_REV_POLARITY_SHIFT;
@@ -6880,18 +6864,18 @@ e1000_check_polarity(struct e1000_hw *hw,
6880 /* Read the Status register to check the speed */ 6864 /* Read the Status register to check the speed */
6881 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6865 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6882 &phy_data); 6866 &phy_data);
6883 if(ret_val) 6867 if (ret_val)
6884 return ret_val; 6868 return ret_val;
6885 6869
6886 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 6870 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6887 * find the polarity status */ 6871 * find the polarity status */
6888 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 6872 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6889 IGP01E1000_PSSR_SPEED_1000MBPS) { 6873 IGP01E1000_PSSR_SPEED_1000MBPS) {
6890 6874
6891 /* Read the GIG initialization PCS register (0x00B4) */ 6875 /* Read the GIG initialization PCS register (0x00B4) */
6892 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 6876 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6893 &phy_data); 6877 &phy_data);
6894 if(ret_val) 6878 if (ret_val)
6895 return ret_val; 6879 return ret_val;
6896 6880
6897 /* Check the polarity bits */ 6881 /* Check the polarity bits */
@@ -6940,7 +6924,7 @@ e1000_check_downshift(struct e1000_hw *hw)
6940 hw->phy_type == e1000_phy_igp_2) { 6924 hw->phy_type == e1000_phy_igp_2) {
6941 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6925 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6942 &phy_data); 6926 &phy_data);
6943 if(ret_val) 6927 if (ret_val)
6944 return ret_val; 6928 return ret_val;
6945 6929
6946 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 6930 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
@@ -6948,7 +6932,7 @@ e1000_check_downshift(struct e1000_hw *hw)
6948 (hw->phy_type == e1000_phy_gg82563)) { 6932 (hw->phy_type == e1000_phy_gg82563)) {
6949 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6933 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6950 &phy_data); 6934 &phy_data);
6951 if(ret_val) 6935 if (ret_val)
6952 return ret_val; 6936 return ret_val;
6953 6937
6954 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6938 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
@@ -6988,42 +6972,42 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6988 6972
6989 DEBUGFUNC("e1000_config_dsp_after_link_change"); 6973 DEBUGFUNC("e1000_config_dsp_after_link_change");
6990 6974
6991 if(hw->phy_type != e1000_phy_igp) 6975 if (hw->phy_type != e1000_phy_igp)
6992 return E1000_SUCCESS; 6976 return E1000_SUCCESS;
6993 6977
6994 if(link_up) { 6978 if (link_up) {
6995 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 6979 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6996 if(ret_val) { 6980 if (ret_val) {
6997 DEBUGOUT("Error getting link speed and duplex\n"); 6981 DEBUGOUT("Error getting link speed and duplex\n");
6998 return ret_val; 6982 return ret_val;
6999 } 6983 }
7000 6984
7001 if(speed == SPEED_1000) { 6985 if (speed == SPEED_1000) {
7002 6986
7003 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 6987 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7004 if (ret_val) 6988 if (ret_val)
7005 return ret_val; 6989 return ret_val;
7006 6990
7007 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 6991 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7008 min_length >= e1000_igp_cable_length_50) { 6992 min_length >= e1000_igp_cable_length_50) {
7009 6993
7010 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6994 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7011 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 6995 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7012 &phy_data); 6996 &phy_data);
7013 if(ret_val) 6997 if (ret_val)
7014 return ret_val; 6998 return ret_val;
7015 6999
7016 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7000 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7017 7001
7018 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 7002 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7019 phy_data); 7003 phy_data);
7020 if(ret_val) 7004 if (ret_val)
7021 return ret_val; 7005 return ret_val;
7022 } 7006 }
7023 hw->dsp_config_state = e1000_dsp_config_activated; 7007 hw->dsp_config_state = e1000_dsp_config_activated;
7024 } 7008 }
7025 7009
7026 if((hw->ffe_config_state == e1000_ffe_config_enabled) && 7010 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7027 (min_length < e1000_igp_cable_length_50)) { 7011 (min_length < e1000_igp_cable_length_50)) {
7028 7012
7029 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7013 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
@@ -7032,70 +7016,70 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7032 /* clear previous idle error counts */ 7016 /* clear previous idle error counts */
7033 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7017 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7034 &phy_data); 7018 &phy_data);
7035 if(ret_val) 7019 if (ret_val)
7036 return ret_val; 7020 return ret_val;
7037 7021
7038 for(i = 0; i < ffe_idle_err_timeout; i++) { 7022 for (i = 0; i < ffe_idle_err_timeout; i++) {
7039 udelay(1000); 7023 udelay(1000);
7040 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7024 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7041 &phy_data); 7025 &phy_data);
7042 if(ret_val) 7026 if (ret_val)
7043 return ret_val; 7027 return ret_val;
7044 7028
7045 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 7029 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7046 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7030 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7047 hw->ffe_config_state = e1000_ffe_config_active; 7031 hw->ffe_config_state = e1000_ffe_config_active;
7048 7032
7049 ret_val = e1000_write_phy_reg(hw, 7033 ret_val = e1000_write_phy_reg(hw,
7050 IGP01E1000_PHY_DSP_FFE, 7034 IGP01E1000_PHY_DSP_FFE,
7051 IGP01E1000_PHY_DSP_FFE_CM_CP); 7035 IGP01E1000_PHY_DSP_FFE_CM_CP);
7052 if(ret_val) 7036 if (ret_val)
7053 return ret_val; 7037 return ret_val;
7054 break; 7038 break;
7055 } 7039 }
7056 7040
7057 if(idle_errs) 7041 if (idle_errs)
7058 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7042 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7059 } 7043 }
7060 } 7044 }
7061 } 7045 }
7062 } else { 7046 } else {
7063 if(hw->dsp_config_state == e1000_dsp_config_activated) { 7047 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7064 /* Save off the current value of register 0x2F5B to be restored at 7048 /* Save off the current value of register 0x2F5B to be restored at
7065 * the end of the routines. */ 7049 * the end of the routines. */
7066 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7050 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7067 7051
7068 if(ret_val) 7052 if (ret_val)
7069 return ret_val; 7053 return ret_val;
7070 7054
7071 /* Disable the PHY transmitter */ 7055 /* Disable the PHY transmitter */
7072 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7056 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7073 7057
7074 if(ret_val) 7058 if (ret_val)
7075 return ret_val; 7059 return ret_val;
7076 7060
7077 msec_delay_irq(20); 7061 msec_delay_irq(20);
7078 7062
7079 ret_val = e1000_write_phy_reg(hw, 0x0000, 7063 ret_val = e1000_write_phy_reg(hw, 0x0000,
7080 IGP01E1000_IEEE_FORCE_GIGA); 7064 IGP01E1000_IEEE_FORCE_GIGA);
7081 if(ret_val) 7065 if (ret_val)
7082 return ret_val; 7066 return ret_val;
7083 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7067 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7084 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); 7068 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7085 if(ret_val) 7069 if (ret_val)
7086 return ret_val; 7070 return ret_val;
7087 7071
7088 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7072 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7089 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7073 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7090 7074
7091 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); 7075 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7092 if(ret_val) 7076 if (ret_val)
7093 return ret_val; 7077 return ret_val;
7094 } 7078 }
7095 7079
7096 ret_val = e1000_write_phy_reg(hw, 0x0000, 7080 ret_val = e1000_write_phy_reg(hw, 0x0000,
7097 IGP01E1000_IEEE_RESTART_AUTONEG); 7081 IGP01E1000_IEEE_RESTART_AUTONEG);
7098 if(ret_val) 7082 if (ret_val)
7099 return ret_val; 7083 return ret_val;
7100 7084
7101 msec_delay_irq(20); 7085 msec_delay_irq(20);
@@ -7103,40 +7087,40 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7103 /* Now enable the transmitter */ 7087 /* Now enable the transmitter */
7104 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7088 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7105 7089
7106 if(ret_val) 7090 if (ret_val)
7107 return ret_val; 7091 return ret_val;
7108 7092
7109 hw->dsp_config_state = e1000_dsp_config_enabled; 7093 hw->dsp_config_state = e1000_dsp_config_enabled;
7110 } 7094 }
7111 7095
7112 if(hw->ffe_config_state == e1000_ffe_config_active) { 7096 if (hw->ffe_config_state == e1000_ffe_config_active) {
7113 /* Save off the current value of register 0x2F5B to be restored at 7097 /* Save off the current value of register 0x2F5B to be restored at
7114 * the end of the routines. */ 7098 * the end of the routines. */
7115 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7099 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7116 7100
7117 if(ret_val) 7101 if (ret_val)
7118 return ret_val; 7102 return ret_val;
7119 7103
7120 /* Disable the PHY transmitter */ 7104 /* Disable the PHY transmitter */
7121 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7105 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7122 7106
7123 if(ret_val) 7107 if (ret_val)
7124 return ret_val; 7108 return ret_val;
7125 7109
7126 msec_delay_irq(20); 7110 msec_delay_irq(20);
7127 7111
7128 ret_val = e1000_write_phy_reg(hw, 0x0000, 7112 ret_val = e1000_write_phy_reg(hw, 0x0000,
7129 IGP01E1000_IEEE_FORCE_GIGA); 7113 IGP01E1000_IEEE_FORCE_GIGA);
7130 if(ret_val) 7114 if (ret_val)
7131 return ret_val; 7115 return ret_val;
7132 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 7116 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7133 IGP01E1000_PHY_DSP_FFE_DEFAULT); 7117 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7134 if(ret_val) 7118 if (ret_val)
7135 return ret_val; 7119 return ret_val;
7136 7120
7137 ret_val = e1000_write_phy_reg(hw, 0x0000, 7121 ret_val = e1000_write_phy_reg(hw, 0x0000,
7138 IGP01E1000_IEEE_RESTART_AUTONEG); 7122 IGP01E1000_IEEE_RESTART_AUTONEG);
7139 if(ret_val) 7123 if (ret_val)
7140 return ret_val; 7124 return ret_val;
7141 7125
7142 msec_delay_irq(20); 7126 msec_delay_irq(20);
@@ -7144,7 +7128,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7144 /* Now enable the transmitter */ 7128 /* Now enable the transmitter */
7145 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7129 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7146 7130
7147 if(ret_val) 7131 if (ret_val)
7148 return ret_val; 7132 return ret_val;
7149 7133
7150 hw->ffe_config_state = e1000_ffe_config_enabled; 7134 hw->ffe_config_state = e1000_ffe_config_enabled;
@@ -7169,20 +7153,20 @@ e1000_set_phy_mode(struct e1000_hw *hw)
7169 7153
7170 DEBUGFUNC("e1000_set_phy_mode"); 7154 DEBUGFUNC("e1000_set_phy_mode");
7171 7155
7172 if((hw->mac_type == e1000_82545_rev_3) && 7156 if ((hw->mac_type == e1000_82545_rev_3) &&
7173 (hw->media_type == e1000_media_type_copper)) { 7157 (hw->media_type == e1000_media_type_copper)) {
7174 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); 7158 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7175 if(ret_val) { 7159 if (ret_val) {
7176 return ret_val; 7160 return ret_val;
7177 } 7161 }
7178 7162
7179 if((eeprom_data != EEPROM_RESERVED_WORD) && 7163 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7180 (eeprom_data & EEPROM_PHY_CLASS_A)) { 7164 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7181 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); 7165 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7182 if(ret_val) 7166 if (ret_val)
7183 return ret_val; 7167 return ret_val;
7184 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); 7168 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7185 if(ret_val) 7169 if (ret_val)
7186 return ret_val; 7170 return ret_val;
7187 7171
7188 hw->phy_reset_disable = FALSE; 7172 hw->phy_reset_disable = FALSE;
@@ -7233,16 +7217,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7233 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7217 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7234 } else { 7218 } else {
7235 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7219 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7236 if(ret_val) 7220 if (ret_val)
7237 return ret_val; 7221 return ret_val;
7238 } 7222 }
7239 7223
7240 if(!active) { 7224 if (!active) {
7241 if(hw->mac_type == e1000_82541_rev_2 || 7225 if (hw->mac_type == e1000_82541_rev_2 ||
7242 hw->mac_type == e1000_82547_rev_2) { 7226 hw->mac_type == e1000_82547_rev_2) {
7243 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 7227 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7244 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7228 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7245 if(ret_val) 7229 if (ret_val)
7246 return ret_val; 7230 return ret_val;
7247 } else { 7231 } else {
7248 if (hw->mac_type == e1000_ich8lan) { 7232 if (hw->mac_type == e1000_ich8lan) {
@@ -7264,13 +7248,13 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7264 if (hw->smart_speed == e1000_smart_speed_on) { 7248 if (hw->smart_speed == e1000_smart_speed_on) {
7265 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7249 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7266 &phy_data); 7250 &phy_data);
7267 if(ret_val) 7251 if (ret_val)
7268 return ret_val; 7252 return ret_val;
7269 7253
7270 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7254 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7271 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7255 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7272 phy_data); 7256 phy_data);
7273 if(ret_val) 7257 if (ret_val)
7274 return ret_val; 7258 return ret_val;
7275 } else if (hw->smart_speed == e1000_smart_speed_off) { 7259 } else if (hw->smart_speed == e1000_smart_speed_off) {
7276 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7260 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7281,19 +7265,19 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7281 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7265 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7282 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7266 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7283 phy_data); 7267 phy_data);
7284 if(ret_val) 7268 if (ret_val)
7285 return ret_val; 7269 return ret_val;
7286 } 7270 }
7287 7271
7288 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || 7272 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7289 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 7273 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7290 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7274 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7291 7275
7292 if(hw->mac_type == e1000_82541_rev_2 || 7276 if (hw->mac_type == e1000_82541_rev_2 ||
7293 hw->mac_type == e1000_82547_rev_2) { 7277 hw->mac_type == e1000_82547_rev_2) {
7294 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7278 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7295 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7279 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7296 if(ret_val) 7280 if (ret_val)
7297 return ret_val; 7281 return ret_val;
7298 } else { 7282 } else {
7299 if (hw->mac_type == e1000_ich8lan) { 7283 if (hw->mac_type == e1000_ich8lan) {
@@ -7310,12 +7294,12 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7310 7294
7311 /* When LPLU is enabled we should disable SmartSpeed */ 7295 /* When LPLU is enabled we should disable SmartSpeed */
7312 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7296 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7313 if(ret_val) 7297 if (ret_val)
7314 return ret_val; 7298 return ret_val;
7315 7299
7316 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7300 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7317 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7301 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7318 if(ret_val) 7302 if (ret_val)
7319 return ret_val; 7303 return ret_val;
7320 7304
7321 } 7305 }
@@ -7345,14 +7329,14 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7345 uint16_t phy_data; 7329 uint16_t phy_data;
7346 DEBUGFUNC("e1000_set_d0_lplu_state"); 7330 DEBUGFUNC("e1000_set_d0_lplu_state");
7347 7331
7348 if(hw->mac_type <= e1000_82547_rev_2) 7332 if (hw->mac_type <= e1000_82547_rev_2)
7349 return E1000_SUCCESS; 7333 return E1000_SUCCESS;
7350 7334
7351 if (hw->mac_type == e1000_ich8lan) { 7335 if (hw->mac_type == e1000_ich8lan) {
7352 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7336 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7353 } else { 7337 } else {
7354 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7338 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7355 if(ret_val) 7339 if (ret_val)
7356 return ret_val; 7340 return ret_val;
7357 } 7341 }
7358 7342
@@ -7374,13 +7358,13 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7374 if (hw->smart_speed == e1000_smart_speed_on) { 7358 if (hw->smart_speed == e1000_smart_speed_on) {
7375 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7359 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7376 &phy_data); 7360 &phy_data);
7377 if(ret_val) 7361 if (ret_val)
7378 return ret_val; 7362 return ret_val;
7379 7363
7380 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7364 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7381 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7365 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7382 phy_data); 7366 phy_data);
7383 if(ret_val) 7367 if (ret_val)
7384 return ret_val; 7368 return ret_val;
7385 } else if (hw->smart_speed == e1000_smart_speed_off) { 7369 } else if (hw->smart_speed == e1000_smart_speed_off) {
7386 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7370 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7391,7 +7375,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7391 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7375 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7392 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7376 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7393 phy_data); 7377 phy_data);
7394 if(ret_val) 7378 if (ret_val)
7395 return ret_val; 7379 return ret_val;
7396 } 7380 }
7397 7381
@@ -7410,12 +7394,12 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7410 7394
7411 /* When LPLU is enabled we should disable SmartSpeed */ 7395 /* When LPLU is enabled we should disable SmartSpeed */
7412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7396 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7413 if(ret_val) 7397 if (ret_val)
7414 return ret_val; 7398 return ret_val;
7415 7399
7416 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7400 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7417 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7401 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7418 if(ret_val) 7402 if (ret_val)
7419 return ret_val; 7403 return ret_val;
7420 7404
7421 } 7405 }
@@ -7436,7 +7420,7 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7436 7420
7437 DEBUGFUNC("e1000_set_vco_speed"); 7421 DEBUGFUNC("e1000_set_vco_speed");
7438 7422
7439 switch(hw->mac_type) { 7423 switch (hw->mac_type) {
7440 case e1000_82545_rev_3: 7424 case e1000_82545_rev_3:
7441 case e1000_82546_rev_3: 7425 case e1000_82546_rev_3:
7442 break; 7426 break;
@@ -7447,39 +7431,39 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7447 /* Set PHY register 30, page 5, bit 8 to 0 */ 7431 /* Set PHY register 30, page 5, bit 8 to 0 */
7448 7432
7449 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 7433 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7450 if(ret_val) 7434 if (ret_val)
7451 return ret_val; 7435 return ret_val;
7452 7436
7453 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 7437 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7454 if(ret_val) 7438 if (ret_val)
7455 return ret_val; 7439 return ret_val;
7456 7440
7457 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7441 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7458 if(ret_val) 7442 if (ret_val)
7459 return ret_val; 7443 return ret_val;
7460 7444
7461 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 7445 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7462 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7446 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7463 if(ret_val) 7447 if (ret_val)
7464 return ret_val; 7448 return ret_val;
7465 7449
7466 /* Set PHY register 30, page 4, bit 11 to 1 */ 7450 /* Set PHY register 30, page 4, bit 11 to 1 */
7467 7451
7468 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 7452 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7469 if(ret_val) 7453 if (ret_val)
7470 return ret_val; 7454 return ret_val;
7471 7455
7472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7456 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7473 if(ret_val) 7457 if (ret_val)
7474 return ret_val; 7458 return ret_val;
7475 7459
7476 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 7460 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7477 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7461 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7478 if(ret_val) 7462 if (ret_val)
7479 return ret_val; 7463 return ret_val;
7480 7464
7481 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 7465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7482 if(ret_val) 7466 if (ret_val)
7483 return ret_val; 7467 return ret_val;
7484 7468
7485 return E1000_SUCCESS; 7469 return E1000_SUCCESS;
@@ -7558,7 +7542,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7558{ 7542{
7559 uint8_t *tmp; 7543 uint8_t *tmp;
7560 uint8_t *bufptr = buffer; 7544 uint8_t *bufptr = buffer;
7561 uint32_t data; 7545 uint32_t data = 0;
7562 uint16_t remaining, i, j, prev_bytes; 7546 uint16_t remaining, i, j, prev_bytes;
7563 7547
7564 /* sum = only sum of the data and it is not checksum */ 7548 /* sum = only sum of the data and it is not checksum */
@@ -7638,7 +7622,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7638 7622
7639 buffer = (uint8_t *) hdr; 7623 buffer = (uint8_t *) hdr;
7640 i = length; 7624 i = length;
7641 while(i--) 7625 while (i--)
7642 sum += buffer[i]; 7626 sum += buffer[i];
7643 7627
7644 hdr->checksum = 0 - sum; 7628 hdr->checksum = 0 - sum;
@@ -7661,8 +7645,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7661 * returns - E1000_SUCCESS for success. 7645 * returns - E1000_SUCCESS for success.
7662 ****************************************************************************/ 7646 ****************************************************************************/
7663static int32_t 7647static int32_t
7664e1000_mng_write_commit( 7648e1000_mng_write_commit(struct e1000_hw * hw)
7665 struct e1000_hw * hw)
7666{ 7649{
7667 uint32_t hicr; 7650 uint32_t hicr;
7668 7651
@@ -7834,31 +7817,31 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7834 /* Disable the transmitter on the PHY */ 7817 /* Disable the transmitter on the PHY */
7835 7818
7836 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7819 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7837 if(ret_val) 7820 if (ret_val)
7838 return ret_val; 7821 return ret_val;
7839 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 7822 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7840 if(ret_val) 7823 if (ret_val)
7841 return ret_val; 7824 return ret_val;
7842 7825
7843 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7826 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7844 if(ret_val) 7827 if (ret_val)
7845 return ret_val; 7828 return ret_val;
7846 7829
7847 /* This loop will early-out if the NO link condition has been met. */ 7830 /* This loop will early-out if the NO link condition has been met. */
7848 for(i = PHY_FORCE_TIME; i > 0; i--) { 7831 for (i = PHY_FORCE_TIME; i > 0; i--) {
7849 /* Read the MII Status Register and wait for Link Status bit 7832 /* Read the MII Status Register and wait for Link Status bit
7850 * to be clear. 7833 * to be clear.
7851 */ 7834 */
7852 7835
7853 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7836 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7854 if(ret_val) 7837 if (ret_val)
7855 return ret_val; 7838 return ret_val;
7856 7839
7857 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7858 if(ret_val) 7841 if (ret_val)
7859 return ret_val; 7842 return ret_val;
7860 7843
7861 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; 7844 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7862 msec_delay_irq(100); 7845 msec_delay_irq(100);
7863 } 7846 }
7864 7847
@@ -7868,40 +7851,40 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7868 /* Now we will re-enable th transmitter on the PHY */ 7851 /* Now we will re-enable th transmitter on the PHY */
7869 7852
7870 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7853 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7871 if(ret_val) 7854 if (ret_val)
7872 return ret_val; 7855 return ret_val;
7873 msec_delay_irq(50); 7856 msec_delay_irq(50);
7874 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 7857 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7875 if(ret_val) 7858 if (ret_val)
7876 return ret_val; 7859 return ret_val;
7877 msec_delay_irq(50); 7860 msec_delay_irq(50);
7878 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 7861 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7879 if(ret_val) 7862 if (ret_val)
7880 return ret_val; 7863 return ret_val;
7881 msec_delay_irq(50); 7864 msec_delay_irq(50);
7882 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 7865 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7883 if(ret_val) 7866 if (ret_val)
7884 return ret_val; 7867 return ret_val;
7885 7868
7886 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7869 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7887 if(ret_val) 7870 if (ret_val)
7888 return ret_val; 7871 return ret_val;
7889 7872
7890 /* This loop will early-out if the link condition has been met. */ 7873 /* This loop will early-out if the link condition has been met. */
7891 for(i = PHY_FORCE_TIME; i > 0; i--) { 7874 for (i = PHY_FORCE_TIME; i > 0; i--) {
7892 /* Read the MII Status Register and wait for Link Status bit 7875 /* Read the MII Status Register and wait for Link Status bit
7893 * to be set. 7876 * to be set.
7894 */ 7877 */
7895 7878
7896 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7879 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7897 if(ret_val) 7880 if (ret_val)
7898 return ret_val; 7881 return ret_val;
7899 7882
7900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7901 if(ret_val) 7884 if (ret_val)
7902 return ret_val; 7885 return ret_val;
7903 7886
7904 if(mii_status_reg & MII_SR_LINK_STATUS) break; 7887 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7905 msec_delay_irq(100); 7888 msec_delay_irq(100);
7906 } 7889 }
7907 return E1000_SUCCESS; 7890 return E1000_SUCCESS;
@@ -7980,15 +7963,15 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
7980 7963
7981 e1000_set_pci_express_master_disable(hw); 7964 e1000_set_pci_express_master_disable(hw);
7982 7965
7983 while(timeout) { 7966 while (timeout) {
7984 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 7967 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7985 break; 7968 break;
7986 else 7969 else
7987 udelay(100); 7970 udelay(100);
7988 timeout--; 7971 timeout--;
7989 } 7972 }
7990 7973
7991 if(!timeout) { 7974 if (!timeout) {
7992 DEBUGOUT("Master requests are pending.\n"); 7975 DEBUGOUT("Master requests are pending.\n");
7993 return -E1000_ERR_MASTER_REQUESTS_PENDING; 7976 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7994 } 7977 }
@@ -8029,7 +8012,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8029 timeout--; 8012 timeout--;
8030 } 8013 }
8031 8014
8032 if(!timeout) { 8015 if (!timeout) {
8033 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); 8016 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8034 return -E1000_ERR_RESET; 8017 return -E1000_ERR_RESET;
8035 } 8018 }
@@ -8110,7 +8093,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8110 8093
8111 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); 8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8112 8095
8113 if(!hw->eeprom_semaphore_present) 8096 if (!hw->eeprom_semaphore_present)
8114 return E1000_SUCCESS; 8097 return E1000_SUCCESS;
8115 8098
8116 if (hw->mac_type == e1000_80003es2lan) { 8099 if (hw->mac_type == e1000_80003es2lan) {
@@ -8121,20 +8104,20 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8121 8104
8122 /* Get the FW semaphore. */ 8105 /* Get the FW semaphore. */
8123 timeout = hw->eeprom.word_size + 1; 8106 timeout = hw->eeprom.word_size + 1;
8124 while(timeout) { 8107 while (timeout) {
8125 swsm = E1000_READ_REG(hw, SWSM); 8108 swsm = E1000_READ_REG(hw, SWSM);
8126 swsm |= E1000_SWSM_SWESMBI; 8109 swsm |= E1000_SWSM_SWESMBI;
8127 E1000_WRITE_REG(hw, SWSM, swsm); 8110 E1000_WRITE_REG(hw, SWSM, swsm);
8128 /* if we managed to set the bit we got the semaphore. */ 8111 /* if we managed to set the bit we got the semaphore. */
8129 swsm = E1000_READ_REG(hw, SWSM); 8112 swsm = E1000_READ_REG(hw, SWSM);
8130 if(swsm & E1000_SWSM_SWESMBI) 8113 if (swsm & E1000_SWSM_SWESMBI)
8131 break; 8114 break;
8132 8115
8133 udelay(50); 8116 udelay(50);
8134 timeout--; 8117 timeout--;
8135 } 8118 }
8136 8119
8137 if(!timeout) { 8120 if (!timeout) {
8138 /* Release semaphores */ 8121 /* Release semaphores */
8139 e1000_put_hw_eeprom_semaphore(hw); 8122 e1000_put_hw_eeprom_semaphore(hw);
8140 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); 8123 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
@@ -8159,7 +8142,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8159 8142
8160 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); 8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8161 8144
8162 if(!hw->eeprom_semaphore_present) 8145 if (!hw->eeprom_semaphore_present)
8163 return; 8146 return;
8164 8147
8165 swsm = E1000_READ_REG(hw, SWSM); 8148 swsm = E1000_READ_REG(hw, SWSM);
@@ -8192,16 +8175,16 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8192 if (hw->mac_type != e1000_80003es2lan) 8175 if (hw->mac_type != e1000_80003es2lan)
8193 return E1000_SUCCESS; 8176 return E1000_SUCCESS;
8194 8177
8195 while(timeout) { 8178 while (timeout) {
8196 swsm = E1000_READ_REG(hw, SWSM); 8179 swsm = E1000_READ_REG(hw, SWSM);
8197 /* If SMBI bit cleared, it is now set and we hold the semaphore */ 8180 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8198 if(!(swsm & E1000_SWSM_SMBI)) 8181 if (!(swsm & E1000_SWSM_SMBI))
8199 break; 8182 break;
8200 msec_delay_irq(1); 8183 msec_delay_irq(1);
8201 timeout--; 8184 timeout--;
8202 } 8185 }
8203 8186
8204 if(!timeout) { 8187 if (!timeout) {
8205 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8188 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8206 return -E1000_ERR_RESET; 8189 return -E1000_ERR_RESET;
8207 } 8190 }
@@ -8277,7 +8260,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
8277 case e1000_82573: 8260 case e1000_82573:
8278 case e1000_80003es2lan: 8261 case e1000_80003es2lan:
8279 fwsm = E1000_READ_REG(hw, FWSM); 8262 fwsm = E1000_READ_REG(hw, FWSM);
8280 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8263 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8281 return TRUE; 8264 return TRUE;
8282 break; 8265 break;
8283 case e1000_ich8lan: 8266 case e1000_ich8lan:
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 375b95518c31..a170e96251f6 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -336,9 +336,9 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
336#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 336#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
337 337
338#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 338#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
341#define E1000_MNG_IAMT_MODE 0x3 341#define E1000_MNG_IAMT_MODE 0x3
342#define E1000_MNG_ICH_IAMT_MODE 0x2 342#define E1000_MNG_ICH_IAMT_MODE 0x2
343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
344 344
@@ -385,7 +385,7 @@ struct e1000_host_mng_dhcp_cookie{
385#endif 385#endif
386 386
387int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, 387int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
388 uint16_t length); 388 uint16_t length);
389boolean_t e1000_check_mng_mode(struct e1000_hw *hw); 389boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
390boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 390boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
391 391
@@ -470,6 +470,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
470#define E1000_DEV_ID_82571EB_COPPER 0x105E 470#define E1000_DEV_ID_82571EB_COPPER 0x105E
471#define E1000_DEV_ID_82571EB_FIBER 0x105F 471#define E1000_DEV_ID_82571EB_FIBER 0x105F
472#define E1000_DEV_ID_82571EB_SERDES 0x1060 472#define E1000_DEV_ID_82571EB_SERDES 0x1060
473#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
473#define E1000_DEV_ID_82572EI_COPPER 0x107D 474#define E1000_DEV_ID_82572EI_COPPER 0x107D
474#define E1000_DEV_ID_82572EI_FIBER 0x107E 475#define E1000_DEV_ID_82572EI_FIBER 0x107E
475#define E1000_DEV_ID_82572EI_SERDES 0x107F 476#define E1000_DEV_ID_82572EI_SERDES 0x107F
@@ -523,7 +524,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
523 524
524 525
525/* 802.1q VLAN Packet Sizes */ 526/* 802.1q VLAN Packet Sizes */
526#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 527#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
527 528
528/* Ethertype field values */ 529/* Ethertype field values */
529#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 530#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
@@ -697,6 +698,7 @@ union e1000_rx_desc_packet_split {
697 E1000_RXDEXT_STATERR_CXE | \ 698 E1000_RXDEXT_STATERR_CXE | \
698 E1000_RXDEXT_STATERR_RXE) 699 E1000_RXDEXT_STATERR_RXE)
699 700
701
700/* Transmit Descriptor */ 702/* Transmit Descriptor */
701struct e1000_tx_desc { 703struct e1000_tx_desc {
702 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 704 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
@@ -2086,7 +2088,7 @@ struct e1000_hw {
2086#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2088#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2087 * filtering */ 2089 * filtering */
2088#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2090#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2089#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2091#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2090#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2092#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2091#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2093#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2092#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2094#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
@@ -2172,7 +2174,7 @@ struct e1000_host_command_info {
2172 2174
2173#define E1000_MDALIGN 4096 2175#define E1000_MDALIGN 4096
2174 2176
2175/* PCI-Ex registers */ 2177/* PCI-Ex registers*/
2176 2178
2177/* PCI-Ex Control Register */ 2179/* PCI-Ex Control Register */
2178#define E1000_GCR_RXD_NO_SNOOP 0x00000001 2180#define E1000_GCR_RXD_NO_SNOOP 0x00000001
@@ -2224,7 +2226,7 @@ struct e1000_host_command_info {
2224#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 2226#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2225 2227
2226/* EEPROM Commands - SPI */ 2228/* EEPROM Commands - SPI */
2227#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2229#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2228#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2230#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2229#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2231#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2230#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2232#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
@@ -3082,10 +3084,10 @@ struct e1000_host_command_info {
3082 3084
3083/* DSP Distance Register (Page 5, Register 26) */ 3085/* DSP Distance Register (Page 5, Register 26) */
3084#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; 3086#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
3085 1 = 50-80M; 3087 1 = 50-80M;
3086 2 = 80-110M; 3088 2 = 80-110M;
3087 3 = 110-140M; 3089 3 = 110-140M;
3088 4 = >140M */ 3090 4 = >140M */
3089 3091
3090/* Kumeran Mode Control Register (Page 193, Register 16) */ 3092/* Kumeran Mode Control Register (Page 193, Register 16) */
3091#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ 3093#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 726f43d55937..1d7c99947e92 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -36,7 +36,7 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
36#else 36#else
37#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
38#endif 38#endif
39#define DRV_VERSION "7.1.9-k4"DRIVERNAPI 39#define DRV_VERSION "7.2.7-k2"DRIVERNAPI
40char e1000_driver_version[] = DRV_VERSION; 40char e1000_driver_version[] = DRV_VERSION;
41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
42 42
@@ -48,7 +48,6 @@ static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)} 48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */ 49 */
50static struct pci_device_id e1000_pci_tbl[] = { 50static struct pci_device_id e1000_pci_tbl[] = {
51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
52 INTEL_E1000_ETHERNET_DEVICE(0x1001), 51 INTEL_E1000_ETHERNET_DEVICE(0x1001),
53 INTEL_E1000_ETHERNET_DEVICE(0x1004), 52 INTEL_E1000_ETHERNET_DEVICE(0x1004),
54 INTEL_E1000_ETHERNET_DEVICE(0x1008), 53 INTEL_E1000_ETHERNET_DEVICE(0x1008),
@@ -99,6 +98,7 @@ static struct pci_device_id e1000_pci_tbl[] = {
99 INTEL_E1000_ETHERNET_DEVICE(0x1098), 98 INTEL_E1000_ETHERNET_DEVICE(0x1098),
100 INTEL_E1000_ETHERNET_DEVICE(0x1099), 99 INTEL_E1000_ETHERNET_DEVICE(0x1099),
101 INTEL_E1000_ETHERNET_DEVICE(0x109A), 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
101 INTEL_E1000_ETHERNET_DEVICE(0x10A4),
102 INTEL_E1000_ETHERNET_DEVICE(0x10B5), 102 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
103 INTEL_E1000_ETHERNET_DEVICE(0x10B9), 103 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BA), 104 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
@@ -245,7 +245,7 @@ e1000_init_module(void)
245 245
246 printk(KERN_INFO "%s\n", e1000_copyright); 246 printk(KERN_INFO "%s\n", e1000_copyright);
247 247
248 ret = pci_module_init(&e1000_driver); 248 ret = pci_register_driver(&e1000_driver);
249 249
250 return ret; 250 return ret;
251} 251}
@@ -485,7 +485,7 @@ e1000_up(struct e1000_adapter *adapter)
485 * 485 *
486 **/ 486 **/
487 487
488static void e1000_power_up_phy(struct e1000_adapter *adapter) 488void e1000_power_up_phy(struct e1000_adapter *adapter)
489{ 489{
490 uint16_t mii_reg = 0; 490 uint16_t mii_reg = 0;
491 491
@@ -682,9 +682,9 @@ e1000_probe(struct pci_dev *pdev,
682 unsigned long flash_start, flash_len; 682 unsigned long flash_start, flash_len;
683 683
684 static int cards_found = 0; 684 static int cards_found = 0;
685 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */ 685 static int global_quad_port_a = 0; /* global ksp3 port a indication */
686 int i, err, pci_using_dac; 686 int i, err, pci_using_dac;
687 uint16_t eeprom_data; 687 uint16_t eeprom_data = 0;
688 uint16_t eeprom_apme_mask = E1000_EEPROM_APME; 688 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
689 if ((err = pci_enable_device(pdev))) 689 if ((err = pci_enable_device(pdev)))
690 return err; 690 return err;
@@ -696,21 +696,20 @@ e1000_probe(struct pci_dev *pdev,
696 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) && 696 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
697 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { 697 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
698 E1000_ERR("No usable DMA configuration, aborting\n"); 698 E1000_ERR("No usable DMA configuration, aborting\n");
699 return err; 699 goto err_dma;
700 } 700 }
701 pci_using_dac = 0; 701 pci_using_dac = 0;
702 } 702 }
703 703
704 if ((err = pci_request_regions(pdev, e1000_driver_name))) 704 if ((err = pci_request_regions(pdev, e1000_driver_name)))
705 return err; 705 goto err_pci_reg;
706 706
707 pci_set_master(pdev); 707 pci_set_master(pdev);
708 708
709 err = -ENOMEM;
709 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 710 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
710 if (!netdev) { 711 if (!netdev)
711 err = -ENOMEM;
712 goto err_alloc_etherdev; 712 goto err_alloc_etherdev;
713 }
714 713
715 SET_MODULE_OWNER(netdev); 714 SET_MODULE_OWNER(netdev);
716 SET_NETDEV_DEV(netdev, &pdev->dev); 715 SET_NETDEV_DEV(netdev, &pdev->dev);
@@ -725,11 +724,10 @@ e1000_probe(struct pci_dev *pdev,
725 mmio_start = pci_resource_start(pdev, BAR_0); 724 mmio_start = pci_resource_start(pdev, BAR_0);
726 mmio_len = pci_resource_len(pdev, BAR_0); 725 mmio_len = pci_resource_len(pdev, BAR_0);
727 726
727 err = -EIO;
728 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 728 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
729 if (!adapter->hw.hw_addr) { 729 if (!adapter->hw.hw_addr)
730 err = -EIO;
731 goto err_ioremap; 730 goto err_ioremap;
732 }
733 731
734 for (i = BAR_1; i <= BAR_5; i++) { 732 for (i = BAR_1; i <= BAR_5; i++) {
735 if (pci_resource_len(pdev, i) == 0) 733 if (pci_resource_len(pdev, i) == 0)
@@ -774,6 +772,7 @@ e1000_probe(struct pci_dev *pdev,
774 if ((err = e1000_sw_init(adapter))) 772 if ((err = e1000_sw_init(adapter)))
775 goto err_sw_init; 773 goto err_sw_init;
776 774
775 err = -EIO;
777 /* Flash BAR mapping must happen after e1000_sw_init 776 /* Flash BAR mapping must happen after e1000_sw_init
778 * because it depends on mac_type */ 777 * because it depends on mac_type */
779 if ((adapter->hw.mac_type == e1000_ich8lan) && 778 if ((adapter->hw.mac_type == e1000_ich8lan) &&
@@ -781,24 +780,13 @@ e1000_probe(struct pci_dev *pdev,
781 flash_start = pci_resource_start(pdev, 1); 780 flash_start = pci_resource_start(pdev, 1);
782 flash_len = pci_resource_len(pdev, 1); 781 flash_len = pci_resource_len(pdev, 1);
783 adapter->hw.flash_address = ioremap(flash_start, flash_len); 782 adapter->hw.flash_address = ioremap(flash_start, flash_len);
784 if (!adapter->hw.flash_address) { 783 if (!adapter->hw.flash_address)
785 err = -EIO;
786 goto err_flashmap; 784 goto err_flashmap;
787 }
788 } 785 }
789 786
790 if ((err = e1000_check_phy_reset_block(&adapter->hw))) 787 if (e1000_check_phy_reset_block(&adapter->hw))
791 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); 788 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
792 789
793 /* if ksp3, indicate if it's port a being setup */
794 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
795 e1000_ksp3_port_a == 0)
796 adapter->ksp3_port_a = 1;
797 e1000_ksp3_port_a++;
798 /* Reset for multiple KP3 adapters */
799 if (e1000_ksp3_port_a == 4)
800 e1000_ksp3_port_a = 0;
801
802 if (adapter->hw.mac_type >= e1000_82543) { 790 if (adapter->hw.mac_type >= e1000_82543) {
803 netdev->features = NETIF_F_SG | 791 netdev->features = NETIF_F_SG |
804 NETIF_F_HW_CSUM | 792 NETIF_F_HW_CSUM |
@@ -830,7 +818,7 @@ e1000_probe(struct pci_dev *pdev,
830 818
831 if (e1000_init_eeprom_params(&adapter->hw)) { 819 if (e1000_init_eeprom_params(&adapter->hw)) {
832 E1000_ERR("EEPROM initialization failed\n"); 820 E1000_ERR("EEPROM initialization failed\n");
833 return -EIO; 821 goto err_eeprom;
834 } 822 }
835 823
836 /* before reading the EEPROM, reset the controller to 824 /* before reading the EEPROM, reset the controller to
@@ -842,7 +830,6 @@ e1000_probe(struct pci_dev *pdev,
842 830
843 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) { 831 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
844 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n"); 832 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
845 err = -EIO;
846 goto err_eeprom; 833 goto err_eeprom;
847 } 834 }
848 835
@@ -855,12 +842,9 @@ e1000_probe(struct pci_dev *pdev,
855 842
856 if (!is_valid_ether_addr(netdev->perm_addr)) { 843 if (!is_valid_ether_addr(netdev->perm_addr)) {
857 DPRINTK(PROBE, ERR, "Invalid MAC Address\n"); 844 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
858 err = -EIO;
859 goto err_eeprom; 845 goto err_eeprom;
860 } 846 }
861 847
862 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
863
864 e1000_get_bus_info(&adapter->hw); 848 e1000_get_bus_info(&adapter->hw);
865 849
866 init_timer(&adapter->tx_fifo_stall_timer); 850 init_timer(&adapter->tx_fifo_stall_timer);
@@ -921,7 +905,38 @@ e1000_probe(struct pci_dev *pdev,
921 break; 905 break;
922 } 906 }
923 if (eeprom_data & eeprom_apme_mask) 907 if (eeprom_data & eeprom_apme_mask)
924 adapter->wol |= E1000_WUFC_MAG; 908 adapter->eeprom_wol |= E1000_WUFC_MAG;
909
910 /* now that we have the eeprom settings, apply the special cases
911 * where the eeprom may be wrong or the board simply won't support
912 * wake on lan on a particular port */
913 switch (pdev->device) {
914 case E1000_DEV_ID_82546GB_PCIE:
915 adapter->eeprom_wol = 0;
916 break;
917 case E1000_DEV_ID_82546EB_FIBER:
918 case E1000_DEV_ID_82546GB_FIBER:
919 case E1000_DEV_ID_82571EB_FIBER:
920 /* Wake events only supported on port A for dual fiber
921 * regardless of eeprom setting */
922 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
923 adapter->eeprom_wol = 0;
924 break;
925 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
926 case E1000_DEV_ID_82571EB_QUAD_COPPER:
927 /* if quad port adapter, disable WoL on all but port A */
928 if (global_quad_port_a != 0)
929 adapter->eeprom_wol = 0;
930 else
931 adapter->quad_port_a = 1;
932 /* Reset for multiple quad port adapters */
933 if (++global_quad_port_a == 4)
934 global_quad_port_a = 0;
935 break;
936 }
937
938 /* initialize the wol settings based on the eeprom settings */
939 adapter->wol = adapter->eeprom_wol;
925 940
926 /* print bus type/speed/width info */ 941 /* print bus type/speed/width info */
927 { 942 {
@@ -964,16 +979,33 @@ e1000_probe(struct pci_dev *pdev,
964 return 0; 979 return 0;
965 980
966err_register: 981err_register:
982 e1000_release_hw_control(adapter);
983err_eeprom:
984 if (!e1000_check_phy_reset_block(&adapter->hw))
985 e1000_phy_hw_reset(&adapter->hw);
986
967 if (adapter->hw.flash_address) 987 if (adapter->hw.flash_address)
968 iounmap(adapter->hw.flash_address); 988 iounmap(adapter->hw.flash_address);
969err_flashmap: 989err_flashmap:
990#ifdef CONFIG_E1000_NAPI
991 for (i = 0; i < adapter->num_rx_queues; i++)
992 dev_put(&adapter->polling_netdev[i]);
993#endif
994
995 kfree(adapter->tx_ring);
996 kfree(adapter->rx_ring);
997#ifdef CONFIG_E1000_NAPI
998 kfree(adapter->polling_netdev);
999#endif
970err_sw_init: 1000err_sw_init:
971err_eeprom:
972 iounmap(adapter->hw.hw_addr); 1001 iounmap(adapter->hw.hw_addr);
973err_ioremap: 1002err_ioremap:
974 free_netdev(netdev); 1003 free_netdev(netdev);
975err_alloc_etherdev: 1004err_alloc_etherdev:
976 pci_release_regions(pdev); 1005 pci_release_regions(pdev);
1006err_pci_reg:
1007err_dma:
1008 pci_disable_device(pdev);
977 return err; 1009 return err;
978} 1010}
979 1011
@@ -1208,7 +1240,7 @@ e1000_open(struct net_device *netdev)
1208 1240
1209 err = e1000_request_irq(adapter); 1241 err = e1000_request_irq(adapter);
1210 if (err) 1242 if (err)
1211 goto err_up; 1243 goto err_req_irq;
1212 1244
1213 e1000_power_up_phy(adapter); 1245 e1000_power_up_phy(adapter);
1214 1246
@@ -1229,6 +1261,9 @@ e1000_open(struct net_device *netdev)
1229 return E1000_SUCCESS; 1261 return E1000_SUCCESS;
1230 1262
1231err_up: 1263err_up:
1264 e1000_power_down_phy(adapter);
1265 e1000_free_irq(adapter);
1266err_req_irq:
1232 e1000_free_all_rx_resources(adapter); 1267 e1000_free_all_rx_resources(adapter);
1233err_setup_rx: 1268err_setup_rx:
1234 e1000_free_all_tx_resources(adapter); 1269 e1000_free_all_tx_resources(adapter);
@@ -1381,10 +1416,6 @@ setup_tx_desc_die:
1381 * (Descriptors) for all queues 1416 * (Descriptors) for all queues
1382 * @adapter: board private structure 1417 * @adapter: board private structure
1383 * 1418 *
1384 * If this function returns with an error, then it's possible one or
1385 * more of the rings is populated (while the rest are not). It is the
1386 * callers duty to clean those orphaned rings.
1387 *
1388 * Return 0 on success, negative on failure 1419 * Return 0 on success, negative on failure
1389 **/ 1420 **/
1390 1421
@@ -1398,6 +1429,9 @@ e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1398 if (err) { 1429 if (err) {
1399 DPRINTK(PROBE, ERR, 1430 DPRINTK(PROBE, ERR,
1400 "Allocation for Tx Queue %u failed\n", i); 1431 "Allocation for Tx Queue %u failed\n", i);
1432 for (i-- ; i >= 0; i--)
1433 e1000_free_tx_resources(adapter,
1434 &adapter->tx_ring[i]);
1401 break; 1435 break;
1402 } 1436 }
1403 } 1437 }
@@ -1499,8 +1533,6 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1499 } else if (hw->mac_type == e1000_80003es2lan) { 1533 } else if (hw->mac_type == e1000_80003es2lan) {
1500 tarc = E1000_READ_REG(hw, TARC0); 1534 tarc = E1000_READ_REG(hw, TARC0);
1501 tarc |= 1; 1535 tarc |= 1;
1502 if (hw->media_type == e1000_media_type_internal_serdes)
1503 tarc |= (1 << 20);
1504 E1000_WRITE_REG(hw, TARC0, tarc); 1536 E1000_WRITE_REG(hw, TARC0, tarc);
1505 tarc = E1000_READ_REG(hw, TARC1); 1537 tarc = E1000_READ_REG(hw, TARC1);
1506 tarc |= 1; 1538 tarc |= 1;
@@ -1639,10 +1671,6 @@ setup_rx_desc_die:
1639 * (Descriptors) for all queues 1671 * (Descriptors) for all queues
1640 * @adapter: board private structure 1672 * @adapter: board private structure
1641 * 1673 *
1642 * If this function returns with an error, then it's possible one or
1643 * more of the rings is populated (while the rest are not). It is the
1644 * callers duty to clean those orphaned rings.
1645 *
1646 * Return 0 on success, negative on failure 1674 * Return 0 on success, negative on failure
1647 **/ 1675 **/
1648 1676
@@ -1656,6 +1684,9 @@ e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1656 if (err) { 1684 if (err) {
1657 DPRINTK(PROBE, ERR, 1685 DPRINTK(PROBE, ERR,
1658 "Allocation for Rx Queue %u failed\n", i); 1686 "Allocation for Rx Queue %u failed\n", i);
1687 for (i-- ; i >= 0; i--)
1688 e1000_free_rx_resources(adapter,
1689 &adapter->rx_ring[i]);
1659 break; 1690 break;
1660 } 1691 }
1661 } 1692 }
@@ -2442,10 +2473,9 @@ e1000_watchdog(unsigned long data)
2442 * disable receives in the ISR and 2473 * disable receives in the ISR and
2443 * reset device here in the watchdog 2474 * reset device here in the watchdog
2444 */ 2475 */
2445 if (adapter->hw.mac_type == e1000_80003es2lan) { 2476 if (adapter->hw.mac_type == e1000_80003es2lan)
2446 /* reset device */ 2477 /* reset device */
2447 schedule_work(&adapter->reset_task); 2478 schedule_work(&adapter->reset_task);
2448 }
2449 } 2479 }
2450 2480
2451 e1000_smartspeed(adapter); 2481 e1000_smartspeed(adapter);
@@ -2545,7 +2575,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2545 cmd_length = E1000_TXD_CMD_IP; 2575 cmd_length = E1000_TXD_CMD_IP;
2546 ipcse = skb->h.raw - skb->data - 1; 2576 ipcse = skb->h.raw - skb->data - 1;
2547#ifdef NETIF_F_TSO_IPV6 2577#ifdef NETIF_F_TSO_IPV6
2548 } else if (skb->protocol == ntohs(ETH_P_IPV6)) { 2578 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2549 skb->nh.ipv6h->payload_len = 0; 2579 skb->nh.ipv6h->payload_len = 0;
2550 skb->h.th->check = 2580 skb->h.th->check =
2551 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr, 2581 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
@@ -3680,7 +3710,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3680 E1000_DBG("%s: Receive packet consumed multiple" 3710 E1000_DBG("%s: Receive packet consumed multiple"
3681 " buffers\n", netdev->name); 3711 " buffers\n", netdev->name);
3682 /* recycle */ 3712 /* recycle */
3683 buffer_info-> skb = skb; 3713 buffer_info->skb = skb;
3684 goto next_desc; 3714 goto next_desc;
3685 } 3715 }
3686 3716
@@ -3711,7 +3741,6 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3711 netdev_alloc_skb(netdev, length + NET_IP_ALIGN); 3741 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
3712 if (new_skb) { 3742 if (new_skb) {
3713 skb_reserve(new_skb, NET_IP_ALIGN); 3743 skb_reserve(new_skb, NET_IP_ALIGN);
3714 new_skb->dev = netdev;
3715 memcpy(new_skb->data - NET_IP_ALIGN, 3744 memcpy(new_skb->data - NET_IP_ALIGN,
3716 skb->data - NET_IP_ALIGN, 3745 skb->data - NET_IP_ALIGN,
3717 length + NET_IP_ALIGN); 3746 length + NET_IP_ALIGN);
@@ -3978,13 +4007,13 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3978 buffer_info = &rx_ring->buffer_info[i]; 4007 buffer_info = &rx_ring->buffer_info[i];
3979 4008
3980 while (cleaned_count--) { 4009 while (cleaned_count--) {
3981 if (!(skb = buffer_info->skb)) 4010 skb = buffer_info->skb;
3982 skb = netdev_alloc_skb(netdev, bufsz); 4011 if (skb) {
3983 else {
3984 skb_trim(skb, 0); 4012 skb_trim(skb, 0);
3985 goto map_skb; 4013 goto map_skb;
3986 } 4014 }
3987 4015
4016 skb = netdev_alloc_skb(netdev, bufsz);
3988 if (unlikely(!skb)) { 4017 if (unlikely(!skb)) {
3989 /* Better luck next round */ 4018 /* Better luck next round */
3990 adapter->alloc_rx_buff_failed++; 4019 adapter->alloc_rx_buff_failed++;
@@ -4009,10 +4038,10 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
4009 dev_kfree_skb(skb); 4038 dev_kfree_skb(skb);
4010 dev_kfree_skb(oldskb); 4039 dev_kfree_skb(oldskb);
4011 break; /* while !buffer_info->skb */ 4040 break; /* while !buffer_info->skb */
4012 } else {
4013 /* Use new allocation */
4014 dev_kfree_skb(oldskb);
4015 } 4041 }
4042
4043 /* Use new allocation */
4044 dev_kfree_skb(oldskb);
4016 } 4045 }
4017 /* Make buffer alignment 2 beyond a 16 byte boundary 4046 /* Make buffer alignment 2 beyond a 16 byte boundary
4018 * this will result in a 16 byte aligned IP header after 4047 * this will result in a 16 byte aligned IP header after
@@ -4020,8 +4049,6 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
4020 */ 4049 */
4021 skb_reserve(skb, NET_IP_ALIGN); 4050 skb_reserve(skb, NET_IP_ALIGN);
4022 4051
4023 skb->dev = netdev;
4024
4025 buffer_info->skb = skb; 4052 buffer_info->skb = skb;
4026 buffer_info->length = adapter->rx_buffer_len; 4053 buffer_info->length = adapter->rx_buffer_len;
4027map_skb: 4054map_skb:
@@ -4135,8 +4162,6 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
4135 */ 4162 */
4136 skb_reserve(skb, NET_IP_ALIGN); 4163 skb_reserve(skb, NET_IP_ALIGN);
4137 4164
4138 skb->dev = netdev;
4139
4140 buffer_info->skb = skb; 4165 buffer_info->skb = skb;
4141 buffer_info->length = adapter->rx_ps_bsize0; 4166 buffer_info->length = adapter->rx_ps_bsize0;
4142 buffer_info->dma = pci_map_single(pdev, skb->data, 4167 buffer_info->dma = pci_map_single(pdev, skb->data,
@@ -4628,7 +4653,7 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4628 e1000_set_multi(netdev); 4653 e1000_set_multi(netdev);
4629 4654
4630 /* turn on all-multi mode if wake on multicast is enabled */ 4655 /* turn on all-multi mode if wake on multicast is enabled */
4631 if (adapter->wol & E1000_WUFC_MC) { 4656 if (wufc & E1000_WUFC_MC) {
4632 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4657 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4633 rctl |= E1000_RCTL_MPE; 4658 rctl |= E1000_RCTL_MPE;
4634 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4659 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
@@ -4700,11 +4725,14 @@ e1000_resume(struct pci_dev *pdev)
4700{ 4725{
4701 struct net_device *netdev = pci_get_drvdata(pdev); 4726 struct net_device *netdev = pci_get_drvdata(pdev);
4702 struct e1000_adapter *adapter = netdev_priv(netdev); 4727 struct e1000_adapter *adapter = netdev_priv(netdev);
4703 uint32_t manc, ret_val; 4728 uint32_t manc, err;
4704 4729
4705 pci_set_power_state(pdev, PCI_D0); 4730 pci_set_power_state(pdev, PCI_D0);
4706 e1000_pci_restore_state(adapter); 4731 e1000_pci_restore_state(adapter);
4707 ret_val = pci_enable_device(pdev); 4732 if ((err = pci_enable_device(pdev))) {
4733 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
4734 return err;
4735 }
4708 pci_set_master(pdev); 4736 pci_set_master(pdev);
4709 4737
4710 pci_enable_wake(pdev, PCI_D3hot, 0); 4738 pci_enable_wake(pdev, PCI_D3hot, 0);
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index 0ef413172c68..212842738972 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -324,7 +324,6 @@ e1000_check_options(struct e1000_adapter *adapter)
324 DPRINTK(PROBE, NOTICE, 324 DPRINTK(PROBE, NOTICE,
325 "Warning: no configuration for board #%i\n", bd); 325 "Warning: no configuration for board #%i\n", bd);
326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n"); 326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n");
327 bd = E1000_MAX_NIC;
328 } 327 }
329 328
330 { /* Transmit Descriptor Count */ 329 { /* Transmit Descriptor Count */
@@ -342,9 +341,14 @@ e1000_check_options(struct e1000_adapter *adapter)
342 opt.arg.r.max = mac_type < e1000_82544 ? 341 opt.arg.r.max = mac_type < e1000_82544 ?
343 E1000_MAX_TXD : E1000_MAX_82544_TXD; 342 E1000_MAX_TXD : E1000_MAX_82544_TXD;
344 343
345 tx_ring->count = TxDescriptors[bd]; 344 if (num_TxDescriptors > bd) {
346 e1000_validate_option(&tx_ring->count, &opt, adapter); 345 tx_ring->count = TxDescriptors[bd];
347 E1000_ROUNDUP(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE); 346 e1000_validate_option(&tx_ring->count, &opt, adapter);
347 E1000_ROUNDUP(tx_ring->count,
348 REQ_TX_DESCRIPTOR_MULTIPLE);
349 } else {
350 tx_ring->count = opt.def;
351 }
348 for (i = 0; i < adapter->num_tx_queues; i++) 352 for (i = 0; i < adapter->num_tx_queues; i++)
349 tx_ring[i].count = tx_ring->count; 353 tx_ring[i].count = tx_ring->count;
350 } 354 }
@@ -363,9 +367,14 @@ e1000_check_options(struct e1000_adapter *adapter)
363 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD : 367 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD :
364 E1000_MAX_82544_RXD; 368 E1000_MAX_82544_RXD;
365 369
366 rx_ring->count = RxDescriptors[bd]; 370 if (num_RxDescriptors > bd) {
367 e1000_validate_option(&rx_ring->count, &opt, adapter); 371 rx_ring->count = RxDescriptors[bd];
368 E1000_ROUNDUP(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE); 372 e1000_validate_option(&rx_ring->count, &opt, adapter);
373 E1000_ROUNDUP(rx_ring->count,
374 REQ_RX_DESCRIPTOR_MULTIPLE);
375 } else {
376 rx_ring->count = opt.def;
377 }
369 for (i = 0; i < adapter->num_rx_queues; i++) 378 for (i = 0; i < adapter->num_rx_queues; i++)
370 rx_ring[i].count = rx_ring->count; 379 rx_ring[i].count = rx_ring->count;
371 } 380 }
@@ -377,9 +386,13 @@ e1000_check_options(struct e1000_adapter *adapter)
377 .def = OPTION_ENABLED 386 .def = OPTION_ENABLED
378 }; 387 };
379 388
380 int rx_csum = XsumRX[bd]; 389 if (num_XsumRX > bd) {
381 e1000_validate_option(&rx_csum, &opt, adapter); 390 int rx_csum = XsumRX[bd];
382 adapter->rx_csum = rx_csum; 391 e1000_validate_option(&rx_csum, &opt, adapter);
392 adapter->rx_csum = rx_csum;
393 } else {
394 adapter->rx_csum = opt.def;
395 }
383 } 396 }
384 { /* Flow Control */ 397 { /* Flow Control */
385 398
@@ -399,9 +412,13 @@ e1000_check_options(struct e1000_adapter *adapter)
399 .p = fc_list }} 412 .p = fc_list }}
400 }; 413 };
401 414
402 int fc = FlowControl[bd]; 415 if (num_FlowControl > bd) {
403 e1000_validate_option(&fc, &opt, adapter); 416 int fc = FlowControl[bd];
404 adapter->hw.fc = adapter->hw.original_fc = fc; 417 e1000_validate_option(&fc, &opt, adapter);
418 adapter->hw.fc = adapter->hw.original_fc = fc;
419 } else {
420 adapter->hw.fc = adapter->hw.original_fc = opt.def;
421 }
405 } 422 }
406 { /* Transmit Interrupt Delay */ 423 { /* Transmit Interrupt Delay */
407 struct e1000_option opt = { 424 struct e1000_option opt = {
@@ -413,8 +430,13 @@ e1000_check_options(struct e1000_adapter *adapter)
413 .max = MAX_TXDELAY }} 430 .max = MAX_TXDELAY }}
414 }; 431 };
415 432
416 adapter->tx_int_delay = TxIntDelay[bd]; 433 if (num_TxIntDelay > bd) {
417 e1000_validate_option(&adapter->tx_int_delay, &opt, adapter); 434 adapter->tx_int_delay = TxIntDelay[bd];
435 e1000_validate_option(&adapter->tx_int_delay, &opt,
436 adapter);
437 } else {
438 adapter->tx_int_delay = opt.def;
439 }
418 } 440 }
419 { /* Transmit Absolute Interrupt Delay */ 441 { /* Transmit Absolute Interrupt Delay */
420 struct e1000_option opt = { 442 struct e1000_option opt = {
@@ -426,9 +448,13 @@ e1000_check_options(struct e1000_adapter *adapter)
426 .max = MAX_TXABSDELAY }} 448 .max = MAX_TXABSDELAY }}
427 }; 449 };
428 450
429 adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; 451 if (num_TxAbsIntDelay > bd) {
430 e1000_validate_option(&adapter->tx_abs_int_delay, &opt, 452 adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
431 adapter); 453 e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
454 adapter);
455 } else {
456 adapter->tx_abs_int_delay = opt.def;
457 }
432 } 458 }
433 { /* Receive Interrupt Delay */ 459 { /* Receive Interrupt Delay */
434 struct e1000_option opt = { 460 struct e1000_option opt = {
@@ -440,8 +466,13 @@ e1000_check_options(struct e1000_adapter *adapter)
440 .max = MAX_RXDELAY }} 466 .max = MAX_RXDELAY }}
441 }; 467 };
442 468
443 adapter->rx_int_delay = RxIntDelay[bd]; 469 if (num_RxIntDelay > bd) {
444 e1000_validate_option(&adapter->rx_int_delay, &opt, adapter); 470 adapter->rx_int_delay = RxIntDelay[bd];
471 e1000_validate_option(&adapter->rx_int_delay, &opt,
472 adapter);
473 } else {
474 adapter->rx_int_delay = opt.def;
475 }
445 } 476 }
446 { /* Receive Absolute Interrupt Delay */ 477 { /* Receive Absolute Interrupt Delay */
447 struct e1000_option opt = { 478 struct e1000_option opt = {
@@ -453,9 +484,13 @@ e1000_check_options(struct e1000_adapter *adapter)
453 .max = MAX_RXABSDELAY }} 484 .max = MAX_RXABSDELAY }}
454 }; 485 };
455 486
456 adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; 487 if (num_RxAbsIntDelay > bd) {
457 e1000_validate_option(&adapter->rx_abs_int_delay, &opt, 488 adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
458 adapter); 489 e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
490 adapter);
491 } else {
492 adapter->rx_abs_int_delay = opt.def;
493 }
459 } 494 }
460 { /* Interrupt Throttling Rate */ 495 { /* Interrupt Throttling Rate */
461 struct e1000_option opt = { 496 struct e1000_option opt = {
@@ -467,18 +502,24 @@ e1000_check_options(struct e1000_adapter *adapter)
467 .max = MAX_ITR }} 502 .max = MAX_ITR }}
468 }; 503 };
469 504
470 adapter->itr = InterruptThrottleRate[bd]; 505 if (num_InterruptThrottleRate > bd) {
471 switch (adapter->itr) { 506 adapter->itr = InterruptThrottleRate[bd];
472 case 0: 507 switch (adapter->itr) {
473 DPRINTK(PROBE, INFO, "%s turned off\n", opt.name); 508 case 0:
474 break; 509 DPRINTK(PROBE, INFO, "%s turned off\n",
475 case 1: 510 opt.name);
476 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 511 break;
477 opt.name); 512 case 1:
478 break; 513 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
479 default: 514 opt.name);
480 e1000_validate_option(&adapter->itr, &opt, adapter); 515 break;
481 break; 516 default:
517 e1000_validate_option(&adapter->itr, &opt,
518 adapter);
519 break;
520 }
521 } else {
522 adapter->itr = opt.def;
482 } 523 }
483 } 524 }
484 { /* Smart Power Down */ 525 { /* Smart Power Down */
@@ -489,9 +530,13 @@ e1000_check_options(struct e1000_adapter *adapter)
489 .def = OPTION_DISABLED 530 .def = OPTION_DISABLED
490 }; 531 };
491 532
492 int spd = SmartPowerDownEnable[bd]; 533 if (num_SmartPowerDownEnable > bd) {
493 e1000_validate_option(&spd, &opt, adapter); 534 int spd = SmartPowerDownEnable[bd];
494 adapter->smart_power_down = spd; 535 e1000_validate_option(&spd, &opt, adapter);
536 adapter->smart_power_down = spd;
537 } else {
538 adapter->smart_power_down = opt.def;
539 }
495 } 540 }
496 { /* Kumeran Lock Loss Workaround */ 541 { /* Kumeran Lock Loss Workaround */
497 struct e1000_option opt = { 542 struct e1000_option opt = {
@@ -501,9 +546,13 @@ e1000_check_options(struct e1000_adapter *adapter)
501 .def = OPTION_ENABLED 546 .def = OPTION_ENABLED
502 }; 547 };
503 548
549 if (num_KumeranLockLoss > bd) {
504 int kmrn_lock_loss = KumeranLockLoss[bd]; 550 int kmrn_lock_loss = KumeranLockLoss[bd];
505 e1000_validate_option(&kmrn_lock_loss, &opt, adapter); 551 e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
506 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss; 552 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss;
553 } else {
554 adapter->hw.kmrn_lock_loss_workaround_disabled = !opt.def;
555 }
507 } 556 }
508 557
509 switch (adapter->hw.media_type) { 558 switch (adapter->hw.media_type) {
@@ -530,18 +579,17 @@ static void __devinit
530e1000_check_fiber_options(struct e1000_adapter *adapter) 579e1000_check_fiber_options(struct e1000_adapter *adapter)
531{ 580{
532 int bd = adapter->bd_number; 581 int bd = adapter->bd_number;
533 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd; 582 if (num_Speed > bd) {
534 if ((Speed[bd] != OPTION_UNSET)) {
535 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, " 583 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, "
536 "parameter ignored\n"); 584 "parameter ignored\n");
537 } 585 }
538 586
539 if ((Duplex[bd] != OPTION_UNSET)) { 587 if (num_Duplex > bd) {
540 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, " 588 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, "
541 "parameter ignored\n"); 589 "parameter ignored\n");
542 } 590 }
543 591
544 if ((AutoNeg[bd] != OPTION_UNSET) && (AutoNeg[bd] != 0x20)) { 592 if ((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) {
545 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is " 593 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is "
546 "not valid for fiber adapters, " 594 "not valid for fiber adapters, "
547 "parameter ignored\n"); 595 "parameter ignored\n");
@@ -560,7 +608,6 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
560{ 608{
561 int speed, dplx, an; 609 int speed, dplx, an;
562 int bd = adapter->bd_number; 610 int bd = adapter->bd_number;
563 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd;
564 611
565 { /* Speed */ 612 { /* Speed */
566 struct e1000_opt_list speed_list[] = {{ 0, "" }, 613 struct e1000_opt_list speed_list[] = {{ 0, "" },
@@ -577,8 +624,12 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
577 .p = speed_list }} 624 .p = speed_list }}
578 }; 625 };
579 626
580 speed = Speed[bd]; 627 if (num_Speed > bd) {
581 e1000_validate_option(&speed, &opt, adapter); 628 speed = Speed[bd];
629 e1000_validate_option(&speed, &opt, adapter);
630 } else {
631 speed = opt.def;
632 }
582 } 633 }
583 { /* Duplex */ 634 { /* Duplex */
584 struct e1000_opt_list dplx_list[] = {{ 0, "" }, 635 struct e1000_opt_list dplx_list[] = {{ 0, "" },
@@ -600,11 +651,15 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
600 "Speed/Duplex/AutoNeg parameter ignored.\n"); 651 "Speed/Duplex/AutoNeg parameter ignored.\n");
601 return; 652 return;
602 } 653 }
603 dplx = Duplex[bd]; 654 if (num_Duplex > bd) {
604 e1000_validate_option(&dplx, &opt, adapter); 655 dplx = Duplex[bd];
656 e1000_validate_option(&dplx, &opt, adapter);
657 } else {
658 dplx = opt.def;
659 }
605 } 660 }
606 661
607 if (AutoNeg[bd] != OPTION_UNSET && (speed != 0 || dplx != 0)) { 662 if ((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) {
608 DPRINTK(PROBE, INFO, 663 DPRINTK(PROBE, INFO,
609 "AutoNeg specified along with Speed or Duplex, " 664 "AutoNeg specified along with Speed or Duplex, "
610 "parameter ignored\n"); 665 "parameter ignored\n");
@@ -653,15 +708,19 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
653 .p = an_list }} 708 .p = an_list }}
654 }; 709 };
655 710
656 an = AutoNeg[bd]; 711 if (num_AutoNeg > bd) {
657 e1000_validate_option(&an, &opt, adapter); 712 an = AutoNeg[bd];
713 e1000_validate_option(&an, &opt, adapter);
714 } else {
715 an = opt.def;
716 }
658 adapter->hw.autoneg_advertised = an; 717 adapter->hw.autoneg_advertised = an;
659 } 718 }
660 719
661 switch (speed + dplx) { 720 switch (speed + dplx) {
662 case 0: 721 case 0:
663 adapter->hw.autoneg = adapter->fc_autoneg = 1; 722 adapter->hw.autoneg = adapter->fc_autoneg = 1;
664 if (Speed[bd] != OPTION_UNSET || Duplex[bd] != OPTION_UNSET) 723 if ((num_Speed > bd) && (speed != 0 || dplx != 0))
665 DPRINTK(PROBE, INFO, 724 DPRINTK(PROBE, INFO,
666 "Speed and duplex autonegotiation enabled\n"); 725 "Speed and duplex autonegotiation enabled\n");
667 break; 726 break;
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index e445988c92ee..a3d515def109 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -2385,7 +2385,7 @@ static int __init eepro100_init_module(void)
2385#ifdef MODULE 2385#ifdef MODULE
2386 printk(version); 2386 printk(version);
2387#endif 2387#endif
2388 return pci_module_init(&eepro100_driver); 2388 return pci_register_driver(&eepro100_driver);
2389} 2389}
2390 2390
2391static void __exit eepro100_cleanup_module(void) 2391static void __exit eepro100_cleanup_module(void)
diff --git a/drivers/net/epic100.c b/drivers/net/epic100.c
index a67650ccf084..25c4619d842e 100644
--- a/drivers/net/epic100.c
+++ b/drivers/net/epic100.c
@@ -1604,7 +1604,7 @@ static int __init epic_init (void)
1604 version, version2, version3); 1604 version, version2, version3);
1605#endif 1605#endif
1606 1606
1607 return pci_module_init (&epic_driver); 1607 return pci_register_driver(&epic_driver);
1608} 1608}
1609 1609
1610 1610
diff --git a/drivers/net/fealnx.c b/drivers/net/fealnx.c
index 567e27413cfd..a2121faa610f 100644
--- a/drivers/net/fealnx.c
+++ b/drivers/net/fealnx.c
@@ -1984,7 +1984,7 @@ static int __init fealnx_init(void)
1984 printk(version); 1984 printk(version);
1985#endif 1985#endif
1986 1986
1987 return pci_module_init(&fealnx_driver); 1987 return pci_register_driver(&fealnx_driver);
1988} 1988}
1989 1989
1990static void __exit fealnx_exit(void) 1990static void __exit fealnx_exit(void)
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 11b8f1b43dd5..59f9a515c07c 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -109,6 +109,7 @@
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup. 109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
110 * 0.55: 22 Mar 2006: Add flow control (pause frame). 110 * 0.55: 22 Mar 2006: Add flow control (pause frame).
111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support. 111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
112 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 113 *
113 * Known bugs: 114 * Known bugs:
114 * We suspect that on some hardware no TX done interrupts are generated. 115 * We suspect that on some hardware no TX done interrupts are generated.
@@ -120,7 +121,12 @@
120 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 121 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
121 * superfluous timer interrupts from the nic. 122 * superfluous timer interrupts from the nic.
122 */ 123 */
123#define FORCEDETH_VERSION "0.56" 124#ifdef CONFIG_FORCEDETH_NAPI
125#define DRIVERNAPI "-NAPI"
126#else
127#define DRIVERNAPI
128#endif
129#define FORCEDETH_VERSION "0.57"
124#define DRV_NAME "forcedeth" 130#define DRV_NAME "forcedeth"
125 131
126#include <linux/module.h> 132#include <linux/module.h>
@@ -262,7 +268,8 @@ enum {
262 NvRegRingSizes = 0x108, 268 NvRegRingSizes = 0x108,
263#define NVREG_RINGSZ_TXSHIFT 0 269#define NVREG_RINGSZ_TXSHIFT 0
264#define NVREG_RINGSZ_RXSHIFT 16 270#define NVREG_RINGSZ_RXSHIFT 16
265 NvRegUnknownTransmitterReg = 0x10c, 271 NvRegTransmitPoll = 0x10c,
272#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
266 NvRegLinkSpeed = 0x110, 273 NvRegLinkSpeed = 0x110,
267#define NVREG_LINKSPEED_FORCE 0x10000 274#define NVREG_LINKSPEED_FORCE 0x10000
268#define NVREG_LINKSPEED_10 1000 275#define NVREG_LINKSPEED_10 1000
@@ -381,21 +388,21 @@ enum {
381 388
382/* Big endian: should work, but is untested */ 389/* Big endian: should work, but is untested */
383struct ring_desc { 390struct ring_desc {
384 u32 PacketBuffer; 391 __le32 buf;
385 u32 FlagLen; 392 __le32 flaglen;
386}; 393};
387 394
388struct ring_desc_ex { 395struct ring_desc_ex {
389 u32 PacketBufferHigh; 396 __le32 bufhigh;
390 u32 PacketBufferLow; 397 __le32 buflow;
391 u32 TxVlan; 398 __le32 txvlan;
392 u32 FlagLen; 399 __le32 flaglen;
393}; 400};
394 401
395typedef union _ring_type { 402union ring_type {
396 struct ring_desc* orig; 403 struct ring_desc* orig;
397 struct ring_desc_ex* ex; 404 struct ring_desc_ex* ex;
398} ring_type; 405};
399 406
400#define FLAG_MASK_V1 0xffff0000 407#define FLAG_MASK_V1 0xffff0000
401#define FLAG_MASK_V2 0xffffc000 408#define FLAG_MASK_V2 0xffffc000
@@ -536,6 +543,9 @@ typedef union _ring_type {
536#define PHYID1_OUI_SHFT 6 543#define PHYID1_OUI_SHFT 6
537#define PHYID2_OUI_MASK 0xfc00 544#define PHYID2_OUI_MASK 0xfc00
538#define PHYID2_OUI_SHFT 10 545#define PHYID2_OUI_SHFT 10
546#define PHYID2_MODEL_MASK 0x03f0
547#define PHY_MODEL_MARVELL_E3016 0x220
548#define PHY_MARVELL_E3016_INITMASK 0x0300
539#define PHY_INIT1 0x0f000 549#define PHY_INIT1 0x0f000
540#define PHY_INIT2 0x0e00 550#define PHY_INIT2 0x0e00
541#define PHY_INIT3 0x01000 551#define PHY_INIT3 0x01000
@@ -653,8 +663,8 @@ static const struct nv_ethtool_str nv_etests_str[] = {
653}; 663};
654 664
655struct register_test { 665struct register_test {
656 u32 reg; 666 __le32 reg;
657 u32 mask; 667 __le32 mask;
658}; 668};
659 669
660static const struct register_test nv_registers_test[] = { 670static const struct register_test nv_registers_test[] = {
@@ -694,6 +704,7 @@ struct fe_priv {
694 int phyaddr; 704 int phyaddr;
695 int wolenabled; 705 int wolenabled;
696 unsigned int phy_oui; 706 unsigned int phy_oui;
707 unsigned int phy_model;
697 u16 gigabit; 708 u16 gigabit;
698 int intr_test; 709 int intr_test;
699 710
@@ -707,13 +718,14 @@ struct fe_priv {
707 u32 vlanctl_bits; 718 u32 vlanctl_bits;
708 u32 driver_data; 719 u32 driver_data;
709 u32 register_size; 720 u32 register_size;
721 int rx_csum;
710 722
711 void __iomem *base; 723 void __iomem *base;
712 724
713 /* rx specific fields. 725 /* rx specific fields.
714 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); 726 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
715 */ 727 */
716 ring_type rx_ring; 728 union ring_type rx_ring;
717 unsigned int cur_rx, refill_rx; 729 unsigned int cur_rx, refill_rx;
718 struct sk_buff **rx_skbuff; 730 struct sk_buff **rx_skbuff;
719 dma_addr_t *rx_dma; 731 dma_addr_t *rx_dma;
@@ -733,7 +745,7 @@ struct fe_priv {
733 /* 745 /*
734 * tx specific fields. 746 * tx specific fields.
735 */ 747 */
736 ring_type tx_ring; 748 union ring_type tx_ring;
737 unsigned int next_tx, nic_tx; 749 unsigned int next_tx, nic_tx;
738 struct sk_buff **tx_skbuff; 750 struct sk_buff **tx_skbuff;
739 dma_addr_t *tx_dma; 751 dma_addr_t *tx_dma;
@@ -826,13 +838,13 @@ static inline void pci_push(u8 __iomem *base)
826 838
827static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) 839static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
828{ 840{
829 return le32_to_cpu(prd->FlagLen) 841 return le32_to_cpu(prd->flaglen)
830 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); 842 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
831} 843}
832 844
833static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) 845static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
834{ 846{
835 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2; 847 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
836} 848}
837 849
838static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, 850static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
@@ -885,7 +897,7 @@ static void free_rings(struct net_device *dev)
885 struct fe_priv *np = get_nvpriv(dev); 897 struct fe_priv *np = get_nvpriv(dev);
886 898
887 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 899 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
888 if(np->rx_ring.orig) 900 if (np->rx_ring.orig)
889 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), 901 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
890 np->rx_ring.orig, np->ring_addr); 902 np->rx_ring.orig, np->ring_addr);
891 } else { 903 } else {
@@ -1020,14 +1032,13 @@ static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1020 return retval; 1032 return retval;
1021} 1033}
1022 1034
1023static int phy_reset(struct net_device *dev) 1035static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1024{ 1036{
1025 struct fe_priv *np = netdev_priv(dev); 1037 struct fe_priv *np = netdev_priv(dev);
1026 u32 miicontrol; 1038 u32 miicontrol;
1027 unsigned int tries = 0; 1039 unsigned int tries = 0;
1028 1040
1029 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 1041 miicontrol = BMCR_RESET | bmcr_setup;
1030 miicontrol |= BMCR_RESET;
1031 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { 1042 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1032 return -1; 1043 return -1;
1033 } 1044 }
@@ -1052,6 +1063,16 @@ static int phy_init(struct net_device *dev)
1052 u8 __iomem *base = get_hwbase(dev); 1063 u8 __iomem *base = get_hwbase(dev);
1053 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; 1064 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1054 1065
1066 /* phy errata for E3016 phy */
1067 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1068 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1069 reg &= ~PHY_MARVELL_E3016_INITMASK;
1070 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1071 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1072 return PHY_ERROR;
1073 }
1074 }
1075
1055 /* set advertise register */ 1076 /* set advertise register */
1056 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); 1077 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1057 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); 1078 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
@@ -1082,8 +1103,13 @@ static int phy_init(struct net_device *dev)
1082 else 1103 else
1083 np->gigabit = 0; 1104 np->gigabit = 0;
1084 1105
1085 /* reset the phy */ 1106 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1086 if (phy_reset(dev)) { 1107 mii_control |= BMCR_ANENABLE;
1108
1109 /* reset the phy
1110 * (certain phys need bmcr to be setup with reset)
1111 */
1112 if (phy_reset(dev, mii_control)) {
1087 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); 1113 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1088 return PHY_ERROR; 1114 return PHY_ERROR;
1089 } 1115 }
@@ -1178,7 +1204,7 @@ static void nv_stop_tx(struct net_device *dev)
1178 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); 1204 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1179 1205
1180 udelay(NV_TXSTOP_DELAY2); 1206 udelay(NV_TXSTOP_DELAY2);
1181 writel(0, base + NvRegUnknownTransmitterReg); 1207 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1182} 1208}
1183 1209
1184static void nv_txrx_reset(struct net_device *dev) 1210static void nv_txrx_reset(struct net_device *dev)
@@ -1258,14 +1284,14 @@ static int nv_alloc_rx(struct net_device *dev)
1258 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, 1284 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1259 skb->end-skb->data, PCI_DMA_FROMDEVICE); 1285 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1260 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 1286 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1261 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]); 1287 np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1262 wmb(); 1288 wmb();
1263 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); 1289 np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1264 } else { 1290 } else {
1265 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32; 1291 np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1266 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF; 1292 np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1267 wmb(); 1293 wmb();
1268 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); 1294 np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1269 } 1295 }
1270 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n", 1296 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1271 dev->name, refill_rx); 1297 dev->name, refill_rx);
@@ -1277,6 +1303,16 @@ static int nv_alloc_rx(struct net_device *dev)
1277 return 0; 1303 return 0;
1278} 1304}
1279 1305
1306/* If rx bufs are exhausted called after 50ms to attempt to refresh */
1307#ifdef CONFIG_FORCEDETH_NAPI
1308static void nv_do_rx_refill(unsigned long data)
1309{
1310 struct net_device *dev = (struct net_device *) data;
1311
1312 /* Just reschedule NAPI rx processing */
1313 netif_rx_schedule(dev);
1314}
1315#else
1280static void nv_do_rx_refill(unsigned long data) 1316static void nv_do_rx_refill(unsigned long data)
1281{ 1317{
1282 struct net_device *dev = (struct net_device *) data; 1318 struct net_device *dev = (struct net_device *) data;
@@ -1305,6 +1341,7 @@ static void nv_do_rx_refill(unsigned long data)
1305 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); 1341 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1306 } 1342 }
1307} 1343}
1344#endif
1308 1345
1309static void nv_init_rx(struct net_device *dev) 1346static void nv_init_rx(struct net_device *dev)
1310{ 1347{
@@ -1315,9 +1352,9 @@ static void nv_init_rx(struct net_device *dev)
1315 np->refill_rx = 0; 1352 np->refill_rx = 0;
1316 for (i = 0; i < np->rx_ring_size; i++) 1353 for (i = 0; i < np->rx_ring_size; i++)
1317 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) 1354 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1318 np->rx_ring.orig[i].FlagLen = 0; 1355 np->rx_ring.orig[i].flaglen = 0;
1319 else 1356 else
1320 np->rx_ring.ex[i].FlagLen = 0; 1357 np->rx_ring.ex[i].flaglen = 0;
1321} 1358}
1322 1359
1323static void nv_init_tx(struct net_device *dev) 1360static void nv_init_tx(struct net_device *dev)
@@ -1328,9 +1365,9 @@ static void nv_init_tx(struct net_device *dev)
1328 np->next_tx = np->nic_tx = 0; 1365 np->next_tx = np->nic_tx = 0;
1329 for (i = 0; i < np->tx_ring_size; i++) { 1366 for (i = 0; i < np->tx_ring_size; i++) {
1330 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) 1367 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1331 np->tx_ring.orig[i].FlagLen = 0; 1368 np->tx_ring.orig[i].flaglen = 0;
1332 else 1369 else
1333 np->tx_ring.ex[i].FlagLen = 0; 1370 np->tx_ring.ex[i].flaglen = 0;
1334 np->tx_skbuff[i] = NULL; 1371 np->tx_skbuff[i] = NULL;
1335 np->tx_dma[i] = 0; 1372 np->tx_dma[i] = 0;
1336 } 1373 }
@@ -1373,9 +1410,9 @@ static void nv_drain_tx(struct net_device *dev)
1373 1410
1374 for (i = 0; i < np->tx_ring_size; i++) { 1411 for (i = 0; i < np->tx_ring_size; i++) {
1375 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) 1412 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1376 np->tx_ring.orig[i].FlagLen = 0; 1413 np->tx_ring.orig[i].flaglen = 0;
1377 else 1414 else
1378 np->tx_ring.ex[i].FlagLen = 0; 1415 np->tx_ring.ex[i].flaglen = 0;
1379 if (nv_release_txskb(dev, i)) 1416 if (nv_release_txskb(dev, i))
1380 np->stats.tx_dropped++; 1417 np->stats.tx_dropped++;
1381 } 1418 }
@@ -1387,9 +1424,9 @@ static void nv_drain_rx(struct net_device *dev)
1387 int i; 1424 int i;
1388 for (i = 0; i < np->rx_ring_size; i++) { 1425 for (i = 0; i < np->rx_ring_size; i++) {
1389 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) 1426 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1390 np->rx_ring.orig[i].FlagLen = 0; 1427 np->rx_ring.orig[i].flaglen = 0;
1391 else 1428 else
1392 np->rx_ring.ex[i].FlagLen = 0; 1429 np->rx_ring.ex[i].flaglen = 0;
1393 wmb(); 1430 wmb();
1394 if (np->rx_skbuff[i]) { 1431 if (np->rx_skbuff[i]) {
1395 pci_unmap_single(np->pci_dev, np->rx_dma[i], 1432 pci_unmap_single(np->pci_dev, np->rx_dma[i],
@@ -1450,17 +1487,17 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1450 np->tx_dma_len[nr] = bcnt; 1487 np->tx_dma_len[nr] = bcnt;
1451 1488
1452 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 1489 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1453 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); 1490 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1454 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); 1491 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1455 } else { 1492 } else {
1456 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; 1493 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1457 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; 1494 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1458 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); 1495 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1459 } 1496 }
1460 tx_flags = np->tx_flags; 1497 tx_flags = np->tx_flags;
1461 offset += bcnt; 1498 offset += bcnt;
1462 size -= bcnt; 1499 size -= bcnt;
1463 } while(size); 1500 } while (size);
1464 1501
1465 /* setup the fragments */ 1502 /* setup the fragments */
1466 for (i = 0; i < fragments; i++) { 1503 for (i = 0; i < fragments; i++) {
@@ -1477,12 +1514,12 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1477 np->tx_dma_len[nr] = bcnt; 1514 np->tx_dma_len[nr] = bcnt;
1478 1515
1479 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 1516 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1480 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); 1517 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1481 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); 1518 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1482 } else { 1519 } else {
1483 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; 1520 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1484 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; 1521 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1485 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); 1522 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1486 } 1523 }
1487 offset += bcnt; 1524 offset += bcnt;
1488 size -= bcnt; 1525 size -= bcnt;
@@ -1491,9 +1528,9 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1491 1528
1492 /* set last fragment flag */ 1529 /* set last fragment flag */
1493 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 1530 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1494 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra); 1531 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1495 } else { 1532 } else {
1496 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra); 1533 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1497 } 1534 }
1498 1535
1499 np->tx_skbuff[nr] = skb; 1536 np->tx_skbuff[nr] = skb;
@@ -1512,10 +1549,10 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1512 1549
1513 /* set tx flags */ 1550 /* set tx flags */
1514 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 1551 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1515 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); 1552 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1516 } else { 1553 } else {
1517 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan); 1554 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1518 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); 1555 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1519 } 1556 }
1520 1557
1521 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n", 1558 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
@@ -1547,7 +1584,7 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1547static void nv_tx_done(struct net_device *dev) 1584static void nv_tx_done(struct net_device *dev)
1548{ 1585{
1549 struct fe_priv *np = netdev_priv(dev); 1586 struct fe_priv *np = netdev_priv(dev);
1550 u32 Flags; 1587 u32 flags;
1551 unsigned int i; 1588 unsigned int i;
1552 struct sk_buff *skb; 1589 struct sk_buff *skb;
1553 1590
@@ -1555,22 +1592,22 @@ static void nv_tx_done(struct net_device *dev)
1555 i = np->nic_tx % np->tx_ring_size; 1592 i = np->nic_tx % np->tx_ring_size;
1556 1593
1557 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) 1594 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1558 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen); 1595 flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1559 else 1596 else
1560 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen); 1597 flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1561 1598
1562 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n", 1599 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1563 dev->name, np->nic_tx, Flags); 1600 dev->name, np->nic_tx, flags);
1564 if (Flags & NV_TX_VALID) 1601 if (flags & NV_TX_VALID)
1565 break; 1602 break;
1566 if (np->desc_ver == DESC_VER_1) { 1603 if (np->desc_ver == DESC_VER_1) {
1567 if (Flags & NV_TX_LASTPACKET) { 1604 if (flags & NV_TX_LASTPACKET) {
1568 skb = np->tx_skbuff[i]; 1605 skb = np->tx_skbuff[i];
1569 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| 1606 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1570 NV_TX_UNDERFLOW|NV_TX_ERROR)) { 1607 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1571 if (Flags & NV_TX_UNDERFLOW) 1608 if (flags & NV_TX_UNDERFLOW)
1572 np->stats.tx_fifo_errors++; 1609 np->stats.tx_fifo_errors++;
1573 if (Flags & NV_TX_CARRIERLOST) 1610 if (flags & NV_TX_CARRIERLOST)
1574 np->stats.tx_carrier_errors++; 1611 np->stats.tx_carrier_errors++;
1575 np->stats.tx_errors++; 1612 np->stats.tx_errors++;
1576 } else { 1613 } else {
@@ -1579,13 +1616,13 @@ static void nv_tx_done(struct net_device *dev)
1579 } 1616 }
1580 } 1617 }
1581 } else { 1618 } else {
1582 if (Flags & NV_TX2_LASTPACKET) { 1619 if (flags & NV_TX2_LASTPACKET) {
1583 skb = np->tx_skbuff[i]; 1620 skb = np->tx_skbuff[i];
1584 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| 1621 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1585 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { 1622 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1586 if (Flags & NV_TX2_UNDERFLOW) 1623 if (flags & NV_TX2_UNDERFLOW)
1587 np->stats.tx_fifo_errors++; 1624 np->stats.tx_fifo_errors++;
1588 if (Flags & NV_TX2_CARRIERLOST) 1625 if (flags & NV_TX2_CARRIERLOST)
1589 np->stats.tx_carrier_errors++; 1626 np->stats.tx_carrier_errors++;
1590 np->stats.tx_errors++; 1627 np->stats.tx_errors++;
1591 } else { 1628 } else {
@@ -1638,29 +1675,29 @@ static void nv_tx_timeout(struct net_device *dev)
1638 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 1675 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1639 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", 1676 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1640 i, 1677 i,
1641 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer), 1678 le32_to_cpu(np->tx_ring.orig[i].buf),
1642 le32_to_cpu(np->tx_ring.orig[i].FlagLen), 1679 le32_to_cpu(np->tx_ring.orig[i].flaglen),
1643 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer), 1680 le32_to_cpu(np->tx_ring.orig[i+1].buf),
1644 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen), 1681 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1645 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer), 1682 le32_to_cpu(np->tx_ring.orig[i+2].buf),
1646 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen), 1683 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1647 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer), 1684 le32_to_cpu(np->tx_ring.orig[i+3].buf),
1648 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen)); 1685 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1649 } else { 1686 } else {
1650 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", 1687 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1651 i, 1688 i,
1652 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh), 1689 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1653 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow), 1690 le32_to_cpu(np->tx_ring.ex[i].buflow),
1654 le32_to_cpu(np->tx_ring.ex[i].FlagLen), 1691 le32_to_cpu(np->tx_ring.ex[i].flaglen),
1655 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh), 1692 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1656 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow), 1693 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1657 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen), 1694 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1658 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh), 1695 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1659 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow), 1696 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1660 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen), 1697 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1661 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh), 1698 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1662 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow), 1699 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1663 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen)); 1700 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1664 } 1701 }
1665 } 1702 }
1666 } 1703 }
@@ -1697,7 +1734,7 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1697 int protolen; /* length as stored in the proto field */ 1734 int protolen; /* length as stored in the proto field */
1698 1735
1699 /* 1) calculate len according to header */ 1736 /* 1) calculate len according to header */
1700 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) { 1737 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1701 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); 1738 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1702 hdrlen = VLAN_HLEN; 1739 hdrlen = VLAN_HLEN;
1703 } else { 1740 } else {
@@ -1740,13 +1777,14 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1740 } 1777 }
1741} 1778}
1742 1779
1743static void nv_rx_process(struct net_device *dev) 1780static int nv_rx_process(struct net_device *dev, int limit)
1744{ 1781{
1745 struct fe_priv *np = netdev_priv(dev); 1782 struct fe_priv *np = netdev_priv(dev);
1746 u32 Flags; 1783 u32 flags;
1747 u32 vlanflags = 0; 1784 u32 vlanflags = 0;
1785 int count;
1748 1786
1749 for (;;) { 1787 for (count = 0; count < limit; ++count) {
1750 struct sk_buff *skb; 1788 struct sk_buff *skb;
1751 int len; 1789 int len;
1752 int i; 1790 int i;
@@ -1755,18 +1793,18 @@ static void nv_rx_process(struct net_device *dev)
1755 1793
1756 i = np->cur_rx % np->rx_ring_size; 1794 i = np->cur_rx % np->rx_ring_size;
1757 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 1795 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1758 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen); 1796 flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1759 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver); 1797 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1760 } else { 1798 } else {
1761 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen); 1799 flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1762 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver); 1800 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1763 vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow); 1801 vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1764 } 1802 }
1765 1803
1766 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n", 1804 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1767 dev->name, np->cur_rx, Flags); 1805 dev->name, np->cur_rx, flags);
1768 1806
1769 if (Flags & NV_RX_AVAIL) 1807 if (flags & NV_RX_AVAIL)
1770 break; /* still owned by hardware, */ 1808 break; /* still owned by hardware, */
1771 1809
1772 /* 1810 /*
@@ -1780,7 +1818,7 @@ static void nv_rx_process(struct net_device *dev)
1780 1818
1781 { 1819 {
1782 int j; 1820 int j;
1783 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags); 1821 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1784 for (j=0; j<64; j++) { 1822 for (j=0; j<64; j++) {
1785 if ((j%16) == 0) 1823 if ((j%16) == 0)
1786 dprintk("\n%03x:", j); 1824 dprintk("\n%03x:", j);
@@ -1790,30 +1828,30 @@ static void nv_rx_process(struct net_device *dev)
1790 } 1828 }
1791 /* look at what we actually got: */ 1829 /* look at what we actually got: */
1792 if (np->desc_ver == DESC_VER_1) { 1830 if (np->desc_ver == DESC_VER_1) {
1793 if (!(Flags & NV_RX_DESCRIPTORVALID)) 1831 if (!(flags & NV_RX_DESCRIPTORVALID))
1794 goto next_pkt; 1832 goto next_pkt;
1795 1833
1796 if (Flags & NV_RX_ERROR) { 1834 if (flags & NV_RX_ERROR) {
1797 if (Flags & NV_RX_MISSEDFRAME) { 1835 if (flags & NV_RX_MISSEDFRAME) {
1798 np->stats.rx_missed_errors++; 1836 np->stats.rx_missed_errors++;
1799 np->stats.rx_errors++; 1837 np->stats.rx_errors++;
1800 goto next_pkt; 1838 goto next_pkt;
1801 } 1839 }
1802 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) { 1840 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1803 np->stats.rx_errors++; 1841 np->stats.rx_errors++;
1804 goto next_pkt; 1842 goto next_pkt;
1805 } 1843 }
1806 if (Flags & NV_RX_CRCERR) { 1844 if (flags & NV_RX_CRCERR) {
1807 np->stats.rx_crc_errors++; 1845 np->stats.rx_crc_errors++;
1808 np->stats.rx_errors++; 1846 np->stats.rx_errors++;
1809 goto next_pkt; 1847 goto next_pkt;
1810 } 1848 }
1811 if (Flags & NV_RX_OVERFLOW) { 1849 if (flags & NV_RX_OVERFLOW) {
1812 np->stats.rx_over_errors++; 1850 np->stats.rx_over_errors++;
1813 np->stats.rx_errors++; 1851 np->stats.rx_errors++;
1814 goto next_pkt; 1852 goto next_pkt;
1815 } 1853 }
1816 if (Flags & NV_RX_ERROR4) { 1854 if (flags & NV_RX_ERROR4) {
1817 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); 1855 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1818 if (len < 0) { 1856 if (len < 0) {
1819 np->stats.rx_errors++; 1857 np->stats.rx_errors++;
@@ -1821,32 +1859,32 @@ static void nv_rx_process(struct net_device *dev)
1821 } 1859 }
1822 } 1860 }
1823 /* framing errors are soft errors. */ 1861 /* framing errors are soft errors. */
1824 if (Flags & NV_RX_FRAMINGERR) { 1862 if (flags & NV_RX_FRAMINGERR) {
1825 if (Flags & NV_RX_SUBSTRACT1) { 1863 if (flags & NV_RX_SUBSTRACT1) {
1826 len--; 1864 len--;
1827 } 1865 }
1828 } 1866 }
1829 } 1867 }
1830 } else { 1868 } else {
1831 if (!(Flags & NV_RX2_DESCRIPTORVALID)) 1869 if (!(flags & NV_RX2_DESCRIPTORVALID))
1832 goto next_pkt; 1870 goto next_pkt;
1833 1871
1834 if (Flags & NV_RX2_ERROR) { 1872 if (flags & NV_RX2_ERROR) {
1835 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) { 1873 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1836 np->stats.rx_errors++; 1874 np->stats.rx_errors++;
1837 goto next_pkt; 1875 goto next_pkt;
1838 } 1876 }
1839 if (Flags & NV_RX2_CRCERR) { 1877 if (flags & NV_RX2_CRCERR) {
1840 np->stats.rx_crc_errors++; 1878 np->stats.rx_crc_errors++;
1841 np->stats.rx_errors++; 1879 np->stats.rx_errors++;
1842 goto next_pkt; 1880 goto next_pkt;
1843 } 1881 }
1844 if (Flags & NV_RX2_OVERFLOW) { 1882 if (flags & NV_RX2_OVERFLOW) {
1845 np->stats.rx_over_errors++; 1883 np->stats.rx_over_errors++;
1846 np->stats.rx_errors++; 1884 np->stats.rx_errors++;
1847 goto next_pkt; 1885 goto next_pkt;
1848 } 1886 }
1849 if (Flags & NV_RX2_ERROR4) { 1887 if (flags & NV_RX2_ERROR4) {
1850 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); 1888 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1851 if (len < 0) { 1889 if (len < 0) {
1852 np->stats.rx_errors++; 1890 np->stats.rx_errors++;
@@ -1854,17 +1892,17 @@ static void nv_rx_process(struct net_device *dev)
1854 } 1892 }
1855 } 1893 }
1856 /* framing errors are soft errors */ 1894 /* framing errors are soft errors */
1857 if (Flags & NV_RX2_FRAMINGERR) { 1895 if (flags & NV_RX2_FRAMINGERR) {
1858 if (Flags & NV_RX2_SUBSTRACT1) { 1896 if (flags & NV_RX2_SUBSTRACT1) {
1859 len--; 1897 len--;
1860 } 1898 }
1861 } 1899 }
1862 } 1900 }
1863 if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) { 1901 if (np->rx_csum) {
1864 Flags &= NV_RX2_CHECKSUMMASK; 1902 flags &= NV_RX2_CHECKSUMMASK;
1865 if (Flags == NV_RX2_CHECKSUMOK1 || 1903 if (flags == NV_RX2_CHECKSUMOK1 ||
1866 Flags == NV_RX2_CHECKSUMOK2 || 1904 flags == NV_RX2_CHECKSUMOK2 ||
1867 Flags == NV_RX2_CHECKSUMOK3) { 1905 flags == NV_RX2_CHECKSUMOK3) {
1868 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name); 1906 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1869 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY; 1907 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1870 } else { 1908 } else {
@@ -1880,17 +1918,27 @@ static void nv_rx_process(struct net_device *dev)
1880 skb->protocol = eth_type_trans(skb, dev); 1918 skb->protocol = eth_type_trans(skb, dev);
1881 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n", 1919 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1882 dev->name, np->cur_rx, len, skb->protocol); 1920 dev->name, np->cur_rx, len, skb->protocol);
1883 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) { 1921#ifdef CONFIG_FORCEDETH_NAPI
1884 vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK); 1922 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1885 } else { 1923 vlan_hwaccel_receive_skb(skb, np->vlangrp,
1924 vlanflags & NV_RX3_VLAN_TAG_MASK);
1925 else
1926 netif_receive_skb(skb);
1927#else
1928 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1929 vlan_hwaccel_rx(skb, np->vlangrp,
1930 vlanflags & NV_RX3_VLAN_TAG_MASK);
1931 else
1886 netif_rx(skb); 1932 netif_rx(skb);
1887 } 1933#endif
1888 dev->last_rx = jiffies; 1934 dev->last_rx = jiffies;
1889 np->stats.rx_packets++; 1935 np->stats.rx_packets++;
1890 np->stats.rx_bytes += len; 1936 np->stats.rx_bytes += len;
1891next_pkt: 1937next_pkt:
1892 np->cur_rx++; 1938 np->cur_rx++;
1893 } 1939 }
1940
1941 return count;
1894} 1942}
1895 1943
1896static void set_bufsize(struct net_device *dev) 1944static void set_bufsize(struct net_device *dev)
@@ -1990,7 +2038,7 @@ static int nv_set_mac_address(struct net_device *dev, void *addr)
1990 struct fe_priv *np = netdev_priv(dev); 2038 struct fe_priv *np = netdev_priv(dev);
1991 struct sockaddr *macaddr = (struct sockaddr*)addr; 2039 struct sockaddr *macaddr = (struct sockaddr*)addr;
1992 2040
1993 if(!is_valid_ether_addr(macaddr->sa_data)) 2041 if (!is_valid_ether_addr(macaddr->sa_data))
1994 return -EADDRNOTAVAIL; 2042 return -EADDRNOTAVAIL;
1995 2043
1996 /* synchronized against open : rtnl_lock() held by caller */ 2044 /* synchronized against open : rtnl_lock() held by caller */
@@ -2032,7 +2080,6 @@ static void nv_set_multicast(struct net_device *dev)
2032 memset(mask, 0, sizeof(mask)); 2080 memset(mask, 0, sizeof(mask));
2033 2081
2034 if (dev->flags & IFF_PROMISC) { 2082 if (dev->flags & IFF_PROMISC) {
2035 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2036 pff |= NVREG_PFF_PROMISC; 2083 pff |= NVREG_PFF_PROMISC;
2037 } else { 2084 } else {
2038 pff |= NVREG_PFF_MYADDR; 2085 pff |= NVREG_PFF_MYADDR;
@@ -2283,20 +2330,20 @@ set_speed:
2283 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM); 2330 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2284 2331
2285 switch (adv_pause) { 2332 switch (adv_pause) {
2286 case (ADVERTISE_PAUSE_CAP): 2333 case ADVERTISE_PAUSE_CAP:
2287 if (lpa_pause & LPA_PAUSE_CAP) { 2334 if (lpa_pause & LPA_PAUSE_CAP) {
2288 pause_flags |= NV_PAUSEFRAME_RX_ENABLE; 2335 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2289 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) 2336 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2290 pause_flags |= NV_PAUSEFRAME_TX_ENABLE; 2337 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2291 } 2338 }
2292 break; 2339 break;
2293 case (ADVERTISE_PAUSE_ASYM): 2340 case ADVERTISE_PAUSE_ASYM:
2294 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM)) 2341 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2295 { 2342 {
2296 pause_flags |= NV_PAUSEFRAME_TX_ENABLE; 2343 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2297 } 2344 }
2298 break; 2345 break;
2299 case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM): 2346 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2300 if (lpa_pause & LPA_PAUSE_CAP) 2347 if (lpa_pause & LPA_PAUSE_CAP)
2301 { 2348 {
2302 pause_flags |= NV_PAUSEFRAME_RX_ENABLE; 2349 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
@@ -2376,14 +2423,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2376 nv_tx_done(dev); 2423 nv_tx_done(dev);
2377 spin_unlock(&np->lock); 2424 spin_unlock(&np->lock);
2378 2425
2379 nv_rx_process(dev);
2380 if (nv_alloc_rx(dev)) {
2381 spin_lock(&np->lock);
2382 if (!np->in_shutdown)
2383 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2384 spin_unlock(&np->lock);
2385 }
2386
2387 if (events & NVREG_IRQ_LINK) { 2426 if (events & NVREG_IRQ_LINK) {
2388 spin_lock(&np->lock); 2427 spin_lock(&np->lock);
2389 nv_link_irq(dev); 2428 nv_link_irq(dev);
@@ -2403,6 +2442,29 @@ static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2403 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", 2442 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2404 dev->name, events); 2443 dev->name, events);
2405 } 2444 }
2445#ifdef CONFIG_FORCEDETH_NAPI
2446 if (events & NVREG_IRQ_RX_ALL) {
2447 netif_rx_schedule(dev);
2448
2449 /* Disable furthur receive irq's */
2450 spin_lock(&np->lock);
2451 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2452
2453 if (np->msi_flags & NV_MSI_X_ENABLED)
2454 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2455 else
2456 writel(np->irqmask, base + NvRegIrqMask);
2457 spin_unlock(&np->lock);
2458 }
2459#else
2460 nv_rx_process(dev, dev->weight);
2461 if (nv_alloc_rx(dev)) {
2462 spin_lock(&np->lock);
2463 if (!np->in_shutdown)
2464 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2465 spin_unlock(&np->lock);
2466 }
2467#endif
2406 if (i > max_interrupt_work) { 2468 if (i > max_interrupt_work) {
2407 spin_lock(&np->lock); 2469 spin_lock(&np->lock);
2408 /* disable interrupts on the nic */ 2470 /* disable interrupts on the nic */
@@ -2474,6 +2536,63 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2474 return IRQ_RETVAL(i); 2536 return IRQ_RETVAL(i);
2475} 2537}
2476 2538
2539#ifdef CONFIG_FORCEDETH_NAPI
2540static int nv_napi_poll(struct net_device *dev, int *budget)
2541{
2542 int pkts, limit = min(*budget, dev->quota);
2543 struct fe_priv *np = netdev_priv(dev);
2544 u8 __iomem *base = get_hwbase(dev);
2545
2546 pkts = nv_rx_process(dev, limit);
2547
2548 if (nv_alloc_rx(dev)) {
2549 spin_lock_irq(&np->lock);
2550 if (!np->in_shutdown)
2551 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2552 spin_unlock_irq(&np->lock);
2553 }
2554
2555 if (pkts < limit) {
2556 /* all done, no more packets present */
2557 netif_rx_complete(dev);
2558
2559 /* re-enable receive interrupts */
2560 spin_lock_irq(&np->lock);
2561 np->irqmask |= NVREG_IRQ_RX_ALL;
2562 if (np->msi_flags & NV_MSI_X_ENABLED)
2563 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2564 else
2565 writel(np->irqmask, base + NvRegIrqMask);
2566 spin_unlock_irq(&np->lock);
2567 return 0;
2568 } else {
2569 /* used up our quantum, so reschedule */
2570 dev->quota -= pkts;
2571 *budget -= pkts;
2572 return 1;
2573 }
2574}
2575#endif
2576
2577#ifdef CONFIG_FORCEDETH_NAPI
2578static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2579{
2580 struct net_device *dev = (struct net_device *) data;
2581 u8 __iomem *base = get_hwbase(dev);
2582 u32 events;
2583
2584 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2585 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2586
2587 if (events) {
2588 netif_rx_schedule(dev);
2589 /* disable receive interrupts on the nic */
2590 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2591 pci_push(base);
2592 }
2593 return IRQ_HANDLED;
2594}
2595#else
2477static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs) 2596static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2478{ 2597{
2479 struct net_device *dev = (struct net_device *) data; 2598 struct net_device *dev = (struct net_device *) data;
@@ -2492,7 +2611,7 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2492 if (!(events & np->irqmask)) 2611 if (!(events & np->irqmask))
2493 break; 2612 break;
2494 2613
2495 nv_rx_process(dev); 2614 nv_rx_process(dev, dev->weight);
2496 if (nv_alloc_rx(dev)) { 2615 if (nv_alloc_rx(dev)) {
2497 spin_lock_irq(&np->lock); 2616 spin_lock_irq(&np->lock);
2498 if (!np->in_shutdown) 2617 if (!np->in_shutdown)
@@ -2514,12 +2633,12 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2514 spin_unlock_irq(&np->lock); 2633 spin_unlock_irq(&np->lock);
2515 break; 2634 break;
2516 } 2635 }
2517
2518 } 2636 }
2519 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); 2637 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2520 2638
2521 return IRQ_RETVAL(i); 2639 return IRQ_RETVAL(i);
2522} 2640}
2641#endif
2523 2642
2524static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs) 2643static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2525{ 2644{
@@ -3057,9 +3176,18 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3057 if (netif_running(dev)) 3176 if (netif_running(dev))
3058 printk(KERN_INFO "%s: link down.\n", dev->name); 3177 printk(KERN_INFO "%s: link down.\n", dev->name);
3059 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 3178 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3060 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 3179 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3061 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); 3180 bmcr |= BMCR_ANENABLE;
3062 3181 /* reset the phy in order for settings to stick,
3182 * and cause autoneg to start */
3183 if (phy_reset(dev, bmcr)) {
3184 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3185 return -EINVAL;
3186 }
3187 } else {
3188 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3189 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3190 }
3063 } else { 3191 } else {
3064 int adv, bmcr; 3192 int adv, bmcr;
3065 3193
@@ -3099,17 +3227,19 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3099 bmcr |= BMCR_FULLDPLX; 3227 bmcr |= BMCR_FULLDPLX;
3100 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) 3228 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3101 bmcr |= BMCR_SPEED100; 3229 bmcr |= BMCR_SPEED100;
3102 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3103 if (np->phy_oui == PHY_OUI_MARVELL) { 3230 if (np->phy_oui == PHY_OUI_MARVELL) {
3104 /* reset the phy */ 3231 /* reset the phy in order for forced mode settings to stick */
3105 if (phy_reset(dev)) { 3232 if (phy_reset(dev, bmcr)) {
3106 printk(KERN_INFO "%s: phy reset failed\n", dev->name); 3233 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3107 return -EINVAL; 3234 return -EINVAL;
3108 } 3235 }
3109 } else if (netif_running(dev)) { 3236 } else {
3110 /* Wait a bit and then reconfigure the nic. */ 3237 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3111 udelay(10); 3238 if (netif_running(dev)) {
3112 nv_linkchange(dev); 3239 /* Wait a bit and then reconfigure the nic. */
3240 udelay(10);
3241 nv_linkchange(dev);
3242 }
3113 } 3243 }
3114 } 3244 }
3115 3245
@@ -3166,8 +3296,17 @@ static int nv_nway_reset(struct net_device *dev)
3166 } 3296 }
3167 3297
3168 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 3298 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3169 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 3299 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3170 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); 3300 bmcr |= BMCR_ANENABLE;
3301 /* reset the phy in order for settings to stick*/
3302 if (phy_reset(dev, bmcr)) {
3303 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3304 return -EINVAL;
3305 }
3306 } else {
3307 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3308 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3309 }
3171 3310
3172 if (netif_running(dev)) { 3311 if (netif_running(dev)) {
3173 nv_start_rx(dev); 3312 nv_start_rx(dev);
@@ -3245,7 +3384,7 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
3245 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) { 3384 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3246 /* fall back to old rings */ 3385 /* fall back to old rings */
3247 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 3386 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3248 if(rxtx_ring) 3387 if (rxtx_ring)
3249 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), 3388 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3250 rxtx_ring, ring_addr); 3389 rxtx_ring, ring_addr);
3251 } else { 3390 } else {
@@ -3418,7 +3557,7 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
3418static u32 nv_get_rx_csum(struct net_device *dev) 3557static u32 nv_get_rx_csum(struct net_device *dev)
3419{ 3558{
3420 struct fe_priv *np = netdev_priv(dev); 3559 struct fe_priv *np = netdev_priv(dev);
3421 return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0; 3560 return (np->rx_csum) != 0;
3422} 3561}
3423 3562
3424static int nv_set_rx_csum(struct net_device *dev, u32 data) 3563static int nv_set_rx_csum(struct net_device *dev, u32 data)
@@ -3428,22 +3567,15 @@ static int nv_set_rx_csum(struct net_device *dev, u32 data)
3428 int retcode = 0; 3567 int retcode = 0;
3429 3568
3430 if (np->driver_data & DEV_HAS_CHECKSUM) { 3569 if (np->driver_data & DEV_HAS_CHECKSUM) {
3431
3432 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3433 (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3434 /* already set or unset */
3435 return 0;
3436 }
3437
3438 if (data) { 3570 if (data) {
3571 np->rx_csum = 1;
3439 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; 3572 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3440 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3441 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3442 } else { 3573 } else {
3443 printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n"); 3574 np->rx_csum = 0;
3444 return -EINVAL; 3575 /* vlan is dependent on rx checksum offload */
3576 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3577 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3445 } 3578 }
3446
3447 if (netif_running(dev)) { 3579 if (netif_running(dev)) {
3448 spin_lock_irq(&np->lock); 3580 spin_lock_irq(&np->lock);
3449 writel(np->txrxctl_bits, base + NvRegTxRxControl); 3581 writel(np->txrxctl_bits, base + NvRegTxRxControl);
@@ -3481,7 +3613,7 @@ static int nv_get_stats_count(struct net_device *dev)
3481 struct fe_priv *np = netdev_priv(dev); 3613 struct fe_priv *np = netdev_priv(dev);
3482 3614
3483 if (np->driver_data & DEV_HAS_STATISTICS) 3615 if (np->driver_data & DEV_HAS_STATISTICS)
3484 return (sizeof(struct nv_ethtool_stats)/sizeof(u64)); 3616 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3485 else 3617 else
3486 return 0; 3618 return 0;
3487} 3619}
@@ -3619,7 +3751,7 @@ static int nv_loopback_test(struct net_device *dev)
3619 struct sk_buff *tx_skb, *rx_skb; 3751 struct sk_buff *tx_skb, *rx_skb;
3620 dma_addr_t test_dma_addr; 3752 dma_addr_t test_dma_addr;
3621 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); 3753 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3622 u32 Flags; 3754 u32 flags;
3623 int len, i, pkt_len; 3755 int len, i, pkt_len;
3624 u8 *pkt_data; 3756 u8 *pkt_data;
3625 u32 filter_flags = 0; 3757 u32 filter_flags = 0;
@@ -3663,12 +3795,12 @@ static int nv_loopback_test(struct net_device *dev)
3663 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE); 3795 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3664 3796
3665 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 3797 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3666 np->tx_ring.orig[0].PacketBuffer = cpu_to_le32(test_dma_addr); 3798 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
3667 np->tx_ring.orig[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); 3799 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3668 } else { 3800 } else {
3669 np->tx_ring.ex[0].PacketBufferHigh = cpu_to_le64(test_dma_addr) >> 32; 3801 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
3670 np->tx_ring.ex[0].PacketBufferLow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF; 3802 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3671 np->tx_ring.ex[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); 3803 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3672 } 3804 }
3673 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); 3805 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3674 pci_push(get_hwbase(dev)); 3806 pci_push(get_hwbase(dev));
@@ -3677,21 +3809,21 @@ static int nv_loopback_test(struct net_device *dev)
3677 3809
3678 /* check for rx of the packet */ 3810 /* check for rx of the packet */
3679 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 3811 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3680 Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen); 3812 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
3681 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); 3813 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3682 3814
3683 } else { 3815 } else {
3684 Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen); 3816 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
3685 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); 3817 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3686 } 3818 }
3687 3819
3688 if (Flags & NV_RX_AVAIL) { 3820 if (flags & NV_RX_AVAIL) {
3689 ret = 0; 3821 ret = 0;
3690 } else if (np->desc_ver == DESC_VER_1) { 3822 } else if (np->desc_ver == DESC_VER_1) {
3691 if (Flags & NV_RX_ERROR) 3823 if (flags & NV_RX_ERROR)
3692 ret = 0; 3824 ret = 0;
3693 } else { 3825 } else {
3694 if (Flags & NV_RX2_ERROR) { 3826 if (flags & NV_RX2_ERROR) {
3695 ret = 0; 3827 ret = 0;
3696 } 3828 }
3697 } 3829 }
@@ -3753,6 +3885,7 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
3753 if (test->flags & ETH_TEST_FL_OFFLINE) { 3885 if (test->flags & ETH_TEST_FL_OFFLINE) {
3754 if (netif_running(dev)) { 3886 if (netif_running(dev)) {
3755 netif_stop_queue(dev); 3887 netif_stop_queue(dev);
3888 netif_poll_disable(dev);
3756 netif_tx_lock_bh(dev); 3889 netif_tx_lock_bh(dev);
3757 spin_lock_irq(&np->lock); 3890 spin_lock_irq(&np->lock);
3758 nv_disable_hw_interrupts(dev, np->irqmask); 3891 nv_disable_hw_interrupts(dev, np->irqmask);
@@ -3811,6 +3944,7 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
3811 nv_start_rx(dev); 3944 nv_start_rx(dev);
3812 nv_start_tx(dev); 3945 nv_start_tx(dev);
3813 netif_start_queue(dev); 3946 netif_start_queue(dev);
3947 netif_poll_enable(dev);
3814 nv_enable_hw_interrupts(dev, np->irqmask); 3948 nv_enable_hw_interrupts(dev, np->irqmask);
3815 } 3949 }
3816 } 3950 }
@@ -3895,10 +4029,9 @@ static int nv_open(struct net_device *dev)
3895 4029
3896 dprintk(KERN_DEBUG "nv_open: begin\n"); 4030 dprintk(KERN_DEBUG "nv_open: begin\n");
3897 4031
3898 /* 1) erase previous misconfiguration */ 4032 /* erase previous misconfiguration */
3899 if (np->driver_data & DEV_HAS_POWER_CNTRL) 4033 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3900 nv_mac_reset(dev); 4034 nv_mac_reset(dev);
3901 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3902 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); 4035 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3903 writel(0, base + NvRegMulticastAddrB); 4036 writel(0, base + NvRegMulticastAddrB);
3904 writel(0, base + NvRegMulticastMaskA); 4037 writel(0, base + NvRegMulticastMaskA);
@@ -3913,26 +4046,22 @@ static int nv_open(struct net_device *dev)
3913 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) 4046 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3914 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); 4047 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3915 4048
3916 /* 2) initialize descriptor rings */ 4049 /* initialize descriptor rings */
3917 set_bufsize(dev); 4050 set_bufsize(dev);
3918 oom = nv_init_ring(dev); 4051 oom = nv_init_ring(dev);
3919 4052
3920 writel(0, base + NvRegLinkSpeed); 4053 writel(0, base + NvRegLinkSpeed);
3921 writel(0, base + NvRegUnknownTransmitterReg); 4054 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
3922 nv_txrx_reset(dev); 4055 nv_txrx_reset(dev);
3923 writel(0, base + NvRegUnknownSetupReg6); 4056 writel(0, base + NvRegUnknownSetupReg6);
3924 4057
3925 np->in_shutdown = 0; 4058 np->in_shutdown = 0;
3926 4059
3927 /* 3) set mac address */ 4060 /* give hw rings */
3928 nv_copy_mac_to_hw(dev);
3929
3930 /* 4) give hw rings */
3931 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); 4061 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3932 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), 4062 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3933 base + NvRegRingSizes); 4063 base + NvRegRingSizes);
3934 4064
3935 /* 5) continue setup */
3936 writel(np->linkspeed, base + NvRegLinkSpeed); 4065 writel(np->linkspeed, base + NvRegLinkSpeed);
3937 if (np->desc_ver == DESC_VER_1) 4066 if (np->desc_ver == DESC_VER_1)
3938 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); 4067 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
@@ -3950,7 +4079,6 @@ static int nv_open(struct net_device *dev)
3950 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); 4079 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3951 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); 4080 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3952 4081
3953 /* 6) continue setup */
3954 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); 4082 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3955 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); 4083 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3956 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); 4084 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
@@ -4020,6 +4148,8 @@ static int nv_open(struct net_device *dev)
4020 nv_start_rx(dev); 4148 nv_start_rx(dev);
4021 nv_start_tx(dev); 4149 nv_start_tx(dev);
4022 netif_start_queue(dev); 4150 netif_start_queue(dev);
4151 netif_poll_enable(dev);
4152
4023 if (ret) { 4153 if (ret) {
4024 netif_carrier_on(dev); 4154 netif_carrier_on(dev);
4025 } else { 4155 } else {
@@ -4049,6 +4179,7 @@ static int nv_close(struct net_device *dev)
4049 spin_lock_irq(&np->lock); 4179 spin_lock_irq(&np->lock);
4050 np->in_shutdown = 1; 4180 np->in_shutdown = 1;
4051 spin_unlock_irq(&np->lock); 4181 spin_unlock_irq(&np->lock);
4182 netif_poll_disable(dev);
4052 synchronize_irq(dev->irq); 4183 synchronize_irq(dev->irq);
4053 4184
4054 del_timer_sync(&np->oom_kick); 4185 del_timer_sync(&np->oom_kick);
@@ -4076,12 +4207,6 @@ static int nv_close(struct net_device *dev)
4076 if (np->wolenabled) 4207 if (np->wolenabled)
4077 nv_start_rx(dev); 4208 nv_start_rx(dev);
4078 4209
4079 /* special op: write back the misordered MAC address - otherwise
4080 * the next nv_probe would see a wrong address.
4081 */
4082 writel(np->orig_mac[0], base + NvRegMacAddrA);
4083 writel(np->orig_mac[1], base + NvRegMacAddrB);
4084
4085 /* FIXME: power down nic */ 4210 /* FIXME: power down nic */
4086 4211
4087 return 0; 4212 return 0;
@@ -4094,7 +4219,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4094 unsigned long addr; 4219 unsigned long addr;
4095 u8 __iomem *base; 4220 u8 __iomem *base;
4096 int err, i; 4221 int err, i;
4097 u32 powerstate; 4222 u32 powerstate, txreg;
4098 4223
4099 dev = alloc_etherdev(sizeof(struct fe_priv)); 4224 dev = alloc_etherdev(sizeof(struct fe_priv));
4100 err = -ENOMEM; 4225 err = -ENOMEM;
@@ -4190,6 +4315,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4190 np->pkt_limit = NV_PKTLIMIT_2; 4315 np->pkt_limit = NV_PKTLIMIT_2;
4191 4316
4192 if (id->driver_data & DEV_HAS_CHECKSUM) { 4317 if (id->driver_data & DEV_HAS_CHECKSUM) {
4318 np->rx_csum = 1;
4193 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; 4319 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4194 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; 4320 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4195#ifdef NETIF_F_TSO 4321#ifdef NETIF_F_TSO
@@ -4270,6 +4396,10 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4270#ifdef CONFIG_NET_POLL_CONTROLLER 4396#ifdef CONFIG_NET_POLL_CONTROLLER
4271 dev->poll_controller = nv_poll_controller; 4397 dev->poll_controller = nv_poll_controller;
4272#endif 4398#endif
4399 dev->weight = 64;
4400#ifdef CONFIG_FORCEDETH_NAPI
4401 dev->poll = nv_napi_poll;
4402#endif
4273 SET_ETHTOOL_OPS(dev, &ops); 4403 SET_ETHTOOL_OPS(dev, &ops);
4274 dev->tx_timeout = nv_tx_timeout; 4404 dev->tx_timeout = nv_tx_timeout;
4275 dev->watchdog_timeo = NV_WATCHDOG_TIMEO; 4405 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
@@ -4281,12 +4411,30 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4281 np->orig_mac[0] = readl(base + NvRegMacAddrA); 4411 np->orig_mac[0] = readl(base + NvRegMacAddrA);
4282 np->orig_mac[1] = readl(base + NvRegMacAddrB); 4412 np->orig_mac[1] = readl(base + NvRegMacAddrB);
4283 4413
4284 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; 4414 /* check the workaround bit for correct mac address order */
4285 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; 4415 txreg = readl(base + NvRegTransmitPoll);
4286 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; 4416 if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4287 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; 4417 /* mac address is already in correct order */
4288 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; 4418 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
4289 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; 4419 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
4420 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4421 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4422 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
4423 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
4424 } else {
4425 /* need to reverse mac address to correct order */
4426 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
4427 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
4428 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4429 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4430 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
4431 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
4432 /* set permanent address to be correct aswell */
4433 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4434 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4435 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4436 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4437 }
4290 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 4438 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4291 4439
4292 if (!is_valid_ether_addr(dev->perm_addr)) { 4440 if (!is_valid_ether_addr(dev->perm_addr)) {
@@ -4309,6 +4457,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4309 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], 4457 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4310 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); 4458 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4311 4459
4460 /* set mac address */
4461 nv_copy_mac_to_hw(dev);
4462
4312 /* disable WOL */ 4463 /* disable WOL */
4313 writel(0, base + NvRegWakeUpFlags); 4464 writel(0, base + NvRegWakeUpFlags);
4314 np->wolenabled = 0; 4465 np->wolenabled = 0;
@@ -4369,6 +4520,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4369 if (id2 < 0 || id2 == 0xffff) 4520 if (id2 < 0 || id2 == 0xffff)
4370 continue; 4521 continue;
4371 4522
4523 np->phy_model = id2 & PHYID2_MODEL_MASK;
4372 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; 4524 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4373 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; 4525 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4374 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", 4526 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
@@ -4421,9 +4573,17 @@ out:
4421static void __devexit nv_remove(struct pci_dev *pci_dev) 4573static void __devexit nv_remove(struct pci_dev *pci_dev)
4422{ 4574{
4423 struct net_device *dev = pci_get_drvdata(pci_dev); 4575 struct net_device *dev = pci_get_drvdata(pci_dev);
4576 struct fe_priv *np = netdev_priv(dev);
4577 u8 __iomem *base = get_hwbase(dev);
4424 4578
4425 unregister_netdev(dev); 4579 unregister_netdev(dev);
4426 4580
4581 /* special op: write back the misordered MAC address - otherwise
4582 * the next nv_probe would see a wrong address.
4583 */
4584 writel(np->orig_mac[0], base + NvRegMacAddrA);
4585 writel(np->orig_mac[1], base + NvRegMacAddrB);
4586
4427 /* free all structures */ 4587 /* free all structures */
4428 free_rings(dev); 4588 free_rings(dev);
4429 iounmap(get_hwbase(dev)); 4589 iounmap(get_hwbase(dev));
@@ -4540,7 +4700,7 @@ static struct pci_driver driver = {
4540static int __init init_nic(void) 4700static int __init init_nic(void)
4541{ 4701{
4542 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); 4702 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4543 return pci_module_init(&driver); 4703 return pci_register_driver(&driver);
4544} 4704}
4545 4705
4546static void __exit exit_nic(void) 4706static void __exit exit_nic(void)
diff --git a/drivers/net/hp100.c b/drivers/net/hp100.c
index e7d9bf330287..ff5a67d619bb 100644
--- a/drivers/net/hp100.c
+++ b/drivers/net/hp100.c
@@ -111,7 +111,6 @@
111#include <linux/etherdevice.h> 111#include <linux/etherdevice.h>
112#include <linux/skbuff.h> 112#include <linux/skbuff.h>
113#include <linux/types.h> 113#include <linux/types.h>
114#include <linux/config.h> /* for CONFIG_PCI */
115#include <linux/delay.h> 114#include <linux/delay.h>
116#include <linux/init.h> 115#include <linux/init.h>
117#include <linux/bitops.h> 116#include <linux/bitops.h>
diff --git a/drivers/net/irda/mcs7780.c b/drivers/net/irda/mcs7780.c
index 47f6f64d604c..415ba8dc94ce 100644
--- a/drivers/net/irda/mcs7780.c
+++ b/drivers/net/irda/mcs7780.c
@@ -45,7 +45,6 @@
45 45
46#include <linux/module.h> 46#include <linux/module.h>
47#include <linux/moduleparam.h> 47#include <linux/moduleparam.h>
48#include <linux/config.h>
49#include <linux/kernel.h> 48#include <linux/kernel.h>
50#include <linux/types.h> 49#include <linux/types.h>
51#include <linux/errno.h> 50#include <linux/errno.h>
diff --git a/drivers/net/irda/w83977af_ir.c b/drivers/net/irda/w83977af_ir.c
index 0ea65c4c6f85..b69776e00951 100644
--- a/drivers/net/irda/w83977af_ir.c
+++ b/drivers/net/irda/w83977af_ir.c
@@ -40,7 +40,6 @@
40 ********************************************************************/ 40 ********************************************************************/
41 41
42#include <linux/module.h> 42#include <linux/module.h>
43#include <linux/config.h>
44#include <linux/kernel.h> 43#include <linux/kernel.h>
45#include <linux/types.h> 44#include <linux/types.h>
46#include <linux/skbuff.h> 45#include <linux/skbuff.h>
diff --git a/drivers/net/ixgb/ixgb.h b/drivers/net/ixgb/ixgb.h
index 82b67af54c94..a51604b3651f 100644
--- a/drivers/net/ixgb/ixgb.h
+++ b/drivers/net/ixgb/ixgb.h
@@ -110,9 +110,6 @@ struct ixgb_adapter;
110#define IXGB_RXBUFFER_8192 8192 110#define IXGB_RXBUFFER_8192 8192
111#define IXGB_RXBUFFER_16384 16384 111#define IXGB_RXBUFFER_16384 16384
112 112
113/* How many Tx Descriptors do we need to call netif_wake_queue? */
114#define IXGB_TX_QUEUE_WAKE 16
115
116/* How many Rx Buffers do we bundle into one write to the hardware ? */ 113/* How many Rx Buffers do we bundle into one write to the hardware ? */
117#define IXGB_RX_BUFFER_WRITE 4 /* Must be power of 2 */ 114#define IXGB_RX_BUFFER_WRITE 4 /* Must be power of 2 */
118 115
@@ -173,7 +170,7 @@ struct ixgb_adapter {
173 unsigned long led_status; 170 unsigned long led_status;
174 171
175 /* TX */ 172 /* TX */
176 struct ixgb_desc_ring tx_ring; 173 struct ixgb_desc_ring tx_ring ____cacheline_aligned_in_smp;
177 unsigned long timeo_start; 174 unsigned long timeo_start;
178 uint32_t tx_cmd_type; 175 uint32_t tx_cmd_type;
179 uint64_t hw_csum_tx_good; 176 uint64_t hw_csum_tx_good;
diff --git a/drivers/net/ixgb/ixgb_ethtool.c b/drivers/net/ixgb/ixgb_ethtool.c
index cf19b898ba9b..ba621083830a 100644
--- a/drivers/net/ixgb/ixgb_ethtool.c
+++ b/drivers/net/ixgb/ixgb_ethtool.c
@@ -654,11 +654,7 @@ ixgb_phys_id(struct net_device *netdev, uint32_t data)
654 654
655 mod_timer(&adapter->blink_timer, jiffies); 655 mod_timer(&adapter->blink_timer, jiffies);
656 656
657 if (data) 657 msleep_interruptible(data * 1000);
658 schedule_timeout_interruptible(data * HZ);
659 else
660 schedule_timeout_interruptible(MAX_SCHEDULE_TIMEOUT);
661
662 del_timer_sync(&adapter->blink_timer); 658 del_timer_sync(&adapter->blink_timer);
663 ixgb_led_off(&adapter->hw); 659 ixgb_led_off(&adapter->hw);
664 clear_bit(IXGB_LED_ON, &adapter->led_status); 660 clear_bit(IXGB_LED_ON, &adapter->led_status);
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
index f7fa10e47fa2..2b1515574faf 100644
--- a/drivers/net/ixgb/ixgb_hw.c
+++ b/drivers/net/ixgb/ixgb_hw.c
@@ -236,6 +236,17 @@ ixgb_identify_phy(struct ixgb_hw *hw)
236 DEBUGOUT("Identified G6104 optics\n"); 236 DEBUGOUT("Identified G6104 optics\n");
237 phy_type = ixgb_phy_type_g6104; 237 phy_type = ixgb_phy_type_g6104;
238 break; 238 break;
239 case IXGB_DEVICE_ID_82597EX_CX4:
240 DEBUGOUT("Identified CX4\n");
241 xpak_vendor = ixgb_identify_xpak_vendor(hw);
242 if (xpak_vendor == ixgb_xpak_vendor_intel) {
243 DEBUGOUT("Identified TXN17201 optics\n");
244 phy_type = ixgb_phy_type_txn17201;
245 } else {
246 DEBUGOUT("Identified G6005 optics\n");
247 phy_type = ixgb_phy_type_g6005;
248 }
249 break;
239 default: 250 default:
240 DEBUGOUT("Unknown physical layer module\n"); 251 DEBUGOUT("Unknown physical layer module\n");
241 phy_type = ixgb_phy_type_unknown; 252 phy_type = ixgb_phy_type_unknown;
diff --git a/drivers/net/ixgb/ixgb_ids.h b/drivers/net/ixgb/ixgb_ids.h
index 40a085f94c7b..9fd61189b4b2 100644
--- a/drivers/net/ixgb/ixgb_ids.h
+++ b/drivers/net/ixgb/ixgb_ids.h
@@ -45,6 +45,7 @@
45 45
46#define IXGB_DEVICE_ID_82597EX_CX4 0x109E 46#define IXGB_DEVICE_ID_82597EX_CX4 0x109E
47#define IXGB_SUBDEVICE_ID_A00C 0xA00C 47#define IXGB_SUBDEVICE_ID_A00C 0xA00C
48#define IXGB_SUBDEVICE_ID_A01C 0xA01C
48 49
49#endif /* #ifndef _IXGB_IDS_H_ */ 50#endif /* #ifndef _IXGB_IDS_H_ */
50/* End of File */ 51/* End of File */
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index 7bbd447289b5..e36dee1dd333 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -36,7 +36,7 @@ static char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver";
36#else 36#else
37#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
38#endif 38#endif
39#define DRV_VERSION "1.0.109-k2"DRIVERNAPI 39#define DRV_VERSION "1.0.112-k2"DRIVERNAPI
40char ixgb_driver_version[] = DRV_VERSION; 40char ixgb_driver_version[] = DRV_VERSION;
41static char ixgb_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char ixgb_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
42 42
@@ -118,15 +118,26 @@ static void ixgb_restore_vlan(struct ixgb_adapter *adapter);
118static void ixgb_netpoll(struct net_device *dev); 118static void ixgb_netpoll(struct net_device *dev);
119#endif 119#endif
120 120
121/* Exported from other modules */ 121static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
122 enum pci_channel_state state);
123static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev);
124static void ixgb_io_resume (struct pci_dev *pdev);
122 125
126/* Exported from other modules */
123extern void ixgb_check_options(struct ixgb_adapter *adapter); 127extern void ixgb_check_options(struct ixgb_adapter *adapter);
124 128
129static struct pci_error_handlers ixgb_err_handler = {
130 .error_detected = ixgb_io_error_detected,
131 .slot_reset = ixgb_io_slot_reset,
132 .resume = ixgb_io_resume,
133};
134
125static struct pci_driver ixgb_driver = { 135static struct pci_driver ixgb_driver = {
126 .name = ixgb_driver_name, 136 .name = ixgb_driver_name,
127 .id_table = ixgb_pci_tbl, 137 .id_table = ixgb_pci_tbl,
128 .probe = ixgb_probe, 138 .probe = ixgb_probe,
129 .remove = __devexit_p(ixgb_remove), 139 .remove = __devexit_p(ixgb_remove),
140 .err_handler = &ixgb_err_handler
130}; 141};
131 142
132MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 143MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
@@ -140,12 +151,12 @@ module_param(debug, int, 0);
140MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 151MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
141 152
142/* some defines for controlling descriptor fetches in h/w */ 153/* some defines for controlling descriptor fetches in h/w */
143#define RXDCTL_WTHRESH_DEFAULT 16 /* chip writes back at this many or RXT0 */ 154#define RXDCTL_WTHRESH_DEFAULT 15 /* chip writes back at this many or RXT0 */
144#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below 155#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below
145 * this */ 156 * this */
146#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail 157#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail
147 * is pushed this many descriptors 158 * is pushed this many descriptors
148 * from head */ 159 * from head */
149 160
150/** 161/**
151 * ixgb_init_module - Driver Registration Routine 162 * ixgb_init_module - Driver Registration Routine
@@ -162,7 +173,7 @@ ixgb_init_module(void)
162 173
163 printk(KERN_INFO "%s\n", ixgb_copyright); 174 printk(KERN_INFO "%s\n", ixgb_copyright);
164 175
165 return pci_module_init(&ixgb_driver); 176 return pci_register_driver(&ixgb_driver);
166} 177}
167 178
168module_init(ixgb_init_module); 179module_init(ixgb_init_module);
@@ -1174,6 +1185,7 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1174 int err; 1185 int err;
1175 1186
1176 if (likely(skb_is_gso(skb))) { 1187 if (likely(skb_is_gso(skb))) {
1188 struct ixgb_buffer *buffer_info;
1177 if (skb_header_cloned(skb)) { 1189 if (skb_header_cloned(skb)) {
1178 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 1190 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1179 if (err) 1191 if (err)
@@ -1196,6 +1208,8 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1196 1208
1197 i = adapter->tx_ring.next_to_use; 1209 i = adapter->tx_ring.next_to_use;
1198 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i); 1210 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
1211 buffer_info = &adapter->tx_ring.buffer_info[i];
1212 WARN_ON(buffer_info->dma != 0);
1199 1213
1200 context_desc->ipcss = ipcss; 1214 context_desc->ipcss = ipcss;
1201 context_desc->ipcso = ipcso; 1215 context_desc->ipcso = ipcso;
@@ -1233,11 +1247,14 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
1233 uint8_t css, cso; 1247 uint8_t css, cso;
1234 1248
1235 if(likely(skb->ip_summed == CHECKSUM_HW)) { 1249 if(likely(skb->ip_summed == CHECKSUM_HW)) {
1250 struct ixgb_buffer *buffer_info;
1236 css = skb->h.raw - skb->data; 1251 css = skb->h.raw - skb->data;
1237 cso = (skb->h.raw + skb->csum) - skb->data; 1252 cso = (skb->h.raw + skb->csum) - skb->data;
1238 1253
1239 i = adapter->tx_ring.next_to_use; 1254 i = adapter->tx_ring.next_to_use;
1240 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i); 1255 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
1256 buffer_info = &adapter->tx_ring.buffer_info[i];
1257 WARN_ON(buffer_info->dma != 0);
1241 1258
1242 context_desc->tucss = css; 1259 context_desc->tucss = css;
1243 context_desc->tucso = cso; 1260 context_desc->tucso = cso;
@@ -1283,6 +1300,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1283 buffer_info = &tx_ring->buffer_info[i]; 1300 buffer_info = &tx_ring->buffer_info[i];
1284 size = min(len, IXGB_MAX_DATA_PER_TXD); 1301 size = min(len, IXGB_MAX_DATA_PER_TXD);
1285 buffer_info->length = size; 1302 buffer_info->length = size;
1303 WARN_ON(buffer_info->dma != 0);
1286 buffer_info->dma = 1304 buffer_info->dma =
1287 pci_map_single(adapter->pdev, 1305 pci_map_single(adapter->pdev,
1288 skb->data + offset, 1306 skb->data + offset,
@@ -1543,6 +1561,11 @@ void
1543ixgb_update_stats(struct ixgb_adapter *adapter) 1561ixgb_update_stats(struct ixgb_adapter *adapter)
1544{ 1562{
1545 struct net_device *netdev = adapter->netdev; 1563 struct net_device *netdev = adapter->netdev;
1564 struct pci_dev *pdev = adapter->pdev;
1565
1566 /* Prevent stats update while adapter is being reset */
1567 if (pdev->error_state && pdev->error_state != pci_channel_io_normal)
1568 return;
1546 1569
1547 if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) || 1570 if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) ||
1548 (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) { 1571 (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) {
@@ -1787,7 +1810,7 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
1787 if (unlikely(netif_queue_stopped(netdev))) { 1810 if (unlikely(netif_queue_stopped(netdev))) {
1788 spin_lock(&adapter->tx_lock); 1811 spin_lock(&adapter->tx_lock);
1789 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev) && 1812 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev) &&
1790 (IXGB_DESC_UNUSED(tx_ring) > IXGB_TX_QUEUE_WAKE)) 1813 (IXGB_DESC_UNUSED(tx_ring) >= DESC_NEEDED))
1791 netif_wake_queue(netdev); 1814 netif_wake_queue(netdev);
1792 spin_unlock(&adapter->tx_lock); 1815 spin_unlock(&adapter->tx_lock);
1793 } 1816 }
@@ -1948,10 +1971,9 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1948#define IXGB_CB_LENGTH 256 1971#define IXGB_CB_LENGTH 256
1949 if (length < IXGB_CB_LENGTH) { 1972 if (length < IXGB_CB_LENGTH) {
1950 struct sk_buff *new_skb = 1973 struct sk_buff *new_skb =
1951 dev_alloc_skb(length + NET_IP_ALIGN); 1974 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
1952 if (new_skb) { 1975 if (new_skb) {
1953 skb_reserve(new_skb, NET_IP_ALIGN); 1976 skb_reserve(new_skb, NET_IP_ALIGN);
1954 new_skb->dev = netdev;
1955 memcpy(new_skb->data - NET_IP_ALIGN, 1977 memcpy(new_skb->data - NET_IP_ALIGN,
1956 skb->data - NET_IP_ALIGN, 1978 skb->data - NET_IP_ALIGN,
1957 length + NET_IP_ALIGN); 1979 length + NET_IP_ALIGN);
@@ -2031,14 +2053,14 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
2031 /* leave three descriptors unused */ 2053 /* leave three descriptors unused */
2032 while(--cleancount > 2) { 2054 while(--cleancount > 2) {
2033 /* recycle! its good for you */ 2055 /* recycle! its good for you */
2034 if (!(skb = buffer_info->skb)) 2056 skb = buffer_info->skb;
2035 skb = dev_alloc_skb(adapter->rx_buffer_len 2057 if (skb) {
2036 + NET_IP_ALIGN);
2037 else {
2038 skb_trim(skb, 0); 2058 skb_trim(skb, 0);
2039 goto map_skb; 2059 goto map_skb;
2040 } 2060 }
2041 2061
2062 skb = netdev_alloc_skb(netdev, adapter->rx_buffer_len
2063 + NET_IP_ALIGN);
2042 if (unlikely(!skb)) { 2064 if (unlikely(!skb)) {
2043 /* Better luck next round */ 2065 /* Better luck next round */
2044 adapter->alloc_rx_buff_failed++; 2066 adapter->alloc_rx_buff_failed++;
@@ -2051,8 +2073,6 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
2051 */ 2073 */
2052 skb_reserve(skb, NET_IP_ALIGN); 2074 skb_reserve(skb, NET_IP_ALIGN);
2053 2075
2054 skb->dev = netdev;
2055
2056 buffer_info->skb = skb; 2076 buffer_info->skb = skb;
2057 buffer_info->length = adapter->rx_buffer_len; 2077 buffer_info->length = adapter->rx_buffer_len;
2058map_skb: 2078map_skb:
@@ -2190,7 +2210,7 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter)
2190 2210
2191static void ixgb_netpoll(struct net_device *dev) 2211static void ixgb_netpoll(struct net_device *dev)
2192{ 2212{
2193 struct ixgb_adapter *adapter = dev->priv; 2213 struct ixgb_adapter *adapter = netdev_priv(dev);
2194 2214
2195 disable_irq(adapter->pdev->irq); 2215 disable_irq(adapter->pdev->irq);
2196 ixgb_intr(adapter->pdev->irq, dev, NULL); 2216 ixgb_intr(adapter->pdev->irq, dev, NULL);
@@ -2198,4 +2218,98 @@ static void ixgb_netpoll(struct net_device *dev)
2198} 2218}
2199#endif 2219#endif
2200 2220
2221/**
2222 * ixgb_io_error_detected() - called when PCI error is detected
2223 * @pdev pointer to pci device with error
2224 * @state pci channel state after error
2225 *
2226 * This callback is called by the PCI subsystem whenever
2227 * a PCI bus error is detected.
2228 */
2229static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
2230 enum pci_channel_state state)
2231{
2232 struct net_device *netdev = pci_get_drvdata(pdev);
2233 struct ixgb_adapter *adapter = netdev->priv;
2234
2235 if(netif_running(netdev))
2236 ixgb_down(adapter, TRUE);
2237
2238 pci_disable_device(pdev);
2239
2240 /* Request a slot reset. */
2241 return PCI_ERS_RESULT_NEED_RESET;
2242}
2243
2244/**
2245 * ixgb_io_slot_reset - called after the pci bus has been reset.
2246 * @pdev pointer to pci device with error
2247 *
2248 * This callback is called after the PCI buss has been reset.
2249 * Basically, this tries to restart the card from scratch.
2250 * This is a shortened version of the device probe/discovery code,
2251 * it resembles the first-half of the ixgb_probe() routine.
2252 */
2253static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev)
2254{
2255 struct net_device *netdev = pci_get_drvdata(pdev);
2256 struct ixgb_adapter *adapter = netdev->priv;
2257
2258 if(pci_enable_device(pdev)) {
2259 DPRINTK(PROBE, ERR, "Cannot re-enable PCI device after reset.\n");
2260 return PCI_ERS_RESULT_DISCONNECT;
2261 }
2262
2263 /* Perform card reset only on one instance of the card */
2264 if (0 != PCI_FUNC (pdev->devfn))
2265 return PCI_ERS_RESULT_RECOVERED;
2266
2267 pci_set_master(pdev);
2268
2269 netif_carrier_off(netdev);
2270 netif_stop_queue(netdev);
2271 ixgb_reset(adapter);
2272
2273 /* Make sure the EEPROM is good */
2274 if(!ixgb_validate_eeprom_checksum(&adapter->hw)) {
2275 DPRINTK(PROBE, ERR, "After reset, the EEPROM checksum is not valid.\n");
2276 return PCI_ERS_RESULT_DISCONNECT;
2277 }
2278 ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
2279 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
2280
2281 if(!is_valid_ether_addr(netdev->perm_addr)) {
2282 DPRINTK(PROBE, ERR, "After reset, invalid MAC address.\n");
2283 return PCI_ERS_RESULT_DISCONNECT;
2284 }
2285
2286 return PCI_ERS_RESULT_RECOVERED;
2287}
2288
2289/**
2290 * ixgb_io_resume - called when its OK to resume normal operations
2291 * @pdev pointer to pci device with error
2292 *
2293 * The error recovery driver tells us that its OK to resume
2294 * normal operation. Implementation resembles the second-half
2295 * of the ixgb_probe() routine.
2296 */
2297static void ixgb_io_resume (struct pci_dev *pdev)
2298{
2299 struct net_device *netdev = pci_get_drvdata(pdev);
2300 struct ixgb_adapter *adapter = netdev->priv;
2301
2302 pci_set_master(pdev);
2303
2304 if(netif_running(netdev)) {
2305 if(ixgb_up(adapter)) {
2306 printk ("ixgb: can't bring device back up after reset\n");
2307 return;
2308 }
2309 }
2310
2311 netif_device_attach(netdev);
2312 mod_timer(&adapter->watchdog_timer, jiffies);
2313}
2314
2201/* ixgb_main.c */ 2315/* ixgb_main.c */
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 9bdd43ab3573..b19e2034d11f 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -187,11 +187,14 @@ struct myri10ge_priv {
187 u8 mac_addr[6]; /* eeprom mac address */ 187 u8 mac_addr[6]; /* eeprom mac address */
188 unsigned long serial_number; 188 unsigned long serial_number;
189 int vendor_specific_offset; 189 int vendor_specific_offset;
190 int fw_multicast_support;
190 u32 devctl; 191 u32 devctl;
191 u16 msi_flags; 192 u16 msi_flags;
192 u32 read_dma; 193 u32 read_dma;
193 u32 write_dma; 194 u32 write_dma;
194 u32 read_write_dma; 195 u32 read_write_dma;
196 u32 link_changes;
197 u32 msg_enable;
195}; 198};
196 199
197static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat"; 200static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
@@ -257,6 +260,12 @@ module_param(myri10ge_max_irq_loops, int, S_IRUGO);
257MODULE_PARM_DESC(myri10ge_max_irq_loops, 260MODULE_PARM_DESC(myri10ge_max_irq_loops,
258 "Set stuck legacy IRQ detection threshold\n"); 261 "Set stuck legacy IRQ detection threshold\n");
259 262
263#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
264
265static int myri10ge_debug = -1; /* defaults above */
266module_param(myri10ge_debug, int, 0);
267MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
268
260#define MYRI10GE_FW_OFFSET 1024*1024 269#define MYRI10GE_FW_OFFSET 1024*1024
261#define MYRI10GE_HIGHPART_TO_U32(X) \ 270#define MYRI10GE_HIGHPART_TO_U32(X) \
262(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0) 271(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
@@ -271,7 +280,7 @@ myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
271 struct mcp_cmd *buf; 280 struct mcp_cmd *buf;
272 char buf_bytes[sizeof(*buf) + 8]; 281 char buf_bytes[sizeof(*buf) + 8];
273 struct mcp_cmd_response *response = mgp->cmd; 282 struct mcp_cmd_response *response = mgp->cmd;
274 char __iomem *cmd_addr = mgp->sram + MXGEFW_CMD_OFFSET; 283 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
275 u32 dma_low, dma_high, result, value; 284 u32 dma_low, dma_high, result, value;
276 int sleep_total = 0; 285 int sleep_total = 0;
277 286
@@ -320,6 +329,8 @@ myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
320 if (result == 0) { 329 if (result == 0) {
321 data->data0 = value; 330 data->data0 = value;
322 return 0; 331 return 0;
332 } else if (result == MXGEFW_CMD_UNKNOWN) {
333 return -ENOSYS;
323 } else { 334 } else {
324 dev_err(&mgp->pdev->dev, 335 dev_err(&mgp->pdev->dev,
325 "command %d failed, result = %d\n", 336 "command %d failed, result = %d\n",
@@ -404,7 +415,7 @@ static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
404 buf[4] = htonl(dma_low); /* dummy addr LSW */ 415 buf[4] = htonl(dma_low); /* dummy addr LSW */
405 buf[5] = htonl(enable); /* enable? */ 416 buf[5] = htonl(enable); /* enable? */
406 417
407 submit = mgp->sram + 0xfc01c0; 418 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
408 419
409 myri10ge_pio_copy(submit, &buf, sizeof(buf)); 420 myri10ge_pio_copy(submit, &buf, sizeof(buf));
410 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++) 421 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
@@ -600,7 +611,7 @@ static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
600 buf[5] = htonl(8); /* where to copy to */ 611 buf[5] = htonl(8); /* where to copy to */
601 buf[6] = htonl(0); /* where to jump to */ 612 buf[6] = htonl(0); /* where to jump to */
602 613
603 submit = mgp->sram + 0xfc0000; 614 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
604 615
605 myri10ge_pio_copy(submit, &buf, sizeof(buf)); 616 myri10ge_pio_copy(submit, &buf, sizeof(buf));
606 mb(); 617 mb();
@@ -764,6 +775,7 @@ static int myri10ge_reset(struct myri10ge_priv *mgp)
764 mgp->rx_small.cnt = 0; 775 mgp->rx_small.cnt = 0;
765 mgp->rx_done.idx = 0; 776 mgp->rx_done.idx = 0;
766 mgp->rx_done.cnt = 0; 777 mgp->rx_done.cnt = 0;
778 mgp->link_changes = 0;
767 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr); 779 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
768 myri10ge_change_promisc(mgp, 0, 0); 780 myri10ge_change_promisc(mgp, 0, 0);
769 myri10ge_change_pause(mgp, mgp->pause); 781 myri10ge_change_pause(mgp, mgp->pause);
@@ -798,12 +810,13 @@ myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
798 * pages directly and building a fraglist in the near future. 810 * pages directly and building a fraglist in the near future.
799 */ 811 */
800 812
801static inline struct sk_buff *myri10ge_alloc_big(int bytes) 813static inline struct sk_buff *myri10ge_alloc_big(struct net_device *dev,
814 int bytes)
802{ 815{
803 struct sk_buff *skb; 816 struct sk_buff *skb;
804 unsigned long data, roundup; 817 unsigned long data, roundup;
805 818
806 skb = dev_alloc_skb(bytes + 4096 + MXGEFW_PAD); 819 skb = netdev_alloc_skb(dev, bytes + 4096 + MXGEFW_PAD);
807 if (skb == NULL) 820 if (skb == NULL)
808 return NULL; 821 return NULL;
809 822
@@ -821,12 +834,13 @@ static inline struct sk_buff *myri10ge_alloc_big(int bytes)
821 834
822/* Allocate 2x as much space as required and use whichever portion 835/* Allocate 2x as much space as required and use whichever portion
823 * does not cross a 4KB boundary */ 836 * does not cross a 4KB boundary */
824static inline struct sk_buff *myri10ge_alloc_small_safe(unsigned int bytes) 837static inline struct sk_buff *myri10ge_alloc_small_safe(struct net_device *dev,
838 unsigned int bytes)
825{ 839{
826 struct sk_buff *skb; 840 struct sk_buff *skb;
827 unsigned long data, boundary; 841 unsigned long data, boundary;
828 842
829 skb = dev_alloc_skb(2 * (bytes + MXGEFW_PAD) - 1); 843 skb = netdev_alloc_skb(dev, 2 * (bytes + MXGEFW_PAD) - 1);
830 if (unlikely(skb == NULL)) 844 if (unlikely(skb == NULL))
831 return NULL; 845 return NULL;
832 846
@@ -847,12 +861,13 @@ static inline struct sk_buff *myri10ge_alloc_small_safe(unsigned int bytes)
847 861
848/* Allocate just enough space, and verify that the allocated 862/* Allocate just enough space, and verify that the allocated
849 * space does not cross a 4KB boundary */ 863 * space does not cross a 4KB boundary */
850static inline struct sk_buff *myri10ge_alloc_small(int bytes) 864static inline struct sk_buff *myri10ge_alloc_small(struct net_device *dev,
865 int bytes)
851{ 866{
852 struct sk_buff *skb; 867 struct sk_buff *skb;
853 unsigned long roundup, data, end; 868 unsigned long roundup, data, end;
854 869
855 skb = dev_alloc_skb(bytes + 16 + MXGEFW_PAD); 870 skb = netdev_alloc_skb(dev, bytes + 16 + MXGEFW_PAD);
856 if (unlikely(skb == NULL)) 871 if (unlikely(skb == NULL))
857 return NULL; 872 return NULL;
858 873
@@ -868,15 +883,17 @@ static inline struct sk_buff *myri10ge_alloc_small(int bytes)
868 "myri10ge_alloc_small: small skb crossed 4KB boundary\n"); 883 "myri10ge_alloc_small: small skb crossed 4KB boundary\n");
869 myri10ge_skb_cross_4k = 1; 884 myri10ge_skb_cross_4k = 1;
870 dev_kfree_skb_any(skb); 885 dev_kfree_skb_any(skb);
871 skb = myri10ge_alloc_small_safe(bytes); 886 skb = myri10ge_alloc_small_safe(dev, bytes);
872 } 887 }
873 return skb; 888 return skb;
874} 889}
875 890
876static inline int 891static inline int
877myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct pci_dev *pdev, int bytes, 892myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct myri10ge_priv *mgp,
878 int idx) 893 int bytes, int idx)
879{ 894{
895 struct net_device *dev = mgp->dev;
896 struct pci_dev *pdev = mgp->pdev;
880 struct sk_buff *skb; 897 struct sk_buff *skb;
881 dma_addr_t bus; 898 dma_addr_t bus;
882 int len, retval = 0; 899 int len, retval = 0;
@@ -884,11 +901,11 @@ myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct pci_dev *pdev, int bytes,
884 bytes += VLAN_HLEN; /* account for 802.1q vlan tag */ 901 bytes += VLAN_HLEN; /* account for 802.1q vlan tag */
885 902
886 if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ ) 903 if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ )
887 skb = myri10ge_alloc_big(bytes); 904 skb = myri10ge_alloc_big(dev, bytes);
888 else if (myri10ge_skb_cross_4k) 905 else if (myri10ge_skb_cross_4k)
889 skb = myri10ge_alloc_small_safe(bytes); 906 skb = myri10ge_alloc_small_safe(dev, bytes);
890 else 907 else
891 skb = myri10ge_alloc_small(bytes); 908 skb = myri10ge_alloc_small(dev, bytes);
892 909
893 if (unlikely(skb == NULL)) { 910 if (unlikely(skb == NULL)) {
894 rx->alloc_fail++; 911 rx->alloc_fail++;
@@ -951,7 +968,7 @@ myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
951 unmap_len = pci_unmap_len(&rx->info[idx], len); 968 unmap_len = pci_unmap_len(&rx->info[idx], len);
952 969
953 /* try to replace the received skb */ 970 /* try to replace the received skb */
954 if (myri10ge_getbuf(rx, mgp->pdev, bytes, idx)) { 971 if (myri10ge_getbuf(rx, mgp, bytes, idx)) {
955 /* drop the frame -- the old skbuf is re-cycled */ 972 /* drop the frame -- the old skbuf is re-cycled */
956 mgp->stats.rx_dropped += 1; 973 mgp->stats.rx_dropped += 1;
957 return 0; 974 return 0;
@@ -968,7 +985,6 @@ myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
968 skb_put(skb, len); 985 skb_put(skb, len);
969 986
970 skb->protocol = eth_type_trans(skb, mgp->dev); 987 skb->protocol = eth_type_trans(skb, mgp->dev);
971 skb->dev = mgp->dev;
972 if (mgp->csum_flag) { 988 if (mgp->csum_flag) {
973 if ((skb->protocol == ntohs(ETH_P_IP)) || 989 if ((skb->protocol == ntohs(ETH_P_IP)) ||
974 (skb->protocol == ntohs(ETH_P_IPV6))) { 990 (skb->protocol == ntohs(ETH_P_IPV6))) {
@@ -1081,13 +1097,19 @@ static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1081 if (mgp->link_state != stats->link_up) { 1097 if (mgp->link_state != stats->link_up) {
1082 mgp->link_state = stats->link_up; 1098 mgp->link_state = stats->link_up;
1083 if (mgp->link_state) { 1099 if (mgp->link_state) {
1084 printk(KERN_INFO "myri10ge: %s: link up\n", 1100 if (netif_msg_link(mgp))
1085 mgp->dev->name); 1101 printk(KERN_INFO
1102 "myri10ge: %s: link up\n",
1103 mgp->dev->name);
1086 netif_carrier_on(mgp->dev); 1104 netif_carrier_on(mgp->dev);
1105 mgp->link_changes++;
1087 } else { 1106 } else {
1088 printk(KERN_INFO "myri10ge: %s: link down\n", 1107 if (netif_msg_link(mgp))
1089 mgp->dev->name); 1108 printk(KERN_INFO
1109 "myri10ge: %s: link down\n",
1110 mgp->dev->name);
1090 netif_carrier_off(mgp->dev); 1111 netif_carrier_off(mgp->dev);
1112 mgp->link_changes++;
1091 } 1113 }
1092 } 1114 }
1093 if (mgp->rdma_tags_available != 1115 if (mgp->rdma_tags_available !=
@@ -1289,7 +1311,8 @@ static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1289 "serial_number", "tx_pkt_start", "tx_pkt_done", 1311 "serial_number", "tx_pkt_start", "tx_pkt_done",
1290 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt", 1312 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1291 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized", 1313 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1292 "link_up", "dropped_link_overflow", "dropped_link_error_or_filtered", 1314 "link_changes", "link_up", "dropped_link_overflow",
1315 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
1293 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer", 1316 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1294 "dropped_no_big_buffer" 1317 "dropped_no_big_buffer"
1295}; 1318};
@@ -1341,16 +1364,31 @@ myri10ge_get_ethtool_stats(struct net_device *netdev,
1341 data[i++] = (unsigned int)mgp->stop_queue; 1364 data[i++] = (unsigned int)mgp->stop_queue;
1342 data[i++] = (unsigned int)mgp->watchdog_resets; 1365 data[i++] = (unsigned int)mgp->watchdog_resets;
1343 data[i++] = (unsigned int)mgp->tx_linearized; 1366 data[i++] = (unsigned int)mgp->tx_linearized;
1367 data[i++] = (unsigned int)mgp->link_changes;
1344 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up); 1368 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1345 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow); 1369 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1346 data[i++] = 1370 data[i++] =
1347 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered); 1371 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1372 data[i++] =
1373 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1348 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt); 1374 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1349 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun); 1375 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1350 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer); 1376 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1351 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer); 1377 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1352} 1378}
1353 1379
1380static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1381{
1382 struct myri10ge_priv *mgp = netdev_priv(netdev);
1383 mgp->msg_enable = value;
1384}
1385
1386static u32 myri10ge_get_msglevel(struct net_device *netdev)
1387{
1388 struct myri10ge_priv *mgp = netdev_priv(netdev);
1389 return mgp->msg_enable;
1390}
1391
1354static struct ethtool_ops myri10ge_ethtool_ops = { 1392static struct ethtool_ops myri10ge_ethtool_ops = {
1355 .get_settings = myri10ge_get_settings, 1393 .get_settings = myri10ge_get_settings,
1356 .get_drvinfo = myri10ge_get_drvinfo, 1394 .get_drvinfo = myri10ge_get_drvinfo,
@@ -1371,7 +1409,9 @@ static struct ethtool_ops myri10ge_ethtool_ops = {
1371#endif 1409#endif
1372 .get_strings = myri10ge_get_strings, 1410 .get_strings = myri10ge_get_strings,
1373 .get_stats_count = myri10ge_get_stats_count, 1411 .get_stats_count = myri10ge_get_stats_count,
1374 .get_ethtool_stats = myri10ge_get_ethtool_stats 1412 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1413 .set_msglevel = myri10ge_set_msglevel,
1414 .get_msglevel = myri10ge_get_msglevel
1375}; 1415};
1376 1416
1377static int myri10ge_allocate_rings(struct net_device *dev) 1417static int myri10ge_allocate_rings(struct net_device *dev)
@@ -1439,7 +1479,7 @@ static int myri10ge_allocate_rings(struct net_device *dev)
1439 /* Fill the receive rings */ 1479 /* Fill the receive rings */
1440 1480
1441 for (i = 0; i <= mgp->rx_small.mask; i++) { 1481 for (i = 0; i <= mgp->rx_small.mask; i++) {
1442 status = myri10ge_getbuf(&mgp->rx_small, mgp->pdev, 1482 status = myri10ge_getbuf(&mgp->rx_small, mgp,
1443 mgp->small_bytes, i); 1483 mgp->small_bytes, i);
1444 if (status) { 1484 if (status) {
1445 printk(KERN_ERR 1485 printk(KERN_ERR
@@ -1451,8 +1491,7 @@ static int myri10ge_allocate_rings(struct net_device *dev)
1451 1491
1452 for (i = 0; i <= mgp->rx_big.mask; i++) { 1492 for (i = 0; i <= mgp->rx_big.mask; i++) {
1453 status = 1493 status =
1454 myri10ge_getbuf(&mgp->rx_big, mgp->pdev, 1494 myri10ge_getbuf(&mgp->rx_big, mgp, dev->mtu + ETH_HLEN, i);
1455 dev->mtu + ETH_HLEN, i);
1456 if (status) { 1495 if (status) {
1457 printk(KERN_ERR 1496 printk(KERN_ERR
1458 "myri10ge: %s: alloced only %d big bufs\n", 1497 "myri10ge: %s: alloced only %d big bufs\n",
@@ -1648,9 +1687,11 @@ static int myri10ge_open(struct net_device *dev)
1648 } 1687 }
1649 1688
1650 if (mgp->mtrr >= 0) { 1689 if (mgp->mtrr >= 0) {
1651 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + 0x200000; 1690 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1652 mgp->rx_small.wc_fifo = (u8 __iomem *) mgp->sram + 0x300000; 1691 mgp->rx_small.wc_fifo =
1653 mgp->rx_big.wc_fifo = (u8 __iomem *) mgp->sram + 0x340000; 1692 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1693 mgp->rx_big.wc_fifo =
1694 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1654 } else { 1695 } else {
1655 mgp->tx.wc_fifo = NULL; 1696 mgp->tx.wc_fifo = NULL;
1656 mgp->rx_small.wc_fifo = NULL; 1697 mgp->rx_small.wc_fifo = NULL;
@@ -1686,7 +1727,21 @@ static int myri10ge_open(struct net_device *dev)
1686 1727
1687 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus); 1728 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1688 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus); 1729 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1689 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA, &cmd, 0); 1730 cmd.data2 = sizeof(struct mcp_irq_data);
1731 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1732 if (status == -ENOSYS) {
1733 dma_addr_t bus = mgp->fw_stats_bus;
1734 bus += offsetof(struct mcp_irq_data, send_done_count);
1735 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1736 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1737 status = myri10ge_send_cmd(mgp,
1738 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1739 &cmd, 0);
1740 /* Firmware cannot support multicast without STATS_DMA_V2 */
1741 mgp->fw_multicast_support = 0;
1742 } else {
1743 mgp->fw_multicast_support = 1;
1744 }
1690 if (status) { 1745 if (status) {
1691 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n", 1746 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1692 dev->name); 1747 dev->name);
@@ -1841,7 +1896,8 @@ myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1841 if (cnt > 0) { 1896 if (cnt > 0) {
1842 /* pad it to 64 bytes. The src is 64 bytes bigger than it 1897 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1843 * needs to be so that we don't overrun it */ 1898 * needs to be so that we don't overrun it */
1844 myri10ge_pio_copy(tx->wc_fifo + (cnt << 18), src, 64); 1899 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1900 src, 64);
1845 mb(); 1901 mb();
1846 } 1902 }
1847} 1903}
@@ -2140,9 +2196,81 @@ static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2140 2196
2141static void myri10ge_set_multicast_list(struct net_device *dev) 2197static void myri10ge_set_multicast_list(struct net_device *dev)
2142{ 2198{
2199 struct myri10ge_cmd cmd;
2200 struct myri10ge_priv *mgp;
2201 struct dev_mc_list *mc_list;
2202 int err;
2203
2204 mgp = netdev_priv(dev);
2143 /* can be called from atomic contexts, 2205 /* can be called from atomic contexts,
2144 * pass 1 to force atomicity in myri10ge_send_cmd() */ 2206 * pass 1 to force atomicity in myri10ge_send_cmd() */
2145 myri10ge_change_promisc(netdev_priv(dev), dev->flags & IFF_PROMISC, 1); 2207 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2208
2209 /* This firmware is known to not support multicast */
2210 if (!mgp->fw_multicast_support)
2211 return;
2212
2213 /* Disable multicast filtering */
2214
2215 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2216 if (err != 0) {
2217 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2218 " error status: %d\n", dev->name, err);
2219 goto abort;
2220 }
2221
2222 if (dev->flags & IFF_ALLMULTI) {
2223 /* request to disable multicast filtering, so quit here */
2224 return;
2225 }
2226
2227 /* Flush the filters */
2228
2229 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2230 &cmd, 1);
2231 if (err != 0) {
2232 printk(KERN_ERR
2233 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2234 ", error status: %d\n", dev->name, err);
2235 goto abort;
2236 }
2237
2238 /* Walk the multicast list, and add each address */
2239 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2240 memcpy(&cmd.data0, &mc_list->dmi_addr, 4);
2241 memcpy(&cmd.data1, ((char *)&mc_list->dmi_addr) + 4, 2);
2242 cmd.data0 = htonl(cmd.data0);
2243 cmd.data1 = htonl(cmd.data1);
2244 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2245 &cmd, 1);
2246
2247 if (err != 0) {
2248 printk(KERN_ERR "myri10ge: %s: Failed "
2249 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2250 "%d\t", dev->name, err);
2251 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2252 ((unsigned char *)&mc_list->dmi_addr)[0],
2253 ((unsigned char *)&mc_list->dmi_addr)[1],
2254 ((unsigned char *)&mc_list->dmi_addr)[2],
2255 ((unsigned char *)&mc_list->dmi_addr)[3],
2256 ((unsigned char *)&mc_list->dmi_addr)[4],
2257 ((unsigned char *)&mc_list->dmi_addr)[5]
2258 );
2259 goto abort;
2260 }
2261 }
2262 /* Enable multicast filtering */
2263 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2264 if (err != 0) {
2265 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2266 "error status: %d\n", dev->name, err);
2267 goto abort;
2268 }
2269
2270 return;
2271
2272abort:
2273 return;
2146} 2274}
2147 2275
2148static int myri10ge_set_mac_address(struct net_device *dev, void *addr) 2276static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
@@ -2289,6 +2417,8 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2289 */ 2417 */
2290 2418
2291#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132 2419#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132
2420#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2421#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
2292 2422
2293static void myri10ge_select_firmware(struct myri10ge_priv *mgp) 2423static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2294{ 2424{
@@ -2298,15 +2428,34 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2298 mgp->fw_name = myri10ge_fw_unaligned; 2428 mgp->fw_name = myri10ge_fw_unaligned;
2299 2429
2300 if (myri10ge_force_firmware == 0) { 2430 if (myri10ge_force_firmware == 0) {
2431 int link_width, exp_cap;
2432 u16 lnk;
2433
2434 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2435 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2436 link_width = (lnk >> 4) & 0x3f;
2437
2301 myri10ge_enable_ecrc(mgp); 2438 myri10ge_enable_ecrc(mgp);
2302 2439
2303 /* Check to see if the upstream bridge is known to 2440 /* Check to see if Link is less than 8 or if the
2304 * provide aligned completions */ 2441 * upstream bridge is known to provide aligned
2305 if (bridge 2442 * completions */
2306 /* ServerWorks HT2000/HT1000 */ 2443 if (link_width < 8) {
2307 && bridge->vendor == PCI_VENDOR_ID_SERVERWORKS 2444 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2308 && bridge->device == 2445 link_width);
2309 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) { 2446 mgp->tx.boundary = 4096;
2447 mgp->fw_name = myri10ge_fw_aligned;
2448 } else if (bridge &&
2449 /* ServerWorks HT2000/HT1000 */
2450 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2451 && bridge->device ==
2452 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2453 /* All Intel E5000 PCIE ports */
2454 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2455 && bridge->device >=
2456 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2457 && bridge->device <=
2458 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
2310 dev_info(&mgp->pdev->dev, 2459 dev_info(&mgp->pdev->dev,
2311 "Assuming aligned completions (0x%x:0x%x)\n", 2460 "Assuming aligned completions (0x%x:0x%x)\n",
2312 bridge->vendor, bridge->device); 2461 bridge->vendor, bridge->device);
@@ -2581,6 +2730,7 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2581 mgp->csum_flag = MXGEFW_FLAGS_CKSUM; 2730 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2582 mgp->pause = myri10ge_flow_control; 2731 mgp->pause = myri10ge_flow_control;
2583 mgp->intr_coal_delay = myri10ge_intr_coal_delay; 2732 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2733 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2584 init_waitqueue_head(&mgp->down_wq); 2734 init_waitqueue_head(&mgp->down_wq);
2585 2735
2586 if (pci_enable_device(pdev)) { 2736 if (pci_enable_device(pdev)) {
diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h
index 0a6cae6cb186..9519ae7cd5ec 100644
--- a/drivers/net/myri10ge/myri10ge_mcp.h
+++ b/drivers/net/myri10ge/myri10ge_mcp.h
@@ -91,7 +91,19 @@ struct mcp_kreq_ether_recv {
91 91
92/* Commands */ 92/* Commands */
93 93
94#define MXGEFW_CMD_OFFSET 0xf80000 94#define MXGEFW_BOOT_HANDOFF 0xfc0000
95#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0
96
97#define MXGEFW_ETH_CMD 0xf80000
98#define MXGEFW_ETH_SEND_4 0x200000
99#define MXGEFW_ETH_SEND_1 0x240000
100#define MXGEFW_ETH_SEND_2 0x280000
101#define MXGEFW_ETH_SEND_3 0x2c0000
102#define MXGEFW_ETH_RECV_SMALL 0x300000
103#define MXGEFW_ETH_RECV_BIG 0x340000
104
105#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
106#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
95 107
96enum myri10ge_mcp_cmd_type { 108enum myri10ge_mcp_cmd_type {
97 MXGEFW_CMD_NONE = 0, 109 MXGEFW_CMD_NONE = 0,
@@ -154,7 +166,7 @@ enum myri10ge_mcp_cmd_type {
154 MXGEFW_CMD_SET_MTU, 166 MXGEFW_CMD_SET_MTU,
155 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 167 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */
156 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 168 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */
157 MXGEFW_CMD_SET_STATS_DMA, 169 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */
158 170
159 MXGEFW_ENABLE_PROMISC, 171 MXGEFW_ENABLE_PROMISC,
160 MXGEFW_DISABLE_PROMISC, 172 MXGEFW_DISABLE_PROMISC,
@@ -168,7 +180,26 @@ enum myri10ge_mcp_cmd_type {
168 * data2 = RDMA length (MSH), WDMA length (LSH) 180 * data2 = RDMA length (MSH), WDMA length (LSH)
169 * command return data = repetitions (MSH), 0.5-ms ticks (LSH) 181 * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
170 */ 182 */
171 MXGEFW_DMA_TEST 183 MXGEFW_DMA_TEST,
184
185 MXGEFW_ENABLE_ALLMULTI,
186 MXGEFW_DISABLE_ALLMULTI,
187
188 /* returns MXGEFW_CMD_ERROR_MULTICAST
189 * if there is no room in the cache
190 * data0,MSH(data1) = multicast group address */
191 MXGEFW_JOIN_MULTICAST_GROUP,
192 /* returns MXGEFW_CMD_ERROR_MULTICAST
193 * if the address is not in the cache,
194 * or is equal to FF-FF-FF-FF-FF-FF
195 * data0,MSH(data1) = multicast group address */
196 MXGEFW_LEAVE_MULTICAST_GROUP,
197 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
198
199 MXGEFW_CMD_SET_STATS_DMA_V2,
200 /* data0, data1 = bus addr,
201 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
202 * adding new stuff to mcp_irq_data without changing the ABI */
172}; 203};
173 204
174enum myri10ge_mcp_cmd_status { 205enum myri10ge_mcp_cmd_status {
@@ -180,11 +211,17 @@ enum myri10ge_mcp_cmd_status {
180 MXGEFW_CMD_ERROR_CLOSED, 211 MXGEFW_CMD_ERROR_CLOSED,
181 MXGEFW_CMD_ERROR_HASH_ERROR, 212 MXGEFW_CMD_ERROR_HASH_ERROR,
182 MXGEFW_CMD_ERROR_BAD_PORT, 213 MXGEFW_CMD_ERROR_BAD_PORT,
183 MXGEFW_CMD_ERROR_RESOURCES 214 MXGEFW_CMD_ERROR_RESOURCES,
215 MXGEFW_CMD_ERROR_MULTICAST
184}; 216};
185 217
186/* 40 Bytes */ 218#define MXGEFW_OLD_IRQ_DATA_LEN 40
219
187struct mcp_irq_data { 220struct mcp_irq_data {
221 /* add new counters at the beginning */
222 u32 future_use[5];
223 u32 dropped_multicast_filtered;
224 /* 40 Bytes */
188 u32 send_done_count; 225 u32 send_done_count;
189 226
190 u32 link_up; 227 u32 link_up;
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index db0475a1102f..9510030feeb4 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -3246,7 +3246,7 @@ static int __init natsemi_init_mod (void)
3246 printk(version); 3246 printk(version);
3247#endif 3247#endif
3248 3248
3249 return pci_module_init (&natsemi_driver); 3249 return pci_register_driver(&natsemi_driver);
3250} 3250}
3251 3251
3252static void __exit natsemi_exit_mod (void) 3252static void __exit natsemi_exit_mod (void)
diff --git a/drivers/net/ne2k-pci.c b/drivers/net/ne2k-pci.c
index 34bdba9eec79..654b477b570a 100644
--- a/drivers/net/ne2k-pci.c
+++ b/drivers/net/ne2k-pci.c
@@ -702,7 +702,7 @@ static int __init ne2k_pci_init(void)
702#ifdef MODULE 702#ifdef MODULE
703 printk(version); 703 printk(version);
704#endif 704#endif
705 return pci_module_init (&ne2k_driver); 705 return pci_register_driver(&ne2k_driver);
706} 706}
707 707
708 708
diff --git a/drivers/net/netx-eth.c b/drivers/net/netx-eth.c
index b1311ae82675..30ed9a5a40e0 100644
--- a/drivers/net/netx-eth.c
+++ b/drivers/net/netx-eth.c
@@ -17,7 +17,6 @@
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 18 */
19 19
20#include <linux/config.h>
21#include <linux/init.h> 20#include <linux/init.h>
22#include <linux/module.h> 21#include <linux/module.h>
23#include <linux/kernel.h> 22#include <linux/kernel.h>
diff --git a/drivers/net/ns83820.c b/drivers/net/ns83820.c
index 0e76859c90a2..0dedd34804c3 100644
--- a/drivers/net/ns83820.c
+++ b/drivers/net/ns83820.c
@@ -2178,7 +2178,7 @@ static struct pci_driver driver = {
2178static int __init ns83820_init(void) 2178static int __init ns83820_init(void)
2179{ 2179{
2180 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n"); 2180 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2181 return pci_module_init(&driver); 2181 return pci_register_driver(&driver);
2182} 2182}
2183 2183
2184static void __exit ns83820_exit(void) 2184static void __exit ns83820_exit(void)
diff --git a/drivers/net/pci-skeleton.c b/drivers/net/pci-skeleton.c
index e0e293964042..e6347620529e 100644
--- a/drivers/net/pci-skeleton.c
+++ b/drivers/net/pci-skeleton.c
@@ -1963,7 +1963,7 @@ static int __init netdrv_init_module (void)
1963#ifdef MODULE 1963#ifdef MODULE
1964 printk(version); 1964 printk(version);
1965#endif 1965#endif
1966 return pci_module_init (&netdrv_pci_driver); 1966 return pci_register_driver(&netdrv_pci_driver);
1967} 1967}
1968 1968
1969 1969
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c
index 297e9f805366..c54f6a7ebf31 100644
--- a/drivers/net/pcmcia/axnet_cs.c
+++ b/drivers/net/pcmcia/axnet_cs.c
@@ -771,6 +771,7 @@ static struct pcmcia_device_id axnet_ids[] = {
771 PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0309), 771 PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0309),
772 PCMCIA_DEVICE_MANF_CARD(0x0274, 0x1106), 772 PCMCIA_DEVICE_MANF_CARD(0x0274, 0x1106),
773 PCMCIA_DEVICE_MANF_CARD(0x8a01, 0xc1ab), 773 PCMCIA_DEVICE_MANF_CARD(0x8a01, 0xc1ab),
774 PCMCIA_DEVICE_MANF_CARD(0x021b, 0x0202),
774 PCMCIA_DEVICE_PROD_ID12("AmbiCom,Inc.", "Fast Ethernet PC Card(AMB8110)", 0x49b020a7, 0x119cc9fc), 775 PCMCIA_DEVICE_PROD_ID12("AmbiCom,Inc.", "Fast Ethernet PC Card(AMB8110)", 0x49b020a7, 0x119cc9fc),
775 PCMCIA_DEVICE_PROD_ID124("Fast Ethernet", "16-bit PC Card", "AX88190", 0xb4be14e3, 0x9a12eb6a, 0xab9be5ef), 776 PCMCIA_DEVICE_PROD_ID124("Fast Ethernet", "16-bit PC Card", "AX88190", 0xb4be14e3, 0x9a12eb6a, 0xab9be5ef),
776 PCMCIA_DEVICE_PROD_ID12("ASIX", "AX88190", 0x0959823b, 0xab9be5ef), 777 PCMCIA_DEVICE_PROD_ID12("ASIX", "AX88190", 0x0959823b, 0xab9be5ef),
@@ -786,8 +787,6 @@ static struct pcmcia_device_id axnet_ids[] = {
786 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "FastEtherCard", 0x281f1c5d, 0x7ef26116), 787 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "FastEtherCard", 0x281f1c5d, 0x7ef26116),
787 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "FEP501", 0x281f1c5d, 0x2e272058), 788 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "FEP501", 0x281f1c5d, 0x2e272058),
788 PCMCIA_DEVICE_PROD_ID14("Network Everywhere", "AX88190", 0x820a67b6, 0xab9be5ef), 789 PCMCIA_DEVICE_PROD_ID14("Network Everywhere", "AX88190", 0x820a67b6, 0xab9be5ef),
789 /* this is not specific enough */
790 /* PCMCIA_DEVICE_MANF_CARD(0x021b, 0x0202), */
791 PCMCIA_DEVICE_NULL, 790 PCMCIA_DEVICE_NULL,
792}; 791};
793MODULE_DEVICE_TABLE(pcmcia, axnet_ids); 792MODULE_DEVICE_TABLE(pcmcia, axnet_ids);
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index 0ecebfc31f07..cc0dcc9bf636 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -654,11 +654,8 @@ static int pcnet_config(struct pcmcia_device *link)
654 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); 654 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
655 655
656 if (info->flags & (IS_DL10019|IS_DL10022)) { 656 if (info->flags & (IS_DL10019|IS_DL10022)) {
657 u_char id = inb(dev->base_addr + 0x1a);
658 dev->do_ioctl = &ei_ioctl; 657 dev->do_ioctl = &ei_ioctl;
659 mii_phy_probe(dev); 658 mii_phy_probe(dev);
660 if ((id == 0x30) && !info->pna_phy && (info->eth_phy == 4))
661 info->eth_phy = 0;
662 } 659 }
663 660
664 link->dev_node = &info->node; 661 link->dev_node = &info->node;
@@ -821,15 +818,6 @@ static void mdio_write(kio_addr_t addr, int phy_id, int loc, int value)
821 } 818 }
822} 819}
823 820
824static void mdio_reset(kio_addr_t addr, int phy_id)
825{
826 outb_p(0x08, addr);
827 outb_p(0x0c, addr);
828 outb_p(0x08, addr);
829 outb_p(0x0c, addr);
830 outb_p(0x00, addr);
831}
832
833/*====================================================================== 821/*======================================================================
834 822
835 EEPROM access routines for DL10019 and DL10022 based cards 823 EEPROM access routines for DL10019 and DL10022 based cards
@@ -942,7 +930,8 @@ static void set_misc_reg(struct net_device *dev)
942 } 930 }
943 if (info->flags & IS_DL10022) { 931 if (info->flags & IS_DL10022) {
944 if (info->flags & HAS_MII) { 932 if (info->flags & HAS_MII) {
945 mdio_reset(nic_base + DLINK_GPIO, info->eth_phy); 933 /* Advertise 100F, 100H, 10F, 10H */
934 mdio_write(nic_base + DLINK_GPIO, info->eth_phy, 4, 0x01e1);
946 /* Restart MII autonegotiation */ 935 /* Restart MII autonegotiation */
947 mdio_write(nic_base + DLINK_GPIO, info->eth_phy, 0, 0x0000); 936 mdio_write(nic_base + DLINK_GPIO, info->eth_phy, 0, 0x0000);
948 mdio_write(nic_base + DLINK_GPIO, info->eth_phy, 0, 0x1200); 937 mdio_write(nic_base + DLINK_GPIO, info->eth_phy, 0, 0x1200);
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index d50bcb89dd28..5e26fe806e21 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -2978,7 +2978,7 @@ static int __init pcnet32_init_module(void)
2978 tx_start = tx_start_pt; 2978 tx_start = tx_start_pt;
2979 2979
2980 /* find the PCI devices */ 2980 /* find the PCI devices */
2981 if (!pci_module_init(&pcnet32_driver)) 2981 if (!pci_register_driver(&pcnet32_driver))
2982 pcnet32_have_pci = 1; 2982 pcnet32_have_pci = 1;
2983 2983
2984 /* should we find any remaining VLbus devices ? */ 2984 /* should we find any remaining VLbus devices ? */
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 25e31fb5cb31..b1d8ed40ad98 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -14,7 +14,6 @@
14 * 14 *
15 */ 15 */
16 16
17#include <linux/config.h>
18#include <linux/kernel.h> 17#include <linux/kernel.h>
19#include <linux/module.h> 18#include <linux/module.h>
20#include <linux/mii.h> 19#include <linux/mii.h>
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index ffd215d9a9be..792716beb052 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -12,7 +12,6 @@
12 * 12 *
13 */ 13 */
14 14
15#include <linux/config.h>
16#include <linux/kernel.h> 15#include <linux/kernel.h>
17#include <linux/module.h> 16#include <linux/module.h>
18#include <linux/mii.h> 17#include <linux/mii.h>
diff --git a/drivers/net/qla3xxx.c b/drivers/net/qla3xxx.c
new file mode 100644
index 000000000000..c729aeeb4696
--- /dev/null
+++ b/drivers/net/qla3xxx.c
@@ -0,0 +1,3537 @@
1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
25#include <linux/if_arp.h>
26#include <linux/if_ether.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/skbuff.h>
31#include <linux/rtnetlink.h>
32#include <linux/if_vlan.h>
33#include <linux/init.h>
34#include <linux/delay.h>
35#include <linux/mm.h>
36
37#include "qla3xxx.h"
38
39#define DRV_NAME "qla3xxx"
40#define DRV_STRING "QLogic ISP3XXX Network Driver"
41#define DRV_VERSION "v2.02.00-k36"
42#define PFX DRV_NAME " "
43
44static const char ql3xxx_driver_name[] = DRV_NAME;
45static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47MODULE_AUTHOR("QLogic Corporation");
48MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
49MODULE_LICENSE("GPL");
50MODULE_VERSION(DRV_VERSION);
51
52static const u32 default_msg
53 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
54 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
55
56static int debug = -1; /* defaults above */
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60static int msi;
61module_param(msi, int, 0);
62MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
63
64static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
65 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
66 /* required last entry */
67 {0,}
68};
69
70MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
71
72/*
73 * Caller must take hw_lock.
74 */
75static int ql_sem_spinlock(struct ql3_adapter *qdev,
76 u32 sem_mask, u32 sem_bits)
77{
78 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
79 u32 value;
80 unsigned int seconds = 3;
81
82 do {
83 writel((sem_mask | sem_bits),
84 &port_regs->CommonRegs.semaphoreReg);
85 value = readl(&port_regs->CommonRegs.semaphoreReg);
86 if ((value & (sem_mask >> 16)) == sem_bits)
87 return 0;
88 ssleep(1);
89 } while(--seconds);
90 return -1;
91}
92
93static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
94{
95 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
96 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
97 readl(&port_regs->CommonRegs.semaphoreReg);
98}
99
100static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
101{
102 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
103 u32 value;
104
105 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
106 value = readl(&port_regs->CommonRegs.semaphoreReg);
107 return ((value & (sem_mask >> 16)) == sem_bits);
108}
109
110/*
111 * Caller holds hw_lock.
112 */
113static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
114{
115 int i = 0;
116
117 while (1) {
118 if (!ql_sem_lock(qdev,
119 QL_DRVR_SEM_MASK,
120 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
121 * 2) << 1)) {
122 if (i < 10) {
123 ssleep(1);
124 i++;
125 } else {
126 printk(KERN_ERR PFX "%s: Timed out waiting for "
127 "driver lock...\n",
128 qdev->ndev->name);
129 return 0;
130 }
131 } else {
132 printk(KERN_DEBUG PFX
133 "%s: driver lock acquired.\n",
134 qdev->ndev->name);
135 return 1;
136 }
137 }
138}
139
140static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
141{
142 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
143
144 writel(((ISP_CONTROL_NP_MASK << 16) | page),
145 &port_regs->CommonRegs.ispControlStatus);
146 readl(&port_regs->CommonRegs.ispControlStatus);
147 qdev->current_page = page;
148}
149
150static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
151 u32 __iomem * reg)
152{
153 u32 value;
154 unsigned long hw_flags;
155
156 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
157 value = readl(reg);
158 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
159
160 return value;
161}
162
163static u32 ql_read_common_reg(struct ql3_adapter *qdev,
164 u32 __iomem * reg)
165{
166 return readl(reg);
167}
168
169static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
170{
171 u32 value;
172 unsigned long hw_flags;
173
174 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
175
176 if (qdev->current_page != 0)
177 ql_set_register_page(qdev,0);
178 value = readl(reg);
179
180 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
181 return value;
182}
183
184static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
185{
186 if (qdev->current_page != 0)
187 ql_set_register_page(qdev,0);
188 return readl(reg);
189}
190
191static void ql_write_common_reg_l(struct ql3_adapter *qdev,
192 u32 * reg, u32 value)
193{
194 unsigned long hw_flags;
195
196 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
197 writel(value, (u32 *) reg);
198 readl(reg);
199 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
200 return;
201}
202
203static void ql_write_common_reg(struct ql3_adapter *qdev,
204 u32 * reg, u32 value)
205{
206 writel(value, (u32 *) reg);
207 readl(reg);
208 return;
209}
210
211static void ql_write_page0_reg(struct ql3_adapter *qdev,
212 u32 * reg, u32 value)
213{
214 if (qdev->current_page != 0)
215 ql_set_register_page(qdev,0);
216 writel(value, (u32 *) reg);
217 readl(reg);
218 return;
219}
220
221/*
222 * Caller holds hw_lock. Only called during init.
223 */
224static void ql_write_page1_reg(struct ql3_adapter *qdev,
225 u32 * reg, u32 value)
226{
227 if (qdev->current_page != 1)
228 ql_set_register_page(qdev,1);
229 writel(value, (u32 *) reg);
230 readl(reg);
231 return;
232}
233
234/*
235 * Caller holds hw_lock. Only called during init.
236 */
237static void ql_write_page2_reg(struct ql3_adapter *qdev,
238 u32 * reg, u32 value)
239{
240 if (qdev->current_page != 2)
241 ql_set_register_page(qdev,2);
242 writel(value, (u32 *) reg);
243 readl(reg);
244 return;
245}
246
247static void ql_disable_interrupts(struct ql3_adapter *qdev)
248{
249 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
250
251 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
252 (ISP_IMR_ENABLE_INT << 16));
253
254}
255
256static void ql_enable_interrupts(struct ql3_adapter *qdev)
257{
258 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
259
260 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
261 ((0xff << 16) | ISP_IMR_ENABLE_INT));
262
263}
264
265static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
266 struct ql_rcv_buf_cb *lrg_buf_cb)
267{
268 u64 map;
269 lrg_buf_cb->next = NULL;
270
271 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
272 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
273 } else {
274 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
275 qdev->lrg_buf_free_tail = lrg_buf_cb;
276 }
277
278 if (!lrg_buf_cb->skb) {
279 lrg_buf_cb->skb = dev_alloc_skb(qdev->lrg_buffer_len);
280 if (unlikely(!lrg_buf_cb->skb)) {
281 printk(KERN_ERR PFX "%s: failed dev_alloc_skb().\n",
282 qdev->ndev->name);
283 qdev->lrg_buf_skb_check++;
284 } else {
285 /*
286 * We save some space to copy the ethhdr from first
287 * buffer
288 */
289 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
290 map = pci_map_single(qdev->pdev,
291 lrg_buf_cb->skb->data,
292 qdev->lrg_buffer_len -
293 QL_HEADER_SPACE,
294 PCI_DMA_FROMDEVICE);
295 lrg_buf_cb->buf_phy_addr_low =
296 cpu_to_le32(LS_64BITS(map));
297 lrg_buf_cb->buf_phy_addr_high =
298 cpu_to_le32(MS_64BITS(map));
299 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
300 pci_unmap_len_set(lrg_buf_cb, maplen,
301 qdev->lrg_buffer_len -
302 QL_HEADER_SPACE);
303 }
304 }
305
306 qdev->lrg_buf_free_count++;
307}
308
309static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
310 *qdev)
311{
312 struct ql_rcv_buf_cb *lrg_buf_cb;
313
314 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
315 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
316 qdev->lrg_buf_free_tail = NULL;
317 qdev->lrg_buf_free_count--;
318 }
319
320 return lrg_buf_cb;
321}
322
323static u32 addrBits = EEPROM_NO_ADDR_BITS;
324static u32 dataBits = EEPROM_NO_DATA_BITS;
325
326static void fm93c56a_deselect(struct ql3_adapter *qdev);
327static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
328 unsigned short *value);
329
330/*
331 * Caller holds hw_lock.
332 */
333static void fm93c56a_select(struct ql3_adapter *qdev)
334{
335 struct ql3xxx_port_registers __iomem *port_regs =
336 qdev->mem_map_registers;
337
338 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
339 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
340 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
341 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
342 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
343}
344
345/*
346 * Caller holds hw_lock.
347 */
348static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
349{
350 int i;
351 u32 mask;
352 u32 dataBit;
353 u32 previousBit;
354 struct ql3xxx_port_registers __iomem *port_regs =
355 qdev->mem_map_registers;
356
357 /* Clock in a zero, then do the start bit */
358 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
359 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
360 AUBURN_EEPROM_DO_1);
361 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
362 ISP_NVRAM_MASK | qdev->
363 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
364 AUBURN_EEPROM_CLK_RISE);
365 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
366 ISP_NVRAM_MASK | qdev->
367 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
368 AUBURN_EEPROM_CLK_FALL);
369
370 mask = 1 << (FM93C56A_CMD_BITS - 1);
371 /* Force the previous data bit to be different */
372 previousBit = 0xffff;
373 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
374 dataBit =
375 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
376 if (previousBit != dataBit) {
377 /*
378 * If the bit changed, then change the DO state to
379 * match
380 */
381 ql_write_common_reg(qdev,
382 &port_regs->CommonRegs.
383 serialPortInterfaceReg,
384 ISP_NVRAM_MASK | qdev->
385 eeprom_cmd_data | dataBit);
386 previousBit = dataBit;
387 }
388 ql_write_common_reg(qdev,
389 &port_regs->CommonRegs.
390 serialPortInterfaceReg,
391 ISP_NVRAM_MASK | qdev->
392 eeprom_cmd_data | dataBit |
393 AUBURN_EEPROM_CLK_RISE);
394 ql_write_common_reg(qdev,
395 &port_regs->CommonRegs.
396 serialPortInterfaceReg,
397 ISP_NVRAM_MASK | qdev->
398 eeprom_cmd_data | dataBit |
399 AUBURN_EEPROM_CLK_FALL);
400 cmd = cmd << 1;
401 }
402
403 mask = 1 << (addrBits - 1);
404 /* Force the previous data bit to be different */
405 previousBit = 0xffff;
406 for (i = 0; i < addrBits; i++) {
407 dataBit =
408 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
409 AUBURN_EEPROM_DO_0;
410 if (previousBit != dataBit) {
411 /*
412 * If the bit changed, then change the DO state to
413 * match
414 */
415 ql_write_common_reg(qdev,
416 &port_regs->CommonRegs.
417 serialPortInterfaceReg,
418 ISP_NVRAM_MASK | qdev->
419 eeprom_cmd_data | dataBit);
420 previousBit = dataBit;
421 }
422 ql_write_common_reg(qdev,
423 &port_regs->CommonRegs.
424 serialPortInterfaceReg,
425 ISP_NVRAM_MASK | qdev->
426 eeprom_cmd_data | dataBit |
427 AUBURN_EEPROM_CLK_RISE);
428 ql_write_common_reg(qdev,
429 &port_regs->CommonRegs.
430 serialPortInterfaceReg,
431 ISP_NVRAM_MASK | qdev->
432 eeprom_cmd_data | dataBit |
433 AUBURN_EEPROM_CLK_FALL);
434 eepromAddr = eepromAddr << 1;
435 }
436}
437
438/*
439 * Caller holds hw_lock.
440 */
441static void fm93c56a_deselect(struct ql3_adapter *qdev)
442{
443 struct ql3xxx_port_registers __iomem *port_regs =
444 qdev->mem_map_registers;
445 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
446 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
447 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
448}
449
450/*
451 * Caller holds hw_lock.
452 */
453static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
454{
455 int i;
456 u32 data = 0;
457 u32 dataBit;
458 struct ql3xxx_port_registers __iomem *port_regs =
459 qdev->mem_map_registers;
460
461 /* Read the data bits */
462 /* The first bit is a dummy. Clock right over it. */
463 for (i = 0; i < dataBits; i++) {
464 ql_write_common_reg(qdev,
465 &port_regs->CommonRegs.
466 serialPortInterfaceReg,
467 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
468 AUBURN_EEPROM_CLK_RISE);
469 ql_write_common_reg(qdev,
470 &port_regs->CommonRegs.
471 serialPortInterfaceReg,
472 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
473 AUBURN_EEPROM_CLK_FALL);
474 dataBit =
475 (ql_read_common_reg
476 (qdev,
477 &port_regs->CommonRegs.
478 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
479 data = (data << 1) | dataBit;
480 }
481 *value = (u16) data;
482}
483
484/*
485 * Caller holds hw_lock.
486 */
487static void eeprom_readword(struct ql3_adapter *qdev,
488 u32 eepromAddr, unsigned short *value)
489{
490 fm93c56a_select(qdev);
491 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
492 fm93c56a_datain(qdev, value);
493 fm93c56a_deselect(qdev);
494}
495
496static void ql_swap_mac_addr(u8 * macAddress)
497{
498#ifdef __BIG_ENDIAN
499 u8 temp;
500 temp = macAddress[0];
501 macAddress[0] = macAddress[1];
502 macAddress[1] = temp;
503 temp = macAddress[2];
504 macAddress[2] = macAddress[3];
505 macAddress[3] = temp;
506 temp = macAddress[4];
507 macAddress[4] = macAddress[5];
508 macAddress[5] = temp;
509#endif
510}
511
512static int ql_get_nvram_params(struct ql3_adapter *qdev)
513{
514 u16 *pEEPROMData;
515 u16 checksum = 0;
516 u32 index;
517 unsigned long hw_flags;
518
519 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
520
521 pEEPROMData = (u16 *) & qdev->nvram_data;
522 qdev->eeprom_cmd_data = 0;
523 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
524 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
525 2) << 10)) {
526 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
527 __func__);
528 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
529 return -1;
530 }
531
532 for (index = 0; index < EEPROM_SIZE; index++) {
533 eeprom_readword(qdev, index, pEEPROMData);
534 checksum += *pEEPROMData;
535 pEEPROMData++;
536 }
537 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
538
539 if (checksum != 0) {
540 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
541 qdev->ndev->name, checksum);
542 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
543 return -1;
544 }
545
546 /*
547 * We have a problem with endianness for the MAC addresses
548 * and the two 8-bit values version, and numPorts. We
549 * have to swap them on big endian systems.
550 */
551 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
552 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
553 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
554 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
555 pEEPROMData = (u16 *) & qdev->nvram_data.version;
556 *pEEPROMData = le16_to_cpu(*pEEPROMData);
557
558 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
559 return checksum;
560}
561
562static const u32 PHYAddr[2] = {
563 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
564};
565
566static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
567{
568 struct ql3xxx_port_registers __iomem *port_regs =
569 qdev->mem_map_registers;
570 u32 temp;
571 int count = 1000;
572
573 while (count) {
574 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
575 if (!(temp & MAC_MII_STATUS_BSY))
576 return 0;
577 udelay(10);
578 count--;
579 }
580 return -1;
581}
582
583static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
584{
585 struct ql3xxx_port_registers __iomem *port_regs =
586 qdev->mem_map_registers;
587 u32 scanControl;
588
589 if (qdev->numPorts > 1) {
590 /* Auto scan will cycle through multiple ports */
591 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
592 } else {
593 scanControl = MAC_MII_CONTROL_SC;
594 }
595
596 /*
597 * Scan register 1 of PHY/PETBI,
598 * Set up to scan both devices
599 * The autoscan starts from the first register, completes
600 * the last one before rolling over to the first
601 */
602 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
603 PHYAddr[0] | MII_SCAN_REGISTER);
604
605 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
606 (scanControl) |
607 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
608}
609
610static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
611{
612 u8 ret;
613 struct ql3xxx_port_registers __iomem *port_regs =
614 qdev->mem_map_registers;
615
616 /* See if scan mode is enabled before we turn it off */
617 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
618 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
619 /* Scan is enabled */
620 ret = 1;
621 } else {
622 /* Scan is disabled */
623 ret = 0;
624 }
625
626 /*
627 * When disabling scan mode you must first change the MII register
628 * address
629 */
630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
631 PHYAddr[0] | MII_SCAN_REGISTER);
632
633 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
634 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
635 MAC_MII_CONTROL_RC) << 16));
636
637 return ret;
638}
639
640static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
641 u16 regAddr, u16 value, u32 mac_index)
642{
643 struct ql3xxx_port_registers __iomem *port_regs =
644 qdev->mem_map_registers;
645 u8 scanWasEnabled;
646
647 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
648
649 if (ql_wait_for_mii_ready(qdev)) {
650 if (netif_msg_link(qdev))
651 printk(KERN_WARNING PFX
652 "%s Timed out waiting for management port to "
653 "get free before issuing command.\n",
654 qdev->ndev->name);
655 return -1;
656 }
657
658 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
659 PHYAddr[mac_index] | regAddr);
660
661 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
662
663 /* Wait for write to complete 9/10/04 SJP */
664 if (ql_wait_for_mii_ready(qdev)) {
665 if (netif_msg_link(qdev))
666 printk(KERN_WARNING PFX
667 "%s: Timed out waiting for management port to"
668 "get free before issuing command.\n",
669 qdev->ndev->name);
670 return -1;
671 }
672
673 if (scanWasEnabled)
674 ql_mii_enable_scan_mode(qdev);
675
676 return 0;
677}
678
679static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
680 u16 * value, u32 mac_index)
681{
682 struct ql3xxx_port_registers __iomem *port_regs =
683 qdev->mem_map_registers;
684 u8 scanWasEnabled;
685 u32 temp;
686
687 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
688
689 if (ql_wait_for_mii_ready(qdev)) {
690 if (netif_msg_link(qdev))
691 printk(KERN_WARNING PFX
692 "%s: Timed out waiting for management port to "
693 "get free before issuing command.\n",
694 qdev->ndev->name);
695 return -1;
696 }
697
698 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
699 PHYAddr[mac_index] | regAddr);
700
701 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
702 (MAC_MII_CONTROL_RC << 16));
703
704 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
705 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
706
707 /* Wait for the read to complete */
708 if (ql_wait_for_mii_ready(qdev)) {
709 if (netif_msg_link(qdev))
710 printk(KERN_WARNING PFX
711 "%s: Timed out waiting for management port to "
712 "get free after issuing command.\n",
713 qdev->ndev->name);
714 return -1;
715 }
716
717 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
718 *value = (u16) temp;
719
720 if (scanWasEnabled)
721 ql_mii_enable_scan_mode(qdev);
722
723 return 0;
724}
725
726static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
727{
728 struct ql3xxx_port_registers __iomem *port_regs =
729 qdev->mem_map_registers;
730
731 ql_mii_disable_scan_mode(qdev);
732
733 if (ql_wait_for_mii_ready(qdev)) {
734 if (netif_msg_link(qdev))
735 printk(KERN_WARNING PFX
736 "%s: Timed out waiting for management port to "
737 "get free before issuing command.\n",
738 qdev->ndev->name);
739 return -1;
740 }
741
742 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
743 qdev->PHYAddr | regAddr);
744
745 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
746
747 /* Wait for write to complete. */
748 if (ql_wait_for_mii_ready(qdev)) {
749 if (netif_msg_link(qdev))
750 printk(KERN_WARNING PFX
751 "%s: Timed out waiting for management port to "
752 "get free before issuing command.\n",
753 qdev->ndev->name);
754 return -1;
755 }
756
757 ql_mii_enable_scan_mode(qdev);
758
759 return 0;
760}
761
762static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
763{
764 u32 temp;
765 struct ql3xxx_port_registers __iomem *port_regs =
766 qdev->mem_map_registers;
767
768 ql_mii_disable_scan_mode(qdev);
769
770 if (ql_wait_for_mii_ready(qdev)) {
771 if (netif_msg_link(qdev))
772 printk(KERN_WARNING PFX
773 "%s: Timed out waiting for management port to "
774 "get free before issuing command.\n",
775 qdev->ndev->name);
776 return -1;
777 }
778
779 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
780 qdev->PHYAddr | regAddr);
781
782 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
783 (MAC_MII_CONTROL_RC << 16));
784
785 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
786 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
787
788 /* Wait for the read to complete */
789 if (ql_wait_for_mii_ready(qdev)) {
790 if (netif_msg_link(qdev))
791 printk(KERN_WARNING PFX
792 "%s: Timed out waiting for management port to "
793 "get free before issuing command.\n",
794 qdev->ndev->name);
795 return -1;
796 }
797
798 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
799 *value = (u16) temp;
800
801 ql_mii_enable_scan_mode(qdev);
802
803 return 0;
804}
805
806static void ql_petbi_reset(struct ql3_adapter *qdev)
807{
808 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
809}
810
811static void ql_petbi_start_neg(struct ql3_adapter *qdev)
812{
813 u16 reg;
814
815 /* Enable Auto-negotiation sense */
816 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
817 reg |= PETBI_TBI_AUTO_SENSE;
818 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
819
820 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
821 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
822
823 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
824 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
825 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
826
827}
828
829static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
830{
831 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
832 mac_index);
833}
834
835static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
836{
837 u16 reg;
838
839 /* Enable Auto-negotiation sense */
840 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
841 reg |= PETBI_TBI_AUTO_SENSE;
842 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
843
844 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
845 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
846
847 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
848 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
849 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
850 mac_index);
851}
852
853static void ql_petbi_init(struct ql3_adapter *qdev)
854{
855 ql_petbi_reset(qdev);
856 ql_petbi_start_neg(qdev);
857}
858
859static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
860{
861 ql_petbi_reset_ex(qdev, mac_index);
862 ql_petbi_start_neg_ex(qdev, mac_index);
863}
864
865static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
866{
867 u16 reg;
868
869 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
870 return 0;
871
872 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
873}
874
875static int ql_phy_get_speed(struct ql3_adapter *qdev)
876{
877 u16 reg;
878
879 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
880 return 0;
881
882 reg = (((reg & 0x18) >> 3) & 3);
883
884 if (reg == 2)
885 return SPEED_1000;
886 else if (reg == 1)
887 return SPEED_100;
888 else if (reg == 0)
889 return SPEED_10;
890 else
891 return -1;
892}
893
894static int ql_is_full_dup(struct ql3_adapter *qdev)
895{
896 u16 reg;
897
898 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
899 return 0;
900
901 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
902}
903
904static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
905{
906 u16 reg;
907
908 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
909 return 0;
910
911 return (reg & PHY_NEG_PAUSE) != 0;
912}
913
914/*
915 * Caller holds hw_lock.
916 */
917static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
918{
919 struct ql3xxx_port_registers __iomem *port_regs =
920 qdev->mem_map_registers;
921 u32 value;
922
923 if (enable)
924 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
925 else
926 value = (MAC_CONFIG_REG_PE << 16);
927
928 if (qdev->mac_index)
929 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
930 else
931 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
932}
933
934/*
935 * Caller holds hw_lock.
936 */
937static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
938{
939 struct ql3xxx_port_registers __iomem *port_regs =
940 qdev->mem_map_registers;
941 u32 value;
942
943 if (enable)
944 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
945 else
946 value = (MAC_CONFIG_REG_SR << 16);
947
948 if (qdev->mac_index)
949 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
950 else
951 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
952}
953
954/*
955 * Caller holds hw_lock.
956 */
957static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
958{
959 struct ql3xxx_port_registers __iomem *port_regs =
960 qdev->mem_map_registers;
961 u32 value;
962
963 if (enable)
964 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
965 else
966 value = (MAC_CONFIG_REG_GM << 16);
967
968 if (qdev->mac_index)
969 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
970 else
971 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
972}
973
974/*
975 * Caller holds hw_lock.
976 */
977static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
978{
979 struct ql3xxx_port_registers __iomem *port_regs =
980 qdev->mem_map_registers;
981 u32 value;
982
983 if (enable)
984 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
985 else
986 value = (MAC_CONFIG_REG_FD << 16);
987
988 if (qdev->mac_index)
989 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
990 else
991 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
992}
993
994/*
995 * Caller holds hw_lock.
996 */
997static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
998{
999 struct ql3xxx_port_registers __iomem *port_regs =
1000 qdev->mem_map_registers;
1001 u32 value;
1002
1003 if (enable)
1004 value =
1005 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1006 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1007 else
1008 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1009
1010 if (qdev->mac_index)
1011 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1012 else
1013 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1014}
1015
1016/*
1017 * Caller holds hw_lock.
1018 */
1019static int ql_is_fiber(struct ql3_adapter *qdev)
1020{
1021 struct ql3xxx_port_registers __iomem *port_regs =
1022 qdev->mem_map_registers;
1023 u32 bitToCheck = 0;
1024 u32 temp;
1025
1026 switch (qdev->mac_index) {
1027 case 0:
1028 bitToCheck = PORT_STATUS_SM0;
1029 break;
1030 case 1:
1031 bitToCheck = PORT_STATUS_SM1;
1032 break;
1033 }
1034
1035 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1036 return (temp & bitToCheck) != 0;
1037}
1038
1039static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1040{
1041 u16 reg;
1042 ql_mii_read_reg(qdev, 0x00, &reg);
1043 return (reg & 0x1000) != 0;
1044}
1045
1046/*
1047 * Caller holds hw_lock.
1048 */
1049static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1050{
1051 struct ql3xxx_port_registers __iomem *port_regs =
1052 qdev->mem_map_registers;
1053 u32 bitToCheck = 0;
1054 u32 temp;
1055
1056 switch (qdev->mac_index) {
1057 case 0:
1058 bitToCheck = PORT_STATUS_AC0;
1059 break;
1060 case 1:
1061 bitToCheck = PORT_STATUS_AC1;
1062 break;
1063 }
1064
1065 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1066 if (temp & bitToCheck) {
1067 if (netif_msg_link(qdev))
1068 printk(KERN_INFO PFX
1069 "%s: Auto-Negotiate complete.\n",
1070 qdev->ndev->name);
1071 return 1;
1072 } else {
1073 if (netif_msg_link(qdev))
1074 printk(KERN_WARNING PFX
1075 "%s: Auto-Negotiate incomplete.\n",
1076 qdev->ndev->name);
1077 return 0;
1078 }
1079}
1080
1081/*
1082 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1083 */
1084static int ql_is_neg_pause(struct ql3_adapter *qdev)
1085{
1086 if (ql_is_fiber(qdev))
1087 return ql_is_petbi_neg_pause(qdev);
1088 else
1089 return ql_is_phy_neg_pause(qdev);
1090}
1091
1092static int ql_auto_neg_error(struct ql3_adapter *qdev)
1093{
1094 struct ql3xxx_port_registers __iomem *port_regs =
1095 qdev->mem_map_registers;
1096 u32 bitToCheck = 0;
1097 u32 temp;
1098
1099 switch (qdev->mac_index) {
1100 case 0:
1101 bitToCheck = PORT_STATUS_AE0;
1102 break;
1103 case 1:
1104 bitToCheck = PORT_STATUS_AE1;
1105 break;
1106 }
1107 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1108 return (temp & bitToCheck) != 0;
1109}
1110
1111static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1112{
1113 if (ql_is_fiber(qdev))
1114 return SPEED_1000;
1115 else
1116 return ql_phy_get_speed(qdev);
1117}
1118
1119static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1120{
1121 if (ql_is_fiber(qdev))
1122 return 1;
1123 else
1124 return ql_is_full_dup(qdev);
1125}
1126
1127/*
1128 * Caller holds hw_lock.
1129 */
1130static int ql_link_down_detect(struct ql3_adapter *qdev)
1131{
1132 struct ql3xxx_port_registers __iomem *port_regs =
1133 qdev->mem_map_registers;
1134 u32 bitToCheck = 0;
1135 u32 temp;
1136
1137 switch (qdev->mac_index) {
1138 case 0:
1139 bitToCheck = ISP_CONTROL_LINK_DN_0;
1140 break;
1141 case 1:
1142 bitToCheck = ISP_CONTROL_LINK_DN_1;
1143 break;
1144 }
1145
1146 temp =
1147 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1148 return (temp & bitToCheck) != 0;
1149}
1150
1151/*
1152 * Caller holds hw_lock.
1153 */
1154static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1155{
1156 struct ql3xxx_port_registers __iomem *port_regs =
1157 qdev->mem_map_registers;
1158
1159 switch (qdev->mac_index) {
1160 case 0:
1161 ql_write_common_reg(qdev,
1162 &port_regs->CommonRegs.ispControlStatus,
1163 (ISP_CONTROL_LINK_DN_0) |
1164 (ISP_CONTROL_LINK_DN_0 << 16));
1165 break;
1166
1167 case 1:
1168 ql_write_common_reg(qdev,
1169 &port_regs->CommonRegs.ispControlStatus,
1170 (ISP_CONTROL_LINK_DN_1) |
1171 (ISP_CONTROL_LINK_DN_1 << 16));
1172 break;
1173
1174 default:
1175 return 1;
1176 }
1177
1178 return 0;
1179}
1180
1181/*
1182 * Caller holds hw_lock.
1183 */
1184static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1185 u32 mac_index)
1186{
1187 struct ql3xxx_port_registers __iomem *port_regs =
1188 qdev->mem_map_registers;
1189 u32 bitToCheck = 0;
1190 u32 temp;
1191
1192 switch (mac_index) {
1193 case 0:
1194 bitToCheck = PORT_STATUS_F1_ENABLED;
1195 break;
1196 case 1:
1197 bitToCheck = PORT_STATUS_F3_ENABLED;
1198 break;
1199 default:
1200 break;
1201 }
1202
1203 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1204 if (temp & bitToCheck) {
1205 if (netif_msg_link(qdev))
1206 printk(KERN_DEBUG PFX
1207 "%s: is not link master.\n", qdev->ndev->name);
1208 return 0;
1209 } else {
1210 if (netif_msg_link(qdev))
1211 printk(KERN_DEBUG PFX
1212 "%s: is link master.\n", qdev->ndev->name);
1213 return 1;
1214 }
1215}
1216
1217static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1218{
1219 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1220}
1221
1222static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1223{
1224 u16 reg;
1225
1226 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1227 PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1228
1229 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1230 ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1231 mac_index);
1232}
1233
1234static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1235{
1236 ql_phy_reset_ex(qdev, mac_index);
1237 ql_phy_start_neg_ex(qdev, mac_index);
1238}
1239
1240/*
1241 * Caller holds hw_lock.
1242 */
1243static u32 ql_get_link_state(struct ql3_adapter *qdev)
1244{
1245 struct ql3xxx_port_registers __iomem *port_regs =
1246 qdev->mem_map_registers;
1247 u32 bitToCheck = 0;
1248 u32 temp, linkState;
1249
1250 switch (qdev->mac_index) {
1251 case 0:
1252 bitToCheck = PORT_STATUS_UP0;
1253 break;
1254 case 1:
1255 bitToCheck = PORT_STATUS_UP1;
1256 break;
1257 }
1258 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1259 if (temp & bitToCheck) {
1260 linkState = LS_UP;
1261 } else {
1262 linkState = LS_DOWN;
1263 if (netif_msg_link(qdev))
1264 printk(KERN_WARNING PFX
1265 "%s: Link is down.\n", qdev->ndev->name);
1266 }
1267 return linkState;
1268}
1269
1270static int ql_port_start(struct ql3_adapter *qdev)
1271{
1272 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1273 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1274 2) << 7))
1275 return -1;
1276
1277 if (ql_is_fiber(qdev)) {
1278 ql_petbi_init(qdev);
1279 } else {
1280 /* Copper port */
1281 ql_phy_init_ex(qdev, qdev->mac_index);
1282 }
1283
1284 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1285 return 0;
1286}
1287
1288static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1289{
1290
1291 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1292 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1293 2) << 7))
1294 return -1;
1295
1296 if (!ql_auto_neg_error(qdev)) {
1297 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1298 /* configure the MAC */
1299 if (netif_msg_link(qdev))
1300 printk(KERN_DEBUG PFX
1301 "%s: Configuring link.\n",
1302 qdev->ndev->
1303 name);
1304 ql_mac_cfg_soft_reset(qdev, 1);
1305 ql_mac_cfg_gig(qdev,
1306 (ql_get_link_speed
1307 (qdev) ==
1308 SPEED_1000));
1309 ql_mac_cfg_full_dup(qdev,
1310 ql_is_link_full_dup
1311 (qdev));
1312 ql_mac_cfg_pause(qdev,
1313 ql_is_neg_pause
1314 (qdev));
1315 ql_mac_cfg_soft_reset(qdev, 0);
1316
1317 /* enable the MAC */
1318 if (netif_msg_link(qdev))
1319 printk(KERN_DEBUG PFX
1320 "%s: Enabling mac.\n",
1321 qdev->ndev->
1322 name);
1323 ql_mac_enable(qdev, 1);
1324 }
1325
1326 if (netif_msg_link(qdev))
1327 printk(KERN_DEBUG PFX
1328 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1329 qdev->ndev->name);
1330 qdev->port_link_state = LS_UP;
1331 netif_start_queue(qdev->ndev);
1332 netif_carrier_on(qdev->ndev);
1333 if (netif_msg_link(qdev))
1334 printk(KERN_INFO PFX
1335 "%s: Link is up at %d Mbps, %s duplex.\n",
1336 qdev->ndev->name,
1337 ql_get_link_speed(qdev),
1338 ql_is_link_full_dup(qdev)
1339 ? "full" : "half");
1340
1341 } else { /* Remote error detected */
1342
1343 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1344 if (netif_msg_link(qdev))
1345 printk(KERN_DEBUG PFX
1346 "%s: Remote error detected. "
1347 "Calling ql_port_start().\n",
1348 qdev->ndev->
1349 name);
1350 /*
1351 * ql_port_start() is shared code and needs
1352 * to lock the PHY on it's own.
1353 */
1354 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1355 if(ql_port_start(qdev)) {/* Restart port */
1356 return -1;
1357 } else
1358 return 0;
1359 }
1360 }
1361 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1362 return 0;
1363}
1364
1365static void ql_link_state_machine(struct ql3_adapter *qdev)
1366{
1367 u32 curr_link_state;
1368 unsigned long hw_flags;
1369
1370 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1371
1372 curr_link_state = ql_get_link_state(qdev);
1373
1374 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1375 if (netif_msg_link(qdev))
1376 printk(KERN_INFO PFX
1377 "%s: Reset in progress, skip processing link "
1378 "state.\n", qdev->ndev->name);
1379 return;
1380 }
1381
1382 switch (qdev->port_link_state) {
1383 default:
1384 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1385 ql_port_start(qdev);
1386 }
1387 qdev->port_link_state = LS_DOWN;
1388 /* Fall Through */
1389
1390 case LS_DOWN:
1391 if (netif_msg_link(qdev))
1392 printk(KERN_DEBUG PFX
1393 "%s: port_link_state = LS_DOWN.\n",
1394 qdev->ndev->name);
1395 if (curr_link_state == LS_UP) {
1396 if (netif_msg_link(qdev))
1397 printk(KERN_DEBUG PFX
1398 "%s: curr_link_state = LS_UP.\n",
1399 qdev->ndev->name);
1400 if (ql_is_auto_neg_complete(qdev))
1401 ql_finish_auto_neg(qdev);
1402
1403 if (qdev->port_link_state == LS_UP)
1404 ql_link_down_detect_clear(qdev);
1405
1406 }
1407 break;
1408
1409 case LS_UP:
1410 /*
1411 * See if the link is currently down or went down and came
1412 * back up
1413 */
1414 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1415 if (netif_msg_link(qdev))
1416 printk(KERN_INFO PFX "%s: Link is down.\n",
1417 qdev->ndev->name);
1418 qdev->port_link_state = LS_DOWN;
1419 }
1420 break;
1421 }
1422 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1423}
1424
1425/*
1426 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1427 */
1428static void ql_get_phy_owner(struct ql3_adapter *qdev)
1429{
1430 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1431 set_bit(QL_LINK_MASTER,&qdev->flags);
1432 else
1433 clear_bit(QL_LINK_MASTER,&qdev->flags);
1434}
1435
1436/*
1437 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1438 */
1439static void ql_init_scan_mode(struct ql3_adapter *qdev)
1440{
1441 ql_mii_enable_scan_mode(qdev);
1442
1443 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1444 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1445 ql_petbi_init_ex(qdev, qdev->mac_index);
1446 } else {
1447 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1448 ql_phy_init_ex(qdev, qdev->mac_index);
1449 }
1450}
1451
1452/*
1453 * MII_Setup needs to be called before taking the PHY out of reset so that the
1454 * management interface clock speed can be set properly. It would be better if
1455 * we had a way to disable MDC until after the PHY is out of reset, but we
1456 * don't have that capability.
1457 */
1458static int ql_mii_setup(struct ql3_adapter *qdev)
1459{
1460 u32 reg;
1461 struct ql3xxx_port_registers __iomem *port_regs =
1462 qdev->mem_map_registers;
1463
1464 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1465 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1466 2) << 7))
1467 return -1;
1468
1469 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1470 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1471
1472 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1473 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1474
1475 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1476 return 0;
1477}
1478
1479static u32 ql_supported_modes(struct ql3_adapter *qdev)
1480{
1481 u32 supported;
1482
1483 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1484 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1485 | SUPPORTED_Autoneg;
1486 } else {
1487 supported = SUPPORTED_10baseT_Half
1488 | SUPPORTED_10baseT_Full
1489 | SUPPORTED_100baseT_Half
1490 | SUPPORTED_100baseT_Full
1491 | SUPPORTED_1000baseT_Half
1492 | SUPPORTED_1000baseT_Full
1493 | SUPPORTED_Autoneg | SUPPORTED_TP;
1494 }
1495
1496 return supported;
1497}
1498
1499static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1500{
1501 int status;
1502 unsigned long hw_flags;
1503 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1504 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1505 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1506 2) << 7))
1507 return 0;
1508 status = ql_is_auto_cfg(qdev);
1509 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1510 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1511 return status;
1512}
1513
1514static u32 ql_get_speed(struct ql3_adapter *qdev)
1515{
1516 u32 status;
1517 unsigned long hw_flags;
1518 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1519 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1520 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1521 2) << 7))
1522 return 0;
1523 status = ql_get_link_speed(qdev);
1524 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1525 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1526 return status;
1527}
1528
1529static int ql_get_full_dup(struct ql3_adapter *qdev)
1530{
1531 int status;
1532 unsigned long hw_flags;
1533 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1534 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1535 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1536 2) << 7))
1537 return 0;
1538 status = ql_is_link_full_dup(qdev);
1539 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1540 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1541 return status;
1542}
1543
1544
1545static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1546{
1547 struct ql3_adapter *qdev = netdev_priv(ndev);
1548
1549 ecmd->transceiver = XCVR_INTERNAL;
1550 ecmd->supported = ql_supported_modes(qdev);
1551
1552 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1553 ecmd->port = PORT_FIBRE;
1554 } else {
1555 ecmd->port = PORT_TP;
1556 ecmd->phy_address = qdev->PHYAddr;
1557 }
1558 ecmd->advertising = ql_supported_modes(qdev);
1559 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1560 ecmd->speed = ql_get_speed(qdev);
1561 ecmd->duplex = ql_get_full_dup(qdev);
1562 return 0;
1563}
1564
1565static void ql_get_drvinfo(struct net_device *ndev,
1566 struct ethtool_drvinfo *drvinfo)
1567{
1568 struct ql3_adapter *qdev = netdev_priv(ndev);
1569 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1570 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1571 strncpy(drvinfo->fw_version, "N/A", 32);
1572 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1573 drvinfo->n_stats = 0;
1574 drvinfo->testinfo_len = 0;
1575 drvinfo->regdump_len = 0;
1576 drvinfo->eedump_len = 0;
1577}
1578
1579static u32 ql_get_msglevel(struct net_device *ndev)
1580{
1581 struct ql3_adapter *qdev = netdev_priv(ndev);
1582 return qdev->msg_enable;
1583}
1584
1585static void ql_set_msglevel(struct net_device *ndev, u32 value)
1586{
1587 struct ql3_adapter *qdev = netdev_priv(ndev);
1588 qdev->msg_enable = value;
1589}
1590
1591static struct ethtool_ops ql3xxx_ethtool_ops = {
1592 .get_settings = ql_get_settings,
1593 .get_drvinfo = ql_get_drvinfo,
1594 .get_perm_addr = ethtool_op_get_perm_addr,
1595 .get_link = ethtool_op_get_link,
1596 .get_msglevel = ql_get_msglevel,
1597 .set_msglevel = ql_set_msglevel,
1598};
1599
1600static int ql_populate_free_queue(struct ql3_adapter *qdev)
1601{
1602 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1603 u64 map;
1604
1605 while (lrg_buf_cb) {
1606 if (!lrg_buf_cb->skb) {
1607 lrg_buf_cb->skb = dev_alloc_skb(qdev->lrg_buffer_len);
1608 if (unlikely(!lrg_buf_cb->skb)) {
1609 printk(KERN_DEBUG PFX
1610 "%s: Failed dev_alloc_skb().\n",
1611 qdev->ndev->name);
1612 break;
1613 } else {
1614 /*
1615 * We save some space to copy the ethhdr from
1616 * first buffer
1617 */
1618 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1619 map = pci_map_single(qdev->pdev,
1620 lrg_buf_cb->skb->data,
1621 qdev->lrg_buffer_len -
1622 QL_HEADER_SPACE,
1623 PCI_DMA_FROMDEVICE);
1624 lrg_buf_cb->buf_phy_addr_low =
1625 cpu_to_le32(LS_64BITS(map));
1626 lrg_buf_cb->buf_phy_addr_high =
1627 cpu_to_le32(MS_64BITS(map));
1628 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1629 pci_unmap_len_set(lrg_buf_cb, maplen,
1630 qdev->lrg_buffer_len -
1631 QL_HEADER_SPACE);
1632 --qdev->lrg_buf_skb_check;
1633 if (!qdev->lrg_buf_skb_check)
1634 return 1;
1635 }
1636 }
1637 lrg_buf_cb = lrg_buf_cb->next;
1638 }
1639 return 0;
1640}
1641
1642/*
1643 * Caller holds hw_lock.
1644 */
1645static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1646{
1647 struct bufq_addr_element *lrg_buf_q_ele;
1648 int i;
1649 struct ql_rcv_buf_cb *lrg_buf_cb;
1650 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1651
1652 if ((qdev->lrg_buf_free_count >= 8)
1653 && (qdev->lrg_buf_release_cnt >= 16)) {
1654
1655 if (qdev->lrg_buf_skb_check)
1656 if (!ql_populate_free_queue(qdev))
1657 return;
1658
1659 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1660
1661 while ((qdev->lrg_buf_release_cnt >= 16)
1662 && (qdev->lrg_buf_free_count >= 8)) {
1663
1664 for (i = 0; i < 8; i++) {
1665 lrg_buf_cb =
1666 ql_get_from_lrg_buf_free_list(qdev);
1667 lrg_buf_q_ele->addr_high =
1668 lrg_buf_cb->buf_phy_addr_high;
1669 lrg_buf_q_ele->addr_low =
1670 lrg_buf_cb->buf_phy_addr_low;
1671 lrg_buf_q_ele++;
1672
1673 qdev->lrg_buf_release_cnt--;
1674 }
1675
1676 qdev->lrg_buf_q_producer_index++;
1677
1678 if (qdev->lrg_buf_q_producer_index == NUM_LBUFQ_ENTRIES)
1679 qdev->lrg_buf_q_producer_index = 0;
1680
1681 if (qdev->lrg_buf_q_producer_index ==
1682 (NUM_LBUFQ_ENTRIES - 1)) {
1683 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1684 }
1685 }
1686
1687 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1688
1689 ql_write_common_reg(qdev,
1690 (u32 *) & port_regs->CommonRegs.
1691 rxLargeQProducerIndex,
1692 qdev->lrg_buf_q_producer_index);
1693 }
1694}
1695
1696static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1697 struct ob_mac_iocb_rsp *mac_rsp)
1698{
1699 struct ql_tx_buf_cb *tx_cb;
1700
1701 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1702 pci_unmap_single(qdev->pdev,
1703 pci_unmap_addr(tx_cb, mapaddr),
1704 pci_unmap_len(tx_cb, maplen), PCI_DMA_TODEVICE);
1705 dev_kfree_skb_irq(tx_cb->skb);
1706 qdev->stats.tx_packets++;
1707 qdev->stats.tx_bytes += tx_cb->skb->len;
1708 tx_cb->skb = NULL;
1709 atomic_inc(&qdev->tx_count);
1710}
1711
1712static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1713 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1714{
1715 long int offset;
1716 u32 lrg_buf_phy_addr_low = 0;
1717 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1718 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1719 u32 *curr_ial_ptr;
1720 struct sk_buff *skb;
1721 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1722
1723 /*
1724 * Get the inbound address list (small buffer).
1725 */
1726 offset = qdev->small_buf_index * QL_SMALL_BUFFER_SIZE;
1727 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1728 qdev->small_buf_index = 0;
1729
1730 curr_ial_ptr = (u32 *) (qdev->small_buf_virt_addr + offset);
1731 qdev->last_rsp_offset = qdev->small_buf_phy_addr_low + offset;
1732 qdev->small_buf_release_cnt++;
1733
1734 /* start of first buffer */
1735 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1736 lrg_buf_cb1 = &qdev->lrg_buf[qdev->lrg_buf_index];
1737 qdev->lrg_buf_release_cnt++;
1738 if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS)
1739 qdev->lrg_buf_index = 0;
1740 curr_ial_ptr++; /* 64-bit pointers require two incs. */
1741 curr_ial_ptr++;
1742
1743 /* start of second buffer */
1744 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1745 lrg_buf_cb2 = &qdev->lrg_buf[qdev->lrg_buf_index];
1746
1747 /*
1748 * Second buffer gets sent up the stack.
1749 */
1750 qdev->lrg_buf_release_cnt++;
1751 if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS)
1752 qdev->lrg_buf_index = 0;
1753 skb = lrg_buf_cb2->skb;
1754
1755 qdev->stats.rx_packets++;
1756 qdev->stats.rx_bytes += length;
1757
1758 skb_put(skb, length);
1759 pci_unmap_single(qdev->pdev,
1760 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1761 pci_unmap_len(lrg_buf_cb2, maplen),
1762 PCI_DMA_FROMDEVICE);
1763 prefetch(skb->data);
1764 skb->dev = qdev->ndev;
1765 skb->ip_summed = CHECKSUM_NONE;
1766 skb->protocol = eth_type_trans(skb, qdev->ndev);
1767
1768 netif_receive_skb(skb);
1769 qdev->ndev->last_rx = jiffies;
1770 lrg_buf_cb2->skb = NULL;
1771
1772 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1773 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1774}
1775
1776static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1777 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1778{
1779 long int offset;
1780 u32 lrg_buf_phy_addr_low = 0;
1781 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1782 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1783 u32 *curr_ial_ptr;
1784 struct sk_buff *skb1, *skb2;
1785 struct net_device *ndev = qdev->ndev;
1786 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1787 u16 size = 0;
1788
1789 /*
1790 * Get the inbound address list (small buffer).
1791 */
1792
1793 offset = qdev->small_buf_index * QL_SMALL_BUFFER_SIZE;
1794 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1795 qdev->small_buf_index = 0;
1796 curr_ial_ptr = (u32 *) (qdev->small_buf_virt_addr + offset);
1797 qdev->last_rsp_offset = qdev->small_buf_phy_addr_low + offset;
1798 qdev->small_buf_release_cnt++;
1799
1800 /* start of first buffer */
1801 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1802 lrg_buf_cb1 = &qdev->lrg_buf[qdev->lrg_buf_index];
1803
1804 qdev->lrg_buf_release_cnt++;
1805 if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS)
1806 qdev->lrg_buf_index = 0;
1807 skb1 = lrg_buf_cb1->skb;
1808 curr_ial_ptr++; /* 64-bit pointers require two incs. */
1809 curr_ial_ptr++;
1810
1811 /* start of second buffer */
1812 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1813 lrg_buf_cb2 = &qdev->lrg_buf[qdev->lrg_buf_index];
1814 skb2 = lrg_buf_cb2->skb;
1815 qdev->lrg_buf_release_cnt++;
1816 if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS)
1817 qdev->lrg_buf_index = 0;
1818
1819 qdev->stats.rx_packets++;
1820 qdev->stats.rx_bytes += length;
1821
1822 /*
1823 * Copy the ethhdr from first buffer to second. This
1824 * is necessary for IP completions.
1825 */
1826 if (*((u16 *) skb1->data) != 0xFFFF)
1827 size = VLAN_ETH_HLEN;
1828 else
1829 size = ETH_HLEN;
1830
1831 skb_put(skb2, length); /* Just the second buffer length here. */
1832 pci_unmap_single(qdev->pdev,
1833 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1834 pci_unmap_len(lrg_buf_cb2, maplen),
1835 PCI_DMA_FROMDEVICE);
1836 prefetch(skb2->data);
1837
1838 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1839 skb2->dev = qdev->ndev;
1840 skb2->ip_summed = CHECKSUM_NONE;
1841 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1842
1843 netif_receive_skb(skb2);
1844 ndev->last_rx = jiffies;
1845 lrg_buf_cb2->skb = NULL;
1846
1847 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1848 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1849}
1850
1851static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1852 int *tx_cleaned, int *rx_cleaned, int work_to_do)
1853{
1854 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1855 struct net_rsp_iocb *net_rsp;
1856 struct net_device *ndev = qdev->ndev;
1857 unsigned long hw_flags;
1858
1859 /* While there are entries in the completion queue. */
1860 while ((cpu_to_le32(*(qdev->prsp_producer_index)) !=
1861 qdev->rsp_consumer_index) && (*rx_cleaned < work_to_do)) {
1862
1863 net_rsp = qdev->rsp_current;
1864 switch (net_rsp->opcode) {
1865
1866 case OPCODE_OB_MAC_IOCB_FN0:
1867 case OPCODE_OB_MAC_IOCB_FN2:
1868 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1869 net_rsp);
1870 (*tx_cleaned)++;
1871 break;
1872
1873 case OPCODE_IB_MAC_IOCB:
1874 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1875 net_rsp);
1876 (*rx_cleaned)++;
1877 break;
1878
1879 case OPCODE_IB_IP_IOCB:
1880 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1881 net_rsp);
1882 (*rx_cleaned)++;
1883 break;
1884 default:
1885 {
1886 u32 *tmp = (u32 *) net_rsp;
1887 printk(KERN_ERR PFX
1888 "%s: Hit default case, not "
1889 "handled!\n"
1890 " dropping the packet, opcode = "
1891 "%x.\n",
1892 ndev->name, net_rsp->opcode);
1893 printk(KERN_ERR PFX
1894 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1895 (unsigned long int)tmp[0],
1896 (unsigned long int)tmp[1],
1897 (unsigned long int)tmp[2],
1898 (unsigned long int)tmp[3]);
1899 }
1900 }
1901
1902 qdev->rsp_consumer_index++;
1903
1904 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
1905 qdev->rsp_consumer_index = 0;
1906 qdev->rsp_current = qdev->rsp_q_virt_addr;
1907 } else {
1908 qdev->rsp_current++;
1909 }
1910 }
1911
1912 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1913
1914 ql_update_lrg_bufq_prod_index(qdev);
1915
1916 if (qdev->small_buf_release_cnt >= 16) {
1917 while (qdev->small_buf_release_cnt >= 16) {
1918 qdev->small_buf_q_producer_index++;
1919
1920 if (qdev->small_buf_q_producer_index ==
1921 NUM_SBUFQ_ENTRIES)
1922 qdev->small_buf_q_producer_index = 0;
1923 qdev->small_buf_release_cnt -= 8;
1924 }
1925
1926 ql_write_common_reg(qdev,
1927 (u32 *) & port_regs->CommonRegs.
1928 rxSmallQProducerIndex,
1929 qdev->small_buf_q_producer_index);
1930 }
1931
1932 ql_write_common_reg(qdev,
1933 (u32 *) & port_regs->CommonRegs.rspQConsumerIndex,
1934 qdev->rsp_consumer_index);
1935 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1936
1937 if (unlikely(netif_queue_stopped(qdev->ndev))) {
1938 if (netif_queue_stopped(qdev->ndev) &&
1939 (atomic_read(&qdev->tx_count) > (NUM_REQ_Q_ENTRIES / 4)))
1940 netif_wake_queue(qdev->ndev);
1941 }
1942
1943 return *tx_cleaned + *rx_cleaned;
1944}
1945
1946static int ql_poll(struct net_device *ndev, int *budget)
1947{
1948 struct ql3_adapter *qdev = netdev_priv(ndev);
1949 int work_to_do = min(*budget, ndev->quota);
1950 int rx_cleaned = 0, tx_cleaned = 0;
1951
1952 if (!netif_carrier_ok(ndev))
1953 goto quit_polling;
1954
1955 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
1956 *budget -= rx_cleaned;
1957 ndev->quota -= rx_cleaned;
1958
1959 if ((!tx_cleaned && !rx_cleaned) || !netif_running(ndev)) {
1960quit_polling:
1961 netif_rx_complete(ndev);
1962 ql_enable_interrupts(qdev);
1963 return 0;
1964 }
1965 return 1;
1966}
1967
1968static irqreturn_t ql3xxx_isr(int irq, void *dev_id, struct pt_regs *regs)
1969{
1970
1971 struct net_device *ndev = dev_id;
1972 struct ql3_adapter *qdev = netdev_priv(ndev);
1973 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1974 u32 value;
1975 int handled = 1;
1976 u32 var;
1977
1978 port_regs = qdev->mem_map_registers;
1979
1980 value =
1981 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
1982
1983 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
1984 spin_lock(&qdev->adapter_lock);
1985 netif_stop_queue(qdev->ndev);
1986 netif_carrier_off(qdev->ndev);
1987 ql_disable_interrupts(qdev);
1988 qdev->port_link_state = LS_DOWN;
1989 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
1990
1991 if (value & ISP_CONTROL_FE) {
1992 /*
1993 * Chip Fatal Error.
1994 */
1995 var =
1996 ql_read_page0_reg_l(qdev,
1997 &port_regs->PortFatalErrStatus);
1998 printk(KERN_WARNING PFX
1999 "%s: Resetting chip. PortFatalErrStatus "
2000 "register = 0x%x\n", ndev->name, var);
2001 set_bit(QL_RESET_START,&qdev->flags) ;
2002 } else {
2003 /*
2004 * Soft Reset Requested.
2005 */
2006 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2007 printk(KERN_ERR PFX
2008 "%s: Another function issued a reset to the "
2009 "chip. ISR value = %x.\n", ndev->name, value);
2010 }
2011 queue_work(qdev->workqueue, &qdev->reset_work);
2012 spin_unlock(&qdev->adapter_lock);
2013 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2014 ql_disable_interrupts(qdev);
2015 if (likely(netif_rx_schedule_prep(ndev)))
2016 __netif_rx_schedule(ndev);
2017 else
2018 ql_enable_interrupts(qdev);
2019 } else {
2020 return IRQ_NONE;
2021 }
2022
2023 return IRQ_RETVAL(handled);
2024}
2025
2026static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2027{
2028 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2029 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2030 struct ql_tx_buf_cb *tx_cb;
2031 struct ob_mac_iocb_req *mac_iocb_ptr;
2032 u64 map;
2033
2034 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2035 if (!netif_queue_stopped(ndev))
2036 netif_stop_queue(ndev);
2037 return NETDEV_TX_BUSY;
2038 }
2039 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2040 mac_iocb_ptr = tx_cb->queue_entry;
2041 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2042 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2043 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2044 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2045 mac_iocb_ptr->data_len = cpu_to_le16((u16) skb->len);
2046 tx_cb->skb = skb;
2047 map = pci_map_single(qdev->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
2048 mac_iocb_ptr->buf_addr0_low = cpu_to_le32(LS_64BITS(map));
2049 mac_iocb_ptr->buf_addr0_high = cpu_to_le32(MS_64BITS(map));
2050 mac_iocb_ptr->buf_0_len = cpu_to_le32(skb->len | OB_MAC_IOCB_REQ_E);
2051 pci_unmap_addr_set(tx_cb, mapaddr, map);
2052 pci_unmap_len_set(tx_cb, maplen, skb->len);
2053 atomic_dec(&qdev->tx_count);
2054
2055 qdev->req_producer_index++;
2056 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2057 qdev->req_producer_index = 0;
2058 wmb();
2059 ql_write_common_reg_l(qdev,
2060 (u32 *) & port_regs->CommonRegs.reqQProducerIndex,
2061 qdev->req_producer_index);
2062
2063 ndev->trans_start = jiffies;
2064 if (netif_msg_tx_queued(qdev))
2065 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2066 ndev->name, qdev->req_producer_index, skb->len);
2067
2068 return NETDEV_TX_OK;
2069}
2070static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2071{
2072 qdev->req_q_size =
2073 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2074
2075 qdev->req_q_virt_addr =
2076 pci_alloc_consistent(qdev->pdev,
2077 (size_t) qdev->req_q_size,
2078 &qdev->req_q_phy_addr);
2079
2080 if ((qdev->req_q_virt_addr == NULL) ||
2081 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2082 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2083 qdev->ndev->name);
2084 return -ENOMEM;
2085 }
2086
2087 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2088
2089 qdev->rsp_q_virt_addr =
2090 pci_alloc_consistent(qdev->pdev,
2091 (size_t) qdev->rsp_q_size,
2092 &qdev->rsp_q_phy_addr);
2093
2094 if ((qdev->rsp_q_virt_addr == NULL) ||
2095 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2096 printk(KERN_ERR PFX
2097 "%s: rspQ allocation failed\n",
2098 qdev->ndev->name);
2099 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2100 qdev->req_q_virt_addr,
2101 qdev->req_q_phy_addr);
2102 return -ENOMEM;
2103 }
2104
2105 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2106
2107 return 0;
2108}
2109
2110static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2111{
2112 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2113 printk(KERN_INFO PFX
2114 "%s: Already done.\n", qdev->ndev->name);
2115 return;
2116 }
2117
2118 pci_free_consistent(qdev->pdev,
2119 qdev->req_q_size,
2120 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2121
2122 qdev->req_q_virt_addr = NULL;
2123
2124 pci_free_consistent(qdev->pdev,
2125 qdev->rsp_q_size,
2126 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2127
2128 qdev->rsp_q_virt_addr = NULL;
2129
2130 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2131}
2132
2133static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2134{
2135 /* Create Large Buffer Queue */
2136 qdev->lrg_buf_q_size =
2137 NUM_LBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2138 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2139 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2140 else
2141 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2142
2143 qdev->lrg_buf_q_alloc_virt_addr =
2144 pci_alloc_consistent(qdev->pdev,
2145 qdev->lrg_buf_q_alloc_size,
2146 &qdev->lrg_buf_q_alloc_phy_addr);
2147
2148 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2149 printk(KERN_ERR PFX
2150 "%s: lBufQ failed\n", qdev->ndev->name);
2151 return -ENOMEM;
2152 }
2153 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2154 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2155
2156 /* Create Small Buffer Queue */
2157 qdev->small_buf_q_size =
2158 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2159 if (qdev->small_buf_q_size < PAGE_SIZE)
2160 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2161 else
2162 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2163
2164 qdev->small_buf_q_alloc_virt_addr =
2165 pci_alloc_consistent(qdev->pdev,
2166 qdev->small_buf_q_alloc_size,
2167 &qdev->small_buf_q_alloc_phy_addr);
2168
2169 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2170 printk(KERN_ERR PFX
2171 "%s: Small Buffer Queue allocation failed.\n",
2172 qdev->ndev->name);
2173 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2174 qdev->lrg_buf_q_alloc_virt_addr,
2175 qdev->lrg_buf_q_alloc_phy_addr);
2176 return -ENOMEM;
2177 }
2178
2179 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2180 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2181 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2182 return 0;
2183}
2184
2185static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2186{
2187 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2188 printk(KERN_INFO PFX
2189 "%s: Already done.\n", qdev->ndev->name);
2190 return;
2191 }
2192
2193 pci_free_consistent(qdev->pdev,
2194 qdev->lrg_buf_q_alloc_size,
2195 qdev->lrg_buf_q_alloc_virt_addr,
2196 qdev->lrg_buf_q_alloc_phy_addr);
2197
2198 qdev->lrg_buf_q_virt_addr = NULL;
2199
2200 pci_free_consistent(qdev->pdev,
2201 qdev->small_buf_q_alloc_size,
2202 qdev->small_buf_q_alloc_virt_addr,
2203 qdev->small_buf_q_alloc_phy_addr);
2204
2205 qdev->small_buf_q_virt_addr = NULL;
2206
2207 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2208}
2209
2210static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2211{
2212 int i;
2213 struct bufq_addr_element *small_buf_q_entry;
2214
2215 /* Currently we allocate on one of memory and use it for smallbuffers */
2216 qdev->small_buf_total_size =
2217 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2218 QL_SMALL_BUFFER_SIZE);
2219
2220 qdev->small_buf_virt_addr =
2221 pci_alloc_consistent(qdev->pdev,
2222 qdev->small_buf_total_size,
2223 &qdev->small_buf_phy_addr);
2224
2225 if (qdev->small_buf_virt_addr == NULL) {
2226 printk(KERN_ERR PFX
2227 "%s: Failed to get small buffer memory.\n",
2228 qdev->ndev->name);
2229 return -ENOMEM;
2230 }
2231
2232 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2233 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2234
2235 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2236
2237 qdev->last_rsp_offset = qdev->small_buf_phy_addr_low;
2238
2239 /* Initialize the small buffer queue. */
2240 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2241 small_buf_q_entry->addr_high =
2242 cpu_to_le32(qdev->small_buf_phy_addr_high);
2243 small_buf_q_entry->addr_low =
2244 cpu_to_le32(qdev->small_buf_phy_addr_low +
2245 (i * QL_SMALL_BUFFER_SIZE));
2246 small_buf_q_entry++;
2247 }
2248 qdev->small_buf_index = 0;
2249 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2250 return 0;
2251}
2252
2253static void ql_free_small_buffers(struct ql3_adapter *qdev)
2254{
2255 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2256 printk(KERN_INFO PFX
2257 "%s: Already done.\n", qdev->ndev->name);
2258 return;
2259 }
2260 if (qdev->small_buf_virt_addr != NULL) {
2261 pci_free_consistent(qdev->pdev,
2262 qdev->small_buf_total_size,
2263 qdev->small_buf_virt_addr,
2264 qdev->small_buf_phy_addr);
2265
2266 qdev->small_buf_virt_addr = NULL;
2267 }
2268}
2269
2270static void ql_free_large_buffers(struct ql3_adapter *qdev)
2271{
2272 int i = 0;
2273 struct ql_rcv_buf_cb *lrg_buf_cb;
2274
2275 for (i = 0; i < NUM_LARGE_BUFFERS; i++) {
2276 lrg_buf_cb = &qdev->lrg_buf[i];
2277 if (lrg_buf_cb->skb) {
2278 dev_kfree_skb(lrg_buf_cb->skb);
2279 pci_unmap_single(qdev->pdev,
2280 pci_unmap_addr(lrg_buf_cb, mapaddr),
2281 pci_unmap_len(lrg_buf_cb, maplen),
2282 PCI_DMA_FROMDEVICE);
2283 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2284 } else {
2285 break;
2286 }
2287 }
2288}
2289
2290static void ql_init_large_buffers(struct ql3_adapter *qdev)
2291{
2292 int i;
2293 struct ql_rcv_buf_cb *lrg_buf_cb;
2294 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2295
2296 for (i = 0; i < NUM_LARGE_BUFFERS; i++) {
2297 lrg_buf_cb = &qdev->lrg_buf[i];
2298 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2299 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2300 buf_addr_ele++;
2301 }
2302 qdev->lrg_buf_index = 0;
2303 qdev->lrg_buf_skb_check = 0;
2304}
2305
2306static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2307{
2308 int i;
2309 struct ql_rcv_buf_cb *lrg_buf_cb;
2310 struct sk_buff *skb;
2311 u64 map;
2312
2313 for (i = 0; i < NUM_LARGE_BUFFERS; i++) {
2314 skb = dev_alloc_skb(qdev->lrg_buffer_len);
2315 if (unlikely(!skb)) {
2316 /* Better luck next round */
2317 printk(KERN_ERR PFX
2318 "%s: large buff alloc failed, "
2319 "for %d bytes at index %d.\n",
2320 qdev->ndev->name,
2321 qdev->lrg_buffer_len * 2, i);
2322 ql_free_large_buffers(qdev);
2323 return -ENOMEM;
2324 } else {
2325
2326 lrg_buf_cb = &qdev->lrg_buf[i];
2327 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2328 lrg_buf_cb->index = i;
2329 lrg_buf_cb->skb = skb;
2330 /*
2331 * We save some space to copy the ethhdr from first
2332 * buffer
2333 */
2334 skb_reserve(skb, QL_HEADER_SPACE);
2335 map = pci_map_single(qdev->pdev,
2336 skb->data,
2337 qdev->lrg_buffer_len -
2338 QL_HEADER_SPACE,
2339 PCI_DMA_FROMDEVICE);
2340 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2341 pci_unmap_len_set(lrg_buf_cb, maplen,
2342 qdev->lrg_buffer_len -
2343 QL_HEADER_SPACE);
2344 lrg_buf_cb->buf_phy_addr_low =
2345 cpu_to_le32(LS_64BITS(map));
2346 lrg_buf_cb->buf_phy_addr_high =
2347 cpu_to_le32(MS_64BITS(map));
2348 }
2349 }
2350 return 0;
2351}
2352
2353static void ql_create_send_free_list(struct ql3_adapter *qdev)
2354{
2355 struct ql_tx_buf_cb *tx_cb;
2356 int i;
2357 struct ob_mac_iocb_req *req_q_curr =
2358 qdev->req_q_virt_addr;
2359
2360 /* Create free list of transmit buffers */
2361 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2362 tx_cb = &qdev->tx_buf[i];
2363 tx_cb->skb = NULL;
2364 tx_cb->queue_entry = req_q_curr;
2365 req_q_curr++;
2366 }
2367}
2368
2369static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2370{
2371 if (qdev->ndev->mtu == NORMAL_MTU_SIZE)
2372 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2373 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2374 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2375 } else {
2376 printk(KERN_ERR PFX
2377 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2378 qdev->ndev->name);
2379 return -ENOMEM;
2380 }
2381 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2382 qdev->max_frame_size =
2383 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2384
2385 /*
2386 * First allocate a page of shared memory and use it for shadow
2387 * locations of Network Request Queue Consumer Address Register and
2388 * Network Completion Queue Producer Index Register
2389 */
2390 qdev->shadow_reg_virt_addr =
2391 pci_alloc_consistent(qdev->pdev,
2392 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2393
2394 if (qdev->shadow_reg_virt_addr != NULL) {
2395 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2396 qdev->req_consumer_index_phy_addr_high =
2397 MS_64BITS(qdev->shadow_reg_phy_addr);
2398 qdev->req_consumer_index_phy_addr_low =
2399 LS_64BITS(qdev->shadow_reg_phy_addr);
2400
2401 qdev->prsp_producer_index =
2402 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2403 qdev->rsp_producer_index_phy_addr_high =
2404 qdev->req_consumer_index_phy_addr_high;
2405 qdev->rsp_producer_index_phy_addr_low =
2406 qdev->req_consumer_index_phy_addr_low + 8;
2407 } else {
2408 printk(KERN_ERR PFX
2409 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2410 return -ENOMEM;
2411 }
2412
2413 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2414 printk(KERN_ERR PFX
2415 "%s: ql_alloc_net_req_rsp_queues failed.\n",
2416 qdev->ndev->name);
2417 goto err_req_rsp;
2418 }
2419
2420 if (ql_alloc_buffer_queues(qdev) != 0) {
2421 printk(KERN_ERR PFX
2422 "%s: ql_alloc_buffer_queues failed.\n",
2423 qdev->ndev->name);
2424 goto err_buffer_queues;
2425 }
2426
2427 if (ql_alloc_small_buffers(qdev) != 0) {
2428 printk(KERN_ERR PFX
2429 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2430 goto err_small_buffers;
2431 }
2432
2433 if (ql_alloc_large_buffers(qdev) != 0) {
2434 printk(KERN_ERR PFX
2435 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2436 goto err_small_buffers;
2437 }
2438
2439 /* Initialize the large buffer queue. */
2440 ql_init_large_buffers(qdev);
2441 ql_create_send_free_list(qdev);
2442
2443 qdev->rsp_current = qdev->rsp_q_virt_addr;
2444
2445 return 0;
2446
2447err_small_buffers:
2448 ql_free_buffer_queues(qdev);
2449err_buffer_queues:
2450 ql_free_net_req_rsp_queues(qdev);
2451err_req_rsp:
2452 pci_free_consistent(qdev->pdev,
2453 PAGE_SIZE,
2454 qdev->shadow_reg_virt_addr,
2455 qdev->shadow_reg_phy_addr);
2456
2457 return -ENOMEM;
2458}
2459
2460static void ql_free_mem_resources(struct ql3_adapter *qdev)
2461{
2462 ql_free_large_buffers(qdev);
2463 ql_free_small_buffers(qdev);
2464 ql_free_buffer_queues(qdev);
2465 ql_free_net_req_rsp_queues(qdev);
2466 if (qdev->shadow_reg_virt_addr != NULL) {
2467 pci_free_consistent(qdev->pdev,
2468 PAGE_SIZE,
2469 qdev->shadow_reg_virt_addr,
2470 qdev->shadow_reg_phy_addr);
2471 qdev->shadow_reg_virt_addr = NULL;
2472 }
2473}
2474
2475static int ql_init_misc_registers(struct ql3_adapter *qdev)
2476{
2477 struct ql3xxx_local_ram_registers *local_ram =
2478 (struct ql3xxx_local_ram_registers *)qdev->mem_map_registers;
2479
2480 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2481 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2482 2) << 4))
2483 return -1;
2484
2485 ql_write_page2_reg(qdev,
2486 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2487
2488 ql_write_page2_reg(qdev,
2489 &local_ram->maxBufletCount,
2490 qdev->nvram_data.bufletCount);
2491
2492 ql_write_page2_reg(qdev,
2493 &local_ram->freeBufletThresholdLow,
2494 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2495 (qdev->nvram_data.tcpWindowThreshold0));
2496
2497 ql_write_page2_reg(qdev,
2498 &local_ram->freeBufletThresholdHigh,
2499 qdev->nvram_data.tcpWindowThreshold50);
2500
2501 ql_write_page2_reg(qdev,
2502 &local_ram->ipHashTableBase,
2503 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2504 qdev->nvram_data.ipHashTableBaseLo);
2505 ql_write_page2_reg(qdev,
2506 &local_ram->ipHashTableCount,
2507 qdev->nvram_data.ipHashTableSize);
2508 ql_write_page2_reg(qdev,
2509 &local_ram->tcpHashTableBase,
2510 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2511 qdev->nvram_data.tcpHashTableBaseLo);
2512 ql_write_page2_reg(qdev,
2513 &local_ram->tcpHashTableCount,
2514 qdev->nvram_data.tcpHashTableSize);
2515 ql_write_page2_reg(qdev,
2516 &local_ram->ncbBase,
2517 (qdev->nvram_data.ncbTableBaseHi << 16) |
2518 qdev->nvram_data.ncbTableBaseLo);
2519 ql_write_page2_reg(qdev,
2520 &local_ram->maxNcbCount,
2521 qdev->nvram_data.ncbTableSize);
2522 ql_write_page2_reg(qdev,
2523 &local_ram->drbBase,
2524 (qdev->nvram_data.drbTableBaseHi << 16) |
2525 qdev->nvram_data.drbTableBaseLo);
2526 ql_write_page2_reg(qdev,
2527 &local_ram->maxDrbCount,
2528 qdev->nvram_data.drbTableSize);
2529 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2530 return 0;
2531}
2532
2533static int ql_adapter_initialize(struct ql3_adapter *qdev)
2534{
2535 u32 value;
2536 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2537 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2538 (struct ql3xxx_host_memory_registers *)port_regs;
2539 u32 delay = 10;
2540 int status = 0;
2541
2542 if(ql_mii_setup(qdev))
2543 return -1;
2544
2545 /* Bring out PHY out of reset */
2546 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2547 (ISP_SERIAL_PORT_IF_WE |
2548 (ISP_SERIAL_PORT_IF_WE << 16)));
2549
2550 qdev->port_link_state = LS_DOWN;
2551 netif_carrier_off(qdev->ndev);
2552
2553 /* V2 chip fix for ARS-39168. */
2554 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2555 (ISP_SERIAL_PORT_IF_SDE |
2556 (ISP_SERIAL_PORT_IF_SDE << 16)));
2557
2558 /* Request Queue Registers */
2559 *((u32 *) (qdev->preq_consumer_index)) = 0;
2560 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2561 qdev->req_producer_index = 0;
2562
2563 ql_write_page1_reg(qdev,
2564 &hmem_regs->reqConsumerIndexAddrHigh,
2565 qdev->req_consumer_index_phy_addr_high);
2566 ql_write_page1_reg(qdev,
2567 &hmem_regs->reqConsumerIndexAddrLow,
2568 qdev->req_consumer_index_phy_addr_low);
2569
2570 ql_write_page1_reg(qdev,
2571 &hmem_regs->reqBaseAddrHigh,
2572 MS_64BITS(qdev->req_q_phy_addr));
2573 ql_write_page1_reg(qdev,
2574 &hmem_regs->reqBaseAddrLow,
2575 LS_64BITS(qdev->req_q_phy_addr));
2576 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2577
2578 /* Response Queue Registers */
2579 *((u16 *) (qdev->prsp_producer_index)) = 0;
2580 qdev->rsp_consumer_index = 0;
2581 qdev->rsp_current = qdev->rsp_q_virt_addr;
2582
2583 ql_write_page1_reg(qdev,
2584 &hmem_regs->rspProducerIndexAddrHigh,
2585 qdev->rsp_producer_index_phy_addr_high);
2586
2587 ql_write_page1_reg(qdev,
2588 &hmem_regs->rspProducerIndexAddrLow,
2589 qdev->rsp_producer_index_phy_addr_low);
2590
2591 ql_write_page1_reg(qdev,
2592 &hmem_regs->rspBaseAddrHigh,
2593 MS_64BITS(qdev->rsp_q_phy_addr));
2594
2595 ql_write_page1_reg(qdev,
2596 &hmem_regs->rspBaseAddrLow,
2597 LS_64BITS(qdev->rsp_q_phy_addr));
2598
2599 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2600
2601 /* Large Buffer Queue */
2602 ql_write_page1_reg(qdev,
2603 &hmem_regs->rxLargeQBaseAddrHigh,
2604 MS_64BITS(qdev->lrg_buf_q_phy_addr));
2605
2606 ql_write_page1_reg(qdev,
2607 &hmem_regs->rxLargeQBaseAddrLow,
2608 LS_64BITS(qdev->lrg_buf_q_phy_addr));
2609
2610 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, NUM_LBUFQ_ENTRIES);
2611
2612 ql_write_page1_reg(qdev,
2613 &hmem_regs->rxLargeBufferLength,
2614 qdev->lrg_buffer_len);
2615
2616 /* Small Buffer Queue */
2617 ql_write_page1_reg(qdev,
2618 &hmem_regs->rxSmallQBaseAddrHigh,
2619 MS_64BITS(qdev->small_buf_q_phy_addr));
2620
2621 ql_write_page1_reg(qdev,
2622 &hmem_regs->rxSmallQBaseAddrLow,
2623 LS_64BITS(qdev->small_buf_q_phy_addr));
2624
2625 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
2626 ql_write_page1_reg(qdev,
2627 &hmem_regs->rxSmallBufferLength,
2628 QL_SMALL_BUFFER_SIZE);
2629
2630 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
2631 qdev->small_buf_release_cnt = 8;
2632 qdev->lrg_buf_q_producer_index = NUM_LBUFQ_ENTRIES - 1;
2633 qdev->lrg_buf_release_cnt = 8;
2634 qdev->lrg_buf_next_free =
2635 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
2636 qdev->small_buf_index = 0;
2637 qdev->lrg_buf_index = 0;
2638 qdev->lrg_buf_free_count = 0;
2639 qdev->lrg_buf_free_head = NULL;
2640 qdev->lrg_buf_free_tail = NULL;
2641
2642 ql_write_common_reg(qdev,
2643 (u32 *) & port_regs->CommonRegs.
2644 rxSmallQProducerIndex,
2645 qdev->small_buf_q_producer_index);
2646 ql_write_common_reg(qdev,
2647 (u32 *) & port_regs->CommonRegs.
2648 rxLargeQProducerIndex,
2649 qdev->lrg_buf_q_producer_index);
2650
2651 /*
2652 * Find out if the chip has already been initialized. If it has, then
2653 * we skip some of the initialization.
2654 */
2655 clear_bit(QL_LINK_MASTER, &qdev->flags);
2656 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2657 if ((value & PORT_STATUS_IC) == 0) {
2658
2659 /* Chip has not been configured yet, so let it rip. */
2660 if(ql_init_misc_registers(qdev)) {
2661 status = -1;
2662 goto out;
2663 }
2664
2665 if (qdev->mac_index)
2666 ql_write_page0_reg(qdev,
2667 &port_regs->mac1MaxFrameLengthReg,
2668 qdev->max_frame_size);
2669 else
2670 ql_write_page0_reg(qdev,
2671 &port_regs->mac0MaxFrameLengthReg,
2672 qdev->max_frame_size);
2673
2674 value = qdev->nvram_data.tcpMaxWindowSize;
2675 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
2676
2677 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
2678
2679 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
2680 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
2681 * 2) << 13)) {
2682 status = -1;
2683 goto out;
2684 }
2685 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
2686 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
2687 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
2688 16) | (INTERNAL_CHIP_SD |
2689 INTERNAL_CHIP_WE)));
2690 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
2691 }
2692
2693
2694 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
2695 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2696 2) << 7)) {
2697 status = -1;
2698 goto out;
2699 }
2700
2701 ql_init_scan_mode(qdev);
2702 ql_get_phy_owner(qdev);
2703
2704 /* Load the MAC Configuration */
2705
2706 /* Program lower 32 bits of the MAC address */
2707 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2708 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
2709 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2710 ((qdev->ndev->dev_addr[2] << 24)
2711 | (qdev->ndev->dev_addr[3] << 16)
2712 | (qdev->ndev->dev_addr[4] << 8)
2713 | qdev->ndev->dev_addr[5]));
2714
2715 /* Program top 16 bits of the MAC address */
2716 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2717 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
2718 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2719 ((qdev->ndev->dev_addr[0] << 8)
2720 | qdev->ndev->dev_addr[1]));
2721
2722 /* Enable Primary MAC */
2723 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2724 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
2725 MAC_ADDR_INDIRECT_PTR_REG_PE));
2726
2727 /* Clear Primary and Secondary IP addresses */
2728 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2729 ((IP_ADDR_INDEX_REG_MASK << 16) |
2730 (qdev->mac_index << 2)));
2731 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2732
2733 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2734 ((IP_ADDR_INDEX_REG_MASK << 16) |
2735 ((qdev->mac_index << 2) + 1)));
2736 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2737
2738 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
2739
2740 /* Indicate Configuration Complete */
2741 ql_write_page0_reg(qdev,
2742 &port_regs->portControl,
2743 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
2744
2745 do {
2746 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2747 if (value & PORT_STATUS_IC)
2748 break;
2749 msleep(500);
2750 } while (--delay);
2751
2752 if (delay == 0) {
2753 printk(KERN_ERR PFX
2754 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
2755 status = -1;
2756 goto out;
2757 }
2758
2759 /* Enable Ethernet Function */
2760 value =
2761 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
2762 PORT_CONTROL_HH);
2763 ql_write_page0_reg(qdev, &port_regs->portControl,
2764 ((value << 16) | value));
2765
2766out:
2767 return status;
2768}
2769
2770/*
2771 * Caller holds hw_lock.
2772 */
2773static int ql_adapter_reset(struct ql3_adapter *qdev)
2774{
2775 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2776 int status = 0;
2777 u16 value;
2778 int max_wait_time;
2779
2780 set_bit(QL_RESET_ACTIVE, &qdev->flags);
2781 clear_bit(QL_RESET_DONE, &qdev->flags);
2782
2783 /*
2784 * Issue soft reset to chip.
2785 */
2786 printk(KERN_DEBUG PFX
2787 "%s: Issue soft reset to chip.\n",
2788 qdev->ndev->name);
2789 ql_write_common_reg(qdev,
2790 (u32 *) & port_regs->CommonRegs.ispControlStatus,
2791 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
2792
2793 /* Wait 3 seconds for reset to complete. */
2794 printk(KERN_DEBUG PFX
2795 "%s: Wait 10 milliseconds for reset to complete.\n",
2796 qdev->ndev->name);
2797
2798 /* Wait until the firmware tells us the Soft Reset is done */
2799 max_wait_time = 5;
2800 do {
2801 value =
2802 ql_read_common_reg(qdev,
2803 &port_regs->CommonRegs.ispControlStatus);
2804 if ((value & ISP_CONTROL_SR) == 0)
2805 break;
2806
2807 ssleep(1);
2808 } while ((--max_wait_time));
2809
2810 /*
2811 * Also, make sure that the Network Reset Interrupt bit has been
2812 * cleared after the soft reset has taken place.
2813 */
2814 value =
2815 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
2816 if (value & ISP_CONTROL_RI) {
2817 printk(KERN_DEBUG PFX
2818 "ql_adapter_reset: clearing RI after reset.\n");
2819 ql_write_common_reg(qdev,
2820 (u32 *) & port_regs->CommonRegs.
2821 ispControlStatus,
2822 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
2823 }
2824
2825 if (max_wait_time == 0) {
2826 /* Issue Force Soft Reset */
2827 ql_write_common_reg(qdev,
2828 (u32 *) & port_regs->CommonRegs.
2829 ispControlStatus,
2830 ((ISP_CONTROL_FSR << 16) |
2831 ISP_CONTROL_FSR));
2832 /*
2833 * Wait until the firmware tells us the Force Soft Reset is
2834 * done
2835 */
2836 max_wait_time = 5;
2837 do {
2838 value =
2839 ql_read_common_reg(qdev,
2840 &port_regs->CommonRegs.
2841 ispControlStatus);
2842 if ((value & ISP_CONTROL_FSR) == 0) {
2843 break;
2844 }
2845 ssleep(1);
2846 } while ((--max_wait_time));
2847 }
2848 if (max_wait_time == 0)
2849 status = 1;
2850
2851 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
2852 set_bit(QL_RESET_DONE, &qdev->flags);
2853 return status;
2854}
2855
2856static void ql_set_mac_info(struct ql3_adapter *qdev)
2857{
2858 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2859 u32 value, port_status;
2860 u8 func_number;
2861
2862 /* Get the function number */
2863 value =
2864 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2865 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
2866 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
2867 switch (value & ISP_CONTROL_FN_MASK) {
2868 case ISP_CONTROL_FN0_NET:
2869 qdev->mac_index = 0;
2870 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
2871 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
2872 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
2873 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
2874 qdev->PHYAddr = PORT0_PHY_ADDRESS;
2875 if (port_status & PORT_STATUS_SM0)
2876 set_bit(QL_LINK_OPTICAL,&qdev->flags);
2877 else
2878 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
2879 break;
2880
2881 case ISP_CONTROL_FN1_NET:
2882 qdev->mac_index = 1;
2883 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
2884 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
2885 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
2886 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
2887 qdev->PHYAddr = PORT1_PHY_ADDRESS;
2888 if (port_status & PORT_STATUS_SM1)
2889 set_bit(QL_LINK_OPTICAL,&qdev->flags);
2890 else
2891 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
2892 break;
2893
2894 case ISP_CONTROL_FN0_SCSI:
2895 case ISP_CONTROL_FN1_SCSI:
2896 default:
2897 printk(KERN_DEBUG PFX
2898 "%s: Invalid function number, ispControlStatus = 0x%x\n",
2899 qdev->ndev->name,value);
2900 break;
2901 }
2902 qdev->numPorts = qdev->nvram_data.numPorts;
2903}
2904
2905static void ql_display_dev_info(struct net_device *ndev)
2906{
2907 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2908 struct pci_dev *pdev = qdev->pdev;
2909
2910 printk(KERN_INFO PFX
2911 "\n%s Adapter %d RevisionID %d found on PCI slot %d.\n",
2912 DRV_NAME, qdev->index, qdev->chip_rev_id, qdev->pci_slot);
2913 printk(KERN_INFO PFX
2914 "%s Interface.\n",
2915 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
2916
2917 /*
2918 * Print PCI bus width/type.
2919 */
2920 printk(KERN_INFO PFX
2921 "Bus interface is %s %s.\n",
2922 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
2923 ((qdev->pci_x) ? "PCI-X" : "PCI"));
2924
2925 printk(KERN_INFO PFX
2926 "mem IO base address adjusted = 0x%p\n",
2927 qdev->mem_map_registers);
2928 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
2929
2930 if (netif_msg_probe(qdev))
2931 printk(KERN_INFO PFX
2932 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
2933 ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
2934 ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
2935 ndev->dev_addr[5]);
2936}
2937
2938static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
2939{
2940 struct net_device *ndev = qdev->ndev;
2941 int retval = 0;
2942
2943 netif_stop_queue(ndev);
2944 netif_carrier_off(ndev);
2945
2946 clear_bit(QL_ADAPTER_UP,&qdev->flags);
2947 clear_bit(QL_LINK_MASTER,&qdev->flags);
2948
2949 ql_disable_interrupts(qdev);
2950
2951 free_irq(qdev->pdev->irq, ndev);
2952
2953 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
2954 printk(KERN_INFO PFX
2955 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
2956 clear_bit(QL_MSI_ENABLED,&qdev->flags);
2957 pci_disable_msi(qdev->pdev);
2958 }
2959
2960 del_timer_sync(&qdev->adapter_timer);
2961
2962 netif_poll_disable(ndev);
2963
2964 if (do_reset) {
2965 int soft_reset;
2966 unsigned long hw_flags;
2967
2968 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2969 if (ql_wait_for_drvr_lock(qdev)) {
2970 if ((soft_reset = ql_adapter_reset(qdev))) {
2971 printk(KERN_ERR PFX
2972 "%s: ql_adapter_reset(%d) FAILED!\n",
2973 ndev->name, qdev->index);
2974 }
2975 printk(KERN_ERR PFX
2976 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
2977 } else {
2978 printk(KERN_ERR PFX
2979 "%s: Could not acquire driver lock to do "
2980 "reset!\n", ndev->name);
2981 retval = -1;
2982 }
2983 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2984 }
2985 ql_free_mem_resources(qdev);
2986 return retval;
2987}
2988
2989static int ql_adapter_up(struct ql3_adapter *qdev)
2990{
2991 struct net_device *ndev = qdev->ndev;
2992 int err;
2993 unsigned long irq_flags = SA_SAMPLE_RANDOM | SA_SHIRQ;
2994 unsigned long hw_flags;
2995
2996 if (ql_alloc_mem_resources(qdev)) {
2997 printk(KERN_ERR PFX
2998 "%s Unable to allocate buffers.\n", ndev->name);
2999 return -ENOMEM;
3000 }
3001
3002 if (qdev->msi) {
3003 if (pci_enable_msi(qdev->pdev)) {
3004 printk(KERN_ERR PFX
3005 "%s: User requested MSI, but MSI failed to "
3006 "initialize. Continuing without MSI.\n",
3007 qdev->ndev->name);
3008 qdev->msi = 0;
3009 } else {
3010 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3011 set_bit(QL_MSI_ENABLED,&qdev->flags);
3012 irq_flags &= ~SA_SHIRQ;
3013 }
3014 }
3015
3016 if ((err = request_irq(qdev->pdev->irq,
3017 ql3xxx_isr,
3018 irq_flags, ndev->name, ndev))) {
3019 printk(KERN_ERR PFX
3020 "%s: Failed to reserve interrupt %d already in use.\n",
3021 ndev->name, qdev->pdev->irq);
3022 goto err_irq;
3023 }
3024
3025 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3026
3027 if ((err = ql_wait_for_drvr_lock(qdev))) {
3028 if ((err = ql_adapter_initialize(qdev))) {
3029 printk(KERN_ERR PFX
3030 "%s: Unable to initialize adapter.\n",
3031 ndev->name);
3032 goto err_init;
3033 }
3034 printk(KERN_ERR PFX
3035 "%s: Releaseing driver lock.\n",ndev->name);
3036 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3037 } else {
3038 printk(KERN_ERR PFX
3039 "%s: Could not aquire driver lock.\n",
3040 ndev->name);
3041 goto err_lock;
3042 }
3043
3044 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3045
3046 set_bit(QL_ADAPTER_UP,&qdev->flags);
3047
3048 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3049
3050 netif_poll_enable(ndev);
3051 ql_enable_interrupts(qdev);
3052 return 0;
3053
3054err_init:
3055 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3056err_lock:
3057 free_irq(qdev->pdev->irq, ndev);
3058err_irq:
3059 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3060 printk(KERN_INFO PFX
3061 "%s: calling pci_disable_msi().\n",
3062 qdev->ndev->name);
3063 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3064 pci_disable_msi(qdev->pdev);
3065 }
3066 return err;
3067}
3068
3069static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3070{
3071 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3072 printk(KERN_ERR PFX
3073 "%s: Driver up/down cycle failed, "
3074 "closing device\n",qdev->ndev->name);
3075 dev_close(qdev->ndev);
3076 return -1;
3077 }
3078 return 0;
3079}
3080
3081static int ql3xxx_close(struct net_device *ndev)
3082{
3083 struct ql3_adapter *qdev = netdev_priv(ndev);
3084
3085 /*
3086 * Wait for device to recover from a reset.
3087 * (Rarely happens, but possible.)
3088 */
3089 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3090 msleep(50);
3091
3092 ql_adapter_down(qdev,QL_DO_RESET);
3093 return 0;
3094}
3095
3096static int ql3xxx_open(struct net_device *ndev)
3097{
3098 struct ql3_adapter *qdev = netdev_priv(ndev);
3099 return (ql_adapter_up(qdev));
3100}
3101
3102static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3103{
3104 struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3105 return &qdev->stats;
3106}
3107
3108static int ql3xxx_change_mtu(struct net_device *ndev, int new_mtu)
3109{
3110 struct ql3_adapter *qdev = netdev_priv(ndev);
3111 printk(KERN_ERR PFX "%s: new mtu size = %d.\n", ndev->name, new_mtu);
3112 if (new_mtu != NORMAL_MTU_SIZE && new_mtu != JUMBO_MTU_SIZE) {
3113 printk(KERN_ERR PFX
3114 "%s: mtu size of %d is not valid. Use exactly %d or "
3115 "%d.\n", ndev->name, new_mtu, NORMAL_MTU_SIZE,
3116 JUMBO_MTU_SIZE);
3117 return -EINVAL;
3118 }
3119
3120 if (!netif_running(ndev)) {
3121 ndev->mtu = new_mtu;
3122 return 0;
3123 }
3124
3125 ndev->mtu = new_mtu;
3126 return ql_cycle_adapter(qdev,QL_DO_RESET);
3127}
3128
3129static void ql3xxx_set_multicast_list(struct net_device *ndev)
3130{
3131 /*
3132 * We are manually parsing the list in the net_device structure.
3133 */
3134 return;
3135}
3136
3137static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3138{
3139 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3140 struct ql3xxx_port_registers __iomem *port_regs =
3141 qdev->mem_map_registers;
3142 struct sockaddr *addr = p;
3143 unsigned long hw_flags;
3144
3145 if (netif_running(ndev))
3146 return -EBUSY;
3147
3148 if (!is_valid_ether_addr(addr->sa_data))
3149 return -EADDRNOTAVAIL;
3150
3151 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3152
3153 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3154 /* Program lower 32 bits of the MAC address */
3155 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3156 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3157 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3158 ((ndev->dev_addr[2] << 24) | (ndev->
3159 dev_addr[3] << 16) |
3160 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3161
3162 /* Program top 16 bits of the MAC address */
3163 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3164 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3165 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3166 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3167 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3168
3169 return 0;
3170}
3171
3172static void ql3xxx_tx_timeout(struct net_device *ndev)
3173{
3174 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3175
3176 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3177 /*
3178 * Stop the queues, we've got a problem.
3179 */
3180 netif_stop_queue(ndev);
3181
3182 /*
3183 * Wake up the worker to process this event.
3184 */
3185 queue_work(qdev->workqueue, &qdev->tx_timeout_work);
3186}
3187
3188static void ql_reset_work(struct ql3_adapter *qdev)
3189{
3190 struct net_device *ndev = qdev->ndev;
3191 u32 value;
3192 struct ql_tx_buf_cb *tx_cb;
3193 int max_wait_time, i;
3194 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3195 unsigned long hw_flags;
3196
3197 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3198 clear_bit(QL_LINK_MASTER,&qdev->flags);
3199
3200 /*
3201 * Loop through the active list and return the skb.
3202 */
3203 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3204 tx_cb = &qdev->tx_buf[i];
3205 if (tx_cb->skb) {
3206
3207 printk(KERN_DEBUG PFX
3208 "%s: Freeing lost SKB.\n",
3209 qdev->ndev->name);
3210 pci_unmap_single(qdev->pdev,
3211 pci_unmap_addr(tx_cb, mapaddr),
3212 pci_unmap_len(tx_cb, maplen), PCI_DMA_TODEVICE);
3213 dev_kfree_skb(tx_cb->skb);
3214 tx_cb->skb = NULL;
3215 }
3216 }
3217
3218 printk(KERN_ERR PFX
3219 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3220 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3221 ql_write_common_reg(qdev,
3222 &port_regs->CommonRegs.
3223 ispControlStatus,
3224 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3225 /*
3226 * Wait the for Soft Reset to Complete.
3227 */
3228 max_wait_time = 10;
3229 do {
3230 value = ql_read_common_reg(qdev,
3231 &port_regs->CommonRegs.
3232
3233 ispControlStatus);
3234 if ((value & ISP_CONTROL_SR) == 0) {
3235 printk(KERN_DEBUG PFX
3236 "%s: reset completed.\n",
3237 qdev->ndev->name);
3238 break;
3239 }
3240
3241 if (value & ISP_CONTROL_RI) {
3242 printk(KERN_DEBUG PFX
3243 "%s: clearing NRI after reset.\n",
3244 qdev->ndev->name);
3245 ql_write_common_reg(qdev,
3246 (u32 *) &
3247 port_regs->
3248 CommonRegs.
3249 ispControlStatus,
3250 ((ISP_CONTROL_RI <<
3251 16) | ISP_CONTROL_RI));
3252 }
3253
3254 ssleep(1);
3255 } while (--max_wait_time);
3256 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3257
3258 if (value & ISP_CONTROL_SR) {
3259
3260 /*
3261 * Set the reset flags and clear the board again.
3262 * Nothing else to do...
3263 */
3264 printk(KERN_ERR PFX
3265 "%s: Timed out waiting for reset to "
3266 "complete.\n", ndev->name);
3267 printk(KERN_ERR PFX
3268 "%s: Do a reset.\n", ndev->name);
3269 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3270 clear_bit(QL_RESET_START,&qdev->flags);
3271 ql_cycle_adapter(qdev,QL_DO_RESET);
3272 return;
3273 }
3274
3275 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3276 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3277 clear_bit(QL_RESET_START,&qdev->flags);
3278 ql_cycle_adapter(qdev,QL_NO_RESET);
3279 }
3280}
3281
3282static void ql_tx_timeout_work(struct ql3_adapter *qdev)
3283{
3284 ql_cycle_adapter(qdev,QL_DO_RESET);
3285}
3286
3287static void ql_get_board_info(struct ql3_adapter *qdev)
3288{
3289 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3290 u32 value;
3291
3292 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3293
3294 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3295 if (value & PORT_STATUS_64)
3296 qdev->pci_width = 64;
3297 else
3298 qdev->pci_width = 32;
3299 if (value & PORT_STATUS_X)
3300 qdev->pci_x = 1;
3301 else
3302 qdev->pci_x = 0;
3303 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3304}
3305
3306static void ql3xxx_timer(unsigned long ptr)
3307{
3308 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3309
3310 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3311 printk(KERN_DEBUG PFX
3312 "%s: Reset in progress.\n",
3313 qdev->ndev->name);
3314 goto end;
3315 }
3316
3317 ql_link_state_machine(qdev);
3318
3319 /* Restart timer on 2 second interval. */
3320end:
3321 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3322}
3323
3324static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3325 const struct pci_device_id *pci_entry)
3326{
3327 struct net_device *ndev = NULL;
3328 struct ql3_adapter *qdev = NULL;
3329 static int cards_found = 0;
3330 int pci_using_dac, err;
3331
3332 err = pci_enable_device(pdev);
3333 if (err) {
3334 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3335 pci_name(pdev));
3336 goto err_out;
3337 }
3338
3339 err = pci_request_regions(pdev, DRV_NAME);
3340 if (err) {
3341 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3342 pci_name(pdev));
3343 goto err_out_disable_pdev;
3344 }
3345
3346 pci_set_master(pdev);
3347
3348 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3349 pci_using_dac = 1;
3350 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3351 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3352 pci_using_dac = 0;
3353 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3354 }
3355
3356 if (err) {
3357 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3358 pci_name(pdev));
3359 goto err_out_free_regions;
3360 }
3361
3362 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3363 if (!ndev)
3364 goto err_out_free_regions;
3365
3366 SET_MODULE_OWNER(ndev);
3367 SET_NETDEV_DEV(ndev, &pdev->dev);
3368
3369 ndev->features = NETIF_F_LLTX;
3370 if (pci_using_dac)
3371 ndev->features |= NETIF_F_HIGHDMA;
3372
3373 pci_set_drvdata(pdev, ndev);
3374
3375 qdev = netdev_priv(ndev);
3376 qdev->index = cards_found;
3377 qdev->ndev = ndev;
3378 qdev->pdev = pdev;
3379 qdev->port_link_state = LS_DOWN;
3380 if (msi)
3381 qdev->msi = 1;
3382
3383 qdev->msg_enable = netif_msg_init(debug, default_msg);
3384
3385 qdev->mem_map_registers =
3386 ioremap_nocache(pci_resource_start(pdev, 1),
3387 pci_resource_len(qdev->pdev, 1));
3388 if (!qdev->mem_map_registers) {
3389 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3390 pci_name(pdev));
3391 goto err_out_free_ndev;
3392 }
3393
3394 spin_lock_init(&qdev->adapter_lock);
3395 spin_lock_init(&qdev->hw_lock);
3396
3397 /* Set driver entry points */
3398 ndev->open = ql3xxx_open;
3399 ndev->hard_start_xmit = ql3xxx_send;
3400 ndev->stop = ql3xxx_close;
3401 ndev->get_stats = ql3xxx_get_stats;
3402 ndev->change_mtu = ql3xxx_change_mtu;
3403 ndev->set_multicast_list = ql3xxx_set_multicast_list;
3404 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3405 ndev->set_mac_address = ql3xxx_set_mac_address;
3406 ndev->tx_timeout = ql3xxx_tx_timeout;
3407 ndev->watchdog_timeo = 5 * HZ;
3408
3409 ndev->poll = &ql_poll;
3410 ndev->weight = 64;
3411
3412 ndev->irq = pdev->irq;
3413
3414 /* make sure the EEPROM is good */
3415 if (ql_get_nvram_params(qdev)) {
3416 printk(KERN_ALERT PFX
3417 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3418 qdev->index);
3419 goto err_out_iounmap;
3420 }
3421
3422 ql_set_mac_info(qdev);
3423
3424 /* Validate and set parameters */
3425 if (qdev->mac_index) {
3426 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3427 ETH_ALEN);
3428 } else {
3429 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3430 ETH_ALEN);
3431 }
3432 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3433
3434 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3435
3436 /* Turn off support for multicasting */
3437 ndev->flags &= ~IFF_MULTICAST;
3438
3439 /* Record PCI bus information. */
3440 ql_get_board_info(qdev);
3441
3442 /*
3443 * Set the Maximum Memory Read Byte Count value. We do this to handle
3444 * jumbo frames.
3445 */
3446 if (qdev->pci_x) {
3447 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3448 }
3449
3450 err = register_netdev(ndev);
3451 if (err) {
3452 printk(KERN_ERR PFX "%s: cannot register net device\n",
3453 pci_name(pdev));
3454 goto err_out_iounmap;
3455 }
3456
3457 /* we're going to reset, so assume we have no link for now */
3458
3459 netif_carrier_off(ndev);
3460 netif_stop_queue(ndev);
3461
3462 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3463 INIT_WORK(&qdev->reset_work, (void (*)(void *))ql_reset_work, qdev);
3464 INIT_WORK(&qdev->tx_timeout_work,
3465 (void (*)(void *))ql_tx_timeout_work, qdev);
3466
3467 init_timer(&qdev->adapter_timer);
3468 qdev->adapter_timer.function = ql3xxx_timer;
3469 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3470 qdev->adapter_timer.data = (unsigned long)qdev;
3471
3472 if(!cards_found) {
3473 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3474 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3475 DRV_NAME, DRV_VERSION);
3476 }
3477 ql_display_dev_info(ndev);
3478
3479 cards_found++;
3480 return 0;
3481
3482err_out_iounmap:
3483 iounmap(qdev->mem_map_registers);
3484err_out_free_ndev:
3485 free_netdev(ndev);
3486err_out_free_regions:
3487 pci_release_regions(pdev);
3488err_out_disable_pdev:
3489 pci_disable_device(pdev);
3490 pci_set_drvdata(pdev, NULL);
3491err_out:
3492 return err;
3493}
3494
3495static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3496{
3497 struct net_device *ndev = pci_get_drvdata(pdev);
3498 struct ql3_adapter *qdev = netdev_priv(ndev);
3499
3500 unregister_netdev(ndev);
3501 qdev = netdev_priv(ndev);
3502
3503 ql_disable_interrupts(qdev);
3504
3505 if (qdev->workqueue) {
3506 cancel_delayed_work(&qdev->reset_work);
3507 cancel_delayed_work(&qdev->tx_timeout_work);
3508 destroy_workqueue(qdev->workqueue);
3509 qdev->workqueue = NULL;
3510 }
3511
3512 iounmap((void *)qdev->mmap_virt_base);
3513 pci_release_regions(pdev);
3514 pci_set_drvdata(pdev, NULL);
3515 free_netdev(ndev);
3516}
3517
3518static struct pci_driver ql3xxx_driver = {
3519
3520 .name = DRV_NAME,
3521 .id_table = ql3xxx_pci_tbl,
3522 .probe = ql3xxx_probe,
3523 .remove = __devexit_p(ql3xxx_remove),
3524};
3525
3526static int __init ql3xxx_init_module(void)
3527{
3528 return pci_register_driver(&ql3xxx_driver);
3529}
3530
3531static void __exit ql3xxx_exit(void)
3532{
3533 pci_unregister_driver(&ql3xxx_driver);
3534}
3535
3536module_init(ql3xxx_init_module);
3537module_exit(ql3xxx_exit);
diff --git a/drivers/net/qla3xxx.h b/drivers/net/qla3xxx.h
new file mode 100644
index 000000000000..9492cee6b083
--- /dev/null
+++ b/drivers/net/qla3xxx.h
@@ -0,0 +1,1194 @@
1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7#ifndef _QLA3XXX_H_
8#define _QLA3XXX_H_
9
10/*
11 * IOCB Definitions...
12 */
13#pragma pack(1)
14
15#define OPCODE_OB_MAC_IOCB_FN0 0x01
16#define OPCODE_OB_MAC_IOCB_FN2 0x21
17#define OPCODE_OB_TCP_IOCB_FN0 0x03
18#define OPCODE_OB_TCP_IOCB_FN2 0x23
19#define OPCODE_UPDATE_NCB_IOCB_FN0 0x00
20#define OPCODE_UPDATE_NCB_IOCB_FN2 0x20
21
22#define OPCODE_UPDATE_NCB_IOCB 0xF0
23#define OPCODE_IB_MAC_IOCB 0xF9
24#define OPCODE_IB_IP_IOCB 0xFA
25#define OPCODE_IB_TCP_IOCB 0xFB
26#define OPCODE_DUMP_PROTO_IOCB 0xFE
27#define OPCODE_BUFFER_ALERT_IOCB 0xFB
28
29#define OPCODE_FUNC_ID_MASK 0x30
30#define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
31#define OUTBOUND_TCP_IOCB 0x03 /* plus function bits */
32#define UPDATE_NCB_IOCB 0x00 /* plus function bits */
33
34#define FN0_MA_BITS_MASK 0x00
35#define FN1_MA_BITS_MASK 0x80
36
37struct ob_mac_iocb_req {
38 u8 opcode;
39 u8 flags;
40#define OB_MAC_IOCB_REQ_MA 0xC0
41#define OB_MAC_IOCB_REQ_F 0x20
42#define OB_MAC_IOCB_REQ_X 0x10
43#define OB_MAC_IOCB_REQ_D 0x02
44#define OB_MAC_IOCB_REQ_I 0x01
45 __le16 reserved0;
46
47 __le32 transaction_id;
48 __le16 data_len;
49 __le16 reserved1;
50 __le32 reserved2;
51 __le32 reserved3;
52 __le32 buf_addr0_low;
53 __le32 buf_addr0_high;
54 __le32 buf_0_len;
55 __le32 buf_addr1_low;
56 __le32 buf_addr1_high;
57 __le32 buf_1_len;
58 __le32 buf_addr2_low;
59 __le32 buf_addr2_high;
60 __le32 buf_2_len;
61 __le32 reserved4;
62 __le32 reserved5;
63};
64/*
65 * The following constants define control bits for buffer
66 * length fields for all IOCB's.
67 */
68#define OB_MAC_IOCB_REQ_E 0x80000000 /* Last valid buffer in list. */
69#define OB_MAC_IOCB_REQ_C 0x40000000 /* points to an OAL. (continuation) */
70#define OB_MAC_IOCB_REQ_L 0x20000000 /* Auburn local address pointer. */
71#define OB_MAC_IOCB_REQ_R 0x10000000 /* 32-bit address pointer. */
72
73struct ob_mac_iocb_rsp {
74 u8 opcode;
75 u8 flags;
76#define OB_MAC_IOCB_RSP_P 0x08
77#define OB_MAC_IOCB_RSP_S 0x02
78#define OB_MAC_IOCB_RSP_I 0x01
79
80 __le16 reserved0;
81 __le32 transaction_id;
82 __le32 reserved1;
83 __le32 reserved2;
84};
85
86struct ib_mac_iocb_rsp {
87 u8 opcode;
88 u8 flags;
89#define IB_MAC_IOCB_RSP_S 0x80
90#define IB_MAC_IOCB_RSP_H1 0x40
91#define IB_MAC_IOCB_RSP_H0 0x20
92#define IB_MAC_IOCB_RSP_B 0x10
93#define IB_MAC_IOCB_RSP_M 0x08
94#define IB_MAC_IOCB_RSP_MA 0x07
95
96 __le16 length;
97 __le32 reserved;
98 __le32 ial_low;
99 __le32 ial_high;
100
101};
102
103struct ob_ip_iocb_req {
104 u8 opcode;
105 __le16 flags;
106#define OB_IP_IOCB_REQ_O 0x100
107#define OB_IP_IOCB_REQ_H 0x008
108#define OB_IP_IOCB_REQ_U 0x004
109#define OB_IP_IOCB_REQ_D 0x002
110#define OB_IP_IOCB_REQ_I 0x001
111
112 u8 reserved0;
113
114 __le32 transaction_id;
115 __le16 data_len;
116 __le16 reserved1;
117 __le32 hncb_ptr_low;
118 __le32 hncb_ptr_high;
119 __le32 buf_addr0_low;
120 __le32 buf_addr0_high;
121 __le32 buf_0_len;
122 __le32 buf_addr1_low;
123 __le32 buf_addr1_high;
124 __le32 buf_1_len;
125 __le32 buf_addr2_low;
126 __le32 buf_addr2_high;
127 __le32 buf_2_len;
128 __le32 reserved2;
129 __le32 reserved3;
130};
131
132/* defines for BufferLength fields above */
133#define OB_IP_IOCB_REQ_E 0x80000000
134#define OB_IP_IOCB_REQ_C 0x40000000
135#define OB_IP_IOCB_REQ_L 0x20000000
136#define OB_IP_IOCB_REQ_R 0x10000000
137
138struct ob_ip_iocb_rsp {
139 u8 opcode;
140 u8 flags;
141#define OB_MAC_IOCB_RSP_E 0x08
142#define OB_MAC_IOCB_RSP_L 0x04
143#define OB_MAC_IOCB_RSP_S 0x02
144#define OB_MAC_IOCB_RSP_I 0x01
145
146 __le16 reserved0;
147 __le32 transaction_id;
148 __le32 reserved1;
149 __le32 reserved2;
150};
151
152struct ob_tcp_iocb_req {
153 u8 opcode;
154
155 u8 flags0;
156#define OB_TCP_IOCB_REQ_P 0x80
157#define OB_TCP_IOCB_REQ_CI 0x20
158#define OB_TCP_IOCB_REQ_H 0x10
159#define OB_TCP_IOCB_REQ_LN 0x08
160#define OB_TCP_IOCB_REQ_K 0x04
161#define OB_TCP_IOCB_REQ_D 0x02
162#define OB_TCP_IOCB_REQ_I 0x01
163
164 u8 flags1;
165#define OB_TCP_IOCB_REQ_OSM 0x40
166#define OB_TCP_IOCB_REQ_URG 0x20
167#define OB_TCP_IOCB_REQ_ACK 0x10
168#define OB_TCP_IOCB_REQ_PSH 0x08
169#define OB_TCP_IOCB_REQ_RST 0x04
170#define OB_TCP_IOCB_REQ_SYN 0x02
171#define OB_TCP_IOCB_REQ_FIN 0x01
172
173 u8 options_len;
174#define OB_TCP_IOCB_REQ_OMASK 0xF0
175#define OB_TCP_IOCB_REQ_SHIFT 4
176
177 __le32 transaction_id;
178 __le32 data_len;
179 __le32 hncb_ptr_low;
180 __le32 hncb_ptr_high;
181 __le32 buf_addr0_low;
182 __le32 buf_addr0_high;
183 __le32 buf_0_len;
184 __le32 buf_addr1_low;
185 __le32 buf_addr1_high;
186 __le32 buf_1_len;
187 __le32 buf_addr2_low;
188 __le32 buf_addr2_high;
189 __le32 buf_2_len;
190 __le32 time_stamp;
191 __le32 reserved1;
192};
193
194struct ob_tcp_iocb_rsp {
195 u8 opcode;
196
197 u8 flags0;
198#define OB_TCP_IOCB_RSP_C 0x20
199#define OB_TCP_IOCB_RSP_H 0x10
200#define OB_TCP_IOCB_RSP_LN 0x08
201#define OB_TCP_IOCB_RSP_K 0x04
202#define OB_TCP_IOCB_RSP_D 0x02
203#define OB_TCP_IOCB_RSP_I 0x01
204
205 u8 flags1;
206#define OB_TCP_IOCB_RSP_E 0x10
207#define OB_TCP_IOCB_RSP_W 0x08
208#define OB_TCP_IOCB_RSP_P 0x04
209#define OB_TCP_IOCB_RSP_T 0x02
210#define OB_TCP_IOCB_RSP_F 0x01
211
212 u8 state;
213#define OB_TCP_IOCB_RSP_SMASK 0xF0
214#define OB_TCP_IOCB_RSP_SHIFT 4
215
216 __le32 transaction_id;
217 __le32 local_ncb_ptr;
218 __le32 reserved0;
219};
220
221struct ib_ip_iocb_rsp {
222 u8 opcode;
223 u8 flags;
224#define IB_IP_IOCB_RSP_S 0x80
225#define IB_IP_IOCB_RSP_H1 0x40
226#define IB_IP_IOCB_RSP_H0 0x20
227#define IB_IP_IOCB_RSP_B 0x10
228#define IB_IP_IOCB_RSP_M 0x08
229#define IB_IP_IOCB_RSP_MA 0x07
230
231 __le16 length;
232 __le16 checksum;
233 __le16 reserved;
234#define IB_IP_IOCB_RSP_R 0x01
235 __le32 ial_low;
236 __le32 ial_high;
237};
238
239struct ib_tcp_iocb_rsp {
240 u8 opcode;
241 u8 flags;
242#define IB_TCP_IOCB_RSP_P 0x80
243#define IB_TCP_IOCB_RSP_T 0x40
244#define IB_TCP_IOCB_RSP_D 0x20
245#define IB_TCP_IOCB_RSP_N 0x10
246#define IB_TCP_IOCB_RSP_IP 0x03
247#define IB_TCP_FLAG_MASK 0xf0
248#define IB_TCP_FLAG_IOCB_SYN 0x00
249
250#define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)
251
252 __le16 length;
253 __le32 hncb_ref_num;
254 __le32 ial_low;
255 __le32 ial_high;
256};
257
258struct net_rsp_iocb {
259 u8 opcode;
260 u8 flags;
261 __le16 reserved0;
262 __le32 reserved[3];
263};
264#pragma pack()
265
266/*
267 * Register Definitions...
268 */
269#define PORT0_PHY_ADDRESS 0x1e00
270#define PORT1_PHY_ADDRESS 0x1f00
271
272#define ETHERNET_CRC_SIZE 4
273
274#define MII_SCAN_REGISTER 0x00000001
275
276/* 32-bit ispControlStatus */
277enum {
278 ISP_CONTROL_NP_MASK = 0x0003,
279 ISP_CONTROL_NP_PCSR = 0x0000,
280 ISP_CONTROL_NP_HMCR = 0x0001,
281 ISP_CONTROL_NP_LRAMCR = 0x0002,
282 ISP_CONTROL_NP_PSR = 0x0003,
283 ISP_CONTROL_RI = 0x0008,
284 ISP_CONTROL_CI = 0x0010,
285 ISP_CONTROL_PI = 0x0020,
286 ISP_CONTROL_IN = 0x0040,
287 ISP_CONTROL_BE = 0x0080,
288 ISP_CONTROL_FN_MASK = 0x0700,
289 ISP_CONTROL_FN0_NET = 0x0400,
290 ISP_CONTROL_FN0_SCSI = 0x0500,
291 ISP_CONTROL_FN1_NET = 0x0600,
292 ISP_CONTROL_FN1_SCSI = 0x0700,
293 ISP_CONTROL_LINK_DN_0 = 0x0800,
294 ISP_CONTROL_LINK_DN_1 = 0x1000,
295 ISP_CONTROL_FSR = 0x2000,
296 ISP_CONTROL_FE = 0x4000,
297 ISP_CONTROL_SR = 0x8000,
298};
299
300/* 32-bit ispInterruptMaskReg */
301enum {
302 ISP_IMR_ENABLE_INT = 0x0004,
303 ISP_IMR_DISABLE_RESET_INT = 0x0008,
304 ISP_IMR_DISABLE_CMPL_INT = 0x0010,
305 ISP_IMR_DISABLE_PROC_INT = 0x0020,
306};
307
308/* 32-bit serialPortInterfaceReg */
309enum {
310 ISP_SERIAL_PORT_IF_CLK = 0x0001,
311 ISP_SERIAL_PORT_IF_CS = 0x0002,
312 ISP_SERIAL_PORT_IF_D0 = 0x0004,
313 ISP_SERIAL_PORT_IF_DI = 0x0008,
314 ISP_NVRAM_MASK = (0x000F << 16),
315 ISP_SERIAL_PORT_IF_WE = 0x0010,
316 ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
317 ISP_SERIAL_PORT_IF_SCI = 0x0400,
318 ISP_SERIAL_PORT_IF_SC0 = 0x0800,
319 ISP_SERIAL_PORT_IF_SCE = 0x1000,
320 ISP_SERIAL_PORT_IF_SDI = 0x2000,
321 ISP_SERIAL_PORT_IF_SDO = 0x4000,
322 ISP_SERIAL_PORT_IF_SDE = 0x8000,
323 ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
324};
325
326/* semaphoreReg */
327enum {
328 QL_RESOURCE_MASK_BASE_CODE = 0x7,
329 QL_RESOURCE_BITS_BASE_CODE = 0x4,
330 QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
331 QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
332 QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
333 QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
334 QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
335 QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
336 QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
337 QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
338 QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
339 QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
340};
341
342 /*
343 * QL3XXX memory-mapped registers
344 * QL3XXX has 4 "pages" of registers, each page occupying
345 * 256 bytes. Each page has a "common" area at the start and then
346 * page-specific registers after that.
347 */
348struct ql3xxx_common_registers {
349 u32 MB0; /* Offset 0x00 */
350 u32 MB1; /* Offset 0x04 */
351 u32 MB2; /* Offset 0x08 */
352 u32 MB3; /* Offset 0x0c */
353 u32 MB4; /* Offset 0x10 */
354 u32 MB5; /* Offset 0x14 */
355 u32 MB6; /* Offset 0x18 */
356 u32 MB7; /* Offset 0x1c */
357 u32 flashBiosAddr;
358 u32 flashBiosData;
359 u32 ispControlStatus;
360 u32 ispInterruptMaskReg;
361 u32 serialPortInterfaceReg;
362 u32 semaphoreReg;
363 u32 reqQProducerIndex;
364 u32 rspQConsumerIndex;
365
366 u32 rxLargeQProducerIndex;
367 u32 rxSmallQProducerIndex;
368 u32 arcMadiCommand;
369 u32 arcMadiData;
370};
371
372enum {
373 EXT_HW_CONFIG_SP_MASK = 0x0006,
374 EXT_HW_CONFIG_SP_NONE = 0x0000,
375 EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
376 EXT_HW_CONFIG_SP_ECC = 0x0004,
377 EXT_HW_CONFIG_SP_ECCx = 0x0006,
378 EXT_HW_CONFIG_SIZE_MASK = 0x0060,
379 EXT_HW_CONFIG_SIZE_128M = 0x0000,
380 EXT_HW_CONFIG_SIZE_256M = 0x0020,
381 EXT_HW_CONFIG_SIZE_512M = 0x0040,
382 EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
383 EXT_HW_CONFIG_PD = 0x0080,
384 EXT_HW_CONFIG_FW = 0x0200,
385 EXT_HW_CONFIG_US = 0x0400,
386 EXT_HW_CONFIG_DCS_MASK = 0x1800,
387 EXT_HW_CONFIG_DCS_9MA = 0x0000,
388 EXT_HW_CONFIG_DCS_15MA = 0x0800,
389 EXT_HW_CONFIG_DCS_18MA = 0x1000,
390 EXT_HW_CONFIG_DCS_24MA = 0x1800,
391 EXT_HW_CONFIG_DDS_MASK = 0x6000,
392 EXT_HW_CONFIG_DDS_9MA = 0x0000,
393 EXT_HW_CONFIG_DDS_15MA = 0x2000,
394 EXT_HW_CONFIG_DDS_18MA = 0x4000,
395 EXT_HW_CONFIG_DDS_24MA = 0x6000,
396};
397
398/* InternalChipConfig */
399enum {
400 INTERNAL_CHIP_DM = 0x0001,
401 INTERNAL_CHIP_SD = 0x0002,
402 INTERNAL_CHIP_RAP_MASK = 0x000C,
403 INTERNAL_CHIP_RAP_RR = 0x0000,
404 INTERNAL_CHIP_RAP_NRM = 0x0004,
405 INTERNAL_CHIP_RAP_ERM = 0x0008,
406 INTERNAL_CHIP_RAP_ERMx = 0x000C,
407 INTERNAL_CHIP_WE = 0x0010,
408 INTERNAL_CHIP_EF = 0x0020,
409 INTERNAL_CHIP_FR = 0x0040,
410 INTERNAL_CHIP_FW = 0x0080,
411 INTERNAL_CHIP_FI = 0x0100,
412 INTERNAL_CHIP_FT = 0x0200,
413};
414
415/* portControl */
416enum {
417 PORT_CONTROL_DS = 0x0001,
418 PORT_CONTROL_HH = 0x0002,
419 PORT_CONTROL_EI = 0x0004,
420 PORT_CONTROL_ET = 0x0008,
421 PORT_CONTROL_EF = 0x0010,
422 PORT_CONTROL_DRM = 0x0020,
423 PORT_CONTROL_RLB = 0x0040,
424 PORT_CONTROL_RCB = 0x0080,
425 PORT_CONTROL_MAC = 0x0100,
426 PORT_CONTROL_IPV = 0x0200,
427 PORT_CONTROL_IFP = 0x0400,
428 PORT_CONTROL_ITP = 0x0800,
429 PORT_CONTROL_FI = 0x1000,
430 PORT_CONTROL_DFP = 0x2000,
431 PORT_CONTROL_OI = 0x4000,
432 PORT_CONTROL_CC = 0x8000,
433};
434
435/* portStatus */
436enum {
437 PORT_STATUS_SM0 = 0x0001,
438 PORT_STATUS_SM1 = 0x0002,
439 PORT_STATUS_X = 0x0008,
440 PORT_STATUS_DL = 0x0080,
441 PORT_STATUS_IC = 0x0200,
442 PORT_STATUS_MRC = 0x0400,
443 PORT_STATUS_NL = 0x0800,
444 PORT_STATUS_REV_ID_MASK = 0x7000,
445 PORT_STATUS_REV_ID_1 = 0x1000,
446 PORT_STATUS_REV_ID_2 = 0x2000,
447 PORT_STATUS_REV_ID_3 = 0x3000,
448 PORT_STATUS_64 = 0x8000,
449 PORT_STATUS_UP0 = 0x10000,
450 PORT_STATUS_AC0 = 0x20000,
451 PORT_STATUS_AE0 = 0x40000,
452 PORT_STATUS_UP1 = 0x100000,
453 PORT_STATUS_AC1 = 0x200000,
454 PORT_STATUS_AE1 = 0x400000,
455 PORT_STATUS_F0_ENABLED = 0x1000000,
456 PORT_STATUS_F1_ENABLED = 0x2000000,
457 PORT_STATUS_F2_ENABLED = 0x4000000,
458 PORT_STATUS_F3_ENABLED = 0x8000000,
459};
460
461/* macMIIMgmtControlReg */
462enum {
463 MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
464 MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
465 MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
466 MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
467 MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
468 MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
469 MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
470 MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
471 MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
472 MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
473};
474
475/* macMIIMgmtControlReg */
476enum {
477 MAC_MII_CONTROL_RC = 0x0001,
478 MAC_MII_CONTROL_SC = 0x0002,
479 MAC_MII_CONTROL_AS = 0x0004,
480 MAC_MII_CONTROL_NP = 0x0008,
481 MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
482 MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
483 MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
484 MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
485 MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
486 MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
487 MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
488 MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
489 MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
490 MAC_MII_CONTROL_RM = 0x8000,
491};
492
493/* macMIIStatusReg */
494enum {
495 MAC_MII_STATUS_BSY = 0x0001,
496 MAC_MII_STATUS_SC = 0x0002,
497 MAC_MII_STATUS_NV = 0x0004,
498};
499
500enum {
501 MAC_CONFIG_REG_PE = 0x0001,
502 MAC_CONFIG_REG_TF = 0x0002,
503 MAC_CONFIG_REG_RF = 0x0004,
504 MAC_CONFIG_REG_FD = 0x0008,
505 MAC_CONFIG_REG_GM = 0x0010,
506 MAC_CONFIG_REG_LB = 0x0020,
507 MAC_CONFIG_REG_SR = 0x8000,
508};
509
510enum {
511 MAC_HALF_DUPLEX_REG_ED = 0x10000,
512 MAC_HALF_DUPLEX_REG_NB = 0x20000,
513 MAC_HALF_DUPLEX_REG_BNB = 0x40000,
514 MAC_HALF_DUPLEX_REG_ALT = 0x80000,
515};
516
517enum {
518 IP_ADDR_INDEX_REG_MASK = 0x000f,
519 IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
520 IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
521 IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
522 IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
523 IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
524 IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
525 IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
526 IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
527};
528
529enum {
530 PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
531 PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
532 PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
533 PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
534 PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
535 PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
536 PROBE_MUX_ADDR_REG_UP = 0x4000,
537 PROBE_MUX_ADDR_REG_RE = 0x8000,
538};
539
540enum {
541 STATISTICS_INDEX_REG_MASK = 0x01ff,
542 STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
543 STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
544 STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
545 STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
546 STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
547 STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
548 STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
549 STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
550 STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
551 STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
552 STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
553 STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
554 STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
555 STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
556 STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
557 STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
558 STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
559 STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
560 STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
561 STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
562 STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
563 STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
564 STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
565 STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
566 STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
567 STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
568 STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
569 STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
570 STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
571 STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
572 STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
573 STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
574 STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
575 STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
576 STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
577 STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
578 STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
579 STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
580 STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
581 STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
582 STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
583 STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
584 STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
585 STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
586 STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
587 STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
588 STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
589 STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
590 STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
591 STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
592 STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
593 STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
594};
595
596enum {
597 PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
598 PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
599 PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
600 PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
601 PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
602 PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
603 PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
604 PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
605 PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
606 PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
607 PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
608 PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
609 PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
610 PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
611 PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
612 PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
613 PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
614 PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
615 PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
616 PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
617 PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
618 PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
619 PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
620 PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
621 PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
622};
623
624/*
625 * port control and status page - page 0
626 */
627
628struct ql3xxx_port_registers {
629 struct ql3xxx_common_registers CommonRegs;
630
631 u32 ExternalHWConfig;
632 u32 InternalChipConfig;
633 u32 portControl;
634 u32 portStatus;
635 u32 macAddrIndirectPtrReg;
636 u32 macAddrDataReg;
637 u32 macMIIMgmtControlReg;
638 u32 macMIIMgmtAddrReg;
639 u32 macMIIMgmtDataReg;
640 u32 macMIIStatusReg;
641 u32 mac0ConfigReg;
642 u32 mac0IpgIfgReg;
643 u32 mac0HalfDuplexReg;
644 u32 mac0MaxFrameLengthReg;
645 u32 mac0PauseThresholdReg;
646 u32 mac1ConfigReg;
647 u32 mac1IpgIfgReg;
648 u32 mac1HalfDuplexReg;
649 u32 mac1MaxFrameLengthReg;
650 u32 mac1PauseThresholdReg;
651 u32 ipAddrIndexReg;
652 u32 ipAddrDataReg;
653 u32 ipReassemblyTimeout;
654 u32 tcpMaxWindow;
655 u32 currentTcpTimestamp[2];
656 u32 internalRamRWAddrReg;
657 u32 internalRamWDataReg;
658 u32 reclaimedBufferAddrRegLow;
659 u32 reclaimedBufferAddrRegHigh;
660 u32 reserved[2];
661 u32 fpgaRevID;
662 u32 localRamAddr;
663 u32 localRamDataAutoIncr;
664 u32 localRamDataNonIncr;
665 u32 gpOutput;
666 u32 gpInput;
667 u32 probeMuxAddr;
668 u32 probeMuxData;
669 u32 statisticsIndexReg;
670 u32 statisticsReadDataRegAutoIncr;
671 u32 statisticsReadDataRegNoIncr;
672 u32 PortFatalErrStatus;
673};
674
675/*
676 * port host memory config page - page 1
677 */
678struct ql3xxx_host_memory_registers {
679 struct ql3xxx_common_registers CommonRegs;
680
681 u32 reserved[12];
682
683 /* Network Request Queue */
684 u32 reqConsumerIndex;
685 u32 reqConsumerIndexAddrLow;
686 u32 reqConsumerIndexAddrHigh;
687 u32 reqBaseAddrLow;
688 u32 reqBaseAddrHigh;
689 u32 reqLength;
690
691 /* Network Completion Queue */
692 u32 rspProducerIndex;
693 u32 rspProducerIndexAddrLow;
694 u32 rspProducerIndexAddrHigh;
695 u32 rspBaseAddrLow;
696 u32 rspBaseAddrHigh;
697 u32 rspLength;
698
699 /* RX Large Buffer Queue */
700 u32 rxLargeQConsumerIndex;
701 u32 rxLargeQBaseAddrLow;
702 u32 rxLargeQBaseAddrHigh;
703 u32 rxLargeQLength;
704 u32 rxLargeBufferLength;
705
706 /* RX Small Buffer Queue */
707 u32 rxSmallQConsumerIndex;
708 u32 rxSmallQBaseAddrLow;
709 u32 rxSmallQBaseAddrHigh;
710 u32 rxSmallQLength;
711 u32 rxSmallBufferLength;
712
713};
714
715/*
716 * port local RAM page - page 2
717 */
718struct ql3xxx_local_ram_registers {
719 struct ql3xxx_common_registers CommonRegs;
720 u32 bufletSize;
721 u32 maxBufletCount;
722 u32 currentBufletCount;
723 u32 reserved;
724 u32 freeBufletThresholdLow;
725 u32 freeBufletThresholdHigh;
726 u32 ipHashTableBase;
727 u32 ipHashTableCount;
728 u32 tcpHashTableBase;
729 u32 tcpHashTableCount;
730 u32 ncbBase;
731 u32 maxNcbCount;
732 u32 currentNcbCount;
733 u32 drbBase;
734 u32 maxDrbCount;
735 u32 currentDrbCount;
736};
737
738/*
739 * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
740 */
741
742#define LS_64BITS(x) (u32)(0xffffffff & ((u64)x))
743#define MS_64BITS(x) (u32)(0xffffffff & (((u64)x)>>16>>16) )
744
745/*
746 * I/O register
747 */
748
749enum {
750 CONTROL_REG = 0,
751 STATUS_REG = 1,
752 PHY_STAT_LINK_UP = 0x0004,
753 PHY_CTRL_LOOPBACK = 0x4000,
754
755 PETBI_CONTROL_REG = 0x00,
756 PETBI_CTRL_SOFT_RESET = 0x8000,
757 PETBI_CTRL_AUTO_NEG = 0x1000,
758 PETBI_CTRL_RESTART_NEG = 0x0200,
759 PETBI_CTRL_FULL_DUPLEX = 0x0100,
760 PETBI_CTRL_SPEED_1000 = 0x0040,
761
762 PETBI_STATUS_REG = 0x01,
763 PETBI_STAT_NEG_DONE = 0x0020,
764 PETBI_STAT_LINK_UP = 0x0004,
765
766 PETBI_NEG_ADVER = 0x04,
767 PETBI_NEG_PAUSE = 0x0080,
768 PETBI_NEG_PAUSE_MASK = 0x0180,
769 PETBI_NEG_DUPLEX = 0x0020,
770 PETBI_NEG_DUPLEX_MASK = 0x0060,
771
772 PETBI_NEG_PARTNER = 0x05,
773 PETBI_NEG_ERROR_MASK = 0x3000,
774
775 PETBI_EXPANSION_REG = 0x06,
776 PETBI_EXP_PAGE_RX = 0x0002,
777
778 PETBI_TBI_CTRL = 0x11,
779 PETBI_TBI_RESET = 0x8000,
780 PETBI_TBI_AUTO_SENSE = 0x0100,
781 PETBI_TBI_SERDES_MODE = 0x0010,
782 PETBI_TBI_SERDES_WRAP = 0x0002,
783
784 AUX_CONTROL_STATUS = 0x1c,
785 PHY_AUX_NEG_DONE = 0x8000,
786 PHY_NEG_PARTNER = 5,
787 PHY_AUX_DUPLEX_STAT = 0x0020,
788 PHY_AUX_SPEED_STAT = 0x0018,
789 PHY_AUX_NO_HW_STRAP = 0x0004,
790 PHY_AUX_RESET_STICK = 0x0002,
791 PHY_NEG_PAUSE = 0x0400,
792 PHY_CTRL_SOFT_RESET = 0x8000,
793 PHY_NEG_ADVER = 4,
794 PHY_NEG_ADV_SPEED = 0x01e0,
795 PHY_CTRL_RESTART_NEG = 0x0200,
796};
797enum {
798/* AM29LV Flash definitions */
799 FM93C56A_START = 0x1,
800/* Commands */
801 FM93C56A_READ = 0x2,
802 FM93C56A_WEN = 0x0,
803 FM93C56A_WRITE = 0x1,
804 FM93C56A_WRITE_ALL = 0x0,
805 FM93C56A_WDS = 0x0,
806 FM93C56A_ERASE = 0x3,
807 FM93C56A_ERASE_ALL = 0x0,
808/* Command Extentions */
809 FM93C56A_WEN_EXT = 0x3,
810 FM93C56A_WRITE_ALL_EXT = 0x1,
811 FM93C56A_WDS_EXT = 0x0,
812 FM93C56A_ERASE_ALL_EXT = 0x2,
813/* Special Bits */
814 FM93C56A_READ_DUMMY_BITS = 1,
815 FM93C56A_READY = 0,
816 FM93C56A_BUSY = 1,
817 FM93C56A_CMD_BITS = 2,
818/* AM29LV Flash definitions */
819 FM93C56A_SIZE_8 = 0x100,
820 FM93C56A_SIZE_16 = 0x80,
821 FM93C66A_SIZE_8 = 0x200,
822 FM93C66A_SIZE_16 = 0x100,
823 FM93C86A_SIZE_16 = 0x400,
824/* Address Bits */
825 FM93C56A_NO_ADDR_BITS_16 = 8,
826 FM93C56A_NO_ADDR_BITS_8 = 9,
827 FM93C86A_NO_ADDR_BITS_16 = 10,
828/* Data Bits */
829 FM93C56A_DATA_BITS_16 = 16,
830 FM93C56A_DATA_BITS_8 = 8,
831};
832enum {
833/* Auburn Bits */
834 AUBURN_EEPROM_DI = 0x8,
835 AUBURN_EEPROM_DI_0 = 0x0,
836 AUBURN_EEPROM_DI_1 = 0x8,
837 AUBURN_EEPROM_DO = 0x4,
838 AUBURN_EEPROM_DO_0 = 0x0,
839 AUBURN_EEPROM_DO_1 = 0x4,
840 AUBURN_EEPROM_CS = 0x2,
841 AUBURN_EEPROM_CS_0 = 0x0,
842 AUBURN_EEPROM_CS_1 = 0x2,
843 AUBURN_EEPROM_CLK_RISE = 0x1,
844 AUBURN_EEPROM_CLK_FALL = 0x0,
845};
846enum {EEPROM_SIZE = FM93C86A_SIZE_16,
847 EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
848 EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
849};
850
851/*
852 * MAC Config data structure
853 */
854 struct eeprom_port_cfg {
855 u16 etherMtu_mac;
856 u16 pauseThreshold_mac;
857 u16 resumeThreshold_mac;
858 u16 portConfiguration;
859#define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000
860#define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000
861#define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000
862#define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000
863#define PORT_CONFIG_1000MB_SPEED 0x0400
864#define PORT_CONFIG_100MB_SPEED 0x0200
865#define PORT_CONFIG_10MB_SPEED 0x0100
866#define PORT_CONFIG_LINK_SPEED_MASK 0x0F00
867 u16 reserved[12];
868
869};
870
871/*
872 * BIOS data structure
873 */
874struct eeprom_bios_cfg {
875 u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
876
877 u8 bootID0:7, boodID0Valid:1;
878 u8 bootLun0[8];
879
880 u8 bootID1:7, boodID1Valid:1;
881 u8 bootLun1[8];
882
883 u16 MaxLunsTrgt;
884 u8 reserved[10];
885};
886
887/*
888 * Function Specific Data structure
889 */
890struct eeprom_function_cfg {
891 u8 reserved[30];
892 u8 macAddress[6];
893 u8 macAddressSecondary[6];
894
895 u16 subsysVendorId;
896 u16 subsysDeviceId;
897};
898
899/*
900 * EEPROM format
901 */
902struct eeprom_data {
903 u8 asicId[4];
904 u8 version;
905 u8 numPorts;
906 u16 boardId;
907
908#define EEPROM_BOARDID_STR_SIZE 16
909#define EEPROM_SERIAL_NUM_SIZE 16
910
911 u8 boardIdStr[16];
912 u8 serialNumber[16];
913 u16 extHwConfig;
914 struct eeprom_port_cfg macCfg_port0;
915 struct eeprom_port_cfg macCfg_port1;
916 u16 bufletSize;
917 u16 bufletCount;
918 u16 tcpWindowThreshold50;
919 u16 tcpWindowThreshold25;
920 u16 tcpWindowThreshold0;
921 u16 ipHashTableBaseHi;
922 u16 ipHashTableBaseLo;
923 u16 ipHashTableSize;
924 u16 tcpHashTableBaseHi;
925 u16 tcpHashTableBaseLo;
926 u16 tcpHashTableSize;
927 u16 ncbTableBaseHi;
928 u16 ncbTableBaseLo;
929 u16 ncbTableSize;
930 u16 drbTableBaseHi;
931 u16 drbTableBaseLo;
932 u16 drbTableSize;
933 u16 reserved_142[4];
934 u16 ipReassemblyTimeout;
935 u16 tcpMaxWindowSize;
936 u16 ipSecurity;
937#define IPSEC_CONFIG_PRESENT 0x0001
938 u8 reserved_156[294];
939 u16 qDebug[8];
940 struct eeprom_function_cfg funcCfg_fn0;
941 u16 reserved_510;
942 u8 oemSpace[432];
943 struct eeprom_bios_cfg biosCfg_fn1;
944 struct eeprom_function_cfg funcCfg_fn1;
945 u16 reserved_1022;
946 u8 reserved_1024[464];
947 struct eeprom_function_cfg funcCfg_fn2;
948 u16 reserved_1534;
949 u8 reserved_1536[432];
950 struct eeprom_bios_cfg biosCfg_fn3;
951 struct eeprom_function_cfg funcCfg_fn3;
952 u16 checksum;
953};
954
955/*
956 * General definitions...
957 */
958
959/*
960 * Below are a number compiler switches for controlling driver behavior.
961 * Some are not supported under certain conditions and are notated as such.
962 */
963
964#define QL3XXX_VENDOR_ID 0x1077
965#define QL3022_DEVICE_ID 0x3022
966
967/* MTU & Frame Size stuff */
968#define NORMAL_MTU_SIZE ETH_DATA_LEN
969#define JUMBO_MTU_SIZE 9000
970#define VLAN_ID_LEN 2
971
972/* Request Queue Related Definitions */
973#define NUM_REQ_Q_ENTRIES 256 /* so that 64 * 64 = 4096 (1 page) */
974
975/* Response Queue Related Definitions */
976#define NUM_RSP_Q_ENTRIES 256 /* so that 256 * 16 = 4096 (1 page) */
977
978/* Transmit and Receive Buffers */
979#define NUM_LBUFQ_ENTRIES 128
980#define NUM_SBUFQ_ENTRIES 64
981#define QL_SMALL_BUFFER_SIZE 32
982#define QL_ADDR_ELE_PER_BUFQ_ENTRY \
983(sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
984 /* Each send has at least control block. This is how many we keep. */
985#define NUM_SMALL_BUFFERS NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
986#define NUM_LARGE_BUFFERS NUM_LBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
987#define QL_HEADER_SPACE 32 /* make header space at top of skb. */
988/*
989 * Large & Small Buffers for Receives
990 */
991struct lrg_buf_q_entry {
992
993 u32 addr0_lower;
994#define IAL_LAST_ENTRY 0x00000001
995#define IAL_CONT_ENTRY 0x00000002
996#define IAL_FLAG_MASK 0x00000003
997 u32 addr0_upper;
998 u32 addr1_lower;
999 u32 addr1_upper;
1000 u32 addr2_lower;
1001 u32 addr2_upper;
1002 u32 addr3_lower;
1003 u32 addr3_upper;
1004 u32 addr4_lower;
1005 u32 addr4_upper;
1006 u32 addr5_lower;
1007 u32 addr5_upper;
1008 u32 addr6_lower;
1009 u32 addr6_upper;
1010 u32 addr7_lower;
1011 u32 addr7_upper;
1012
1013};
1014
1015struct bufq_addr_element {
1016 u32 addr_low;
1017 u32 addr_high;
1018};
1019
1020#define QL_NO_RESET 0
1021#define QL_DO_RESET 1
1022
1023enum link_state_t {
1024 LS_UNKNOWN = 0,
1025 LS_DOWN,
1026 LS_DEGRADE,
1027 LS_RECOVER,
1028 LS_UP,
1029};
1030
1031struct ql_rcv_buf_cb {
1032 struct ql_rcv_buf_cb *next;
1033 struct sk_buff *skb;
1034 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1035 DECLARE_PCI_UNMAP_LEN(maplen);
1036 __le32 buf_phy_addr_low;
1037 __le32 buf_phy_addr_high;
1038 int index;
1039};
1040
1041struct ql_tx_buf_cb {
1042 struct sk_buff *skb;
1043 struct ob_mac_iocb_req *queue_entry ;
1044 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1045 DECLARE_PCI_UNMAP_LEN(maplen);
1046};
1047
1048/* definitions for type field */
1049#define QL_BUF_TYPE_MACIOCB 0x01
1050#define QL_BUF_TYPE_IPIOCB 0x02
1051#define QL_BUF_TYPE_TCPIOCB 0x03
1052
1053/* qdev->flags definitions. */
1054enum { QL_RESET_DONE = 1, /* Reset finished. */
1055 QL_RESET_ACTIVE = 2, /* Waiting for reset to finish. */
1056 QL_RESET_START = 3, /* Please reset the chip. */
1057 QL_RESET_PER_SCSI = 4, /* SCSI driver requests reset. */
1058 QL_TX_TIMEOUT = 5, /* Timeout in progress. */
1059 QL_LINK_MASTER = 6, /* This driver controls the link. */
1060 QL_ADAPTER_UP = 7, /* Adapter has been brought up. */
1061 QL_THREAD_UP = 8, /* This flag is available. */
1062 QL_LINK_UP = 9, /* Link Status. */
1063 QL_ALLOC_REQ_RSP_Q_DONE = 10,
1064 QL_ALLOC_BUFQS_DONE = 11,
1065 QL_ALLOC_SMALL_BUF_DONE = 12,
1066 QL_LINK_OPTICAL = 13,
1067 QL_MSI_ENABLED = 14,
1068};
1069
1070/*
1071 * ql3_adapter - The main Adapter structure definition.
1072 * This structure has all fields relevant to the hardware.
1073 */
1074
1075struct ql3_adapter {
1076 u32 reserved_00;
1077 unsigned long flags;
1078
1079 /* PCI Configuration information for this device */
1080 struct pci_dev *pdev;
1081 struct net_device *ndev; /* Parent NET device */
1082
1083 /* Hardware information */
1084 u8 chip_rev_id;
1085 u8 pci_slot;
1086 u8 pci_width;
1087 u8 pci_x;
1088 u32 msi;
1089 int index;
1090 struct timer_list adapter_timer; /* timer used for various functions */
1091
1092 spinlock_t adapter_lock;
1093 spinlock_t hw_lock;
1094
1095 /* PCI Bus Relative Register Addresses */
1096 u8 *mmap_virt_base; /* stores return value from ioremap() */
1097 struct ql3xxx_port_registers __iomem *mem_map_registers;
1098 u32 current_page; /* tracks current register page */
1099
1100 u32 msg_enable;
1101 u8 reserved_01[2];
1102 u8 reserved_02[2];
1103
1104 /* Page for Shadow Registers */
1105 void *shadow_reg_virt_addr;
1106 dma_addr_t shadow_reg_phy_addr;
1107
1108 /* Net Request Queue */
1109 u32 req_q_size;
1110 u32 reserved_03;
1111 struct ob_mac_iocb_req *req_q_virt_addr;
1112 dma_addr_t req_q_phy_addr;
1113 u16 req_producer_index;
1114 u16 reserved_04;
1115 u16 *preq_consumer_index;
1116 u32 req_consumer_index_phy_addr_high;
1117 u32 req_consumer_index_phy_addr_low;
1118 atomic_t tx_count;
1119 struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
1120
1121 /* Net Response Queue */
1122 u32 rsp_q_size;
1123 u32 eeprom_cmd_data;
1124 struct net_rsp_iocb *rsp_q_virt_addr;
1125 dma_addr_t rsp_q_phy_addr;
1126 struct net_rsp_iocb *rsp_current;
1127 u16 rsp_consumer_index;
1128 u16 reserved_06;
1129 u32 *prsp_producer_index;
1130 u32 rsp_producer_index_phy_addr_high;
1131 u32 rsp_producer_index_phy_addr_low;
1132
1133 /* Large Buffer Queue */
1134 u32 lrg_buf_q_alloc_size;
1135 u32 lrg_buf_q_size;
1136 void *lrg_buf_q_alloc_virt_addr;
1137 void *lrg_buf_q_virt_addr;
1138 dma_addr_t lrg_buf_q_alloc_phy_addr;
1139 dma_addr_t lrg_buf_q_phy_addr;
1140 u32 lrg_buf_q_producer_index;
1141 u32 lrg_buf_release_cnt;
1142 struct bufq_addr_element *lrg_buf_next_free;
1143
1144 /* Large (Receive) Buffers */
1145 struct ql_rcv_buf_cb lrg_buf[NUM_LARGE_BUFFERS];
1146 struct ql_rcv_buf_cb *lrg_buf_free_head;
1147 struct ql_rcv_buf_cb *lrg_buf_free_tail;
1148 u32 lrg_buf_free_count;
1149 u32 lrg_buffer_len;
1150 u32 lrg_buf_index;
1151 u32 lrg_buf_skb_check;
1152
1153 /* Small Buffer Queue */
1154 u32 small_buf_q_alloc_size;
1155 u32 small_buf_q_size;
1156 u32 small_buf_q_producer_index;
1157 void *small_buf_q_alloc_virt_addr;
1158 void *small_buf_q_virt_addr;
1159 dma_addr_t small_buf_q_alloc_phy_addr;
1160 dma_addr_t small_buf_q_phy_addr;
1161 u32 small_buf_index;
1162
1163 /* Small (Receive) Buffers */
1164 void *small_buf_virt_addr;
1165 dma_addr_t small_buf_phy_addr;
1166 u32 small_buf_phy_addr_low;
1167 u32 small_buf_phy_addr_high;
1168 u32 small_buf_release_cnt;
1169 u32 small_buf_total_size;
1170
1171 /* ISR related, saves status for DPC. */
1172 u32 control_status;
1173
1174 struct eeprom_data nvram_data;
1175 struct timer_list ioctl_timer;
1176 u32 port_link_state;
1177 u32 last_rsp_offset;
1178
1179 /* 4022 specific */
1180 u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1181 u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1182 u32 mac_ob_opcode; /* Opcode to use on mac transmission */
1183 u32 tcp_ob_opcode; /* Opcode to use on tcp transmission */
1184 u32 update_ob_opcode; /* Opcode to use for updating NCB */
1185 u32 mb_bit_mask; /* MA Bits mask to use on transmission */
1186 u32 numPorts;
1187 struct net_device_stats stats;
1188 struct workqueue_struct *workqueue;
1189 struct work_struct reset_work;
1190 struct work_struct tx_timeout_work;
1191 u32 max_frame_size;
1192};
1193
1194#endif /* _QLA3XXX_H_ */
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 4c2f575faad7..5722a5638ffc 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -2809,7 +2809,7 @@ static struct pci_driver rtl8169_pci_driver = {
2809static int __init 2809static int __init
2810rtl8169_init_module(void) 2810rtl8169_init_module(void)
2811{ 2811{
2812 return pci_module_init(&rtl8169_pci_driver); 2812 return pci_register_driver(&rtl8169_pci_driver);
2813} 2813}
2814 2814
2815static void __exit 2815static void __exit
diff --git a/drivers/net/rrunner.c b/drivers/net/rrunner.c
index c3ed734cbe39..31bcdad54716 100644
--- a/drivers/net/rrunner.c
+++ b/drivers/net/rrunner.c
@@ -1736,7 +1736,7 @@ static struct pci_driver rr_driver = {
1736 1736
1737static int __init rr_init_module(void) 1737static int __init rr_init_module(void)
1738{ 1738{
1739 return pci_module_init(&rr_driver); 1739 return pci_register_driver(&rr_driver);
1740} 1740}
1741 1741
1742static void __exit rr_cleanup_module(void) 1742static void __exit rr_cleanup_module(void)
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index e72e0e099060..c16f9156c98a 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -7233,7 +7233,7 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7233 7233
7234int __init s2io_starter(void) 7234int __init s2io_starter(void)
7235{ 7235{
7236 return pci_module_init(&s2io_driver); 7236 return pci_register_driver(&s2io_driver);
7237} 7237}
7238 7238
7239/** 7239/**
diff --git a/drivers/net/saa9730.c b/drivers/net/saa9730.c
index b2acedbefa8f..c479b07be788 100644
--- a/drivers/net/saa9730.c
+++ b/drivers/net/saa9730.c
@@ -1131,7 +1131,7 @@ static struct pci_driver saa9730_driver = {
1131 1131
1132static int __init saa9730_init(void) 1132static int __init saa9730_init(void)
1133{ 1133{
1134 return pci_module_init(&saa9730_driver); 1134 return pci_register_driver(&saa9730_driver);
1135} 1135}
1136 1136
1137static void __exit saa9730_cleanup(void) 1137static void __exit saa9730_cleanup(void)
diff --git a/drivers/net/sis190.c b/drivers/net/sis190.c
index df0cbebb3277..16e30d523fc5 100644
--- a/drivers/net/sis190.c
+++ b/drivers/net/sis190.c
@@ -1871,7 +1871,7 @@ static struct pci_driver sis190_pci_driver = {
1871 1871
1872static int __init sis190_init_module(void) 1872static int __init sis190_init_module(void)
1873{ 1873{
1874 return pci_module_init(&sis190_pci_driver); 1874 return pci_register_driver(&sis190_pci_driver);
1875} 1875}
1876 1876
1877static void __exit sis190_cleanup_module(void) 1877static void __exit sis190_cleanup_module(void)
diff --git a/drivers/net/sis900.c b/drivers/net/sis900.c
index 29ee7ffedfff..6af50286349d 100644
--- a/drivers/net/sis900.c
+++ b/drivers/net/sis900.c
@@ -134,6 +134,7 @@ static const struct mii_chip_info {
134 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN }, 134 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
135 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME}, 135 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME},
136 { "ICS LAN PHY", 0x0015, 0xF440, LAN }, 136 { "ICS LAN PHY", 0x0015, 0xF440, LAN },
137 { "ICS LAN PHY", 0x0143, 0xBC70, LAN },
137 { "NS 83851 PHY", 0x2000, 0x5C20, MIX }, 138 { "NS 83851 PHY", 0x2000, 0x5C20, MIX },
138 { "NS 83847 PHY", 0x2000, 0x5C30, MIX }, 139 { "NS 83847 PHY", 0x2000, 0x5C30, MIX },
139 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN }, 140 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN },
@@ -2495,7 +2496,7 @@ static int __init sis900_init_module(void)
2495 printk(version); 2496 printk(version);
2496#endif 2497#endif
2497 2498
2498 return pci_module_init(&sis900_pci_driver); 2499 return pci_register_driver(&sis900_pci_driver);
2499} 2500}
2500 2501
2501static void __exit sis900_cleanup_module(void) 2502static void __exit sis900_cleanup_module(void)
diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c
index ee62845d3ac9..49e76c7f10da 100644
--- a/drivers/net/sk98lin/skge.c
+++ b/drivers/net/sk98lin/skge.c
@@ -5133,7 +5133,7 @@ static struct pci_driver skge_driver = {
5133 5133
5134static int __init skge_init(void) 5134static int __init skge_init(void)
5135{ 5135{
5136 return pci_module_init(&skge_driver); 5136 return pci_register_driver(&skge_driver);
5137} 5137}
5138 5138
5139static void __exit skge_exit(void) 5139static void __exit skge_exit(void)
diff --git a/drivers/net/skfp/skfddi.c b/drivers/net/skfp/skfddi.c
index b5714a60237d..8e4d18440a56 100644
--- a/drivers/net/skfp/skfddi.c
+++ b/drivers/net/skfp/skfddi.c
@@ -2280,7 +2280,7 @@ static struct pci_driver skfddi_pci_driver = {
2280 2280
2281static int __init skfd_init(void) 2281static int __init skfd_init(void)
2282{ 2282{
2283 return pci_module_init(&skfddi_pci_driver); 2283 return pci_register_driver(&skfddi_pci_driver);
2284} 2284}
2285 2285
2286static void __exit skfd_exit(void) 2286static void __exit skfd_exit(void)
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index ad878dfddef4..fba8b7455d8b 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -43,7 +43,7 @@
43#include "skge.h" 43#include "skge.h"
44 44
45#define DRV_NAME "skge" 45#define DRV_NAME "skge"
46#define DRV_VERSION "1.6" 46#define DRV_VERSION "1.8"
47#define PFX DRV_NAME " " 47#define PFX DRV_NAME " "
48 48
49#define DEFAULT_TX_RING_SIZE 128 49#define DEFAULT_TX_RING_SIZE 128
@@ -91,7 +91,7 @@ MODULE_DEVICE_TABLE(pci, skge_id_table);
91static int skge_up(struct net_device *dev); 91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev); 92static int skge_down(struct net_device *dev);
93static void skge_phy_reset(struct skge_port *skge); 93static void skge_phy_reset(struct skge_port *skge);
94static void skge_tx_clean(struct skge_port *skge); 94static void skge_tx_clean(struct net_device *dev);
95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static void genesis_get_stats(struct skge_port *skge, u64 *data); 97static void genesis_get_stats(struct skge_port *skge, u64 *data);
@@ -105,6 +105,7 @@ static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 }; 105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
108 109
109static int skge_get_regs_len(struct net_device *dev) 110static int skge_get_regs_len(struct net_device *dev)
110{ 111{
@@ -818,8 +819,9 @@ static void skge_rx_clean(struct skge_port *skge)
818/* Allocate buffers for receive ring 819/* Allocate buffers for receive ring
819 * For receive: to_clean is next received frame. 820 * For receive: to_clean is next received frame.
820 */ 821 */
821static int skge_rx_fill(struct skge_port *skge) 822static int skge_rx_fill(struct net_device *dev)
822{ 823{
824 struct skge_port *skge = netdev_priv(dev);
823 struct skge_ring *ring = &skge->rx_ring; 825 struct skge_ring *ring = &skge->rx_ring;
824 struct skge_element *e; 826 struct skge_element *e;
825 827
@@ -827,7 +829,8 @@ static int skge_rx_fill(struct skge_port *skge)
827 do { 829 do {
828 struct sk_buff *skb; 830 struct sk_buff *skb;
829 831
830 skb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_KERNEL); 832 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
833 GFP_KERNEL);
831 if (!skb) 834 if (!skb)
832 return -ENOMEM; 835 return -ENOMEM;
833 836
@@ -2178,7 +2181,7 @@ static int skge_up(struct net_device *dev)
2178 if (err) 2181 if (err)
2179 goto free_pci_mem; 2182 goto free_pci_mem;
2180 2183
2181 err = skge_rx_fill(skge); 2184 err = skge_rx_fill(dev);
2182 if (err) 2185 if (err)
2183 goto free_rx_ring; 2186 goto free_rx_ring;
2184 2187
@@ -2281,7 +2284,7 @@ static int skge_down(struct net_device *dev)
2281 skge_led(skge, LED_MODE_OFF); 2284 skge_led(skge, LED_MODE_OFF);
2282 2285
2283 netif_poll_disable(dev); 2286 netif_poll_disable(dev);
2284 skge_tx_clean(skge); 2287 skge_tx_clean(dev);
2285 skge_rx_clean(skge); 2288 skge_rx_clean(skge);
2286 2289
2287 kfree(skge->rx_ring.start); 2290 kfree(skge->rx_ring.start);
@@ -2306,25 +2309,12 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2306 int i; 2309 int i;
2307 u32 control, len; 2310 u32 control, len;
2308 u64 map; 2311 u64 map;
2309 unsigned long flags;
2310 2312
2311 if (skb_padto(skb, ETH_ZLEN)) 2313 if (skb_padto(skb, ETH_ZLEN))
2312 return NETDEV_TX_OK; 2314 return NETDEV_TX_OK;
2313 2315
2314 if (!spin_trylock_irqsave(&skge->tx_lock, flags)) 2316 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2315 /* Collision - tell upper layer to requeue */
2316 return NETDEV_TX_LOCKED;
2317
2318 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
2319 if (!netif_queue_stopped(dev)) {
2320 netif_stop_queue(dev);
2321
2322 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2323 dev->name);
2324 }
2325 spin_unlock_irqrestore(&skge->tx_lock, flags);
2326 return NETDEV_TX_BUSY; 2317 return NETDEV_TX_BUSY;
2327 }
2328 2318
2329 e = skge->tx_ring.to_use; 2319 e = skge->tx_ring.to_use;
2330 td = e->desc; 2320 td = e->desc;
@@ -2399,8 +2389,6 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2399 netif_stop_queue(dev); 2389 netif_stop_queue(dev);
2400 } 2390 }
2401 2391
2402 spin_unlock_irqrestore(&skge->tx_lock, flags);
2403
2404 dev->trans_start = jiffies; 2392 dev->trans_start = jiffies;
2405 2393
2406 return NETDEV_TX_OK; 2394 return NETDEV_TX_OK;
@@ -2430,18 +2418,18 @@ static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2430 printk(KERN_DEBUG PFX "%s: tx done slot %td\n", 2418 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2431 skge->netdev->name, e - skge->tx_ring.start); 2419 skge->netdev->name, e - skge->tx_ring.start);
2432 2420
2433 dev_kfree_skb_any(e->skb); 2421 dev_kfree_skb(e->skb);
2434 } 2422 }
2435 e->skb = NULL; 2423 e->skb = NULL;
2436} 2424}
2437 2425
2438/* Free all buffers in transmit ring */ 2426/* Free all buffers in transmit ring */
2439static void skge_tx_clean(struct skge_port *skge) 2427static void skge_tx_clean(struct net_device *dev)
2440{ 2428{
2429 struct skge_port *skge = netdev_priv(dev);
2441 struct skge_element *e; 2430 struct skge_element *e;
2442 unsigned long flags;
2443 2431
2444 spin_lock_irqsave(&skge->tx_lock, flags); 2432 netif_tx_lock_bh(dev);
2445 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 2433 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2446 struct skge_tx_desc *td = e->desc; 2434 struct skge_tx_desc *td = e->desc;
2447 skge_tx_free(skge, e, td->control); 2435 skge_tx_free(skge, e, td->control);
@@ -2449,8 +2437,8 @@ static void skge_tx_clean(struct skge_port *skge)
2449 } 2437 }
2450 2438
2451 skge->tx_ring.to_clean = e; 2439 skge->tx_ring.to_clean = e;
2452 netif_wake_queue(skge->netdev); 2440 netif_wake_queue(dev);
2453 spin_unlock_irqrestore(&skge->tx_lock, flags); 2441 netif_tx_unlock_bh(dev);
2454} 2442}
2455 2443
2456static void skge_tx_timeout(struct net_device *dev) 2444static void skge_tx_timeout(struct net_device *dev)
@@ -2461,7 +2449,7 @@ static void skge_tx_timeout(struct net_device *dev)
2461 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name); 2449 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2462 2450
2463 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); 2451 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2464 skge_tx_clean(skge); 2452 skge_tx_clean(dev);
2465} 2453}
2466 2454
2467static int skge_change_mtu(struct net_device *dev, int new_mtu) 2455static int skge_change_mtu(struct net_device *dev, int new_mtu)
@@ -2584,16 +2572,17 @@ static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2584/* Get receive buffer from descriptor. 2572/* Get receive buffer from descriptor.
2585 * Handles copy of small buffers and reallocation failures 2573 * Handles copy of small buffers and reallocation failures
2586 */ 2574 */
2587static inline struct sk_buff *skge_rx_get(struct skge_port *skge, 2575static struct sk_buff *skge_rx_get(struct net_device *dev,
2588 struct skge_element *e, 2576 struct skge_element *e,
2589 u32 control, u32 status, u16 csum) 2577 u32 control, u32 status, u16 csum)
2590{ 2578{
2579 struct skge_port *skge = netdev_priv(dev);
2591 struct sk_buff *skb; 2580 struct sk_buff *skb;
2592 u16 len = control & BMU_BBC; 2581 u16 len = control & BMU_BBC;
2593 2582
2594 if (unlikely(netif_msg_rx_status(skge))) 2583 if (unlikely(netif_msg_rx_status(skge)))
2595 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n", 2584 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2596 skge->netdev->name, e - skge->rx_ring.start, 2585 dev->name, e - skge->rx_ring.start,
2597 status, len); 2586 status, len);
2598 2587
2599 if (len > skge->rx_buf_size) 2588 if (len > skge->rx_buf_size)
@@ -2609,7 +2598,7 @@ static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2609 goto error; 2598 goto error;
2610 2599
2611 if (len < RX_COPY_THRESHOLD) { 2600 if (len < RX_COPY_THRESHOLD) {
2612 skb = alloc_skb(len + 2, GFP_ATOMIC); 2601 skb = netdev_alloc_skb(dev, len + 2);
2613 if (!skb) 2602 if (!skb)
2614 goto resubmit; 2603 goto resubmit;
2615 2604
@@ -2624,7 +2613,7 @@ static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2624 skge_rx_reuse(e, skge->rx_buf_size); 2613 skge_rx_reuse(e, skge->rx_buf_size);
2625 } else { 2614 } else {
2626 struct sk_buff *nskb; 2615 struct sk_buff *nskb;
2627 nskb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_ATOMIC); 2616 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2628 if (!nskb) 2617 if (!nskb)
2629 goto resubmit; 2618 goto resubmit;
2630 2619
@@ -2639,20 +2628,19 @@ static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2639 } 2628 }
2640 2629
2641 skb_put(skb, len); 2630 skb_put(skb, len);
2642 skb->dev = skge->netdev;
2643 if (skge->rx_csum) { 2631 if (skge->rx_csum) {
2644 skb->csum = csum; 2632 skb->csum = csum;
2645 skb->ip_summed = CHECKSUM_HW; 2633 skb->ip_summed = CHECKSUM_HW;
2646 } 2634 }
2647 2635
2648 skb->protocol = eth_type_trans(skb, skge->netdev); 2636 skb->protocol = eth_type_trans(skb, dev);
2649 2637
2650 return skb; 2638 return skb;
2651error: 2639error:
2652 2640
2653 if (netif_msg_rx_err(skge)) 2641 if (netif_msg_rx_err(skge))
2654 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n", 2642 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2655 skge->netdev->name, e - skge->rx_ring.start, 2643 dev->name, e - skge->rx_ring.start,
2656 control, status); 2644 control, status);
2657 2645
2658 if (skge->hw->chip_id == CHIP_ID_GENESIS) { 2646 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
@@ -2677,15 +2665,15 @@ resubmit:
2677} 2665}
2678 2666
2679/* Free all buffers in Tx ring which are no longer owned by device */ 2667/* Free all buffers in Tx ring which are no longer owned by device */
2680static void skge_txirq(struct net_device *dev) 2668static void skge_tx_done(struct net_device *dev)
2681{ 2669{
2682 struct skge_port *skge = netdev_priv(dev); 2670 struct skge_port *skge = netdev_priv(dev);
2683 struct skge_ring *ring = &skge->tx_ring; 2671 struct skge_ring *ring = &skge->tx_ring;
2684 struct skge_element *e; 2672 struct skge_element *e;
2685 2673
2686 rmb(); 2674 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2687 2675
2688 spin_lock(&skge->tx_lock); 2676 netif_tx_lock(dev);
2689 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 2677 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2690 struct skge_tx_desc *td = e->desc; 2678 struct skge_tx_desc *td = e->desc;
2691 2679
@@ -2696,11 +2684,10 @@ static void skge_txirq(struct net_device *dev)
2696 } 2684 }
2697 skge->tx_ring.to_clean = e; 2685 skge->tx_ring.to_clean = e;
2698 2686
2699 if (netif_queue_stopped(skge->netdev) 2687 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2700 && skge_avail(&skge->tx_ring) > TX_LOW_WATER) 2688 netif_wake_queue(dev);
2701 netif_wake_queue(skge->netdev);
2702 2689
2703 spin_unlock(&skge->tx_lock); 2690 netif_tx_unlock(dev);
2704} 2691}
2705 2692
2706static int skge_poll(struct net_device *dev, int *budget) 2693static int skge_poll(struct net_device *dev, int *budget)
@@ -2712,6 +2699,10 @@ static int skge_poll(struct net_device *dev, int *budget)
2712 int to_do = min(dev->quota, *budget); 2699 int to_do = min(dev->quota, *budget);
2713 int work_done = 0; 2700 int work_done = 0;
2714 2701
2702 skge_tx_done(dev);
2703
2704 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2705
2715 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) { 2706 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2716 struct skge_rx_desc *rd = e->desc; 2707 struct skge_rx_desc *rd = e->desc;
2717 struct sk_buff *skb; 2708 struct sk_buff *skb;
@@ -2722,7 +2713,7 @@ static int skge_poll(struct net_device *dev, int *budget)
2722 if (control & BMU_OWN) 2713 if (control & BMU_OWN)
2723 break; 2714 break;
2724 2715
2725 skb = skge_rx_get(skge, e, control, rd->status, rd->csum2); 2716 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
2726 if (likely(skb)) { 2717 if (likely(skb)) {
2727 dev->last_rx = jiffies; 2718 dev->last_rx = jiffies;
2728 netif_receive_skb(skb); 2719 netif_receive_skb(skb);
@@ -2742,12 +2733,11 @@ static int skge_poll(struct net_device *dev, int *budget)
2742 if (work_done >= to_do) 2733 if (work_done >= to_do)
2743 return 1; /* not done */ 2734 return 1; /* not done */
2744 2735
2745 netif_rx_complete(dev);
2746
2747 spin_lock_irq(&hw->hw_lock); 2736 spin_lock_irq(&hw->hw_lock);
2748 hw->intr_mask |= rxirqmask[skge->port]; 2737 __netif_rx_complete(dev);
2738 hw->intr_mask |= irqmask[skge->port];
2749 skge_write32(hw, B0_IMSK, hw->intr_mask); 2739 skge_write32(hw, B0_IMSK, hw->intr_mask);
2750 mmiowb(); 2740 skge_read32(hw, B0_IMSK);
2751 spin_unlock_irq(&hw->hw_lock); 2741 spin_unlock_irq(&hw->hw_lock);
2752 2742
2753 return 0; 2743 return 0;
@@ -2881,6 +2871,7 @@ static void skge_extirq(void *arg)
2881 spin_lock_irq(&hw->hw_lock); 2871 spin_lock_irq(&hw->hw_lock);
2882 hw->intr_mask |= IS_EXT_REG; 2872 hw->intr_mask |= IS_EXT_REG;
2883 skge_write32(hw, B0_IMSK, hw->intr_mask); 2873 skge_write32(hw, B0_IMSK, hw->intr_mask);
2874 skge_read32(hw, B0_IMSK);
2884 spin_unlock_irq(&hw->hw_lock); 2875 spin_unlock_irq(&hw->hw_lock);
2885} 2876}
2886 2877
@@ -2888,27 +2879,23 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2888{ 2879{
2889 struct skge_hw *hw = dev_id; 2880 struct skge_hw *hw = dev_id;
2890 u32 status; 2881 u32 status;
2882 int handled = 0;
2891 2883
2884 spin_lock(&hw->hw_lock);
2892 /* Reading this register masks IRQ */ 2885 /* Reading this register masks IRQ */
2893 status = skge_read32(hw, B0_SP_ISRC); 2886 status = skge_read32(hw, B0_SP_ISRC);
2894 if (status == 0) 2887 if (status == 0 || status == ~0)
2895 return IRQ_NONE; 2888 goto out;
2896 2889
2897 spin_lock(&hw->hw_lock); 2890 handled = 1;
2898 status &= hw->intr_mask; 2891 status &= hw->intr_mask;
2899 if (status & IS_EXT_REG) { 2892 if (status & IS_EXT_REG) {
2900 hw->intr_mask &= ~IS_EXT_REG; 2893 hw->intr_mask &= ~IS_EXT_REG;
2901 schedule_work(&hw->phy_work); 2894 schedule_work(&hw->phy_work);
2902 } 2895 }
2903 2896
2904 if (status & IS_XA1_F) { 2897 if (status & (IS_XA1_F|IS_R1_F)) {
2905 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F); 2898 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
2906 skge_txirq(hw->dev[0]);
2907 }
2908
2909 if (status & IS_R1_F) {
2910 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2911 hw->intr_mask &= ~IS_R1_F;
2912 netif_rx_schedule(hw->dev[0]); 2899 netif_rx_schedule(hw->dev[0]);
2913 } 2900 }
2914 2901
@@ -2927,14 +2914,8 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2927 skge_mac_intr(hw, 0); 2914 skge_mac_intr(hw, 0);
2928 2915
2929 if (hw->dev[1]) { 2916 if (hw->dev[1]) {
2930 if (status & IS_XA2_F) { 2917 if (status & (IS_XA2_F|IS_R2_F)) {
2931 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F); 2918 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
2932 skge_txirq(hw->dev[1]);
2933 }
2934
2935 if (status & IS_R2_F) {
2936 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2937 hw->intr_mask &= ~IS_R2_F;
2938 netif_rx_schedule(hw->dev[1]); 2919 netif_rx_schedule(hw->dev[1]);
2939 } 2920 }
2940 2921
@@ -2955,9 +2936,11 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2955 skge_error_irq(hw); 2936 skge_error_irq(hw);
2956 2937
2957 skge_write32(hw, B0_IMSK, hw->intr_mask); 2938 skge_write32(hw, B0_IMSK, hw->intr_mask);
2939 skge_read32(hw, B0_IMSK);
2940out:
2958 spin_unlock(&hw->hw_lock); 2941 spin_unlock(&hw->hw_lock);
2959 2942
2960 return IRQ_HANDLED; 2943 return IRQ_RETVAL(handled);
2961} 2944}
2962 2945
2963#ifdef CONFIG_NET_POLL_CONTROLLER 2946#ifdef CONFIG_NET_POLL_CONTROLLER
@@ -3106,7 +3089,6 @@ static int skge_reset(struct skge_hw *hw)
3106 else 3089 else
3107 hw->ram_size = t8 * 4096; 3090 hw->ram_size = t8 * 4096;
3108 3091
3109 spin_lock_init(&hw->hw_lock);
3110 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1; 3092 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3111 if (hw->ports > 1) 3093 if (hw->ports > 1)
3112 hw->intr_mask |= IS_PORT_2; 3094 hw->intr_mask |= IS_PORT_2;
@@ -3222,7 +3204,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3222 dev->poll_controller = skge_netpoll; 3204 dev->poll_controller = skge_netpoll;
3223#endif 3205#endif
3224 dev->irq = hw->pdev->irq; 3206 dev->irq = hw->pdev->irq;
3225 dev->features = NETIF_F_LLTX; 3207
3226 if (highmem) 3208 if (highmem)
3227 dev->features |= NETIF_F_HIGHDMA; 3209 dev->features |= NETIF_F_HIGHDMA;
3228 3210
@@ -3244,8 +3226,6 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3244 3226
3245 skge->port = port; 3227 skge->port = port;
3246 3228
3247 spin_lock_init(&skge->tx_lock);
3248
3249 if (hw->chip_id != CHIP_ID_GENESIS) { 3229 if (hw->chip_id != CHIP_ID_GENESIS) {
3250 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 3230 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3251 skge->rx_csum = 1; 3231 skge->rx_csum = 1;
@@ -3332,6 +3312,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3332 hw->pdev = pdev; 3312 hw->pdev = pdev;
3333 mutex_init(&hw->phy_mutex); 3313 mutex_init(&hw->phy_mutex);
3334 INIT_WORK(&hw->phy_work, skge_extirq, hw); 3314 INIT_WORK(&hw->phy_work, skge_extirq, hw);
3315 spin_lock_init(&hw->hw_lock);
3335 3316
3336 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 3317 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3337 if (!hw->regs) { 3318 if (!hw->regs) {
@@ -3340,23 +3321,16 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3340 goto err_out_free_hw; 3321 goto err_out_free_hw;
3341 } 3322 }
3342 3323
3343 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, DRV_NAME, hw);
3344 if (err) {
3345 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3346 pci_name(pdev), pdev->irq);
3347 goto err_out_iounmap;
3348 }
3349 pci_set_drvdata(pdev, hw);
3350
3351 err = skge_reset(hw); 3324 err = skge_reset(hw);
3352 if (err) 3325 if (err)
3353 goto err_out_free_irq; 3326 goto err_out_iounmap;
3354 3327
3355 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n", 3328 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3356 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, 3329 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3357 skge_board_name(hw), hw->chip_rev); 3330 skge_board_name(hw), hw->chip_rev);
3358 3331
3359 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL) 3332 dev = skge_devinit(hw, 0, using_dac);
3333 if (!dev)
3360 goto err_out_led_off; 3334 goto err_out_led_off;
3361 3335
3362 if (!is_valid_ether_addr(dev->dev_addr)) { 3336 if (!is_valid_ether_addr(dev->dev_addr)) {
@@ -3366,7 +3340,6 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3366 goto err_out_free_netdev; 3340 goto err_out_free_netdev;
3367 } 3341 }
3368 3342
3369
3370 err = register_netdev(dev); 3343 err = register_netdev(dev);
3371 if (err) { 3344 if (err) {
3372 printk(KERN_ERR PFX "%s: cannot register net device\n", 3345 printk(KERN_ERR PFX "%s: cannot register net device\n",
@@ -3374,6 +3347,12 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3374 goto err_out_free_netdev; 3347 goto err_out_free_netdev;
3375 } 3348 }
3376 3349
3350 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3351 if (err) {
3352 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3353 dev->name, pdev->irq);
3354 goto err_out_unregister;
3355 }
3377 skge_show_addr(dev); 3356 skge_show_addr(dev);
3378 3357
3379 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { 3358 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
@@ -3386,15 +3365,16 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3386 free_netdev(dev1); 3365 free_netdev(dev1);
3387 } 3366 }
3388 } 3367 }
3368 pci_set_drvdata(pdev, hw);
3389 3369
3390 return 0; 3370 return 0;
3391 3371
3372err_out_unregister:
3373 unregister_netdev(dev);
3392err_out_free_netdev: 3374err_out_free_netdev:
3393 free_netdev(dev); 3375 free_netdev(dev);
3394err_out_led_off: 3376err_out_led_off:
3395 skge_write16(hw, B0_LED, LED_STAT_OFF); 3377 skge_write16(hw, B0_LED, LED_STAT_OFF);
3396err_out_free_irq:
3397 free_irq(pdev->irq, hw);
3398err_out_iounmap: 3378err_out_iounmap:
3399 iounmap(hw->regs); 3379 iounmap(hw->regs);
3400err_out_free_hw: 3380err_out_free_hw:
@@ -3424,6 +3404,7 @@ static void __devexit skge_remove(struct pci_dev *pdev)
3424 spin_lock_irq(&hw->hw_lock); 3404 spin_lock_irq(&hw->hw_lock);
3425 hw->intr_mask = 0; 3405 hw->intr_mask = 0;
3426 skge_write32(hw, B0_IMSK, 0); 3406 skge_write32(hw, B0_IMSK, 0);
3407 skge_read32(hw, B0_IMSK);
3427 spin_unlock_irq(&hw->hw_lock); 3408 spin_unlock_irq(&hw->hw_lock);
3428 3409
3429 skge_write16(hw, B0_LED, LED_STAT_OFF); 3410 skge_write16(hw, B0_LED, LED_STAT_OFF);
@@ -3449,26 +3430,25 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3449 struct skge_hw *hw = pci_get_drvdata(pdev); 3430 struct skge_hw *hw = pci_get_drvdata(pdev);
3450 int i, wol = 0; 3431 int i, wol = 0;
3451 3432
3452 for (i = 0; i < 2; i++) { 3433 pci_save_state(pdev);
3434 for (i = 0; i < hw->ports; i++) {
3453 struct net_device *dev = hw->dev[i]; 3435 struct net_device *dev = hw->dev[i];
3454 3436
3455 if (dev) { 3437 if (netif_running(dev)) {
3456 struct skge_port *skge = netdev_priv(dev); 3438 struct skge_port *skge = netdev_priv(dev);
3457 if (netif_running(dev)) { 3439
3458 netif_carrier_off(dev); 3440 netif_carrier_off(dev);
3459 if (skge->wol) 3441 if (skge->wol)
3460 netif_stop_queue(dev); 3442 netif_stop_queue(dev);
3461 else 3443 else
3462 skge_down(dev); 3444 skge_down(dev);
3463 }
3464 netif_device_detach(dev);
3465 wol |= skge->wol; 3445 wol |= skge->wol;
3466 } 3446 }
3447 netif_device_detach(dev);
3467 } 3448 }
3468 3449
3469 pci_save_state(pdev); 3450 skge_write32(hw, B0_IMSK, 0);
3470 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); 3451 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3471 pci_disable_device(pdev);
3472 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 3452 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3473 3453
3474 return 0; 3454 return 0;
@@ -3477,23 +3457,33 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3477static int skge_resume(struct pci_dev *pdev) 3457static int skge_resume(struct pci_dev *pdev)
3478{ 3458{
3479 struct skge_hw *hw = pci_get_drvdata(pdev); 3459 struct skge_hw *hw = pci_get_drvdata(pdev);
3480 int i; 3460 int i, err;
3481 3461
3482 pci_set_power_state(pdev, PCI_D0); 3462 pci_set_power_state(pdev, PCI_D0);
3483 pci_restore_state(pdev); 3463 pci_restore_state(pdev);
3484 pci_enable_wake(pdev, PCI_D0, 0); 3464 pci_enable_wake(pdev, PCI_D0, 0);
3485 3465
3486 skge_reset(hw); 3466 err = skge_reset(hw);
3467 if (err)
3468 goto out;
3487 3469
3488 for (i = 0; i < 2; i++) { 3470 for (i = 0; i < hw->ports; i++) {
3489 struct net_device *dev = hw->dev[i]; 3471 struct net_device *dev = hw->dev[i];
3490 if (dev) { 3472
3491 netif_device_attach(dev); 3473 netif_device_attach(dev);
3492 if (netif_running(dev) && skge_up(dev)) 3474 if (netif_running(dev)) {
3475 err = skge_up(dev);
3476
3477 if (err) {
3478 printk(KERN_ERR PFX "%s: could not up: %d\n",
3479 dev->name, err);
3493 dev_close(dev); 3480 dev_close(dev);
3481 goto out;
3482 }
3494 } 3483 }
3495 } 3484 }
3496 return 0; 3485out:
3486 return err;
3497} 3487}
3498#endif 3488#endif
3499 3489
@@ -3510,7 +3500,7 @@ static struct pci_driver skge_driver = {
3510 3500
3511static int __init skge_init_module(void) 3501static int __init skge_init_module(void)
3512{ 3502{
3513 return pci_module_init(&skge_driver); 3503 return pci_register_driver(&skge_driver);
3514} 3504}
3515 3505
3516static void __exit skge_cleanup_module(void) 3506static void __exit skge_cleanup_module(void)
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index 593387b3c0dd..79e09271bcf9 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -2417,7 +2417,6 @@ struct skge_port {
2417 struct net_device *netdev; 2417 struct net_device *netdev;
2418 int port; 2418 int port;
2419 2419
2420 spinlock_t tx_lock;
2421 struct skge_ring tx_ring; 2420 struct skge_ring tx_ring;
2422 struct skge_ring rx_ring; 2421 struct skge_ring rx_ring;
2423 2422
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 933e87f1cc68..7ce0663baf45 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -50,7 +50,7 @@
50#include "sky2.h" 50#include "sky2.h"
51 51
52#define DRV_NAME "sky2" 52#define DRV_NAME "sky2"
53#define DRV_VERSION "1.5" 53#define DRV_VERSION "1.7"
54#define PFX DRV_NAME " " 54#define PFX DRV_NAME " "
55 55
56/* 56/*
@@ -106,6 +106,7 @@ static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
@@ -117,10 +118,17 @@ static const struct pci_device_id sky2_id_table[] = {
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
124 { 0 } 132 { 0 }
125}; 133};
126 134
@@ -190,7 +198,6 @@ static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
190static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) 198static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
191{ 199{
192 u16 power_control; 200 u16 power_control;
193 u32 reg1;
194 int vaux; 201 int vaux;
195 202
196 pr_debug("sky2_set_power_state %d\n", state); 203 pr_debug("sky2_set_power_state %d\n", state);
@@ -223,20 +230,9 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
223 else 230 else
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225 232
226 /* Turn off phy power saving */
227 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229
230 /* looks like this XL is back asswards .. */
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
233 if (hw->ports > 1)
234 reg1 |= PCI_Y2_PHY2_COMA;
235 }
236 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
237 udelay(100);
238
239 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 233 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
234 u32 reg1;
235
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); 237 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
242 reg1 &= P_ASPM_CONTROL_MSK; 238 reg1 &= P_ASPM_CONTROL_MSK;
@@ -248,15 +244,6 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
248 244
249 case PCI_D3hot: 245 case PCI_D3hot:
250 case PCI_D3cold: 246 case PCI_D3cold:
251 /* Turn on phy power saving */
252 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
253 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
254 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
255 else
256 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
257 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
258 udelay(100);
259
260 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
261 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
262 else 249 else
@@ -280,7 +267,7 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
281} 268}
282 269
283static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) 270static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
284{ 271{
285 u16 reg; 272 u16 reg;
286 273
@@ -528,6 +515,29 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
528 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 515 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
529} 516}
530 517
518static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
519{
520 u32 reg1;
521 static const u32 phy_power[]
522 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
523
524 /* looks like this XL is back asswards .. */
525 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
526 onoff = !onoff;
527
528 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
529
530 if (onoff)
531 /* Turn off phy power saving */
532 reg1 &= ~phy_power[port];
533 else
534 reg1 |= phy_power[port];
535
536 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
537 sky2_pci_read32(hw, PCI_DEV_REG1);
538 udelay(100);
539}
540
531/* Force a renegotiation */ 541/* Force a renegotiation */
532static void sky2_phy_reinit(struct sky2_port *sky2) 542static void sky2_phy_reinit(struct sky2_port *sky2)
533{ 543{
@@ -760,9 +770,10 @@ static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
760/* Update chip's next pointer */ 770/* Update chip's next pointer */
761static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 771static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
762{ 772{
773 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
763 wmb(); 774 wmb();
764 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 775 sky2_write16(hw, q, idx);
765 mmiowb(); 776 sky2_read16(hw, q);
766} 777}
767 778
768 779
@@ -949,14 +960,16 @@ static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
949/* 960/*
950 * It appears the hardware has a bug in the FIFO logic that 961 * It appears the hardware has a bug in the FIFO logic that
951 * cause it to hang if the FIFO gets overrun and the receive buffer 962 * cause it to hang if the FIFO gets overrun and the receive buffer
952 * is not aligned. ALso alloc_skb() won't align properly if slab 963 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
953 * debugging is enabled. 964 * aligned except if slab debugging is enabled.
954 */ 965 */
955static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) 966static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
967 unsigned int length,
968 gfp_t gfp_mask)
956{ 969{
957 struct sk_buff *skb; 970 struct sk_buff *skb;
958 971
959 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); 972 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
960 if (likely(skb)) { 973 if (likely(skb)) {
961 unsigned long p = (unsigned long) skb->data; 974 unsigned long p = (unsigned long) skb->data;
962 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); 975 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
@@ -992,7 +1005,8 @@ static int sky2_rx_start(struct sky2_port *sky2)
992 for (i = 0; i < sky2->rx_pending; i++) { 1005 for (i = 0; i < sky2->rx_pending; i++) {
993 struct ring_info *re = sky2->rx_ring + i; 1006 struct ring_info *re = sky2->rx_ring + i;
994 1007
995 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); 1008 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
1009 GFP_KERNEL);
996 if (!re->skb) 1010 if (!re->skb)
997 goto nomem; 1011 goto nomem;
998 1012
@@ -1080,6 +1094,8 @@ static int sky2_up(struct net_device *dev)
1080 if (!sky2->rx_ring) 1094 if (!sky2->rx_ring)
1081 goto err_out; 1095 goto err_out;
1082 1096
1097 sky2_phy_power(hw, port, 1);
1098
1083 sky2_mac_init(hw, port); 1099 sky2_mac_init(hw, port);
1084 1100
1085 /* Determine available ram buffer space (in 4K blocks). 1101 /* Determine available ram buffer space (in 4K blocks).
@@ -1184,7 +1200,6 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1184 struct sky2_tx_le *le = NULL; 1200 struct sky2_tx_le *le = NULL;
1185 struct tx_ring_info *re; 1201 struct tx_ring_info *re;
1186 unsigned i, len; 1202 unsigned i, len;
1187 int avail;
1188 dma_addr_t mapping; 1203 dma_addr_t mapping;
1189 u32 addr64; 1204 u32 addr64;
1190 u16 mss; 1205 u16 mss;
@@ -1234,25 +1249,18 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1234 /* Check for TCP Segmentation Offload */ 1249 /* Check for TCP Segmentation Offload */
1235 mss = skb_shinfo(skb)->gso_size; 1250 mss = skb_shinfo(skb)->gso_size;
1236 if (mss != 0) { 1251 if (mss != 0) {
1237 /* just drop the packet if non-linear expansion fails */
1238 if (skb_header_cloned(skb) &&
1239 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1240 dev_kfree_skb(skb);
1241 goto out_unlock;
1242 }
1243
1244 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ 1252 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1245 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); 1253 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1246 mss += ETH_HLEN; 1254 mss += ETH_HLEN;
1247 }
1248 1255
1249 if (mss != sky2->tx_last_mss) { 1256 if (mss != sky2->tx_last_mss) {
1250 le = get_tx_le(sky2); 1257 le = get_tx_le(sky2);
1251 le->tx.tso.size = cpu_to_le16(mss); 1258 le->tx.tso.size = cpu_to_le16(mss);
1252 le->tx.tso.rsvd = 0; 1259 le->tx.tso.rsvd = 0;
1253 le->opcode = OP_LRGLEN | HW_OWNER; 1260 le->opcode = OP_LRGLEN | HW_OWNER;
1254 le->ctrl = 0; 1261 le->ctrl = 0;
1255 sky2->tx_last_mss = mss; 1262 sky2->tx_last_mss = mss;
1263 }
1256 } 1264 }
1257 1265
1258 ctrl = 0; 1266 ctrl = 0;
@@ -1280,12 +1288,17 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1280 if (skb->nh.iph->protocol == IPPROTO_UDP) 1288 if (skb->nh.iph->protocol == IPPROTO_UDP)
1281 ctrl |= UDPTCP; 1289 ctrl |= UDPTCP;
1282 1290
1283 le = get_tx_le(sky2); 1291 if (hdr != sky2->tx_csum_start || offset != sky2->tx_csum_offset) {
1284 le->tx.csum.start = cpu_to_le16(hdr); 1292 sky2->tx_csum_start = hdr;
1285 le->tx.csum.offset = cpu_to_le16(offset); 1293 sky2->tx_csum_offset = offset;
1286 le->length = 0; /* initial checksum value */ 1294
1287 le->ctrl = 1; /* one packet */ 1295 le = get_tx_le(sky2);
1288 le->opcode = OP_TCPLISW | HW_OWNER; 1296 le->tx.csum.start = cpu_to_le16(hdr);
1297 le->tx.csum.offset = cpu_to_le16(offset);
1298 le->length = 0; /* initial checksum value */
1299 le->ctrl = 1; /* one packet */
1300 le->opcode = OP_TCPLISW | HW_OWNER;
1301 }
1289 } 1302 }
1290 1303
1291 le = get_tx_le(sky2); 1304 le = get_tx_le(sky2);
@@ -1320,23 +1333,18 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1320 le->opcode = OP_BUFFER | HW_OWNER; 1333 le->opcode = OP_BUFFER | HW_OWNER;
1321 1334
1322 fre = sky2->tx_ring 1335 fre = sky2->tx_ring
1323 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE); 1336 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1324 pci_unmap_addr_set(fre, mapaddr, mapping); 1337 pci_unmap_addr_set(fre, mapaddr, mapping);
1325 } 1338 }
1326 1339
1327 re->idx = sky2->tx_prod; 1340 re->idx = sky2->tx_prod;
1328 le->ctrl |= EOP; 1341 le->ctrl |= EOP;
1329 1342
1330 avail = tx_avail(sky2); 1343 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1331 if (mss != 0 || avail < TX_MIN_PENDING) { 1344 netif_stop_queue(dev);
1332 le->ctrl |= FRC_STAT;
1333 if (avail <= MAX_SKB_TX_LE)
1334 netif_stop_queue(dev);
1335 }
1336 1345
1337 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1346 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1338 1347
1339out_unlock:
1340 spin_unlock(&sky2->tx_lock); 1348 spin_unlock(&sky2->tx_lock);
1341 1349
1342 dev->trans_start = jiffies; 1350 dev->trans_start = jiffies;
@@ -1421,7 +1429,7 @@ static int sky2_down(struct net_device *dev)
1421 /* Stop more packets from being queued */ 1429 /* Stop more packets from being queued */
1422 netif_stop_queue(dev); 1430 netif_stop_queue(dev);
1423 1431
1424 sky2_phy_reset(hw, port); 1432 sky2_gmac_reset(hw, port);
1425 1433
1426 /* Stop transmitter */ 1434 /* Stop transmitter */
1427 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 1435 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
@@ -1469,6 +1477,8 @@ static int sky2_down(struct net_device *dev)
1469 imask &= ~portirq_msk[port]; 1477 imask &= ~portirq_msk[port];
1470 sky2_write32(hw, B0_IMSK, imask); 1478 sky2_write32(hw, B0_IMSK, imask);
1471 1479
1480 sky2_phy_power(hw, port, 0);
1481
1472 /* turn off LED's */ 1482 /* turn off LED's */
1473 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); 1483 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1474 1484
@@ -1832,15 +1842,16 @@ static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1832 * For small packets or errors, just reuse existing skb. 1842 * For small packets or errors, just reuse existing skb.
1833 * For larger packets, get new buffer. 1843 * For larger packets, get new buffer.
1834 */ 1844 */
1835static struct sk_buff *sky2_receive(struct sky2_port *sky2, 1845static struct sk_buff *sky2_receive(struct net_device *dev,
1836 u16 length, u32 status) 1846 u16 length, u32 status)
1837{ 1847{
1848 struct sky2_port *sky2 = netdev_priv(dev);
1838 struct ring_info *re = sky2->rx_ring + sky2->rx_next; 1849 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1839 struct sk_buff *skb = NULL; 1850 struct sk_buff *skb = NULL;
1840 1851
1841 if (unlikely(netif_msg_rx_status(sky2))) 1852 if (unlikely(netif_msg_rx_status(sky2)))
1842 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", 1853 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1843 sky2->netdev->name, sky2->rx_next, status, length); 1854 dev->name, sky2->rx_next, status, length);
1844 1855
1845 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 1856 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1846 prefetch(sky2->rx_ring + sky2->rx_next); 1857 prefetch(sky2->rx_ring + sky2->rx_next);
@@ -1851,11 +1862,11 @@ static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1851 if (!(status & GMR_FS_RX_OK)) 1862 if (!(status & GMR_FS_RX_OK))
1852 goto resubmit; 1863 goto resubmit;
1853 1864
1854 if (length > sky2->netdev->mtu + ETH_HLEN) 1865 if (length > dev->mtu + ETH_HLEN)
1855 goto oversize; 1866 goto oversize;
1856 1867
1857 if (length < copybreak) { 1868 if (length < copybreak) {
1858 skb = alloc_skb(length + 2, GFP_ATOMIC); 1869 skb = netdev_alloc_skb(dev, length + 2);
1859 if (!skb) 1870 if (!skb)
1860 goto resubmit; 1871 goto resubmit;
1861 1872
@@ -1870,7 +1881,7 @@ static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1870 } else { 1881 } else {
1871 struct sk_buff *nskb; 1882 struct sk_buff *nskb;
1872 1883
1873 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); 1884 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
1874 if (!nskb) 1885 if (!nskb)
1875 goto resubmit; 1886 goto resubmit;
1876 1887
@@ -1900,7 +1911,7 @@ error:
1900 1911
1901 if (netif_msg_rx_err(sky2) && net_ratelimit()) 1912 if (netif_msg_rx_err(sky2) && net_ratelimit())
1902 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", 1913 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1903 sky2->netdev->name, status, length); 1914 dev->name, status, length);
1904 1915
1905 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) 1916 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1906 sky2->net_stats.rx_length_errors++; 1917 sky2->net_stats.rx_length_errors++;
@@ -1926,12 +1937,6 @@ static inline void sky2_tx_done(struct net_device *dev, u16 last)
1926 } 1937 }
1927} 1938}
1928 1939
1929/* Is status ring empty or is there more to do? */
1930static inline int sky2_more_work(const struct sky2_hw *hw)
1931{
1932 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1933}
1934
1935/* Process status response ring */ 1940/* Process status response ring */
1936static int sky2_status_intr(struct sky2_hw *hw, int to_do) 1941static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1937{ 1942{
@@ -1960,11 +1965,10 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1960 1965
1961 switch (le->opcode & ~HW_OWNER) { 1966 switch (le->opcode & ~HW_OWNER) {
1962 case OP_RXSTAT: 1967 case OP_RXSTAT:
1963 skb = sky2_receive(sky2, length, status); 1968 skb = sky2_receive(dev, length, status);
1964 if (!skb) 1969 if (!skb)
1965 break; 1970 break;
1966 1971
1967 skb->dev = dev;
1968 skb->protocol = eth_type_trans(skb, dev); 1972 skb->protocol = eth_type_trans(skb, dev);
1969 dev->last_rx = jiffies; 1973 dev->last_rx = jiffies;
1970 1974
@@ -2022,6 +2026,9 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2022 } 2026 }
2023 } 2027 }
2024 2028
2029 /* Fully processed status ring so clear irq */
2030 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2031
2025exit_loop: 2032exit_loop:
2026 if (buf_write[0]) { 2033 if (buf_write[0]) {
2027 sky2 = netdev_priv(hw->dev[0]); 2034 sky2 = netdev_priv(hw->dev[0]);
@@ -2231,19 +2238,16 @@ static int sky2_poll(struct net_device *dev0, int *budget)
2231 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); 2238 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2232 2239
2233 work_done = sky2_status_intr(hw, work_limit); 2240 work_done = sky2_status_intr(hw, work_limit);
2234 *budget -= work_done; 2241 if (work_done < work_limit) {
2235 dev0->quota -= work_done; 2242 netif_rx_complete(dev0);
2236 2243
2237 if (status & Y2_IS_STAT_BMU) 2244 sky2_read32(hw, B0_Y2_SP_LISR);
2238 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2245 return 0;
2239 2246 } else {
2240 if (sky2_more_work(hw)) 2247 *budget -= work_done;
2248 dev0->quota -= work_done;
2241 return 1; 2249 return 1;
2242 2250 }
2243 netif_rx_complete(dev0);
2244
2245 sky2_read32(hw, B0_Y2_SP_LISR);
2246 return 0;
2247} 2251}
2248 2252
2249static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) 2253static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
@@ -2409,7 +2413,7 @@ static int sky2_reset(struct sky2_hw *hw)
2409 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); 2413 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2410 2414
2411 for (i = 0; i < hw->ports; i++) 2415 for (i = 0; i < hw->ports; i++)
2412 sky2_phy_reset(hw, i); 2416 sky2_gmac_reset(hw, i);
2413 2417
2414 memset(hw->st_le, 0, STATUS_LE_BYTES); 2418 memset(hw->st_le, 0, STATUS_LE_BYTES);
2415 hw->st_idx = 0; 2419 hw->st_idx = 0;
@@ -3200,6 +3204,8 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3200 struct pci_dev *pdev = hw->pdev; 3204 struct pci_dev *pdev = hw->pdev;
3201 int err; 3205 int err;
3202 3206
3207 init_waitqueue_head (&hw->msi_wait);
3208
3203 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 3209 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3204 3210
3205 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw); 3211 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
@@ -3209,10 +3215,8 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3209 return err; 3215 return err;
3210 } 3216 }
3211 3217
3212 init_waitqueue_head (&hw->msi_wait);
3213
3214 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 3218 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3215 wmb(); 3219 sky2_read8(hw, B0_CTST);
3216 3220
3217 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); 3221 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3218 3222
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 2db8d19b22d1..fa8af9f503e4 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -1748,7 +1748,6 @@ enum {
1748 INIT_SUM= 1<<3, 1748 INIT_SUM= 1<<3,
1749 LOCK_SUM= 1<<4, 1749 LOCK_SUM= 1<<4,
1750 INS_VLAN= 1<<5, 1750 INS_VLAN= 1<<5,
1751 FRC_STAT= 1<<6,
1752 EOP = 1<<7, 1751 EOP = 1<<7,
1753}; 1752};
1754 1753
@@ -1844,6 +1843,8 @@ struct sky2_port {
1844 u32 tx_addr64; 1843 u32 tx_addr64;
1845 u16 tx_pending; 1844 u16 tx_pending;
1846 u16 tx_last_mss; 1845 u16 tx_last_mss;
1846 u16 tx_csum_start;
1847 u16 tx_csum_offset;
1847 1848
1848 struct ring_info *rx_ring ____cacheline_aligned_in_smp; 1849 struct ring_info *rx_ring ____cacheline_aligned_in_smp;
1849 struct sky2_rx_le *rx_le; 1850 struct sky2_rx_le *rx_le;
diff --git a/drivers/net/slhc.c b/drivers/net/slhc.c
index 3a1b7131681c..9a540e2092b9 100644
--- a/drivers/net/slhc.c
+++ b/drivers/net/slhc.c
@@ -94,27 +94,23 @@ slhc_init(int rslots, int tslots)
94 register struct cstate *ts; 94 register struct cstate *ts;
95 struct slcompress *comp; 95 struct slcompress *comp;
96 96
97 comp = (struct slcompress *)kmalloc(sizeof(struct slcompress), 97 comp = kzalloc(sizeof(struct slcompress), GFP_KERNEL);
98 GFP_KERNEL);
99 if (! comp) 98 if (! comp)
100 goto out_fail; 99 goto out_fail;
101 memset(comp, 0, sizeof(struct slcompress));
102 100
103 if ( rslots > 0 && rslots < 256 ) { 101 if ( rslots > 0 && rslots < 256 ) {
104 size_t rsize = rslots * sizeof(struct cstate); 102 size_t rsize = rslots * sizeof(struct cstate);
105 comp->rstate = (struct cstate *) kmalloc(rsize, GFP_KERNEL); 103 comp->rstate = kzalloc(rsize, GFP_KERNEL);
106 if (! comp->rstate) 104 if (! comp->rstate)
107 goto out_free; 105 goto out_free;
108 memset(comp->rstate, 0, rsize);
109 comp->rslot_limit = rslots - 1; 106 comp->rslot_limit = rslots - 1;
110 } 107 }
111 108
112 if ( tslots > 0 && tslots < 256 ) { 109 if ( tslots > 0 && tslots < 256 ) {
113 size_t tsize = tslots * sizeof(struct cstate); 110 size_t tsize = tslots * sizeof(struct cstate);
114 comp->tstate = (struct cstate *) kmalloc(tsize, GFP_KERNEL); 111 comp->tstate = kzalloc(tsize, GFP_KERNEL);
115 if (! comp->tstate) 112 if (! comp->tstate)
116 goto out_free2; 113 goto out_free2;
117 memset(comp->tstate, 0, tsize);
118 comp->tslot_limit = tslots - 1; 114 comp->tslot_limit = tslots - 1;
119 } 115 }
120 116
@@ -141,9 +137,9 @@ slhc_init(int rslots, int tslots)
141 return comp; 137 return comp;
142 138
143out_free2: 139out_free2:
144 kfree((unsigned char *)comp->rstate); 140 kfree(comp->rstate);
145out_free: 141out_free:
146 kfree((unsigned char *)comp); 142 kfree(comp);
147out_fail: 143out_fail:
148 return NULL; 144 return NULL;
149} 145}
@@ -700,20 +696,6 @@ EXPORT_SYMBOL(slhc_compress);
700EXPORT_SYMBOL(slhc_uncompress); 696EXPORT_SYMBOL(slhc_uncompress);
701EXPORT_SYMBOL(slhc_toss); 697EXPORT_SYMBOL(slhc_toss);
702 698
703#ifdef MODULE
704
705int init_module(void)
706{
707 printk(KERN_INFO "CSLIP: code copyright 1989 Regents of the University of California\n");
708 return 0;
709}
710
711void cleanup_module(void)
712{
713 return;
714}
715
716#endif /* MODULE */
717#else /* CONFIG_INET */ 699#else /* CONFIG_INET */
718 700
719 701
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 0b15290df278..4438fe8c9499 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -55,8 +55,6 @@ static const char version[] =
55 ) 55 )
56#endif 56#endif
57 57
58
59#include <linux/config.h>
60#include <linux/init.h> 58#include <linux/init.h>
61#include <linux/module.h> 59#include <linux/module.h>
62#include <linux/kernel.h> 60#include <linux/kernel.h>
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index c0a62b00ffc8..8e1f6206b7d0 100644
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -2053,7 +2053,7 @@ static int __init starfire_init (void)
2053 return -ENODEV; 2053 return -ENODEV;
2054 } 2054 }
2055 2055
2056 return pci_module_init (&starfire_driver); 2056 return pci_register_driver(&starfire_driver);
2057} 2057}
2058 2058
2059 2059
diff --git a/drivers/net/sundance.c b/drivers/net/sundance.c
index 698568e751da..c243a80f4006 100644
--- a/drivers/net/sundance.c
+++ b/drivers/net/sundance.c
@@ -17,6 +17,8 @@
17 Support and updates available at 17 Support and updates available at
18 http://www.scyld.com/network/sundance.html 18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik] 19 [link no longer provides useful info -jgarzik]
20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
20 22
21*/ 23*/
22 24
@@ -646,7 +648,7 @@ static int __devinit sundance_probe1 (struct pci_dev *pdev,
646 /* Reset the chip to erase previous misconfiguration. */ 648 /* Reset the chip to erase previous misconfiguration. */
647 if (netif_msg_hw(np)) 649 if (netif_msg_hw(np))
648 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl)); 650 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
649 iowrite16(0x00ff, ioaddr + ASICCtrl + 2); 651 sundance_reset(dev, 0x00ff << 16);
650 if (netif_msg_hw(np)) 652 if (netif_msg_hw(np))
651 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl)); 653 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
652 654
@@ -1075,13 +1077,8 @@ reset_tx (struct net_device *dev)
1075 1077
1076 /* Reset tx logic, TxListPtr will be cleaned */ 1078 /* Reset tx logic, TxListPtr will be cleaned */
1077 iowrite16 (TxDisable, ioaddr + MACCtrl1); 1079 iowrite16 (TxDisable, ioaddr + MACCtrl1);
1078 iowrite16 (TxReset | DMAReset | FIFOReset | NetworkReset, 1080 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1079 ioaddr + ASICCtrl + 2); 1081
1080 for (i=50; i > 0; i--) {
1081 if ((ioread16(ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
1082 break;
1083 mdelay(1);
1084 }
1085 /* free all tx skbuff */ 1082 /* free all tx skbuff */
1086 for (i = 0; i < TX_RING_SIZE; i++) { 1083 for (i = 0; i < TX_RING_SIZE; i++) {
1087 skb = np->tx_skbuff[i]; 1084 skb = np->tx_skbuff[i];
@@ -1736,7 +1733,7 @@ static int __init sundance_init(void)
1736#ifdef MODULE 1733#ifdef MODULE
1737 printk(version); 1734 printk(version);
1738#endif 1735#endif
1739 return pci_module_init(&sundance_driver); 1736 return pci_register_driver(&sundance_driver);
1740} 1737}
1741 1738
1742static void __exit sundance_exit(void) 1739static void __exit sundance_exit(void)
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index b70bbd748978..1a441a8a2add 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -3194,7 +3194,7 @@ static struct pci_driver gem_driver = {
3194 3194
3195static int __init gem_init(void) 3195static int __init gem_init(void)
3196{ 3196{
3197 return pci_module_init(&gem_driver); 3197 return pci_register_driver(&gem_driver);
3198} 3198}
3199 3199
3200static void __exit gem_cleanup(void) 3200static void __exit gem_cleanup(void)
diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c
index 8b53ded66d37..39460fa916fe 100644
--- a/drivers/net/tc35815.c
+++ b/drivers/net/tc35815.c
@@ -1725,7 +1725,7 @@ static struct pci_driver tc35815_driver = {
1725 1725
1726static int __init tc35815_init_module(void) 1726static int __init tc35815_init_module(void)
1727{ 1727{
1728 return pci_module_init(&tc35815_driver); 1728 return pci_register_driver(&tc35815_driver);
1729} 1729}
1730 1730
1731static void __exit tc35815_cleanup_module(void) 1731static void __exit tc35815_cleanup_module(void)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index eafabb253f08..d6e2a6869f28 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -11819,7 +11819,7 @@ static struct pci_driver tg3_driver = {
11819 11819
11820static int __init tg3_init(void) 11820static int __init tg3_init(void)
11821{ 11821{
11822 return pci_module_init(&tg3_driver); 11822 return pci_register_driver(&tg3_driver);
11823} 11823}
11824 11824
11825static void __exit tg3_cleanup(void) 11825static void __exit tg3_cleanup(void)
diff --git a/drivers/net/tokenring/3c359.c b/drivers/net/tokenring/3c359.c
index 465921e3874c..412390ba142e 100644
--- a/drivers/net/tokenring/3c359.c
+++ b/drivers/net/tokenring/3c359.c
@@ -1815,7 +1815,7 @@ static struct pci_driver xl_3c359_driver = {
1815 1815
1816static int __init xl_pci_init (void) 1816static int __init xl_pci_init (void)
1817{ 1817{
1818 return pci_module_init (&xl_3c359_driver); 1818 return pci_register_driver(&xl_3c359_driver);
1819} 1819}
1820 1820
1821 1821
diff --git a/drivers/net/tokenring/lanstreamer.c b/drivers/net/tokenring/lanstreamer.c
index 28d968ffd5d0..0d66700c6ced 100644
--- a/drivers/net/tokenring/lanstreamer.c
+++ b/drivers/net/tokenring/lanstreamer.c
@@ -1998,7 +1998,7 @@ static struct pci_driver streamer_pci_driver = {
1998}; 1998};
1999 1999
2000static int __init streamer_init_module(void) { 2000static int __init streamer_init_module(void) {
2001 return pci_module_init(&streamer_pci_driver); 2001 return pci_register_driver(&streamer_pci_driver);
2002} 2002}
2003 2003
2004static void __exit streamer_cleanup_module(void) { 2004static void __exit streamer_cleanup_module(void) {
diff --git a/drivers/net/tulip/21142.c b/drivers/net/tulip/21142.c
index 683f14b01c06..fa3a2bb105ad 100644
--- a/drivers/net/tulip/21142.c
+++ b/drivers/net/tulip/21142.c
@@ -1,7 +1,7 @@
1/* 1/*
2 drivers/net/tulip/21142.c 2 drivers/net/tulip/21142.c
3 3
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 7
@@ -26,9 +26,9 @@ static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
26 26
27/* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list 27/* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list
28 of available transceivers. */ 28 of available transceivers. */
29void t21142_timer(unsigned long data) 29void t21142_media_task(void *data)
30{ 30{
31 struct net_device *dev = (struct net_device *)data; 31 struct net_device *dev = data;
32 struct tulip_private *tp = netdev_priv(dev); 32 struct tulip_private *tp = netdev_priv(dev);
33 void __iomem *ioaddr = tp->base_addr; 33 void __iomem *ioaddr = tp->base_addr;
34 int csr12 = ioread32(ioaddr + CSR12); 34 int csr12 = ioread32(ioaddr + CSR12);
diff --git a/drivers/net/tulip/de2104x.c b/drivers/net/tulip/de2104x.c
index d05c5aa254ee..17a2ebaef58c 100644
--- a/drivers/net/tulip/de2104x.c
+++ b/drivers/net/tulip/de2104x.c
@@ -2138,17 +2138,21 @@ static int de_resume (struct pci_dev *pdev)
2138{ 2138{
2139 struct net_device *dev = pci_get_drvdata (pdev); 2139 struct net_device *dev = pci_get_drvdata (pdev);
2140 struct de_private *de = dev->priv; 2140 struct de_private *de = dev->priv;
2141 int retval = 0;
2141 2142
2142 rtnl_lock(); 2143 rtnl_lock();
2143 if (netif_device_present(dev)) 2144 if (netif_device_present(dev))
2144 goto out; 2145 goto out;
2145 if (netif_running(dev)) { 2146 if (!netif_running(dev))
2146 pci_enable_device(pdev); 2147 goto out_attach;
2147 de_init_hw(de); 2148 if ((retval = pci_enable_device(pdev))) {
2148 netif_device_attach(dev); 2149 printk (KERN_ERR "%s: pci_enable_device failed in resume\n",
2149 } else { 2150 dev->name);
2150 netif_device_attach(dev); 2151 goto out;
2151 } 2152 }
2153 de_init_hw(de);
2154out_attach:
2155 netif_device_attach(dev);
2152out: 2156out:
2153 rtnl_unlock(); 2157 rtnl_unlock();
2154 return 0; 2158 return 0;
@@ -2172,7 +2176,7 @@ static int __init de_init (void)
2172#ifdef MODULE 2176#ifdef MODULE
2173 printk("%s", version); 2177 printk("%s", version);
2174#endif 2178#endif
2175 return pci_module_init (&de_driver); 2179 return pci_register_driver(&de_driver);
2176} 2180}
2177 2181
2178static void __exit de_exit (void) 2182static void __exit de_exit (void)
diff --git a/drivers/net/tulip/de4x5.c b/drivers/net/tulip/de4x5.c
index 75ff14a55239..e661d0a9cc64 100644
--- a/drivers/net/tulip/de4x5.c
+++ b/drivers/net/tulip/de4x5.c
@@ -5754,7 +5754,7 @@ static int __init de4x5_module_init (void)
5754 int err = 0; 5754 int err = 0;
5755 5755
5756#ifdef CONFIG_PCI 5756#ifdef CONFIG_PCI
5757 err = pci_module_init (&de4x5_pci_driver); 5757 err = pci_register_driver(&de4x5_pci_driver);
5758#endif 5758#endif
5759#ifdef CONFIG_EISA 5759#ifdef CONFIG_EISA
5760 err |= eisa_driver_register (&de4x5_eisa_driver); 5760 err |= eisa_driver_register (&de4x5_eisa_driver);
diff --git a/drivers/net/tulip/dmfe.c b/drivers/net/tulip/dmfe.c
index 4e5b0f2acc39..66dade556821 100644
--- a/drivers/net/tulip/dmfe.c
+++ b/drivers/net/tulip/dmfe.c
@@ -2039,7 +2039,7 @@ static int __init dmfe_init_module(void)
2039 if (HPNA_NoiseFloor > 15) 2039 if (HPNA_NoiseFloor > 15)
2040 HPNA_NoiseFloor = 0; 2040 HPNA_NoiseFloor = 0;
2041 2041
2042 rc = pci_module_init(&dmfe_driver); 2042 rc = pci_register_driver(&dmfe_driver);
2043 if (rc < 0) 2043 if (rc < 0)
2044 return rc; 2044 return rc;
2045 2045
diff --git a/drivers/net/tulip/eeprom.c b/drivers/net/tulip/eeprom.c
index 5ffbd5b300c0..206918bad539 100644
--- a/drivers/net/tulip/eeprom.c
+++ b/drivers/net/tulip/eeprom.c
@@ -1,7 +1,7 @@
1/* 1/*
2 drivers/net/tulip/eeprom.c 2 drivers/net/tulip/eeprom.c
3 3
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 7
diff --git a/drivers/net/tulip/interrupt.c b/drivers/net/tulip/interrupt.c
index 99ccf2ebb342..7f8f5d42a761 100644
--- a/drivers/net/tulip/interrupt.c
+++ b/drivers/net/tulip/interrupt.c
@@ -1,7 +1,7 @@
1/* 1/*
2 drivers/net/tulip/interrupt.c 2 drivers/net/tulip/interrupt.c
3 3
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 7
diff --git a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c
index e9bc2a958c14..20bd52b86993 100644
--- a/drivers/net/tulip/media.c
+++ b/drivers/net/tulip/media.c
@@ -1,7 +1,7 @@
1/* 1/*
2 drivers/net/tulip/media.c 2 drivers/net/tulip/media.c
3 3
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 7
diff --git a/drivers/net/tulip/pnic.c b/drivers/net/tulip/pnic.c
index ca7e53246adb..85a521e0d052 100644
--- a/drivers/net/tulip/pnic.c
+++ b/drivers/net/tulip/pnic.c
@@ -1,7 +1,7 @@
1/* 1/*
2 drivers/net/tulip/pnic.c 2 drivers/net/tulip/pnic.c
3 3
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 7
diff --git a/drivers/net/tulip/pnic2.c b/drivers/net/tulip/pnic2.c
index ab985023fcca..c31be0e377a8 100644
--- a/drivers/net/tulip/pnic2.c
+++ b/drivers/net/tulip/pnic2.c
@@ -1,7 +1,7 @@
1/* 1/*
2 drivers/net/tulip/pnic2.c 2 drivers/net/tulip/pnic2.c
3 3
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 Modified to hep support PNIC_II by Kevin B. Hendricks 7 Modified to hep support PNIC_II by Kevin B. Hendricks
diff --git a/drivers/net/tulip/timer.c b/drivers/net/tulip/timer.c
index e058a9fbfe88..066e5d6bcbd8 100644
--- a/drivers/net/tulip/timer.c
+++ b/drivers/net/tulip/timer.c
@@ -1,7 +1,7 @@
1/* 1/*
2 drivers/net/tulip/timer.c 2 drivers/net/tulip/timer.c
3 3
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 7
@@ -18,13 +18,14 @@
18#include "tulip.h" 18#include "tulip.h"
19 19
20 20
21void tulip_timer(unsigned long data) 21void tulip_media_task(void *data)
22{ 22{
23 struct net_device *dev = (struct net_device *)data; 23 struct net_device *dev = data;
24 struct tulip_private *tp = netdev_priv(dev); 24 struct tulip_private *tp = netdev_priv(dev);
25 void __iomem *ioaddr = tp->base_addr; 25 void __iomem *ioaddr = tp->base_addr;
26 u32 csr12 = ioread32(ioaddr + CSR12); 26 u32 csr12 = ioread32(ioaddr + CSR12);
27 int next_tick = 2*HZ; 27 int next_tick = 2*HZ;
28 unsigned long flags;
28 29
29 if (tulip_debug > 2) { 30 if (tulip_debug > 2) {
30 printk(KERN_DEBUG "%s: Media selection tick, %s, status %8.8x mode" 31 printk(KERN_DEBUG "%s: Media selection tick, %s, status %8.8x mode"
@@ -126,6 +127,15 @@ void tulip_timer(unsigned long data)
126 } 127 }
127 break; 128 break;
128 } 129 }
130
131
132 spin_lock_irqsave(&tp->lock, flags);
133 if (tp->timeout_recovery) {
134 tulip_tx_timeout_complete(tp, ioaddr);
135 tp->timeout_recovery = 0;
136 }
137 spin_unlock_irqrestore(&tp->lock, flags);
138
129 /* mod_timer synchronizes us with potential add_timer calls 139 /* mod_timer synchronizes us with potential add_timer calls
130 * from interrupts. 140 * from interrupts.
131 */ 141 */
diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h
index 3bcfbf3d23ed..25668ddb1f7e 100644
--- a/drivers/net/tulip/tulip.h
+++ b/drivers/net/tulip/tulip.h
@@ -30,11 +30,10 @@
30/* undefine, or define to various debugging levels (>4 == obscene levels) */ 30/* undefine, or define to various debugging levels (>4 == obscene levels) */
31#define TULIP_DEBUG 1 31#define TULIP_DEBUG 1
32 32
33/* undefine USE_IO_OPS for MMIO, define for PIO */
34#ifdef CONFIG_TULIP_MMIO 33#ifdef CONFIG_TULIP_MMIO
35# undef USE_IO_OPS 34#define TULIP_BAR 1 /* CBMA */
36#else 35#else
37# define USE_IO_OPS 1 36#define TULIP_BAR 0 /* CBIO */
38#endif 37#endif
39 38
40 39
@@ -44,7 +43,8 @@ struct tulip_chip_table {
44 int io_size; 43 int io_size;
45 int valid_intrs; /* CSR7 interrupt enable settings */ 44 int valid_intrs; /* CSR7 interrupt enable settings */
46 int flags; 45 int flags;
47 void (*media_timer) (unsigned long data); 46 void (*media_timer) (unsigned long);
47 void (*media_task) (void *);
48}; 48};
49 49
50 50
@@ -142,6 +142,7 @@ enum status_bits {
142 RxNoBuf = 0x80, 142 RxNoBuf = 0x80,
143 RxIntr = 0x40, 143 RxIntr = 0x40,
144 TxFIFOUnderflow = 0x20, 144 TxFIFOUnderflow = 0x20,
145 RxErrIntr = 0x10,
145 TxJabber = 0x08, 146 TxJabber = 0x08,
146 TxNoBuf = 0x04, 147 TxNoBuf = 0x04,
147 TxDied = 0x02, 148 TxDied = 0x02,
@@ -192,9 +193,14 @@ struct tulip_tx_desc {
192 193
193 194
194enum desc_status_bits { 195enum desc_status_bits {
195 DescOwned = 0x80000000, 196 DescOwned = 0x80000000,
196 RxDescFatalErr = 0x8000, 197 DescWholePkt = 0x60000000,
197 RxWholePkt = 0x0300, 198 DescEndPkt = 0x40000000,
199 DescStartPkt = 0x20000000,
200 DescEndRing = 0x02000000,
201 DescUseLink = 0x01000000,
202 RxDescFatalErr = 0x008000,
203 RxWholePkt = 0x00000300,
198}; 204};
199 205
200 206
@@ -366,6 +372,7 @@ struct tulip_private {
366 unsigned int medialock:1; /* Don't sense media type. */ 372 unsigned int medialock:1; /* Don't sense media type. */
367 unsigned int mediasense:1; /* Media sensing in progress. */ 373 unsigned int mediasense:1; /* Media sensing in progress. */
368 unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */ 374 unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
375 unsigned int timeout_recovery:1;
369 unsigned int csr0; /* CSR0 setting. */ 376 unsigned int csr0; /* CSR0 setting. */
370 unsigned int csr6; /* Current CSR6 control settings. */ 377 unsigned int csr6; /* Current CSR6 control settings. */
371 unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */ 378 unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
@@ -384,6 +391,7 @@ struct tulip_private {
384 void __iomem *base_addr; 391 void __iomem *base_addr;
385 int csr12_shadow; 392 int csr12_shadow;
386 int pad0; /* Used for 8-byte alignment */ 393 int pad0; /* Used for 8-byte alignment */
394 struct work_struct media_work;
387}; 395};
388 396
389 397
@@ -398,7 +406,7 @@ struct eeprom_fixup {
398 406
399/* 21142.c */ 407/* 21142.c */
400extern u16 t21142_csr14[]; 408extern u16 t21142_csr14[];
401void t21142_timer(unsigned long data); 409void t21142_media_task(void *data);
402void t21142_start_nway(struct net_device *dev); 410void t21142_start_nway(struct net_device *dev);
403void t21142_lnk_change(struct net_device *dev, int csr5); 411void t21142_lnk_change(struct net_device *dev, int csr5);
404 412
@@ -436,7 +444,7 @@ void pnic_lnk_change(struct net_device *dev, int csr5);
436void pnic_timer(unsigned long data); 444void pnic_timer(unsigned long data);
437 445
438/* timer.c */ 446/* timer.c */
439void tulip_timer(unsigned long data); 447void tulip_media_task(void *data);
440void mxic_timer(unsigned long data); 448void mxic_timer(unsigned long data);
441void comet_timer(unsigned long data); 449void comet_timer(unsigned long data);
442 450
@@ -485,4 +493,14 @@ static inline void tulip_restart_rxtx(struct tulip_private *tp)
485 tulip_start_rxtx(tp); 493 tulip_start_rxtx(tp);
486} 494}
487 495
496static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
497{
498 /* Stop and restart the chip's Tx processes. */
499 tulip_restart_rxtx(tp);
500 /* Trigger an immediate transmit demand. */
501 iowrite32(0, ioaddr + CSR1);
502
503 tp->stats.tx_errors++;
504}
505
488#endif /* __NET_TULIP_H__ */ 506#endif /* __NET_TULIP_H__ */
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index 7351831f57ce..8092c4f8c036 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -1,7 +1,7 @@
1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */ 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2 2
3/* 3/*
4 Maintained by Jeff Garzik <jgarzik@pobox.com> 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 6 Written/copyright 1994-2001 by Donald Becker.
7 7
@@ -130,7 +130,14 @@ int tulip_debug = TULIP_DEBUG;
130int tulip_debug = 1; 130int tulip_debug = 1;
131#endif 131#endif
132 132
133static void tulip_timer(unsigned long data)
134{
135 struct net_device *dev = (struct net_device *)data;
136 struct tulip_private *tp = netdev_priv(dev);
133 137
138 if (netif_running(dev))
139 schedule_work(&tp->media_work);
140}
134 141
135/* 142/*
136 * This table use during operation for capabilities and media timer. 143 * This table use during operation for capabilities and media timer.
@@ -144,59 +151,60 @@ struct tulip_chip_table tulip_tbl[] = {
144 151
145 /* DC21140 */ 152 /* DC21140 */
146 { "Digital DS21140 Tulip", 128, 0x0001ebef, 153 { "Digital DS21140 Tulip", 128, 0x0001ebef,
147 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer }, 154 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
155 tulip_media_task },
148 156
149 /* DC21142, DC21143 */ 157 /* DC21142, DC21143 */
150 { "Digital DS21143 Tulip", 128, 0x0801fbff, 158 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
151 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY 159 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
152 | HAS_INTR_MITIGATION | HAS_PCI_MWI, t21142_timer }, 160 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
153 161
154 /* LC82C168 */ 162 /* LC82C168 */
155 { "Lite-On 82c168 PNIC", 256, 0x0001fbef, 163 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
156 HAS_MII | HAS_PNICNWAY, pnic_timer }, 164 HAS_MII | HAS_PNICNWAY, pnic_timer, },
157 165
158 /* MX98713 */ 166 /* MX98713 */
159 { "Macronix 98713 PMAC", 128, 0x0001ebef, 167 { "Macronix 98713 PMAC", 128, 0x0001ebef,
160 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer }, 168 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
161 169
162 /* MX98715 */ 170 /* MX98715 */
163 { "Macronix 98715 PMAC", 256, 0x0001ebef, 171 { "Macronix 98715 PMAC", 256, 0x0001ebef,
164 HAS_MEDIA_TABLE, mxic_timer }, 172 HAS_MEDIA_TABLE, mxic_timer, },
165 173
166 /* MX98725 */ 174 /* MX98725 */
167 { "Macronix 98725 PMAC", 256, 0x0001ebef, 175 { "Macronix 98725 PMAC", 256, 0x0001ebef,
168 HAS_MEDIA_TABLE, mxic_timer }, 176 HAS_MEDIA_TABLE, mxic_timer, },
169 177
170 /* AX88140 */ 178 /* AX88140 */
171 { "ASIX AX88140", 128, 0x0001fbff, 179 { "ASIX AX88140", 128, 0x0001fbff,
172 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY 180 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
173 | IS_ASIX, tulip_timer }, 181 | IS_ASIX, tulip_timer, tulip_media_task },
174 182
175 /* PNIC2 */ 183 /* PNIC2 */
176 { "Lite-On PNIC-II", 256, 0x0801fbff, 184 { "Lite-On PNIC-II", 256, 0x0801fbff,
177 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer }, 185 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
178 186
179 /* COMET */ 187 /* COMET */
180 { "ADMtek Comet", 256, 0x0001abef, 188 { "ADMtek Comet", 256, 0x0001abef,
181 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer }, 189 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
182 190
183 /* COMPEX9881 */ 191 /* COMPEX9881 */
184 { "Compex 9881 PMAC", 128, 0x0001ebef, 192 { "Compex 9881 PMAC", 128, 0x0001ebef,
185 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer }, 193 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
186 194
187 /* I21145 */ 195 /* I21145 */
188 { "Intel DS21145 Tulip", 128, 0x0801fbff, 196 { "Intel DS21145 Tulip", 128, 0x0801fbff,
189 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI 197 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
190 | HAS_NWAY | HAS_PCI_MWI, t21142_timer }, 198 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
191 199
192 /* DM910X */ 200 /* DM910X */
193 { "Davicom DM9102/DM9102A", 128, 0x0001ebef, 201 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
194 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI, 202 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
195 tulip_timer }, 203 tulip_timer, tulip_media_task },
196 204
197 /* RS7112 */ 205 /* RS7112 */
198 { "Conexant LANfinity", 256, 0x0001ebef, 206 { "Conexant LANfinity", 256, 0x0001ebef,
199 HAS_MII | HAS_ACPI, tulip_timer }, 207 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
200 208
201}; 209};
202 210
@@ -295,12 +303,14 @@ static void tulip_up(struct net_device *dev)
295 303
296 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ 304 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
297 iowrite32(0x00000001, ioaddr + CSR0); 305 iowrite32(0x00000001, ioaddr + CSR0);
306 pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
298 udelay(100); 307 udelay(100);
299 308
300 /* Deassert reset. 309 /* Deassert reset.
301 Wait the specified 50 PCI cycles after a reset by initializing 310 Wait the specified 50 PCI cycles after a reset by initializing
302 Tx and Rx queues and the address filter list. */ 311 Tx and Rx queues and the address filter list. */
303 iowrite32(tp->csr0, ioaddr + CSR0); 312 iowrite32(tp->csr0, ioaddr + CSR0);
313 pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
304 udelay(100); 314 udelay(100);
305 315
306 if (tulip_debug > 1) 316 if (tulip_debug > 1)
@@ -522,20 +532,9 @@ static void tulip_tx_timeout(struct net_device *dev)
522 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n", 532 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
523 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12), 533 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
524 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15)); 534 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
525 if ( ! tp->medialock && tp->mtable) { 535 tp->timeout_recovery = 1;
526 do 536 schedule_work(&tp->media_work);
527 --tp->cur_index; 537 goto out_unlock;
528 while (tp->cur_index >= 0
529 && (tulip_media_cap[tp->mtable->mleaf[tp->cur_index].media]
530 & MediaIsFD));
531 if (--tp->cur_index < 0) {
532 /* We start again, but should instead look for default. */
533 tp->cur_index = tp->mtable->leafcount - 1;
534 }
535 tulip_select_media(dev, 0);
536 printk(KERN_WARNING "%s: transmit timed out, switching to %s "
537 "media.\n", dev->name, medianame[dev->if_port]);
538 }
539 } else if (tp->chip_id == PNIC2) { 538 } else if (tp->chip_id == PNIC2) {
540 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, " 539 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
541 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n", 540 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
@@ -575,14 +574,9 @@ static void tulip_tx_timeout(struct net_device *dev)
575 } 574 }
576#endif 575#endif
577 576
578 /* Stop and restart the chip's Tx processes . */ 577 tulip_tx_timeout_complete(tp, ioaddr);
579
580 tulip_restart_rxtx(tp);
581 /* Trigger an immediate transmit demand. */
582 iowrite32(0, ioaddr + CSR1);
583
584 tp->stats.tx_errors++;
585 578
579out_unlock:
586 spin_unlock_irqrestore (&tp->lock, flags); 580 spin_unlock_irqrestore (&tp->lock, flags);
587 dev->trans_start = jiffies; 581 dev->trans_start = jiffies;
588 netif_wake_queue (dev); 582 netif_wake_queue (dev);
@@ -732,6 +726,8 @@ static void tulip_down (struct net_device *dev)
732 void __iomem *ioaddr = tp->base_addr; 726 void __iomem *ioaddr = tp->base_addr;
733 unsigned long flags; 727 unsigned long flags;
734 728
729 flush_scheduled_work();
730
735 del_timer_sync (&tp->timer); 731 del_timer_sync (&tp->timer);
736#ifdef CONFIG_TULIP_NAPI 732#ifdef CONFIG_TULIP_NAPI
737 del_timer_sync (&tp->oom_timer); 733 del_timer_sync (&tp->oom_timer);
@@ -1361,11 +1357,8 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
1361 if (pci_request_regions (pdev, "tulip")) 1357 if (pci_request_regions (pdev, "tulip"))
1362 goto err_out_free_netdev; 1358 goto err_out_free_netdev;
1363 1359
1364#ifndef USE_IO_OPS 1360 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1365 ioaddr = pci_iomap(pdev, 1, tulip_tbl[chip_idx].io_size); 1361
1366#else
1367 ioaddr = pci_iomap(pdev, 0, tulip_tbl[chip_idx].io_size);
1368#endif
1369 if (!ioaddr) 1362 if (!ioaddr)
1370 goto err_out_free_res; 1363 goto err_out_free_res;
1371 1364
@@ -1398,6 +1391,8 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
1398 tp->timer.data = (unsigned long)dev; 1391 tp->timer.data = (unsigned long)dev;
1399 tp->timer.function = tulip_tbl[tp->chip_id].media_timer; 1392 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1400 1393
1394 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task, dev);
1395
1401 dev->base_addr = (unsigned long)ioaddr; 1396 dev->base_addr = (unsigned long)ioaddr;
1402 1397
1403#ifdef CONFIG_TULIP_MWI 1398#ifdef CONFIG_TULIP_MWI
@@ -1644,8 +1639,14 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
1644 if (register_netdev(dev)) 1639 if (register_netdev(dev))
1645 goto err_out_free_ring; 1640 goto err_out_free_ring;
1646 1641
1647 printk(KERN_INFO "%s: %s rev %d at %p,", 1642 printk(KERN_INFO "%s: %s rev %d at "
1648 dev->name, chip_name, chip_rev, ioaddr); 1643#ifdef CONFIG_TULIP_MMIO
1644 "MMIO"
1645#else
1646 "Port"
1647#endif
1648 " %#llx,", dev->name, chip_name, chip_rev,
1649 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1649 pci_set_drvdata(pdev, dev); 1650 pci_set_drvdata(pdev, dev);
1650 1651
1651 if (eeprom_missing) 1652 if (eeprom_missing)
@@ -1768,7 +1769,10 @@ static int tulip_resume(struct pci_dev *pdev)
1768 pci_set_power_state(pdev, PCI_D0); 1769 pci_set_power_state(pdev, PCI_D0);
1769 pci_restore_state(pdev); 1770 pci_restore_state(pdev);
1770 1771
1771 pci_enable_device(pdev); 1772 if ((retval = pci_enable_device(pdev))) {
1773 printk (KERN_ERR "tulip: pci_enable_device failed in resume\n");
1774 return retval;
1775 }
1772 1776
1773 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) { 1777 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1774 printk (KERN_ERR "tulip: request_irq failed in resume\n"); 1778 printk (KERN_ERR "tulip: request_irq failed in resume\n");
@@ -1849,7 +1853,7 @@ static int __init tulip_init (void)
1849 tulip_max_interrupt_work = max_interrupt_work; 1853 tulip_max_interrupt_work = max_interrupt_work;
1850 1854
1851 /* probe for and init boards */ 1855 /* probe for and init boards */
1852 return pci_module_init (&tulip_driver); 1856 return pci_register_driver(&tulip_driver);
1853} 1857}
1854 1858
1855 1859
diff --git a/drivers/net/tulip/uli526x.c b/drivers/net/tulip/uli526x.c
index fd64b2b3e99c..c4c720e2d4c3 100644
--- a/drivers/net/tulip/uli526x.c
+++ b/drivers/net/tulip/uli526x.c
@@ -1702,7 +1702,6 @@ MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8
1702 1702
1703static int __init uli526x_init_module(void) 1703static int __init uli526x_init_module(void)
1704{ 1704{
1705 int rc;
1706 1705
1707 printk(version); 1706 printk(version);
1708 printed_version = 1; 1707 printed_version = 1;
@@ -1714,22 +1713,19 @@ static int __init uli526x_init_module(void)
1714 if (cr6set) 1713 if (cr6set)
1715 uli526x_cr6_user_set = cr6set; 1714 uli526x_cr6_user_set = cr6set;
1716 1715
1717 switch(mode) { 1716 switch (mode) {
1718 case ULI526X_10MHF: 1717 case ULI526X_10MHF:
1719 case ULI526X_100MHF: 1718 case ULI526X_100MHF:
1720 case ULI526X_10MFD: 1719 case ULI526X_10MFD:
1721 case ULI526X_100MFD: 1720 case ULI526X_100MFD:
1722 uli526x_media_mode = mode; 1721 uli526x_media_mode = mode;
1723 break; 1722 break;
1724 default:uli526x_media_mode = ULI526X_AUTO; 1723 default:
1724 uli526x_media_mode = ULI526X_AUTO;
1725 break; 1725 break;
1726 } 1726 }
1727 1727
1728 rc = pci_module_init(&uli526x_driver); 1728 return pci_register_driver(&uli526x_driver);
1729 if (rc < 0)
1730 return rc;
1731
1732 return 0;
1733} 1729}
1734 1730
1735 1731
diff --git a/drivers/net/tulip/winbond-840.c b/drivers/net/tulip/winbond-840.c
index eba9083da146..a64d6828d9aa 100644
--- a/drivers/net/tulip/winbond-840.c
+++ b/drivers/net/tulip/winbond-840.c
@@ -90,10 +90,8 @@ static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
90 Making the Tx ring too large decreases the effectiveness of channel 90 Making the Tx ring too large decreases the effectiveness of channel
91 bonding and packet priority. 91 bonding and packet priority.
92 There are no ill effects from too-large receive rings. */ 92 There are no ill effects from too-large receive rings. */
93#define TX_RING_SIZE 16
94#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ 93#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
95#define TX_QUEUE_LEN_RESTART 5 94#define TX_QUEUE_LEN_RESTART 5
96#define RX_RING_SIZE 32
97 95
98#define TX_BUFLIMIT (1024-128) 96#define TX_BUFLIMIT (1024-128)
99 97
@@ -137,6 +135,8 @@ static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
137#include <asm/io.h> 135#include <asm/io.h>
138#include <asm/irq.h> 136#include <asm/irq.h>
139 137
138#include "tulip.h"
139
140/* These identify the driver base version and may not be removed. */ 140/* These identify the driver base version and may not be removed. */
141static char version[] = 141static char version[] =
142KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE " Donald Becker <becker@scyld.com>\n" 142KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
@@ -242,8 +242,8 @@ static const struct pci_id_info pci_id_tbl[] __devinitdata = {
242}; 242};
243 243
244/* This driver was written to use PCI memory space, however some x86 systems 244/* This driver was written to use PCI memory space, however some x86 systems
245 work only with I/O space accesses. Pass -DUSE_IO_OPS to use PCI I/O space 245 work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
246 accesses instead of memory space. */ 246*/
247 247
248/* Offsets to the Command and Status Registers, "CSRs". 248/* Offsets to the Command and Status Registers, "CSRs".
249 While similar to the Tulip, these registers are longword aligned. 249 While similar to the Tulip, these registers are longword aligned.
@@ -261,21 +261,11 @@ enum w840_offsets {
261 CurTxDescAddr=0x4C, CurTxBufAddr=0x50, 261 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
262}; 262};
263 263
264/* Bits in the interrupt status/enable registers. */
265/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
266enum intr_status_bits {
267 NormalIntr=0x10000, AbnormalIntr=0x8000,
268 IntrPCIErr=0x2000, TimerInt=0x800,
269 IntrRxDied=0x100, RxNoBuf=0x80, IntrRxDone=0x40,
270 TxFIFOUnderflow=0x20, RxErrIntr=0x10,
271 TxIdle=0x04, IntrTxStopped=0x02, IntrTxDone=0x01,
272};
273
274/* Bits in the NetworkConfig register. */ 264/* Bits in the NetworkConfig register. */
275enum rx_mode_bits { 265enum rx_mode_bits {
276 AcceptErr=0x80, AcceptRunt=0x40, 266 AcceptErr=0x80,
277 AcceptBroadcast=0x20, AcceptMulticast=0x10, 267 RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
278 AcceptAllPhys=0x08, AcceptMyPhys=0x02, 268 RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
279}; 269};
280 270
281enum mii_reg_bits { 271enum mii_reg_bits {
@@ -297,13 +287,6 @@ struct w840_tx_desc {
297 u32 buffer1, buffer2; 287 u32 buffer1, buffer2;
298}; 288};
299 289
300/* Bits in network_desc.status */
301enum desc_status_bits {
302 DescOwn=0x80000000, DescEndRing=0x02000000, DescUseLink=0x01000000,
303 DescWholePkt=0x60000000, DescStartPkt=0x20000000, DescEndPkt=0x40000000,
304 DescIntr=0x80000000,
305};
306
307#define MII_CNT 1 /* winbond only supports one MII */ 290#define MII_CNT 1 /* winbond only supports one MII */
308struct netdev_private { 291struct netdev_private {
309 struct w840_rx_desc *rx_ring; 292 struct w840_rx_desc *rx_ring;
@@ -371,7 +354,6 @@ static int __devinit w840_probe1 (struct pci_dev *pdev,
371 int irq; 354 int irq;
372 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; 355 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
373 void __iomem *ioaddr; 356 void __iomem *ioaddr;
374 int bar = 1;
375 357
376 i = pci_enable_device(pdev); 358 i = pci_enable_device(pdev);
377 if (i) return i; 359 if (i) return i;
@@ -393,10 +375,8 @@ static int __devinit w840_probe1 (struct pci_dev *pdev,
393 375
394 if (pci_request_regions(pdev, DRV_NAME)) 376 if (pci_request_regions(pdev, DRV_NAME))
395 goto err_out_netdev; 377 goto err_out_netdev;
396#ifdef USE_IO_OPS 378
397 bar = 0; 379 ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
398#endif
399 ioaddr = pci_iomap(pdev, bar, netdev_res_size);
400 if (!ioaddr) 380 if (!ioaddr)
401 goto err_out_free_res; 381 goto err_out_free_res;
402 382
@@ -838,7 +818,7 @@ static void init_rxtx_rings(struct net_device *dev)
838 np->rx_buf_sz,PCI_DMA_FROMDEVICE); 818 np->rx_buf_sz,PCI_DMA_FROMDEVICE);
839 819
840 np->rx_ring[i].buffer1 = np->rx_addr[i]; 820 np->rx_ring[i].buffer1 = np->rx_addr[i];
841 np->rx_ring[i].status = DescOwn; 821 np->rx_ring[i].status = DescOwned;
842 } 822 }
843 823
844 np->cur_rx = 0; 824 np->cur_rx = 0;
@@ -923,7 +903,7 @@ static void init_registers(struct net_device *dev)
923 } 903 }
924#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__) 904#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
925 i |= 0xE000; 905 i |= 0xE000;
926#elif defined(__sparc__) 906#elif defined(__sparc__) || defined (CONFIG_PARISC)
927 i |= 0x4800; 907 i |= 0x4800;
928#else 908#else
929#warning Processor architecture undefined 909#warning Processor architecture undefined
@@ -1043,11 +1023,11 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
1043 1023
1044 /* Now acquire the irq spinlock. 1024 /* Now acquire the irq spinlock.
1045 * The difficult race is the the ordering between 1025 * The difficult race is the the ordering between
1046 * increasing np->cur_tx and setting DescOwn: 1026 * increasing np->cur_tx and setting DescOwned:
1047 * - if np->cur_tx is increased first the interrupt 1027 * - if np->cur_tx is increased first the interrupt
1048 * handler could consider the packet as transmitted 1028 * handler could consider the packet as transmitted
1049 * since DescOwn is cleared. 1029 * since DescOwned is cleared.
1050 * - If DescOwn is set first the NIC could report the 1030 * - If DescOwned is set first the NIC could report the
1051 * packet as sent, but the interrupt handler would ignore it 1031 * packet as sent, but the interrupt handler would ignore it
1052 * since the np->cur_tx was not yet increased. 1032 * since the np->cur_tx was not yet increased.
1053 */ 1033 */
@@ -1055,7 +1035,7 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
1055 np->cur_tx++; 1035 np->cur_tx++;
1056 1036
1057 wmb(); /* flush length, buffer1, buffer2 */ 1037 wmb(); /* flush length, buffer1, buffer2 */
1058 np->tx_ring[entry].status = DescOwn; 1038 np->tx_ring[entry].status = DescOwned;
1059 wmb(); /* flush status and kick the hardware */ 1039 wmb(); /* flush status and kick the hardware */
1060 iowrite32(0, np->base_addr + TxStartDemand); 1040 iowrite32(0, np->base_addr + TxStartDemand);
1061 np->tx_q_bytes += skb->len; 1041 np->tx_q_bytes += skb->len;
@@ -1155,12 +1135,12 @@ static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs
1155 1135
1156 handled = 1; 1136 handled = 1;
1157 1137
1158 if (intr_status & (IntrRxDone | RxNoBuf)) 1138 if (intr_status & (RxIntr | RxNoBuf))
1159 netdev_rx(dev); 1139 netdev_rx(dev);
1160 if (intr_status & RxNoBuf) 1140 if (intr_status & RxNoBuf)
1161 iowrite32(0, ioaddr + RxStartDemand); 1141 iowrite32(0, ioaddr + RxStartDemand);
1162 1142
1163 if (intr_status & (TxIdle | IntrTxDone) && 1143 if (intr_status & (TxNoBuf | TxIntr) &&
1164 np->cur_tx != np->dirty_tx) { 1144 np->cur_tx != np->dirty_tx) {
1165 spin_lock(&np->lock); 1145 spin_lock(&np->lock);
1166 netdev_tx_done(dev); 1146 netdev_tx_done(dev);
@@ -1168,8 +1148,8 @@ static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs
1168 } 1148 }
1169 1149
1170 /* Abnormal error summary/uncommon events handlers. */ 1150 /* Abnormal error summary/uncommon events handlers. */
1171 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | IntrPCIErr | 1151 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SytemError |
1172 TimerInt | IntrTxStopped)) 1152 TimerInt | TxDied))
1173 netdev_error(dev, intr_status); 1153 netdev_error(dev, intr_status);
1174 1154
1175 if (--work_limit < 0) { 1155 if (--work_limit < 0) {
@@ -1305,7 +1285,7 @@ static int netdev_rx(struct net_device *dev)
1305 np->rx_ring[entry].buffer1 = np->rx_addr[entry]; 1285 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1306 } 1286 }
1307 wmb(); 1287 wmb();
1308 np->rx_ring[entry].status = DescOwn; 1288 np->rx_ring[entry].status = DescOwned;
1309 } 1289 }
1310 1290
1311 return 0; 1291 return 0;
@@ -1342,7 +1322,7 @@ static void netdev_error(struct net_device *dev, int intr_status)
1342 dev->name, new); 1322 dev->name, new);
1343 update_csr6(dev, new); 1323 update_csr6(dev, new);
1344 } 1324 }
1345 if (intr_status & IntrRxDied) { /* Missed a Rx frame. */ 1325 if (intr_status & RxDied) { /* Missed a Rx frame. */
1346 np->stats.rx_errors++; 1326 np->stats.rx_errors++;
1347 } 1327 }
1348 if (intr_status & TimerInt) { 1328 if (intr_status & TimerInt) {
@@ -1381,13 +1361,13 @@ static u32 __set_rx_mode(struct net_device *dev)
1381 /* Unconditionally log net taps. */ 1361 /* Unconditionally log net taps. */
1382 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); 1362 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1383 memset(mc_filter, 0xff, sizeof(mc_filter)); 1363 memset(mc_filter, 0xff, sizeof(mc_filter));
1384 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAllPhys 1364 rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
1385 | AcceptMyPhys; 1365 | AcceptMyPhys;
1386 } else if ((dev->mc_count > multicast_filter_limit) 1366 } else if ((dev->mc_count > multicast_filter_limit)
1387 || (dev->flags & IFF_ALLMULTI)) { 1367 || (dev->flags & IFF_ALLMULTI)) {
1388 /* Too many to match, or accept all multicasts. */ 1368 /* Too many to match, or accept all multicasts. */
1389 memset(mc_filter, 0xff, sizeof(mc_filter)); 1369 memset(mc_filter, 0xff, sizeof(mc_filter));
1390 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 1370 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1391 } else { 1371 } else {
1392 struct dev_mc_list *mclist; 1372 struct dev_mc_list *mclist;
1393 int i; 1373 int i;
@@ -1398,7 +1378,7 @@ static u32 __set_rx_mode(struct net_device *dev)
1398 filterbit &= 0x3f; 1378 filterbit &= 0x3f;
1399 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31); 1379 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1400 } 1380 }
1401 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 1381 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1402 } 1382 }
1403 iowrite32(mc_filter[0], ioaddr + MulticastFilter0); 1383 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1404 iowrite32(mc_filter[1], ioaddr + MulticastFilter1); 1384 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
@@ -1646,14 +1626,18 @@ static int w840_resume (struct pci_dev *pdev)
1646{ 1626{
1647 struct net_device *dev = pci_get_drvdata (pdev); 1627 struct net_device *dev = pci_get_drvdata (pdev);
1648 struct netdev_private *np = netdev_priv(dev); 1628 struct netdev_private *np = netdev_priv(dev);
1629 int retval = 0;
1649 1630
1650 rtnl_lock(); 1631 rtnl_lock();
1651 if (netif_device_present(dev)) 1632 if (netif_device_present(dev))
1652 goto out; /* device not suspended */ 1633 goto out; /* device not suspended */
1653 if (netif_running(dev)) { 1634 if (netif_running(dev)) {
1654 pci_enable_device(pdev); 1635 if ((retval = pci_enable_device(pdev))) {
1655 /* pci_power_on(pdev); */ 1636 printk (KERN_ERR
1656 1637 "%s: pci_enable_device failed in resume\n",
1638 dev->name);
1639 goto out;
1640 }
1657 spin_lock_irq(&np->lock); 1641 spin_lock_irq(&np->lock);
1658 iowrite32(1, np->base_addr+PCIBusCfg); 1642 iowrite32(1, np->base_addr+PCIBusCfg);
1659 ioread32(np->base_addr+PCIBusCfg); 1643 ioread32(np->base_addr+PCIBusCfg);
@@ -1671,7 +1655,7 @@ static int w840_resume (struct pci_dev *pdev)
1671 } 1655 }
1672out: 1656out:
1673 rtnl_unlock(); 1657 rtnl_unlock();
1674 return 0; 1658 return retval;
1675} 1659}
1676#endif 1660#endif
1677 1661
@@ -1689,7 +1673,7 @@ static struct pci_driver w840_driver = {
1689static int __init w840_init(void) 1673static int __init w840_init(void)
1690{ 1674{
1691 printk(version); 1675 printk(version);
1692 return pci_module_init(&w840_driver); 1676 return pci_register_driver(&w840_driver);
1693} 1677}
1694 1678
1695static void __exit w840_exit(void) 1679static void __exit w840_exit(void)
diff --git a/drivers/net/tulip/xircom_tulip_cb.c b/drivers/net/tulip/xircom_tulip_cb.c
index 17ca7dc42e6f..d797b7b2e35f 100644
--- a/drivers/net/tulip/xircom_tulip_cb.c
+++ b/drivers/net/tulip/xircom_tulip_cb.c
@@ -1707,7 +1707,7 @@ static int __init xircom_init(void)
1707#ifdef MODULE 1707#ifdef MODULE
1708 printk(version); 1708 printk(version);
1709#endif 1709#endif
1710 return pci_module_init(&xircom_driver); 1710 return pci_register_driver(&xircom_driver);
1711} 1711}
1712 1712
1713 1713
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c
index 4103c37172f9..1014461178cc 100644
--- a/drivers/net/typhoon.c
+++ b/drivers/net/typhoon.c
@@ -2660,7 +2660,7 @@ static struct pci_driver typhoon_driver = {
2660static int __init 2660static int __init
2661typhoon_init(void) 2661typhoon_init(void)
2662{ 2662{
2663 return pci_module_init(&typhoon_driver); 2663 return pci_register_driver(&typhoon_driver);
2664} 2664}
2665 2665
2666static void __exit 2666static void __exit
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c
index ae971080e2e4..efeb10b9c61b 100644
--- a/drivers/net/via-rhine.c
+++ b/drivers/net/via-rhine.c
@@ -2005,7 +2005,7 @@ static int __init rhine_init(void)
2005#ifdef MODULE 2005#ifdef MODULE
2006 printk(version); 2006 printk(version);
2007#endif 2007#endif
2008 return pci_module_init(&rhine_driver); 2008 return pci_register_driver(&rhine_driver);
2009} 2009}
2010 2010
2011 2011
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c
index aa9cd92f46b2..e266db1518e7 100644
--- a/drivers/net/via-velocity.c
+++ b/drivers/net/via-velocity.c
@@ -2250,7 +2250,7 @@ static int __init velocity_init_module(void)
2250 int ret; 2250 int ret;
2251 2251
2252 velocity_register_notifier(); 2252 velocity_register_notifier();
2253 ret = pci_module_init(&velocity_driver); 2253 ret = pci_register_driver(&velocity_driver);
2254 if (ret < 0) 2254 if (ret < 0)
2255 velocity_unregister_notifier(); 2255 velocity_unregister_notifier();
2256 return ret; 2256 return ret;
diff --git a/drivers/net/via-velocity.h b/drivers/net/via-velocity.h
index 496c3d597444..4665ef2c63df 100644
--- a/drivers/net/via-velocity.h
+++ b/drivers/net/via-velocity.h
@@ -262,25 +262,6 @@ struct velocity_rd_info {
262 dma_addr_t skb_dma; 262 dma_addr_t skb_dma;
263}; 263};
264 264
265/**
266 * alloc_rd_info - allocate an rd info block
267 *
268 * Alocate and initialize a receive info structure used for keeping
269 * track of kernel side information related to each receive
270 * descriptor we are using
271 */
272
273static inline struct velocity_rd_info *alloc_rd_info(void)
274{
275 struct velocity_rd_info *ptr;
276 if ((ptr = kmalloc(sizeof(struct velocity_rd_info), GFP_ATOMIC)) == NULL)
277 return NULL;
278 else {
279 memset(ptr, 0, sizeof(struct velocity_rd_info));
280 return ptr;
281 }
282}
283
284/* 265/*
285 * Used to track transmit side buffers. 266 * Used to track transmit side buffers.
286 */ 267 */
diff --git a/drivers/net/wan/cycx_main.c b/drivers/net/wan/cycx_main.c
index 430b1f630fb4..a5e7ce1bd16a 100644
--- a/drivers/net/wan/cycx_main.c
+++ b/drivers/net/wan/cycx_main.c
@@ -40,7 +40,6 @@
40* 1998/08/08 acme Initial version. 40* 1998/08/08 acme Initial version.
41*/ 41*/
42 42
43#include <linux/config.h> /* OS configuration options */
44#include <linux/stddef.h> /* offsetof(), etc. */ 43#include <linux/stddef.h> /* offsetof(), etc. */
45#include <linux/errno.h> /* return codes */ 44#include <linux/errno.h> /* return codes */
46#include <linux/string.h> /* inline memset(), etc. */ 45#include <linux/string.h> /* inline memset(), etc. */
diff --git a/drivers/net/wan/dlci.c b/drivers/net/wan/dlci.c
index 6e1ec5bf22fc..736987559432 100644
--- a/drivers/net/wan/dlci.c
+++ b/drivers/net/wan/dlci.c
@@ -28,7 +28,6 @@
28 * 2 of the License, or (at your option) any later version. 28 * 2 of the License, or (at your option) any later version.
29 */ 29 */
30 30
31#include <linux/config.h> /* for CONFIG_DLCI_COUNT */
32#include <linux/module.h> 31#include <linux/module.h>
33#include <linux/kernel.h> 32#include <linux/kernel.h>
34#include <linux/types.h> 33#include <linux/types.h>
diff --git a/drivers/net/wan/dscc4.c b/drivers/net/wan/dscc4.c
index 684af4316ffd..af4d4155905b 100644
--- a/drivers/net/wan/dscc4.c
+++ b/drivers/net/wan/dscc4.c
@@ -2062,7 +2062,7 @@ static struct pci_driver dscc4_driver = {
2062 2062
2063static int __init dscc4_init_module(void) 2063static int __init dscc4_init_module(void)
2064{ 2064{
2065 return pci_module_init(&dscc4_driver); 2065 return pci_register_driver(&dscc4_driver);
2066} 2066}
2067 2067
2068static void __exit dscc4_cleanup_module(void) 2068static void __exit dscc4_cleanup_module(void)
diff --git a/drivers/net/wan/farsync.c b/drivers/net/wan/farsync.c
index 3705db04a343..564351aafa41 100644
--- a/drivers/net/wan/farsync.c
+++ b/drivers/net/wan/farsync.c
@@ -2697,7 +2697,7 @@ fst_init(void)
2697 for (i = 0; i < FST_MAX_CARDS; i++) 2697 for (i = 0; i < FST_MAX_CARDS; i++)
2698 fst_card_array[i] = NULL; 2698 fst_card_array[i] = NULL;
2699 spin_lock_init(&fst_work_q_lock); 2699 spin_lock_init(&fst_work_q_lock);
2700 return pci_module_init(&fst_driver); 2700 return pci_register_driver(&fst_driver);
2701} 2701}
2702 2702
2703static void __exit 2703static void __exit
diff --git a/drivers/net/wan/lmc/lmc_main.c b/drivers/net/wan/lmc/lmc_main.c
index 39f44241a728..7b5d81deb028 100644
--- a/drivers/net/wan/lmc/lmc_main.c
+++ b/drivers/net/wan/lmc/lmc_main.c
@@ -1790,7 +1790,7 @@ static struct pci_driver lmc_driver = {
1790 1790
1791static int __init init_lmc(void) 1791static int __init init_lmc(void)
1792{ 1792{
1793 return pci_module_init(&lmc_driver); 1793 return pci_register_driver(&lmc_driver);
1794} 1794}
1795 1795
1796static void __exit exit_lmc(void) 1796static void __exit exit_lmc(void)
diff --git a/drivers/net/wan/pc300_drv.c b/drivers/net/wan/pc300_drv.c
index 567effff4a3e..56e69403d178 100644
--- a/drivers/net/wan/pc300_drv.c
+++ b/drivers/net/wan/pc300_drv.c
@@ -3677,7 +3677,7 @@ static struct pci_driver cpc_driver = {
3677 3677
3678static int __init cpc_init(void) 3678static int __init cpc_init(void)
3679{ 3679{
3680 return pci_module_init(&cpc_driver); 3680 return pci_register_driver(&cpc_driver);
3681} 3681}
3682 3682
3683static void __exit cpc_cleanup_module(void) 3683static void __exit cpc_cleanup_module(void)
diff --git a/drivers/net/wan/pci200syn.c b/drivers/net/wan/pci200syn.c
index 4df61fa3214b..a6b9c33b68e4 100644
--- a/drivers/net/wan/pci200syn.c
+++ b/drivers/net/wan/pci200syn.c
@@ -476,7 +476,7 @@ static int __init pci200_init_module(void)
476 printk(KERN_ERR "pci200syn: Invalid PCI clock frequency\n"); 476 printk(KERN_ERR "pci200syn: Invalid PCI clock frequency\n");
477 return -EINVAL; 477 return -EINVAL;
478 } 478 }
479 return pci_module_init(&pci200_pci_driver); 479 return pci_register_driver(&pci200_pci_driver);
480} 480}
481 481
482 482
diff --git a/drivers/net/wan/sdla.c b/drivers/net/wan/sdla.c
index 7628c2d81f45..0ba018f8382b 100644
--- a/drivers/net/wan/sdla.c
+++ b/drivers/net/wan/sdla.c
@@ -32,7 +32,6 @@
32 * 2 of the License, or (at your option) any later version. 32 * 2 of the License, or (at your option) any later version.
33 */ 33 */
34 34
35#include <linux/config.h> /* for CONFIG_DLCI_MAX */
36#include <linux/module.h> 35#include <linux/module.h>
37#include <linux/kernel.h> 36#include <linux/kernel.h>
38#include <linux/types.h> 37#include <linux/types.h>
diff --git a/drivers/net/wan/wanxl.c b/drivers/net/wan/wanxl.c
index b2031dfc4bb1..ec68f7dfd93f 100644
--- a/drivers/net/wan/wanxl.c
+++ b/drivers/net/wan/wanxl.c
@@ -837,7 +837,7 @@ static int __init wanxl_init_module(void)
837#ifdef MODULE 837#ifdef MODULE
838 printk(KERN_INFO "%s\n", version); 838 printk(KERN_INFO "%s\n", version);
839#endif 839#endif
840 return pci_module_init(&wanxl_pci_driver); 840 return pci_register_driver(&wanxl_pci_driver);
841} 841}
842 842
843static void __exit wanxl_cleanup_module(void) 843static void __exit wanxl_cleanup_module(void)
diff --git a/drivers/net/wireless/atmel_pci.c b/drivers/net/wireless/atmel_pci.c
index d425c3cefded..3bfa791c323d 100644
--- a/drivers/net/wireless/atmel_pci.c
+++ b/drivers/net/wireless/atmel_pci.c
@@ -76,7 +76,7 @@ static void __devexit atmel_pci_remove(struct pci_dev *pdev)
76 76
77static int __init atmel_init_module(void) 77static int __init atmel_init_module(void)
78{ 78{
79 return pci_module_init(&atmel_driver); 79 return pci_register_driver(&atmel_driver);
80} 80}
81 81
82static void __exit atmel_cleanup_module(void) 82static void __exit atmel_cleanup_module(void)
diff --git a/drivers/net/wireless/ipw2100.c b/drivers/net/wireless/ipw2100.c
index 5d5dab6a209c..d2db8eb412c1 100644
--- a/drivers/net/wireless/ipw2100.c
+++ b/drivers/net/wireless/ipw2100.c
@@ -6532,7 +6532,7 @@ static int __init ipw2100_init(void)
6532 printk(KERN_INFO DRV_NAME ": %s, %s\n", DRV_DESCRIPTION, DRV_VERSION); 6532 printk(KERN_INFO DRV_NAME ": %s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
6533 printk(KERN_INFO DRV_NAME ": %s\n", DRV_COPYRIGHT); 6533 printk(KERN_INFO DRV_NAME ": %s\n", DRV_COPYRIGHT);
6534 6534
6535 ret = pci_module_init(&ipw2100_pci_driver); 6535 ret = pci_register_driver(&ipw2100_pci_driver);
6536 6536
6537#ifdef CONFIG_IPW2100_DEBUG 6537#ifdef CONFIG_IPW2100_DEBUG
6538 ipw2100_debug_level = debug; 6538 ipw2100_debug_level = debug;
diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c
index fa245f126c84..f29ec0ebed2f 100644
--- a/drivers/net/wireless/ipw2200.c
+++ b/drivers/net/wireless/ipw2200.c
@@ -11788,7 +11788,7 @@ static int __init ipw_init(void)
11788 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); 11788 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
11789 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); 11789 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
11790 11790
11791 ret = pci_module_init(&ipw_driver); 11791 ret = pci_register_driver(&ipw_driver);
11792 if (ret) { 11792 if (ret) {
11793 IPW_ERROR("Unable to initialize PCI module\n"); 11793 IPW_ERROR("Unable to initialize PCI module\n");
11794 return ret; 11794 return ret;
diff --git a/drivers/net/wireless/orinoco_nortel.c b/drivers/net/wireless/orinoco_nortel.c
index bf05b907747e..eaf3d13b851c 100644
--- a/drivers/net/wireless/orinoco_nortel.c
+++ b/drivers/net/wireless/orinoco_nortel.c
@@ -304,7 +304,7 @@ MODULE_LICENSE("Dual MPL/GPL");
304static int __init orinoco_nortel_init(void) 304static int __init orinoco_nortel_init(void)
305{ 305{
306 printk(KERN_DEBUG "%s\n", version); 306 printk(KERN_DEBUG "%s\n", version);
307 return pci_module_init(&orinoco_nortel_driver); 307 return pci_register_driver(&orinoco_nortel_driver);
308} 308}
309 309
310static void __exit orinoco_nortel_exit(void) 310static void __exit orinoco_nortel_exit(void)
diff --git a/drivers/net/wireless/orinoco_pci.c b/drivers/net/wireless/orinoco_pci.c
index 1759c543fbee..97a8b4ff32bd 100644
--- a/drivers/net/wireless/orinoco_pci.c
+++ b/drivers/net/wireless/orinoco_pci.c
@@ -244,7 +244,7 @@ MODULE_LICENSE("Dual MPL/GPL");
244static int __init orinoco_pci_init(void) 244static int __init orinoco_pci_init(void)
245{ 245{
246 printk(KERN_DEBUG "%s\n", version); 246 printk(KERN_DEBUG "%s\n", version);
247 return pci_module_init(&orinoco_pci_driver); 247 return pci_register_driver(&orinoco_pci_driver);
248} 248}
249 249
250static void __exit orinoco_pci_exit(void) 250static void __exit orinoco_pci_exit(void)
diff --git a/drivers/net/wireless/orinoco_plx.c b/drivers/net/wireless/orinoco_plx.c
index 7f006f624171..31162ac25a92 100644
--- a/drivers/net/wireless/orinoco_plx.c
+++ b/drivers/net/wireless/orinoco_plx.c
@@ -351,7 +351,7 @@ MODULE_LICENSE("Dual MPL/GPL");
351static int __init orinoco_plx_init(void) 351static int __init orinoco_plx_init(void)
352{ 352{
353 printk(KERN_DEBUG "%s\n", version); 353 printk(KERN_DEBUG "%s\n", version);
354 return pci_module_init(&orinoco_plx_driver); 354 return pci_register_driver(&orinoco_plx_driver);
355} 355}
356 356
357static void __exit orinoco_plx_exit(void) 357static void __exit orinoco_plx_exit(void)
diff --git a/drivers/net/wireless/orinoco_tmd.c b/drivers/net/wireless/orinoco_tmd.c
index 0831721e4d6c..7c7b960c91df 100644
--- a/drivers/net/wireless/orinoco_tmd.c
+++ b/drivers/net/wireless/orinoco_tmd.c
@@ -228,7 +228,7 @@ MODULE_LICENSE("Dual MPL/GPL");
228static int __init orinoco_tmd_init(void) 228static int __init orinoco_tmd_init(void)
229{ 229{
230 printk(KERN_DEBUG "%s\n", version); 230 printk(KERN_DEBUG "%s\n", version);
231 return pci_module_init(&orinoco_tmd_driver); 231 return pci_register_driver(&orinoco_tmd_driver);
232} 232}
233 233
234static void __exit orinoco_tmd_exit(void) 234static void __exit orinoco_tmd_exit(void)
diff --git a/drivers/net/wireless/prism54/islpci_hotplug.c b/drivers/net/wireless/prism54/islpci_hotplug.c
index 09fc17a0f029..f692dccf0d07 100644
--- a/drivers/net/wireless/prism54/islpci_hotplug.c
+++ b/drivers/net/wireless/prism54/islpci_hotplug.c
@@ -313,7 +313,7 @@ prism54_module_init(void)
313 313
314 __bug_on_wrong_struct_sizes (); 314 __bug_on_wrong_struct_sizes ();
315 315
316 return pci_module_init(&prism54_driver); 316 return pci_register_driver(&prism54_driver);
317} 317}
318 318
319/* by the time prism54_module_exit() terminates, as a postcondition 319/* by the time prism54_module_exit() terminates, as a postcondition
diff --git a/drivers/net/yellowfin.c b/drivers/net/yellowfin.c
index 8459a18254a4..b6b247433709 100644
--- a/drivers/net/yellowfin.c
+++ b/drivers/net/yellowfin.c
@@ -1434,7 +1434,7 @@ static int __init yellowfin_init (void)
1434#ifdef MODULE 1434#ifdef MODULE
1435 printk(version); 1435 printk(version);
1436#endif 1436#endif
1437 return pci_module_init (&yellowfin_driver); 1437 return pci_register_driver(&yellowfin_driver);
1438} 1438}
1439 1439
1440 1440
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 06:24:00 -0500