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-rw-r--r--drivers/net/sky2.c40
-rw-r--r--drivers/net/sky2.h7
2 files changed, 45 insertions, 2 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index ad35674ba838..59cb9cd00ad2 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -641,11 +641,47 @@ static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
641static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 641static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
642{ 642{
643 u32 reg1; 643 u32 reg1;
644 u16 ctrl;
645
646 /* release GPHY Control reset */
647 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
648
649 /* release GMAC reset */
650 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
651
652 if (hw->flags & SKY2_HW_NEWER_PHY) {
653 /* select page 2 to access MAC control register */
654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
655
656 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
657 /* allow GMII Power Down */
658 ctrl &= ~PHY_M_MAC_GMIF_PUP;
659 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
660
661 /* set page register back to 0 */
662 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
663 }
664
665 /* setup General Purpose Control Register */
666 gma_write16(hw, port, GM_GP_CTRL,
667 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
668
669 if (hw->chip_id != CHIP_ID_YUKON_EC) {
670 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672
673 /* enable Power Down */
674 ctrl |= PHY_M_PC_POW_D_ENA;
675 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
676 }
677
678 /* set IEEE compatible Power Down Mode (dev. #4.99) */
679 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
680 }
644 681
645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 682 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
646 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 683 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
647 reg1 |= phy_power[port]; 684 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
648
649 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 685 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
650 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 686 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
651} 687}
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index c0a5eea20007..d63106cd74ba 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -1143,6 +1143,12 @@ enum {
1143 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ 1143 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1144}; 1144};
1145 1145
1146/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1147enum {
1148 PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */
1149 PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */
1150};
1151
1146/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1152/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1147enum { 1153enum {
1148 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ 1154 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
@@ -1411,6 +1417,7 @@ enum {
1411/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1417/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1412enum { 1418enum {
1413 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ 1419 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1420 PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */
1414 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ 1421 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1415 PHY_M_MAC_MD_COPPER = 5,/* Copper only */ 1422 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1416 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ 1423 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */