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-rw-r--r--drivers/net/3c523.c1
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/b44.c3
-rw-r--r--drivers/net/cs89x0.c40
-rw-r--r--drivers/net/cs89x0.h2
-rw-r--r--drivers/net/e100.c25
-rw-r--r--drivers/net/e1000/e1000.h4
-rw-r--r--drivers/net/e1000/e1000_ethtool.c131
-rw-r--r--drivers/net/e1000/e1000_hw.c23
-rw-r--r--drivers/net/e1000/e1000_hw.h1
-rw-r--r--drivers/net/e1000/e1000_main.c111
-rw-r--r--drivers/net/forcedeth.c53
-rw-r--r--drivers/net/gianfar.c652
-rw-r--r--drivers/net/gianfar.h363
-rw-r--r--drivers/net/gianfar_ethtool.c277
-rw-r--r--drivers/net/pcnet32.c2
-rw-r--r--drivers/net/sb1000.c14
-rw-r--r--drivers/net/skfp/Makefile4
-rw-r--r--drivers/net/skfp/drvfbi.c222
-rw-r--r--drivers/net/skfp/ess.c4
-rw-r--r--drivers/net/skfp/fplustm.c70
-rw-r--r--drivers/net/skfp/h/cmtdef.h7
-rw-r--r--drivers/net/skfp/h/hwmtm.h25
-rw-r--r--drivers/net/skfp/hwmtm.c34
-rw-r--r--drivers/net/skfp/pcmplc.c7
-rw-r--r--drivers/net/skfp/pmf.c11
-rw-r--r--drivers/net/skfp/skfddi.c1
-rw-r--r--drivers/net/skfp/smt.c46
-rw-r--r--drivers/net/skfp/smtdef.c5
-rw-r--r--drivers/net/skfp/smtparse.c467
-rw-r--r--drivers/net/skge.c1710
-rw-r--r--drivers/net/skge.h586
-rw-r--r--drivers/net/smc91x.c43
-rw-r--r--drivers/net/tokenring/lanstreamer.c6
-rw-r--r--drivers/net/tulip/tulip_core.c44
-rw-r--r--drivers/net/via-rhine.c6
-rw-r--r--drivers/net/wan/farsync.c1
-rw-r--r--drivers/net/wireless/airo.c2
-rw-r--r--drivers/net/wireless/orinoco.c2465
-rw-r--r--drivers/net/wireless/orinoco.h30
-rw-r--r--drivers/net/wireless/prism54/isl_38xx.c6
41 files changed, 3686 insertions, 3820 deletions
diff --git a/drivers/net/3c523.c b/drivers/net/3c523.c
index 1247a25f1093..9e1fe2e0478c 100644
--- a/drivers/net/3c523.c
+++ b/drivers/net/3c523.c
@@ -1274,6 +1274,7 @@ module_param_array(irq, int, NULL, 0);
1274module_param_array(io, int, NULL, 0); 1274module_param_array(io, int, NULL, 0);
1275MODULE_PARM_DESC(io, "EtherLink/MC I/O base address(es)"); 1275MODULE_PARM_DESC(io, "EtherLink/MC I/O base address(es)");
1276MODULE_PARM_DESC(irq, "EtherLink/MC IRQ number(s)"); 1276MODULE_PARM_DESC(irq, "EtherLink/MC IRQ number(s)");
1277MODULE_LICENSE("GPL");
1277 1278
1278int init_module(void) 1279int init_module(void)
1279{ 1280{
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 47e158fa5aac..2b55687f6ee9 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1320,7 +1320,7 @@ config FORCEDETH
1320 1320
1321config CS89x0 1321config CS89x0
1322 tristate "CS89x0 support" 1322 tristate "CS89x0 support"
1323 depends on NET_PCI && (ISA || ARCH_IXDP2X01) 1323 depends on (NET_PCI && (ISA || ARCH_IXDP2X01)) || ARCH_PNX0105
1324 ---help--- 1324 ---help---
1325 Support for CS89x0 chipset based Ethernet cards. If you have a 1325 Support for CS89x0 chipset based Ethernet cards. If you have a
1326 network (Ethernet) card of this type, say Y and read the 1326 network (Ethernet) card of this type, say Y and read the
diff --git a/drivers/net/b44.c b/drivers/net/b44.c
index 3fe8ba992c38..f1bd45e3da31 100644
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -1285,6 +1285,9 @@ static int b44_open(struct net_device *dev)
1285 b44_init_hw(bp); 1285 b44_init_hw(bp);
1286 bp->flags |= B44_FLAG_INIT_COMPLETE; 1286 bp->flags |= B44_FLAG_INIT_COMPLETE;
1287 1287
1288 netif_carrier_off(dev);
1289 b44_check_phy(bp);
1290
1288 spin_unlock_irq(&bp->lock); 1291 spin_unlock_irq(&bp->lock);
1289 1292
1290 init_timer(&bp->timer); 1293 init_timer(&bp->timer);
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index 25e4495de79e..b96d6fb1929e 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -174,6 +174,13 @@ static unsigned int cs8900_irq_map[] = {1,0,0,0};
174#include <asm/irq.h> 174#include <asm/irq.h>
175static unsigned int netcard_portlist[] __initdata = {IXDP2X01_CS8900_VIRT_BASE, 0}; 175static unsigned int netcard_portlist[] __initdata = {IXDP2X01_CS8900_VIRT_BASE, 0};
176static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0}; 176static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0};
177#elif defined(CONFIG_ARCH_PNX0105)
178#include <asm/irq.h>
179#include <asm/arch/gpio.h>
180#define CIRRUS_DEFAULT_BASE IO_ADDRESS(EXT_STATIC2_s0_BASE + 0x200000) /* = Physical address 0x48200000 */
181#define CIRRUS_DEFAULT_IRQ VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */
182static unsigned int netcard_portlist[] __initdata = {CIRRUS_DEFAULT_BASE, 0};
183static unsigned int cs8900_irq_map[] = {CIRRUS_DEFAULT_IRQ, 0, 0, 0};
177#else 184#else
178static unsigned int netcard_portlist[] __initdata = 185static unsigned int netcard_portlist[] __initdata =
179 { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; 186 { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0};
@@ -431,6 +438,30 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
431#endif 438#endif
432 } 439 }
433 440
441#ifdef CONFIG_ARCH_PNX0105
442 initialize_ebi();
443
444 /* Map GPIO registers for the pins connected to the CS8900a. */
445 if (map_cirrus_gpio() < 0)
446 return -ENODEV;
447
448 reset_cirrus();
449
450 /* Map event-router registers. */
451 if (map_event_router() < 0)
452 return -ENODEV;
453
454 enable_cirrus_irq();
455
456 unmap_cirrus_gpio();
457 unmap_event_router();
458
459 dev->base_addr = ioaddr;
460
461 for (i = 0 ; i < 3 ; i++)
462 readreg(dev, 0);
463#endif
464
434 /* Grab the region so we can find another board if autoIRQ fails. */ 465 /* Grab the region so we can find another board if autoIRQ fails. */
435 /* WTF is going on here? */ 466 /* WTF is going on here? */
436 if (!request_region(ioaddr & ~3, NETCARD_IO_EXTENT, DRV_NAME)) { 467 if (!request_region(ioaddr & ~3, NETCARD_IO_EXTENT, DRV_NAME)) {
@@ -672,7 +703,7 @@ printk("PP_addr=0x%x\n", inw(ioaddr + ADD_PORT));
672 } else { 703 } else {
673 i = lp->isa_config & INT_NO_MASK; 704 i = lp->isa_config & INT_NO_MASK;
674 if (lp->chip_type == CS8900) { 705 if (lp->chip_type == CS8900) {
675#ifdef CONFIG_ARCH_IXDP2X01 706#if defined(CONFIG_ARCH_IXDP2X01) || defined(CONFIG_ARCH_PNX0105)
676 i = cs8900_irq_map[0]; 707 i = cs8900_irq_map[0];
677#else 708#else
678 /* Translate the IRQ using the IRQ mapping table. */ 709 /* Translate the IRQ using the IRQ mapping table. */
@@ -1145,7 +1176,7 @@ net_open(struct net_device *dev)
1145 int i; 1176 int i;
1146 int ret; 1177 int ret;
1147 1178
1148#ifndef CONFIG_SH_HICOSH4 /* uses irq#1, so this won't work */ 1179#if !defined(CONFIG_SH_HICOSH4) && !defined(CONFIG_ARCH_PNX0105) /* uses irq#1, so this won't work */
1149 if (dev->irq < 2) { 1180 if (dev->irq < 2) {
1150 /* Allow interrupts to be generated by the chip */ 1181 /* Allow interrupts to be generated by the chip */
1151/* Cirrus' release had this: */ 1182/* Cirrus' release had this: */
@@ -1176,7 +1207,7 @@ net_open(struct net_device *dev)
1176 else 1207 else
1177#endif 1208#endif
1178 { 1209 {
1179#ifndef CONFIG_ARCH_IXDP2X01 1210#if !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_ARCH_PNX0105)
1180 if (((1 << dev->irq) & lp->irq_map) == 0) { 1211 if (((1 << dev->irq) & lp->irq_map) == 0) {
1181 printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n", 1212 printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n",
1182 dev->name, dev->irq, lp->irq_map); 1213 dev->name, dev->irq, lp->irq_map);
@@ -1261,6 +1292,9 @@ net_open(struct net_device *dev)
1261 case A_CNF_MEDIA_10B_2: result = lp->adapter_cnf & A_CNF_10B_2; break; 1292 case A_CNF_MEDIA_10B_2: result = lp->adapter_cnf & A_CNF_10B_2; break;
1262 default: result = lp->adapter_cnf & (A_CNF_10B_T | A_CNF_AUI | A_CNF_10B_2); 1293 default: result = lp->adapter_cnf & (A_CNF_10B_T | A_CNF_AUI | A_CNF_10B_2);
1263 } 1294 }
1295#ifdef CONFIG_ARCH_PNX0105
1296 result = A_CNF_10B_T;
1297#endif
1264 if (!result) { 1298 if (!result) {
1265 printk(KERN_ERR "%s: EEPROM is configured for unavailable media\n", dev->name); 1299 printk(KERN_ERR "%s: EEPROM is configured for unavailable media\n", dev->name);
1266 release_irq: 1300 release_irq:
diff --git a/drivers/net/cs89x0.h b/drivers/net/cs89x0.h
index b0ef7ad2baad..bd3ad8e6cce9 100644
--- a/drivers/net/cs89x0.h
+++ b/drivers/net/cs89x0.h
@@ -16,7 +16,7 @@
16 16
17#include <linux/config.h> 17#include <linux/config.h>
18 18
19#ifdef CONFIG_ARCH_IXDP2X01 19#if defined(CONFIG_ARCH_IXDP2X01) || defined(CONFIG_ARCH_PNX0105)
20/* IXDP2401/IXDP2801 uses dword-aligned register addressing */ 20/* IXDP2401/IXDP2801 uses dword-aligned register addressing */
21#define CS89x0_PORT(reg) ((reg) * 2) 21#define CS89x0_PORT(reg) ((reg) * 2)
22#else 22#else
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index cfaa6b2bf345..1e56c8eea35f 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -1093,11 +1093,16 @@ static int e100_phy_init(struct nic *nic)
1093 } 1093 }
1094 1094
1095 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) && 1095 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1096 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) && 1096 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000))) {
1097 (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) 1097 /* enable/disable MDI/MDI-X auto-switching.
1098 /* enable/disable MDI/MDI-X auto-switching */ 1098 MDI/MDI-X auto-switching is disabled for 82551ER/QM chips */
1099 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 1099 if((nic->mac == mac_82551_E) || (nic->mac == mac_82551_F) ||
1100 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH); 1100 (nic->mac == mac_82551_10) || (nic->mii.force_media) ||
1101 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))
1102 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 0);
1103 else
1104 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, NCONFIG_AUTO_SWITCH);
1105 }
1101 1106
1102 return 0; 1107 return 0;
1103} 1108}
@@ -1666,8 +1671,10 @@ static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1666 if(stat_ack & stat_ack_rnr) 1671 if(stat_ack & stat_ack_rnr)
1667 nic->ru_running = RU_SUSPENDED; 1672 nic->ru_running = RU_SUSPENDED;
1668 1673
1669 e100_disable_irq(nic); 1674 if(likely(netif_rx_schedule_prep(netdev))) {
1670 netif_rx_schedule(netdev); 1675 e100_disable_irq(nic);
1676 __netif_rx_schedule(netdev);
1677 }
1671 1678
1672 return IRQ_HANDLED; 1679 return IRQ_HANDLED;
1673} 1680}
@@ -2335,11 +2342,11 @@ static int __devinit e100_probe(struct pci_dev *pdev,
2335 goto err_out_iounmap; 2342 goto err_out_iounmap;
2336 } 2343 }
2337 2344
2338 e100_phy_init(nic);
2339
2340 if((err = e100_eeprom_load(nic))) 2345 if((err = e100_eeprom_load(nic)))
2341 goto err_out_free; 2346 goto err_out_free;
2342 2347
2348 e100_phy_init(nic);
2349
2343 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN); 2350 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2344 if(!is_valid_ether_addr(netdev->dev_addr)) { 2351 if(!is_valid_ether_addr(netdev->dev_addr)) {
2345 DPRINTK(PROBE, ERR, "Invalid MAC address from " 2352 DPRINTK(PROBE, ERR, "Invalid MAC address from "
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index af1e82c5b808..092757bc721f 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -140,7 +140,7 @@ struct e1000_adapter;
140#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 140#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
141 141
142#define AUTO_ALL_MODES 0 142#define AUTO_ALL_MODES 0
143#define E1000_EEPROM_82544_APM 0x0400 143#define E1000_EEPROM_82544_APM 0x0004
144#define E1000_EEPROM_APME 0x0400 144#define E1000_EEPROM_APME 0x0400
145 145
146#ifndef E1000_MASTER_SLAVE 146#ifndef E1000_MASTER_SLAVE
@@ -159,7 +159,7 @@ struct e1000_adapter;
159 * so a DMA handle can be stored along with the buffer */ 159 * so a DMA handle can be stored along with the buffer */
160struct e1000_buffer { 160struct e1000_buffer {
161 struct sk_buff *skb; 161 struct sk_buff *skb;
162 uint64_t dma; 162 dma_addr_t dma;
163 unsigned long time_stamp; 163 unsigned long time_stamp;
164 uint16_t length; 164 uint16_t length;
165 uint16_t next_to_watch; 165 uint16_t next_to_watch;
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 237247f74df4..f133ff0b0b94 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -105,7 +105,7 @@ static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
105static int 105static int
106e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 106e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
107{ 107{
108 struct e1000_adapter *adapter = netdev->priv; 108 struct e1000_adapter *adapter = netdev_priv(netdev);
109 struct e1000_hw *hw = &adapter->hw; 109 struct e1000_hw *hw = &adapter->hw;
110 110
111 if(hw->media_type == e1000_media_type_copper) { 111 if(hw->media_type == e1000_media_type_copper) {
@@ -141,9 +141,9 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
141 SUPPORTED_FIBRE | 141 SUPPORTED_FIBRE |
142 SUPPORTED_Autoneg); 142 SUPPORTED_Autoneg);
143 143
144 ecmd->advertising = (SUPPORTED_1000baseT_Full | 144 ecmd->advertising = (ADVERTISED_1000baseT_Full |
145 SUPPORTED_FIBRE | 145 ADVERTISED_FIBRE |
146 SUPPORTED_Autoneg); 146 ADVERTISED_Autoneg);
147 147
148 ecmd->port = PORT_FIBRE; 148 ecmd->port = PORT_FIBRE;
149 149
@@ -179,13 +179,24 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
179static int 179static int
180e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 180e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
181{ 181{
182 struct e1000_adapter *adapter = netdev->priv; 182 struct e1000_adapter *adapter = netdev_priv(netdev);
183 struct e1000_hw *hw = &adapter->hw; 183 struct e1000_hw *hw = &adapter->hw;
184 184
185 if(ecmd->autoneg == AUTONEG_ENABLE) { 185 if(ecmd->autoneg == AUTONEG_ENABLE) {
186 hw->autoneg = 1; 186 hw->autoneg = 1;
187 hw->autoneg_advertised = 0x002F; 187 if(hw->media_type == e1000_media_type_fiber)
188 ecmd->advertising = 0x002F; 188 hw->autoneg_advertised = ADVERTISED_1000baseT_Full |
189 ADVERTISED_FIBRE |
190 ADVERTISED_Autoneg;
191 else
192 hw->autoneg_advertised = ADVERTISED_10baseT_Half |
193 ADVERTISED_10baseT_Full |
194 ADVERTISED_100baseT_Half |
195 ADVERTISED_100baseT_Full |
196 ADVERTISED_1000baseT_Full|
197 ADVERTISED_Autoneg |
198 ADVERTISED_TP;
199 ecmd->advertising = hw->autoneg_advertised;
189 } else 200 } else
190 if(e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) 201 if(e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex))
191 return -EINVAL; 202 return -EINVAL;
@@ -206,7 +217,7 @@ static void
206e1000_get_pauseparam(struct net_device *netdev, 217e1000_get_pauseparam(struct net_device *netdev,
207 struct ethtool_pauseparam *pause) 218 struct ethtool_pauseparam *pause)
208{ 219{
209 struct e1000_adapter *adapter = netdev->priv; 220 struct e1000_adapter *adapter = netdev_priv(netdev);
210 struct e1000_hw *hw = &adapter->hw; 221 struct e1000_hw *hw = &adapter->hw;
211 222
212 pause->autoneg = 223 pause->autoneg =
@@ -226,7 +237,7 @@ static int
226e1000_set_pauseparam(struct net_device *netdev, 237e1000_set_pauseparam(struct net_device *netdev,
227 struct ethtool_pauseparam *pause) 238 struct ethtool_pauseparam *pause)
228{ 239{
229 struct e1000_adapter *adapter = netdev->priv; 240 struct e1000_adapter *adapter = netdev_priv(netdev);
230 struct e1000_hw *hw = &adapter->hw; 241 struct e1000_hw *hw = &adapter->hw;
231 242
232 adapter->fc_autoneg = pause->autoneg; 243 adapter->fc_autoneg = pause->autoneg;
@@ -259,14 +270,14 @@ e1000_set_pauseparam(struct net_device *netdev,
259static uint32_t 270static uint32_t
260e1000_get_rx_csum(struct net_device *netdev) 271e1000_get_rx_csum(struct net_device *netdev)
261{ 272{
262 struct e1000_adapter *adapter = netdev->priv; 273 struct e1000_adapter *adapter = netdev_priv(netdev);
263 return adapter->rx_csum; 274 return adapter->rx_csum;
264} 275}
265 276
266static int 277static int
267e1000_set_rx_csum(struct net_device *netdev, uint32_t data) 278e1000_set_rx_csum(struct net_device *netdev, uint32_t data)
268{ 279{
269 struct e1000_adapter *adapter = netdev->priv; 280 struct e1000_adapter *adapter = netdev_priv(netdev);
270 adapter->rx_csum = data; 281 adapter->rx_csum = data;
271 282
272 if(netif_running(netdev)) { 283 if(netif_running(netdev)) {
@@ -286,7 +297,7 @@ e1000_get_tx_csum(struct net_device *netdev)
286static int 297static int
287e1000_set_tx_csum(struct net_device *netdev, uint32_t data) 298e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
288{ 299{
289 struct e1000_adapter *adapter = netdev->priv; 300 struct e1000_adapter *adapter = netdev_priv(netdev);
290 301
291 if(adapter->hw.mac_type < e1000_82543) { 302 if(adapter->hw.mac_type < e1000_82543) {
292 if (!data) 303 if (!data)
@@ -306,8 +317,8 @@ e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
306static int 317static int
307e1000_set_tso(struct net_device *netdev, uint32_t data) 318e1000_set_tso(struct net_device *netdev, uint32_t data)
308{ 319{
309 struct e1000_adapter *adapter = netdev->priv; 320 struct e1000_adapter *adapter = netdev_priv(netdev);
310 if ((adapter->hw.mac_type < e1000_82544) || 321 if((adapter->hw.mac_type < e1000_82544) ||
311 (adapter->hw.mac_type == e1000_82547)) 322 (adapter->hw.mac_type == e1000_82547))
312 return data ? -EINVAL : 0; 323 return data ? -EINVAL : 0;
313 324
@@ -322,14 +333,14 @@ e1000_set_tso(struct net_device *netdev, uint32_t data)
322static uint32_t 333static uint32_t
323e1000_get_msglevel(struct net_device *netdev) 334e1000_get_msglevel(struct net_device *netdev)
324{ 335{
325 struct e1000_adapter *adapter = netdev->priv; 336 struct e1000_adapter *adapter = netdev_priv(netdev);
326 return adapter->msg_enable; 337 return adapter->msg_enable;
327} 338}
328 339
329static void 340static void
330e1000_set_msglevel(struct net_device *netdev, uint32_t data) 341e1000_set_msglevel(struct net_device *netdev, uint32_t data)
331{ 342{
332 struct e1000_adapter *adapter = netdev->priv; 343 struct e1000_adapter *adapter = netdev_priv(netdev);
333 adapter->msg_enable = data; 344 adapter->msg_enable = data;
334} 345}
335 346
@@ -344,7 +355,7 @@ static void
344e1000_get_regs(struct net_device *netdev, 355e1000_get_regs(struct net_device *netdev,
345 struct ethtool_regs *regs, void *p) 356 struct ethtool_regs *regs, void *p)
346{ 357{
347 struct e1000_adapter *adapter = netdev->priv; 358 struct e1000_adapter *adapter = netdev_priv(netdev);
348 struct e1000_hw *hw = &adapter->hw; 359 struct e1000_hw *hw = &adapter->hw;
349 uint32_t *regs_buff = p; 360 uint32_t *regs_buff = p;
350 uint16_t phy_data; 361 uint16_t phy_data;
@@ -432,7 +443,7 @@ e1000_get_regs(struct net_device *netdev,
432static int 443static int
433e1000_get_eeprom_len(struct net_device *netdev) 444e1000_get_eeprom_len(struct net_device *netdev)
434{ 445{
435 struct e1000_adapter *adapter = netdev->priv; 446 struct e1000_adapter *adapter = netdev_priv(netdev);
436 return adapter->hw.eeprom.word_size * 2; 447 return adapter->hw.eeprom.word_size * 2;
437} 448}
438 449
@@ -440,7 +451,7 @@ static int
440e1000_get_eeprom(struct net_device *netdev, 451e1000_get_eeprom(struct net_device *netdev,
441 struct ethtool_eeprom *eeprom, uint8_t *bytes) 452 struct ethtool_eeprom *eeprom, uint8_t *bytes)
442{ 453{
443 struct e1000_adapter *adapter = netdev->priv; 454 struct e1000_adapter *adapter = netdev_priv(netdev);
444 struct e1000_hw *hw = &adapter->hw; 455 struct e1000_hw *hw = &adapter->hw;
445 uint16_t *eeprom_buff; 456 uint16_t *eeprom_buff;
446 int first_word, last_word; 457 int first_word, last_word;
@@ -486,7 +497,7 @@ static int
486e1000_set_eeprom(struct net_device *netdev, 497e1000_set_eeprom(struct net_device *netdev,
487 struct ethtool_eeprom *eeprom, uint8_t *bytes) 498 struct ethtool_eeprom *eeprom, uint8_t *bytes)
488{ 499{
489 struct e1000_adapter *adapter = netdev->priv; 500 struct e1000_adapter *adapter = netdev_priv(netdev);
490 struct e1000_hw *hw = &adapter->hw; 501 struct e1000_hw *hw = &adapter->hw;
491 uint16_t *eeprom_buff; 502 uint16_t *eeprom_buff;
492 void *ptr; 503 void *ptr;
@@ -547,7 +558,7 @@ static void
547e1000_get_drvinfo(struct net_device *netdev, 558e1000_get_drvinfo(struct net_device *netdev,
548 struct ethtool_drvinfo *drvinfo) 559 struct ethtool_drvinfo *drvinfo)
549{ 560{
550 struct e1000_adapter *adapter = netdev->priv; 561 struct e1000_adapter *adapter = netdev_priv(netdev);
551 562
552 strncpy(drvinfo->driver, e1000_driver_name, 32); 563 strncpy(drvinfo->driver, e1000_driver_name, 32);
553 strncpy(drvinfo->version, e1000_driver_version, 32); 564 strncpy(drvinfo->version, e1000_driver_version, 32);
@@ -563,7 +574,7 @@ static void
563e1000_get_ringparam(struct net_device *netdev, 574e1000_get_ringparam(struct net_device *netdev,
564 struct ethtool_ringparam *ring) 575 struct ethtool_ringparam *ring)
565{ 576{
566 struct e1000_adapter *adapter = netdev->priv; 577 struct e1000_adapter *adapter = netdev_priv(netdev);
567 e1000_mac_type mac_type = adapter->hw.mac_type; 578 e1000_mac_type mac_type = adapter->hw.mac_type;
568 struct e1000_desc_ring *txdr = &adapter->tx_ring; 579 struct e1000_desc_ring *txdr = &adapter->tx_ring;
569 struct e1000_desc_ring *rxdr = &adapter->rx_ring; 580 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
@@ -584,7 +595,7 @@ static int
584e1000_set_ringparam(struct net_device *netdev, 595e1000_set_ringparam(struct net_device *netdev,
585 struct ethtool_ringparam *ring) 596 struct ethtool_ringparam *ring)
586{ 597{
587 struct e1000_adapter *adapter = netdev->priv; 598 struct e1000_adapter *adapter = netdev_priv(netdev);
588 e1000_mac_type mac_type = adapter->hw.mac_type; 599 e1000_mac_type mac_type = adapter->hw.mac_type;
589 struct e1000_desc_ring *txdr = &adapter->tx_ring; 600 struct e1000_desc_ring *txdr = &adapter->tx_ring;
590 struct e1000_desc_ring *rxdr = &adapter->rx_ring; 601 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
@@ -651,6 +662,9 @@ err_setup_rx:
651 E1000_WRITE_REG(&adapter->hw, R, (test[pat] & W)); \ 662 E1000_WRITE_REG(&adapter->hw, R, (test[pat] & W)); \
652 value = E1000_READ_REG(&adapter->hw, R); \ 663 value = E1000_READ_REG(&adapter->hw, R); \
653 if(value != (test[pat] & W & M)) { \ 664 if(value != (test[pat] & W & M)) { \
665 DPRINTK(DRV, ERR, "pattern test reg %04X failed: got " \
666 "0x%08X expected 0x%08X\n", \
667 E1000_##R, value, (test[pat] & W & M)); \
654 *data = (adapter->hw.mac_type < e1000_82543) ? \ 668 *data = (adapter->hw.mac_type < e1000_82543) ? \
655 E1000_82542_##R : E1000_##R; \ 669 E1000_82542_##R : E1000_##R; \
656 return 1; \ 670 return 1; \
@@ -663,7 +677,9 @@ err_setup_rx:
663 uint32_t value; \ 677 uint32_t value; \
664 E1000_WRITE_REG(&adapter->hw, R, W & M); \ 678 E1000_WRITE_REG(&adapter->hw, R, W & M); \
665 value = E1000_READ_REG(&adapter->hw, R); \ 679 value = E1000_READ_REG(&adapter->hw, R); \
666 if ((W & M) != (value & M)) { \ 680 if((W & M) != (value & M)) { \
681 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
682 "expected 0x%08X\n", E1000_##R, (value & M), (W & M)); \
667 *data = (adapter->hw.mac_type < e1000_82543) ? \ 683 *data = (adapter->hw.mac_type < e1000_82543) ? \
668 E1000_82542_##R : E1000_##R; \ 684 E1000_82542_##R : E1000_##R; \
669 return 1; \ 685 return 1; \
@@ -673,18 +689,33 @@ err_setup_rx:
673static int 689static int
674e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data) 690e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
675{ 691{
676 uint32_t value; 692 uint32_t value, before, after;
677 uint32_t i; 693 uint32_t i, toggle;
678 694
679 /* The status register is Read Only, so a write should fail. 695 /* The status register is Read Only, so a write should fail.
680 * Some bits that get toggled are ignored. 696 * Some bits that get toggled are ignored.
681 */ 697 */
682 value = (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833)); 698 switch (adapter->hw.mac_type) {
683 E1000_WRITE_REG(&adapter->hw, STATUS, (0xFFFFFFFF)); 699 case e1000_82573:
684 if(value != (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833))) { 700 toggle = 0x7FFFF033;
701 break;
702 default:
703 toggle = 0xFFFFF833;
704 break;
705 }
706
707 before = E1000_READ_REG(&adapter->hw, STATUS);
708 value = (E1000_READ_REG(&adapter->hw, STATUS) & toggle);
709 E1000_WRITE_REG(&adapter->hw, STATUS, toggle);
710 after = E1000_READ_REG(&adapter->hw, STATUS) & toggle;
711 if(value != after) {
712 DPRINTK(DRV, ERR, "failed STATUS register test got: "
713 "0x%08X expected: 0x%08X\n", after, value);
685 *data = 1; 714 *data = 1;
686 return 1; 715 return 1;
687 } 716 }
717 /* restore previous status */
718 E1000_WRITE_REG(&adapter->hw, STATUS, before);
688 719
689 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); 720 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
690 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); 721 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
@@ -766,7 +797,7 @@ e1000_test_intr(int irq,
766 struct pt_regs *regs) 797 struct pt_regs *regs)
767{ 798{
768 struct net_device *netdev = (struct net_device *) data; 799 struct net_device *netdev = (struct net_device *) data;
769 struct e1000_adapter *adapter = netdev->priv; 800 struct e1000_adapter *adapter = netdev_priv(netdev);
770 801
771 adapter->test_icr |= E1000_READ_REG(&adapter->hw, ICR); 802 adapter->test_icr |= E1000_READ_REG(&adapter->hw, ICR);
772 803
@@ -1214,6 +1245,7 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
1214 case e1000_82541_rev_2: 1245 case e1000_82541_rev_2:
1215 case e1000_82547: 1246 case e1000_82547:
1216 case e1000_82547_rev_2: 1247 case e1000_82547_rev_2:
1248 case e1000_82573:
1217 return e1000_integrated_phy_loopback(adapter); 1249 return e1000_integrated_phy_loopback(adapter);
1218 break; 1250 break;
1219 1251
@@ -1422,7 +1454,7 @@ static void
1422e1000_diag_test(struct net_device *netdev, 1454e1000_diag_test(struct net_device *netdev,
1423 struct ethtool_test *eth_test, uint64_t *data) 1455 struct ethtool_test *eth_test, uint64_t *data)
1424{ 1456{
1425 struct e1000_adapter *adapter = netdev->priv; 1457 struct e1000_adapter *adapter = netdev_priv(netdev);
1426 boolean_t if_running = netif_running(netdev); 1458 boolean_t if_running = netif_running(netdev);
1427 1459
1428 if(eth_test->flags == ETH_TEST_FL_OFFLINE) { 1460 if(eth_test->flags == ETH_TEST_FL_OFFLINE) {
@@ -1482,7 +1514,7 @@ e1000_diag_test(struct net_device *netdev,
1482static void 1514static void
1483e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1515e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1484{ 1516{
1485 struct e1000_adapter *adapter = netdev->priv; 1517 struct e1000_adapter *adapter = netdev_priv(netdev);
1486 struct e1000_hw *hw = &adapter->hw; 1518 struct e1000_hw *hw = &adapter->hw;
1487 1519
1488 switch(adapter->hw.device_id) { 1520 switch(adapter->hw.device_id) {
@@ -1527,7 +1559,7 @@ e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1527static int 1559static int
1528e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1560e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1529{ 1561{
1530 struct e1000_adapter *adapter = netdev->priv; 1562 struct e1000_adapter *adapter = netdev_priv(netdev);
1531 struct e1000_hw *hw = &adapter->hw; 1563 struct e1000_hw *hw = &adapter->hw;
1532 1564
1533 switch(adapter->hw.device_id) { 1565 switch(adapter->hw.device_id) {
@@ -1588,22 +1620,31 @@ e1000_led_blink_callback(unsigned long data)
1588static int 1620static int
1589e1000_phys_id(struct net_device *netdev, uint32_t data) 1621e1000_phys_id(struct net_device *netdev, uint32_t data)
1590{ 1622{
1591 struct e1000_adapter *adapter = netdev->priv; 1623 struct e1000_adapter *adapter = netdev_priv(netdev);
1592 1624
1593 if(!data || data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ)) 1625 if(!data || data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ))
1594 data = (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ); 1626 data = (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ);
1595 1627
1596 if(!adapter->blink_timer.function) { 1628 if(adapter->hw.mac_type < e1000_82573) {
1597 init_timer(&adapter->blink_timer); 1629 if(!adapter->blink_timer.function) {
1598 adapter->blink_timer.function = e1000_led_blink_callback; 1630 init_timer(&adapter->blink_timer);
1599 adapter->blink_timer.data = (unsigned long) adapter; 1631 adapter->blink_timer.function = e1000_led_blink_callback;
1632 adapter->blink_timer.data = (unsigned long) adapter;
1633 }
1634 e1000_setup_led(&adapter->hw);
1635 mod_timer(&adapter->blink_timer, jiffies);
1636 msleep_interruptible(data * 1000);
1637 del_timer_sync(&adapter->blink_timer);
1638 }
1639 else {
1640 E1000_WRITE_REG(&adapter->hw, LEDCTL, (E1000_LEDCTL_LED2_BLINK_RATE |
1641 E1000_LEDCTL_LED1_BLINK | E1000_LEDCTL_LED2_BLINK |
1642 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED2_MODE_SHIFT) |
1643 (E1000_LEDCTL_MODE_LINK_ACTIVITY << E1000_LEDCTL_LED1_MODE_SHIFT) |
1644 (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT)));
1645 msleep_interruptible(data * 1000);
1600 } 1646 }
1601 1647
1602 e1000_setup_led(&adapter->hw);
1603 mod_timer(&adapter->blink_timer, jiffies);
1604
1605 msleep_interruptible(data * 1000);
1606 del_timer_sync(&adapter->blink_timer);
1607 e1000_led_off(&adapter->hw); 1648 e1000_led_off(&adapter->hw);
1608 clear_bit(E1000_LED_ON, &adapter->led_status); 1649 clear_bit(E1000_LED_ON, &adapter->led_status);
1609 e1000_cleanup_led(&adapter->hw); 1650 e1000_cleanup_led(&adapter->hw);
@@ -1614,7 +1655,7 @@ e1000_phys_id(struct net_device *netdev, uint32_t data)
1614static int 1655static int
1615e1000_nway_reset(struct net_device *netdev) 1656e1000_nway_reset(struct net_device *netdev)
1616{ 1657{
1617 struct e1000_adapter *adapter = netdev->priv; 1658 struct e1000_adapter *adapter = netdev_priv(netdev);
1618 if(netif_running(netdev)) { 1659 if(netif_running(netdev)) {
1619 e1000_down(adapter); 1660 e1000_down(adapter);
1620 e1000_up(adapter); 1661 e1000_up(adapter);
@@ -1632,7 +1673,7 @@ static void
1632e1000_get_ethtool_stats(struct net_device *netdev, 1673e1000_get_ethtool_stats(struct net_device *netdev,
1633 struct ethtool_stats *stats, uint64_t *data) 1674 struct ethtool_stats *stats, uint64_t *data)
1634{ 1675{
1635 struct e1000_adapter *adapter = netdev->priv; 1676 struct e1000_adapter *adapter = netdev_priv(netdev);
1636 int i; 1677 int i;
1637 1678
1638 e1000_update_stats(adapter); 1679 e1000_update_stats(adapter);
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 723589b28be5..045f5426ab9a 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -354,18 +354,27 @@ e1000_set_media_type(struct e1000_hw *hw)
354 hw->media_type = e1000_media_type_internal_serdes; 354 hw->media_type = e1000_media_type_internal_serdes;
355 break; 355 break;
356 default: 356 default:
357 if(hw->mac_type >= e1000_82543) { 357 switch (hw->mac_type) {
358 case e1000_82542_rev2_0:
359 case e1000_82542_rev2_1:
360 hw->media_type = e1000_media_type_fiber;
361 break;
362 case e1000_82573:
363 /* The STATUS_TBIMODE bit is reserved or reused for the this
364 * device.
365 */
366 hw->media_type = e1000_media_type_copper;
367 break;
368 default:
358 status = E1000_READ_REG(hw, STATUS); 369 status = E1000_READ_REG(hw, STATUS);
359 if(status & E1000_STATUS_TBIMODE) { 370 if (status & E1000_STATUS_TBIMODE) {
360 hw->media_type = e1000_media_type_fiber; 371 hw->media_type = e1000_media_type_fiber;
361 /* tbi_compatibility not valid on fiber */ 372 /* tbi_compatibility not valid on fiber */
362 hw->tbi_compatibility_en = FALSE; 373 hw->tbi_compatibility_en = FALSE;
363 } else { 374 } else {
364 hw->media_type = e1000_media_type_copper; 375 hw->media_type = e1000_media_type_copper;
365 } 376 }
366 } else { 377 break;
367 /* This is an 82542 (fiber only) */
368 hw->media_type = e1000_media_type_fiber;
369 } 378 }
370 } 379 }
371} 380}
@@ -1189,9 +1198,9 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1189 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1198 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1190 if(ret_val) 1199 if(ret_val)
1191 return ret_val; 1200 return ret_val;
1192 } 1201 }
1193 1202
1194 return E1000_SUCCESS; 1203 return E1000_SUCCESS;
1195} 1204}
1196 1205
1197 1206
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index a0263ee96c6b..93e9f8788751 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -66,6 +66,7 @@ typedef enum {
66 e1000_eeprom_spi, 66 e1000_eeprom_spi,
67 e1000_eeprom_microwire, 67 e1000_eeprom_microwire,
68 e1000_eeprom_flash, 68 e1000_eeprom_flash,
69 e1000_eeprom_none, /* No NVM support */
69 e1000_num_eeprom_types 70 e1000_num_eeprom_types
70} e1000_eeprom_type; 71} e1000_eeprom_type;
71 72
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 137226d98d47..cb7f051a60ad 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -29,6 +29,8 @@
29#include "e1000.h" 29#include "e1000.h"
30 30
31/* Change Log 31/* Change Log
32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
32 * 6.0.44+ 2/15/05 34 * 6.0.44+ 2/15/05
33 * o applied Anton's patch to resolve tx hang in hardware 35 * o applied Anton's patch to resolve tx hang in hardware
34 * o Applied Andrew Mortons patch - e1000 stops working after resume 36 * o Applied Andrew Mortons patch - e1000 stops working after resume
@@ -41,9 +43,9 @@ char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
41#else 43#else
42#define DRIVERNAPI "-NAPI" 44#define DRIVERNAPI "-NAPI"
43#endif 45#endif
44#define DRV_VERSION "6.0.54-k2"DRIVERNAPI 46#define DRV_VERSION "6.0.60-k2"DRIVERNAPI
45char e1000_driver_version[] = DRV_VERSION; 47char e1000_driver_version[] = DRV_VERSION;
46char e1000_copyright[] = "Copyright (c) 1999-2004 Intel Corporation."; 48char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
47 49
48/* e1000_pci_tbl - PCI Device ID Table 50/* e1000_pci_tbl - PCI Device ID Table
49 * 51 *
@@ -517,7 +519,7 @@ e1000_probe(struct pci_dev *pdev,
517 SET_NETDEV_DEV(netdev, &pdev->dev); 519 SET_NETDEV_DEV(netdev, &pdev->dev);
518 520
519 pci_set_drvdata(pdev, netdev); 521 pci_set_drvdata(pdev, netdev);
520 adapter = netdev->priv; 522 adapter = netdev_priv(netdev);
521 adapter->netdev = netdev; 523 adapter->netdev = netdev;
522 adapter->pdev = pdev; 524 adapter->pdev = pdev;
523 adapter->hw.back = adapter; 525 adapter->hw.back = adapter;
@@ -738,7 +740,7 @@ static void __devexit
738e1000_remove(struct pci_dev *pdev) 740e1000_remove(struct pci_dev *pdev)
739{ 741{
740 struct net_device *netdev = pci_get_drvdata(pdev); 742 struct net_device *netdev = pci_get_drvdata(pdev);
741 struct e1000_adapter *adapter = netdev->priv; 743 struct e1000_adapter *adapter = netdev_priv(netdev);
742 uint32_t manc, swsm; 744 uint32_t manc, swsm;
743 745
744 flush_scheduled_work(); 746 flush_scheduled_work();
@@ -871,7 +873,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
871static int 873static int
872e1000_open(struct net_device *netdev) 874e1000_open(struct net_device *netdev)
873{ 875{
874 struct e1000_adapter *adapter = netdev->priv; 876 struct e1000_adapter *adapter = netdev_priv(netdev);
875 int err; 877 int err;
876 878
877 /* allocate transmit descriptors */ 879 /* allocate transmit descriptors */
@@ -919,7 +921,7 @@ err_setup_tx:
919static int 921static int
920e1000_close(struct net_device *netdev) 922e1000_close(struct net_device *netdev)
921{ 923{
922 struct e1000_adapter *adapter = netdev->priv; 924 struct e1000_adapter *adapter = netdev_priv(netdev);
923 925
924 e1000_down(adapter); 926 e1000_down(adapter);
925 927
@@ -1599,7 +1601,7 @@ e1000_leave_82542_rst(struct e1000_adapter *adapter)
1599static int 1601static int
1600e1000_set_mac(struct net_device *netdev, void *p) 1602e1000_set_mac(struct net_device *netdev, void *p)
1601{ 1603{
1602 struct e1000_adapter *adapter = netdev->priv; 1604 struct e1000_adapter *adapter = netdev_priv(netdev);
1603 struct sockaddr *addr = p; 1605 struct sockaddr *addr = p;
1604 1606
1605 if(!is_valid_ether_addr(addr->sa_data)) 1607 if(!is_valid_ether_addr(addr->sa_data))
@@ -1634,7 +1636,7 @@ e1000_set_mac(struct net_device *netdev, void *p)
1634static void 1636static void
1635e1000_set_multi(struct net_device *netdev) 1637e1000_set_multi(struct net_device *netdev)
1636{ 1638{
1637 struct e1000_adapter *adapter = netdev->priv; 1639 struct e1000_adapter *adapter = netdev_priv(netdev);
1638 struct e1000_hw *hw = &adapter->hw; 1640 struct e1000_hw *hw = &adapter->hw;
1639 struct dev_mc_list *mc_ptr; 1641 struct dev_mc_list *mc_ptr;
1640 unsigned long flags; 1642 unsigned long flags;
@@ -2213,7 +2215,7 @@ e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2213static int 2215static int
2214e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2216e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2215{ 2217{
2216 struct e1000_adapter *adapter = netdev->priv; 2218 struct e1000_adapter *adapter = netdev_priv(netdev);
2217 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD; 2219 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2218 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR; 2220 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2219 unsigned int tx_flags = 0; 2221 unsigned int tx_flags = 0;
@@ -2344,7 +2346,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2344static void 2346static void
2345e1000_tx_timeout(struct net_device *netdev) 2347e1000_tx_timeout(struct net_device *netdev)
2346{ 2348{
2347 struct e1000_adapter *adapter = netdev->priv; 2349 struct e1000_adapter *adapter = netdev_priv(netdev);
2348 2350
2349 /* Do the reset outside of interrupt context */ 2351 /* Do the reset outside of interrupt context */
2350 schedule_work(&adapter->tx_timeout_task); 2352 schedule_work(&adapter->tx_timeout_task);
@@ -2353,7 +2355,7 @@ e1000_tx_timeout(struct net_device *netdev)
2353static void 2355static void
2354e1000_tx_timeout_task(struct net_device *netdev) 2356e1000_tx_timeout_task(struct net_device *netdev)
2355{ 2357{
2356 struct e1000_adapter *adapter = netdev->priv; 2358 struct e1000_adapter *adapter = netdev_priv(netdev);
2357 2359
2358 e1000_down(adapter); 2360 e1000_down(adapter);
2359 e1000_up(adapter); 2361 e1000_up(adapter);
@@ -2370,7 +2372,7 @@ e1000_tx_timeout_task(struct net_device *netdev)
2370static struct net_device_stats * 2372static struct net_device_stats *
2371e1000_get_stats(struct net_device *netdev) 2373e1000_get_stats(struct net_device *netdev)
2372{ 2374{
2373 struct e1000_adapter *adapter = netdev->priv; 2375 struct e1000_adapter *adapter = netdev_priv(netdev);
2374 2376
2375 e1000_update_stats(adapter); 2377 e1000_update_stats(adapter);
2376 return &adapter->net_stats; 2378 return &adapter->net_stats;
@@ -2387,7 +2389,7 @@ e1000_get_stats(struct net_device *netdev)
2387static int 2389static int
2388e1000_change_mtu(struct net_device *netdev, int new_mtu) 2390e1000_change_mtu(struct net_device *netdev, int new_mtu)
2389{ 2391{
2390 struct e1000_adapter *adapter = netdev->priv; 2392 struct e1000_adapter *adapter = netdev_priv(netdev);
2391 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 2393 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2392 2394
2393 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || 2395 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
@@ -2598,7 +2600,7 @@ static irqreturn_t
2598e1000_intr(int irq, void *data, struct pt_regs *regs) 2600e1000_intr(int irq, void *data, struct pt_regs *regs)
2599{ 2601{
2600 struct net_device *netdev = data; 2602 struct net_device *netdev = data;
2601 struct e1000_adapter *adapter = netdev->priv; 2603 struct e1000_adapter *adapter = netdev_priv(netdev);
2602 struct e1000_hw *hw = &adapter->hw; 2604 struct e1000_hw *hw = &adapter->hw;
2603 uint32_t icr = E1000_READ_REG(hw, ICR); 2605 uint32_t icr = E1000_READ_REG(hw, ICR);
2604#ifndef CONFIG_E1000_NAPI 2606#ifndef CONFIG_E1000_NAPI
@@ -2661,7 +2663,7 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
2661static int 2663static int
2662e1000_clean(struct net_device *netdev, int *budget) 2664e1000_clean(struct net_device *netdev, int *budget)
2663{ 2665{
2664 struct e1000_adapter *adapter = netdev->priv; 2666 struct e1000_adapter *adapter = netdev_priv(netdev);
2665 int work_to_do = min(*budget, netdev->quota); 2667 int work_to_do = min(*budget, netdev->quota);
2666 int tx_cleaned; 2668 int tx_cleaned;
2667 int work_done = 0; 2669 int work_done = 0;
@@ -2672,8 +2674,8 @@ e1000_clean(struct net_device *netdev, int *budget)
2672 *budget -= work_done; 2674 *budget -= work_done;
2673 netdev->quota -= work_done; 2675 netdev->quota -= work_done;
2674 2676
2675 /* If no Tx and no Rx work done, exit the polling mode */
2676 if ((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) { 2677 if ((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
2678 /* If no Tx and not enough Rx work done, exit the polling mode */
2677 netif_rx_complete(netdev); 2679 netif_rx_complete(netdev);
2678 e1000_irq_enable(adapter); 2680 e1000_irq_enable(adapter);
2679 return 0; 2681 return 0;
@@ -2769,13 +2771,13 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter)
2769 i = tx_ring->next_to_clean; 2771 i = tx_ring->next_to_clean;
2770 eop = tx_ring->buffer_info[i].next_to_watch; 2772 eop = tx_ring->buffer_info[i].next_to_watch;
2771 eop_desc = E1000_TX_DESC(*tx_ring, eop); 2773 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2772 DPRINTK(TX_ERR, ERR, "Detected Tx Unit Hang\n" 2774 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
2773 " TDH <%x>\n" 2775 " TDH <%x>\n"
2774 " TDT <%x>\n" 2776 " TDT <%x>\n"
2775 " next_to_use <%x>\n" 2777 " next_to_use <%x>\n"
2776 " next_to_clean <%x>\n" 2778 " next_to_clean <%x>\n"
2777 "buffer_info[next_to_clean]\n" 2779 "buffer_info[next_to_clean]\n"
2778 " dma <%llx>\n" 2780 " dma <%zx>\n"
2779 " time_stamp <%lx>\n" 2781 " time_stamp <%lx>\n"
2780 " next_to_watch <%x>\n" 2782 " next_to_watch <%x>\n"
2781 " jiffies <%lx>\n" 2783 " jiffies <%lx>\n"
@@ -2994,7 +2996,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter)
2994 2996
2995 i = rx_ring->next_to_clean; 2997 i = rx_ring->next_to_clean;
2996 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 2998 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
2997 staterr = rx_desc->wb.middle.status_error; 2999 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2998 3000
2999 while(staterr & E1000_RXD_STAT_DD) { 3001 while(staterr & E1000_RXD_STAT_DD) {
3000 buffer_info = &rx_ring->buffer_info[i]; 3002 buffer_info = &rx_ring->buffer_info[i];
@@ -3065,16 +3067,16 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter)
3065#ifdef CONFIG_E1000_NAPI 3067#ifdef CONFIG_E1000_NAPI
3066 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) { 3068 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3067 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 3069 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3068 le16_to_cpu(rx_desc->wb.middle.vlan & 3070 le16_to_cpu(rx_desc->wb.middle.vlan) &
3069 E1000_RXD_SPC_VLAN_MASK)); 3071 E1000_RXD_SPC_VLAN_MASK);
3070 } else { 3072 } else {
3071 netif_receive_skb(skb); 3073 netif_receive_skb(skb);
3072 } 3074 }
3073#else /* CONFIG_E1000_NAPI */ 3075#else /* CONFIG_E1000_NAPI */
3074 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) { 3076 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3075 vlan_hwaccel_rx(skb, adapter->vlgrp, 3077 vlan_hwaccel_rx(skb, adapter->vlgrp,
3076 le16_to_cpu(rx_desc->wb.middle.vlan & 3078 le16_to_cpu(rx_desc->wb.middle.vlan) &
3077 E1000_RXD_SPC_VLAN_MASK)); 3079 E1000_RXD_SPC_VLAN_MASK);
3078 } else { 3080 } else {
3079 netif_rx(skb); 3081 netif_rx(skb);
3080 } 3082 }
@@ -3087,7 +3089,7 @@ next_desc:
3087 if(unlikely(++i == rx_ring->count)) i = 0; 3089 if(unlikely(++i == rx_ring->count)) i = 0;
3088 3090
3089 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 3091 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3090 staterr = rx_desc->wb.middle.status_error; 3092 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
3091 } 3093 }
3092 rx_ring->next_to_clean = i; 3094 rx_ring->next_to_clean = i;
3093 adapter->alloc_rx_buf(adapter); 3095 adapter->alloc_rx_buf(adapter);
@@ -3371,11 +3373,12 @@ e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3371static int 3373static int
3372e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 3374e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3373{ 3375{
3374 struct e1000_adapter *adapter = netdev->priv; 3376 struct e1000_adapter *adapter = netdev_priv(netdev);
3375 struct mii_ioctl_data *data = if_mii(ifr); 3377 struct mii_ioctl_data *data = if_mii(ifr);
3376 int retval; 3378 int retval;
3377 uint16_t mii_reg; 3379 uint16_t mii_reg;
3378 uint16_t spddplx; 3380 uint16_t spddplx;
3381 unsigned long flags;
3379 3382
3380 if(adapter->hw.media_type != e1000_media_type_copper) 3383 if(adapter->hw.media_type != e1000_media_type_copper)
3381 return -EOPNOTSUPP; 3384 return -EOPNOTSUPP;
@@ -3385,22 +3388,29 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3385 data->phy_id = adapter->hw.phy_addr; 3388 data->phy_id = adapter->hw.phy_addr;
3386 break; 3389 break;
3387 case SIOCGMIIREG: 3390 case SIOCGMIIREG:
3388 if (!capable(CAP_NET_ADMIN)) 3391 if(!capable(CAP_NET_ADMIN))
3389 return -EPERM; 3392 return -EPERM;
3390 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 3393 spin_lock_irqsave(&adapter->stats_lock, flags);
3391 &data->val_out)) 3394 if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
3395 &data->val_out)) {
3396 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3392 return -EIO; 3397 return -EIO;
3398 }
3399 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3393 break; 3400 break;
3394 case SIOCSMIIREG: 3401 case SIOCSMIIREG:
3395 if (!capable(CAP_NET_ADMIN)) 3402 if(!capable(CAP_NET_ADMIN))
3396 return -EPERM; 3403 return -EPERM;
3397 if (data->reg_num & ~(0x1F)) 3404 if(data->reg_num & ~(0x1F))
3398 return -EFAULT; 3405 return -EFAULT;
3399 mii_reg = data->val_in; 3406 mii_reg = data->val_in;
3400 if (e1000_write_phy_reg(&adapter->hw, data->reg_num, 3407 spin_lock_irqsave(&adapter->stats_lock, flags);
3401 mii_reg)) 3408 if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
3409 mii_reg)) {
3410 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3402 return -EIO; 3411 return -EIO;
3403 if (adapter->hw.phy_type == e1000_phy_m88) { 3412 }
3413 if(adapter->hw.phy_type == e1000_phy_m88) {
3404 switch (data->reg_num) { 3414 switch (data->reg_num) {
3405 case PHY_CTRL: 3415 case PHY_CTRL:
3406 if(mii_reg & MII_CR_POWER_DOWN) 3416 if(mii_reg & MII_CR_POWER_DOWN)
@@ -3420,8 +3430,12 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3420 HALF_DUPLEX; 3430 HALF_DUPLEX;
3421 retval = e1000_set_spd_dplx(adapter, 3431 retval = e1000_set_spd_dplx(adapter,
3422 spddplx); 3432 spddplx);
3423 if(retval) 3433 if(retval) {
3434 spin_unlock_irqrestore(
3435 &adapter->stats_lock,
3436 flags);
3424 return retval; 3437 return retval;
3438 }
3425 } 3439 }
3426 if(netif_running(adapter->netdev)) { 3440 if(netif_running(adapter->netdev)) {
3427 e1000_down(adapter); 3441 e1000_down(adapter);
@@ -3431,8 +3445,11 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3431 break; 3445 break;
3432 case M88E1000_PHY_SPEC_CTRL: 3446 case M88E1000_PHY_SPEC_CTRL:
3433 case M88E1000_EXT_PHY_SPEC_CTRL: 3447 case M88E1000_EXT_PHY_SPEC_CTRL:
3434 if (e1000_phy_reset(&adapter->hw)) 3448 if(e1000_phy_reset(&adapter->hw)) {
3449 spin_unlock_irqrestore(
3450 &adapter->stats_lock, flags);
3435 return -EIO; 3451 return -EIO;
3452 }
3436 break; 3453 break;
3437 } 3454 }
3438 } else { 3455 } else {
@@ -3448,6 +3465,7 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3448 break; 3465 break;
3449 } 3466 }
3450 } 3467 }
3468 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3451 break; 3469 break;
3452 default: 3470 default:
3453 return -EOPNOTSUPP; 3471 return -EOPNOTSUPP;
@@ -3504,7 +3522,7 @@ e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
3504static void 3522static void
3505e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) 3523e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
3506{ 3524{
3507 struct e1000_adapter *adapter = netdev->priv; 3525 struct e1000_adapter *adapter = netdev_priv(netdev);
3508 uint32_t ctrl, rctl; 3526 uint32_t ctrl, rctl;
3509 3527
3510 e1000_irq_disable(adapter); 3528 e1000_irq_disable(adapter);
@@ -3544,7 +3562,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
3544static void 3562static void
3545e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid) 3563e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
3546{ 3564{
3547 struct e1000_adapter *adapter = netdev->priv; 3565 struct e1000_adapter *adapter = netdev_priv(netdev);
3548 uint32_t vfta, index; 3566 uint32_t vfta, index;
3549 if((adapter->hw.mng_cookie.status & 3567 if((adapter->hw.mng_cookie.status &
3550 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && 3568 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
@@ -3560,7 +3578,7 @@ e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
3560static void 3578static void
3561e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid) 3579e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
3562{ 3580{
3563 struct e1000_adapter *adapter = netdev->priv; 3581 struct e1000_adapter *adapter = netdev_priv(netdev);
3564 uint32_t vfta, index; 3582 uint32_t vfta, index;
3565 3583
3566 e1000_irq_disable(adapter); 3584 e1000_irq_disable(adapter);
@@ -3601,6 +3619,13 @@ e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
3601{ 3619{
3602 adapter->hw.autoneg = 0; 3620 adapter->hw.autoneg = 0;
3603 3621
3622 /* Fiber NICs only allow 1000 gbps Full duplex */
3623 if((adapter->hw.media_type == e1000_media_type_fiber) &&
3624 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3625 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
3626 return -EINVAL;
3627 }
3628
3604 switch(spddplx) { 3629 switch(spddplx) {
3605 case SPEED_10 + DUPLEX_HALF: 3630 case SPEED_10 + DUPLEX_HALF:
3606 adapter->hw.forced_speed_duplex = e1000_10_half; 3631 adapter->hw.forced_speed_duplex = e1000_10_half;
@@ -3647,7 +3672,7 @@ static int
3647e1000_suspend(struct pci_dev *pdev, uint32_t state) 3672e1000_suspend(struct pci_dev *pdev, uint32_t state)
3648{ 3673{
3649 struct net_device *netdev = pci_get_drvdata(pdev); 3674 struct net_device *netdev = pci_get_drvdata(pdev);
3650 struct e1000_adapter *adapter = netdev->priv; 3675 struct e1000_adapter *adapter = netdev_priv(netdev);
3651 uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm; 3676 uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm;
3652 uint32_t wufc = adapter->wol; 3677 uint32_t wufc = adapter->wol;
3653 3678
@@ -3740,12 +3765,12 @@ static int
3740e1000_resume(struct pci_dev *pdev) 3765e1000_resume(struct pci_dev *pdev)
3741{ 3766{
3742 struct net_device *netdev = pci_get_drvdata(pdev); 3767 struct net_device *netdev = pci_get_drvdata(pdev);
3743 struct e1000_adapter *adapter = netdev->priv; 3768 struct e1000_adapter *adapter = netdev_priv(netdev);
3744 uint32_t manc, ret, swsm; 3769 uint32_t manc, ret_val, swsm;
3745 3770
3746 pci_set_power_state(pdev, 0); 3771 pci_set_power_state(pdev, 0);
3747 pci_restore_state(pdev); 3772 pci_restore_state(pdev);
3748 ret = pci_enable_device(pdev); 3773 ret_val = pci_enable_device(pdev);
3749 pci_set_master(pdev); 3774 pci_set_master(pdev);
3750 3775
3751 pci_enable_wake(pdev, 3, 0); 3776 pci_enable_wake(pdev, 3, 0);
@@ -3788,7 +3813,7 @@ e1000_resume(struct pci_dev *pdev)
3788static void 3813static void
3789e1000_netpoll(struct net_device *netdev) 3814e1000_netpoll(struct net_device *netdev)
3790{ 3815{
3791 struct e1000_adapter *adapter = netdev->priv; 3816 struct e1000_adapter *adapter = netdev_priv(netdev);
3792 disable_irq(adapter->pdev->irq); 3817 disable_irq(adapter->pdev->irq);
3793 e1000_intr(adapter->pdev->irq, netdev, NULL); 3818 e1000_intr(adapter->pdev->irq, netdev, NULL);
3794 enable_irq(adapter->pdev->irq); 3819 enable_irq(adapter->pdev->irq);
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 4ebcd052e150..64f0f697c958 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -82,6 +82,9 @@
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link 82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * capabilities. 83 * capabilities.
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added. 84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
85 * 88 *
86 * Known bugs: 89 * Known bugs:
87 * We suspect that on some hardware no TX done interrupts are generated. 90 * We suspect that on some hardware no TX done interrupts are generated.
@@ -93,7 +96,7 @@
93 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 96 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
94 * superfluous timer interrupts from the nic. 97 * superfluous timer interrupts from the nic.
95 */ 98 */
96#define FORCEDETH_VERSION "0.32" 99#define FORCEDETH_VERSION "0.35"
97#define DRV_NAME "forcedeth" 100#define DRV_NAME "forcedeth"
98 101
99#include <linux/module.h> 102#include <linux/module.h>
@@ -2005,7 +2008,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
2005 /* handle different descriptor versions */ 2008 /* handle different descriptor versions */
2006 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 || 2009 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
2007 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 || 2010 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
2008 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3) 2011 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3 ||
2012 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
2013 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_13)
2009 np->desc_ver = DESC_VER_1; 2014 np->desc_ver = DESC_VER_1;
2010 else 2015 else
2011 np->desc_ver = DESC_VER_2; 2016 np->desc_ver = DESC_VER_2;
@@ -2215,56 +2220,84 @@ static struct pci_device_id pci_tbl[] = {
2215 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4, 2220 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4,
2216 .subvendor = PCI_ANY_ID, 2221 .subvendor = PCI_ANY_ID,
2217 .subdevice = PCI_ANY_ID, 2222 .subdevice = PCI_ANY_ID,
2218 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2223 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2219 }, 2224 },
2220 { /* nForce3 Ethernet Controller */ 2225 { /* nForce3 Ethernet Controller */
2221 .vendor = PCI_VENDOR_ID_NVIDIA, 2226 .vendor = PCI_VENDOR_ID_NVIDIA,
2222 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5, 2227 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5,
2223 .subvendor = PCI_ANY_ID, 2228 .subvendor = PCI_ANY_ID,
2224 .subdevice = PCI_ANY_ID, 2229 .subdevice = PCI_ANY_ID,
2225 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2230 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2226 }, 2231 },
2227 { /* nForce3 Ethernet Controller */ 2232 { /* nForce3 Ethernet Controller */
2228 .vendor = PCI_VENDOR_ID_NVIDIA, 2233 .vendor = PCI_VENDOR_ID_NVIDIA,
2229 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6, 2234 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6,
2230 .subvendor = PCI_ANY_ID, 2235 .subvendor = PCI_ANY_ID,
2231 .subdevice = PCI_ANY_ID, 2236 .subdevice = PCI_ANY_ID,
2232 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2237 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2233 }, 2238 },
2234 { /* nForce3 Ethernet Controller */ 2239 { /* nForce3 Ethernet Controller */
2235 .vendor = PCI_VENDOR_ID_NVIDIA, 2240 .vendor = PCI_VENDOR_ID_NVIDIA,
2236 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7, 2241 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7,
2237 .subvendor = PCI_ANY_ID, 2242 .subvendor = PCI_ANY_ID,
2238 .subdevice = PCI_ANY_ID, 2243 .subdevice = PCI_ANY_ID,
2239 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2244 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2240 }, 2245 },
2241 { /* CK804 Ethernet Controller */ 2246 { /* CK804 Ethernet Controller */
2242 .vendor = PCI_VENDOR_ID_NVIDIA, 2247 .vendor = PCI_VENDOR_ID_NVIDIA,
2243 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8, 2248 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8,
2244 .subvendor = PCI_ANY_ID, 2249 .subvendor = PCI_ANY_ID,
2245 .subdevice = PCI_ANY_ID, 2250 .subdevice = PCI_ANY_ID,
2246 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2251 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2247 }, 2252 },
2248 { /* CK804 Ethernet Controller */ 2253 { /* CK804 Ethernet Controller */
2249 .vendor = PCI_VENDOR_ID_NVIDIA, 2254 .vendor = PCI_VENDOR_ID_NVIDIA,
2250 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9, 2255 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9,
2251 .subvendor = PCI_ANY_ID, 2256 .subvendor = PCI_ANY_ID,
2252 .subdevice = PCI_ANY_ID, 2257 .subdevice = PCI_ANY_ID,
2253 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2258 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2254 }, 2259 },
2255 { /* MCP04 Ethernet Controller */ 2260 { /* MCP04 Ethernet Controller */
2256 .vendor = PCI_VENDOR_ID_NVIDIA, 2261 .vendor = PCI_VENDOR_ID_NVIDIA,
2257 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10, 2262 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10,
2258 .subvendor = PCI_ANY_ID, 2263 .subvendor = PCI_ANY_ID,
2259 .subdevice = PCI_ANY_ID, 2264 .subdevice = PCI_ANY_ID,
2260 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2265 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2261 }, 2266 },
2262 { /* MCP04 Ethernet Controller */ 2267 { /* MCP04 Ethernet Controller */
2263 .vendor = PCI_VENDOR_ID_NVIDIA, 2268 .vendor = PCI_VENDOR_ID_NVIDIA,
2264 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11, 2269 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11,
2265 .subvendor = PCI_ANY_ID, 2270 .subvendor = PCI_ANY_ID,
2266 .subdevice = PCI_ANY_ID, 2271 .subdevice = PCI_ANY_ID,
2267 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, 2272 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2273 },
2274 { /* MCP51 Ethernet Controller */
2275 .vendor = PCI_VENDOR_ID_NVIDIA,
2276 .device = PCI_DEVICE_ID_NVIDIA_NVENET_12,
2277 .subvendor = PCI_ANY_ID,
2278 .subdevice = PCI_ANY_ID,
2279 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2280 },
2281 { /* MCP51 Ethernet Controller */
2282 .vendor = PCI_VENDOR_ID_NVIDIA,
2283 .device = PCI_DEVICE_ID_NVIDIA_NVENET_13,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2287 },
2288 { /* MCP55 Ethernet Controller */
2289 .vendor = PCI_VENDOR_ID_NVIDIA,
2290 .device = PCI_DEVICE_ID_NVIDIA_NVENET_14,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2294 },
2295 { /* MCP55 Ethernet Controller */
2296 .vendor = PCI_VENDOR_ID_NVIDIA,
2297 .device = PCI_DEVICE_ID_NVIDIA_NVENET_15,
2298 .subvendor = PCI_ANY_ID,
2299 .subdevice = PCI_ANY_ID,
2300 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2268 }, 2301 },
2269 {0,}, 2302 {0,},
2270}; 2303};
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index b43b2b11aacd..6518334b9280 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -1,4 +1,4 @@
1/* 1/*
2 * drivers/net/gianfar.c 2 * drivers/net/gianfar.c
3 * 3 *
4 * Gianfar Ethernet Driver 4 * Gianfar Ethernet Driver
@@ -22,10 +22,9 @@
22 * B-V +1.62 22 * B-V +1.62
23 * 23 *
24 * Theory of operation 24 * Theory of operation
25 * This driver is designed for the Triple-speed Ethernet 25 * This driver is designed for the non-CPM ethernet controllers
26 * controllers on the Freescale 8540/8560 integrated processors, 26 * on the 85xx and 83xx family of integrated processors
27 * as well as the Fast Ethernet Controller on the 8540. 27 *
28 *
29 * The driver is initialized through platform_device. Structures which 28 * The driver is initialized through platform_device. Structures which
30 * define the configuration needed by the board are defined in a 29 * define the configuration needed by the board are defined in a
31 * board structure in arch/ppc/platforms (though I do not 30 * board structure in arch/ppc/platforms (though I do not
@@ -39,12 +38,12 @@
39 * 38 *
40 * The Gianfar Ethernet Controller uses a ring of buffer 39 * The Gianfar Ethernet Controller uses a ring of buffer
41 * descriptors. The beginning is indicated by a register 40 * descriptors. The beginning is indicated by a register
42 * pointing to the physical address of the start of the ring. 41 * pointing to the physical address of the start of the ring.
43 * The end is determined by a "wrap" bit being set in the 42 * The end is determined by a "wrap" bit being set in the
44 * last descriptor of the ring. 43 * last descriptor of the ring.
45 * 44 *
46 * When a packet is received, the RXF bit in the 45 * When a packet is received, the RXF bit in the
47 * IEVENT register is set, triggering an interrupt when the 46 * IEVENT register is set, triggering an interrupt when the
48 * corresponding bit in the IMASK register is also set (if 47 * corresponding bit in the IMASK register is also set (if
49 * interrupt coalescing is active, then the interrupt may not 48 * interrupt coalescing is active, then the interrupt may not
50 * happen immediately, but will wait until either a set number 49 * happen immediately, but will wait until either a set number
@@ -52,7 +51,7 @@
52 * interrupt handler will signal there is work to be done, and 51 * interrupt handler will signal there is work to be done, and
53 * exit. Without NAPI, the packet(s) will be handled 52 * exit. Without NAPI, the packet(s) will be handled
54 * immediately. Both methods will start at the last known empty 53 * immediately. Both methods will start at the last known empty
55 * descriptor, and process every subsequent descriptor until there 54 * descriptor, and process every subsequent descriptor until there
56 * are none left with data (NAPI will stop after a set number of 55 * are none left with data (NAPI will stop after a set number of
57 * packets to give time to other tasks, but will eventually 56 * packets to give time to other tasks, but will eventually
58 * process all the packets). The data arrives inside a 57 * process all the packets). The data arrives inside a
@@ -83,9 +82,13 @@
83#include <linux/netdevice.h> 82#include <linux/netdevice.h>
84#include <linux/etherdevice.h> 83#include <linux/etherdevice.h>
85#include <linux/skbuff.h> 84#include <linux/skbuff.h>
85#include <linux/if_vlan.h>
86#include <linux/spinlock.h> 86#include <linux/spinlock.h>
87#include <linux/mm.h> 87#include <linux/mm.h>
88#include <linux/device.h> 88#include <linux/device.h>
89#include <linux/ip.h>
90#include <linux/tcp.h>
91#include <linux/udp.h>
89 92
90#include <asm/io.h> 93#include <asm/io.h>
91#include <asm/irq.h> 94#include <asm/irq.h>
@@ -123,7 +126,7 @@ static int gfar_set_mac_address(struct net_device *dev);
123static int gfar_change_mtu(struct net_device *dev, int new_mtu); 126static int gfar_change_mtu(struct net_device *dev, int new_mtu);
124static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs); 127static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs);
125static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs); 128static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs);
126irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs); 129static irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs);
127static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs); 130static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs);
128static irqreturn_t phy_interrupt(int irq, void *dev_id, struct pt_regs *regs); 131static irqreturn_t phy_interrupt(int irq, void *dev_id, struct pt_regs *regs);
129static void gfar_phy_change(void *data); 132static void gfar_phy_change(void *data);
@@ -139,9 +142,12 @@ static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
139#ifdef CONFIG_GFAR_NAPI 142#ifdef CONFIG_GFAR_NAPI
140static int gfar_poll(struct net_device *dev, int *budget); 143static int gfar_poll(struct net_device *dev, int *budget);
141#endif 144#endif
142static int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); 145int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
143static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length); 146static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
144static void gfar_phy_startup_timer(unsigned long data); 147static void gfar_phy_startup_timer(unsigned long data);
148static void gfar_vlan_rx_register(struct net_device *netdev,
149 struct vlan_group *grp);
150static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
145 151
146extern struct ethtool_ops gfar_ethtool_ops; 152extern struct ethtool_ops gfar_ethtool_ops;
147 153
@@ -149,6 +155,13 @@ MODULE_AUTHOR("Freescale Semiconductor, Inc");
149MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 155MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150MODULE_LICENSE("GPL"); 156MODULE_LICENSE("GPL");
151 157
158int gfar_uses_fcb(struct gfar_private *priv)
159{
160 if (priv->vlan_enable || priv->rx_csum_enable)
161 return 1;
162 else
163 return 0;
164}
152static int gfar_probe(struct device *device) 165static int gfar_probe(struct device *device)
153{ 166{
154 u32 tempval; 167 u32 tempval;
@@ -159,7 +172,6 @@ static int gfar_probe(struct device *device)
159 struct resource *r; 172 struct resource *r;
160 int idx; 173 int idx;
161 int err = 0; 174 int err = 0;
162 int dev_ethtool_ops = 0;
163 175
164 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data; 176 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
165 177
@@ -265,15 +277,69 @@ static int gfar_probe(struct device *device)
265 dev->mtu = 1500; 277 dev->mtu = 1500;
266 dev->set_multicast_list = gfar_set_multi; 278 dev->set_multicast_list = gfar_set_multi;
267 279
268 /* Index into the array of possible ethtool 280 dev->ethtool_ops = &gfar_ethtool_ops;
269 * ops to catch all 4 possibilities */ 281
270 if((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) == 0) 282 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
271 dev_ethtool_ops += 1; 283 priv->rx_csum_enable = 1;
284 dev->features |= NETIF_F_IP_CSUM;
285 } else
286 priv->rx_csum_enable = 0;
287
288 priv->vlgrp = NULL;
272 289
273 if((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE) == 0) 290 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
274 dev_ethtool_ops += 2; 291 dev->vlan_rx_register = gfar_vlan_rx_register;
292 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
275 293
276 dev->ethtool_ops = gfar_op_array[dev_ethtool_ops]; 294 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
295
296 priv->vlan_enable = 1;
297 }
298
299 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
300 priv->extended_hash = 1;
301 priv->hash_width = 9;
302
303 priv->hash_regs[0] = &priv->regs->igaddr0;
304 priv->hash_regs[1] = &priv->regs->igaddr1;
305 priv->hash_regs[2] = &priv->regs->igaddr2;
306 priv->hash_regs[3] = &priv->regs->igaddr3;
307 priv->hash_regs[4] = &priv->regs->igaddr4;
308 priv->hash_regs[5] = &priv->regs->igaddr5;
309 priv->hash_regs[6] = &priv->regs->igaddr6;
310 priv->hash_regs[7] = &priv->regs->igaddr7;
311 priv->hash_regs[8] = &priv->regs->gaddr0;
312 priv->hash_regs[9] = &priv->regs->gaddr1;
313 priv->hash_regs[10] = &priv->regs->gaddr2;
314 priv->hash_regs[11] = &priv->regs->gaddr3;
315 priv->hash_regs[12] = &priv->regs->gaddr4;
316 priv->hash_regs[13] = &priv->regs->gaddr5;
317 priv->hash_regs[14] = &priv->regs->gaddr6;
318 priv->hash_regs[15] = &priv->regs->gaddr7;
319
320 } else {
321 priv->extended_hash = 0;
322 priv->hash_width = 8;
323
324 priv->hash_regs[0] = &priv->regs->gaddr0;
325 priv->hash_regs[1] = &priv->regs->gaddr1;
326 priv->hash_regs[2] = &priv->regs->gaddr2;
327 priv->hash_regs[3] = &priv->regs->gaddr3;
328 priv->hash_regs[4] = &priv->regs->gaddr4;
329 priv->hash_regs[5] = &priv->regs->gaddr5;
330 priv->hash_regs[6] = &priv->regs->gaddr6;
331 priv->hash_regs[7] = &priv->regs->gaddr7;
332 }
333
334 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
335 priv->padding = DEFAULT_PADDING;
336 else
337 priv->padding = 0;
338
339 dev->hard_header_len += priv->padding;
340
341 if (dev->features & NETIF_F_IP_CSUM)
342 dev->hard_header_len += GMAC_FCB_LEN;
277 343
278 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; 344 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
279#ifdef CONFIG_GFAR_BUFSTASH 345#ifdef CONFIG_GFAR_BUFSTASH
@@ -289,6 +355,9 @@ static int gfar_probe(struct device *device)
289 priv->rxcount = DEFAULT_RXCOUNT; 355 priv->rxcount = DEFAULT_RXCOUNT;
290 priv->rxtime = DEFAULT_RXTIME; 356 priv->rxtime = DEFAULT_RXTIME;
291 357
358 /* Enable most messages by default */
359 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
360
292 err = register_netdev(dev); 361 err = register_netdev(dev);
293 362
294 if (err) { 363 if (err) {
@@ -360,8 +429,9 @@ static int init_phy(struct net_device *dev)
360 GFP_KERNEL); 429 GFP_KERNEL);
361 430
362 if(NULL == mii_info) { 431 if(NULL == mii_info) {
363 printk(KERN_ERR "%s: Could not allocate mii_info\n", 432 if (netif_msg_ifup(priv))
364 dev->name); 433 printk(KERN_ERR "%s: Could not allocate mii_info\n",
434 dev->name);
365 return -ENOMEM; 435 return -ENOMEM;
366 } 436 }
367 437
@@ -410,7 +480,8 @@ static int init_phy(struct net_device *dev)
410 curphy = get_phy_info(priv->mii_info); 480 curphy = get_phy_info(priv->mii_info);
411 481
412 if (curphy == NULL) { 482 if (curphy == NULL) {
413 printk(KERN_ERR "%s: No PHY found\n", dev->name); 483 if (netif_msg_ifup(priv))
484 printk(KERN_ERR "%s: No PHY found\n", dev->name);
414 err = -1; 485 err = -1;
415 goto no_phy; 486 goto no_phy;
416 } 487 }
@@ -421,7 +492,7 @@ static int init_phy(struct net_device *dev)
421 if(curphy->init) { 492 if(curphy->init) {
422 err = curphy->init(priv->mii_info); 493 err = curphy->init(priv->mii_info);
423 494
424 if (err) 495 if (err)
425 goto phy_init_fail; 496 goto phy_init_fail;
426 } 497 }
427 498
@@ -446,14 +517,14 @@ static void init_registers(struct net_device *dev)
446 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR); 517 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
447 518
448 /* Init hash registers to zero */ 519 /* Init hash registers to zero */
449 gfar_write(&priv->regs->iaddr0, 0); 520 gfar_write(&priv->regs->igaddr0, 0);
450 gfar_write(&priv->regs->iaddr1, 0); 521 gfar_write(&priv->regs->igaddr1, 0);
451 gfar_write(&priv->regs->iaddr2, 0); 522 gfar_write(&priv->regs->igaddr2, 0);
452 gfar_write(&priv->regs->iaddr3, 0); 523 gfar_write(&priv->regs->igaddr3, 0);
453 gfar_write(&priv->regs->iaddr4, 0); 524 gfar_write(&priv->regs->igaddr4, 0);
454 gfar_write(&priv->regs->iaddr5, 0); 525 gfar_write(&priv->regs->igaddr5, 0);
455 gfar_write(&priv->regs->iaddr6, 0); 526 gfar_write(&priv->regs->igaddr6, 0);
456 gfar_write(&priv->regs->iaddr7, 0); 527 gfar_write(&priv->regs->igaddr7, 0);
457 528
458 gfar_write(&priv->regs->gaddr0, 0); 529 gfar_write(&priv->regs->gaddr0, 0);
459 gfar_write(&priv->regs->gaddr1, 0); 530 gfar_write(&priv->regs->gaddr1, 0);
@@ -464,9 +535,6 @@ static void init_registers(struct net_device *dev)
464 gfar_write(&priv->regs->gaddr6, 0); 535 gfar_write(&priv->regs->gaddr6, 0);
465 gfar_write(&priv->regs->gaddr7, 0); 536 gfar_write(&priv->regs->gaddr7, 0);
466 537
467 /* Zero out rctrl */
468 gfar_write(&priv->regs->rctrl, 0x00000000);
469
470 /* Zero out the rmon mib registers if it has them */ 538 /* Zero out the rmon mib registers if it has them */
471 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 539 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
472 memset((void *) &(priv->regs->rmon), 0, 540 memset((void *) &(priv->regs->rmon), 0,
@@ -497,20 +565,14 @@ static void init_registers(struct net_device *dev)
497 gfar_write(&priv->regs->tbipa, TBIPA_VALUE); 565 gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
498} 566}
499 567
500void stop_gfar(struct net_device *dev) 568
569/* Halt the receive and transmit queues */
570void gfar_halt(struct net_device *dev)
501{ 571{
502 struct gfar_private *priv = netdev_priv(dev); 572 struct gfar_private *priv = netdev_priv(dev);
503 struct gfar *regs = priv->regs; 573 struct gfar *regs = priv->regs;
504 unsigned long flags;
505 u32 tempval; 574 u32 tempval;
506 575
507 /* Lock it down */
508 spin_lock_irqsave(&priv->lock, flags);
509
510 /* Tell the kernel the link is down */
511 priv->mii_info->link = 0;
512 adjust_link(dev);
513
514 /* Mask all interrupts */ 576 /* Mask all interrupts */
515 gfar_write(&regs->imask, IMASK_INIT_CLEAR); 577 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
516 578
@@ -533,13 +595,29 @@ void stop_gfar(struct net_device *dev)
533 tempval = gfar_read(&regs->maccfg1); 595 tempval = gfar_read(&regs->maccfg1);
534 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 596 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
535 gfar_write(&regs->maccfg1, tempval); 597 gfar_write(&regs->maccfg1, tempval);
598}
599
600void stop_gfar(struct net_device *dev)
601{
602 struct gfar_private *priv = netdev_priv(dev);
603 struct gfar *regs = priv->regs;
604 unsigned long flags;
605
606 /* Lock it down */
607 spin_lock_irqsave(&priv->lock, flags);
608
609 /* Tell the kernel the link is down */
610 priv->mii_info->link = 0;
611 adjust_link(dev);
612
613 gfar_halt(dev);
536 614
537 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) { 615 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) {
538 /* Clear any pending interrupts */ 616 /* Clear any pending interrupts */
539 mii_clear_phy_interrupt(priv->mii_info); 617 mii_clear_phy_interrupt(priv->mii_info);
540 618
541 /* Disable PHY Interrupts */ 619 /* Disable PHY Interrupts */
542 mii_configure_phy_interrupt(priv->mii_info, 620 mii_configure_phy_interrupt(priv->mii_info,
543 MII_INTERRUPT_DISABLED); 621 MII_INTERRUPT_DISABLED);
544 } 622 }
545 623
@@ -566,7 +644,7 @@ void stop_gfar(struct net_device *dev)
566 sizeof(struct txbd8)*priv->tx_ring_size 644 sizeof(struct txbd8)*priv->tx_ring_size
567 + sizeof(struct rxbd8)*priv->rx_ring_size, 645 + sizeof(struct rxbd8)*priv->rx_ring_size,
568 priv->tx_bd_base, 646 priv->tx_bd_base,
569 gfar_read(&regs->tbase)); 647 gfar_read(&regs->tbase0));
570} 648}
571 649
572/* If there are any tx skbs or rx skbs still around, free them. 650/* If there are any tx skbs or rx skbs still around, free them.
@@ -620,6 +698,34 @@ void free_skb_resources(struct gfar_private *priv)
620 } 698 }
621} 699}
622 700
701void gfar_start(struct net_device *dev)
702{
703 struct gfar_private *priv = netdev_priv(dev);
704 struct gfar *regs = priv->regs;
705 u32 tempval;
706
707 /* Enable Rx and Tx in MACCFG1 */
708 tempval = gfar_read(&regs->maccfg1);
709 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
710 gfar_write(&regs->maccfg1, tempval);
711
712 /* Initialize DMACTRL to have WWR and WOP */
713 tempval = gfar_read(&priv->regs->dmactrl);
714 tempval |= DMACTRL_INIT_SETTINGS;
715 gfar_write(&priv->regs->dmactrl, tempval);
716
717 /* Clear THLT, so that the DMA starts polling now */
718 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
719
720 /* Make sure we aren't stopped */
721 tempval = gfar_read(&priv->regs->dmactrl);
722 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
723 gfar_write(&priv->regs->dmactrl, tempval);
724
725 /* Unmask the interrupts we look for */
726 gfar_write(&regs->imask, IMASK_DEFAULT);
727}
728
623/* Bring the controller up and running */ 729/* Bring the controller up and running */
624int startup_gfar(struct net_device *dev) 730int startup_gfar(struct net_device *dev)
625{ 731{
@@ -630,33 +736,34 @@ int startup_gfar(struct net_device *dev)
630 int i; 736 int i;
631 struct gfar_private *priv = netdev_priv(dev); 737 struct gfar_private *priv = netdev_priv(dev);
632 struct gfar *regs = priv->regs; 738 struct gfar *regs = priv->regs;
633 u32 tempval;
634 int err = 0; 739 int err = 0;
740 u32 rctrl = 0;
635 741
636 gfar_write(&regs->imask, IMASK_INIT_CLEAR); 742 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
637 743
638 /* Allocate memory for the buffer descriptors */ 744 /* Allocate memory for the buffer descriptors */
639 vaddr = (unsigned long) dma_alloc_coherent(NULL, 745 vaddr = (unsigned long) dma_alloc_coherent(NULL,
640 sizeof (struct txbd8) * priv->tx_ring_size + 746 sizeof (struct txbd8) * priv->tx_ring_size +
641 sizeof (struct rxbd8) * priv->rx_ring_size, 747 sizeof (struct rxbd8) * priv->rx_ring_size,
642 &addr, GFP_KERNEL); 748 &addr, GFP_KERNEL);
643 749
644 if (vaddr == 0) { 750 if (vaddr == 0) {
645 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n", 751 if (netif_msg_ifup(priv))
646 dev->name); 752 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
753 dev->name);
647 return -ENOMEM; 754 return -ENOMEM;
648 } 755 }
649 756
650 priv->tx_bd_base = (struct txbd8 *) vaddr; 757 priv->tx_bd_base = (struct txbd8 *) vaddr;
651 758
652 /* enet DMA only understands physical addresses */ 759 /* enet DMA only understands physical addresses */
653 gfar_write(&regs->tbase, addr); 760 gfar_write(&regs->tbase0, addr);
654 761
655 /* Start the rx descriptor ring where the tx ring leaves off */ 762 /* Start the rx descriptor ring where the tx ring leaves off */
656 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size; 763 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
657 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size; 764 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
658 priv->rx_bd_base = (struct rxbd8 *) vaddr; 765 priv->rx_bd_base = (struct rxbd8 *) vaddr;
659 gfar_write(&regs->rbase, addr); 766 gfar_write(&regs->rbase0, addr);
660 767
661 /* Setup the skbuff rings */ 768 /* Setup the skbuff rings */
662 priv->tx_skbuff = 769 priv->tx_skbuff =
@@ -664,8 +771,9 @@ int startup_gfar(struct net_device *dev)
664 priv->tx_ring_size, GFP_KERNEL); 771 priv->tx_ring_size, GFP_KERNEL);
665 772
666 if (priv->tx_skbuff == NULL) { 773 if (priv->tx_skbuff == NULL) {
667 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n", 774 if (netif_msg_ifup(priv))
668 dev->name); 775 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
776 dev->name);
669 err = -ENOMEM; 777 err = -ENOMEM;
670 goto tx_skb_fail; 778 goto tx_skb_fail;
671 } 779 }
@@ -678,8 +786,9 @@ int startup_gfar(struct net_device *dev)
678 priv->rx_ring_size, GFP_KERNEL); 786 priv->rx_ring_size, GFP_KERNEL);
679 787
680 if (priv->rx_skbuff == NULL) { 788 if (priv->rx_skbuff == NULL) {
681 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n", 789 if (netif_msg_ifup(priv))
682 dev->name); 790 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
791 dev->name);
683 err = -ENOMEM; 792 err = -ENOMEM;
684 goto rx_skb_fail; 793 goto rx_skb_fail;
685 } 794 }
@@ -726,12 +835,13 @@ int startup_gfar(struct net_device *dev)
726 /* If the device has multiple interrupts, register for 835 /* If the device has multiple interrupts, register for
727 * them. Otherwise, only register for the one */ 836 * them. Otherwise, only register for the one */
728 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 837 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
729 /* Install our interrupt handlers for Error, 838 /* Install our interrupt handlers for Error,
730 * Transmit, and Receive */ 839 * Transmit, and Receive */
731 if (request_irq(priv->interruptError, gfar_error, 840 if (request_irq(priv->interruptError, gfar_error,
732 0, "enet_error", dev) < 0) { 841 0, "enet_error", dev) < 0) {
733 printk(KERN_ERR "%s: Can't get IRQ %d\n", 842 if (netif_msg_intr(priv))
734 dev->name, priv->interruptError); 843 printk(KERN_ERR "%s: Can't get IRQ %d\n",
844 dev->name, priv->interruptError);
735 845
736 err = -1; 846 err = -1;
737 goto err_irq_fail; 847 goto err_irq_fail;
@@ -739,8 +849,9 @@ int startup_gfar(struct net_device *dev)
739 849
740 if (request_irq(priv->interruptTransmit, gfar_transmit, 850 if (request_irq(priv->interruptTransmit, gfar_transmit,
741 0, "enet_tx", dev) < 0) { 851 0, "enet_tx", dev) < 0) {
742 printk(KERN_ERR "%s: Can't get IRQ %d\n", 852 if (netif_msg_intr(priv))
743 dev->name, priv->interruptTransmit); 853 printk(KERN_ERR "%s: Can't get IRQ %d\n",
854 dev->name, priv->interruptTransmit);
744 855
745 err = -1; 856 err = -1;
746 857
@@ -749,8 +860,9 @@ int startup_gfar(struct net_device *dev)
749 860
750 if (request_irq(priv->interruptReceive, gfar_receive, 861 if (request_irq(priv->interruptReceive, gfar_receive,
751 0, "enet_rx", dev) < 0) { 862 0, "enet_rx", dev) < 0) {
752 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n", 863 if (netif_msg_intr(priv))
753 dev->name, priv->interruptReceive); 864 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
865 dev->name, priv->interruptReceive);
754 866
755 err = -1; 867 err = -1;
756 goto rx_irq_fail; 868 goto rx_irq_fail;
@@ -758,8 +870,9 @@ int startup_gfar(struct net_device *dev)
758 } else { 870 } else {
759 if (request_irq(priv->interruptTransmit, gfar_interrupt, 871 if (request_irq(priv->interruptTransmit, gfar_interrupt,
760 0, "gfar_interrupt", dev) < 0) { 872 0, "gfar_interrupt", dev) < 0) {
761 printk(KERN_ERR "%s: Can't get IRQ %d\n", 873 if (netif_msg_intr(priv))
762 dev->name, priv->interruptError); 874 printk(KERN_ERR "%s: Can't get IRQ %d\n",
875 dev->name, priv->interruptError);
763 876
764 err = -1; 877 err = -1;
765 goto err_irq_fail; 878 goto err_irq_fail;
@@ -787,28 +900,22 @@ int startup_gfar(struct net_device *dev)
787 else 900 else
788 gfar_write(&regs->rxic, 0); 901 gfar_write(&regs->rxic, 0);
789 902
790 init_waitqueue_head(&priv->rxcleanupq); 903 if (priv->rx_csum_enable)
904 rctrl |= RCTRL_CHECKSUMMING;
791 905
792 /* Enable Rx and Tx in MACCFG1 */ 906 if (priv->extended_hash)
793 tempval = gfar_read(&regs->maccfg1); 907 rctrl |= RCTRL_EXTHASH;
794 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
795 gfar_write(&regs->maccfg1, tempval);
796 908
797 /* Initialize DMACTRL to have WWR and WOP */ 909 if (priv->vlan_enable)
798 tempval = gfar_read(&priv->regs->dmactrl); 910 rctrl |= RCTRL_VLAN;
799 tempval |= DMACTRL_INIT_SETTINGS;
800 gfar_write(&priv->regs->dmactrl, tempval);
801 911
802 /* Clear THLT, so that the DMA starts polling now */ 912 /* Init rctrl based on our settings */
803 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT); 913 gfar_write(&priv->regs->rctrl, rctrl);
804 914
805 /* Make sure we aren't stopped */ 915 if (dev->features & NETIF_F_IP_CSUM)
806 tempval = gfar_read(&priv->regs->dmactrl); 916 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
807 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
808 gfar_write(&priv->regs->dmactrl, tempval);
809 917
810 /* Unmask the interrupts we look for */ 918 gfar_start(dev);
811 gfar_write(&regs->imask, IMASK_DEFAULT);
812 919
813 return 0; 920 return 0;
814 921
@@ -824,7 +931,7 @@ tx_skb_fail:
824 sizeof(struct txbd8)*priv->tx_ring_size 931 sizeof(struct txbd8)*priv->tx_ring_size
825 + sizeof(struct rxbd8)*priv->rx_ring_size, 932 + sizeof(struct rxbd8)*priv->rx_ring_size,
826 priv->tx_bd_base, 933 priv->tx_bd_base,
827 gfar_read(&regs->tbase)); 934 gfar_read(&regs->tbase0));
828 935
829 if (priv->mii_info->phyinfo->close) 936 if (priv->mii_info->phyinfo->close)
830 priv->mii_info->phyinfo->close(priv->mii_info); 937 priv->mii_info->phyinfo->close(priv->mii_info);
@@ -857,11 +964,62 @@ static int gfar_enet_open(struct net_device *dev)
857 return err; 964 return err;
858} 965}
859 966
967static struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
968{
969 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
970
971 memset(fcb, 0, GMAC_FCB_LEN);
972
973 /* Flag the bd so the controller looks for the FCB */
974 bdp->status |= TXBD_TOE;
975
976 return fcb;
977}
978
979static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
980{
981 int len;
982
983 /* If we're here, it's a IP packet with a TCP or UDP
984 * payload. We set it to checksum, using a pseudo-header
985 * we provide
986 */
987 fcb->ip = 1;
988 fcb->tup = 1;
989 fcb->ctu = 1;
990 fcb->nph = 1;
991
992 /* Notify the controller what the protocol is */
993 if (skb->nh.iph->protocol == IPPROTO_UDP)
994 fcb->udp = 1;
995
996 /* l3os is the distance between the start of the
997 * frame (skb->data) and the start of the IP hdr.
998 * l4os is the distance between the start of the
999 * l3 hdr and the l4 hdr */
1000 fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
1001 fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
1002
1003 len = skb->nh.iph->tot_len - fcb->l4os;
1004
1005 /* Provide the pseudoheader csum */
1006 fcb->phcs = ~csum_tcpudp_magic(skb->nh.iph->saddr,
1007 skb->nh.iph->daddr, len,
1008 skb->nh.iph->protocol, 0);
1009}
1010
1011void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1012{
1013 fcb->vln = 1;
1014 fcb->vlctl = vlan_tx_tag_get(skb);
1015}
1016
860/* This is called by the kernel when a frame is ready for transmission. */ 1017/* This is called by the kernel when a frame is ready for transmission. */
861/* It is pointed to by the dev->hard_start_xmit function pointer */ 1018/* It is pointed to by the dev->hard_start_xmit function pointer */
862static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 1019static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
863{ 1020{
864 struct gfar_private *priv = netdev_priv(dev); 1021 struct gfar_private *priv = netdev_priv(dev);
1022 struct txfcb *fcb = NULL;
865 struct txbd8 *txbdp; 1023 struct txbd8 *txbdp;
866 1024
867 /* Update transmit stats */ 1025 /* Update transmit stats */
@@ -876,9 +1034,24 @@ static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
876 /* Clear all but the WRAP status flags */ 1034 /* Clear all but the WRAP status flags */
877 txbdp->status &= TXBD_WRAP; 1035 txbdp->status &= TXBD_WRAP;
878 1036
1037 /* Set up checksumming */
1038 if ((dev->features & NETIF_F_IP_CSUM)
1039 && (CHECKSUM_HW == skb->ip_summed)) {
1040 fcb = gfar_add_fcb(skb, txbdp);
1041 gfar_tx_checksum(skb, fcb);
1042 }
1043
1044 if (priv->vlan_enable &&
1045 unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1046 if (NULL == fcb)
1047 fcb = gfar_add_fcb(skb, txbdp);
1048
1049 gfar_tx_vlan(skb, fcb);
1050 }
1051
879 /* Set buffer length and pointer */ 1052 /* Set buffer length and pointer */
880 txbdp->length = skb->len; 1053 txbdp->length = skb->len;
881 txbdp->bufPtr = dma_map_single(NULL, skb->data, 1054 txbdp->bufPtr = dma_map_single(NULL, skb->data,
882 skb->len, DMA_TO_DEVICE); 1055 skb->len, DMA_TO_DEVICE);
883 1056
884 /* Save the skb pointer so we can free it later */ 1057 /* Save the skb pointer so we can free it later */
@@ -972,15 +1145,78 @@ int gfar_set_mac_address(struct net_device *dev)
972} 1145}
973 1146
974 1147
1148/* Enables and disables VLAN insertion/extraction */
1149static void gfar_vlan_rx_register(struct net_device *dev,
1150 struct vlan_group *grp)
1151{
1152 struct gfar_private *priv = netdev_priv(dev);
1153 unsigned long flags;
1154 u32 tempval;
1155
1156 spin_lock_irqsave(&priv->lock, flags);
1157
1158 priv->vlgrp = grp;
1159
1160 if (grp) {
1161 /* Enable VLAN tag insertion */
1162 tempval = gfar_read(&priv->regs->tctrl);
1163 tempval |= TCTRL_VLINS;
1164
1165 gfar_write(&priv->regs->tctrl, tempval);
1166
1167 /* Enable VLAN tag extraction */
1168 tempval = gfar_read(&priv->regs->rctrl);
1169 tempval |= RCTRL_VLEX;
1170 gfar_write(&priv->regs->rctrl, tempval);
1171 } else {
1172 /* Disable VLAN tag insertion */
1173 tempval = gfar_read(&priv->regs->tctrl);
1174 tempval &= ~TCTRL_VLINS;
1175 gfar_write(&priv->regs->tctrl, tempval);
1176
1177 /* Disable VLAN tag extraction */
1178 tempval = gfar_read(&priv->regs->rctrl);
1179 tempval &= ~RCTRL_VLEX;
1180 gfar_write(&priv->regs->rctrl, tempval);
1181 }
1182
1183 spin_unlock_irqrestore(&priv->lock, flags);
1184}
1185
1186
1187static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1188{
1189 struct gfar_private *priv = netdev_priv(dev);
1190 unsigned long flags;
1191
1192 spin_lock_irqsave(&priv->lock, flags);
1193
1194 if (priv->vlgrp)
1195 priv->vlgrp->vlan_devices[vid] = NULL;
1196
1197 spin_unlock_irqrestore(&priv->lock, flags);
1198}
1199
1200
975static int gfar_change_mtu(struct net_device *dev, int new_mtu) 1201static int gfar_change_mtu(struct net_device *dev, int new_mtu)
976{ 1202{
977 int tempsize, tempval; 1203 int tempsize, tempval;
978 struct gfar_private *priv = netdev_priv(dev); 1204 struct gfar_private *priv = netdev_priv(dev);
979 int oldsize = priv->rx_buffer_size; 1205 int oldsize = priv->rx_buffer_size;
980 int frame_size = new_mtu + 18; 1206 int frame_size = new_mtu + ETH_HLEN;
1207
1208 if (priv->vlan_enable)
1209 frame_size += VLAN_ETH_HLEN;
1210
1211 if (gfar_uses_fcb(priv))
1212 frame_size += GMAC_FCB_LEN;
1213
1214 frame_size += priv->padding;
981 1215
982 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { 1216 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
983 printk(KERN_ERR "%s: Invalid MTU setting\n", dev->name); 1217 if (netif_msg_drv(priv))
1218 printk(KERN_ERR "%s: Invalid MTU setting\n",
1219 dev->name);
984 return -EINVAL; 1220 return -EINVAL;
985 } 1221 }
986 1222
@@ -1120,7 +1356,7 @@ struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1120 skb->dev = dev; 1356 skb->dev = dev;
1121 1357
1122 bdp->bufPtr = dma_map_single(NULL, skb->data, 1358 bdp->bufPtr = dma_map_single(NULL, skb->data,
1123 priv->rx_buffer_size + RXBUF_ALIGNMENT, 1359 priv->rx_buffer_size + RXBUF_ALIGNMENT,
1124 DMA_FROM_DEVICE); 1360 DMA_FROM_DEVICE);
1125 1361
1126 bdp->length = 0; 1362 bdp->length = 0;
@@ -1190,11 +1426,10 @@ irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1190 1426
1191 __netif_rx_schedule(dev); 1427 __netif_rx_schedule(dev);
1192 } else { 1428 } else {
1193#ifdef VERBOSE_GFAR_ERRORS 1429 if (netif_msg_rx_err(priv))
1194 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n", 1430 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1195 dev->name, gfar_read(&priv->regs->ievent), 1431 dev->name, gfar_read(&priv->regs->ievent),
1196 gfar_read(&priv->regs->imask)); 1432 gfar_read(&priv->regs->imask));
1197#endif
1198 } 1433 }
1199#else 1434#else
1200 1435
@@ -1209,15 +1444,43 @@ irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1209 else 1444 else
1210 gfar_write(&priv->regs->rxic, 0); 1445 gfar_write(&priv->regs->rxic, 0);
1211 1446
1212 /* Just in case we need to wake the ring param changer */
1213 priv->rxclean = 1;
1214
1215 spin_unlock(&priv->lock); 1447 spin_unlock(&priv->lock);
1216#endif 1448#endif
1217 1449
1218 return IRQ_HANDLED; 1450 return IRQ_HANDLED;
1219} 1451}
1220 1452
1453static inline int gfar_rx_vlan(struct sk_buff *skb,
1454 struct vlan_group *vlgrp, unsigned short vlctl)
1455{
1456#ifdef CONFIG_GFAR_NAPI
1457 return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1458#else
1459 return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1460#endif
1461}
1462
1463static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1464{
1465 /* If valid headers were found, and valid sums
1466 * were verified, then we tell the kernel that no
1467 * checksumming is necessary. Otherwise, it is */
1468 if (fcb->cip && !fcb->eip && fcb->ctu && !fcb->etu)
1469 skb->ip_summed = CHECKSUM_UNNECESSARY;
1470 else
1471 skb->ip_summed = CHECKSUM_NONE;
1472}
1473
1474
1475static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1476{
1477 struct rxfcb *fcb = (struct rxfcb *)skb->data;
1478
1479 /* Remove the FCB from the skb */
1480 skb_pull(skb, GMAC_FCB_LEN);
1481
1482 return fcb;
1483}
1221 1484
1222/* gfar_process_frame() -- handle one incoming packet if skb 1485/* gfar_process_frame() -- handle one incoming packet if skb
1223 * isn't NULL. */ 1486 * isn't NULL. */
@@ -1225,35 +1488,51 @@ static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1225 int length) 1488 int length)
1226{ 1489{
1227 struct gfar_private *priv = netdev_priv(dev); 1490 struct gfar_private *priv = netdev_priv(dev);
1491 struct rxfcb *fcb = NULL;
1228 1492
1229 if (skb == NULL) { 1493 if (skb == NULL) {
1230#ifdef BRIEF_GFAR_ERRORS 1494 if (netif_msg_rx_err(priv))
1231 printk(KERN_WARNING "%s: Missing skb!!.\n", 1495 printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1232 dev->name);
1233#endif
1234 priv->stats.rx_dropped++; 1496 priv->stats.rx_dropped++;
1235 priv->extra_stats.rx_skbmissing++; 1497 priv->extra_stats.rx_skbmissing++;
1236 } else { 1498 } else {
1499 int ret;
1500
1237 /* Prep the skb for the packet */ 1501 /* Prep the skb for the packet */
1238 skb_put(skb, length); 1502 skb_put(skb, length);
1239 1503
1504 /* Grab the FCB if there is one */
1505 if (gfar_uses_fcb(priv))
1506 fcb = gfar_get_fcb(skb);
1507
1508 /* Remove the padded bytes, if there are any */
1509 if (priv->padding)
1510 skb_pull(skb, priv->padding);
1511
1512 if (priv->rx_csum_enable)
1513 gfar_rx_checksum(skb, fcb);
1514
1240 /* Tell the skb what kind of packet this is */ 1515 /* Tell the skb what kind of packet this is */
1241 skb->protocol = eth_type_trans(skb, dev); 1516 skb->protocol = eth_type_trans(skb, dev);
1242 1517
1243 /* Send the packet up the stack */ 1518 /* Send the packet up the stack */
1244 if (RECEIVE(skb) == NET_RX_DROP) { 1519 if (unlikely(priv->vlgrp && fcb->vln))
1520 ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1521 else
1522 ret = RECEIVE(skb);
1523
1524 if (NET_RX_DROP == ret)
1245 priv->extra_stats.kernel_dropped++; 1525 priv->extra_stats.kernel_dropped++;
1246 }
1247 } 1526 }
1248 1527
1249 return 0; 1528 return 0;
1250} 1529}
1251 1530
1252/* gfar_clean_rx_ring() -- Processes each frame in the rx ring 1531/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1253 * until the budget/quota has been reached. Returns the number 1532 * until the budget/quota has been reached. Returns the number
1254 * of frames handled 1533 * of frames handled
1255 */ 1534 */
1256static int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) 1535int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1257{ 1536{
1258 struct rxbd8 *bdp; 1537 struct rxbd8 *bdp;
1259 struct sk_buff *skb; 1538 struct sk_buff *skb;
@@ -1355,9 +1634,6 @@ static int gfar_poll(struct net_device *dev, int *budget)
1355 mk_ic_value(priv->rxcount, priv->rxtime)); 1634 mk_ic_value(priv->rxcount, priv->rxtime));
1356 else 1635 else
1357 gfar_write(&priv->regs->rxic, 0); 1636 gfar_write(&priv->regs->rxic, 0);
1358
1359 /* Signal to the ring size changer that it's safe to go */
1360 priv->rxclean = 1;
1361 } 1637 }
1362 1638
1363 return (rx_work_limit < 0) ? 1 : 0; 1639 return (rx_work_limit < 0) ? 1 : 0;
@@ -1393,10 +1669,8 @@ static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1393 if (events & IEVENT_CRL) 1669 if (events & IEVENT_CRL)
1394 priv->stats.tx_aborted_errors++; 1670 priv->stats.tx_aborted_errors++;
1395 if (events & IEVENT_XFUN) { 1671 if (events & IEVENT_XFUN) {
1396#ifdef VERBOSE_GFAR_ERRORS 1672 if (netif_msg_tx_err(priv))
1397 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", 1673 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1398 dev->name);
1399#endif
1400 priv->stats.tx_dropped++; 1674 priv->stats.tx_dropped++;
1401 priv->extra_stats.tx_underrun++; 1675 priv->extra_stats.tx_underrun++;
1402 1676
@@ -1415,36 +1689,30 @@ static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1415 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); 1689 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1416#endif 1690#endif
1417 1691
1418#ifdef VERBOSE_GFAR_ERRORS 1692 if (netif_msg_rx_err(priv))
1419 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n", dev->name, 1693 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1420 gfar_read(&priv->regs->rstat)); 1694 dev->name,
1421#endif 1695 gfar_read(&priv->regs->rstat));
1422 } 1696 }
1423 if (events & IEVENT_BABR) { 1697 if (events & IEVENT_BABR) {
1424 priv->stats.rx_errors++; 1698 priv->stats.rx_errors++;
1425 priv->extra_stats.rx_babr++; 1699 priv->extra_stats.rx_babr++;
1426 1700
1427#ifdef VERBOSE_GFAR_ERRORS 1701 if (netif_msg_rx_err(priv))
1428 printk(KERN_DEBUG "%s: babbling error\n", dev->name); 1702 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1429#endif
1430 } 1703 }
1431 if (events & IEVENT_EBERR) { 1704 if (events & IEVENT_EBERR) {
1432 priv->extra_stats.eberr++; 1705 priv->extra_stats.eberr++;
1433#ifdef VERBOSE_GFAR_ERRORS 1706 if (netif_msg_rx_err(priv))
1434 printk(KERN_DEBUG "%s: EBERR\n", dev->name); 1707 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1435#endif
1436 }
1437 if (events & IEVENT_RXC) {
1438#ifdef VERBOSE_GFAR_ERRORS
1439 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1440#endif
1441 } 1708 }
1709 if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1710 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1442 1711
1443 if (events & IEVENT_BABT) { 1712 if (events & IEVENT_BABT) {
1444 priv->extra_stats.tx_babt++; 1713 priv->extra_stats.tx_babt++;
1445#ifdef VERBOSE_GFAR_ERRORS 1714 if (netif_msg_rx_err(priv))
1446 printk(KERN_DEBUG "%s: babt error\n", dev->name); 1715 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1447#endif
1448 } 1716 }
1449 1717
1450 return IRQ_HANDLED; 1718 return IRQ_HANDLED;
@@ -1510,7 +1778,7 @@ static void gfar_phy_timer(unsigned long data)
1510 * If, after GFAR_AN_TIMEOUT seconds, it has not 1778 * If, after GFAR_AN_TIMEOUT seconds, it has not
1511 * finished, we switch to forced. 1779 * finished, we switch to forced.
1512 * Either way, once the process has completed, we either 1780 * Either way, once the process has completed, we either
1513 * request the interrupt, or switch the timer over to 1781 * request the interrupt, or switch the timer over to
1514 * using gfar_phy_timer to check status */ 1782 * using gfar_phy_timer to check status */
1515static void gfar_phy_startup_timer(unsigned long data) 1783static void gfar_phy_startup_timer(unsigned long data)
1516{ 1784{
@@ -1535,8 +1803,9 @@ static void gfar_phy_startup_timer(unsigned long data)
1535 1803
1536 /* Forcing failed! Give up */ 1804 /* Forcing failed! Give up */
1537 if(result) { 1805 if(result) {
1538 printk(KERN_ERR "%s: Forcing failed!\n", 1806 if (netif_msg_link(priv))
1539 mii_info->dev->name); 1807 printk(KERN_ERR "%s: Forcing failed!\n",
1808 mii_info->dev->name);
1540 return; 1809 return;
1541 } 1810 }
1542 } 1811 }
@@ -1546,16 +1815,17 @@ static void gfar_phy_startup_timer(unsigned long data)
1546 1815
1547 /* Grab the PHY interrupt, if necessary/possible */ 1816 /* Grab the PHY interrupt, if necessary/possible */
1548 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) { 1817 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) {
1549 if (request_irq(priv->einfo->interruptPHY, 1818 if (request_irq(priv->einfo->interruptPHY,
1550 phy_interrupt, 1819 phy_interrupt,
1551 SA_SHIRQ, 1820 SA_SHIRQ,
1552 "phy_interrupt", 1821 "phy_interrupt",
1553 mii_info->dev) < 0) { 1822 mii_info->dev) < 0) {
1554 printk(KERN_ERR "%s: Can't get IRQ %d (PHY)\n", 1823 if (netif_msg_intr(priv))
1555 mii_info->dev->name, 1824 printk(KERN_ERR "%s: Can't get IRQ %d (PHY)\n",
1825 mii_info->dev->name,
1556 priv->einfo->interruptPHY); 1826 priv->einfo->interruptPHY);
1557 } else { 1827 } else {
1558 mii_configure_phy_interrupt(priv->mii_info, 1828 mii_configure_phy_interrupt(priv->mii_info,
1559 MII_INTERRUPT_ENABLED); 1829 MII_INTERRUPT_ENABLED);
1560 return; 1830 return;
1561 } 1831 }
@@ -1592,15 +1862,17 @@ static void adjust_link(struct net_device *dev)
1592 tempval &= ~(MACCFG2_FULL_DUPLEX); 1862 tempval &= ~(MACCFG2_FULL_DUPLEX);
1593 gfar_write(&regs->maccfg2, tempval); 1863 gfar_write(&regs->maccfg2, tempval);
1594 1864
1595 printk(KERN_INFO "%s: Half Duplex\n", 1865 if (netif_msg_link(priv))
1596 dev->name); 1866 printk(KERN_INFO "%s: Half Duplex\n",
1867 dev->name);
1597 } else { 1868 } else {
1598 tempval = gfar_read(&regs->maccfg2); 1869 tempval = gfar_read(&regs->maccfg2);
1599 tempval |= MACCFG2_FULL_DUPLEX; 1870 tempval |= MACCFG2_FULL_DUPLEX;
1600 gfar_write(&regs->maccfg2, tempval); 1871 gfar_write(&regs->maccfg2, tempval);
1601 1872
1602 printk(KERN_INFO "%s: Full Duplex\n", 1873 if (netif_msg_link(priv))
1603 dev->name); 1874 printk(KERN_INFO "%s: Full Duplex\n",
1875 dev->name);
1604 } 1876 }
1605 1877
1606 priv->oldduplex = mii_info->duplex; 1878 priv->oldduplex = mii_info->duplex;
@@ -1622,27 +1894,32 @@ static void adjust_link(struct net_device *dev)
1622 gfar_write(&regs->maccfg2, tempval); 1894 gfar_write(&regs->maccfg2, tempval);
1623 break; 1895 break;
1624 default: 1896 default:
1625 printk(KERN_WARNING 1897 if (netif_msg_link(priv))
1626 "%s: Ack! Speed (%d) is not 10/100/1000!\n", 1898 printk(KERN_WARNING
1627 dev->name, mii_info->speed); 1899 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1900 dev->name, mii_info->speed);
1628 break; 1901 break;
1629 } 1902 }
1630 1903
1631 printk(KERN_INFO "%s: Speed %dBT\n", dev->name, 1904 if (netif_msg_link(priv))
1632 mii_info->speed); 1905 printk(KERN_INFO "%s: Speed %dBT\n", dev->name,
1906 mii_info->speed);
1633 1907
1634 priv->oldspeed = mii_info->speed; 1908 priv->oldspeed = mii_info->speed;
1635 } 1909 }
1636 1910
1637 if (!priv->oldlink) { 1911 if (!priv->oldlink) {
1638 printk(KERN_INFO "%s: Link is up\n", dev->name); 1912 if (netif_msg_link(priv))
1913 printk(KERN_INFO "%s: Link is up\n", dev->name);
1639 priv->oldlink = 1; 1914 priv->oldlink = 1;
1640 netif_carrier_on(dev); 1915 netif_carrier_on(dev);
1641 netif_schedule(dev); 1916 netif_schedule(dev);
1642 } 1917 }
1643 } else { 1918 } else {
1644 if (priv->oldlink) { 1919 if (priv->oldlink) {
1645 printk(KERN_INFO "%s: Link is down\n", dev->name); 1920 if (netif_msg_link(priv))
1921 printk(KERN_INFO "%s: Link is down\n",
1922 dev->name);
1646 priv->oldlink = 0; 1923 priv->oldlink = 0;
1647 priv->oldspeed = 0; 1924 priv->oldspeed = 0;
1648 priv->oldduplex = -1; 1925 priv->oldduplex = -1;
@@ -1664,8 +1941,9 @@ static void gfar_set_multi(struct net_device *dev)
1664 u32 tempval; 1941 u32 tempval;
1665 1942
1666 if(dev->flags & IFF_PROMISC) { 1943 if(dev->flags & IFF_PROMISC) {
1667 printk(KERN_INFO "%s: Entering promiscuous mode.\n", 1944 if (netif_msg_drv(priv))
1668 dev->name); 1945 printk(KERN_INFO "%s: Entering promiscuous mode.\n",
1946 dev->name);
1669 /* Set RCTRL to PROM */ 1947 /* Set RCTRL to PROM */
1670 tempval = gfar_read(&regs->rctrl); 1948 tempval = gfar_read(&regs->rctrl);
1671 tempval |= RCTRL_PROM; 1949 tempval |= RCTRL_PROM;
@@ -1679,6 +1957,14 @@ static void gfar_set_multi(struct net_device *dev)
1679 1957
1680 if(dev->flags & IFF_ALLMULTI) { 1958 if(dev->flags & IFF_ALLMULTI) {
1681 /* Set the hash to rx all multicast frames */ 1959 /* Set the hash to rx all multicast frames */
1960 gfar_write(&regs->igaddr0, 0xffffffff);
1961 gfar_write(&regs->igaddr1, 0xffffffff);
1962 gfar_write(&regs->igaddr2, 0xffffffff);
1963 gfar_write(&regs->igaddr3, 0xffffffff);
1964 gfar_write(&regs->igaddr4, 0xffffffff);
1965 gfar_write(&regs->igaddr5, 0xffffffff);
1966 gfar_write(&regs->igaddr6, 0xffffffff);
1967 gfar_write(&regs->igaddr7, 0xffffffff);
1682 gfar_write(&regs->gaddr0, 0xffffffff); 1968 gfar_write(&regs->gaddr0, 0xffffffff);
1683 gfar_write(&regs->gaddr1, 0xffffffff); 1969 gfar_write(&regs->gaddr1, 0xffffffff);
1684 gfar_write(&regs->gaddr2, 0xffffffff); 1970 gfar_write(&regs->gaddr2, 0xffffffff);
@@ -1689,6 +1975,14 @@ static void gfar_set_multi(struct net_device *dev)
1689 gfar_write(&regs->gaddr7, 0xffffffff); 1975 gfar_write(&regs->gaddr7, 0xffffffff);
1690 } else { 1976 } else {
1691 /* zero out the hash */ 1977 /* zero out the hash */
1978 gfar_write(&regs->igaddr0, 0x0);
1979 gfar_write(&regs->igaddr1, 0x0);
1980 gfar_write(&regs->igaddr2, 0x0);
1981 gfar_write(&regs->igaddr3, 0x0);
1982 gfar_write(&regs->igaddr4, 0x0);
1983 gfar_write(&regs->igaddr5, 0x0);
1984 gfar_write(&regs->igaddr6, 0x0);
1985 gfar_write(&regs->igaddr7, 0x0);
1692 gfar_write(&regs->gaddr0, 0x0); 1986 gfar_write(&regs->gaddr0, 0x0);
1693 gfar_write(&regs->gaddr1, 0x0); 1987 gfar_write(&regs->gaddr1, 0x0);
1694 gfar_write(&regs->gaddr2, 0x0); 1988 gfar_write(&regs->gaddr2, 0x0);
@@ -1727,16 +2021,15 @@ static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1727{ 2021{
1728 u32 tempval; 2022 u32 tempval;
1729 struct gfar_private *priv = netdev_priv(dev); 2023 struct gfar_private *priv = netdev_priv(dev);
1730 struct gfar *regs = priv->regs;
1731 u32 *hash = &regs->gaddr0;
1732 u32 result = ether_crc(MAC_ADDR_LEN, addr); 2024 u32 result = ether_crc(MAC_ADDR_LEN, addr);
1733 u8 whichreg = ((result >> 29) & 0x7); 2025 int width = priv->hash_width;
1734 u8 whichbit = ((result >> 24) & 0x1f); 2026 u8 whichbit = (result >> (32 - width)) & 0x1f;
2027 u8 whichreg = result >> (32 - width + 5);
1735 u32 value = (1 << (31-whichbit)); 2028 u32 value = (1 << (31-whichbit));
1736 2029
1737 tempval = gfar_read(&hash[whichreg]); 2030 tempval = gfar_read(priv->hash_regs[whichreg]);
1738 tempval |= value; 2031 tempval |= value;
1739 gfar_write(&hash[whichreg], tempval); 2032 gfar_write(priv->hash_regs[whichreg], tempval);
1740 2033
1741 return; 2034 return;
1742} 2035}
@@ -1754,10 +2047,9 @@ static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1754 gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK); 2047 gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1755 2048
1756 /* Hmm... */ 2049 /* Hmm... */
1757#if defined (BRIEF_GFAR_ERRORS) || defined (VERBOSE_GFAR_ERRORS) 2050 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1758 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", 2051 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1759 dev->name, events, gfar_read(&priv->regs->imask)); 2052 dev->name, events, gfar_read(&priv->regs->imask));
1760#endif
1761 2053
1762 /* Update the error counters */ 2054 /* Update the error counters */
1763 if (events & IEVENT_TXE) { 2055 if (events & IEVENT_TXE) {
@@ -1768,19 +2060,17 @@ static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1768 if (events & IEVENT_CRL) 2060 if (events & IEVENT_CRL)
1769 priv->stats.tx_aborted_errors++; 2061 priv->stats.tx_aborted_errors++;
1770 if (events & IEVENT_XFUN) { 2062 if (events & IEVENT_XFUN) {
1771#ifdef VERBOSE_GFAR_ERRORS 2063 if (netif_msg_tx_err(priv))
1772 printk(KERN_DEBUG "%s: underrun. packet dropped.\n", 2064 printk(KERN_DEBUG "%s: underrun. packet dropped.\n",
1773 dev->name); 2065 dev->name);
1774#endif
1775 priv->stats.tx_dropped++; 2066 priv->stats.tx_dropped++;
1776 priv->extra_stats.tx_underrun++; 2067 priv->extra_stats.tx_underrun++;
1777 2068
1778 /* Reactivate the Tx Queues */ 2069 /* Reactivate the Tx Queues */
1779 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); 2070 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1780 } 2071 }
1781#ifdef VERBOSE_GFAR_ERRORS 2072 if (netif_msg_tx_err(priv))
1782 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); 2073 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1783#endif
1784 } 2074 }
1785 if (events & IEVENT_BSY) { 2075 if (events & IEVENT_BSY) {
1786 priv->stats.rx_errors++; 2076 priv->stats.rx_errors++;
@@ -1793,35 +2083,31 @@ static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1793 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); 2083 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1794#endif 2084#endif
1795 2085
1796#ifdef VERBOSE_GFAR_ERRORS 2086 if (netif_msg_rx_err(priv))
1797 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n", dev->name, 2087 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1798 gfar_read(&priv->regs->rstat)); 2088 dev->name,
1799#endif 2089 gfar_read(&priv->regs->rstat));
1800 } 2090 }
1801 if (events & IEVENT_BABR) { 2091 if (events & IEVENT_BABR) {
1802 priv->stats.rx_errors++; 2092 priv->stats.rx_errors++;
1803 priv->extra_stats.rx_babr++; 2093 priv->extra_stats.rx_babr++;
1804 2094
1805#ifdef VERBOSE_GFAR_ERRORS 2095 if (netif_msg_rx_err(priv))
1806 printk(KERN_DEBUG "%s: babbling error\n", dev->name); 2096 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1807#endif
1808 } 2097 }
1809 if (events & IEVENT_EBERR) { 2098 if (events & IEVENT_EBERR) {
1810 priv->extra_stats.eberr++; 2099 priv->extra_stats.eberr++;
1811#ifdef VERBOSE_GFAR_ERRORS 2100 if (netif_msg_rx_err(priv))
1812 printk(KERN_DEBUG "%s: EBERR\n", dev->name); 2101 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1813#endif
1814 } 2102 }
1815 if (events & IEVENT_RXC) 2103 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1816#ifdef VERBOSE_GFAR_ERRORS 2104 if (netif_msg_rx_status(priv))
1817 printk(KERN_DEBUG "%s: control frame\n", dev->name); 2105 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1818#endif
1819 2106
1820 if (events & IEVENT_BABT) { 2107 if (events & IEVENT_BABT) {
1821 priv->extra_stats.tx_babt++; 2108 priv->extra_stats.tx_babt++;
1822#ifdef VERBOSE_GFAR_ERRORS 2109 if (netif_msg_tx_err(priv))
1823 printk(KERN_DEBUG "%s: babt error\n", dev->name); 2110 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1824#endif
1825 } 2111 }
1826 return IRQ_HANDLED; 2112 return IRQ_HANDLED;
1827} 2113}
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index c2f783a6a9fa..28af087d9fbb 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * drivers/net/gianfar.h 2 * drivers/net/gianfar.h
3 * 3 *
4 * Gianfar Ethernet Driver 4 * Gianfar Ethernet Driver
@@ -53,6 +53,12 @@
53/* The maximum number of packets to be handled in one call of gfar_poll */ 53/* The maximum number of packets to be handled in one call of gfar_poll */
54#define GFAR_DEV_WEIGHT 64 54#define GFAR_DEV_WEIGHT 64
55 55
56/* Length for FCB */
57#define GMAC_FCB_LEN 8
58
59/* Default padding amount */
60#define DEFAULT_PADDING 2
61
56/* Number of bytes to align the rx bufs to */ 62/* Number of bytes to align the rx bufs to */
57#define RXBUF_ALIGNMENT 64 63#define RXBUF_ALIGNMENT 64
58 64
@@ -91,7 +97,7 @@ extern const char gfar_driver_version[];
91#define JUMBO_FRAME_SIZE 9600 97#define JUMBO_FRAME_SIZE 9600
92 98
93/* Latency of interface clock in nanoseconds */ 99/* Latency of interface clock in nanoseconds */
94/* Interface clock latency , in this case, means the 100/* Interface clock latency , in this case, means the
95 * time described by a value of 1 in the interrupt 101 * time described by a value of 1 in the interrupt
96 * coalescing registers' time fields. Since those fields 102 * coalescing registers' time fields. Since those fields
97 * refer to the time it takes for 64 clocks to pass, the 103 * refer to the time it takes for 64 clocks to pass, the
@@ -166,9 +172,28 @@ extern const char gfar_driver_version[];
166 mk_ic_icft(count) | \ 172 mk_ic_icft(count) | \
167 mk_ic_ictt(time)) 173 mk_ic_ictt(time))
168 174
175#define RCTRL_PAL_MASK 0x001f0000
176#define RCTRL_VLEX 0x00002000
177#define RCTRL_FILREN 0x00001000
178#define RCTRL_GHTX 0x00000400
179#define RCTRL_IPCSEN 0x00000200
180#define RCTRL_TUCSEN 0x00000100
181#define RCTRL_PRSDEP_MASK 0x000000c0
182#define RCTRL_PRSDEP_INIT 0x000000c0
169#define RCTRL_PROM 0x00000008 183#define RCTRL_PROM 0x00000008
184#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \
185 | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
186#define RCTRL_EXTHASH (RCTRL_GHTX)
187#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
188
189
170#define RSTAT_CLEAR_RHALT 0x00800000 190#define RSTAT_CLEAR_RHALT 0x00800000
171 191
192#define TCTRL_IPCSEN 0x00004000
193#define TCTRL_TUCSEN 0x00002000
194#define TCTRL_VLINS 0x00001000
195#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
196
172#define IEVENT_INIT_CLEAR 0xffffffff 197#define IEVENT_INIT_CLEAR 0xffffffff
173#define IEVENT_BABR 0x80000000 198#define IEVENT_BABR 0x80000000
174#define IEVENT_RXC 0x40000000 199#define IEVENT_RXC 0x40000000
@@ -187,12 +212,16 @@ extern const char gfar_driver_version[];
187#define IEVENT_RXB0 0x00008000 212#define IEVENT_RXB0 0x00008000
188#define IEVENT_GRSC 0x00000100 213#define IEVENT_GRSC 0x00000100
189#define IEVENT_RXF0 0x00000080 214#define IEVENT_RXF0 0x00000080
215#define IEVENT_FIR 0x00000008
216#define IEVENT_FIQ 0x00000004
217#define IEVENT_DPE 0x00000002
218#define IEVENT_PERR 0x00000001
190#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0) 219#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0)
191#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 220#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
192#define IEVENT_ERR_MASK \ 221#define IEVENT_ERR_MASK \
193(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 222(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
194 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 223 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
195 | IEVENT_CRL | IEVENT_XFUN) 224 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
196 225
197#define IMASK_INIT_CLEAR 0x00000000 226#define IMASK_INIT_CLEAR 0x00000000
198#define IMASK_BABR 0x80000000 227#define IMASK_BABR 0x80000000
@@ -212,10 +241,15 @@ extern const char gfar_driver_version[];
212#define IMASK_RXB0 0x00008000 241#define IMASK_RXB0 0x00008000
213#define IMASK_GTSC 0x00000100 242#define IMASK_GTSC 0x00000100
214#define IMASK_RXFEN0 0x00000080 243#define IMASK_RXFEN0 0x00000080
244#define IMASK_FIR 0x00000008
245#define IMASK_FIQ 0x00000004
246#define IMASK_DPE 0x00000002
247#define IMASK_PERR 0x00000001
215#define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY) 248#define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
216#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 249#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
217 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 250 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
218 IMASK_XFUN | IMASK_RXC | IMASK_BABT) 251 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
252 | IMASK_PERR)
219 253
220 254
221/* Attribute fields */ 255/* Attribute fields */
@@ -254,6 +288,18 @@ extern const char gfar_driver_version[];
254#define TXBD_RETRYLIMIT 0x0040 288#define TXBD_RETRYLIMIT 0x0040
255#define TXBD_RETRYCOUNTMASK 0x003c 289#define TXBD_RETRYCOUNTMASK 0x003c
256#define TXBD_UNDERRUN 0x0002 290#define TXBD_UNDERRUN 0x0002
291#define TXBD_TOE 0x0002
292
293/* Tx FCB param bits */
294#define TXFCB_VLN 0x80
295#define TXFCB_IP 0x40
296#define TXFCB_IP6 0x20
297#define TXFCB_TUP 0x10
298#define TXFCB_UDP 0x08
299#define TXFCB_CIP 0x04
300#define TXFCB_CTU 0x02
301#define TXFCB_NPH 0x01
302#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
257 303
258/* RxBD status field bits */ 304/* RxBD status field bits */
259#define RXBD_EMPTY 0x8000 305#define RXBD_EMPTY 0x8000
@@ -273,6 +319,18 @@ extern const char gfar_driver_version[];
273#define RXBD_TRUNCATED 0x0001 319#define RXBD_TRUNCATED 0x0001
274#define RXBD_STATS 0x01ff 320#define RXBD_STATS 0x01ff
275 321
322/* Rx FCB status field bits */
323#define RXFCB_VLN 0x8000
324#define RXFCB_IP 0x4000
325#define RXFCB_IP6 0x2000
326#define RXFCB_TUP 0x1000
327#define RXFCB_CIP 0x0800
328#define RXFCB_CTU 0x0400
329#define RXFCB_EIP 0x0200
330#define RXFCB_ETU 0x0100
331#define RXFCB_PERR_MASK 0x000c
332#define RXFCB_PERR_BADL3 0x0008
333
276struct txbd8 334struct txbd8
277{ 335{
278 u16 status; /* Status Fields */ 336 u16 status; /* Status Fields */
@@ -280,6 +338,22 @@ struct txbd8
280 u32 bufPtr; /* Buffer Pointer */ 338 u32 bufPtr; /* Buffer Pointer */
281}; 339};
282 340
341struct txfcb {
342 u8 vln:1,
343 ip:1,
344 ip6:1,
345 tup:1,
346 udp:1,
347 cip:1,
348 ctu:1,
349 nph:1;
350 u8 reserved;
351 u8 l4os; /* Level 4 Header Offset */
352 u8 l3os; /* Level 3 Header Offset */
353 u16 phcs; /* Pseudo-header Checksum */
354 u16 vlctl; /* VLAN control word */
355};
356
283struct rxbd8 357struct rxbd8
284{ 358{
285 u16 status; /* Status Fields */ 359 u16 status; /* Status Fields */
@@ -287,6 +361,21 @@ struct rxbd8
287 u32 bufPtr; /* Buffer Pointer */ 361 u32 bufPtr; /* Buffer Pointer */
288}; 362};
289 363
364struct rxfcb {
365 u16 vln:1,
366 ip:1,
367 ip6:1,
368 tup:1,
369 cip:1,
370 ctu:1,
371 eip:1,
372 etu:1;
373 u8 rq; /* Receive Queue index */
374 u8 pro; /* Layer 4 Protocol */
375 u16 reserved;
376 u16 vlctl; /* VLAN control word */
377};
378
290struct rmon_mib 379struct rmon_mib
291{ 380{
292 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 381 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
@@ -371,90 +460,191 @@ struct gfar_stats {
371 460
372 461
373struct gfar { 462struct gfar {
374 u8 res1[16]; 463 u32 tsec_id; /* 0x.000 - Controller ID register */
375 u32 ievent; /* 0x.010 - Interrupt Event Register */ 464 u8 res1[12];
376 u32 imask; /* 0x.014 - Interrupt Mask Register */ 465 u32 ievent; /* 0x.010 - Interrupt Event Register */
377 u32 edis; /* 0x.018 - Error Disabled Register */ 466 u32 imask; /* 0x.014 - Interrupt Mask Register */
467 u32 edis; /* 0x.018 - Error Disabled Register */
378 u8 res2[4]; 468 u8 res2[4];
379 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 469 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
380 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 470 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
381 u32 ptv; /* 0x.028 - Pause Time Value Register */ 471 u32 ptv; /* 0x.028 - Pause Time Value Register */
382 u32 dmactrl; /* 0x.02c - DMA Control Register */ 472 u32 dmactrl; /* 0x.02c - DMA Control Register */
383 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 473 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
384 u8 res3[88]; 474 u8 res3[88];
385 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 475 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
386 u8 res4[8]; 476 u8 res4[8];
387 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 477 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
388 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 478 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
389 u8 res5[96]; 479 u8 res5[4];
390 u32 tctrl; /* 0x.100 - Transmit Control Register */ 480 u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
391 u32 tstat; /* 0x.104 - Transmit Status Register */ 481 u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
392 u8 res6[4]; 482 u8 res6[84];
393 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 483 u32 tctrl; /* 0x.100 - Transmit Control Register */
394 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 484 u32 tstat; /* 0x.104 - Transmit Status Register */
395 u8 res7[16]; 485 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
396 u32 ctbptr; /* 0x.124 - Current Transmit Buffer Descriptor Pointer Register */ 486 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
397 u8 res8[92]; 487 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
398 u32 tbptr; /* 0x.184 - Transmit Buffer Descriptor Pointer Low Register */ 488 u32 tqueue; /* 0x.114 - Transmit queue control register */
399 u8 res9[124]; 489 u8 res7[40];
400 u32 tbase; /* 0x.204 - Transmit Descriptor Base Address Register */ 490 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
401 u8 res10[168]; 491 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
402 u32 ostbd; /* 0x.2b0 - Out-of-Sequence Transmit Buffer Descriptor Register */ 492 u8 res8[52];
403 u32 ostbdp; /* 0x.2b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */ 493 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
404 u8 res11[72]; 494 u8 res9a[4];
405 u32 rctrl; /* 0x.300 - Receive Control Register */ 495 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
406 u32 rstat; /* 0x.304 - Receive Status Register */ 496 u8 res9b[4];
407 u8 res12[4]; 497 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
408 u32 rbdlen; /* 0x.30c - RxBD Data Length Register */ 498 u8 res9c[4];
409 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 499 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
410 u8 res13[16]; 500 u8 res9d[4];
411 u32 crbptr; /* 0x.324 - Current Receive Buffer Descriptor Pointer */ 501 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
412 u8 res14[24]; 502 u8 res9e[4];
413 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 503 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
414 u8 res15[64]; 504 u8 res9f[4];
415 u32 rbptr; /* 0x.384 - Receive Buffer Descriptor Pointer */ 505 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
416 u8 res16[124]; 506 u8 res9g[4];
417 u32 rbase; /* 0x.404 - Receive Descriptor Base Address */ 507 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
418 u8 res17[248]; 508 u8 res9h[4];
419 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 509 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
420 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 510 u8 res9[64];
421 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 511 u32 tbaseh; /* 0x.200 - TxBD base address high */
422 u32 hafdup; /* 0x.50c - Half Duplex Register */ 512 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
423 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 513 u8 res10a[4];
514 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
515 u8 res10b[4];
516 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
517 u8 res10c[4];
518 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
519 u8 res10d[4];
520 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
521 u8 res10e[4];
522 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
523 u8 res10f[4];
524 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
525 u8 res10g[4];
526 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
527 u8 res10[192];
528 u32 rctrl; /* 0x.300 - Receive Control Register */
529 u32 rstat; /* 0x.304 - Receive Status Register */
530 u8 res12[8];
531 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
532 u32 rqueue; /* 0x.314 - Receive queue control register */
533 u8 res13[24];
534 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
535 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
536 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
537 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
538 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
539 u8 res14[56];
540 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
541 u8 res15a[4];
542 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
543 u8 res15b[4];
544 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
545 u8 res15c[4];
546 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
547 u8 res15d[4];
548 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
549 u8 res15e[4];
550 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
551 u8 res15f[4];
552 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
553 u8 res15g[4];
554 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
555 u8 res15h[4];
556 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
557 u8 res16[64];
558 u32 rbaseh; /* 0x.400 - RxBD base address high */
559 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
560 u8 res17a[4];
561 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
562 u8 res17b[4];
563 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
564 u8 res17c[4];
565 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
566 u8 res17d[4];
567 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
568 u8 res17e[4];
569 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
570 u8 res17f[4];
571 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
572 u8 res17g[4];
573 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
574 u8 res17[192];
575 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
576 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
577 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
578 u32 hafdup; /* 0x.50c - Half Duplex Register */
579 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
424 u8 res18[12]; 580 u8 res18[12];
425 u32 miimcfg; /* 0x.520 - MII Management Configuration Register */ 581 u32 miimcfg; /* 0x.520 - MII Management Configuration Register */
426 u32 miimcom; /* 0x.524 - MII Management Command Register */ 582 u32 miimcom; /* 0x.524 - MII Management Command Register */
427 u32 miimadd; /* 0x.528 - MII Management Address Register */ 583 u32 miimadd; /* 0x.528 - MII Management Address Register */
428 u32 miimcon; /* 0x.52c - MII Management Control Register */ 584 u32 miimcon; /* 0x.52c - MII Management Control Register */
429 u32 miimstat; /* 0x.530 - MII Management Status Register */ 585 u32 miimstat; /* 0x.530 - MII Management Status Register */
430 u32 miimind; /* 0x.534 - MII Management Indicator Register */ 586 u32 miimind; /* 0x.534 - MII Management Indicator Register */
431 u8 res19[4]; 587 u8 res19[4];
432 u32 ifstat; /* 0x.53c - Interface Status Register */ 588 u32 ifstat; /* 0x.53c - Interface Status Register */
433 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 589 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
434 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 590 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
435 u8 res20[312]; 591 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
436 struct rmon_mib rmon; 592 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
437 u8 res21[192]; 593 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
438 u32 iaddr0; /* 0x.800 - Indivdual address register 0 */ 594 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
439 u32 iaddr1; /* 0x.804 - Indivdual address register 1 */ 595 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
440 u32 iaddr2; /* 0x.808 - Indivdual address register 2 */ 596 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
441 u32 iaddr3; /* 0x.80c - Indivdual address register 3 */ 597 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
442 u32 iaddr4; /* 0x.810 - Indivdual address register 4 */ 598 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
443 u32 iaddr5; /* 0x.814 - Indivdual address register 5 */ 599 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
444 u32 iaddr6; /* 0x.818 - Indivdual address register 6 */ 600 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
445 u32 iaddr7; /* 0x.81c - Indivdual address register 7 */ 601 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
602 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
603 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
604 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
605 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
606 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
607 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
608 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
609 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
610 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
611 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
612 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
613 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
614 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
615 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
616 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
617 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
618 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
619 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
620 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
621 u8 res20[192];
622 struct rmon_mib rmon; /* 0x.680-0x.73c */
623 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
624 u8 res21[188];
625 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
626 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
627 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
628 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
629 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
630 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
631 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
632 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
446 u8 res22[96]; 633 u8 res22[96];
447 u32 gaddr0; /* 0x.880 - Global address register 0 */ 634 u32 gaddr0; /* 0x.880 - Group address register 0 */
448 u32 gaddr1; /* 0x.884 - Global address register 1 */ 635 u32 gaddr1; /* 0x.884 - Group address register 1 */
449 u32 gaddr2; /* 0x.888 - Global address register 2 */ 636 u32 gaddr2; /* 0x.888 - Group address register 2 */
450 u32 gaddr3; /* 0x.88c - Global address register 3 */ 637 u32 gaddr3; /* 0x.88c - Group address register 3 */
451 u32 gaddr4; /* 0x.890 - Global address register 4 */ 638 u32 gaddr4; /* 0x.890 - Group address register 4 */
452 u32 gaddr5; /* 0x.894 - Global address register 5 */ 639 u32 gaddr5; /* 0x.894 - Group address register 5 */
453 u32 gaddr6; /* 0x.898 - Global address register 6 */ 640 u32 gaddr6; /* 0x.898 - Group address register 6 */
454 u32 gaddr7; /* 0x.89c - Global address register 7 */ 641 u32 gaddr7; /* 0x.89c - Group address register 7 */
455 u8 res23[856]; 642 u8 res23a[352];
456 u32 attr; /* 0x.bf8 - Attributes Register */ 643 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
457 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 644 u8 res23b[252];
645 u8 res23c[248];
646 u32 attr; /* 0x.bf8 - Attributes Register */
647 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
458 u8 res24[1024]; 648 u8 res24[1024];
459 649
460}; 650};
@@ -496,6 +686,8 @@ struct gfar_private {
496 struct txbd8 *cur_tx; /* Next free ring entry */ 686 struct txbd8 *cur_tx; /* Next free ring entry */
497 struct txbd8 *dirty_tx; /* The Ring entry to be freed. */ 687 struct txbd8 *dirty_tx; /* The Ring entry to be freed. */
498 struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */ 688 struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */
689 u32 *hash_regs[16];
690 int hash_width;
499 struct gfar *phyregs; 691 struct gfar *phyregs;
500 struct work_struct tq; 692 struct work_struct tq;
501 struct timer_list phy_info_timer; 693 struct timer_list phy_info_timer;
@@ -506,9 +698,12 @@ struct gfar_private {
506 unsigned int rx_stash_size; 698 unsigned int rx_stash_size;
507 unsigned int tx_ring_size; 699 unsigned int tx_ring_size;
508 unsigned int rx_ring_size; 700 unsigned int rx_ring_size;
509 wait_queue_head_t rxcleanupq;
510 unsigned int rxclean;
511 701
702 unsigned char vlan_enable:1,
703 rx_csum_enable:1,
704 extended_hash:1;
705 unsigned short padding;
706 struct vlan_group *vlgrp;
512 /* Info structure initialized by board setup code */ 707 /* Info structure initialized by board setup code */
513 unsigned int interruptTransmit; 708 unsigned int interruptTransmit;
514 unsigned int interruptReceive; 709 unsigned int interruptReceive;
@@ -519,6 +714,8 @@ struct gfar_private {
519 int oldspeed; 714 int oldspeed;
520 int oldduplex; 715 int oldduplex;
521 int oldlink; 716 int oldlink;
717
718 uint32_t msg_enable;
522}; 719};
523 720
524extern inline u32 gfar_read(volatile unsigned *addr) 721extern inline u32 gfar_read(volatile unsigned *addr)
diff --git a/drivers/net/gianfar_ethtool.c b/drivers/net/gianfar_ethtool.c
index 28046e9e88ba..a451de629197 100644
--- a/drivers/net/gianfar_ethtool.c
+++ b/drivers/net/gianfar_ethtool.c
@@ -46,16 +46,18 @@
46 46
47extern int startup_gfar(struct net_device *dev); 47extern int startup_gfar(struct net_device *dev);
48extern void stop_gfar(struct net_device *dev); 48extern void stop_gfar(struct net_device *dev);
49extern void gfar_receive(int irq, void *dev_id, struct pt_regs *regs); 49extern void gfar_halt(struct net_device *dev);
50extern void gfar_start(struct net_device *dev);
51extern int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
50 52
51void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, 53static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
52 u64 * buf); 54 u64 * buf);
53void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf); 55static void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf);
54int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals); 56static int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals);
55int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals); 57static int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals);
56void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals); 58static void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals);
57int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals); 59static int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals);
58void gfar_gdrvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo); 60static void gfar_gdrvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo);
59 61
60static char stat_gstrings[][ETH_GSTRING_LEN] = { 62static char stat_gstrings[][ETH_GSTRING_LEN] = {
61 "rx-dropped-by-kernel", 63 "rx-dropped-by-kernel",
@@ -118,57 +120,56 @@ static char stat_gstrings[][ETH_GSTRING_LEN] = {
118 "tx-fragmented-frames", 120 "tx-fragmented-frames",
119}; 121};
120 122
123/* Fill in a buffer with the strings which correspond to the
124 * stats */
125static void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf)
126{
127 struct gfar_private *priv = netdev_priv(dev);
128
129 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON)
130 memcpy(buf, stat_gstrings, GFAR_STATS_LEN * ETH_GSTRING_LEN);
131 else
132 memcpy(buf, stat_gstrings,
133 GFAR_EXTRA_STATS_LEN * ETH_GSTRING_LEN);
134}
135
121/* Fill in an array of 64-bit statistics from various sources. 136/* Fill in an array of 64-bit statistics from various sources.
122 * This array will be appended to the end of the ethtool_stats 137 * This array will be appended to the end of the ethtool_stats
123 * structure, and returned to user space 138 * structure, and returned to user space
124 */ 139 */
125void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, u64 * buf) 140static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, u64 * buf)
126{ 141{
127 int i; 142 int i;
128 struct gfar_private *priv = netdev_priv(dev); 143 struct gfar_private *priv = netdev_priv(dev);
129 u32 *rmon = (u32 *) & priv->regs->rmon;
130 u64 *extra = (u64 *) & priv->extra_stats; 144 u64 *extra = (u64 *) & priv->extra_stats;
131 struct gfar_stats *stats = (struct gfar_stats *) buf;
132 145
133 for (i = 0; i < GFAR_RMON_LEN; i++) { 146 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
134 stats->rmon[i] = (u64) (rmon[i]); 147 u32 *rmon = (u32 *) & priv->regs->rmon;
135 } 148 struct gfar_stats *stats = (struct gfar_stats *) buf;
136
137 for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++) {
138 stats->extra[i] = extra[i];
139 }
140}
141 149
142/* Returns the number of stats (and their corresponding strings) */ 150 for (i = 0; i < GFAR_RMON_LEN; i++)
143int gfar_stats_count(struct net_device *dev) 151 stats->rmon[i] = (u64) (rmon[i]);
144{
145 return GFAR_STATS_LEN;
146}
147 152
148void gfar_gstrings_normon(struct net_device *dev, u32 stringset, u8 * buf) 153 for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++)
149{ 154 stats->extra[i] = extra[i];
150 memcpy(buf, stat_gstrings, GFAR_EXTRA_STATS_LEN * ETH_GSTRING_LEN); 155 } else
156 for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++)
157 buf[i] = extra[i];
151} 158}
152 159
153void gfar_fill_stats_normon(struct net_device *dev, 160/* Returns the number of stats (and their corresponding strings) */
154 struct ethtool_stats *dummy, u64 * buf) 161static int gfar_stats_count(struct net_device *dev)
155{ 162{
156 int i;
157 struct gfar_private *priv = netdev_priv(dev); 163 struct gfar_private *priv = netdev_priv(dev);
158 u64 *extra = (u64 *) & priv->extra_stats;
159 164
160 for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++) { 165 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON)
161 buf[i] = extra[i]; 166 return GFAR_STATS_LEN;
162 } 167 else
168 return GFAR_EXTRA_STATS_LEN;
163} 169}
164 170
165
166int gfar_stats_count_normon(struct net_device *dev)
167{
168 return GFAR_EXTRA_STATS_LEN;
169}
170/* Fills in the drvinfo structure with some basic info */ 171/* Fills in the drvinfo structure with some basic info */
171void gfar_gdrvinfo(struct net_device *dev, struct 172static void gfar_gdrvinfo(struct net_device *dev, struct
172 ethtool_drvinfo *drvinfo) 173 ethtool_drvinfo *drvinfo)
173{ 174{
174 strncpy(drvinfo->driver, DRV_NAME, GFAR_INFOSTR_LEN); 175 strncpy(drvinfo->driver, DRV_NAME, GFAR_INFOSTR_LEN);
@@ -182,7 +183,7 @@ void gfar_gdrvinfo(struct net_device *dev, struct
182} 183}
183 184
184/* Return the current settings in the ethtool_cmd structure */ 185/* Return the current settings in the ethtool_cmd structure */
185int gfar_gsettings(struct net_device *dev, struct ethtool_cmd *cmd) 186static int gfar_gsettings(struct net_device *dev, struct ethtool_cmd *cmd)
186{ 187{
187 struct gfar_private *priv = netdev_priv(dev); 188 struct gfar_private *priv = netdev_priv(dev);
188 uint gigabit_support = 189 uint gigabit_support =
@@ -216,13 +217,13 @@ int gfar_gsettings(struct net_device *dev, struct ethtool_cmd *cmd)
216} 217}
217 218
218/* Return the length of the register structure */ 219/* Return the length of the register structure */
219int gfar_reglen(struct net_device *dev) 220static int gfar_reglen(struct net_device *dev)
220{ 221{
221 return sizeof (struct gfar); 222 return sizeof (struct gfar);
222} 223}
223 224
224/* Return a dump of the GFAR register space */ 225/* Return a dump of the GFAR register space */
225void gfar_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 226static void gfar_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
226{ 227{
227 int i; 228 int i;
228 struct gfar_private *priv = netdev_priv(dev); 229 struct gfar_private *priv = netdev_priv(dev);
@@ -233,13 +234,6 @@ void gfar_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regb
233 buf[i] = theregs[i]; 234 buf[i] = theregs[i];
234} 235}
235 236
236/* Fill in a buffer with the strings which correspond to the
237 * stats */
238void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf)
239{
240 memcpy(buf, stat_gstrings, GFAR_STATS_LEN * ETH_GSTRING_LEN);
241}
242
243/* Convert microseconds to ethernet clock ticks, which changes 237/* Convert microseconds to ethernet clock ticks, which changes
244 * depending on what speed the controller is running at */ 238 * depending on what speed the controller is running at */
245static unsigned int gfar_usecs2ticks(struct gfar_private *priv, unsigned int usecs) 239static unsigned int gfar_usecs2ticks(struct gfar_private *priv, unsigned int usecs)
@@ -291,9 +285,12 @@ static unsigned int gfar_ticks2usecs(struct gfar_private *priv, unsigned int tic
291 285
292/* Get the coalescing parameters, and put them in the cvals 286/* Get the coalescing parameters, and put them in the cvals
293 * structure. */ 287 * structure. */
294int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals) 288static int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
295{ 289{
296 struct gfar_private *priv = netdev_priv(dev); 290 struct gfar_private *priv = netdev_priv(dev);
291
292 if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE))
293 return -EOPNOTSUPP;
297 294
298 cvals->rx_coalesce_usecs = gfar_ticks2usecs(priv, priv->rxtime); 295 cvals->rx_coalesce_usecs = gfar_ticks2usecs(priv, priv->rxtime);
299 cvals->rx_max_coalesced_frames = priv->rxcount; 296 cvals->rx_max_coalesced_frames = priv->rxcount;
@@ -337,10 +334,13 @@ int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
337 * Both cvals->*_usecs and cvals->*_frames have to be > 0 334 * Both cvals->*_usecs and cvals->*_frames have to be > 0
338 * in order for coalescing to be active 335 * in order for coalescing to be active
339 */ 336 */
340int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals) 337static int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
341{ 338{
342 struct gfar_private *priv = netdev_priv(dev); 339 struct gfar_private *priv = netdev_priv(dev);
343 340
341 if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE))
342 return -EOPNOTSUPP;
343
344 /* Set up rx coalescing */ 344 /* Set up rx coalescing */
345 if ((cvals->rx_coalesce_usecs == 0) || 345 if ((cvals->rx_coalesce_usecs == 0) ||
346 (cvals->rx_max_coalesced_frames == 0)) 346 (cvals->rx_max_coalesced_frames == 0))
@@ -379,7 +379,7 @@ int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
379/* Fills in rvals with the current ring parameters. Currently, 379/* Fills in rvals with the current ring parameters. Currently,
380 * rx, rx_mini, and rx_jumbo rings are the same size, as mini and 380 * rx, rx_mini, and rx_jumbo rings are the same size, as mini and
381 * jumbo are ignored by the driver */ 381 * jumbo are ignored by the driver */
382void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals) 382static void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
383{ 383{
384 struct gfar_private *priv = netdev_priv(dev); 384 struct gfar_private *priv = netdev_priv(dev);
385 385
@@ -401,9 +401,8 @@ void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
401 * necessary so that we don't mess things up while we're in 401 * necessary so that we don't mess things up while we're in
402 * motion. We wait for the ring to be clean before reallocating 402 * motion. We wait for the ring to be clean before reallocating
403 * the rings. */ 403 * the rings. */
404int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals) 404static int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
405{ 405{
406 u32 tempval;
407 struct gfar_private *priv = netdev_priv(dev); 406 struct gfar_private *priv = netdev_priv(dev);
408 int err = 0; 407 int err = 0;
409 408
@@ -425,37 +424,54 @@ int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
425 return -EINVAL; 424 return -EINVAL;
426 } 425 }
427 426
428 /* Stop the controller so we don't rx any more frames */ 427 if (dev->flags & IFF_UP) {
429 /* But first, make sure we clear the bits */ 428 unsigned long flags;
430 tempval = gfar_read(&priv->regs->dmactrl);
431 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
432 gfar_write(&priv->regs->dmactrl, tempval);
433 429
434 tempval = gfar_read(&priv->regs->dmactrl); 430 /* Halt TX and RX, and process the frames which
435 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 431 * have already been received */
436 gfar_write(&priv->regs->dmactrl, tempval); 432 spin_lock_irqsave(&priv->lock, flags);
433 gfar_halt(dev);
434 gfar_clean_rx_ring(dev, priv->rx_ring_size);
435 spin_unlock_irqrestore(&priv->lock, flags);
437 436
438 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))) 437 /* Now we take down the rings to rebuild them */
439 cpu_relax(); 438 stop_gfar(dev);
439 }
440 440
441 /* Note that rx is not clean right now */ 441 /* Change the size */
442 priv->rxclean = 0; 442 priv->rx_ring_size = rvals->rx_pending;
443 priv->tx_ring_size = rvals->tx_pending;
443 444
444 if (dev->flags & IFF_UP) { 445 /* Rebuild the rings with the new size */
445 /* Tell the driver to process the rest of the frames */ 446 if (dev->flags & IFF_UP)
446 gfar_receive(0, (void *) dev, NULL); 447 err = startup_gfar(dev);
447 448
448 /* Now wait for it to be done */ 449 return err;
449 wait_event_interruptible(priv->rxcleanupq, priv->rxclean); 450}
450 451
451 /* Ok, all packets have been handled. Now we bring it down, 452static int gfar_set_rx_csum(struct net_device *dev, uint32_t data)
452 * change the ring size, and bring it up */ 453{
454 struct gfar_private *priv = netdev_priv(dev);
455 int err = 0;
453 456
457 if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
458 return -EOPNOTSUPP;
459
460 if (dev->flags & IFF_UP) {
461 unsigned long flags;
462
463 /* Halt TX and RX, and process the frames which
464 * have already been received */
465 spin_lock_irqsave(&priv->lock, flags);
466 gfar_halt(dev);
467 gfar_clean_rx_ring(dev, priv->rx_ring_size);
468 spin_unlock_irqrestore(&priv->lock, flags);
469
470 /* Now we take down the rings to rebuild them */
454 stop_gfar(dev); 471 stop_gfar(dev);
455 } 472 }
456 473
457 priv->rx_ring_size = rvals->rx_pending; 474 priv->rx_csum_enable = data;
458 priv->tx_ring_size = rvals->tx_pending;
459 475
460 if (dev->flags & IFF_UP) 476 if (dev->flags & IFF_UP)
461 err = startup_gfar(dev); 477 err = startup_gfar(dev);
@@ -463,6 +479,61 @@ int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
463 return err; 479 return err;
464} 480}
465 481
482static uint32_t gfar_get_rx_csum(struct net_device *dev)
483{
484 struct gfar_private *priv = netdev_priv(dev);
485
486 if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
487 return 0;
488
489 return priv->rx_csum_enable;
490}
491
492static int gfar_set_tx_csum(struct net_device *dev, uint32_t data)
493{
494 unsigned long flags;
495 struct gfar_private *priv = netdev_priv(dev);
496
497 if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
498 return -EOPNOTSUPP;
499
500 spin_lock_irqsave(&priv->lock, flags);
501 gfar_halt(dev);
502
503 if (data)
504 dev->features |= NETIF_F_IP_CSUM;
505 else
506 dev->features &= ~NETIF_F_IP_CSUM;
507
508 gfar_start(dev);
509 spin_unlock_irqrestore(&priv->lock, flags);
510
511 return 0;
512}
513
514static uint32_t gfar_get_tx_csum(struct net_device *dev)
515{
516 struct gfar_private *priv = netdev_priv(dev);
517
518 if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
519 return 0;
520
521 return (dev->features & NETIF_F_IP_CSUM) != 0;
522}
523
524static uint32_t gfar_get_msglevel(struct net_device *dev)
525{
526 struct gfar_private *priv = netdev_priv(dev);
527 return priv->msg_enable;
528}
529
530static void gfar_set_msglevel(struct net_device *dev, uint32_t data)
531{
532 struct gfar_private *priv = netdev_priv(dev);
533 priv->msg_enable = data;
534}
535
536
466struct ethtool_ops gfar_ethtool_ops = { 537struct ethtool_ops gfar_ethtool_ops = {
467 .get_settings = gfar_gsettings, 538 .get_settings = gfar_gsettings,
468 .get_drvinfo = gfar_gdrvinfo, 539 .get_drvinfo = gfar_gdrvinfo,
@@ -476,52 +547,10 @@ struct ethtool_ops gfar_ethtool_ops = {
476 .get_strings = gfar_gstrings, 547 .get_strings = gfar_gstrings,
477 .get_stats_count = gfar_stats_count, 548 .get_stats_count = gfar_stats_count,
478 .get_ethtool_stats = gfar_fill_stats, 549 .get_ethtool_stats = gfar_fill_stats,
479}; 550 .get_rx_csum = gfar_get_rx_csum,
480 551 .get_tx_csum = gfar_get_tx_csum,
481struct ethtool_ops gfar_normon_nocoalesce_ethtool_ops = { 552 .set_rx_csum = gfar_set_rx_csum,
482 .get_settings = gfar_gsettings, 553 .set_tx_csum = gfar_set_tx_csum,
483 .get_drvinfo = gfar_gdrvinfo, 554 .get_msglevel = gfar_get_msglevel,
484 .get_regs_len = gfar_reglen, 555 .set_msglevel = gfar_set_msglevel,
485 .get_regs = gfar_get_regs,
486 .get_link = ethtool_op_get_link,
487 .get_ringparam = gfar_gringparam,
488 .set_ringparam = gfar_sringparam,
489 .get_strings = gfar_gstrings_normon,
490 .get_stats_count = gfar_stats_count_normon,
491 .get_ethtool_stats = gfar_fill_stats_normon,
492};
493
494struct ethtool_ops gfar_nocoalesce_ethtool_ops = {
495 .get_settings = gfar_gsettings,
496 .get_drvinfo = gfar_gdrvinfo,
497 .get_regs_len = gfar_reglen,
498 .get_regs = gfar_get_regs,
499 .get_link = ethtool_op_get_link,
500 .get_ringparam = gfar_gringparam,
501 .set_ringparam = gfar_sringparam,
502 .get_strings = gfar_gstrings,
503 .get_stats_count = gfar_stats_count,
504 .get_ethtool_stats = gfar_fill_stats,
505};
506
507struct ethtool_ops gfar_normon_ethtool_ops = {
508 .get_settings = gfar_gsettings,
509 .get_drvinfo = gfar_gdrvinfo,
510 .get_regs_len = gfar_reglen,
511 .get_regs = gfar_get_regs,
512 .get_link = ethtool_op_get_link,
513 .get_coalesce = gfar_gcoalesce,
514 .set_coalesce = gfar_scoalesce,
515 .get_ringparam = gfar_gringparam,
516 .set_ringparam = gfar_sringparam,
517 .get_strings = gfar_gstrings_normon,
518 .get_stats_count = gfar_stats_count_normon,
519 .get_ethtool_stats = gfar_fill_stats_normon,
520};
521
522struct ethtool_ops *gfar_op_array[] = {
523 &gfar_ethtool_ops,
524 &gfar_normon_ethtool_ops,
525 &gfar_nocoalesce_ethtool_ops,
526 &gfar_normon_nocoalesce_ethtool_ops
527}; 556};
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index 13f114876965..3213f3e50487 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -850,7 +850,7 @@ static int pcnet32_phys_id(struct net_device *dev, u32 data)
850 if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))) 850 if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)))
851 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); 851 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
852 852
853 schedule_timeout(data * HZ); 853 msleep_interruptible(data * 1000);
854 del_timer_sync(&lp->blink_timer); 854 del_timer_sync(&lp->blink_timer);
855 855
856 /* Restore the original value of the bcrs */ 856 /* Restore the original value of the bcrs */
diff --git a/drivers/net/sb1000.c b/drivers/net/sb1000.c
index e15369c8d165..d6388e1533f0 100644
--- a/drivers/net/sb1000.c
+++ b/drivers/net/sb1000.c
@@ -90,7 +90,6 @@ static int sb1000_close(struct net_device *dev);
90 90
91 91
92/* SB1000 hardware routines to be used during open/configuration phases */ 92/* SB1000 hardware routines to be used during open/configuration phases */
93static inline void nicedelay(unsigned long usecs);
94static inline int card_wait_for_busy_clear(const int ioaddr[], 93static inline int card_wait_for_busy_clear(const int ioaddr[],
95 const char* name); 94 const char* name);
96static inline int card_wait_for_ready(const int ioaddr[], const char* name, 95static inline int card_wait_for_ready(const int ioaddr[], const char* name,
@@ -254,13 +253,6 @@ static struct pnp_driver sb1000_driver = {
254 253
255static const int TimeOutJiffies = (875 * HZ) / 100; 254static const int TimeOutJiffies = (875 * HZ) / 100;
256 255
257static inline void nicedelay(unsigned long usecs)
258{
259 current->state = TASK_INTERRUPTIBLE;
260 schedule_timeout(HZ);
261 return;
262}
263
264/* Card Wait For Busy Clear (cannot be used during an interrupt) */ 256/* Card Wait For Busy Clear (cannot be used during an interrupt) */
265static inline int 257static inline int
266card_wait_for_busy_clear(const int ioaddr[], const char* name) 258card_wait_for_busy_clear(const int ioaddr[], const char* name)
@@ -475,7 +467,7 @@ sb1000_reset(const int ioaddr[], const char* name)
475 udelay(1000); 467 udelay(1000);
476 outb(0x0, port); 468 outb(0x0, port);
477 inb(port); 469 inb(port);
478 nicedelay(60000); 470 ssleep(1);
479 outb(0x4, port); 471 outb(0x4, port);
480 inb(port); 472 inb(port);
481 udelay(1000); 473 udelay(1000);
@@ -537,7 +529,7 @@ sb1000_activate(const int ioaddr[], const char* name)
537 const unsigned char Command0[6] = {0x80, 0x11, 0x00, 0x00, 0x00, 0x00}; 529 const unsigned char Command0[6] = {0x80, 0x11, 0x00, 0x00, 0x00, 0x00};
538 const unsigned char Command1[6] = {0x80, 0x16, 0x00, 0x00, 0x00, 0x00}; 530 const unsigned char Command1[6] = {0x80, 0x16, 0x00, 0x00, 0x00, 0x00};
539 531
540 nicedelay(50000); 532 ssleep(1);
541 if ((status = card_send_command(ioaddr, name, Command0, st))) 533 if ((status = card_send_command(ioaddr, name, Command0, st)))
542 return status; 534 return status;
543 if ((status = card_send_command(ioaddr, name, Command1, st))) 535 if ((status = card_send_command(ioaddr, name, Command1, st)))
@@ -944,7 +936,7 @@ sb1000_open(struct net_device *dev)
944 /* initialize sb1000 */ 936 /* initialize sb1000 */
945 if ((status = sb1000_reset(ioaddr, name))) 937 if ((status = sb1000_reset(ioaddr, name)))
946 return status; 938 return status;
947 nicedelay(200000); 939 ssleep(1);
948 if ((status = sb1000_check_CRC(ioaddr, name))) 940 if ((status = sb1000_check_CRC(ioaddr, name)))
949 return status; 941 return status;
950 942
diff --git a/drivers/net/skfp/Makefile b/drivers/net/skfp/Makefile
index 5f4bb1a67400..cb23580fcffa 100644
--- a/drivers/net/skfp/Makefile
+++ b/drivers/net/skfp/Makefile
@@ -6,8 +6,8 @@ obj-$(CONFIG_SKFP) += skfp.o
6 6
7skfp-objs := skfddi.o hwmtm.o fplustm.o smt.o cfm.o \ 7skfp-objs := skfddi.o hwmtm.o fplustm.o smt.o cfm.o \
8 ecm.o pcmplc.o pmf.o queue.o rmt.o \ 8 ecm.o pcmplc.o pmf.o queue.o rmt.o \
9 smtdef.o smtinit.o smttimer.o srf.o smtparse.o\ 9 smtdef.o smtinit.o smttimer.o srf.o hwt.o \
10 hwt.o drvfbi.o ess.o 10 drvfbi.o ess.o
11 11
12# NOTE: 12# NOTE:
13# Compiling this driver produces some warnings (and some more are 13# Compiling this driver produces some warnings (and some more are
diff --git a/drivers/net/skfp/drvfbi.c b/drivers/net/skfp/drvfbi.c
index 052e841ba187..5b475833f645 100644
--- a/drivers/net/skfp/drvfbi.c
+++ b/drivers/net/skfp/drvfbi.c
@@ -105,8 +105,8 @@ extern int AIX_vpdReadByte() ;
105#endif 105#endif
106 106
107 107
108/* Prototypes of local functions. */ 108/* Prototype of a local function. */
109void smt_stop_watchdog(struct s_smc *smc); 109static void smt_stop_watchdog(struct s_smc *smc);
110 110
111#ifdef MCA 111#ifdef MCA
112static int read_card_id() ; 112static int read_card_id() ;
@@ -631,7 +631,7 @@ void plc_clear_irq(struct s_smc *smc, int p)
631 * LED_Y_OFF just switch yellow LED off 631 * LED_Y_OFF just switch yellow LED off
632 * LED_Y_ON just switch yello LED on 632 * LED_Y_ON just switch yello LED on
633 */ 633 */
634void led_indication(struct s_smc *smc, int led_event) 634static void led_indication(struct s_smc *smc, int led_event)
635{ 635{
636 /* use smc->hw.mac_ring_is_up == TRUE 636 /* use smc->hw.mac_ring_is_up == TRUE
637 * as indication for Ring Operational 637 * as indication for Ring Operational
@@ -764,122 +764,6 @@ void llc_recover_tx(struct s_smc *smc)
764#endif 764#endif
765} 765}
766 766
767/*--------------------------- DMA init ----------------------------*/
768#ifdef ISA
769
770/*
771 * init DMA
772 */
773void init_dma(struct s_smc *smc, int dma)
774{
775 SK_UNUSED(smc) ;
776
777 /*
778 * set cascade mode,
779 * clear mask bit (enable DMA cannal)
780 */
781 if (dma > 3) {
782 outp(0xd6,(dma & 0x03) | 0xc0) ;
783 outp(0xd4, dma & 0x03) ;
784 }
785 else {
786 outp(0x0b,(dma & 0x03) | 0xc0) ;
787 outp(0x0a,dma & 0x03) ;
788 }
789}
790
791/*
792 * disable DMA
793 */
794void dis_dma(struct s_smc *smc, int dma)
795{
796 SK_UNUSED(smc) ;
797
798 /*
799 * set mask bit (disable DMA cannal)
800 */
801 if (dma > 3) {
802 outp(0xd4,(dma & 0x03) | 0x04) ;
803 }
804 else {
805 outp(0x0a,(dma & 0x03) | 0x04) ;
806 }
807}
808
809#endif /* ISA */
810
811#ifdef EISA
812
813/*arrays with io addresses of dma controller length and address registers*/
814static const int cntr[8] = { 0x001,0x003,0x005,0x007,0,0x0c6,0x0ca,0x0ce } ;
815static const int base[8] = { 0x000,0x002,0x004,0x006,0,0x0c4,0x0c8,0x0cc } ;
816static const int page[8] = { 0x087,0x083,0x081,0x082,0,0x08b,0x089,0x08a } ;
817
818void init_dma(struct s_smc *smc, int dma)
819{
820 /*
821 * extended mode register
822 * 32 bit IO
823 * type c
824 * TC output
825 * disable stop
826 */
827
828 /* mode read (write) demand */
829 smc->hw.dma_rmode = (dma & 3) | 0x08 | 0x0 ;
830 smc->hw.dma_wmode = (dma & 3) | 0x04 | 0x0 ;
831
832 /* 32 bit IO's, burst DMA mode (type "C") */
833 smc->hw.dma_emode = (dma & 3) | 0x08 | 0x30 ;
834
835 outp((dma < 4) ? 0x40b : 0x4d6,smc->hw.dma_emode) ;
836
837 /* disable chaining */
838 outp((dma < 4) ? 0x40a : 0x4d4,(dma&3)) ;
839
840 /*load dma controller addresses for fast access during set dma*/
841 smc->hw.dma_base_word_count = cntr[smc->hw.dma];
842 smc->hw.dma_base_address = base[smc->hw.dma];
843 smc->hw.dma_base_address_page = page[smc->hw.dma];
844
845}
846
847void dis_dma(struct s_smc *smc, int dma)
848{
849 SK_UNUSED(smc) ;
850
851 outp((dma < 4) ? 0x0a : 0xd4,(dma&3)|4) ;/* mask bit */
852}
853#endif /* EISA */
854
855#ifdef MCA
856void init_dma(struct s_smc *smc, int dma)
857{
858 SK_UNUSED(smc) ;
859 SK_UNUSED(dma) ;
860}
861
862void dis_dma(struct s_smc *smc, int dma)
863{
864 SK_UNUSED(smc) ;
865 SK_UNUSED(dma) ;
866}
867#endif
868
869#ifdef PCI
870void init_dma(struct s_smc *smc, int dma)
871{
872 SK_UNUSED(smc) ;
873 SK_UNUSED(dma) ;
874}
875
876void dis_dma(struct s_smc *smc, int dma)
877{
878 SK_UNUSED(smc) ;
879 SK_UNUSED(dma) ;
880}
881#endif
882
883#ifdef MULT_OEM 767#ifdef MULT_OEM
884static int is_equal_num(char comp1[], char comp2[], int num) 768static int is_equal_num(char comp1[], char comp2[], int num)
885{ 769{
@@ -1407,7 +1291,7 @@ void smt_start_watchdog(struct s_smc *smc)
1407#endif /* DEBUG */ 1291#endif /* DEBUG */
1408} 1292}
1409 1293
1410void smt_stop_watchdog(struct s_smc *smc) 1294static void smt_stop_watchdog(struct s_smc *smc)
1411{ 1295{
1412 SK_UNUSED(smc) ; /* Make LINT happy. */ 1296 SK_UNUSED(smc) ; /* Make LINT happy. */
1413#ifndef DEBUG 1297#ifndef DEBUG
@@ -1422,104 +1306,6 @@ void smt_stop_watchdog(struct s_smc *smc)
1422} 1306}
1423 1307
1424#ifdef PCI 1308#ifdef PCI
1425static char get_rom_byte(struct s_smc *smc, u_short addr)
1426{
1427 GET_PAGE(addr) ;
1428 return (READ_PROM(ADDR(B2_FDP))) ;
1429}
1430
1431/*
1432 * ROM image defines
1433 */
1434#define ROM_SIG_1 0
1435#define ROM_SIG_2 1
1436#define PCI_DATA_1 0x18
1437#define PCI_DATA_2 0x19
1438
1439/*
1440 * PCI data structure defines
1441 */
1442#define VPD_DATA_1 0x08
1443#define VPD_DATA_2 0x09
1444#define IMAGE_LEN_1 0x10
1445#define IMAGE_LEN_2 0x11
1446#define CODE_TYPE 0x14
1447#define INDICATOR 0x15
1448
1449/*
1450 * BEGIN_MANUAL_ENTRY(mac_drv_vpd_read)
1451 * mac_drv_vpd_read(smc,buf,size,image)
1452 *
1453 * function DOWNCALL (FDDIWARE)
1454 * reads the VPD data of the FPROM and writes it into the
1455 * buffer
1456 *
1457 * para buf points to the buffer for the VPD data
1458 * size size of the VPD data buffer
1459 * image boot image; code type of the boot image
1460 * image = 0 Intel x86, PC-AT compatible
1461 * 1 OPENBOOT standard for PCI
1462 * 2-FF reserved
1463 *
1464 * returns len number of VPD data bytes read form the FPROM
1465 * <0 number of read bytes
1466 * >0 error: data invalid
1467 *
1468 * END_MANUAL_ENTRY
1469 */
1470int mac_drv_vpd_read(struct s_smc *smc, char *buf, int size, char image)
1471{
1472 u_short ibase ;
1473 u_short pci_base ;
1474 u_short vpd ;
1475 int len ;
1476
1477 len = 0 ;
1478 ibase = 0 ;
1479 /*
1480 * as long images defined
1481 */
1482 while (get_rom_byte(smc,ibase+ROM_SIG_1) == 0x55 &&
1483 (u_char) get_rom_byte(smc,ibase+ROM_SIG_2) == 0xaa) {
1484 /*
1485 * get the pointer to the PCI data structure
1486 */
1487 pci_base = ibase + get_rom_byte(smc,ibase+PCI_DATA_1) +
1488 (get_rom_byte(smc,ibase+PCI_DATA_2) << 8) ;
1489
1490 if (image == get_rom_byte(smc,pci_base+CODE_TYPE)) {
1491 /*
1492 * we have the right image, read the VPD data
1493 */
1494 vpd = ibase + get_rom_byte(smc,pci_base+VPD_DATA_1) +
1495 (get_rom_byte(smc,pci_base+VPD_DATA_2) << 8) ;
1496 if (vpd == ibase) {
1497 break ; /* no VPD data */
1498 }
1499 for (len = 0; len < size; len++,buf++,vpd++) {
1500 *buf = get_rom_byte(smc,vpd) ;
1501 }
1502 break ;
1503 }
1504 else {
1505 /*
1506 * try the next image
1507 */
1508 if (get_rom_byte(smc,pci_base+INDICATOR) & 0x80) {
1509 break ; /* this was the last image */
1510 }
1511 ibase = ibase + get_rom_byte(smc,ibase+IMAGE_LEN_1) +
1512 (get_rom_byte(smc,ibase+IMAGE_LEN_2) << 8) ;
1513 }
1514 }
1515
1516 return(len) ;
1517}
1518
1519void mac_drv_pci_fix(struct s_smc *smc, u_long fix_value)
1520{
1521 smc->hw.pci_fix_value = fix_value ;
1522}
1523 1309
1524void mac_do_pci_fix(struct s_smc *smc) 1310void mac_do_pci_fix(struct s_smc *smc)
1525{ 1311{
diff --git a/drivers/net/skfp/ess.c b/drivers/net/skfp/ess.c
index fd39b4b2ef7d..62b01328c496 100644
--- a/drivers/net/skfp/ess.c
+++ b/drivers/net/skfp/ess.c
@@ -102,7 +102,7 @@ void ess_timer_poll(struct s_smc *smc);
102void ess_para_change(struct s_smc *smc); 102void ess_para_change(struct s_smc *smc);
103int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm, 103int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm,
104 int fs); 104 int fs);
105int process_bw_alloc(struct s_smc *smc, long int payload, long int overhead); 105static int process_bw_alloc(struct s_smc *smc, long int payload, long int overhead);
106 106
107 107
108/* 108/*
@@ -375,7 +375,7 @@ int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm,
375 * determines the synchronous bandwidth, set the TSYNC register and the 375 * determines the synchronous bandwidth, set the TSYNC register and the
376 * mib variables SBAPayload, SBAOverhead and fddiMACT-NEG. 376 * mib variables SBAPayload, SBAOverhead and fddiMACT-NEG.
377 */ 377 */
378int process_bw_alloc(struct s_smc *smc, long int payload, long int overhead) 378static int process_bw_alloc(struct s_smc *smc, long int payload, long int overhead)
379{ 379{
380 /* 380 /*
381 * determine the synchronous bandwidth (sync_bw) in bytes per T-NEG, 381 * determine the synchronous bandwidth (sync_bw) in bytes per T-NEG,
diff --git a/drivers/net/skfp/fplustm.c b/drivers/net/skfp/fplustm.c
index 76e78442fc24..a2ed47f1cc70 100644
--- a/drivers/net/skfp/fplustm.c
+++ b/drivers/net/skfp/fplustm.c
@@ -1117,30 +1117,6 @@ void mac_clear_multicast(struct s_smc *smc)
1117/* 1117/*
1118 BEGIN_MANUAL_ENTRY(if,func;others;2) 1118 BEGIN_MANUAL_ENTRY(if,func;others;2)
1119 1119
1120 int mac_set_func_addr(smc,f_addr)
1121 struct s_smc *smc ;
1122 u_long f_addr ;
1123
1124Function DOWNCALL (SMT, fplustm.c)
1125 Set a Token-Ring functional address, the address will
1126 be activated after calling mac_update_multicast()
1127
1128Para f_addr functional bits in non-canonical format
1129
1130Returns 0: always success
1131
1132 END_MANUAL_ENTRY()
1133 */
1134int mac_set_func_addr(struct s_smc *smc, u_long f_addr)
1135{
1136 smc->hw.fp.func_addr = f_addr ;
1137 return(0) ;
1138}
1139
1140
1141/*
1142 BEGIN_MANUAL_ENTRY(if,func;others;2)
1143
1144 int mac_add_multicast(smc,addr,can) 1120 int mac_add_multicast(smc,addr,can)
1145 struct s_smc *smc ; 1121 struct s_smc *smc ;
1146 struct fddi_addr *addr ; 1122 struct fddi_addr *addr ;
@@ -1203,52 +1179,6 @@ int mac_add_multicast(struct s_smc *smc, struct fddi_addr *addr, int can)
1203} 1179}
1204 1180
1205/* 1181/*
1206 BEGIN_MANUAL_ENTRY(if,func;others;2)
1207
1208 void mac_del_multicast(smc,addr,can)
1209 struct s_smc *smc ;
1210 struct fddi_addr *addr ;
1211 int can ;
1212
1213Function DOWNCALL (SMT, fplustm.c)
1214 Delete an entry from the multicast table
1215
1216Para addr pointer to a multicast address
1217 can = 0: the multicast address has the physical format
1218 = 1: the multicast address has the canonical format
1219 | 0x80 permanent
1220
1221 END_MANUAL_ENTRY()
1222 */
1223void mac_del_multicast(struct s_smc *smc, struct fddi_addr *addr, int can)
1224{
1225 SK_LOC_DECL(struct fddi_addr,own) ;
1226 struct s_fpmc *tb ;
1227
1228 if (!(tb = mac_get_mc_table(smc,addr,&own,1,can & ~0x80)))
1229 return ;
1230 /*
1231 * permanent addresses must be deleted with perm bit
1232 * and vice versa
1233 */
1234 if (( tb->perm && (can & 0x80)) ||
1235 (!tb->perm && !(can & 0x80))) {
1236 /*
1237 * delete it
1238 */
1239 if (tb->n) {
1240 tb->n-- ;
1241 if (tb->perm) {
1242 smc->hw.fp.smt_slots_used-- ;
1243 }
1244 else {
1245 smc->hw.fp.os_slots_used-- ;
1246 }
1247 }
1248 }
1249}
1250
1251/*
1252 * mode 1182 * mode
1253 */ 1183 */
1254 1184
diff --git a/drivers/net/skfp/h/cmtdef.h b/drivers/net/skfp/h/cmtdef.h
index 603982debc71..f2f771d8be76 100644
--- a/drivers/net/skfp/h/cmtdef.h
+++ b/drivers/net/skfp/h/cmtdef.h
@@ -507,7 +507,6 @@ void pcm_status_state(struct s_smc *smc, int np, int *type, int *state,
507 int *remote, int *mac); 507 int *remote, int *mac);
508void plc_config_mux(struct s_smc *smc, int mux); 508void plc_config_mux(struct s_smc *smc, int mux);
509void sm_lem_evaluate(struct s_smc *smc); 509void sm_lem_evaluate(struct s_smc *smc);
510void smt_clear_una_dna(struct s_smc *smc);
511void mac_update_counter(struct s_smc *smc); 510void mac_update_counter(struct s_smc *smc);
512void sm_pm_ls_latch(struct s_smc *smc, int phy, int on_off); 511void sm_pm_ls_latch(struct s_smc *smc, int phy, int on_off);
513void sm_ma_control(struct s_smc *smc, int mode); 512void sm_ma_control(struct s_smc *smc, int mode);
@@ -541,11 +540,9 @@ void smt_timer_poll(struct s_smc *smc);
541u_long smt_get_time(void); 540u_long smt_get_time(void);
542u_long smt_get_tid(struct s_smc *smc); 541u_long smt_get_tid(struct s_smc *smc);
543void smt_timer_done(struct s_smc *smc); 542void smt_timer_done(struct s_smc *smc);
544void smt_set_defaults(struct s_smc *smc);
545void smt_fixup_mib(struct s_smc *smc); 543void smt_fixup_mib(struct s_smc *smc);
546void smt_reset_defaults(struct s_smc *smc, int level); 544void smt_reset_defaults(struct s_smc *smc, int level);
547void smt_agent_task(struct s_smc *smc); 545void smt_agent_task(struct s_smc *smc);
548void smt_please_reconnect(struct s_smc *smc, int reconn_time);
549int smt_check_para(struct s_smc *smc, struct smt_header *sm, 546int smt_check_para(struct s_smc *smc, struct smt_header *sm,
550 const u_short list[]); 547 const u_short list[]);
551void driver_get_bia(struct s_smc *smc, struct fddi_addr *bia_addr); 548void driver_get_bia(struct s_smc *smc, struct fddi_addr *bia_addr);
@@ -568,7 +565,6 @@ int pcm_get_s_port(struct s_smc *smc);
568int pcm_rooted_station(struct s_smc *smc); 565int pcm_rooted_station(struct s_smc *smc);
569int cfm_get_mac_input(struct s_smc *smc); 566int cfm_get_mac_input(struct s_smc *smc);
570int cfm_get_mac_output(struct s_smc *smc); 567int cfm_get_mac_output(struct s_smc *smc);
571int port_to_mib(struct s_smc *smc, int p);
572int cem_build_path(struct s_smc *smc, char *to, int path_index); 568int cem_build_path(struct s_smc *smc, char *to, int path_index);
573int sm_mac_get_tx_state(struct s_smc *smc); 569int sm_mac_get_tx_state(struct s_smc *smc);
574char *get_pcmstate(struct s_smc *smc, int np); 570char *get_pcmstate(struct s_smc *smc, int np);
@@ -580,8 +576,6 @@ void smt_send_frame(struct s_smc *smc, SMbuf *mb, int fc, int local);
580void smt_set_timestamp(struct s_smc *smc, u_char *p); 576void smt_set_timestamp(struct s_smc *smc, u_char *p);
581void mac_set_rx_mode(struct s_smc *smc, int mode); 577void mac_set_rx_mode(struct s_smc *smc, int mode);
582int mac_add_multicast(struct s_smc *smc, struct fddi_addr *addr, int can); 578int mac_add_multicast(struct s_smc *smc, struct fddi_addr *addr, int can);
583int mac_set_func_addr(struct s_smc *smc, u_long f_addr);
584void mac_del_multicast(struct s_smc *smc, struct fddi_addr *addr, int can);
585void mac_update_multicast(struct s_smc *smc); 579void mac_update_multicast(struct s_smc *smc);
586void mac_clear_multicast(struct s_smc *smc); 580void mac_clear_multicast(struct s_smc *smc);
587void set_formac_tsync(struct s_smc *smc, long sync_bw); 581void set_formac_tsync(struct s_smc *smc, long sync_bw);
@@ -599,7 +593,6 @@ void plc_irq(struct s_smc *smc, int np, unsigned int cmd);
599int smt_set_mac_opvalues(struct s_smc *smc); 593int smt_set_mac_opvalues(struct s_smc *smc);
600 594
601#ifdef TAG_MODE 595#ifdef TAG_MODE
602void mac_drv_pci_fix(struct s_smc *smc, u_long fix_value);
603void mac_do_pci_fix(struct s_smc *smc); 596void mac_do_pci_fix(struct s_smc *smc);
604void mac_drv_clear_tx_queue(struct s_smc *smc); 597void mac_drv_clear_tx_queue(struct s_smc *smc);
605void mac_drv_repair_descr(struct s_smc *smc); 598void mac_drv_repair_descr(struct s_smc *smc);
diff --git a/drivers/net/skfp/h/hwmtm.h b/drivers/net/skfp/h/hwmtm.h
index 4e360af07d77..1a606d4bfe5e 100644
--- a/drivers/net/skfp/h/hwmtm.h
+++ b/drivers/net/skfp/h/hwmtm.h
@@ -262,31 +262,6 @@ struct os_debug {
262 (smc)->hw.fp.tx_q[queue].tx_curr_put 262 (smc)->hw.fp.tx_q[queue].tx_curr_put
263 263
264/* 264/*
265 * BEGIN_MANUAL_ENTRY(HWM_TX_CHECK)
266 * void HWM_TX_CHECK(smc,frame_status,low_water)
267 *
268 * function MACRO (hardware module, hwmtm.h)
269 * This macro is invoked by the OS-specific before it left it's
270 * driver_send function. This macro calls mac_drv_clear_txd
271 * if the free TxDs of the current transmit queue is equal or
272 * lower than the given low water mark.
273 *
274 * para frame_status status of the frame, see design description
275 * low_water low water mark of free TxD's
276 *
277 * END_MANUAL_ENTRY
278 */
279#ifndef HWM_NO_FLOW_CTL
280#define HWM_TX_CHECK(smc,frame_status,low_water) {\
281 if ((low_water)>=(smc)->hw.fp.tx_q[(frame_status)&QUEUE_A0].tx_free) {\
282 mac_drv_clear_txd(smc) ;\
283 }\
284}
285#else
286#define HWM_TX_CHECK(smc,frame_status,low_water) mac_drv_clear_txd(smc)
287#endif
288
289/*
290 * BEGIN_MANUAL_ENTRY(HWM_GET_RX_FRAG_LEN) 265 * BEGIN_MANUAL_ENTRY(HWM_GET_RX_FRAG_LEN)
291 * int HWM_GET_RX_FRAG_LEN(rxd) 266 * int HWM_GET_RX_FRAG_LEN(rxd)
292 * 267 *
diff --git a/drivers/net/skfp/hwmtm.c b/drivers/net/skfp/hwmtm.c
index 18d429021edb..438f424e6361 100644
--- a/drivers/net/skfp/hwmtm.c
+++ b/drivers/net/skfp/hwmtm.c
@@ -86,6 +86,7 @@ static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue);
86static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue); 86static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue);
87static SMbuf* get_llc_rx(struct s_smc *smc); 87static SMbuf* get_llc_rx(struct s_smc *smc);
88static SMbuf* get_txd_mb(struct s_smc *smc); 88static SMbuf* get_txd_mb(struct s_smc *smc);
89static void mac_drv_clear_txd(struct s_smc *smc);
89 90
90/* 91/*
91 ------------------------------------------------------------- 92 -------------------------------------------------------------
@@ -146,7 +147,6 @@ extern int mac_drv_rx_init(struct s_smc *smc, int len, int fc, char *look_ahead,
146*/ 147*/
147void process_receive(struct s_smc *smc); 148void process_receive(struct s_smc *smc);
148void fddi_isr(struct s_smc *smc); 149void fddi_isr(struct s_smc *smc);
149void mac_drv_clear_txd(struct s_smc *smc);
150void smt_free_mbuf(struct s_smc *smc, SMbuf *mb); 150void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
151void init_driver_fplus(struct s_smc *smc); 151void init_driver_fplus(struct s_smc *smc);
152void mac_drv_rx_mode(struct s_smc *smc, int mode); 152void mac_drv_rx_mode(struct s_smc *smc, int mode);
@@ -158,7 +158,6 @@ void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
158void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len, 158void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
159 int frame_status); 159 int frame_status);
160 160
161int mac_drv_rx_frag(struct s_smc *smc, void far *virt, int len);
162int mac_drv_init(struct s_smc *smc); 161int mac_drv_init(struct s_smc *smc);
163int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len, 162int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
164 int frame_status); 163 int frame_status);
@@ -1448,35 +1447,6 @@ void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1448 NDD_TRACE("RHfE",r,AIX_REVERSE(r->rxd_rbadr),0) ; 1447 NDD_TRACE("RHfE",r,AIX_REVERSE(r->rxd_rbadr),0) ;
1449} 1448}
1450 1449
1451#ifndef NDIS_OS2
1452/*
1453 * BEGIN_MANUAL_ENTRY(mac_drv_rx_frag)
1454 * int mac_drv_rx_frag(smc,virt,len)
1455 *
1456 * function DOWNCALL (hwmtm.c)
1457 * mac_drv_rx_frag fills the fragment with a part of the frame.
1458 *
1459 * para virt the virtual address of the fragment
1460 * len the length in bytes of the fragment
1461 *
1462 * return 0: success code, no errors possible
1463 *
1464 * END_MANUAL_ENTRY
1465 */
1466int mac_drv_rx_frag(struct s_smc *smc, void far *virt, int len)
1467{
1468 NDD_TRACE("RHSB",virt,len,smc->os.hwm.r.mb_pos) ;
1469
1470 DB_RX("receive from queue: len/virt: = %d/%x",len,virt,4) ;
1471 memcpy((char far *)virt,smc->os.hwm.r.mb_pos,len) ;
1472 smc->os.hwm.r.mb_pos += len ;
1473
1474 NDD_TRACE("RHSE",smc->os.hwm.r.mb_pos,0,0) ;
1475 return(0) ;
1476}
1477#endif
1478
1479
1480/* 1450/*
1481 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue) 1451 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue)
1482 * 1452 *
@@ -1978,7 +1948,7 @@ void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc)
1978 * 1948 *
1979 * END_MANUAL_ENTRY 1949 * END_MANUAL_ENTRY
1980 */ 1950 */
1981void mac_drv_clear_txd(struct s_smc *smc) 1951static void mac_drv_clear_txd(struct s_smc *smc)
1982{ 1952{
1983 struct s_smt_tx_queue *queue ; 1953 struct s_smt_tx_queue *queue ;
1984 struct s_smt_fp_txd volatile *t1 ; 1954 struct s_smt_fp_txd volatile *t1 ;
diff --git a/drivers/net/skfp/pcmplc.c b/drivers/net/skfp/pcmplc.c
index 571f055c096b..cd0aa4c151b0 100644
--- a/drivers/net/skfp/pcmplc.c
+++ b/drivers/net/skfp/pcmplc.c
@@ -1861,13 +1861,6 @@ void plc_irq(struct s_smc *smc, int np, unsigned int cmd)
1861#endif 1861#endif
1862} 1862}
1863 1863
1864void pcm_set_lct_short(struct s_smc *smc, int n)
1865{
1866 if (n <= 0 || n > 1000)
1867 return ;
1868 smc->s.lct_short = n ;
1869}
1870
1871#ifdef DEBUG 1864#ifdef DEBUG
1872/* 1865/*
1873 * fill state struct 1866 * fill state struct
diff --git a/drivers/net/skfp/pmf.c b/drivers/net/skfp/pmf.c
index f2b446d8b0bf..efc639c013fd 100644
--- a/drivers/net/skfp/pmf.c
+++ b/drivers/net/skfp/pmf.c
@@ -36,12 +36,13 @@ static int smt_authorize(struct s_smc *smc, struct smt_header *sm);
36static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm); 36static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm);
37static const struct s_p_tab* smt_get_ptab(u_short para); 37static const struct s_p_tab* smt_get_ptab(u_short para);
38static int smt_mib_phys(struct s_smc *smc); 38static int smt_mib_phys(struct s_smc *smc);
39int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index, int local, 39static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
40 int set); 40 int local, int set);
41void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para, 41void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
42 int index, int local); 42 int index, int local);
43static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req, 43static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req,
44 int set, int local); 44 int set, int local);
45static int port_to_mib(struct s_smc *smc, int p);
45 46
46#define MOFFSS(e) ((int)&(((struct fddi_mib *)0)->e)) 47#define MOFFSS(e) ((int)&(((struct fddi_mib *)0)->e))
47#define MOFFSA(e) ((int) (((struct fddi_mib *)0)->e)) 48#define MOFFSA(e) ((int) (((struct fddi_mib *)0)->e))
@@ -1078,8 +1079,8 @@ wrong_error:
1078/* 1079/*
1079 * set parameter 1080 * set parameter
1080 */ 1081 */
1081int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index, int local, 1082static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
1082 int set) 1083 int local, int set)
1083{ 1084{
1084#define IFSET(x) if (set) (x) 1085#define IFSET(x) if (set) (x)
1085 1086
@@ -1549,7 +1550,7 @@ static int smt_mib_phys(struct s_smc *smc)
1549#endif 1550#endif
1550} 1551}
1551 1552
1552int port_to_mib(struct s_smc *smc, int p) 1553static int port_to_mib(struct s_smc *smc, int p)
1553{ 1554{
1554#ifdef CONCENTRATOR 1555#ifdef CONCENTRATOR
1555 SK_UNUSED(smc) ; 1556 SK_UNUSED(smc) ;
diff --git a/drivers/net/skfp/skfddi.c b/drivers/net/skfp/skfddi.c
index c88aad6edd74..4b5ed2c63177 100644
--- a/drivers/net/skfp/skfddi.c
+++ b/drivers/net/skfp/skfddi.c
@@ -149,7 +149,6 @@ extern void hwm_rx_frag(struct s_smc *smc, char far * virt, u_long phys,
149extern void mac_drv_rx_mode(struct s_smc *smc, int mode); 149extern void mac_drv_rx_mode(struct s_smc *smc, int mode);
150extern void mac_drv_clear_rx_queue(struct s_smc *smc); 150extern void mac_drv_clear_rx_queue(struct s_smc *smc);
151extern void enable_tx_irq(struct s_smc *smc, u_short queue); 151extern void enable_tx_irq(struct s_smc *smc, u_short queue);
152extern void mac_drv_clear_txd(struct s_smc *smc);
153 152
154static struct pci_device_id skfddi_pci_tbl[] = { 153static struct pci_device_id skfddi_pci_tbl[] = {
155 { PCI_VENDOR_ID_SK, PCI_DEVICE_ID_SK_FP, PCI_ANY_ID, PCI_ANY_ID, }, 154 { PCI_VENDOR_ID_SK, PCI_DEVICE_ID_SK_FP, PCI_ANY_ID, PCI_ANY_ID, },
diff --git a/drivers/net/skfp/smt.c b/drivers/net/skfp/smt.c
index c3a0d2f10b2b..f17c05cbe44b 100644
--- a/drivers/net/skfp/smt.c
+++ b/drivers/net/skfp/smt.c
@@ -110,7 +110,7 @@ static void smt_fill_setcount(struct s_smc *smc, struct smt_p_setcount *setcount
110static void smt_fill_echo(struct s_smc *smc, struct smt_p_echo *echo, u_long seed, 110static void smt_fill_echo(struct s_smc *smc, struct smt_p_echo *echo, u_long seed,
111 int len); 111 int len);
112 112
113void smt_clear_una_dna(struct s_smc *smc); 113static void smt_clear_una_dna(struct s_smc *smc);
114static void smt_clear_old_una_dna(struct s_smc *smc); 114static void smt_clear_old_una_dna(struct s_smc *smc);
115#ifdef CONCENTRATOR 115#ifdef CONCENTRATOR
116static int entity_to_index(void); 116static int entity_to_index(void);
@@ -118,7 +118,7 @@ static int entity_to_index(void);
118static void update_dac(struct s_smc *smc, int report); 118static void update_dac(struct s_smc *smc, int report);
119static int div_ratio(u_long upper, u_long lower); 119static int div_ratio(u_long upper, u_long lower);
120#ifdef USE_CAN_ADDR 120#ifdef USE_CAN_ADDR
121void hwm_conv_can(struct s_smc *smc, char *data, int len); 121static void hwm_conv_can(struct s_smc *smc, char *data, int len);
122#else 122#else
123#define hwm_conv_can(smc,data,len) 123#define hwm_conv_can(smc,data,len)
124#endif 124#endif
@@ -216,24 +216,6 @@ void smt_agent_task(struct s_smc *smc)
216 DB_SMT("SMT agent task\n",0,0) ; 216 DB_SMT("SMT agent task\n",0,0) ;
217} 217}
218 218
219void smt_please_reconnect(struct s_smc *smc, int reconn_time)
220/* struct s_smc *smc; Pointer to SMT context */
221/* int reconn_time; Wait for reconnect time in seconds */
222{
223 /*
224 * The please reconnect variable is used as a timer.
225 * It is decremented each time smt_event is called.
226 * This happens every second or when smt_force_irq is called.
227 * Note: smt_force_irq () is called on some packet receives and
228 * when a multicast address is changed. Since nothing
229 * is received during the disconnect and the multicast
230 * address changes can be viewed as not very often and
231 * the timer runs out close to its given value
232 * (reconn_time).
233 */
234 smc->sm.please_reconnect = reconn_time ;
235}
236
237#ifndef SMT_REAL_TOKEN_CT 219#ifndef SMT_REAL_TOKEN_CT
238void smt_emulate_token_ct(struct s_smc *smc, int mac_index) 220void smt_emulate_token_ct(struct s_smc *smc, int mac_index)
239{ 221{
@@ -1574,7 +1556,7 @@ static void smt_fill_echo(struct s_smc *smc, struct smt_p_echo *echo, u_long see
1574 * clear DNA and UNA 1556 * clear DNA and UNA
1575 * called from CFM if configuration changes 1557 * called from CFM if configuration changes
1576 */ 1558 */
1577void smt_clear_una_dna(struct s_smc *smc) 1559static void smt_clear_una_dna(struct s_smc *smc)
1578{ 1560{
1579 smc->mib.m[MAC0].fddiMACUpstreamNbr = SMT_Unknown ; 1561 smc->mib.m[MAC0].fddiMACUpstreamNbr = SMT_Unknown ;
1580 smc->mib.m[MAC0].fddiMACDownstreamNbr = SMT_Unknown ; 1562 smc->mib.m[MAC0].fddiMACDownstreamNbr = SMT_Unknown ;
@@ -2058,30 +2040,10 @@ int smt_action(struct s_smc *smc, int class, int code, int index)
2058} 2040}
2059 2041
2060/* 2042/*
2061 * change tneg
2062 * set T_Req in MIB (Path Attribute)
2063 * calculate new values for MAC
2064 * if change required
2065 * disconnect
2066 * set reconnect
2067 * end
2068 */
2069void smt_change_t_neg(struct s_smc *smc, u_long tneg)
2070{
2071 smc->mib.a[PATH0].fddiPATHMaxT_Req = tneg ;
2072
2073 if (smt_set_mac_opvalues(smc)) {
2074 RS_SET(smc,RS_EVENT) ;
2075 smc->sm.please_reconnect = 1 ;
2076 queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
2077 }
2078}
2079
2080/*
2081 * canonical conversion of <len> bytes beginning form *data 2043 * canonical conversion of <len> bytes beginning form *data
2082 */ 2044 */
2083#ifdef USE_CAN_ADDR 2045#ifdef USE_CAN_ADDR
2084void hwm_conv_can(struct s_smc *smc, char *data, int len) 2046static void hwm_conv_can(struct s_smc *smc, char *data, int len)
2085{ 2047{
2086 int i ; 2048 int i ;
2087 2049
diff --git a/drivers/net/skfp/smtdef.c b/drivers/net/skfp/smtdef.c
index 5a0c8db816d8..4e07ff7073f1 100644
--- a/drivers/net/skfp/smtdef.c
+++ b/drivers/net/skfp/smtdef.c
@@ -76,11 +76,6 @@ void smt_reset_defaults(struct s_smc *smc, int level);
76static void smt_init_mib(struct s_smc *smc, int level); 76static void smt_init_mib(struct s_smc *smc, int level);
77static int set_min_max(int maxflag, u_long mib, u_long limit, u_long *oper); 77static int set_min_max(int maxflag, u_long mib, u_long limit, u_long *oper);
78 78
79void smt_set_defaults(struct s_smc *smc)
80{
81 smt_reset_defaults(smc,0) ;
82}
83
84#define MS2BCLK(x) ((x)*12500L) 79#define MS2BCLK(x) ((x)*12500L)
85#define US2BCLK(x) ((x)*1250L) 80#define US2BCLK(x) ((x)*1250L)
86 81
diff --git a/drivers/net/skfp/smtparse.c b/drivers/net/skfp/smtparse.c
deleted file mode 100644
index d5779e414dbe..000000000000
--- a/drivers/net/skfp/smtparse.c
+++ /dev/null
@@ -1,467 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17
18/*
19 parser for SMT parameters
20*/
21
22#include "h/types.h"
23#include "h/fddi.h"
24#include "h/smc.h"
25#include "h/smt_p.h"
26
27#define KERNEL
28#include "h/smtstate.h"
29
30#ifndef lint
31static const char ID_sccs[] = "@(#)smtparse.c 1.12 98/10/06 (C) SK " ;
32#endif
33
34#ifdef sun
35#define _far
36#endif
37
38/*
39 * convert to BCLK units
40 */
41#define MS2BCLK(x) ((x)*12500L)
42#define US2BCLK(x) ((x/10)*125L)
43
44/*
45 * parameter table
46 */
47static struct s_ptab {
48 char *pt_name ;
49 u_short pt_num ;
50 u_short pt_type ;
51 u_long pt_min ;
52 u_long pt_max ;
53} ptab[] = {
54 { "PMFPASSWD",0, 0 } ,
55 { "USERDATA",1, 0 } ,
56 { "LERCUTOFFA",2, 1, 4, 15 } ,
57 { "LERCUTOFFB",3, 1, 4, 15 } ,
58 { "LERALARMA",4, 1, 4, 15 } ,
59 { "LERALARMB",5, 1, 4, 15 } ,
60 { "TMAX",6, 1, 5, 165 } ,
61 { "TMIN",7, 1, 5, 165 } ,
62 { "TREQ",8, 1, 5, 165 } ,
63 { "TVX",9, 1, 2500, 10000 } ,
64#ifdef ESS
65 { "SBAPAYLOAD",10, 1, 0, 1562 } ,
66 { "SBAOVERHEAD",11, 1, 50, 5000 } ,
67 { "MAXTNEG",12, 1, 5, 165 } ,
68 { "MINSEGMENTSIZE",13, 1, 0, 4478 } ,
69 { "SBACATEGORY",14, 1, 0, 0xffff } ,
70 { "SYNCHTXMODE",15, 0 } ,
71#endif
72#ifdef SBA
73 { "SBACOMMAND",16, 0 } ,
74 { "SBAAVAILABLE",17, 1, 0, 100 } ,
75#endif
76 { NULL }
77} ;
78
79/* Define maximum string size for values and keybuffer */
80#define MAX_VAL 40
81
82/*
83 * local function declarations
84 */
85static u_long parse_num(int type, char _far *value, char *v, u_long mn,
86 u_long mx, int scale);
87static int parse_word(char *buf, char _far *text);
88
89#ifdef SIM
90#define DB_MAIN(a,b,c) printf(a,b,c)
91#else
92#define DB_MAIN(a,b,c)
93#endif
94
95/*
96 * BEGIN_MANUAL_ENTRY()
97 *
98 * int smt_parse_arg(struct s_smc *,char _far *keyword,int type,
99 char _far *value)
100 *
101 * parse SMT parameter
102 * *keyword
103 * pointer to keyword, must be \0, \n or \r terminated
104 * *value pointer to value, either char * or u_long *
105 * if char *
106 * pointer to value, must be \0, \n or \r terminated
107 * if u_long *
108 * contains binary value
109 *
110 * type 0: integer
111 * 1: string
112 * return
113 * 0 parameter parsed ok
114 * != 0 error
115 * NOTE:
116 * function can be called with DS != SS
117 *
118 *
119 * END_MANUAL_ENTRY()
120 */
121int smt_parse_arg(struct s_smc *smc, char _far *keyword, int type,
122 char _far *value)
123{
124 char keybuf[MAX_VAL+1];
125 char valbuf[MAX_VAL+1];
126 char c ;
127 char *p ;
128 char *v ;
129 char *d ;
130 u_long val = 0 ;
131 struct s_ptab *pt ;
132 int st ;
133 int i ;
134
135 /*
136 * parse keyword
137 */
138 if ((st = parse_word(keybuf,keyword)))
139 return(st) ;
140 /*
141 * parse value if given as string
142 */
143 if (type == 1) {
144 if ((st = parse_word(valbuf,value)))
145 return(st) ;
146 }
147 /*
148 * search in table
149 */
150 st = 0 ;
151 for (pt = ptab ; (v = pt->pt_name) ; pt++) {
152 for (p = keybuf ; (c = *p) ; p++,v++) {
153 if (c != *v)
154 break ;
155 }
156 if (!c && !*v)
157 break ;
158 }
159 if (!v)
160 return(-1) ;
161#if 0
162 printf("=>%s<==>%s<=\n",pt->pt_name,valbuf) ;
163#endif
164 /*
165 * set value in MIB
166 */
167 if (pt->pt_type)
168 val = parse_num(type,value,valbuf,pt->pt_min,pt->pt_max,1) ;
169 switch (pt->pt_num) {
170 case 0 :
171 v = valbuf ;
172 d = (char *) smc->mib.fddiPRPMFPasswd ;
173 for (i = 0 ; i < (signed)sizeof(smc->mib.fddiPRPMFPasswd) ; i++)
174 *d++ = *v++ ;
175 DB_MAIN("SET %s = %s\n",pt->pt_name,smc->mib.fddiPRPMFPasswd) ;
176 break ;
177 case 1 :
178 v = valbuf ;
179 d = (char *) smc->mib.fddiSMTUserData ;
180 for (i = 0 ; i < (signed)sizeof(smc->mib.fddiSMTUserData) ; i++)
181 *d++ = *v++ ;
182 DB_MAIN("SET %s = %s\n",pt->pt_name,smc->mib.fddiSMTUserData) ;
183 break ;
184 case 2 :
185 smc->mib.p[PA].fddiPORTLer_Cutoff = (u_char) val ;
186 DB_MAIN("SET %s = %d\n",
187 pt->pt_name,smc->mib.p[PA].fddiPORTLer_Cutoff) ;
188 break ;
189 case 3 :
190 smc->mib.p[PB].fddiPORTLer_Cutoff = (u_char) val ;
191 DB_MAIN("SET %s = %d\n",
192 pt->pt_name,smc->mib.p[PB].fddiPORTLer_Cutoff) ;
193 break ;
194 case 4 :
195 smc->mib.p[PA].fddiPORTLer_Alarm = (u_char) val ;
196 DB_MAIN("SET %s = %d\n",
197 pt->pt_name,smc->mib.p[PA].fddiPORTLer_Alarm) ;
198 break ;
199 case 5 :
200 smc->mib.p[PB].fddiPORTLer_Alarm = (u_char) val ;
201 DB_MAIN("SET %s = %d\n",
202 pt->pt_name,smc->mib.p[PB].fddiPORTLer_Alarm) ;
203 break ;
204 case 6 : /* TMAX */
205 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
206 smc->mib.a[PATH0].fddiPATHT_MaxLowerBound =
207 (u_long) -MS2BCLK((long)val) ;
208 break ;
209 case 7 : /* TMIN */
210 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
211 smc->mib.m[MAC0].fddiMACT_Min =
212 (u_long) -MS2BCLK((long)val) ;
213 break ;
214 case 8 : /* TREQ */
215 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
216 smc->mib.a[PATH0].fddiPATHMaxT_Req =
217 (u_long) -MS2BCLK((long)val) ;
218 break ;
219 case 9 : /* TVX */
220 DB_MAIN("SET %s = %d \n",pt->pt_name,val) ;
221 smc->mib.a[PATH0].fddiPATHTVXLowerBound =
222 (u_long) -US2BCLK((long)val) ;
223 break ;
224#ifdef ESS
225 case 10 : /* SBAPAYLOAD */
226 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
227 if (smc->mib.fddiESSPayload != val) {
228 smc->ess.raf_act_timer_poll = TRUE ;
229 smc->mib.fddiESSPayload = val ;
230 }
231 break ;
232 case 11 : /* SBAOVERHEAD */
233 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
234 smc->mib.fddiESSOverhead = val ;
235 break ;
236 case 12 : /* MAXTNEG */
237 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
238 smc->mib.fddiESSMaxTNeg = (u_long) -MS2BCLK((long)val) ;
239 break ;
240 case 13 : /* MINSEGMENTSIZE */
241 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
242 smc->mib.fddiESSMinSegmentSize = val ;
243 break ;
244 case 14 : /* SBACATEGORY */
245 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
246 smc->mib.fddiESSCategory =
247 (smc->mib.fddiESSCategory & 0xffff) |
248 ((u_long)(val << 16)) ;
249 break ;
250 case 15 : /* SYNCHTXMODE */
251 /* do not use memcmp(valbuf,"ALL",3) because DS != SS */
252 if (valbuf[0] == 'A' && valbuf[1] == 'L' && valbuf[2] == 'L') {
253 smc->mib.fddiESSSynchTxMode = TRUE ;
254 DB_MAIN("SET %s = %s\n",pt->pt_name,valbuf) ;
255 }
256 /* if (!memcmp(valbuf,"SPLIT",5)) { */
257 if (valbuf[0] == 'S' && valbuf[1] == 'P' && valbuf[2] == 'L' &&
258 valbuf[3] == 'I' && valbuf[4] == 'T') {
259 DB_MAIN("SET %s = %s\n",pt->pt_name,valbuf) ;
260 smc->mib.fddiESSSynchTxMode = FALSE ;
261 }
262 break ;
263#endif
264#ifdef SBA
265 case 16 : /* SBACOMMAND */
266 /* if (!memcmp(valbuf,"START",5)) { */
267 if (valbuf[0] == 'S' && valbuf[1] == 'T' && valbuf[2] == 'A' &&
268 valbuf[3] == 'R' && valbuf[4] == 'T') {
269 DB_MAIN("SET %s = %s\n",pt->pt_name,valbuf) ;
270 smc->mib.fddiSBACommand = SB_START ;
271 }
272 /* if (!memcmp(valbuf,"STOP",4)) { */
273 if (valbuf[0] == 'S' && valbuf[1] == 'T' && valbuf[2] == 'O' &&
274 valbuf[3] == 'P') {
275 DB_MAIN("SET %s = %s\n",pt->pt_name,valbuf) ;
276 smc->mib.fddiSBACommand = SB_STOP ;
277 }
278 break ;
279 case 17 : /* SBAAVAILABLE */
280 DB_MAIN("SET %s = %d\n",pt->pt_name,val) ;
281 smc->mib.fddiSBAAvailable = (u_char) val ;
282 break ;
283#endif
284 }
285 return(0) ;
286}
287
288static int parse_word(char *buf, char _far *text)
289{
290 char c ;
291 char *p ;
292 int p_len ;
293 int quote ;
294 int i ;
295 int ok ;
296
297 /*
298 * skip leading white space
299 */
300 p = buf ;
301 for (i = 0 ; i < MAX_VAL ; i++)
302 *p++ = 0 ;
303 p = buf ;
304 p_len = 0 ;
305 ok = 0 ;
306 while ( (c = *text++) && (c != '\n') && (c != '\r')) {
307 if ((c != ' ') && (c != '\t')) {
308 ok = 1 ;
309 break ;
310 }
311 }
312 if (!ok)
313 return(-1) ;
314 if (c == '"') {
315 quote = 1 ;
316 }
317 else {
318 quote = 0 ;
319 text-- ;
320 }
321 /*
322 * parse valbuf
323 */
324 ok = 0 ;
325 while (!ok && p_len < MAX_VAL-1 && (c = *text++) && (c != '\n')
326 && (c != '\r')) {
327 switch (quote) {
328 case 0 :
329 if ((c == ' ') || (c == '\t') || (c == '=')) {
330 ok = 1 ;
331 break ;
332 }
333 *p++ = c ;
334 p_len++ ;
335 break ;
336 case 2 :
337 *p++ = c ;
338 p_len++ ;
339 quote = 1 ;
340 break ;
341 case 1 :
342 switch (c) {
343 case '"' :
344 ok = 1 ;
345 break ;
346 case '\\' :
347 quote = 2 ;
348 break ;
349 default :
350 *p++ = c ;
351 p_len++ ;
352 }
353 }
354 }
355 *p++ = 0 ;
356 for (p = buf ; (c = *p) ; p++) {
357 if (c >= 'a' && c <= 'z')
358 *p = c + 'A' - 'a' ;
359 }
360 return(0) ;
361}
362
363static u_long parse_num(int type, char _far *value, char *v, u_long mn,
364 u_long mx, int scale)
365{
366 u_long x = 0 ;
367 char c ;
368
369 if (type == 0) { /* integer */
370 u_long _far *l ;
371 u_long u1 ;
372
373 l = (u_long _far *) value ;
374 u1 = *l ;
375 /*
376 * if the value is negative take the lower limit
377 */
378 if ((long)u1 < 0) {
379 if (- ((long)u1) > (long) mx) {
380 u1 = 0 ;
381 }
382 else {
383 u1 = (u_long) - ((long)u1) ;
384 }
385 }
386 x = u1 ;
387 }
388 else { /* string */
389 int sign = 0 ;
390
391 if (*v == '-') {
392 sign = 1 ;
393 }
394 while ((c = *v++) && (c >= '0') && (c <= '9')) {
395 x = x * 10 + c - '0' ;
396 }
397 if (scale == 10) {
398 x *= 10 ;
399 if (c == '.') {
400 if ((c = *v++) && (c >= '0') && (c <= '9')) {
401 x += c - '0' ;
402 }
403 }
404 }
405 if (sign)
406 x = (u_long) - ((long)x) ;
407 }
408 /*
409 * if the value is negative
410 * and the absolute value is outside the limits
411 * take the lower limit
412 * else
413 * take the absoute value
414 */
415 if ((long)x < 0) {
416 if (- ((long)x) > (long) mx) {
417 x = 0 ;
418 }
419 else {
420 x = (u_long) - ((long)x) ;
421 }
422 }
423 if (x < mn)
424 return(mn) ;
425 else if (x > mx)
426 return(mx) ;
427 return(x) ;
428}
429
430#if 0
431struct s_smc SMC ;
432main()
433{
434 char *p ;
435 char *v ;
436 char buf[100] ;
437 int toggle = 0 ;
438
439 while (gets(buf)) {
440 p = buf ;
441 while (*p && ((*p == ' ') || (*p == '\t')))
442 p++ ;
443
444 while (*p && ((*p != ' ') && (*p != '\t')))
445 p++ ;
446
447 v = p ;
448 while (*v && ((*v == ' ') || (*v == '\t')))
449 v++ ;
450 if ((*v >= '0') && (*v <= '9')) {
451 toggle = !toggle ;
452 if (toggle) {
453 u_long l ;
454 l = atol(v) ;
455 smt_parse_arg(&SMC,buf,0,(char _far *)&l) ;
456 }
457 else
458 smt_parse_arg(&SMC,buf,1,(char _far *)p) ;
459 }
460 else {
461 smt_parse_arg(&SMC,buf,1,(char _far *)p) ;
462 }
463 }
464 exit(0) ;
465}
466#endif
467
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 30e8d589d167..3dbb1cb09ed8 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -7,7 +7,7 @@
7 * of the original driver such as link fail-over and link management because 7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels. 8 * those should be done at higher levels.
9 * 9 *
10 * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org> 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 13 * it under the terms of the GNU General Public License as published by
@@ -42,19 +42,20 @@
42#include "skge.h" 42#include "skge.h"
43 43
44#define DRV_NAME "skge" 44#define DRV_NAME "skge"
45#define DRV_VERSION "0.6" 45#define DRV_VERSION "0.7"
46#define PFX DRV_NAME " " 46#define PFX DRV_NAME " "
47 47
48#define DEFAULT_TX_RING_SIZE 128 48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512 49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024 50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096 51#define MAX_RX_RING_SIZE 4096
52#define RX_COPY_THRESHOLD 128
53#define RX_BUF_SIZE 1536
52#define PHY_RETRIES 1000 54#define PHY_RETRIES 1000
53#define ETH_JUMBO_MTU 9000 55#define ETH_JUMBO_MTU 9000
54#define TX_WATCHDOG (5 * HZ) 56#define TX_WATCHDOG (5 * HZ)
55#define NAPI_WEIGHT 64 57#define NAPI_WEIGHT 64
56#define BLINK_HZ (HZ/4) 58#define BLINK_HZ (HZ/4)
57#define LINK_POLL_HZ (HZ/10)
58 59
59MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); 60MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); 61MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
@@ -70,28 +71,17 @@ module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 71MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71 72
72static const struct pci_device_id skge_id_table[] = { 73static const struct pci_device_id skge_id_table[] = {
73 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940, 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
74 PCI_ANY_ID, PCI_ANY_ID }, 75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
75 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B, 76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
76 PCI_ANY_ID, PCI_ANY_ID }, 77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
77 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE, 78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
78 PCI_ANY_ID, PCI_ANY_ID }, 79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU, 80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 PCI_ANY_ID, PCI_ANY_ID }, 81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_VENDOR_ID_SYSKONNECT, 0x9E00, /* SK-9Exx */ 82 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 PCI_ANY_ID, PCI_ANY_ID }, 83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T, 84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
84 PCI_ANY_ID, PCI_ANY_ID },
85 { PCI_VENDOR_ID_MARVELL, 0x4320, /* Gigabit Ethernet Controller */
86 PCI_ANY_ID, PCI_ANY_ID },
87 { PCI_VENDOR_ID_MARVELL, 0x5005, /* Marvell (11ab), Belkin */
88 PCI_ANY_ID, PCI_ANY_ID },
89 { PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD,
90 PCI_ANY_ID, PCI_ANY_ID },
91 { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032,
92 PCI_ANY_ID, PCI_ANY_ID },
93 { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064,
94 PCI_ANY_ID, PCI_ANY_ID },
95 { 0 } 85 { 0 }
96}; 86};
97MODULE_DEVICE_TABLE(pci, skge_id_table); 87MODULE_DEVICE_TABLE(pci, skge_id_table);
@@ -99,19 +89,22 @@ MODULE_DEVICE_TABLE(pci, skge_id_table);
99static int skge_up(struct net_device *dev); 89static int skge_up(struct net_device *dev);
100static int skge_down(struct net_device *dev); 90static int skge_down(struct net_device *dev);
101static void skge_tx_clean(struct skge_port *skge); 91static void skge_tx_clean(struct skge_port *skge);
102static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 92static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 93static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
104static void genesis_get_stats(struct skge_port *skge, u64 *data); 94static void genesis_get_stats(struct skge_port *skge, u64 *data);
105static void yukon_get_stats(struct skge_port *skge, u64 *data); 95static void yukon_get_stats(struct skge_port *skge, u64 *data);
106static void yukon_init(struct skge_hw *hw, int port); 96static void yukon_init(struct skge_hw *hw, int port);
107static void yukon_reset(struct skge_hw *hw, int port); 97static void yukon_reset(struct skge_hw *hw, int port);
108static void genesis_mac_init(struct skge_hw *hw, int port); 98static void genesis_mac_init(struct skge_hw *hw, int port);
109static void genesis_reset(struct skge_hw *hw, int port); 99static void genesis_reset(struct skge_hw *hw, int port);
100static void genesis_link_up(struct skge_port *skge);
110 101
102/* Avoid conditionals by using array */
111static const int txqaddr[] = { Q_XA1, Q_XA2 }; 103static const int txqaddr[] = { Q_XA1, Q_XA2 };
112static const int rxqaddr[] = { Q_R1, Q_R2 }; 104static const int rxqaddr[] = { Q_R1, Q_R2 };
113static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 105static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
114static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 106static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
115 108
116/* Don't need to look at whole 16K. 109/* Don't need to look at whole 16K.
117 * last interesting register is descriptor poll timer. 110 * last interesting register is descriptor poll timer.
@@ -154,7 +147,7 @@ static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
154static int wol_supported(const struct skge_hw *hw) 147static int wol_supported(const struct skge_hw *hw)
155{ 148{
156 return !((hw->chip_id == CHIP_ID_GENESIS || 149 return !((hw->chip_id == CHIP_ID_GENESIS ||
157 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0))); 150 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
158} 151}
159 152
160static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 153static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
@@ -170,7 +163,7 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
170 struct skge_port *skge = netdev_priv(dev); 163 struct skge_port *skge = netdev_priv(dev);
171 struct skge_hw *hw = skge->hw; 164 struct skge_hw *hw = skge->hw;
172 165
173 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) 166 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
174 return -EOPNOTSUPP; 167 return -EOPNOTSUPP;
175 168
176 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw)) 169 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
@@ -190,6 +183,36 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
190 return 0; 183 return 0;
191} 184}
192 185
186/* Determine supported/adverised modes based on hardware.
187 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
188 */
189static u32 skge_supported_modes(const struct skge_hw *hw)
190{
191 u32 supported;
192
193 if (iscopper(hw)) {
194 supported = SUPPORTED_10baseT_Half
195 | SUPPORTED_10baseT_Full
196 | SUPPORTED_100baseT_Half
197 | SUPPORTED_100baseT_Full
198 | SUPPORTED_1000baseT_Half
199 | SUPPORTED_1000baseT_Full
200 | SUPPORTED_Autoneg| SUPPORTED_TP;
201
202 if (hw->chip_id == CHIP_ID_GENESIS)
203 supported &= ~(SUPPORTED_10baseT_Half
204 | SUPPORTED_10baseT_Full
205 | SUPPORTED_100baseT_Half
206 | SUPPORTED_100baseT_Full);
207
208 else if (hw->chip_id == CHIP_ID_YUKON)
209 supported &= ~SUPPORTED_1000baseT_Half;
210 } else
211 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
212 | SUPPORTED_Autoneg;
213
214 return supported;
215}
193 216
194static int skge_get_settings(struct net_device *dev, 217static int skge_get_settings(struct net_device *dev,
195 struct ethtool_cmd *ecmd) 218 struct ethtool_cmd *ecmd)
@@ -198,38 +221,13 @@ static int skge_get_settings(struct net_device *dev,
198 struct skge_hw *hw = skge->hw; 221 struct skge_hw *hw = skge->hw;
199 222
200 ecmd->transceiver = XCVR_INTERNAL; 223 ecmd->transceiver = XCVR_INTERNAL;
224 ecmd->supported = skge_supported_modes(hw);
201 225
202 if (iscopper(hw)) { 226 if (iscopper(hw)) {
203 if (hw->chip_id == CHIP_ID_GENESIS)
204 ecmd->supported = SUPPORTED_1000baseT_Full
205 | SUPPORTED_1000baseT_Half
206 | SUPPORTED_Autoneg | SUPPORTED_TP;
207 else {
208 ecmd->supported = SUPPORTED_10baseT_Half
209 | SUPPORTED_10baseT_Full
210 | SUPPORTED_100baseT_Half
211 | SUPPORTED_100baseT_Full
212 | SUPPORTED_1000baseT_Half
213 | SUPPORTED_1000baseT_Full
214 | SUPPORTED_Autoneg| SUPPORTED_TP;
215
216 if (hw->chip_id == CHIP_ID_YUKON)
217 ecmd->supported &= ~SUPPORTED_1000baseT_Half;
218
219 else if (hw->chip_id == CHIP_ID_YUKON_FE)
220 ecmd->supported &= ~(SUPPORTED_1000baseT_Half
221 | SUPPORTED_1000baseT_Full);
222 }
223
224 ecmd->port = PORT_TP; 227 ecmd->port = PORT_TP;
225 ecmd->phy_address = hw->phy_addr; 228 ecmd->phy_address = hw->phy_addr;
226 } else { 229 } else
227 ecmd->supported = SUPPORTED_1000baseT_Full
228 | SUPPORTED_FIBRE
229 | SUPPORTED_Autoneg;
230
231 ecmd->port = PORT_FIBRE; 230 ecmd->port = PORT_FIBRE;
232 }
233 231
234 ecmd->advertising = skge->advertising; 232 ecmd->advertising = skge->advertising;
235 ecmd->autoneg = skge->autoneg; 233 ecmd->autoneg = skge->autoneg;
@@ -238,65 +236,57 @@ static int skge_get_settings(struct net_device *dev,
238 return 0; 236 return 0;
239} 237}
240 238
241static u32 skge_modes(const struct skge_hw *hw)
242{
243 u32 modes = ADVERTISED_Autoneg
244 | ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half
245 | ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half
246 | ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half;
247
248 if (iscopper(hw)) {
249 modes |= ADVERTISED_TP;
250 switch(hw->chip_id) {
251 case CHIP_ID_GENESIS:
252 modes &= ~(ADVERTISED_100baseT_Full
253 | ADVERTISED_100baseT_Half
254 | ADVERTISED_10baseT_Full
255 | ADVERTISED_10baseT_Half);
256 break;
257
258 case CHIP_ID_YUKON:
259 modes &= ~ADVERTISED_1000baseT_Half;
260 break;
261
262 case CHIP_ID_YUKON_FE:
263 modes &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
264 break;
265 }
266 } else {
267 modes |= ADVERTISED_FIBRE;
268 modes &= ~ADVERTISED_1000baseT_Half;
269 }
270 return modes;
271}
272
273static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 239static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
274{ 240{
275 struct skge_port *skge = netdev_priv(dev); 241 struct skge_port *skge = netdev_priv(dev);
276 const struct skge_hw *hw = skge->hw; 242 const struct skge_hw *hw = skge->hw;
243 u32 supported = skge_supported_modes(hw);
277 244
278 if (ecmd->autoneg == AUTONEG_ENABLE) { 245 if (ecmd->autoneg == AUTONEG_ENABLE) {
279 if (ecmd->advertising & skge_modes(hw)) 246 ecmd->advertising = supported;
280 return -EINVAL; 247 skge->duplex = -1;
248 skge->speed = -1;
281 } else { 249 } else {
250 u32 setting;
251
282 switch(ecmd->speed) { 252 switch(ecmd->speed) {
283 case SPEED_1000: 253 case SPEED_1000:
284 if (hw->chip_id == CHIP_ID_YUKON_FE) 254 if (ecmd->duplex == DUPLEX_FULL)
255 setting = SUPPORTED_1000baseT_Full;
256 else if (ecmd->duplex == DUPLEX_HALF)
257 setting = SUPPORTED_1000baseT_Half;
258 else
285 return -EINVAL; 259 return -EINVAL;
286 break; 260 break;
287 case SPEED_100: 261 case SPEED_100:
262 if (ecmd->duplex == DUPLEX_FULL)
263 setting = SUPPORTED_100baseT_Full;
264 else if (ecmd->duplex == DUPLEX_HALF)
265 setting = SUPPORTED_100baseT_Half;
266 else
267 return -EINVAL;
268 break;
269
288 case SPEED_10: 270 case SPEED_10:
289 if (iscopper(hw) || hw->chip_id == CHIP_ID_GENESIS) 271 if (ecmd->duplex == DUPLEX_FULL)
272 setting = SUPPORTED_10baseT_Full;
273 else if (ecmd->duplex == DUPLEX_HALF)
274 setting = SUPPORTED_10baseT_Half;
275 else
290 return -EINVAL; 276 return -EINVAL;
291 break; 277 break;
292 default: 278 default:
293 return -EINVAL; 279 return -EINVAL;
294 } 280 }
281
282 if ((setting & supported) == 0)
283 return -EINVAL;
284
285 skge->speed = ecmd->speed;
286 skge->duplex = ecmd->duplex;
295 } 287 }
296 288
297 skge->autoneg = ecmd->autoneg; 289 skge->autoneg = ecmd->autoneg;
298 skge->speed = ecmd->speed;
299 skge->duplex = ecmd->duplex;
300 skge->advertising = ecmd->advertising; 290 skge->advertising = ecmd->advertising;
301 291
302 if (netif_running(dev)) { 292 if (netif_running(dev)) {
@@ -393,7 +383,7 @@ static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
393{ 383{
394 int i; 384 int i;
395 385
396 switch(stringset) { 386 switch (stringset) {
397 case ETH_SS_STATS: 387 case ETH_SS_STATS:
398 for (i = 0; i < ARRAY_SIZE(skge_stats); i++) 388 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
399 memcpy(data + i * ETH_GSTRING_LEN, 389 memcpy(data + i * ETH_GSTRING_LEN,
@@ -511,14 +501,6 @@ static int skge_set_rx_csum(struct net_device *dev, u32 data)
511 return 0; 501 return 0;
512} 502}
513 503
514/* Only Yukon II supports TSO (not implemented yet) */
515static int skge_set_tso(struct net_device *dev, u32 data)
516{
517 if (data)
518 return -EOPNOTSUPP;
519 return 0;
520}
521
522static void skge_get_pauseparam(struct net_device *dev, 504static void skge_get_pauseparam(struct net_device *dev,
523 struct ethtool_pauseparam *ecmd) 505 struct ethtool_pauseparam *ecmd)
524{ 506{
@@ -540,9 +522,9 @@ static int skge_set_pauseparam(struct net_device *dev,
540 skge->autoneg = ecmd->autoneg; 522 skge->autoneg = ecmd->autoneg;
541 if (ecmd->rx_pause && ecmd->tx_pause) 523 if (ecmd->rx_pause && ecmd->tx_pause)
542 skge->flow_control = FLOW_MODE_SYMMETRIC; 524 skge->flow_control = FLOW_MODE_SYMMETRIC;
543 else if(ecmd->rx_pause && !ecmd->tx_pause) 525 else if (ecmd->rx_pause && !ecmd->tx_pause)
544 skge->flow_control = FLOW_MODE_REM_SEND; 526 skge->flow_control = FLOW_MODE_REM_SEND;
545 else if(!ecmd->rx_pause && ecmd->tx_pause) 527 else if (!ecmd->rx_pause && ecmd->tx_pause)
546 skge->flow_control = FLOW_MODE_LOC_SEND; 528 skge->flow_control = FLOW_MODE_LOC_SEND;
547 else 529 else
548 skge->flow_control = FLOW_MODE_NONE; 530 skge->flow_control = FLOW_MODE_NONE;
@@ -559,8 +541,6 @@ static inline u32 hwkhz(const struct skge_hw *hw)
559{ 541{
560 if (hw->chip_id == CHIP_ID_GENESIS) 542 if (hw->chip_id == CHIP_ID_GENESIS)
561 return 53215; /* or: 53.125 MHz */ 543 return 53215; /* or: 53.125 MHz */
562 else if (hw->chip_id == CHIP_ID_YUKON_EC)
563 return 125000; /* or: 125.000 MHz */
564 else 544 else
565 return 78215; /* or: 78.125 MHz */ 545 return 78215; /* or: 78.125 MHz */
566} 546}
@@ -643,30 +623,18 @@ static int skge_set_coalesce(struct net_device *dev,
643static void skge_led_on(struct skge_hw *hw, int port) 623static void skge_led_on(struct skge_hw *hw, int port)
644{ 624{
645 if (hw->chip_id == CHIP_ID_GENESIS) { 625 if (hw->chip_id == CHIP_ID_GENESIS) {
646 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON); 626 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
647 skge_write8(hw, B0_LED, LED_STAT_ON); 627 skge_write8(hw, B0_LED, LED_STAT_ON);
648 628
649 skge_write8(hw, SKGEMAC_REG(port, RX_LED_TST), LED_T_ON); 629 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
650 skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 100); 630 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
651 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START); 631 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
652 632
653 switch (hw->phy_type) { 633 /* For Broadcom Phy only */
654 case SK_PHY_BCOM: 634 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
655 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
656 PHY_B_PEC_LED_ON);
657 break;
658 case SK_PHY_LONE:
659 skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
660 0x0800);
661 break;
662 default:
663 skge_write8(hw, SKGEMAC_REG(port, TX_LED_TST), LED_T_ON);
664 skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 100);
665 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START);
666 }
667 } else { 635 } else {
668 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 636 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
669 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, 637 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
670 PHY_M_LED_MO_DUP(MO_LED_ON) | 638 PHY_M_LED_MO_DUP(MO_LED_ON) |
671 PHY_M_LED_MO_10(MO_LED_ON) | 639 PHY_M_LED_MO_10(MO_LED_ON) |
672 PHY_M_LED_MO_100(MO_LED_ON) | 640 PHY_M_LED_MO_100(MO_LED_ON) |
@@ -678,28 +646,17 @@ static void skge_led_on(struct skge_hw *hw, int port)
678static void skge_led_off(struct skge_hw *hw, int port) 646static void skge_led_off(struct skge_hw *hw, int port)
679{ 647{
680 if (hw->chip_id == CHIP_ID_GENESIS) { 648 if (hw->chip_id == CHIP_ID_GENESIS) {
681 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_OFF); 649 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
682 skge_write8(hw, B0_LED, LED_STAT_OFF); 650 skge_write8(hw, B0_LED, LED_STAT_OFF);
683 651
684 skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 0); 652 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
685 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_T_OFF); 653 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
686 654
687 switch (hw->phy_type) { 655 /* Broadcom only */
688 case SK_PHY_BCOM: 656 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
689 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
690 PHY_B_PEC_LED_OFF);
691 break;
692 case SK_PHY_LONE:
693 skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
694 PHY_L_LC_LEDT);
695 break;
696 default:
697 skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 0);
698 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_T_OFF);
699 }
700 } else { 657 } else {
701 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
702 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, 659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
703 PHY_M_LED_MO_DUP(MO_LED_OFF) | 660 PHY_M_LED_MO_DUP(MO_LED_OFF) |
704 PHY_M_LED_MO_10(MO_LED_OFF) | 661 PHY_M_LED_MO_10(MO_LED_OFF) |
705 PHY_M_LED_MO_100(MO_LED_OFF) | 662 PHY_M_LED_MO_100(MO_LED_OFF) |
@@ -730,7 +687,7 @@ static int skge_phys_id(struct net_device *dev, u32 data)
730{ 687{
731 struct skge_port *skge = netdev_priv(dev); 688 struct skge_port *skge = netdev_priv(dev);
732 689
733 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) 690 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
734 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); 691 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
735 692
736 /* start blinking */ 693 /* start blinking */
@@ -763,8 +720,6 @@ static struct ethtool_ops skge_ethtool_ops = {
763 .set_pauseparam = skge_set_pauseparam, 720 .set_pauseparam = skge_set_pauseparam,
764 .get_coalesce = skge_get_coalesce, 721 .get_coalesce = skge_get_coalesce,
765 .set_coalesce = skge_set_coalesce, 722 .set_coalesce = skge_set_coalesce,
766 .get_tso = ethtool_op_get_tso,
767 .set_tso = skge_set_tso,
768 .get_sg = ethtool_op_get_sg, 723 .get_sg = ethtool_op_get_sg,
769 .set_sg = skge_set_sg, 724 .set_sg = skge_set_sg,
770 .get_tx_csum = ethtool_op_get_tx_csum, 725 .get_tx_csum = ethtool_op_get_tx_csum,
@@ -793,6 +748,7 @@ static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
793 748
794 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { 749 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
795 e->desc = d; 750 e->desc = d;
751 e->skb = NULL;
796 if (i == ring->count - 1) { 752 if (i == ring->count - 1) {
797 e->next = ring->start; 753 e->next = ring->start;
798 d->next_offset = base; 754 d->next_offset = base;
@@ -806,24 +762,23 @@ static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
806 return 0; 762 return 0;
807} 763}
808 764
809/* Setup buffer for receiving */ 765static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
810static inline int skge_rx_alloc(struct skge_port *skge,
811 struct skge_element *e)
812{ 766{
813 unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */ 767 struct sk_buff *skb = dev_alloc_skb(size);
814 struct skge_rx_desc *rd = e->desc;
815 struct sk_buff *skb;
816 u64 map;
817 768
818 skb = dev_alloc_skb(bufsize + NET_IP_ALIGN); 769 if (likely(skb)) {
819 if (unlikely(!skb)) { 770 skb->dev = dev;
820 printk(KERN_DEBUG PFX "%s: out of memory for receive\n", 771 skb_reserve(skb, NET_IP_ALIGN);
821 skge->netdev->name);
822 return -ENOMEM;
823 } 772 }
773 return skb;
774}
824 775
825 skb->dev = skge->netdev; 776/* Allocate and setup a new buffer for receiving */
826 skb_reserve(skb, NET_IP_ALIGN); 777static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
778 struct sk_buff *skb, unsigned int bufsize)
779{
780 struct skge_rx_desc *rd = e->desc;
781 u64 map;
827 782
828 map = pci_map_single(skge->hw->pdev, skb->data, bufsize, 783 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
829 PCI_DMA_FROMDEVICE); 784 PCI_DMA_FROMDEVICE);
@@ -841,55 +796,69 @@ static inline int skge_rx_alloc(struct skge_port *skge,
841 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; 796 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
842 pci_unmap_addr_set(e, mapaddr, map); 797 pci_unmap_addr_set(e, mapaddr, map);
843 pci_unmap_len_set(e, maplen, bufsize); 798 pci_unmap_len_set(e, maplen, bufsize);
844 return 0;
845} 799}
846 800
847/* Free all unused buffers in receive ring, assumes receiver stopped */ 801/* Resume receiving using existing skb,
802 * Note: DMA address is not changed by chip.
803 * MTU not changed while receiver active.
804 */
805static void skge_rx_reuse(struct skge_element *e, unsigned int size)
806{
807 struct skge_rx_desc *rd = e->desc;
808
809 rd->csum2 = 0;
810 rd->csum2_start = ETH_HLEN;
811
812 wmb();
813
814 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
815}
816
817
818/* Free all buffers in receive ring, assumes receiver stopped */
848static void skge_rx_clean(struct skge_port *skge) 819static void skge_rx_clean(struct skge_port *skge)
849{ 820{
850 struct skge_hw *hw = skge->hw; 821 struct skge_hw *hw = skge->hw;
851 struct skge_ring *ring = &skge->rx_ring; 822 struct skge_ring *ring = &skge->rx_ring;
852 struct skge_element *e; 823 struct skge_element *e;
853 824
854 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 825 e = ring->start;
826 do {
855 struct skge_rx_desc *rd = e->desc; 827 struct skge_rx_desc *rd = e->desc;
856 rd->control = 0; 828 rd->control = 0;
857 829 if (e->skb) {
858 pci_unmap_single(hw->pdev, 830 pci_unmap_single(hw->pdev,
859 pci_unmap_addr(e, mapaddr), 831 pci_unmap_addr(e, mapaddr),
860 pci_unmap_len(e, maplen), 832 pci_unmap_len(e, maplen),
861 PCI_DMA_FROMDEVICE); 833 PCI_DMA_FROMDEVICE);
862 dev_kfree_skb(e->skb); 834 dev_kfree_skb(e->skb);
863 e->skb = NULL; 835 e->skb = NULL;
864 } 836 }
865 ring->to_clean = e; 837 } while ((e = e->next) != ring->start);
866} 838}
867 839
840
868/* Allocate buffers for receive ring 841/* Allocate buffers for receive ring
869 * For receive: to_use is refill location 842 * For receive: to_clean is next received frame.
870 * to_clean is next received frame.
871 *
872 * if (to_use == to_clean)
873 * then ring all frames in ring need buffers
874 * if (to_use->next == to_clean)
875 * then ring all frames in ring have buffers
876 */ 843 */
877static int skge_rx_fill(struct skge_port *skge) 844static int skge_rx_fill(struct skge_port *skge)
878{ 845{
879 struct skge_ring *ring = &skge->rx_ring; 846 struct skge_ring *ring = &skge->rx_ring;
880 struct skge_element *e; 847 struct skge_element *e;
881 int ret = 0; 848 unsigned int bufsize = skge->rx_buf_size;
882 849
883 for (e = ring->to_use; e->next != ring->to_clean; e = e->next) { 850 e = ring->start;
884 if (skge_rx_alloc(skge, e)) { 851 do {
885 ret = 1; 852 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
886 break;
887 }
888 853
889 } 854 if (!skb)
890 ring->to_use = e; 855 return -ENOMEM;
856
857 skge_rx_setup(skge, e, skb, bufsize);
858 } while ( (e = e->next) != ring->start);
891 859
892 return ret; 860 ring->to_clean = ring->start;
861 return 0;
893} 862}
894 863
895static void skge_link_up(struct skge_port *skge) 864static void skge_link_up(struct skge_port *skge)
@@ -919,50 +888,50 @@ static void skge_link_down(struct skge_port *skge)
919 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name); 888 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
920} 889}
921 890
922static u16 skge_xm_phy_read(struct skge_hw *hw, int port, u16 reg) 891static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
923{ 892{
924 int i; 893 int i;
925 u16 v; 894 u16 v;
926 895
927 skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 896 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
928 v = skge_xm_read16(hw, port, XM_PHY_DATA); 897 v = xm_read16(hw, port, XM_PHY_DATA);
929 if (hw->phy_type != SK_PHY_XMAC) {
930 for (i = 0; i < PHY_RETRIES; i++) {
931 udelay(1);
932 if (skge_xm_read16(hw, port, XM_MMU_CMD)
933 & XM_MMU_PHY_RDY)
934 goto ready;
935 }
936 898
937 printk(KERN_WARNING PFX "%s: phy read timed out\n", 899 /* Need to wait for external PHY */
938 hw->dev[port]->name); 900 for (i = 0; i < PHY_RETRIES; i++) {
939 return 0; 901 udelay(1);
940 ready: 902 if (xm_read16(hw, port, XM_MMU_CMD)
941 v = skge_xm_read16(hw, port, XM_PHY_DATA); 903 & XM_MMU_PHY_RDY)
904 goto ready;
942 } 905 }
943 906
907 printk(KERN_WARNING PFX "%s: phy read timed out\n",
908 hw->dev[port]->name);
909 return 0;
910 ready:
911 v = xm_read16(hw, port, XM_PHY_DATA);
912
944 return v; 913 return v;
945} 914}
946 915
947static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 916static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
948{ 917{
949 int i; 918 int i;
950 919
951 skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 920 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
952 for (i = 0; i < PHY_RETRIES; i++) { 921 for (i = 0; i < PHY_RETRIES; i++) {
953 if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 922 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
954 goto ready; 923 goto ready;
955 cpu_relax(); 924 udelay(1);
956 } 925 }
957 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n", 926 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
958 hw->dev[port]->name); 927 hw->dev[port]->name);
959 928
960 929
961 ready: 930 ready:
962 skge_xm_write16(hw, port, XM_PHY_DATA, val); 931 xm_write16(hw, port, XM_PHY_DATA, val);
963 for (i = 0; i < PHY_RETRIES; i++) { 932 for (i = 0; i < PHY_RETRIES; i++) {
964 udelay(1); 933 udelay(1);
965 if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 934 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
966 return; 935 return;
967 } 936 }
968 printk(KERN_WARNING PFX "%s: phy write timed out\n", 937 printk(KERN_WARNING PFX "%s: phy write timed out\n",
@@ -999,34 +968,112 @@ static void genesis_init(struct skge_hw *hw)
999 968
1000static void genesis_reset(struct skge_hw *hw, int port) 969static void genesis_reset(struct skge_hw *hw, int port)
1001{ 970{
1002 int i; 971 const u8 zero[8] = { 0 };
1003 u64 zero = 0;
1004 972
1005 /* reset the statistics module */ 973 /* reset the statistics module */
1006 skge_xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); 974 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1007 skge_xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ 975 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1008 skge_xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ 976 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1009 skge_xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ 977 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1010 skge_xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ 978 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1011 979
1012 /* disable all PHY IRQs */ 980 /* disable Broadcom PHY IRQ */
1013 if (hw->phy_type == SK_PHY_BCOM) 981 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1014 skge_xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1015 982
1016 skge_xm_outhash(hw, port, XM_HSM, (u8 *) &zero); 983 xm_outhash(hw, port, XM_HSM, zero);
1017 for (i = 0; i < 15; i++)
1018 skge_xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
1019 skge_xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
1020} 984}
1021 985
1022 986
1023static void genesis_mac_init(struct skge_hw *hw, int port) 987/* Convert mode to MII values */
988static const u16 phy_pause_map[] = {
989 [FLOW_MODE_NONE] = 0,
990 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
991 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
992 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
993};
994
995
996/* Check status of Broadcom phy link */
997static void bcom_check_link(struct skge_hw *hw, int port)
1024{ 998{
1025 struct skge_port *skge = netdev_priv(hw->dev[port]); 999 struct net_device *dev = hw->dev[port];
1000 struct skge_port *skge = netdev_priv(dev);
1001 u16 status;
1002
1003 /* read twice because of latch */
1004 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1005 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1006
1007 pr_debug("bcom_check_link status=0x%x\n", status);
1008
1009 if ((status & PHY_ST_LSYNC) == 0) {
1010 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1011 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1012 xm_write16(hw, port, XM_MMU_CMD, cmd);
1013 /* dummy read to ensure writing */
1014 (void) xm_read16(hw, port, XM_MMU_CMD);
1015
1016 if (netif_carrier_ok(dev))
1017 skge_link_down(skge);
1018 } else {
1019 if (skge->autoneg == AUTONEG_ENABLE &&
1020 (status & PHY_ST_AN_OVER)) {
1021 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1022 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1023
1024 if (lpa & PHY_B_AN_RF) {
1025 printk(KERN_NOTICE PFX "%s: remote fault\n",
1026 dev->name);
1027 return;
1028 }
1029
1030 /* Check Duplex mismatch */
1031 switch(aux & PHY_B_AS_AN_RES_MSK) {
1032 case PHY_B_RES_1000FD:
1033 skge->duplex = DUPLEX_FULL;
1034 break;
1035 case PHY_B_RES_1000HD:
1036 skge->duplex = DUPLEX_HALF;
1037 break;
1038 default:
1039 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1040 dev->name);
1041 return;
1042 }
1043
1044
1045 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1046 switch (aux & PHY_B_AS_PAUSE_MSK) {
1047 case PHY_B_AS_PAUSE_MSK:
1048 skge->flow_control = FLOW_MODE_SYMMETRIC;
1049 break;
1050 case PHY_B_AS_PRR:
1051 skge->flow_control = FLOW_MODE_REM_SEND;
1052 break;
1053 case PHY_B_AS_PRT:
1054 skge->flow_control = FLOW_MODE_LOC_SEND;
1055 break;
1056 default:
1057 skge->flow_control = FLOW_MODE_NONE;
1058 }
1059
1060 skge->speed = SPEED_1000;
1061 }
1062
1063 if (!netif_carrier_ok(dev))
1064 genesis_link_up(skge);
1065 }
1066}
1067
1068/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1069 * Phy on for 100 or 10Mbit operation
1070 */
1071static void bcom_phy_init(struct skge_port *skge, int jumbo)
1072{
1073 struct skge_hw *hw = skge->hw;
1074 int port = skge->port;
1026 int i; 1075 int i;
1027 u32 r; 1076 u16 id1, r, ext, ctl;
1028 u16 id1;
1029 u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
1030 1077
1031 /* magic workaround patterns for Broadcom */ 1078 /* magic workaround patterns for Broadcom */
1032 static const struct { 1079 static const struct {
@@ -1042,16 +1089,120 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1042 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, 1089 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1043 }; 1090 };
1044 1091
1092 pr_debug("bcom_phy_init\n");
1093
1094 /* read Id from external PHY (all have the same address) */
1095 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1096
1097 /* Optimize MDIO transfer by suppressing preamble. */
1098 r = xm_read16(hw, port, XM_MMU_CMD);
1099 r |= XM_MMU_NO_PRE;
1100 xm_write16(hw, port, XM_MMU_CMD,r);
1101
1102 switch(id1) {
1103 case PHY_BCOM_ID1_C0:
1104 /*
1105 * Workaround BCOM Errata for the C0 type.
1106 * Write magic patterns to reserved registers.
1107 */
1108 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1109 xm_phy_write(hw, port,
1110 C0hack[i].reg, C0hack[i].val);
1111
1112 break;
1113 case PHY_BCOM_ID1_A1:
1114 /*
1115 * Workaround BCOM Errata for the A1 type.
1116 * Write magic patterns to reserved registers.
1117 */
1118 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1119 xm_phy_write(hw, port,
1120 A1hack[i].reg, A1hack[i].val);
1121 break;
1122 }
1123
1124 /*
1125 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1126 * Disable Power Management after reset.
1127 */
1128 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1129 r |= PHY_B_AC_DIS_PM;
1130 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1131
1132 /* Dummy read */
1133 xm_read16(hw, port, XM_ISRC);
1134
1135 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1136 ctl = PHY_CT_SP1000; /* always 1000mbit */
1137
1138 if (skge->autoneg == AUTONEG_ENABLE) {
1139 /*
1140 * Workaround BCOM Errata #1 for the C5 type.
1141 * 1000Base-T Link Acquisition Failure in Slave Mode
1142 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1143 */
1144 u16 adv = PHY_B_1000C_RD;
1145 if (skge->advertising & ADVERTISED_1000baseT_Half)
1146 adv |= PHY_B_1000C_AHD;
1147 if (skge->advertising & ADVERTISED_1000baseT_Full)
1148 adv |= PHY_B_1000C_AFD;
1149 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1150
1151 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1152 } else {
1153 if (skge->duplex == DUPLEX_FULL)
1154 ctl |= PHY_CT_DUP_MD;
1155 /* Force to slave */
1156 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1157 }
1158
1159 /* Set autonegotiation pause parameters */
1160 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1161 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1162
1163 /* Handle Jumbo frames */
1164 if (jumbo) {
1165 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1166 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1167
1168 ext |= PHY_B_PEC_HIGH_LA;
1169
1170 }
1171
1172 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1173 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1174
1175 /* Use link status change interrrupt */
1176 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1177
1178 bcom_check_link(hw, port);
1179}
1180
1181static void genesis_mac_init(struct skge_hw *hw, int port)
1182{
1183 struct net_device *dev = hw->dev[port];
1184 struct skge_port *skge = netdev_priv(dev);
1185 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1186 int i;
1187 u32 r;
1188 const u8 zero[6] = { 0 };
1189
1190 /* Clear MIB counters */
1191 xm_write16(hw, port, XM_STAT_CMD,
1192 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1193 /* Clear two times according to Errata #3 */
1194 xm_write16(hw, port, XM_STAT_CMD,
1195 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1045 1196
1046 /* initialize Rx, Tx and Link LED */ 1197 /* initialize Rx, Tx and Link LED */
1047 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON); 1198 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1048 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); 1199 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
1049 1200
1050 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START); 1201 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1051 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START); 1202 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
1052 1203
1053 /* Unreset the XMAC. */ 1204 /* Unreset the XMAC. */
1054 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1205 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1055 1206
1056 /* 1207 /*
1057 * Perform additional initialization for external PHYs, 1208 * Perform additional initialization for external PHYs,
@@ -1059,67 +1210,56 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1059 * GMII mode. 1210 * GMII mode.
1060 */ 1211 */
1061 spin_lock_bh(&hw->phy_lock); 1212 spin_lock_bh(&hw->phy_lock);
1062 if (hw->phy_type != SK_PHY_XMAC) { 1213 /* Take external Phy out of reset */
1063 /* Take PHY out of reset. */ 1214 r = skge_read32(hw, B2_GP_IO);
1064 r = skge_read32(hw, B2_GP_IO); 1215 if (port == 0)
1065 if (port == 0) 1216 r |= GP_DIR_0|GP_IO_0;
1066 r |= GP_DIR_0|GP_IO_0; 1217 else
1067 else 1218 r |= GP_DIR_2|GP_IO_2;
1068 r |= GP_DIR_2|GP_IO_2;
1069
1070 skge_write32(hw, B2_GP_IO, r);
1071 skge_read32(hw, B2_GP_IO);
1072
1073 /* Enable GMII mode on the XMAC. */
1074 skge_xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1075
1076 id1 = skge_xm_phy_read(hw, port, PHY_XMAC_ID1);
1077
1078 /* Optimize MDIO transfer by suppressing preamble. */
1079 skge_xm_write16(hw, port, XM_MMU_CMD,
1080 skge_xm_read16(hw, port, XM_MMU_CMD)
1081 | XM_MMU_NO_PRE);
1082
1083 if (id1 == PHY_BCOM_ID1_C0) {
1084 /*
1085 * Workaround BCOM Errata for the C0 type.
1086 * Write magic patterns to reserved registers.
1087 */
1088 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1089 skge_xm_phy_write(hw, port,
1090 C0hack[i].reg, C0hack[i].val);
1091
1092 } else if (id1 == PHY_BCOM_ID1_A1) {
1093 /*
1094 * Workaround BCOM Errata for the A1 type.
1095 * Write magic patterns to reserved registers.
1096 */
1097 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1098 skge_xm_phy_write(hw, port,
1099 A1hack[i].reg, A1hack[i].val);
1100 }
1101 1219
1102 /* 1220 skge_write32(hw, B2_GP_IO, r);
1103 * Workaround BCOM Errata (#10523) for all BCom PHYs. 1221 skge_read32(hw, B2_GP_IO);
1104 * Disable Power Management after reset. 1222 spin_unlock_bh(&hw->phy_lock);
1105 */
1106 r = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1107 skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
1108 }
1109 1223
1110 /* Dummy read */ 1224 /* Enable GMII interfac */
1111 skge_xm_read16(hw, port, XM_ISRC); 1225 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1226
1227 bcom_phy_init(skge, jumbo);
1228
1229 /* Set Station Address */
1230 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1231
1232 /* We don't use match addresses so clear */
1233 for (i = 1; i < 16; i++)
1234 xm_outaddr(hw, port, XM_EXM(i), zero);
1112 1235
1113 r = skge_xm_read32(hw, port, XM_MODE); 1236 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1114 skge_xm_write32(hw, port, XM_MODE, r|XM_MD_CSA); 1237 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1115 1238
1116 /* We don't need the FCS appended to the packet. */ 1239 /* We don't need the FCS appended to the packet. */
1117 r = skge_xm_read16(hw, port, XM_RX_CMD); 1240 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1118 skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS); 1241 if (jumbo)
1242 r |= XM_RX_BIG_PK_OK;
1243
1244 if (skge->duplex == DUPLEX_HALF) {
1245 /*
1246 * If in manual half duplex mode the other side might be in
1247 * full duplex mode, so ignore if a carrier extension is not seen
1248 * on frames received
1249 */
1250 r |= XM_RX_DIS_CEXT;
1251 }
1252 xm_write16(hw, port, XM_RX_CMD, r);
1253
1119 1254
1120 /* We want short frames padded to 60 bytes. */ 1255 /* We want short frames padded to 60 bytes. */
1121 r = skge_xm_read16(hw, port, XM_TX_CMD); 1256 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1122 skge_xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD); 1257
1258 /*
1259 * Bump up the transmit threshold. This helps hold off transmit
1260 * underruns when we're blasting traffic from both ports at once.
1261 */
1262 xm_write16(hw, port, XM_TX_THR, 512);
1123 1263
1124 /* 1264 /*
1125 * Enable the reception of all error frames. This is is 1265 * Enable the reception of all error frames. This is is
@@ -1135,19 +1275,22 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1135 * case the XMAC will start transfering frames out of the 1275 * case the XMAC will start transfering frames out of the
1136 * RX FIFO as soon as the FIFO threshold is reached. 1276 * RX FIFO as soon as the FIFO threshold is reached.
1137 */ 1277 */
1138 r = skge_xm_read32(hw, port, XM_MODE); 1278 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1139 skge_xm_write32(hw, port, XM_MODE,
1140 XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
1141 XM_MD_RX_ERR|XM_MD_RX_IRLE);
1142 1279
1143 skge_xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
1144 skge_xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
1145 1280
1146 /* 1281 /*
1147 * Bump up the transmit threshold. This helps hold off transmit 1282 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1148 * underruns when we're blasting traffic from both ports at once. 1283 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1284 * and 'Octets Rx OK Hi Cnt Ov'.
1149 */ 1285 */
1150 skge_xm_write16(hw, port, XM_TX_THR, 512); 1286 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1287
1288 /*
1289 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1290 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1291 * and 'Octets Tx OK Hi Cnt Ov'.
1292 */
1293 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1151 1294
1152 /* Configure MAC arbiter */ 1295 /* Configure MAC arbiter */
1153 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1296 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
@@ -1164,137 +1307,30 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1164 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1307 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1165 1308
1166 /* Configure Rx MAC FIFO */ 1309 /* Configure Rx MAC FIFO */
1167 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); 1310 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1168 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); 1311 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1169 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 1312 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1170 1313
1171 /* Configure Tx MAC FIFO */ 1314 /* Configure Tx MAC FIFO */
1172 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); 1315 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1173 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 1316 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1174 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 1317 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1175 1318
1176 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 1319 if (jumbo) {
1177 /* Enable frame flushing if jumbo frames used */ 1320 /* Enable frame flushing if jumbo frames used */
1178 skge_write16(hw, SKGEMAC_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH); 1321 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1179 } else { 1322 } else {
1180 /* enable timeout timers if normal frames */ 1323 /* enable timeout timers if normal frames */
1181 skge_write16(hw, B3_PA_CTRL, 1324 skge_write16(hw, B3_PA_CTRL,
1182 port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); 1325 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1183 } 1326 }
1184
1185
1186 r = skge_xm_read16(hw, port, XM_RX_CMD);
1187 if (hw->dev[port]->mtu > ETH_DATA_LEN)
1188 skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
1189 else
1190 skge_xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
1191
1192 switch (hw->phy_type) {
1193 case SK_PHY_XMAC:
1194 if (skge->autoneg == AUTONEG_ENABLE) {
1195 ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
1196
1197 switch (skge->flow_control) {
1198 case FLOW_MODE_NONE:
1199 ctrl1 |= PHY_X_P_NO_PAUSE;
1200 break;
1201 case FLOW_MODE_LOC_SEND:
1202 ctrl1 |= PHY_X_P_ASYM_MD;
1203 break;
1204 case FLOW_MODE_SYMMETRIC:
1205 ctrl1 |= PHY_X_P_SYM_MD;
1206 break;
1207 case FLOW_MODE_REM_SEND:
1208 ctrl1 |= PHY_X_P_BOTH_MD;
1209 break;
1210 }
1211
1212 skge_xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
1213 ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
1214 } else {
1215 ctrl2 = 0;
1216 if (skge->duplex == DUPLEX_FULL)
1217 ctrl2 |= PHY_CT_DUP_MD;
1218 }
1219
1220 skge_xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
1221 break;
1222
1223 case SK_PHY_BCOM:
1224 ctrl1 = PHY_CT_SP1000;
1225 ctrl2 = 0;
1226 ctrl3 = PHY_SEL_TYPE;
1227 ctrl4 = PHY_B_PEC_EN_LTR;
1228 ctrl5 = PHY_B_AC_TX_TST;
1229
1230 if (skge->autoneg == AUTONEG_ENABLE) {
1231 /*
1232 * Workaround BCOM Errata #1 for the C5 type.
1233 * 1000Base-T Link Acquisition Failure in Slave Mode
1234 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1235 */
1236 ctrl2 |= PHY_B_1000C_RD;
1237 if (skge->advertising & ADVERTISED_1000baseT_Half)
1238 ctrl2 |= PHY_B_1000C_AHD;
1239 if (skge->advertising & ADVERTISED_1000baseT_Full)
1240 ctrl2 |= PHY_B_1000C_AFD;
1241
1242 /* Set Flow-control capabilities */
1243 switch (skge->flow_control) {
1244 case FLOW_MODE_NONE:
1245 ctrl3 |= PHY_B_P_NO_PAUSE;
1246 break;
1247 case FLOW_MODE_LOC_SEND:
1248 ctrl3 |= PHY_B_P_ASYM_MD;
1249 break;
1250 case FLOW_MODE_SYMMETRIC:
1251 ctrl3 |= PHY_B_P_SYM_MD;
1252 break;
1253 case FLOW_MODE_REM_SEND:
1254 ctrl3 |= PHY_B_P_BOTH_MD;
1255 break;
1256 }
1257
1258 /* Restart Auto-negotiation */
1259 ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
1260 } else {
1261 if (skge->duplex == DUPLEX_FULL)
1262 ctrl1 |= PHY_CT_DUP_MD;
1263
1264 ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
1265 }
1266
1267 skge_xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
1268 skge_xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
1269
1270 if (skge->netdev->mtu > ETH_DATA_LEN) {
1271 ctrl4 |= PHY_B_PEC_HIGH_LA;
1272 ctrl5 |= PHY_B_AC_LONG_PACK;
1273
1274 skge_xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
1275 }
1276
1277 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
1278 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
1279 break;
1280 }
1281 spin_unlock_bh(&hw->phy_lock);
1282
1283 /* Clear MIB counters */
1284 skge_xm_write16(hw, port, XM_STAT_CMD,
1285 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1286 /* Clear two times according to Errata #3 */
1287 skge_xm_write16(hw, port, XM_STAT_CMD,
1288 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1289
1290 /* Start polling for link status */
1291 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1292} 1327}
1293 1328
1294static void genesis_stop(struct skge_port *skge) 1329static void genesis_stop(struct skge_port *skge)
1295{ 1330{
1296 struct skge_hw *hw = skge->hw; 1331 struct skge_hw *hw = skge->hw;
1297 int port = skge->port; 1332 int port = skge->port;
1333 u32 reg;
1298 1334
1299 /* Clear Tx packet arbiter timeout IRQ */ 1335 /* Clear Tx packet arbiter timeout IRQ */
1300 skge_write16(hw, B3_PA_CTRL, 1336 skge_write16(hw, B3_PA_CTRL,
@@ -1304,33 +1340,30 @@ static void genesis_stop(struct skge_port *skge)
1304 * If the transfer stucks at the MAC the STOP command will not 1340 * If the transfer stucks at the MAC the STOP command will not
1305 * terminate if we don't flush the XMAC's transmit FIFO ! 1341 * terminate if we don't flush the XMAC's transmit FIFO !
1306 */ 1342 */
1307 skge_xm_write32(hw, port, XM_MODE, 1343 xm_write32(hw, port, XM_MODE,
1308 skge_xm_read32(hw, port, XM_MODE)|XM_MD_FTF); 1344 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1309 1345
1310 1346
1311 /* Reset the MAC */ 1347 /* Reset the MAC */
1312 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); 1348 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1313 1349
1314 /* For external PHYs there must be special handling */ 1350 /* For external PHYs there must be special handling */
1315 if (hw->phy_type != SK_PHY_XMAC) { 1351 reg = skge_read32(hw, B2_GP_IO);
1316 u32 reg = skge_read32(hw, B2_GP_IO); 1352 if (port == 0) {
1317 1353 reg |= GP_DIR_0;
1318 if (port == 0) { 1354 reg &= ~GP_IO_0;
1319 reg |= GP_DIR_0; 1355 } else {
1320 reg &= ~GP_IO_0; 1356 reg |= GP_DIR_2;
1321 } else { 1357 reg &= ~GP_IO_2;
1322 reg |= GP_DIR_2;
1323 reg &= ~GP_IO_2;
1324 }
1325 skge_write32(hw, B2_GP_IO, reg);
1326 skge_read32(hw, B2_GP_IO);
1327 } 1358 }
1359 skge_write32(hw, B2_GP_IO, reg);
1360 skge_read32(hw, B2_GP_IO);
1328 1361
1329 skge_xm_write16(hw, port, XM_MMU_CMD, 1362 xm_write16(hw, port, XM_MMU_CMD,
1330 skge_xm_read16(hw, port, XM_MMU_CMD) 1363 xm_read16(hw, port, XM_MMU_CMD)
1331 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 1364 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1332 1365
1333 skge_xm_read16(hw, port, XM_MMU_CMD); 1366 xm_read16(hw, port, XM_MMU_CMD);
1334} 1367}
1335 1368
1336 1369
@@ -1341,11 +1374,11 @@ static void genesis_get_stats(struct skge_port *skge, u64 *data)
1341 int i; 1374 int i;
1342 unsigned long timeout = jiffies + HZ; 1375 unsigned long timeout = jiffies + HZ;
1343 1376
1344 skge_xm_write16(hw, port, 1377 xm_write16(hw, port,
1345 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); 1378 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1346 1379
1347 /* wait for update to complete */ 1380 /* wait for update to complete */
1348 while (skge_xm_read16(hw, port, XM_STAT_CMD) 1381 while (xm_read16(hw, port, XM_STAT_CMD)
1349 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { 1382 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1350 if (time_after(jiffies, timeout)) 1383 if (time_after(jiffies, timeout))
1351 break; 1384 break;
@@ -1353,68 +1386,60 @@ static void genesis_get_stats(struct skge_port *skge, u64 *data)
1353 } 1386 }
1354 1387
1355 /* special case for 64 bit octet counter */ 1388 /* special case for 64 bit octet counter */
1356 data[0] = (u64) skge_xm_read32(hw, port, XM_TXO_OK_HI) << 32 1389 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1357 | skge_xm_read32(hw, port, XM_TXO_OK_LO); 1390 | xm_read32(hw, port, XM_TXO_OK_LO);
1358 data[1] = (u64) skge_xm_read32(hw, port, XM_RXO_OK_HI) << 32 1391 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1359 | skge_xm_read32(hw, port, XM_RXO_OK_LO); 1392 | xm_read32(hw, port, XM_RXO_OK_LO);
1360 1393
1361 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 1394 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1362 data[i] = skge_xm_read32(hw, port, skge_stats[i].xmac_offset); 1395 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1363} 1396}
1364 1397
1365static void genesis_mac_intr(struct skge_hw *hw, int port) 1398static void genesis_mac_intr(struct skge_hw *hw, int port)
1366{ 1399{
1367 struct skge_port *skge = netdev_priv(hw->dev[port]); 1400 struct skge_port *skge = netdev_priv(hw->dev[port]);
1368 u16 status = skge_xm_read16(hw, port, XM_ISRC); 1401 u16 status = xm_read16(hw, port, XM_ISRC);
1369 1402
1370 pr_debug("genesis_intr status %x\n", status); 1403 if (netif_msg_intr(skge))
1371 if (hw->phy_type == SK_PHY_XMAC) { 1404 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1372 /* LInk down, start polling for state change */ 1405 skge->netdev->name, status);
1373 if (status & XM_IS_INP_ASS) {
1374 skge_xm_write16(hw, port, XM_IMSK,
1375 skge_xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
1376 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1377 }
1378 else if (status & XM_IS_AND)
1379 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1380 }
1381 1406
1382 if (status & XM_IS_TXF_UR) { 1407 if (status & XM_IS_TXF_UR) {
1383 skge_xm_write32(hw, port, XM_MODE, XM_MD_FTF); 1408 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1384 ++skge->net_stats.tx_fifo_errors; 1409 ++skge->net_stats.tx_fifo_errors;
1385 } 1410 }
1386 if (status & XM_IS_RXF_OV) { 1411 if (status & XM_IS_RXF_OV) {
1387 skge_xm_write32(hw, port, XM_MODE, XM_MD_FRF); 1412 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1388 ++skge->net_stats.rx_fifo_errors; 1413 ++skge->net_stats.rx_fifo_errors;
1389 } 1414 }
1390} 1415}
1391 1416
1392static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1417static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1393{ 1418{
1394 int i; 1419 int i;
1395 1420
1396 skge_gma_write16(hw, port, GM_SMI_DATA, val); 1421 gma_write16(hw, port, GM_SMI_DATA, val);
1397 skge_gma_write16(hw, port, GM_SMI_CTRL, 1422 gma_write16(hw, port, GM_SMI_CTRL,
1398 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); 1423 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1399 for (i = 0; i < PHY_RETRIES; i++) { 1424 for (i = 0; i < PHY_RETRIES; i++) {
1400 udelay(1); 1425 udelay(1);
1401 1426
1402 if (!(skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 1427 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1403 break; 1428 break;
1404 } 1429 }
1405} 1430}
1406 1431
1407static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg) 1432static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1408{ 1433{
1409 int i; 1434 int i;
1410 1435
1411 skge_gma_write16(hw, port, GM_SMI_CTRL, 1436 gma_write16(hw, port, GM_SMI_CTRL,
1412 GM_SMI_CT_PHY_AD(hw->phy_addr) 1437 GM_SMI_CT_PHY_AD(hw->phy_addr)
1413 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 1438 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1414 1439
1415 for (i = 0; i < PHY_RETRIES; i++) { 1440 for (i = 0; i < PHY_RETRIES; i++) {
1416 udelay(1); 1441 udelay(1);
1417 if (skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) 1442 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1418 goto ready; 1443 goto ready;
1419 } 1444 }
1420 1445
@@ -1422,24 +1447,7 @@ static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1422 hw->dev[port]->name); 1447 hw->dev[port]->name);
1423 return 0; 1448 return 0;
1424 ready: 1449 ready:
1425 return skge_gma_read16(hw, port, GM_SMI_DATA); 1450 return gma_read16(hw, port, GM_SMI_DATA);
1426}
1427
1428static void genesis_link_down(struct skge_port *skge)
1429{
1430 struct skge_hw *hw = skge->hw;
1431 int port = skge->port;
1432
1433 pr_debug("genesis_link_down\n");
1434
1435 skge_xm_write16(hw, port, XM_MMU_CMD,
1436 skge_xm_read16(hw, port, XM_MMU_CMD)
1437 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1438
1439 /* dummy read to ensure writing */
1440 (void) skge_xm_read16(hw, port, XM_MMU_CMD);
1441
1442 skge_link_down(skge);
1443} 1451}
1444 1452
1445static void genesis_link_up(struct skge_port *skge) 1453static void genesis_link_up(struct skge_port *skge)
@@ -1450,7 +1458,7 @@ static void genesis_link_up(struct skge_port *skge)
1450 u32 mode, msk; 1458 u32 mode, msk;
1451 1459
1452 pr_debug("genesis_link_up\n"); 1460 pr_debug("genesis_link_up\n");
1453 cmd = skge_xm_read16(hw, port, XM_MMU_CMD); 1461 cmd = xm_read16(hw, port, XM_MMU_CMD);
1454 1462
1455 /* 1463 /*
1456 * enabling pause frame reception is required for 1000BT 1464 * enabling pause frame reception is required for 1000BT
@@ -1458,14 +1466,15 @@ static void genesis_link_up(struct skge_port *skge)
1458 */ 1466 */
1459 if (skge->flow_control == FLOW_MODE_NONE || 1467 if (skge->flow_control == FLOW_MODE_NONE ||
1460 skge->flow_control == FLOW_MODE_LOC_SEND) 1468 skge->flow_control == FLOW_MODE_LOC_SEND)
1469 /* Disable Pause Frame Reception */
1461 cmd |= XM_MMU_IGN_PF; 1470 cmd |= XM_MMU_IGN_PF;
1462 else 1471 else
1463 /* Enable Pause Frame Reception */ 1472 /* Enable Pause Frame Reception */
1464 cmd &= ~XM_MMU_IGN_PF; 1473 cmd &= ~XM_MMU_IGN_PF;
1465 1474
1466 skge_xm_write16(hw, port, XM_MMU_CMD, cmd); 1475 xm_write16(hw, port, XM_MMU_CMD, cmd);
1467 1476
1468 mode = skge_xm_read32(hw, port, XM_MODE); 1477 mode = xm_read32(hw, port, XM_MODE);
1469 if (skge->flow_control == FLOW_MODE_SYMMETRIC || 1478 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1470 skge->flow_control == FLOW_MODE_LOC_SEND) { 1479 skge->flow_control == FLOW_MODE_LOC_SEND) {
1471 /* 1480 /*
@@ -1479,10 +1488,10 @@ static void genesis_link_up(struct skge_port *skge)
1479 /* XM_PAUSE_DA = '010000C28001' (default) */ 1488 /* XM_PAUSE_DA = '010000C28001' (default) */
1480 /* XM_MAC_PTIME = 0xffff (maximum) */ 1489 /* XM_MAC_PTIME = 0xffff (maximum) */
1481 /* remember this value is defined in big endian (!) */ 1490 /* remember this value is defined in big endian (!) */
1482 skge_xm_write16(hw, port, XM_MAC_PTIME, 0xffff); 1491 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1483 1492
1484 mode |= XM_PAUSE_MODE; 1493 mode |= XM_PAUSE_MODE;
1485 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); 1494 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1486 } else { 1495 } else {
1487 /* 1496 /*
1488 * disable pause frame generation is required for 1000BT 1497 * disable pause frame generation is required for 1000BT
@@ -1491,125 +1500,68 @@ static void genesis_link_up(struct skge_port *skge)
1491 /* Disable Pause Mode in Mode Register */ 1500 /* Disable Pause Mode in Mode Register */
1492 mode &= ~XM_PAUSE_MODE; 1501 mode &= ~XM_PAUSE_MODE;
1493 1502
1494 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); 1503 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1495 } 1504 }
1496 1505
1497 skge_xm_write32(hw, port, XM_MODE, mode); 1506 xm_write32(hw, port, XM_MODE, mode);
1498 1507
1499 msk = XM_DEF_MSK; 1508 msk = XM_DEF_MSK;
1500 if (hw->phy_type != SK_PHY_XMAC) 1509 /* disable GP0 interrupt bit for external Phy */
1501 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */ 1510 msk |= XM_IS_INP_ASS;
1502 1511
1503 skge_xm_write16(hw, port, XM_IMSK, msk); 1512 xm_write16(hw, port, XM_IMSK, msk);
1504 skge_xm_read16(hw, port, XM_ISRC); 1513 xm_read16(hw, port, XM_ISRC);
1505 1514
1506 /* get MMU Command Reg. */ 1515 /* get MMU Command Reg. */
1507 cmd = skge_xm_read16(hw, port, XM_MMU_CMD); 1516 cmd = xm_read16(hw, port, XM_MMU_CMD);
1508 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) 1517 if (skge->duplex == DUPLEX_FULL)
1509 cmd |= XM_MMU_GMII_FD; 1518 cmd |= XM_MMU_GMII_FD;
1510 1519
1511 if (hw->phy_type == SK_PHY_BCOM) { 1520 /*
1512 /* 1521 * Workaround BCOM Errata (#10523) for all BCom Phys
1513 * Workaround BCOM Errata (#10523) for all BCom Phys 1522 * Enable Power Management after link up
1514 * Enable Power Management after link up 1523 */
1515 */ 1524 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1516 skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1525 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1517 skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) 1526 & ~PHY_B_AC_DIS_PM);
1518 & ~PHY_B_AC_DIS_PM); 1527 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1519 skge_xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
1520 PHY_B_DEF_MSK);
1521 }
1522 1528
1523 /* enable Rx/Tx */ 1529 /* enable Rx/Tx */
1524 skge_xm_write16(hw, port, XM_MMU_CMD, 1530 xm_write16(hw, port, XM_MMU_CMD,
1525 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1531 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1526 skge_link_up(skge); 1532 skge_link_up(skge);
1527} 1533}
1528 1534
1529 1535
1530static void genesis_bcom_intr(struct skge_port *skge) 1536static inline void bcom_phy_intr(struct skge_port *skge)
1531{ 1537{
1532 struct skge_hw *hw = skge->hw; 1538 struct skge_hw *hw = skge->hw;
1533 int port = skge->port; 1539 int port = skge->port;
1534 u16 stat = skge_xm_phy_read(hw, port, PHY_BCOM_INT_STAT); 1540 u16 isrc;
1541
1542 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1543 if (netif_msg_intr(skge))
1544 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1545 skge->netdev->name, isrc);
1535 1546
1536 pr_debug("genesis_bcom intr stat=%x\n", stat); 1547 if (isrc & PHY_B_IS_PSE)
1548 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1549 hw->dev[port]->name);
1537 1550
1538 /* Workaround BCom Errata: 1551 /* Workaround BCom Errata:
1539 * enable and disable loopback mode if "NO HCD" occurs. 1552 * enable and disable loopback mode if "NO HCD" occurs.
1540 */ 1553 */
1541 if (stat & PHY_B_IS_NO_HDCL) { 1554 if (isrc & PHY_B_IS_NO_HDCL) {
1542 u16 ctrl = skge_xm_phy_read(hw, port, PHY_BCOM_CTRL); 1555 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1543 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, 1556 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1544 ctrl | PHY_CT_LOOP); 1557 ctrl | PHY_CT_LOOP);
1545 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, 1558 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1546 ctrl & ~PHY_CT_LOOP); 1559 ctrl & ~PHY_CT_LOOP);
1547 } 1560 }
1548 1561
1549 stat = skge_xm_phy_read(hw, port, PHY_BCOM_STAT); 1562 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1550 if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) { 1563 bcom_check_link(hw, port);
1551 u16 aux = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1552 if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
1553 genesis_link_down(skge);
1554
1555 else if (stat & PHY_B_IS_LST_CHANGE) {
1556 if (aux & PHY_B_AS_AN_C) {
1557 switch (aux & PHY_B_AS_AN_RES_MSK) {
1558 case PHY_B_RES_1000FD:
1559 skge->duplex = DUPLEX_FULL;
1560 break;
1561 case PHY_B_RES_1000HD:
1562 skge->duplex = DUPLEX_HALF;
1563 break;
1564 }
1565
1566 switch (aux & PHY_B_AS_PAUSE_MSK) {
1567 case PHY_B_AS_PAUSE_MSK:
1568 skge->flow_control = FLOW_MODE_SYMMETRIC;
1569 break;
1570 case PHY_B_AS_PRR:
1571 skge->flow_control = FLOW_MODE_REM_SEND;
1572 break;
1573 case PHY_B_AS_PRT:
1574 skge->flow_control = FLOW_MODE_LOC_SEND;
1575 break;
1576 default:
1577 skge->flow_control = FLOW_MODE_NONE;
1578 }
1579 skge->speed = SPEED_1000;
1580 }
1581 genesis_link_up(skge);
1582 }
1583 else
1584 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1585 }
1586}
1587 1564
1588/* Perodic poll of phy status to check for link transistion */
1589static void skge_link_timer(unsigned long __arg)
1590{
1591 struct skge_port *skge = (struct skge_port *) __arg;
1592 struct skge_hw *hw = skge->hw;
1593 int port = skge->port;
1594
1595 if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
1596 return;
1597
1598 spin_lock_bh(&hw->phy_lock);
1599 if (hw->phy_type == SK_PHY_BCOM)
1600 genesis_bcom_intr(skge);
1601 else {
1602 int i;
1603 for (i = 0; i < 3; i++)
1604 if (skge_xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1605 break;
1606
1607 if (i == 3)
1608 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1609 else
1610 genesis_link_up(skge);
1611 }
1612 spin_unlock_bh(&hw->phy_lock);
1613} 1565}
1614 1566
1615/* Marvell Phy Initailization */ 1567/* Marvell Phy Initailization */
@@ -1621,31 +1573,27 @@ static void yukon_init(struct skge_hw *hw, int port)
1621 1573
1622 pr_debug("yukon_init\n"); 1574 pr_debug("yukon_init\n");
1623 if (skge->autoneg == AUTONEG_ENABLE) { 1575 if (skge->autoneg == AUTONEG_ENABLE) {
1624 u16 ectrl = skge_gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 1576 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1625 1577
1626 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 1578 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1627 PHY_M_EC_MAC_S_MSK); 1579 PHY_M_EC_MAC_S_MSK);
1628 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 1580 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1629 1581
1630 /* on PHY 88E1111 there is a change for downshift control */ 1582 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1631 if (hw->chip_id == CHIP_ID_YUKON_EC)
1632 ectrl |= PHY_M_EC_M_DSC_2(0) | PHY_M_EC_DOWN_S_ENA;
1633 else
1634 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1635 1583
1636 skge_gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 1584 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1637 } 1585 }
1638 1586
1639 ctrl = skge_gm_phy_read(hw, port, PHY_MARV_CTRL); 1587 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1640 if (skge->autoneg == AUTONEG_DISABLE) 1588 if (skge->autoneg == AUTONEG_DISABLE)
1641 ctrl &= ~PHY_CT_ANE; 1589 ctrl &= ~PHY_CT_ANE;
1642 1590
1643 ctrl |= PHY_CT_RESET; 1591 ctrl |= PHY_CT_RESET;
1644 skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 1592 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1645 1593
1646 ctrl = 0; 1594 ctrl = 0;
1647 ct1000 = 0; 1595 ct1000 = 0;
1648 adv = PHY_SEL_TYPE; 1596 adv = PHY_AN_CSMA;
1649 1597
1650 if (skge->autoneg == AUTONEG_ENABLE) { 1598 if (skge->autoneg == AUTONEG_ENABLE) {
1651 if (iscopper(hw)) { 1599 if (iscopper(hw)) {
@@ -1661,41 +1609,12 @@ static void yukon_init(struct skge_hw *hw, int port)
1661 adv |= PHY_M_AN_10_FD; 1609 adv |= PHY_M_AN_10_FD;
1662 if (skge->advertising & ADVERTISED_10baseT_Half) 1610 if (skge->advertising & ADVERTISED_10baseT_Half)
1663 adv |= PHY_M_AN_10_HD; 1611 adv |= PHY_M_AN_10_HD;
1664 1612 } else /* special defines for FIBER (88E1011S only) */
1665 /* Set Flow-control capabilities */
1666 switch (skge->flow_control) {
1667 case FLOW_MODE_NONE:
1668 adv |= PHY_B_P_NO_PAUSE;
1669 break;
1670 case FLOW_MODE_LOC_SEND:
1671 adv |= PHY_B_P_ASYM_MD;
1672 break;
1673 case FLOW_MODE_SYMMETRIC:
1674 adv |= PHY_B_P_SYM_MD;
1675 break;
1676 case FLOW_MODE_REM_SEND:
1677 adv |= PHY_B_P_BOTH_MD;
1678 break;
1679 }
1680 } else { /* special defines for FIBER (88E1011S only) */
1681 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; 1613 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1682 1614
1683 /* Set Flow-control capabilities */ 1615 /* Set Flow-control capabilities */
1684 switch (skge->flow_control) { 1616 adv |= phy_pause_map[skge->flow_control];
1685 case FLOW_MODE_NONE: 1617
1686 adv |= PHY_M_P_NO_PAUSE_X;
1687 break;
1688 case FLOW_MODE_LOC_SEND:
1689 adv |= PHY_M_P_ASYM_MD_X;
1690 break;
1691 case FLOW_MODE_SYMMETRIC:
1692 adv |= PHY_M_P_SYM_MD_X;
1693 break;
1694 case FLOW_MODE_REM_SEND:
1695 adv |= PHY_M_P_BOTH_MD_X;
1696 break;
1697 }
1698 }
1699 /* Restart Auto-negotiation */ 1618 /* Restart Auto-negotiation */
1700 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 1619 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1701 } else { 1620 } else {
@@ -1717,36 +1636,23 @@ static void yukon_init(struct skge_hw *hw, int port)
1717 ctrl |= PHY_CT_RESET; 1636 ctrl |= PHY_CT_RESET;
1718 } 1637 }
1719 1638
1720 if (hw->chip_id != CHIP_ID_YUKON_FE) 1639 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1721 skge_gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1722 1640
1723 skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 1641 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1724 skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 1642 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1725 1643
1726 /* Setup Phy LED's */ 1644 /* Setup Phy LED's */
1727 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 1645 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1728 ledover = 0; 1646 ledover = 0;
1729 1647
1730 if (hw->chip_id == CHIP_ID_YUKON_FE) { 1648 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1731 /* on 88E3082 these bits are at 11..9 (shifted left) */
1732 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
1733
1734 skge_gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR,
1735 ((skge_gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR)
1736
1737 & ~PHY_M_FELP_LED1_MSK)
1738 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL)));
1739 } else {
1740 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
1741 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1742 1649
1743 /* turn off the Rx LED (LED_RX) */ 1650 /* turn off the Rx LED (LED_RX) */
1744 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 1651 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
1745 }
1746 1652
1747 /* disable blink mode (LED_DUPLEX) on collisions */ 1653 /* disable blink mode (LED_DUPLEX) on collisions */
1748 ctrl |= PHY_M_LEDC_DP_CTRL; 1654 ctrl |= PHY_M_LEDC_DP_CTRL;
1749 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 1655 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
1750 1656
1751 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) { 1657 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1752 /* turn on 100 Mbps LED (LED_LINK100) */ 1658 /* turn on 100 Mbps LED (LED_LINK100) */
@@ -1754,25 +1660,25 @@ static void yukon_init(struct skge_hw *hw, int port)
1754 } 1660 }
1755 1661
1756 if (ledover) 1662 if (ledover)
1757 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 1663 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
1758 1664
1759 /* Enable phy interrupt on autonegotiation complete (or link up) */ 1665 /* Enable phy interrupt on autonegotiation complete (or link up) */
1760 if (skge->autoneg == AUTONEG_ENABLE) 1666 if (skge->autoneg == AUTONEG_ENABLE)
1761 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 1667 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
1762 else 1668 else
1763 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 1669 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1764} 1670}
1765 1671
1766static void yukon_reset(struct skge_hw *hw, int port) 1672static void yukon_reset(struct skge_hw *hw, int port)
1767{ 1673{
1768 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ 1674 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1769 skge_gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 1675 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1770 skge_gma_write16(hw, port, GM_MC_ADDR_H2, 0); 1676 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1771 skge_gma_write16(hw, port, GM_MC_ADDR_H3, 0); 1677 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1772 skge_gma_write16(hw, port, GM_MC_ADDR_H4, 0); 1678 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1773 1679
1774 skge_gma_write16(hw, port, GM_RX_CTRL, 1680 gma_write16(hw, port, GM_RX_CTRL,
1775 skge_gma_read16(hw, port, GM_RX_CTRL) 1681 gma_read16(hw, port, GM_RX_CTRL)
1776 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 1682 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1777} 1683}
1778 1684
@@ -1785,17 +1691,17 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1785 1691
1786 /* WA code for COMA mode -- set PHY reset */ 1692 /* WA code for COMA mode -- set PHY reset */
1787 if (hw->chip_id == CHIP_ID_YUKON_LITE && 1693 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1788 chip_rev(hw) == CHIP_REV_YU_LITE_A3) 1694 hw->chip_rev == CHIP_REV_YU_LITE_A3)
1789 skge_write32(hw, B2_GP_IO, 1695 skge_write32(hw, B2_GP_IO,
1790 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9)); 1696 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1791 1697
1792 /* hard reset */ 1698 /* hard reset */
1793 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), GPC_RST_SET); 1699 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1794 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_RST_SET); 1700 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1795 1701
1796 /* WA code for COMA mode -- clear PHY reset */ 1702 /* WA code for COMA mode -- clear PHY reset */
1797 if (hw->chip_id == CHIP_ID_YUKON_LITE && 1703 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1798 chip_rev(hw) == CHIP_REV_YU_LITE_A3) 1704 hw->chip_rev == CHIP_REV_YU_LITE_A3)
1799 skge_write32(hw, B2_GP_IO, 1705 skge_write32(hw, B2_GP_IO,
1800 (skge_read32(hw, B2_GP_IO) | GP_DIR_9) 1706 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1801 & ~GP_IO_9); 1707 & ~GP_IO_9);
@@ -1806,13 +1712,13 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1806 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; 1712 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1807 1713
1808 /* Clear GMC reset */ 1714 /* Clear GMC reset */
1809 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_SET); 1715 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1810 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); 1716 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1811 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); 1717 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1812 if (skge->autoneg == AUTONEG_DISABLE) { 1718 if (skge->autoneg == AUTONEG_DISABLE) {
1813 reg = GM_GPCR_AU_ALL_DIS; 1719 reg = GM_GPCR_AU_ALL_DIS;
1814 skge_gma_write16(hw, port, GM_GP_CTRL, 1720 gma_write16(hw, port, GM_GP_CTRL,
1815 skge_gma_read16(hw, port, GM_GP_CTRL) | reg); 1721 gma_read16(hw, port, GM_GP_CTRL) | reg);
1816 1722
1817 switch (skge->speed) { 1723 switch (skge->speed) {
1818 case SPEED_1000: 1724 case SPEED_1000:
@@ -1828,7 +1734,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1828 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 1734 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1829 switch (skge->flow_control) { 1735 switch (skge->flow_control) {
1830 case FLOW_MODE_NONE: 1736 case FLOW_MODE_NONE:
1831 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 1737 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1832 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 1738 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1833 break; 1739 break;
1834 case FLOW_MODE_LOC_SEND: 1740 case FLOW_MODE_LOC_SEND:
@@ -1836,7 +1742,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1836 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 1742 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1837 } 1743 }
1838 1744
1839 skge_gma_write16(hw, port, GM_GP_CTRL, reg); 1745 gma_write16(hw, port, GM_GP_CTRL, reg);
1840 skge_read16(hw, GMAC_IRQ_SRC); 1746 skge_read16(hw, GMAC_IRQ_SRC);
1841 1747
1842 spin_lock_bh(&hw->phy_lock); 1748 spin_lock_bh(&hw->phy_lock);
@@ -1844,25 +1750,25 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1844 spin_unlock_bh(&hw->phy_lock); 1750 spin_unlock_bh(&hw->phy_lock);
1845 1751
1846 /* MIB clear */ 1752 /* MIB clear */
1847 reg = skge_gma_read16(hw, port, GM_PHY_ADDR); 1753 reg = gma_read16(hw, port, GM_PHY_ADDR);
1848 skge_gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 1754 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1849 1755
1850 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 1756 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1851 skge_gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); 1757 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1852 skge_gma_write16(hw, port, GM_PHY_ADDR, reg); 1758 gma_write16(hw, port, GM_PHY_ADDR, reg);
1853 1759
1854 /* transmit control */ 1760 /* transmit control */
1855 skge_gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 1761 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1856 1762
1857 /* receive control reg: unicast + multicast + no FCS */ 1763 /* receive control reg: unicast + multicast + no FCS */
1858 skge_gma_write16(hw, port, GM_RX_CTRL, 1764 gma_write16(hw, port, GM_RX_CTRL,
1859 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 1765 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1860 1766
1861 /* transmit flow control */ 1767 /* transmit flow control */
1862 skge_gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 1768 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1863 1769
1864 /* transmit parameter */ 1770 /* transmit parameter */
1865 skge_gma_write16(hw, port, GM_TX_PARAM, 1771 gma_write16(hw, port, GM_TX_PARAM,
1866 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 1772 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1867 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 1773 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1868 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); 1774 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
@@ -1872,33 +1778,33 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1872 if (hw->dev[port]->mtu > 1500) 1778 if (hw->dev[port]->mtu > 1500)
1873 reg |= GM_SMOD_JUMBO_ENA; 1779 reg |= GM_SMOD_JUMBO_ENA;
1874 1780
1875 skge_gma_write16(hw, port, GM_SERIAL_MODE, reg); 1781 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1876 1782
1877 /* physical address: used for pause frames */ 1783 /* physical address: used for pause frames */
1878 skge_gm_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 1784 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1879 /* virtual address for data */ 1785 /* virtual address for data */
1880 skge_gm_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 1786 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1881 1787
1882 /* enable interrupt mask for counter overflows */ 1788 /* enable interrupt mask for counter overflows */
1883 skge_gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 1789 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1884 skge_gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 1790 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1885 skge_gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 1791 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1886 1792
1887 /* Initialize Mac Fifo */ 1793 /* Initialize Mac Fifo */
1888 1794
1889 /* Configure Rx MAC FIFO */ 1795 /* Configure Rx MAC FIFO */
1890 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); 1796 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1891 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 1797 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1892 if (hw->chip_id == CHIP_ID_YUKON_LITE && 1798 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1893 chip_rev(hw) == CHIP_REV_YU_LITE_A3) 1799 hw->chip_rev == CHIP_REV_YU_LITE_A3)
1894 reg &= ~GMF_RX_F_FL_ON; 1800 reg &= ~GMF_RX_F_FL_ON;
1895 skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 1801 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1896 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), reg); 1802 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1897 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); 1803 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
1898 1804
1899 /* Configure Tx MAC FIFO */ 1805 /* Configure Tx MAC FIFO */
1900 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1806 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1901 skge_write16(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1807 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1902} 1808}
1903 1809
1904static void yukon_stop(struct skge_port *skge) 1810static void yukon_stop(struct skge_port *skge)
@@ -1907,19 +1813,19 @@ static void yukon_stop(struct skge_port *skge)
1907 int port = skge->port; 1813 int port = skge->port;
1908 1814
1909 if (hw->chip_id == CHIP_ID_YUKON_LITE && 1815 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1910 chip_rev(hw) == CHIP_REV_YU_LITE_A3) { 1816 hw->chip_rev == CHIP_REV_YU_LITE_A3) {
1911 skge_write32(hw, B2_GP_IO, 1817 skge_write32(hw, B2_GP_IO,
1912 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9); 1818 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1913 } 1819 }
1914 1820
1915 skge_gma_write16(hw, port, GM_GP_CTRL, 1821 gma_write16(hw, port, GM_GP_CTRL,
1916 skge_gma_read16(hw, port, GM_GP_CTRL) 1822 gma_read16(hw, port, GM_GP_CTRL)
1917 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA)); 1823 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
1918 skge_gma_read16(hw, port, GM_GP_CTRL); 1824 gma_read16(hw, port, GM_GP_CTRL);
1919 1825
1920 /* set GPHY Control reset */ 1826 /* set GPHY Control reset */
1921 skge_gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET); 1827 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1922 skge_gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET); 1828 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
1923} 1829}
1924 1830
1925static void yukon_get_stats(struct skge_port *skge, u64 *data) 1831static void yukon_get_stats(struct skge_port *skge, u64 *data)
@@ -1928,39 +1834,40 @@ static void yukon_get_stats(struct skge_port *skge, u64 *data)
1928 int port = skge->port; 1834 int port = skge->port;
1929 int i; 1835 int i;
1930 1836
1931 data[0] = (u64) skge_gma_read32(hw, port, GM_TXO_OK_HI) << 32 1837 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1932 | skge_gma_read32(hw, port, GM_TXO_OK_LO); 1838 | gma_read32(hw, port, GM_TXO_OK_LO);
1933 data[1] = (u64) skge_gma_read32(hw, port, GM_RXO_OK_HI) << 32 1839 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1934 | skge_gma_read32(hw, port, GM_RXO_OK_LO); 1840 | gma_read32(hw, port, GM_RXO_OK_LO);
1935 1841
1936 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 1842 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1937 data[i] = skge_gma_read32(hw, port, 1843 data[i] = gma_read32(hw, port,
1938 skge_stats[i].gma_offset); 1844 skge_stats[i].gma_offset);
1939} 1845}
1940 1846
1941static void yukon_mac_intr(struct skge_hw *hw, int port) 1847static void yukon_mac_intr(struct skge_hw *hw, int port)
1942{ 1848{
1943 struct skge_port *skge = netdev_priv(hw->dev[port]); 1849 struct net_device *dev = hw->dev[port];
1944 u8 status = skge_read8(hw, SKGEMAC_REG(port, GMAC_IRQ_SRC)); 1850 struct skge_port *skge = netdev_priv(dev);
1851 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1852
1853 if (netif_msg_intr(skge))
1854 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1855 dev->name, status);
1945 1856
1946 pr_debug("yukon_intr status %x\n", status);
1947 if (status & GM_IS_RX_FF_OR) { 1857 if (status & GM_IS_RX_FF_OR) {
1948 ++skge->net_stats.rx_fifo_errors; 1858 ++skge->net_stats.rx_fifo_errors;
1949 skge_gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO); 1859 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
1950 } 1860 }
1951 if (status & GM_IS_TX_FF_UR) { 1861 if (status & GM_IS_TX_FF_UR) {
1952 ++skge->net_stats.tx_fifo_errors; 1862 ++skge->net_stats.tx_fifo_errors;
1953 skge_gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU); 1863 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
1954 } 1864 }
1955 1865
1956} 1866}
1957 1867
1958static u16 yukon_speed(const struct skge_hw *hw, u16 aux) 1868static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1959{ 1869{
1960 if (hw->chip_id == CHIP_ID_YUKON_FE) 1870 switch (aux & PHY_M_PS_SPEED_MSK) {
1961 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1962
1963 switch(aux & PHY_M_PS_SPEED_MSK) {
1964 case PHY_M_PS_SPEED_1000: 1871 case PHY_M_PS_SPEED_1000:
1965 return SPEED_1000; 1872 return SPEED_1000;
1966 case PHY_M_PS_SPEED_100: 1873 case PHY_M_PS_SPEED_100:
@@ -1981,15 +1888,15 @@ static void yukon_link_up(struct skge_port *skge)
1981 /* Enable Transmit FIFO Underrun */ 1888 /* Enable Transmit FIFO Underrun */
1982 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK); 1889 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1983 1890
1984 reg = skge_gma_read16(hw, port, GM_GP_CTRL); 1891 reg = gma_read16(hw, port, GM_GP_CTRL);
1985 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) 1892 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1986 reg |= GM_GPCR_DUP_FULL; 1893 reg |= GM_GPCR_DUP_FULL;
1987 1894
1988 /* enable Rx/Tx */ 1895 /* enable Rx/Tx */
1989 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 1896 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1990 skge_gma_write16(hw, port, GM_GP_CTRL, reg); 1897 gma_write16(hw, port, GM_GP_CTRL, reg);
1991 1898
1992 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 1899 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1993 skge_link_up(skge); 1900 skge_link_up(skge);
1994} 1901}
1995 1902
@@ -1999,16 +1906,15 @@ static void yukon_link_down(struct skge_port *skge)
1999 int port = skge->port; 1906 int port = skge->port;
2000 1907
2001 pr_debug("yukon_link_down\n"); 1908 pr_debug("yukon_link_down\n");
2002 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 1909 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2003 skge_gm_phy_write(hw, port, GM_GP_CTRL, 1910 gm_phy_write(hw, port, GM_GP_CTRL,
2004 skge_gm_phy_read(hw, port, GM_GP_CTRL) 1911 gm_phy_read(hw, port, GM_GP_CTRL)
2005 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)); 1912 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
2006 1913
2007 if (hw->chip_id != CHIP_ID_YUKON_FE && 1914 if (skge->flow_control == FLOW_MODE_REM_SEND) {
2008 skge->flow_control == FLOW_MODE_REM_SEND) {
2009 /* restore Asymmetric Pause bit */ 1915 /* restore Asymmetric Pause bit */
2010 skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 1916 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2011 skge_gm_phy_read(hw, port, 1917 gm_phy_read(hw, port,
2012 PHY_MARV_AUNE_ADV) 1918 PHY_MARV_AUNE_ADV)
2013 | PHY_M_AN_ASP); 1919 | PHY_M_AN_ASP);
2014 1920
@@ -2027,20 +1933,21 @@ static void yukon_phy_intr(struct skge_port *skge)
2027 const char *reason = NULL; 1933 const char *reason = NULL;
2028 u16 istatus, phystat; 1934 u16 istatus, phystat;
2029 1935
2030 istatus = skge_gm_phy_read(hw, port, PHY_MARV_INT_STAT); 1936 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2031 phystat = skge_gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 1937 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2032 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat); 1938
1939 if (netif_msg_intr(skge))
1940 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1941 skge->netdev->name, istatus, phystat);
2033 1942
2034 if (istatus & PHY_M_IS_AN_COMPL) { 1943 if (istatus & PHY_M_IS_AN_COMPL) {
2035 if (skge_gm_phy_read(hw, port, PHY_MARV_AUNE_LP) 1944 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2036 & PHY_M_AN_RF) { 1945 & PHY_M_AN_RF) {
2037 reason = "remote fault"; 1946 reason = "remote fault";
2038 goto failed; 1947 goto failed;
2039 } 1948 }
2040 1949
2041 if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC) 1950 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2042 && (skge_gm_phy_read(hw, port, PHY_MARV_1000T_STAT)
2043 & PHY_B_1000S_MSF)) {
2044 reason = "master/slave fault"; 1951 reason = "master/slave fault";
2045 goto failed; 1952 goto failed;
2046 } 1953 }
@@ -2054,10 +1961,6 @@ static void yukon_phy_intr(struct skge_port *skge)
2054 ? DUPLEX_FULL : DUPLEX_HALF; 1961 ? DUPLEX_FULL : DUPLEX_HALF;
2055 skge->speed = yukon_speed(hw, phystat); 1962 skge->speed = yukon_speed(hw, phystat);
2056 1963
2057 /* Tx & Rx Pause Enabled bits are at 9..8 */
2058 if (hw->chip_id == CHIP_ID_YUKON_XL)
2059 phystat >>= 6;
2060
2061 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1964 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2062 switch (phystat & PHY_M_PS_PAUSE_MSK) { 1965 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2063 case PHY_M_PS_PAUSE_MSK: 1966 case PHY_M_PS_PAUSE_MSK:
@@ -2075,9 +1978,9 @@ static void yukon_phy_intr(struct skge_port *skge)
2075 1978
2076 if (skge->flow_control == FLOW_MODE_NONE || 1979 if (skge->flow_control == FLOW_MODE_NONE ||
2077 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) 1980 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2078 skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 1981 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2079 else 1982 else
2080 skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 1983 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2081 yukon_link_up(skge); 1984 yukon_link_up(skge);
2082 return; 1985 return;
2083 } 1986 }
@@ -2161,6 +2064,12 @@ static int skge_up(struct net_device *dev)
2161 if (netif_msg_ifup(skge)) 2064 if (netif_msg_ifup(skge))
2162 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); 2065 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2163 2066
2067 if (dev->mtu > RX_BUF_SIZE)
2068 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2069 else
2070 skge->rx_buf_size = RX_BUF_SIZE;
2071
2072
2164 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); 2073 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2165 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); 2074 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2166 skge->mem_size = tx_size + rx_size; 2075 skge->mem_size = tx_size + rx_size;
@@ -2173,7 +2082,8 @@ static int skge_up(struct net_device *dev)
2173 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma))) 2082 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2174 goto free_pci_mem; 2083 goto free_pci_mem;
2175 2084
2176 if (skge_rx_fill(skge)) 2085 err = skge_rx_fill(skge);
2086 if (err)
2177 goto free_rx_ring; 2087 goto free_rx_ring;
2178 2088
2179 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, 2089 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
@@ -2182,6 +2092,10 @@ static int skge_up(struct net_device *dev)
2182 2092
2183 skge->tx_avail = skge->tx_ring.count - 1; 2093 skge->tx_avail = skge->tx_ring.count - 1;
2184 2094
2095 /* Enable IRQ from port */
2096 hw->intr_mask |= portirqmask[port];
2097 skge_write32(hw, B0_IMSK, hw->intr_mask);
2098
2185 /* Initialze MAC */ 2099 /* Initialze MAC */
2186 if (hw->chip_id == CHIP_ID_GENESIS) 2100 if (hw->chip_id == CHIP_ID_GENESIS)
2187 genesis_mac_init(hw, port); 2101 genesis_mac_init(hw, port);
@@ -2189,7 +2103,7 @@ static int skge_up(struct net_device *dev)
2189 yukon_mac_init(hw, port); 2103 yukon_mac_init(hw, port);
2190 2104
2191 /* Configure RAMbuffers */ 2105 /* Configure RAMbuffers */
2192 chunk = hw->ram_size / (isdualport(hw) ? 4 : 2); 2106 chunk = hw->ram_size / ((hw->ports + 1)*2);
2193 ram_addr = hw->ram_offset + 2 * chunk * port; 2107 ram_addr = hw->ram_offset + 2 * chunk * port;
2194 2108
2195 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); 2109 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
@@ -2227,7 +2141,6 @@ static int skge_down(struct net_device *dev)
2227 netif_stop_queue(dev); 2141 netif_stop_queue(dev);
2228 2142
2229 del_timer_sync(&skge->led_blink); 2143 del_timer_sync(&skge->led_blink);
2230 del_timer_sync(&skge->link_check);
2231 2144
2232 /* Stop transmitter */ 2145 /* Stop transmitter */
2233 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); 2146 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
@@ -2240,12 +2153,12 @@ static int skge_down(struct net_device *dev)
2240 yukon_stop(skge); 2153 yukon_stop(skge);
2241 2154
2242 /* Disable Force Sync bit and Enable Alloc bit */ 2155 /* Disable Force Sync bit and Enable Alloc bit */
2243 skge_write8(hw, SKGEMAC_REG(port, TXA_CTRL), 2156 skge_write8(hw, SK_REG(port, TXA_CTRL),
2244 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2157 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2245 2158
2246 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2159 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2247 skge_write32(hw, SKGEMAC_REG(port, TXA_ITI_INI), 0L); 2160 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2248 skge_write32(hw, SKGEMAC_REG(port, TXA_LIM_INI), 0L); 2161 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2249 2162
2250 /* Reset PCI FIFO */ 2163 /* Reset PCI FIFO */
2251 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); 2164 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
@@ -2260,13 +2173,13 @@ static int skge_down(struct net_device *dev)
2260 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); 2173 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2261 2174
2262 if (hw->chip_id == CHIP_ID_GENESIS) { 2175 if (hw->chip_id == CHIP_ID_GENESIS) {
2263 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_SET); 2176 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2264 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_SET); 2177 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2265 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_STOP); 2178 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2266 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_STOP); 2179 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
2267 } else { 2180 } else {
2268 skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2181 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2269 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2182 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2270 } 2183 }
2271 2184
2272 /* turn off led's */ 2185 /* turn off led's */
@@ -2299,10 +2212,10 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2299 2212
2300 local_irq_save(flags); 2213 local_irq_save(flags);
2301 if (!spin_trylock(&skge->tx_lock)) { 2214 if (!spin_trylock(&skge->tx_lock)) {
2302 /* Collision - tell upper layer to requeue */ 2215 /* Collision - tell upper layer to requeue */
2303 local_irq_restore(flags); 2216 local_irq_restore(flags);
2304 return NETDEV_TX_LOCKED; 2217 return NETDEV_TX_LOCKED;
2305 } 2218 }
2306 2219
2307 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) { 2220 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2308 netif_stop_queue(dev); 2221 netif_stop_queue(dev);
@@ -2333,7 +2246,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2333 * does. Looks like hardware is wrong? 2246 * does. Looks like hardware is wrong?
2334 */ 2247 */
2335 if (ip->protocol == IPPROTO_UDP 2248 if (ip->protocol == IPPROTO_UDP
2336 && chip_rev(hw) == 0 && hw->chip_id == CHIP_ID_YUKON) 2249 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2337 control = BMU_TCP_CHECK; 2250 control = BMU_TCP_CHECK;
2338 else 2251 else
2339 control = BMU_UDP_CHECK; 2252 control = BMU_UDP_CHECK;
@@ -2394,6 +2307,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2394 2307
2395static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e) 2308static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2396{ 2309{
2310 /* This ring element can be skb or fragment */
2397 if (e->skb) { 2311 if (e->skb) {
2398 pci_unmap_single(hw->pdev, 2312 pci_unmap_single(hw->pdev,
2399 pci_unmap_addr(e, mapaddr), 2313 pci_unmap_addr(e, mapaddr),
@@ -2438,16 +2352,17 @@ static void skge_tx_timeout(struct net_device *dev)
2438static int skge_change_mtu(struct net_device *dev, int new_mtu) 2352static int skge_change_mtu(struct net_device *dev, int new_mtu)
2439{ 2353{
2440 int err = 0; 2354 int err = 0;
2355 int running = netif_running(dev);
2441 2356
2442 if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 2357 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2443 return -EINVAL; 2358 return -EINVAL;
2444 2359
2445 dev->mtu = new_mtu;
2446 2360
2447 if (netif_running(dev)) { 2361 if (running)
2448 skge_down(dev); 2362 skge_down(dev);
2363 dev->mtu = new_mtu;
2364 if (running)
2449 skge_up(dev); 2365 skge_up(dev);
2450 }
2451 2366
2452 return err; 2367 return err;
2453} 2368}
@@ -2462,7 +2377,9 @@ static void genesis_set_multicast(struct net_device *dev)
2462 u32 mode; 2377 u32 mode;
2463 u8 filter[8]; 2378 u8 filter[8];
2464 2379
2465 mode = skge_xm_read32(hw, port, XM_MODE); 2380 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2381
2382 mode = xm_read32(hw, port, XM_MODE);
2466 mode |= XM_MD_ENA_HASH; 2383 mode |= XM_MD_ENA_HASH;
2467 if (dev->flags & IFF_PROMISC) 2384 if (dev->flags & IFF_PROMISC)
2468 mode |= XM_MD_ENA_PROM; 2385 mode |= XM_MD_ENA_PROM;
@@ -2473,17 +2390,16 @@ static void genesis_set_multicast(struct net_device *dev)
2473 memset(filter, 0xff, sizeof(filter)); 2390 memset(filter, 0xff, sizeof(filter));
2474 else { 2391 else {
2475 memset(filter, 0, sizeof(filter)); 2392 memset(filter, 0, sizeof(filter));
2476 for(i = 0; list && i < count; i++, list = list->next) { 2393 for (i = 0; list && i < count; i++, list = list->next) {
2477 u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN); 2394 u32 crc, bit;
2478 u8 bit = 63 - (crc & 63); 2395 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2479 2396 bit = ~crc & 0x3f;
2480 filter[bit/8] |= 1 << (bit%8); 2397 filter[bit/8] |= 1 << (bit%8);
2481 } 2398 }
2482 } 2399 }
2483 2400
2484 skge_xm_outhash(hw, port, XM_HSM, filter); 2401 xm_write32(hw, port, XM_MODE, mode);
2485 2402 xm_outhash(hw, port, XM_HSM, filter);
2486 skge_xm_write32(hw, port, XM_MODE, mode);
2487} 2403}
2488 2404
2489static void yukon_set_multicast(struct net_device *dev) 2405static void yukon_set_multicast(struct net_device *dev)
@@ -2497,7 +2413,7 @@ static void yukon_set_multicast(struct net_device *dev)
2497 2413
2498 memset(filter, 0, sizeof(filter)); 2414 memset(filter, 0, sizeof(filter));
2499 2415
2500 reg = skge_gma_read16(hw, port, GM_RX_CTRL); 2416 reg = gma_read16(hw, port, GM_RX_CTRL);
2501 reg |= GM_RXCR_UCF_ENA; 2417 reg |= GM_RXCR_UCF_ENA;
2502 2418
2503 if (dev->flags & IFF_PROMISC) /* promiscious */ 2419 if (dev->flags & IFF_PROMISC) /* promiscious */
@@ -2510,23 +2426,23 @@ static void yukon_set_multicast(struct net_device *dev)
2510 int i; 2426 int i;
2511 reg |= GM_RXCR_MCF_ENA; 2427 reg |= GM_RXCR_MCF_ENA;
2512 2428
2513 for(i = 0; list && i < dev->mc_count; i++, list = list->next) { 2429 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2514 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; 2430 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2515 filter[bit/8] |= 1 << (bit%8); 2431 filter[bit/8] |= 1 << (bit%8);
2516 } 2432 }
2517 } 2433 }
2518 2434
2519 2435
2520 skge_gma_write16(hw, port, GM_MC_ADDR_H1, 2436 gma_write16(hw, port, GM_MC_ADDR_H1,
2521 (u16)filter[0] | ((u16)filter[1] << 8)); 2437 (u16)filter[0] | ((u16)filter[1] << 8));
2522 skge_gma_write16(hw, port, GM_MC_ADDR_H2, 2438 gma_write16(hw, port, GM_MC_ADDR_H2,
2523 (u16)filter[2] | ((u16)filter[3] << 8)); 2439 (u16)filter[2] | ((u16)filter[3] << 8));
2524 skge_gma_write16(hw, port, GM_MC_ADDR_H3, 2440 gma_write16(hw, port, GM_MC_ADDR_H3,
2525 (u16)filter[4] | ((u16)filter[5] << 8)); 2441 (u16)filter[4] | ((u16)filter[5] << 8));
2526 skge_gma_write16(hw, port, GM_MC_ADDR_H4, 2442 gma_write16(hw, port, GM_MC_ADDR_H4,
2527 (u16)filter[6] | ((u16)filter[7] << 8)); 2443 (u16)filter[6] | ((u16)filter[7] << 8));
2528 2444
2529 skge_gma_write16(hw, port, GM_RX_CTRL, reg); 2445 gma_write16(hw, port, GM_RX_CTRL, reg);
2530} 2446}
2531 2447
2532static inline int bad_phy_status(const struct skge_hw *hw, u32 status) 2448static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
@@ -2545,28 +2461,76 @@ static void skge_rx_error(struct skge_port *skge, int slot,
2545 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n", 2461 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2546 skge->netdev->name, slot, control, status); 2462 skge->netdev->name, slot, control, status);
2547 2463
2548 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF) 2464 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2549 || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2550 skge->net_stats.rx_length_errors++; 2465 skge->net_stats.rx_length_errors++;
2551 else { 2466 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2552 if (skge->hw->chip_id == CHIP_ID_GENESIS) { 2467 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2553 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) 2468 skge->net_stats.rx_length_errors++;
2554 skge->net_stats.rx_length_errors++; 2469 if (status & XMR_FS_FRA_ERR)
2555 if (status & XMR_FS_FRA_ERR) 2470 skge->net_stats.rx_frame_errors++;
2556 skge->net_stats.rx_frame_errors++; 2471 if (status & XMR_FS_FCS_ERR)
2557 if (status & XMR_FS_FCS_ERR) 2472 skge->net_stats.rx_crc_errors++;
2558 skge->net_stats.rx_crc_errors++; 2473 } else {
2559 } else { 2474 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2560 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) 2475 skge->net_stats.rx_length_errors++;
2561 skge->net_stats.rx_length_errors++; 2476 if (status & GMR_FS_FRAGMENT)
2562 if (status & GMR_FS_FRAGMENT) 2477 skge->net_stats.rx_frame_errors++;
2563 skge->net_stats.rx_frame_errors++; 2478 if (status & GMR_FS_CRC_ERR)
2564 if (status & GMR_FS_CRC_ERR) 2479 skge->net_stats.rx_crc_errors++;
2565 skge->net_stats.rx_crc_errors++; 2480 }
2481}
2482
2483/* Get receive buffer from descriptor.
2484 * Handles copy of small buffers and reallocation failures
2485 */
2486static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2487 struct skge_element *e,
2488 unsigned int len)
2489{
2490 struct sk_buff *nskb, *skb;
2491
2492 if (len < RX_COPY_THRESHOLD) {
2493 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2494 if (unlikely(!nskb))
2495 return NULL;
2496
2497 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2498 pci_unmap_addr(e, mapaddr),
2499 len, PCI_DMA_FROMDEVICE);
2500 memcpy(nskb->data, e->skb->data, len);
2501 pci_dma_sync_single_for_device(skge->hw->pdev,
2502 pci_unmap_addr(e, mapaddr),
2503 len, PCI_DMA_FROMDEVICE);
2504
2505 if (skge->rx_csum) {
2506 struct skge_rx_desc *rd = e->desc;
2507 nskb->csum = le16_to_cpu(rd->csum2);
2508 nskb->ip_summed = CHECKSUM_HW;
2566 } 2509 }
2510 skge_rx_reuse(e, skge->rx_buf_size);
2511 return nskb;
2512 } else {
2513 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2514 if (unlikely(!nskb))
2515 return NULL;
2516
2517 pci_unmap_single(skge->hw->pdev,
2518 pci_unmap_addr(e, mapaddr),
2519 pci_unmap_len(e, maplen),
2520 PCI_DMA_FROMDEVICE);
2521 skb = e->skb;
2522 if (skge->rx_csum) {
2523 struct skge_rx_desc *rd = e->desc;
2524 skb->csum = le16_to_cpu(rd->csum2);
2525 skb->ip_summed = CHECKSUM_HW;
2526 }
2527
2528 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2529 return skb;
2567 } 2530 }
2568} 2531}
2569 2532
2533
2570static int skge_poll(struct net_device *dev, int *budget) 2534static int skge_poll(struct net_device *dev, int *budget)
2571{ 2535{
2572 struct skge_port *skge = netdev_priv(dev); 2536 struct skge_port *skge = netdev_priv(dev);
@@ -2575,13 +2539,12 @@ static int skge_poll(struct net_device *dev, int *budget)
2575 struct skge_element *e; 2539 struct skge_element *e;
2576 unsigned int to_do = min(dev->quota, *budget); 2540 unsigned int to_do = min(dev->quota, *budget);
2577 unsigned int work_done = 0; 2541 unsigned int work_done = 0;
2578 int done;
2579 static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
2580 2542
2581 for (e = ring->to_clean; e != ring->to_use && work_done < to_do; 2543 pr_debug("skge_poll\n");
2582 e = e->next) { 2544
2545 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2583 struct skge_rx_desc *rd = e->desc; 2546 struct skge_rx_desc *rd = e->desc;
2584 struct sk_buff *skb = e->skb; 2547 struct sk_buff *skb;
2585 u32 control, len, status; 2548 u32 control, len, status;
2586 2549
2587 rmb(); 2550 rmb();
@@ -2590,19 +2553,12 @@ static int skge_poll(struct net_device *dev, int *budget)
2590 break; 2553 break;
2591 2554
2592 len = control & BMU_BBC; 2555 len = control & BMU_BBC;
2593 e->skb = NULL;
2594
2595 pci_unmap_single(hw->pdev,
2596 pci_unmap_addr(e, mapaddr),
2597 pci_unmap_len(e, maplen),
2598 PCI_DMA_FROMDEVICE);
2599
2600 status = rd->status; 2556 status = rd->status;
2601 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF) 2557
2602 || len > dev->mtu + VLAN_ETH_HLEN 2558 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2603 || bad_phy_status(hw, status)) { 2559 || bad_phy_status(hw, status))) {
2604 skge_rx_error(skge, e - ring->start, control, status); 2560 skge_rx_error(skge, e - ring->start, control, status);
2605 dev_kfree_skb(skb); 2561 skge_rx_reuse(e, skge->rx_buf_size);
2606 continue; 2562 continue;
2607 } 2563 }
2608 2564
@@ -2610,43 +2566,37 @@ static int skge_poll(struct net_device *dev, int *budget)
2610 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n", 2566 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2611 dev->name, e - ring->start, rd->status, len); 2567 dev->name, e - ring->start, rd->status, len);
2612 2568
2613 skb_put(skb, len); 2569 skb = skge_rx_get(skge, e, len);
2614 skb->protocol = eth_type_trans(skb, dev); 2570 if (likely(skb)) {
2615 2571 skb_put(skb, len);
2616 if (skge->rx_csum) { 2572 skb->protocol = eth_type_trans(skb, dev);
2617 skb->csum = le16_to_cpu(rd->csum2);
2618 skb->ip_summed = CHECKSUM_HW;
2619 }
2620 2573
2621 dev->last_rx = jiffies; 2574 dev->last_rx = jiffies;
2622 netif_receive_skb(skb); 2575 netif_receive_skb(skb);
2623 2576
2624 ++work_done; 2577 ++work_done;
2578 } else
2579 skge_rx_reuse(e, skge->rx_buf_size);
2625 } 2580 }
2626 ring->to_clean = e; 2581 ring->to_clean = e;
2627 2582
2628 *budget -= work_done;
2629 dev->quota -= work_done;
2630 done = work_done < to_do;
2631
2632 if (skge_rx_fill(skge))
2633 done = 0;
2634
2635 /* restart receiver */ 2583 /* restart receiver */
2636 wmb(); 2584 wmb();
2637 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), 2585 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2638 CSR_START | CSR_IRQ_CL_F); 2586 CSR_START | CSR_IRQ_CL_F);
2639 2587
2640 if (done) { 2588 *budget -= work_done;
2641 local_irq_disable(); 2589 dev->quota -= work_done;
2642 hw->intr_mask |= irqmask[skge->port];
2643 /* Order is important since data can get interrupted */
2644 skge_write32(hw, B0_IMSK, hw->intr_mask);
2645 __netif_rx_complete(dev);
2646 local_irq_enable();
2647 }
2648 2590
2649 return !done; 2591 if (work_done >= to_do)
2592 return 1; /* not done */
2593
2594 local_irq_disable();
2595 __netif_rx_complete(dev);
2596 hw->intr_mask |= portirqmask[skge->port];
2597 skge_write32(hw, B0_IMSK, hw->intr_mask);
2598 local_irq_enable();
2599 return 0;
2650} 2600}
2651 2601
2652static inline void skge_tx_intr(struct net_device *dev) 2602static inline void skge_tx_intr(struct net_device *dev)
@@ -2657,7 +2607,7 @@ static inline void skge_tx_intr(struct net_device *dev)
2657 struct skge_element *e; 2607 struct skge_element *e;
2658 2608
2659 spin_lock(&skge->tx_lock); 2609 spin_lock(&skge->tx_lock);
2660 for(e = ring->to_clean; e != ring->to_use; e = e->next) { 2610 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2661 struct skge_tx_desc *td = e->desc; 2611 struct skge_tx_desc *td = e->desc;
2662 u32 control; 2612 u32 control;
2663 2613
@@ -2690,12 +2640,12 @@ static void skge_mac_parity(struct skge_hw *hw, int port)
2690 : (port == 0 ? "(port A)": "(port B")); 2640 : (port == 0 ? "(port A)": "(port B"));
2691 2641
2692 if (hw->chip_id == CHIP_ID_GENESIS) 2642 if (hw->chip_id == CHIP_ID_GENESIS)
2693 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), 2643 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2694 MFF_CLR_PERR); 2644 MFF_CLR_PERR);
2695 else 2645 else
2696 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ 2646 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2697 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), 2647 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2698 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0) 2648 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2699 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); 2649 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2700} 2650}
2701 2651
@@ -2703,16 +2653,16 @@ static void skge_pci_clear(struct skge_hw *hw)
2703{ 2653{
2704 u16 status; 2654 u16 status;
2705 2655
2706 status = skge_read16(hw, SKGEPCI_REG(PCI_STATUS)); 2656 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2707 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2657 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2708 skge_write16(hw, SKGEPCI_REG(PCI_STATUS), 2658 pci_write_config_word(hw->pdev, PCI_STATUS,
2709 status | PCI_STATUS_ERROR_BITS); 2659 status | PCI_STATUS_ERROR_BITS);
2710 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2660 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2711} 2661}
2712 2662
2713static void skge_mac_intr(struct skge_hw *hw, int port) 2663static void skge_mac_intr(struct skge_hw *hw, int port)
2714{ 2664{
2715 if (hw->chip_id == CHIP_ID_GENESIS) 2665 if (hw->chip_id == CHIP_ID_GENESIS)
2716 genesis_mac_intr(hw, port); 2666 genesis_mac_intr(hw, port);
2717 else 2667 else
2718 yukon_mac_intr(hw, port); 2668 yukon_mac_intr(hw, port);
@@ -2726,9 +2676,9 @@ static void skge_error_irq(struct skge_hw *hw)
2726 if (hw->chip_id == CHIP_ID_GENESIS) { 2676 if (hw->chip_id == CHIP_ID_GENESIS) {
2727 /* clear xmac errors */ 2677 /* clear xmac errors */
2728 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) 2678 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2729 skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT); 2679 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2730 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) 2680 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2731 skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT); 2681 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2732 } else { 2682 } else {
2733 /* Timestamp (unused) overflow */ 2683 /* Timestamp (unused) overflow */
2734 if (hwstatus & IS_IRQ_TIST_OV) 2684 if (hwstatus & IS_IRQ_TIST_OV)
@@ -2803,8 +2753,8 @@ static void skge_extirq(unsigned long data)
2803 2753
2804 if (hw->chip_id != CHIP_ID_GENESIS) 2754 if (hw->chip_id != CHIP_ID_GENESIS)
2805 yukon_phy_intr(skge); 2755 yukon_phy_intr(skge);
2806 else if (hw->phy_type == SK_PHY_BCOM) 2756 else
2807 genesis_bcom_intr(skge); 2757 bcom_phy_intr(skge);
2808 } 2758 }
2809 } 2759 }
2810 spin_unlock(&hw->phy_lock); 2760 spin_unlock(&hw->phy_lock);
@@ -2824,19 +2774,14 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2824 return IRQ_NONE; 2774 return IRQ_NONE;
2825 2775
2826 status &= hw->intr_mask; 2776 status &= hw->intr_mask;
2827 2777 if (status & IS_R1_F) {
2828 if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
2829 status &= ~IS_R1_F;
2830 hw->intr_mask &= ~IS_R1_F; 2778 hw->intr_mask &= ~IS_R1_F;
2831 skge_write32(hw, B0_IMSK, hw->intr_mask); 2779 netif_rx_schedule(hw->dev[0]);
2832 __netif_rx_schedule(hw->dev[0]);
2833 } 2780 }
2834 2781
2835 if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) { 2782 if (status & IS_R2_F) {
2836 status &= ~IS_R2_F;
2837 hw->intr_mask &= ~IS_R2_F; 2783 hw->intr_mask &= ~IS_R2_F;
2838 skge_write32(hw, B0_IMSK, hw->intr_mask); 2784 netif_rx_schedule(hw->dev[1]);
2839 __netif_rx_schedule(hw->dev[1]);
2840 } 2785 }
2841 2786
2842 if (status & IS_XA1_F) 2787 if (status & IS_XA1_F)
@@ -2845,9 +2790,27 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2845 if (status & IS_XA2_F) 2790 if (status & IS_XA2_F)
2846 skge_tx_intr(hw->dev[1]); 2791 skge_tx_intr(hw->dev[1]);
2847 2792
2793 if (status & IS_PA_TO_RX1) {
2794 struct skge_port *skge = netdev_priv(hw->dev[0]);
2795 ++skge->net_stats.rx_over_errors;
2796 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2797 }
2798
2799 if (status & IS_PA_TO_RX2) {
2800 struct skge_port *skge = netdev_priv(hw->dev[1]);
2801 ++skge->net_stats.rx_over_errors;
2802 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2803 }
2804
2805 if (status & IS_PA_TO_TX1)
2806 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2807
2808 if (status & IS_PA_TO_TX2)
2809 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2810
2848 if (status & IS_MAC1) 2811 if (status & IS_MAC1)
2849 skge_mac_intr(hw, 0); 2812 skge_mac_intr(hw, 0);
2850 2813
2851 if (status & IS_MAC2) 2814 if (status & IS_MAC2)
2852 skge_mac_intr(hw, 1); 2815 skge_mac_intr(hw, 1);
2853 2816
@@ -2859,8 +2822,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2859 tasklet_schedule(&hw->ext_tasklet); 2822 tasklet_schedule(&hw->ext_tasklet);
2860 } 2823 }
2861 2824
2862 if (status) 2825 skge_write32(hw, B0_IMSK, hw->intr_mask);
2863 skge_write32(hw, B0_IMSK, hw->intr_mask);
2864 2826
2865 return IRQ_HANDLED; 2827 return IRQ_HANDLED;
2866} 2828}
@@ -2904,9 +2866,6 @@ static const struct {
2904 { CHIP_ID_YUKON, "Yukon" }, 2866 { CHIP_ID_YUKON, "Yukon" },
2905 { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, 2867 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2906 { CHIP_ID_YUKON_LP, "Yukon-LP"}, 2868 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2907 { CHIP_ID_YUKON_XL, "Yukon-2 XL"},
2908 { CHIP_ID_YUKON_EC, "YUKON-2 EC"},
2909 { CHIP_ID_YUKON_FE, "YUKON-2 FE"},
2910}; 2869};
2911 2870
2912static const char *skge_board_name(const struct skge_hw *hw) 2871static const char *skge_board_name(const struct skge_hw *hw)
@@ -2930,8 +2889,8 @@ static const char *skge_board_name(const struct skge_hw *hw)
2930static int skge_reset(struct skge_hw *hw) 2889static int skge_reset(struct skge_hw *hw)
2931{ 2890{
2932 u16 ctst; 2891 u16 ctst;
2933 u8 t8; 2892 u8 t8, mac_cfg;
2934 int i, ports; 2893 int i;
2935 2894
2936 ctst = skge_read16(hw, B0_CTST); 2895 ctst = skge_read16(hw, B0_CTST);
2937 2896
@@ -2952,12 +2911,9 @@ static int skge_reset(struct skge_hw *hw)
2952 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; 2911 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2953 hw->pmd_type = skge_read8(hw, B2_PMD_TYP); 2912 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2954 2913
2955 switch(hw->chip_id) { 2914 switch (hw->chip_id) {
2956 case CHIP_ID_GENESIS: 2915 case CHIP_ID_GENESIS:
2957 switch (hw->phy_type) { 2916 switch (hw->phy_type) {
2958 case SK_PHY_XMAC:
2959 hw->phy_addr = PHY_ADDR_XMAC;
2960 break;
2961 case SK_PHY_BCOM: 2917 case SK_PHY_BCOM:
2962 hw->phy_addr = PHY_ADDR_BCOM; 2918 hw->phy_addr = PHY_ADDR_BCOM;
2963 break; 2919 break;
@@ -2986,8 +2942,9 @@ static int skge_reset(struct skge_hw *hw)
2986 return -EOPNOTSUPP; 2942 return -EOPNOTSUPP;
2987 } 2943 }
2988 2944
2989 hw->mac_cfg = skge_read8(hw, B2_MAC_CFG); 2945 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2990 ports = isdualport(hw) ? 2 : 1; 2946 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2947 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2991 2948
2992 /* read the adapters RAM size */ 2949 /* read the adapters RAM size */
2993 t8 = skge_read8(hw, B2_E_0); 2950 t8 = skge_read8(hw, B2_E_0);
@@ -3010,9 +2967,9 @@ static int skge_reset(struct skge_hw *hw)
3010 /* switch power to VCC (WA for VAUX problem) */ 2967 /* switch power to VCC (WA for VAUX problem) */
3011 skge_write8(hw, B0_POWER_CTRL, 2968 skge_write8(hw, B0_POWER_CTRL,
3012 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 2969 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3013 for (i = 0; i < ports; i++) { 2970 for (i = 0; i < hw->ports; i++) {
3014 skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 2971 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3015 skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 2972 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3016 } 2973 }
3017 } 2974 }
3018 2975
@@ -3022,8 +2979,8 @@ static int skge_reset(struct skge_hw *hw)
3022 skge_write8(hw, B0_LED, LED_STAT_ON); 2979 skge_write8(hw, B0_LED, LED_STAT_ON);
3023 2980
3024 /* enable the Tx Arbiters */ 2981 /* enable the Tx Arbiters */
3025 for (i = 0; i < ports; i++) 2982 for (i = 0; i < hw->ports; i++)
3026 skge_write8(hw, SKGEMAC_REG(i, TXA_CTRL), TXA_ENA_ARB); 2983 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3027 2984
3028 /* Initialize ram interface */ 2985 /* Initialize ram interface */
3029 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); 2986 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
@@ -3050,16 +3007,14 @@ static int skge_reset(struct skge_hw *hw)
3050 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); 3007 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3051 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 3008 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3052 3009
3053 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1; 3010 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3054 if (isdualport(hw))
3055 hw->intr_mask |= IS_PORT_2;
3056 skge_write32(hw, B0_IMSK, hw->intr_mask); 3011 skge_write32(hw, B0_IMSK, hw->intr_mask);
3057 3012
3058 if (hw->chip_id != CHIP_ID_GENESIS) 3013 if (hw->chip_id != CHIP_ID_GENESIS)
3059 skge_write8(hw, GMAC_IRQ_MSK, 0); 3014 skge_write8(hw, GMAC_IRQ_MSK, 0);
3060 3015
3061 spin_lock_bh(&hw->phy_lock); 3016 spin_lock_bh(&hw->phy_lock);
3062 for (i = 0; i < ports; i++) { 3017 for (i = 0; i < hw->ports; i++) {
3063 if (hw->chip_id == CHIP_ID_GENESIS) 3018 if (hw->chip_id == CHIP_ID_GENESIS)
3064 genesis_reset(hw, i); 3019 genesis_reset(hw, i);
3065 else 3020 else
@@ -3071,7 +3026,8 @@ static int skge_reset(struct skge_hw *hw)
3071} 3026}
3072 3027
3073/* Initialize network device */ 3028/* Initialize network device */
3074static struct net_device *skge_devinit(struct skge_hw *hw, int port) 3029static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3030 int highmem)
3075{ 3031{
3076 struct skge_port *skge; 3032 struct skge_port *skge;
3077 struct net_device *dev = alloc_etherdev(sizeof(*skge)); 3033 struct net_device *dev = alloc_etherdev(sizeof(*skge));
@@ -3104,6 +3060,8 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port)
3104#endif 3060#endif
3105 dev->irq = hw->pdev->irq; 3061 dev->irq = hw->pdev->irq;
3106 dev->features = NETIF_F_LLTX; 3062 dev->features = NETIF_F_LLTX;
3063 if (highmem)
3064 dev->features |= NETIF_F_HIGHDMA;
3107 3065
3108 skge = netdev_priv(dev); 3066 skge = netdev_priv(dev);
3109 skge->netdev = dev; 3067 skge->netdev = dev;
@@ -3117,7 +3075,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port)
3117 skge->flow_control = FLOW_MODE_SYMMETRIC; 3075 skge->flow_control = FLOW_MODE_SYMMETRIC;
3118 skge->duplex = -1; 3076 skge->duplex = -1;
3119 skge->speed = -1; 3077 skge->speed = -1;
3120 skge->advertising = skge_modes(hw); 3078 skge->advertising = skge_supported_modes(hw);
3121 3079
3122 hw->dev[port] = dev; 3080 hw->dev[port] = dev;
3123 3081
@@ -3125,10 +3083,6 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port)
3125 3083
3126 spin_lock_init(&skge->tx_lock); 3084 spin_lock_init(&skge->tx_lock);
3127 3085
3128 init_timer(&skge->link_check);
3129 skge->link_check.function = skge_link_timer;
3130 skge->link_check.data = (unsigned long) skge;
3131
3132 init_timer(&skge->led_blink); 3086 init_timer(&skge->led_blink);
3133 skge->led_blink.function = skge_blink_timer; 3087 skge->led_blink.function = skge_blink_timer;
3134 skge->led_blink.data = (unsigned long) skge; 3088 skge->led_blink.data = (unsigned long) skge;
@@ -3232,14 +3186,11 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3232 3186
3233 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n", 3187 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3234 pci_resource_start(pdev, 0), pdev->irq, 3188 pci_resource_start(pdev, 0), pdev->irq,
3235 skge_board_name(hw), chip_rev(hw)); 3189 skge_board_name(hw), hw->chip_rev);
3236 3190
3237 if ((dev = skge_devinit(hw, 0)) == NULL) 3191 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3238 goto err_out_led_off; 3192 goto err_out_led_off;
3239 3193
3240 if (using_dac)
3241 dev->features |= NETIF_F_HIGHDMA;
3242
3243 if ((err = register_netdev(dev))) { 3194 if ((err = register_netdev(dev))) {
3244 printk(KERN_ERR PFX "%s: cannot register net device\n", 3195 printk(KERN_ERR PFX "%s: cannot register net device\n",
3245 pci_name(pdev)); 3196 pci_name(pdev));
@@ -3248,10 +3199,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3248 3199
3249 skge_show_addr(dev); 3200 skge_show_addr(dev);
3250 3201
3251 if (isdualport(hw) && (dev1 = skge_devinit(hw, 1))) { 3202 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3252 if (using_dac)
3253 dev1->features |= NETIF_F_HIGHDMA;
3254
3255 if (register_netdev(dev1) == 0) 3203 if (register_netdev(dev1) == 0)
3256 skge_show_addr(dev1); 3204 skge_show_addr(dev1);
3257 else { 3205 else {
@@ -3288,7 +3236,7 @@ static void __devexit skge_remove(struct pci_dev *pdev)
3288 struct skge_hw *hw = pci_get_drvdata(pdev); 3236 struct skge_hw *hw = pci_get_drvdata(pdev);
3289 struct net_device *dev0, *dev1; 3237 struct net_device *dev0, *dev1;
3290 3238
3291 if(!hw) 3239 if (!hw)
3292 return; 3240 return;
3293 3241
3294 if ((dev1 = hw->dev[1])) 3242 if ((dev1 = hw->dev[1]))
@@ -3316,7 +3264,7 @@ static int skge_suspend(struct pci_dev *pdev, u32 state)
3316 struct skge_hw *hw = pci_get_drvdata(pdev); 3264 struct skge_hw *hw = pci_get_drvdata(pdev);
3317 int i, wol = 0; 3265 int i, wol = 0;
3318 3266
3319 for(i = 0; i < 2; i++) { 3267 for (i = 0; i < 2; i++) {
3320 struct net_device *dev = hw->dev[i]; 3268 struct net_device *dev = hw->dev[i];
3321 3269
3322 if (dev) { 3270 if (dev) {
@@ -3349,11 +3297,11 @@ static int skge_resume(struct pci_dev *pdev)
3349 3297
3350 skge_reset(hw); 3298 skge_reset(hw);
3351 3299
3352 for(i = 0; i < 2; i++) { 3300 for (i = 0; i < 2; i++) {
3353 struct net_device *dev = hw->dev[i]; 3301 struct net_device *dev = hw->dev[i];
3354 if (dev) { 3302 if (dev) {
3355 netif_device_attach(dev); 3303 netif_device_attach(dev);
3356 if(netif_running(dev)) 3304 if (netif_running(dev))
3357 skge_up(dev); 3305 skge_up(dev);
3358 } 3306 }
3359 } 3307 }
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index 36c62b68fab4..14d0cc01fb9a 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -7,31 +7,6 @@
7/* PCI config registers */ 7/* PCI config registers */
8#define PCI_DEV_REG1 0x40 8#define PCI_DEV_REG1 0x40
9#define PCI_DEV_REG2 0x44 9#define PCI_DEV_REG2 0x44
10#ifndef PCI_VPD
11#define PCI_VPD 0x50
12#endif
13
14/* PCI_OUR_REG_2 32 bit Our Register 2 */
15enum {
16 PCI_VPD_WR_THR = 0xff<<24, /* Bit 31..24: VPD Write Threshold */
17 PCI_DEV_SEL = 0x7f<<17, /* Bit 23..17: EEPROM Device Select */
18 PCI_VPD_ROM_SZ = 7 <<14, /* Bit 16..14: VPD ROM Size */
19 /* Bit 13..12: reserved */
20 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
21 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
22 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
23};
24
25/* PCI_VPD_ADR_REG 16 bit VPD Address Register */
26enum {
27 PCI_VPD_FLAG = 1<<15, /* starts VPD rd/wr cycle */
28 PCI_VPD_ADR_MSK =0x7fffL, /* Bit 14.. 0: VPD Address Mask */
29 VPD_RES_ID = 0x82,
30 VPD_RES_READ = 0x90,
31 VPD_RES_WRITE = 0x81,
32 VPD_RES_END = 0x78,
33};
34
35 10
36#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 11#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
37 PCI_STATUS_SIG_SYSTEM_ERROR | \ 12 PCI_STATUS_SIG_SYSTEM_ERROR | \
@@ -39,7 +14,6 @@ enum {
39 PCI_STATUS_REC_TARGET_ABORT | \ 14 PCI_STATUS_REC_TARGET_ABORT | \
40 PCI_STATUS_PARITY) 15 PCI_STATUS_PARITY)
41 16
42
43enum csr_regs { 17enum csr_regs {
44 B0_RAP = 0x0000, 18 B0_RAP = 0x0000,
45 B0_CTST = 0x0004, 19 B0_CTST = 0x0004,
@@ -229,8 +203,11 @@ enum {
229 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */ 203 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
230 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */ 204 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
231 205
232 IS_PORT_1 = IS_XA1_F| IS_R1_F| IS_MAC1, 206 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
233 IS_PORT_2 = IS_XA2_F| IS_R2_F| IS_MAC2, 207 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
208
209 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
210 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
234}; 211};
235 212
236 213
@@ -288,14 +265,6 @@ enum {
288 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */ 265 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
289}; 266};
290 267
291/* B2_LD_TEST 8 bit EPROM loader test register */
292enum {
293 LD_T_ON = 1<<3, /* Loader Test mode on */
294 LD_T_OFF = 1<<2, /* Loader Test mode off */
295 LD_T_STEP = 1<<1, /* Decrement FPROM addr. Counter */
296 LD_START = 1<<0, /* Start loading FPROM */
297};
298
299/* B2_TI_CTRL 8 bit Timer control */ 268/* B2_TI_CTRL 8 bit Timer control */
300/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 269/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
301enum { 270enum {
@@ -313,16 +282,6 @@ enum {
313 TIM_T_STEP = 1<<0, /* Test step */ 282 TIM_T_STEP = 1<<0, /* Test step */
314}; 283};
315 284
316/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
317/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
318/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
319enum {
320 DPT_MSK = 0x00ffffffL, /* Bit 23.. 0: Desc Poll Timer Bits */
321
322 DPT_START = 1<<1, /* Start Descriptor Poll Timer */
323 DPT_STOP = 1<<0, /* Stop Descriptor Poll Timer */
324};
325
326/* B2_GP_IO 32 bit General Purpose I/O Register */ 285/* B2_GP_IO 32 bit General Purpose I/O Register */
327enum { 286enum {
328 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */ 287 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
@@ -348,30 +307,6 @@ enum {
348 GP_IO_0 = 1<<0, /* IO_0 pin */ 307 GP_IO_0 = 1<<0, /* IO_0 pin */
349}; 308};
350 309
351/* Rx/Tx Path related Arbiter Test Registers */
352/* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
353/* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
354/* B3_PA_TEST 16 bit Packet Arbiter Test Register */
355/* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
356enum {
357 TX2_T_EV = 1<<15,/* TX2 Timeout/Recv Event occured */
358 TX2_T_ON = 1<<14,/* TX2 Timeout/Recv Timer Test On */
359 TX2_T_OFF = 1<<13,/* TX2 Timeout/Recv Timer Tst Off */
360 TX2_T_STEP = 1<<12,/* TX2 Timeout/Recv Timer Step */
361 TX1_T_EV = 1<<11,/* TX1 Timeout/Recv Event occured */
362 TX1_T_ON = 1<<10,/* TX1 Timeout/Recv Timer Test On */
363 TX1_T_OFF = 1<<9, /* TX1 Timeout/Recv Timer Tst Off */
364 TX1_T_STEP = 1<<8, /* TX1 Timeout/Recv Timer Step */
365 RX2_T_EV = 1<<7, /* RX2 Timeout/Recv Event occured */
366 RX2_T_ON = 1<<6, /* RX2 Timeout/Recv Timer Test On */
367 RX2_T_OFF = 1<<5, /* RX2 Timeout/Recv Timer Tst Off */
368 RX2_T_STEP = 1<<4, /* RX2 Timeout/Recv Timer Step */
369 RX1_T_EV = 1<<3, /* RX1 Timeout/Recv Event occured */
370 RX1_T_ON = 1<<2, /* RX1 Timeout/Recv Timer Test On */
371 RX1_T_OFF = 1<<1, /* RX1 Timeout/Recv Timer Tst Off */
372 RX1_T_STEP = 1<<0, /* RX1 Timeout/Recv Timer Step */
373};
374
375/* Descriptor Bit Definition */ 310/* Descriptor Bit Definition */
376/* TxCtrl Transmit Buffer Control Field */ 311/* TxCtrl Transmit Buffer Control Field */
377/* RxCtrl Receive Buffer Control Field */ 312/* RxCtrl Receive Buffer Control Field */
@@ -428,14 +363,6 @@ enum {
428 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ 363 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
429}; 364};
430 365
431/* B3_RI_TEST 8 bit RAM Iface Test Register */
432enum {
433 RI_T_EV = 1<<3, /* Timeout Event occured */
434 RI_T_ON = 1<<2, /* Timeout Timer Test On */
435 RI_T_OFF = 1<<1, /* Timeout Timer Test Off */
436 RI_T_STEP = 1<<0, /* Timeout Timer Step */
437};
438
439/* MAC Arbiter Registers */ 366/* MAC Arbiter Registers */
440/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */ 367/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
441enum { 368enum {
@@ -452,19 +379,6 @@ enum {
452#define SK_PKT_TO_MAX 0xffff /* Maximum value */ 379#define SK_PKT_TO_MAX 0xffff /* Maximum value */
453#define SK_RI_TO_53 36 /* RAM interface timeout */ 380#define SK_RI_TO_53 36 /* RAM interface timeout */
454 381
455
456/* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
457enum {
458 MA_ENA_REC_TX2 = 1<<7, /* Enable Recovery Timer TX2 */
459 MA_DIS_REC_TX2 = 1<<6, /* Disable Recovery Timer TX2 */
460 MA_ENA_REC_TX1 = 1<<5, /* Enable Recovery Timer TX1 */
461 MA_DIS_REC_TX1 = 1<<4, /* Disable Recovery Timer TX1 */
462 MA_ENA_REC_RX2 = 1<<3, /* Enable Recovery Timer RX2 */
463 MA_DIS_REC_RX2 = 1<<2, /* Disable Recovery Timer RX2 */
464 MA_ENA_REC_RX1 = 1<<1, /* Enable Recovery Timer RX1 */
465 MA_DIS_REC_RX1 = 1<<0, /* Disable Recovery Timer RX1 */
466};
467
468/* Packet Arbiter Registers */ 382/* Packet Arbiter Registers */
469/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ 383/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
470enum { 384enum {
@@ -488,7 +402,7 @@ enum {
488 PA_ENA_TO_TX1 | PA_ENA_TO_TX2) 402 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
489 403
490 404
491/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 405/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
492/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 406/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
493/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 407/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
494/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 408/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
@@ -511,7 +425,7 @@ enum {
511/* 425/*
512 * Bank 4 - 5 426 * Bank 4 - 5
513 */ 427 */
514/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 428/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
515enum { 429enum {
516 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ 430 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
517 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ 431 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
@@ -537,7 +451,7 @@ enum {
537 451
538/* Queue Register Offsets, use Q_ADDR() to access */ 452/* Queue Register Offsets, use Q_ADDR() to access */
539enum { 453enum {
540 B8_Q_REGS = 0x0400, /* base of Queue registers */ 454 B8_Q_REGS = 0x0400, /* base of Queue registers */
541 Q_D = 0x00, /* 8*32 bit Current Descriptor */ 455 Q_D = 0x00, /* 8*32 bit Current Descriptor */
542 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ 456 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
543 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ 457 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
@@ -618,8 +532,7 @@ enum {
618enum { 532enum {
619 PHY_ADDR_XMAC = 0<<8, 533 PHY_ADDR_XMAC = 0<<8,
620 PHY_ADDR_BCOM = 1<<8, 534 PHY_ADDR_BCOM = 1<<8,
621 PHY_ADDR_LONE = 3<<8, 535
622 PHY_ADDR_NAT = 0<<8,
623/* GPHY address (bits 15..11 of SMI control reg) */ 536/* GPHY address (bits 15..11 of SMI control reg) */
624 PHY_ADDR_MARV = 0, 537 PHY_ADDR_MARV = 0,
625}; 538};
@@ -986,7 +899,7 @@ enum {
986 LINKLED_BLINK_OFF = 0x10, 899 LINKLED_BLINK_OFF = 0x10,
987 LINKLED_BLINK_ON = 0x20, 900 LINKLED_BLINK_ON = 0x20,
988}; 901};
989 902
990/* GMAC and GPHY Control Registers (YUKON only) */ 903/* GMAC and GPHY Control Registers (YUKON only) */
991enum { 904enum {
992 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ 905 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
@@ -1151,54 +1064,6 @@ enum {
1151 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ 1064 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1152}; 1065};
1153 1066
1154/* Level One-PHY Registers, indirect addressed over XMAC */
1155enum {
1156 PHY_LONE_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1157 PHY_LONE_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1158 PHY_LONE_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1159 PHY_LONE_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1160 PHY_LONE_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1161 PHY_LONE_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1162 PHY_LONE_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1163 PHY_LONE_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1164 PHY_LONE_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1165 /* Level One-specific registers */
1166 PHY_LONE_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1167 PHY_LONE_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1168 PHY_LONE_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1169 PHY_LONE_PORT_CFG = 0x10,/* 16 bit r/w Port Configuration Reg*/
1170 PHY_LONE_Q_STAT = 0x11,/* 16 bit r/o Quick Status Reg */
1171 PHY_LONE_INT_ENAB = 0x12,/* 16 bit r/w Interrupt Enable Reg */
1172 PHY_LONE_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1173 PHY_LONE_LED_CFG = 0x14,/* 16 bit r/w LED Configuration Reg */
1174 PHY_LONE_PORT_CTRL = 0x15,/* 16 bit r/w Port Control Reg */
1175 PHY_LONE_CIM = 0x16,/* 16 bit r/o CIM Reg */
1176};
1177
1178/* National-PHY Registers, indirect addressed over XMAC */
1179enum {
1180 PHY_NAT_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1181 PHY_NAT_STAT = 0x01,/* 16 bit r/w PHY Status Register */
1182 PHY_NAT_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1183 PHY_NAT_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1184 PHY_NAT_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1185 PHY_NAT_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Ability Reg */
1186 PHY_NAT_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1187 PHY_NAT_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1188 PHY_NAT_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner Reg */
1189 /* National-specific registers */
1190 PHY_NAT_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1191 PHY_NAT_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1192 PHY_NAT_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Register */
1193 PHY_NAT_EXT_CTRL1 = 0x10,/* 16 bit r/o Extended Control Reg1 */
1194 PHY_NAT_Q_STAT1 = 0x11,/* 16 bit r/o Quick Status Reg1 */
1195 PHY_NAT_10B_OP = 0x12,/* 16 bit r/o 10Base-T Operations Reg */
1196 PHY_NAT_EXT_CTRL2 = 0x13,/* 16 bit r/o Extended Control Reg1 */
1197 PHY_NAT_Q_STAT2 = 0x14,/* 16 bit r/o Quick Status Reg2 */
1198
1199 PHY_NAT_PHY_ADDR = 0x19,/* 16 bit r/o PHY Address Register */
1200};
1201
1202enum { 1067enum {
1203 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ 1068 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1204 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ 1069 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
@@ -1253,8 +1118,29 @@ enum {
1253 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ 1118 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1254}; 1119};
1255 1120
1121/* Advertisement register bits */
1256enum { 1122enum {
1257 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ 1123 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1124 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1125 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1126
1127 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1128 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1129 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1130 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1131 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1132 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1133 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1134 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1135 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1136 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1137 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1138 PHY_AN_100HALF | PHY_AN_100FULL,
1139};
1140
1141/* Xmac Specific */
1142enum {
1143 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1258 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ 1144 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1259 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */ 1145 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1260 1146
@@ -1263,82 +1149,6 @@ enum {
1263 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */ 1149 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1264}; 1150};
1265 1151
1266enum {
1267 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1268
1269 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1270 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1271 PHY_B_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1272};
1273
1274enum {
1275 PHY_L_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1276 /* Bit 12: reserved */
1277 PHY_L_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1278 PHY_L_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1279
1280 PHY_L_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1281};
1282
1283/* PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement */
1284/* PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1285/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
1286enum {
1287 PHY_N_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1288
1289 PHY_N_AN_100F = 1<<11, /* Bit 11: 100Base-T2 FD Support */
1290 PHY_N_AN_100H = 1<<10, /* Bit 10: 100Base-T2 HD Support */
1291
1292 PHY_N_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1293};
1294
1295/* field type definition for PHY_x_AN_SEL */
1296enum {
1297 PHY_SEL_TYPE = 1, /* 00001 = Ethernet */
1298};
1299
1300enum {
1301 PHY_ANE_LP_NP = 1<<3, /* Bit 3: Link Partner can Next Page */
1302 PHY_ANE_LOC_NP = 1<<2, /* Bit 2: Local PHY can Next Page */
1303 PHY_ANE_RX_PG = 1<<1, /* Bit 1: Page Received */
1304};
1305
1306enum {
1307 PHY_ANE_PAR_DF = 1<<4, /* Bit 4: Parallel Detection Fault */
1308
1309 PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */
1310};
1311
1312enum {
1313 PHY_NP_MORE = 1<<15, /* Bit 15: More, Next Pages to follow */
1314 PHY_NP_ACK1 = 1<<14, /* Bit 14: (ro) Ack1, for receiving a message */
1315 PHY_NP_MSG_VAL = 1<<13, /* Bit 13: Message Page valid */
1316 PHY_NP_ACK2 = 1<<12, /* Bit 12: Ack2, comply with msg content */
1317 PHY_NP_TOG = 1<<11, /* Bit 11: Toggle Bit, ensure sync */
1318 PHY_NP_MSG = 0x07ff, /* Bit 10..0: Message from/to Link Partner */
1319};
1320
1321enum {
1322 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1323 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1324};
1325
1326enum {
1327 PHY_X_RS_PAUSE = 3<<7,/* Bit 8..7: selected Pause Mode */
1328 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1329 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1330 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1331 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1332};
1333
1334/** Remote Fault Bits (PHY_X_AN_RFB) encoding */
1335enum {
1336 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1337 X_RFB_LF = 1<<12, /* Bit 13..12 Link Failure */
1338 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1339 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1340};
1341
1342/* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */ 1152/* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1343enum { 1153enum {
1344 PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */ 1154 PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */
@@ -1418,6 +1228,16 @@ enum {
1418 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */ 1228 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1419}; 1229};
1420 1230
1231/* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1232/* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1233enum {
1234 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1235
1236 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1237 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1238};
1239
1240
1421/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ 1241/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1422enum { 1242enum {
1423 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */ 1243 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
@@ -1478,7 +1298,9 @@ enum {
1478 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */ 1298 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1479 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */ 1299 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1480}; 1300};
1481#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) 1301#define PHY_B_DEF_MSK \
1302 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1303 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1482 1304
1483/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ 1305/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1484enum { 1306enum {
@@ -1495,166 +1317,6 @@ enum {
1495 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */ 1317 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1496}; 1318};
1497 1319
1498/*
1499 * Level One-Specific
1500 */
1501/***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1502enum {
1503 PHY_L_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1504 PHY_L_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1505 PHY_L_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1506 PHY_L_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1507 PHY_L_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1508 PHY_L_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1509};
1510
1511/***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1512enum {
1513 PHY_L_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1514 PHY_L_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1515 PHY_L_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1516 PHY_L_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1517 PHY_L_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1518 PHY_L_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1519
1520 PHY_L_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1521
1522/***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/
1523 PHY_L_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1524 PHY_L_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1525 PHY_L_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1526 PHY_L_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1527};
1528
1529/***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/
1530enum {
1531 PHY_L_PC_REP_MODE = 1<<15, /* Bit 15: Repeater Mode */
1532
1533 PHY_L_PC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1534 PHY_L_PC_BY_SCR = 1<<12, /* Bit 12: Bypass Scrambler */
1535 PHY_L_PC_BY_45 = 1<<11, /* Bit 11: Bypass 4B5B-Decoder */
1536 PHY_L_PC_JAB_DIS = 1<<10, /* Bit 10: Jabber Disabled */
1537 PHY_L_PC_SQE = 1<<9, /* Bit 9: Enable Heartbeat */
1538 PHY_L_PC_TP_LOOP = 1<<8, /* Bit 8: TP Loopback */
1539 PHY_L_PC_SSS = 1<<7, /* Bit 7: Smart Speed Selection */
1540 PHY_L_PC_FIFO_SIZE = 1<<6, /* Bit 6: FIFO Size */
1541 PHY_L_PC_PRE_EN = 1<<5, /* Bit 5: Preamble Enable */
1542 PHY_L_PC_CIM = 1<<4, /* Bit 4: Carrier Integrity Mon */
1543 PHY_L_PC_10_SER = 1<<3, /* Bit 3: Use Serial Output */
1544 PHY_L_PC_ANISOL = 1<<2, /* Bit 2: Unisolate Port */
1545 PHY_L_PC_TEN_BIT = 1<<1, /* Bit 1: 10bit iface mode on */
1546 PHY_L_PC_ALTCLOCK = 1<<0, /* Bit 0: (ro) ALTCLOCK Mode on */
1547};
1548
1549/***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/
1550enum {
1551 PHY_L_QS_D_RATE = 3<<14,/* Bit 15..14: Data Rate */
1552 PHY_L_QS_TX_STAT = 1<<13, /* Bit 13: Transmitting */
1553 PHY_L_QS_RX_STAT = 1<<12, /* Bit 12: Receiving */
1554 PHY_L_QS_COL_STAT = 1<<11, /* Bit 11: Collision */
1555 PHY_L_QS_L_STAT = 1<<10, /* Bit 10: Link is up */
1556 PHY_L_QS_DUP_MOD = 1<<9, /* Bit 9: Full/Half Duplex */
1557 PHY_L_QS_AN = 1<<8, /* Bit 8: AutoNeg is On */
1558 PHY_L_QS_AN_C = 1<<7, /* Bit 7: AN is Complete */
1559 PHY_L_QS_LLE = 7<<4,/* Bit 6..4: Line Length Estim. */
1560 PHY_L_QS_PAUSE = 1<<3, /* Bit 3: LP advertised Pause */
1561 PHY_L_QS_AS_PAUSE = 1<<2, /* Bit 2: LP adv. asym. Pause */
1562 PHY_L_QS_ISOLATE = 1<<1, /* Bit 1: CIM Isolated */
1563 PHY_L_QS_EVENT = 1<<0, /* Bit 0: Event has occurred */
1564};
1565
1566/***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/
1567/***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1568enum {
1569 PHY_L_IS_AN_F = 1<<13, /* Bit 13: Auto-Negotiation fault */
1570 PHY_L_IS_CROSS = 1<<11, /* Bit 11: Crossover used */
1571 PHY_L_IS_POL = 1<<10, /* Bit 10: Polarity correct. used */
1572 PHY_L_IS_SS = 1<<9, /* Bit 9: Smart Speed Downgrade */
1573 PHY_L_IS_CFULL = 1<<8, /* Bit 8: Counter Full */
1574 PHY_L_IS_AN_C = 1<<7, /* Bit 7: AutoNeg Complete */
1575 PHY_L_IS_SPEED = 1<<6, /* Bit 6: Speed Changed */
1576 PHY_L_IS_DUP = 1<<5, /* Bit 5: Duplex Changed */
1577 PHY_L_IS_LS = 1<<4, /* Bit 4: Link Status Changed */
1578 PHY_L_IS_ISOL = 1<<3, /* Bit 3: Isolate Occured */
1579 PHY_L_IS_MDINT = 1<<2, /* Bit 2: (ro) STAT: MII Int Pending */
1580 PHY_L_IS_INTEN = 1<<1, /* Bit 1: ENAB: Enable IRQs */
1581 PHY_L_IS_FORCE = 1<<0, /* Bit 0: ENAB: Force Interrupt */
1582};
1583
1584/* int. mask */
1585#define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
1586
1587/***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/
1588enum {
1589 PHY_L_LC_LEDC = 3<<14,/* Bit 15..14: Col/Blink/On/Off */
1590 PHY_L_LC_LEDR = 3<<12,/* Bit 13..12: Rx/Blink/On/Off */
1591 PHY_L_LC_LEDT = 3<<10,/* Bit 11..10: Tx/Blink/On/Off */
1592 PHY_L_LC_LEDG = 3<<8,/* Bit 9..8: Giga/Blink/On/Off */
1593 PHY_L_LC_LEDS = 3<<6,/* Bit 7..6: 10-100/Blink/On/Off */
1594 PHY_L_LC_LEDL = 3<<4,/* Bit 5..4: Link/Blink/On/Off */
1595 PHY_L_LC_LEDF = 3<<2,/* Bit 3..2: Duplex/Blink/On/Off */
1596 PHY_L_LC_PSTRECH= 1<<1, /* Bit 1: Strech LED Pulses */
1597 PHY_L_LC_FREQ = 1<<0, /* Bit 0: 30/100 ms */
1598};
1599
1600/***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/
1601enum {
1602 PHY_L_PC_TX_TCLK = 1<<15, /* Bit 15: Enable TX_TCLK */
1603 PHY_L_PC_ALT_NP = 1<<13, /* Bit 14: Alternate Next Page */
1604 PHY_L_PC_GMII_ALT= 1<<12, /* Bit 13: Alternate GMII driver */
1605 PHY_L_PC_TEN_CRS = 1<<10, /* Bit 10: Extend CRS*/
1606};
1607
1608/***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
1609enum {
1610 PHY_L_CIM_ISOL = 0xff<<8,/* Bit 15..8: Isolate Count */
1611 PHY_L_CIM_FALSE_CAR = 0xff, /* Bit 7..0: False Carrier Count */
1612};
1613
1614/*
1615 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
1616 */
1617enum {
1618 PHY_L_P_NO_PAUSE= 0<<10,/* Bit 11..10: no Pause Mode */
1619 PHY_L_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1620 PHY_L_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1621 PHY_L_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1622};
1623
1624/*
1625 * National-Specific
1626 */
1627/***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1628enum {
1629 PHY_N_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1630 PHY_N_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1631 PHY_N_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1632 PHY_N_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1633 PHY_N_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1634 PHY_N_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1635 PHY_N_1000C_APC = 1<<7, /* Bit 7: Asymmetric Pause Cap. */};
1636
1637
1638/***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1639enum {
1640 PHY_N_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1641 PHY_N_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1642 PHY_N_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1643 PHY_N_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status*/
1644 PHY_N_1000S_LP_FD= 1<<11, /* Bit 11: Link Partner can FD */
1645 PHY_N_1000S_LP_HD= 1<<10, /* Bit 10: Link Partner can HD */
1646 PHY_N_1000C_LP_APC= 1<<9, /* Bit 9: LP Asym. Pause Cap. */
1647 PHY_N_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1648};
1649
1650/***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/
1651enum {
1652 PHY_N_ES_X_FD_CAP= 1<<15, /* Bit 15: 1000Base-X FD capable */
1653 PHY_N_ES_X_HD_CAP= 1<<14, /* Bit 14: 1000Base-X HD capable */
1654 PHY_N_ES_T_FD_CAP= 1<<13, /* Bit 13: 1000Base-T FD capable */
1655 PHY_N_ES_T_HD_CAP= 1<<12, /* Bit 12: 1000Base-T HD capable */
1656};
1657
1658/** Marvell-Specific */ 1320/** Marvell-Specific */
1659enum { 1321enum {
1660 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ 1322 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
@@ -1718,7 +1380,7 @@ enum {
1718 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ 1380 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1719}; 1381};
1720 1382
1721#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) 1383#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1722 1384
1723enum { 1385enum {
1724 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ 1386 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
@@ -2105,7 +1767,7 @@ enum {
2105 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ 1767 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
2106 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ 1768 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
2107}; 1769};
2108 1770
2109/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1771/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
2110enum { 1772enum {
2111 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ 1773 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
@@ -2127,7 +1789,7 @@ enum {
2127 1789
2128#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1790#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
2129#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) 1791#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
2130 1792
2131/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1793/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
2132enum { 1794enum {
2133 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ 1795 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
@@ -2138,7 +1800,7 @@ enum {
2138 1800
2139#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) 1801#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
2140#define TX_COL_DEF 0x04 1802#define TX_COL_DEF 0x04
2141 1803
2142/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1804/* GM_RX_CTRL 16 bit r/w Receive Control Register */
2143enum { 1805enum {
2144 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ 1806 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
@@ -2146,7 +1808,7 @@ enum {
2146 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ 1808 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
2147 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ 1809 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
2148}; 1810};
2149 1811
2150/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1812/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
2151enum { 1813enum {
2152 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ 1814 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
@@ -2171,7 +1833,7 @@ enum {
2171 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ 1833 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
2172 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ 1834 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
2173}; 1835};
2174 1836
2175#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) 1837#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
2176#define DATA_BLIND_DEF 0x04 1838#define DATA_BLIND_DEF 0x04
2177 1839
@@ -2186,7 +1848,7 @@ enum {
2186 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ 1848 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
2187 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ 1849 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
2188}; 1850};
2189 1851
2190#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK) 1852#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
2191#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK) 1853#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
2192 1854
@@ -2195,7 +1857,7 @@ enum {
2195 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ 1857 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
2196 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ 1858 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
2197}; 1859};
2198 1860
2199/* Receive Frame Status Encoding */ 1861/* Receive Frame Status Encoding */
2200enum { 1862enum {
2201 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ 1863 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
@@ -2217,12 +1879,12 @@ enum {
2217/* 1879/*
2218 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) 1880 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
2219 */ 1881 */
2220 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR | 1882 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
2221 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | 1883 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
2222 GMR_FS_JABBER, 1884 GMR_FS_JABBER,
2223/* Rx GMAC FIFO Flush Mask (default) */ 1885/* Rx GMAC FIFO Flush Mask (default) */
2224 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR | 1886 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
2225 GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE | 1887 GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
2226 GMR_FS_JABBER, 1888 GMR_FS_JABBER,
2227}; 1889};
2228 1890
@@ -2540,10 +2202,6 @@ enum {
2540}; 2202};
2541 2203
2542 2204
2543/* XM_PHY_ADDR 16 bit r/w PHY Address Register */
2544#define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */
2545
2546
2547/* XM_GP_PORT 32 bit r/w General Purpose Port Register */ 2205/* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2548enum { 2206enum {
2549 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */ 2207 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
@@ -2662,8 +2320,8 @@ enum {
2662}; 2320};
2663 2321
2664#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I) 2322#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2665#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\ 2323#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2666 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA) 2324 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2667 2325
2668/* XM_STAT_CMD 16 bit r/w Statistics Command Register */ 2326/* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2669enum { 2327enum {
@@ -2793,28 +2451,20 @@ struct skge_hw {
2793 u32 intr_mask; 2451 u32 intr_mask;
2794 struct net_device *dev[2]; 2452 struct net_device *dev[2];
2795 2453
2796 u8 mac_cfg;
2797 u8 chip_id; 2454 u8 chip_id;
2455 u8 chip_rev;
2798 u8 phy_type; 2456 u8 phy_type;
2799 u8 pmd_type; 2457 u8 pmd_type;
2800 u16 phy_addr; 2458 u16 phy_addr;
2459 u8 ports;
2801 2460
2802 u32 ram_size; 2461 u32 ram_size;
2803 u32 ram_offset; 2462 u32 ram_offset;
2804 2463
2805 struct tasklet_struct ext_tasklet; 2464 struct tasklet_struct ext_tasklet;
2806 spinlock_t phy_lock; 2465 spinlock_t phy_lock;
2807}; 2466};
2808 2467
2809static inline int isdualport(const struct skge_hw *hw)
2810{
2811 return !(hw->mac_cfg & CFG_SNG_MAC);
2812}
2813
2814static inline u8 chip_rev(const struct skge_hw *hw)
2815{
2816 return (hw->mac_cfg & CFG_CHIP_R_MSK) >> 4;
2817}
2818 2468
2819static inline int iscopper(const struct skge_hw *hw) 2469static inline int iscopper(const struct skge_hw *hw)
2820{ 2470{
@@ -2827,7 +2477,7 @@ enum {
2827 FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */ 2477 FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */
2828 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */ 2478 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2829}; 2479};
2830 2480
2831struct skge_port { 2481struct skge_port {
2832 u32 msg_enable; 2482 u32 msg_enable;
2833 struct skge_hw *hw; 2483 struct skge_hw *hw;
@@ -2853,8 +2503,8 @@ struct skge_port {
2853 void *mem; /* PCI memory for rings */ 2503 void *mem; /* PCI memory for rings */
2854 dma_addr_t dma; 2504 dma_addr_t dma;
2855 unsigned long mem_size; 2505 unsigned long mem_size;
2506 unsigned int rx_buf_size;
2856 2507
2857 struct timer_list link_check;
2858 struct timer_list led_blink; 2508 struct timer_list led_blink;
2859}; 2509};
2860 2510
@@ -2863,7 +2513,6 @@ struct skge_port {
2863static inline u32 skge_read32(const struct skge_hw *hw, int reg) 2513static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2864{ 2514{
2865 return readl(hw->regs + reg); 2515 return readl(hw->regs + reg);
2866
2867} 2516}
2868 2517
2869static inline u16 skge_read16(const struct skge_hw *hw, int reg) 2518static inline u16 skge_read16(const struct skge_hw *hw, int reg)
@@ -2892,114 +2541,87 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2892} 2541}
2893 2542
2894/* MAC Related Registers inside the device. */ 2543/* MAC Related Registers inside the device. */
2895#define SKGEMAC_REG(port,reg) (((port)<<7)+(reg)) 2544#define SK_REG(port,reg) (((port)<<7)+(reg))
2896 2545#define SK_XMAC_REG(port, reg) \
2897/* PCI config space can be accessed via memory mapped space */
2898#define SKGEPCI_REG(reg) ((reg)+ 0x380)
2899
2900#define SKGEXM_REG(port, reg) \
2901 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1) 2546 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2902 2547
2903static inline u32 skge_xm_read32(const struct skge_hw *hw, int port, int reg) 2548static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2904{
2905 return skge_read32(hw, SKGEXM_REG(port,reg));
2906}
2907
2908static inline u16 skge_xm_read16(const struct skge_hw *hw, int port, int reg)
2909{ 2549{
2910 return skge_read16(hw, SKGEXM_REG(port,reg)); 2550 u32 v;
2551 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2552 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2553 return v;
2911} 2554}
2912 2555
2913static inline u8 skge_xm_read8(const struct skge_hw *hw, int port, int reg) 2556static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2914{ 2557{
2915 return skge_read8(hw, SKGEXM_REG(port,reg)); 2558 return skge_read16(hw, SK_XMAC_REG(port,reg));
2916} 2559}
2917 2560
2918static inline void skge_xm_write32(const struct skge_hw *hw, int port, int r, u32 v) 2561static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2919{ 2562{
2920 skge_write32(hw, SKGEXM_REG(port,r), v); 2563 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2564 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2921} 2565}
2922 2566
2923static inline void skge_xm_write16(const struct skge_hw *hw, int port, int r, u16 v) 2567static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2924{ 2568{
2925 skge_write16(hw, SKGEXM_REG(port,r), v); 2569 skge_write16(hw, SK_XMAC_REG(port,r), v);
2926} 2570}
2927 2571
2928static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8 v) 2572static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2929{
2930 skge_write8(hw, SKGEXM_REG(port,r), v);
2931}
2932
2933static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg,
2934 const u8 *hash) 2573 const u8 *hash)
2935{ 2574{
2936 skge_xm_write16(hw, port, reg, 2575 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2937 (u16)hash[0] | ((u16)hash[1] << 8)); 2576 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2938 skge_xm_write16(hw, port, reg+2, 2577 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2939 (u16)hash[2] | ((u16)hash[3] << 8)); 2578 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2940 skge_xm_write16(hw, port, reg+4,
2941 (u16)hash[4] | ((u16)hash[5] << 8));
2942 skge_xm_write16(hw, port, reg+6,
2943 (u16)hash[6] | ((u16)hash[7] << 8));
2944} 2579}
2945 2580
2946static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg, 2581static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2947 const u8 *addr) 2582 const u8 *addr)
2948{ 2583{
2949 skge_xm_write16(hw, port, reg, 2584 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2950 (u16)addr[0] | ((u16)addr[1] << 8)); 2585 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2951 skge_xm_write16(hw, port, reg, 2586 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2952 (u16)addr[2] | ((u16)addr[3] << 8));
2953 skge_xm_write16(hw, port, reg,
2954 (u16)addr[4] | ((u16)addr[5] << 8));
2955} 2587}
2956 2588
2589#define SK_GMAC_REG(port,reg) \
2590 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2957 2591
2958#define SKGEGMA_REG(port,reg) \ 2592static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2959 ((reg) + BASE_GMAC_1 + \
2960 (port) * (BASE_GMAC_2-BASE_GMAC_1))
2961
2962static inline u16 skge_gma_read16(const struct skge_hw *hw, int port, int reg)
2963{ 2593{
2964 return skge_read16(hw, SKGEGMA_REG(port,reg)); 2594 return skge_read16(hw, SK_GMAC_REG(port,reg));
2965} 2595}
2966 2596
2967static inline u32 skge_gma_read32(const struct skge_hw *hw, int port, int reg) 2597static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2968{ 2598{
2969 return (u32) skge_read16(hw, SKGEGMA_REG(port,reg)) 2599 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2970 | ((u32)skge_read16(hw, SKGEGMA_REG(port,reg+4)) << 16); 2600 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2971} 2601}
2972 2602
2973static inline u8 skge_gma_read8(const struct skge_hw *hw, int port, int reg) 2603static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2974{ 2604{
2975 return skge_read8(hw, SKGEGMA_REG(port,reg)); 2605 skge_write16(hw, SK_GMAC_REG(port,r), v);
2976} 2606}
2977 2607
2978static inline void skge_gma_write16(const struct skge_hw *hw, int port, int r, u16 v) 2608static inline void gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
2979{ 2609{
2980 skge_write16(hw, SKGEGMA_REG(port,r), v); 2610 skge_write16(hw, SK_GMAC_REG(port, r), (u16) v);
2611 skge_write32(hw, SK_GMAC_REG(port, r+4), (u16)(v >> 16));
2981} 2612}
2982 2613
2983static inline void skge_gma_write32(const struct skge_hw *hw, int port, int r, u32 v) 2614static inline void gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
2984{ 2615{
2985 skge_write16(hw, SKGEGMA_REG(port, r), (u16) v); 2616 skge_write8(hw, SK_GMAC_REG(port,r), v);
2986 skge_write32(hw, SKGEGMA_REG(port, r+4), (u16)(v >> 16));
2987} 2617}
2988 2618
2989static inline void skge_gma_write8(const struct skge_hw *hw, int port, int r, u8 v) 2619static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2990{
2991 skge_write8(hw, SKGEGMA_REG(port,r), v);
2992}
2993
2994static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg,
2995 const u8 *addr) 2620 const u8 *addr)
2996{ 2621{
2997 skge_gma_write16(hw, port, reg, 2622 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2998 (u16) addr[0] | ((u16) addr[1] << 8)); 2623 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2999 skge_gma_write16(hw, port, reg+4, 2624 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
3000 (u16) addr[2] | ((u16) addr[3] << 8));
3001 skge_gma_write16(hw, port, reg+8,
3002 (u16) addr[4] | ((u16) addr[5] << 8));
3003} 2625}
3004 2626
3005#endif 2627#endif
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index fd80048f7f7a..cfb9d3cdb04a 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -315,15 +315,25 @@ static void smc_reset(struct net_device *dev)
315 struct smc_local *lp = netdev_priv(dev); 315 struct smc_local *lp = netdev_priv(dev);
316 void __iomem *ioaddr = lp->base; 316 void __iomem *ioaddr = lp->base;
317 unsigned int ctl, cfg; 317 unsigned int ctl, cfg;
318 struct sk_buff *pending_skb;
318 319
319 DBG(2, "%s: %s\n", dev->name, __FUNCTION__); 320 DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
320 321
321 /* Disable all interrupts */ 322 /* Disable all interrupts, block TX tasklet */
322 spin_lock(&lp->lock); 323 spin_lock(&lp->lock);
323 SMC_SELECT_BANK(2); 324 SMC_SELECT_BANK(2);
324 SMC_SET_INT_MASK(0); 325 SMC_SET_INT_MASK(0);
326 pending_skb = lp->pending_tx_skb;
327 lp->pending_tx_skb = NULL;
325 spin_unlock(&lp->lock); 328 spin_unlock(&lp->lock);
326 329
330 /* free any pending tx skb */
331 if (pending_skb) {
332 dev_kfree_skb(pending_skb);
333 lp->stats.tx_errors++;
334 lp->stats.tx_aborted_errors++;
335 }
336
327 /* 337 /*
328 * This resets the registers mostly to defaults, but doesn't 338 * This resets the registers mostly to defaults, but doesn't
329 * affect EEPROM. That seems unnecessary 339 * affect EEPROM. That seems unnecessary
@@ -389,14 +399,6 @@ static void smc_reset(struct net_device *dev)
389 SMC_SELECT_BANK(2); 399 SMC_SELECT_BANK(2);
390 SMC_SET_MMU_CMD(MC_RESET); 400 SMC_SET_MMU_CMD(MC_RESET);
391 SMC_WAIT_MMU_BUSY(); 401 SMC_WAIT_MMU_BUSY();
392
393 /* clear anything saved */
394 if (lp->pending_tx_skb != NULL) {
395 dev_kfree_skb (lp->pending_tx_skb);
396 lp->pending_tx_skb = NULL;
397 lp->stats.tx_errors++;
398 lp->stats.tx_aborted_errors++;
399 }
400} 402}
401 403
402/* 404/*
@@ -440,6 +442,7 @@ static void smc_shutdown(struct net_device *dev)
440{ 442{
441 struct smc_local *lp = netdev_priv(dev); 443 struct smc_local *lp = netdev_priv(dev);
442 void __iomem *ioaddr = lp->base; 444 void __iomem *ioaddr = lp->base;
445 struct sk_buff *pending_skb;
443 446
444 DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); 447 DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
445 448
@@ -447,7 +450,11 @@ static void smc_shutdown(struct net_device *dev)
447 spin_lock(&lp->lock); 450 spin_lock(&lp->lock);
448 SMC_SELECT_BANK(2); 451 SMC_SELECT_BANK(2);
449 SMC_SET_INT_MASK(0); 452 SMC_SET_INT_MASK(0);
453 pending_skb = lp->pending_tx_skb;
454 lp->pending_tx_skb = NULL;
450 spin_unlock(&lp->lock); 455 spin_unlock(&lp->lock);
456 if (pending_skb)
457 dev_kfree_skb(pending_skb);
451 458
452 /* and tell the card to stay away from that nasty outside world */ 459 /* and tell the card to stay away from that nasty outside world */
453 SMC_SELECT_BANK(0); 460 SMC_SELECT_BANK(0);
@@ -627,7 +634,12 @@ static void smc_hardware_send_pkt(unsigned long data)
627 } 634 }
628 635
629 skb = lp->pending_tx_skb; 636 skb = lp->pending_tx_skb;
637 if (unlikely(!skb)) {
638 smc_special_unlock(&lp->lock);
639 return;
640 }
630 lp->pending_tx_skb = NULL; 641 lp->pending_tx_skb = NULL;
642
631 packet_no = SMC_GET_AR(); 643 packet_no = SMC_GET_AR();
632 if (unlikely(packet_no & AR_FAILED)) { 644 if (unlikely(packet_no & AR_FAILED)) {
633 printk("%s: Memory allocation failed.\n", dev->name); 645 printk("%s: Memory allocation failed.\n", dev->name);
@@ -702,7 +714,6 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
702 DBG(3, "%s: %s\n", dev->name, __FUNCTION__); 714 DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
703 715
704 BUG_ON(lp->pending_tx_skb != NULL); 716 BUG_ON(lp->pending_tx_skb != NULL);
705 lp->pending_tx_skb = skb;
706 717
707 /* 718 /*
708 * The MMU wants the number of pages to be the number of 256 bytes 719 * The MMU wants the number of pages to be the number of 256 bytes
@@ -718,7 +729,6 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
718 numPages = ((skb->len & ~1) + (6 - 1)) >> 8; 729 numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
719 if (unlikely(numPages > 7)) { 730 if (unlikely(numPages > 7)) {
720 printk("%s: Far too big packet error.\n", dev->name); 731 printk("%s: Far too big packet error.\n", dev->name);
721 lp->pending_tx_skb = NULL;
722 lp->stats.tx_errors++; 732 lp->stats.tx_errors++;
723 lp->stats.tx_dropped++; 733 lp->stats.tx_dropped++;
724 dev_kfree_skb(skb); 734 dev_kfree_skb(skb);
@@ -745,6 +755,7 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
745 755
746 smc_special_unlock(&lp->lock); 756 smc_special_unlock(&lp->lock);
747 757
758 lp->pending_tx_skb = skb;
748 if (!poll_count) { 759 if (!poll_count) {
749 /* oh well, wait until the chip finds memory later */ 760 /* oh well, wait until the chip finds memory later */
750 netif_stop_queue(dev); 761 netif_stop_queue(dev);
@@ -1062,7 +1073,7 @@ static void smc_phy_powerdown(struct net_device *dev)
1062 above). linkwatch_event() also wants the netlink semaphore. 1073 above). linkwatch_event() also wants the netlink semaphore.
1063 */ 1074 */
1064 while(lp->work_pending) 1075 while(lp->work_pending)
1065 schedule(); 1076 yield();
1066 1077
1067 bmcr = smc_phy_read(dev, phy, MII_BMCR); 1078 bmcr = smc_phy_read(dev, phy, MII_BMCR);
1068 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); 1079 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
@@ -1606,14 +1617,8 @@ static int smc_close(struct net_device *dev)
1606 1617
1607 /* clear everything */ 1618 /* clear everything */
1608 smc_shutdown(dev); 1619 smc_shutdown(dev);
1609 1620 tasklet_kill(&lp->tx_task);
1610 smc_phy_powerdown(dev); 1621 smc_phy_powerdown(dev);
1611
1612 if (lp->pending_tx_skb) {
1613 dev_kfree_skb(lp->pending_tx_skb);
1614 lp->pending_tx_skb = NULL;
1615 }
1616
1617 return 0; 1622 return 0;
1618} 1623}
1619 1624
diff --git a/drivers/net/tokenring/lanstreamer.c b/drivers/net/tokenring/lanstreamer.c
index 6e5ade99a38f..97712c3c4e07 100644
--- a/drivers/net/tokenring/lanstreamer.c
+++ b/drivers/net/tokenring/lanstreamer.c
@@ -455,8 +455,7 @@ static int streamer_reset(struct net_device *dev)
455 writew(readw(streamer_mmio + BCTL) | BCTL_SOFTRESET, streamer_mmio + BCTL); 455 writew(readw(streamer_mmio + BCTL) | BCTL_SOFTRESET, streamer_mmio + BCTL);
456 t = jiffies; 456 t = jiffies;
457 /* Hold soft reset bit for a while */ 457 /* Hold soft reset bit for a while */
458 current->state = TASK_UNINTERRUPTIBLE; 458 ssleep(1);
459 schedule_timeout(HZ);
460 459
461 writew(readw(streamer_mmio + BCTL) & ~BCTL_SOFTRESET, 460 writew(readw(streamer_mmio + BCTL) & ~BCTL_SOFTRESET,
462 streamer_mmio + BCTL); 461 streamer_mmio + BCTL);
@@ -512,8 +511,7 @@ static int streamer_reset(struct net_device *dev)
512 writew(SISR_MI, streamer_mmio + SISR_MASK_SUM); 511 writew(SISR_MI, streamer_mmio + SISR_MASK_SUM);
513 512
514 while (!((readw(streamer_mmio + SISR)) & SISR_SRB_REPLY)) { 513 while (!((readw(streamer_mmio + SISR)) & SISR_SRB_REPLY)) {
515 current->state = TASK_INTERRUPTIBLE; 514 msleep_interruptible(100);
516 schedule_timeout(HZ/10);
517 if (jiffies - t > 40 * HZ) { 515 if (jiffies - t > 40 * HZ) {
518 printk(KERN_ERR 516 printk(KERN_ERR
519 "IBM PCI tokenring card not responding\n"); 517 "IBM PCI tokenring card not responding\n");
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index cfc346e72d62..08e0f80f89d5 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -242,6 +242,7 @@ static struct pci_device_id tulip_pci_tbl[] = {
242 { 0x10b9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */ 242 { 0x10b9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
243 { 0x10b9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */ 243 { 0x10b9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
244 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */ 244 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
245 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
245 { } /* terminate list */ 246 { } /* terminate list */
246}; 247};
247MODULE_DEVICE_TABLE(pci, tulip_pci_tbl); 248MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
@@ -1756,11 +1757,19 @@ static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1756{ 1757{
1757 struct net_device *dev = pci_get_drvdata(pdev); 1758 struct net_device *dev = pci_get_drvdata(pdev);
1758 1759
1759 if (dev && netif_running (dev) && netif_device_present (dev)) { 1760 if (!dev)
1760 netif_device_detach (dev); 1761 return -EINVAL;
1761 tulip_down (dev); 1762
1762 /* pci_power_off(pdev, -1); */ 1763 if (netif_running(dev))
1763 } 1764 tulip_down(dev);
1765
1766 netif_device_detach(dev);
1767 free_irq(dev->irq, dev);
1768
1769 pci_save_state(pdev);
1770 pci_disable_device(pdev);
1771 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1772
1764 return 0; 1773 return 0;
1765} 1774}
1766 1775
@@ -1768,15 +1777,26 @@ static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1768static int tulip_resume(struct pci_dev *pdev) 1777static int tulip_resume(struct pci_dev *pdev)
1769{ 1778{
1770 struct net_device *dev = pci_get_drvdata(pdev); 1779 struct net_device *dev = pci_get_drvdata(pdev);
1780 int retval;
1771 1781
1772 if (dev && netif_running (dev) && !netif_device_present (dev)) { 1782 if (!dev)
1773#if 1 1783 return -EINVAL;
1774 pci_enable_device (pdev); 1784
1775#endif 1785 pci_set_power_state(pdev, PCI_D0);
1776 /* pci_power_on(pdev); */ 1786 pci_restore_state(pdev);
1777 tulip_up (dev); 1787
1778 netif_device_attach (dev); 1788 pci_enable_device(pdev);
1789
1790 if ((retval = request_irq(dev->irq, &tulip_interrupt, SA_SHIRQ, dev->name, dev))) {
1791 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1792 return retval;
1779 } 1793 }
1794
1795 netif_device_attach(dev);
1796
1797 if (netif_running(dev))
1798 tulip_up(dev);
1799
1780 return 0; 1800 return 0;
1781} 1801}
1782 1802
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c
index 6200cfc4244e..be1c1047b9ba 100644
--- a/drivers/net/via-rhine.c
+++ b/drivers/net/via-rhine.c
@@ -1398,7 +1398,7 @@ static void rhine_tx(struct net_device *dev)
1398 while (rp->dirty_tx != rp->cur_tx) { 1398 while (rp->dirty_tx != rp->cur_tx) {
1399 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status); 1399 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1400 if (debug > 6) 1400 if (debug > 6)
1401 printk(KERN_DEBUG " Tx scavenge %d status %8.8x.\n", 1401 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
1402 entry, txstatus); 1402 entry, txstatus);
1403 if (txstatus & DescOwn) 1403 if (txstatus & DescOwn)
1404 break; 1404 break;
@@ -1469,7 +1469,7 @@ static void rhine_rx(struct net_device *dev)
1469 int data_size = desc_status >> 16; 1469 int data_size = desc_status >> 16;
1470 1470
1471 if (debug > 4) 1471 if (debug > 4)
1472 printk(KERN_DEBUG " rhine_rx() status is %8.8x.\n", 1472 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
1473 desc_status); 1473 desc_status);
1474 if (--boguscnt < 0) 1474 if (--boguscnt < 0)
1475 break; 1475 break;
@@ -1487,7 +1487,7 @@ static void rhine_rx(struct net_device *dev)
1487 } else if (desc_status & RxErr) { 1487 } else if (desc_status & RxErr) {
1488 /* There was a error. */ 1488 /* There was a error. */
1489 if (debug > 2) 1489 if (debug > 2)
1490 printk(KERN_DEBUG " rhine_rx() Rx " 1490 printk(KERN_DEBUG "rhine_rx() Rx "
1491 "error was %8.8x.\n", 1491 "error was %8.8x.\n",
1492 desc_status); 1492 desc_status);
1493 rp->stats.rx_errors++; 1493 rp->stats.rx_errors++;
diff --git a/drivers/net/wan/farsync.c b/drivers/net/wan/farsync.c
index 7575b799ce53..7217d44e8854 100644
--- a/drivers/net/wan/farsync.c
+++ b/drivers/net/wan/farsync.c
@@ -981,6 +981,7 @@ fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
981 /* Wait for any previous command to complete */ 981 /* Wait for any previous command to complete */
982 while (mbval > NAK) { 982 while (mbval > NAK) {
983 spin_unlock_irqrestore(&card->card_lock, flags); 983 spin_unlock_irqrestore(&card->card_lock, flags);
984 set_current_state(TASK_UNINTERRUPTIBLE);
984 schedule_timeout(1); 985 schedule_timeout(1);
985 spin_lock_irqsave(&card->card_lock, flags); 986 spin_lock_irqsave(&card->card_lock, flags);
986 987
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index 943be6baaad9..758b48ba65ce 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -900,7 +900,7 @@ typedef struct aironet_ioctl {
900 unsigned char __user *data; // d-data 900 unsigned char __user *data; // d-data
901} aironet_ioctl; 901} aironet_ioctl;
902 902
903static char *swversion = "2.1"; 903static char swversion[] = "2.1";
904#endif /* CISCO_EXT */ 904#endif /* CISCO_EXT */
905 905
906#define NUM_MODULES 2 906#define NUM_MODULES 2
diff --git a/drivers/net/wireless/orinoco.c b/drivers/net/wireless/orinoco.c
index a57187391f81..4d0b5a336bd7 100644
--- a/drivers/net/wireless/orinoco.c
+++ b/drivers/net/wireless/orinoco.c
@@ -46,382 +46,9 @@
46 * under either the MPL or the GPL. */ 46 * under either the MPL or the GPL. */
47 47
48/* 48/*
49 * v0.01 -> v0.02 - 21/3/2001 - Jean II
50 * o Allow to use regular ethX device name instead of dldwdX
51 * o Warning on IBSS with ESSID=any for firmware 6.06
52 * o Put proper range.throughput values (optimistic)
53 * o IWSPY support (IOCTL and stat gather in Rx path)
54 * o Allow setting frequency in Ad-Hoc mode
55 * o Disable WEP setting if !has_wep to work on old firmware
56 * o Fix txpower range
57 * o Start adding support for Samsung/Compaq firmware
58 *
59 * v0.02 -> v0.03 - 23/3/2001 - Jean II
60 * o Start adding Symbol support - need to check all that
61 * o Fix Prism2/Symbol WEP to accept 128 bits keys
62 * o Add Symbol WEP (add authentication type)
63 * o Add Prism2/Symbol rate
64 * o Add PM timeout (holdover duration)
65 * o Enable "iwconfig eth0 key off" and friends (toggle flags)
66 * o Enable "iwconfig eth0 power unicast/all" (toggle flags)
67 * o Try with an Intel card. It report firmware 1.01, behave like
68 * an antiquated firmware, however on windows it says 2.00. Yuck !
69 * o Workaround firmware bug in allocate buffer (Intel 1.01)
70 * o Finish external renaming to orinoco...
71 * o Testing with various Wavelan firmwares
72 *
73 * v0.03 -> v0.04 - 30/3/2001 - Jean II
74 * o Update to Wireless 11 -> add retry limit/lifetime support
75 * o Tested with a D-Link DWL 650 card, fill in firmware support
76 * o Warning on Vcc mismatch (D-Link 3.3v card in Lucent 5v only slot)
77 * o Fixed the Prism2 WEP bugs that I introduced in v0.03 :-(
78 * It works on D-Link *only* after a tcpdump. Weird...
79 * And still doesn't work on Intel card. Grrrr...
80 * o Update the mode after a setport3
81 * o Add preamble setting for Symbol cards (not yet enabled)
82 * o Don't complain as much about Symbol cards...
83 *
84 * v0.04 -> v0.04b - 22/4/2001 - David Gibson
85 * o Removed the 'eth' parameter - always use ethXX as the
86 * interface name instead of dldwdXX. The other was racy
87 * anyway.
88 * o Clean up RID definitions in hermes.h, other cleanups
89 *
90 * v0.04b -> v0.04c - 24/4/2001 - Jean II
91 * o Tim Hurley <timster AT seiki.bliztech.com> reported a D-Link card
92 * with vendor 02 and firmware 0.08. Added in the capabilities...
93 * o Tested Lucent firmware 7.28, everything works...
94 *
95 * v0.04c -> v0.05 - 3/5/2001 - Benjamin Herrenschmidt
96 * o Spin-off Pcmcia code. This file is renamed orinoco.c,
97 * and orinoco_cs.c now contains only the Pcmcia specific stuff
98 * o Add Airport driver support on top of orinoco.c (see airport.c)
99 *
100 * v0.05 -> v0.05a - 4/5/2001 - Jean II
101 * o Revert to old Pcmcia code to fix breakage of Ben's changes...
102 *
103 * v0.05a -> v0.05b - 4/5/2001 - Jean II
104 * o add module parameter 'ignore_cis_vcc' for D-Link @ 5V
105 * o D-Link firmware doesn't support multicast. We just print a few
106 * error messages, but otherwise everything works...
107 * o For David : set/getport3 works fine, just upgrade iwpriv...
108 *
109 * v0.05b -> v0.05c - 5/5/2001 - Benjamin Herrenschmidt
110 * o Adapt airport.c to latest changes in orinoco.c
111 * o Remove deferred power enabling code
112 *
113 * v0.05c -> v0.05d - 5/5/2001 - Jean II
114 * o Workaround to SNAP decapsulate frame from Linksys AP
115 * original patch from : Dong Liu <dliu AT research.bell-labs.com>
116 * (note : the memcmp bug was mine - fixed)
117 * o Remove set_retry stuff, no firmware support it (bloat--).
118 *
119 * v0.05d -> v0.06 - 25/5/2001 - Jean II
120 * Original patch from "Hong Lin" <alin AT redhat.com>,
121 * "Ian Kinner" <ikinner AT redhat.com>
122 * and "David Smith" <dsmith AT redhat.com>
123 * o Init of priv->tx_rate_ctrl in firmware specific section.
124 * o Prism2/Symbol rate, upto should be 0xF and not 0x15. Doh !
125 * o Spectrum card always need cor_reset (for every reset)
126 * o Fix cor_reset to not lose bit 7 in the register
127 * o flush_stale_links to remove zombie Pcmcia instances
128 * o Ack previous hermes event before reset
129 * Me (with my little hands)
130 * o Allow orinoco.c to call cor_reset via priv->card_reset_handler
131 * o Add priv->need_card_reset to toggle this feature
132 * o Fix various buglets when setting WEP in Symbol firmware
133 * Now, encryption is fully functional on Symbol cards. Youpi !
134 *
135 * v0.06 -> v0.06b - 25/5/2001 - Jean II
136 * o IBSS on Symbol use port_mode = 4. Please don't ask...
137 *
138 * v0.06b -> v0.06c - 29/5/2001 - Jean II
139 * o Show first spy address in /proc/net/wireless for IBSS mode as well
140 *
141 * v0.06c -> v0.06d - 6/7/2001 - David Gibson
142 * o Change a bunch of KERN_INFO messages to KERN_DEBUG, as per Linus'
143 * wishes to reduce the number of unnecessary messages.
144 * o Removed bogus message on CRC error.
145 * o Merged fixes for v0.08 Prism 2 firmware from William Waghorn
146 * <willwaghorn AT yahoo.co.uk>
147 * o Slight cleanup/re-arrangement of firmware detection code.
148 *
149 * v0.06d -> v0.06e - 1/8/2001 - David Gibson
150 * o Removed some redundant global initializers (orinoco_cs.c).
151 * o Added some module metadata
152 *
153 * v0.06e -> v0.06f - 14/8/2001 - David Gibson
154 * o Wording fix to license
155 * o Added a 'use_alternate_encaps' module parameter for APs which need an
156 * oui of 00:00:00. We really need a better way of handling this, but
157 * the module flag is better than nothing for now.
158 *
159 * v0.06f -> v0.07 - 20/8/2001 - David Gibson
160 * o Removed BAP error retries from hermes_bap_seek(). For Tx we now
161 * let the upper layers handle the retry, we retry explicitly in the
162 * Rx path, but don't make as much noise about it.
163 * o Firmware detection cleanups.
164 *
165 * v0.07 -> v0.07a - 1/10/3001 - Jean II
166 * o Add code to read Symbol firmware revision, inspired by latest code
167 * in Spectrum24 by Lee John Keyser-Allen - Thanks Lee !
168 * o Thanks to Jared Valentine <hidden AT xmission.com> for "providing" me
169 * a 3Com card with a recent firmware, fill out Symbol firmware
170 * capabilities of latest rev (2.20), as well as older Symbol cards.
171 * o Disable Power Management in newer Symbol firmware, the API
172 * has changed (documentation needed).
173 *
174 * v0.07a -> v0.08 - 3/10/2001 - David Gibson
175 * o Fixed a possible buffer overrun found by the Stanford checker (in
176 * dldwd_ioctl_setiwencode()). Can only be called by root anyway, so not
177 * a big problem.
178 * o Turned has_big_wep on for Intersil cards. That's not true for all of
179 * them but we should at least let the capable ones try.
180 * o Wait for BUSY to clear at the beginning of hermes_bap_seek(). I
181 * realized that my assumption that the driver's serialization
182 * would prevent the BAP being busy on entry was possibly false, because
183 * things other than seeks may make the BAP busy.
184 * o Use "alternate" (oui 00:00:00) encapsulation by default.
185 * Setting use_old_encaps will mimic the old behaviour, but I think we
186 * will be able to eliminate this.
187 * o Don't try to make __initdata const (the version string). This can't
188 * work because of the way the __initdata sectioning works.
189 * o Added MODULE_LICENSE tags.
190 * o Support for PLX (transparent PCMCIA->PCI bridge) cards.
191 * o Changed to using the new type-fascist min/max.
192 *
193 * v0.08 -> v0.08a - 9/10/2001 - David Gibson
194 * o Inserted some missing acknowledgements/info into the Changelog.
195 * o Fixed some bugs in the normalization of signal level reporting.
196 * o Fixed bad bug in WEP key handling on Intersil and Symbol firmware,
197 * which led to an instant crash on big-endian machines.
198 *
199 * v0.08a -> v0.08b - 20/11/2001 - David Gibson
200 * o Lots of cleanup and bugfixes in orinoco_plx.c
201 * o Cleanup to handling of Tx rate setting.
202 * o Removed support for old encapsulation method.
203 * o Removed old "dldwd" names.
204 * o Split RID constants into a new file hermes_rid.h
205 * o Renamed RID constants to match linux-wlan-ng and prism2.o
206 * o Bugfixes in hermes.c
207 * o Poke the PLX's INTCSR register, so it actually starts
208 * generating interrupts. These cards might actually work now.
209 * o Update to wireless extensions v12 (Jean II)
210 * o Support for tallies and inquire command (Jean II)
211 * o Airport updates for newer PPC kernels (BenH)
212 *
213 * v0.08b -> v0.09 - 21/12/2001 - David Gibson
214 * o Some new PCI IDs for PLX cards.
215 * o Removed broken attempt to do ALLMULTI reception. Just use
216 * promiscuous mode instead
217 * o Preliminary work for list-AP (Jean II)
218 * o Airport updates from (BenH)
219 * o Eliminated racy hw_ready stuff
220 * o Fixed generation of fake events in irq handler. This should
221 * finally kill the EIO problems (Jean II & dgibson)
222 * o Fixed breakage of bitrate set/get on Agere firmware (Jean II)
223 *
224 * v0.09 -> v0.09a - 2/1/2002 - David Gibson
225 * o Fixed stupid mistake in multicast list handling, triggering
226 * a BUG()
227 *
228 * v0.09a -> v0.09b - 16/1/2002 - David Gibson
229 * o Fixed even stupider mistake in new interrupt handling, which
230 * seriously broke things on big-endian machines.
231 * o Removed a bunch of redundant includes and exports.
232 * o Removed a redundant MOD_{INC,DEC}_USE_COUNT pair in airport.c
233 * o Don't attempt to do hardware level multicast reception on
234 * Intersil firmware, just go promisc instead.
235 * o Typo fixed in hermes_issue_cmd()
236 * o Eliminated WIRELESS_SPY #ifdefs
237 * o Status code reported on Tx exceptions
238 * o Moved netif_wake_queue() from ALLOC interrupts to TX and TXEXC
239 * interrupts, which should fix the timeouts we're seeing.
240 *
241 * v0.09b -> v0.10 - 25 Feb 2002 - David Gibson
242 * o Removed nested structures used for header parsing, so the
243 * driver should now work without hackery on ARM
244 * o Fix for WEP handling on Intersil (Hawk Newton)
245 * o Eliminated the /proc/hermes/ethXX/regs debugging file. It
246 * was never very useful.
247 * o Make Rx errors less noisy.
248 *
249 * v0.10 -> v0.11 - 5 Apr 2002 - David Gibson
250 * o Laid the groundwork in hermes.[ch] for devices which map
251 * into PCI memory space rather than IO space.
252 * o Fixed bug in multicast handling (cleared multicast list when
253 * leaving promiscuous mode).
254 * o Relegated Tx error messages to debug.
255 * o Cleaned up / corrected handling of allocation lengths.
256 * o Set OWNSSID in IBSS mode for WinXP interoperability (jimc).
257 * o Change to using alloc_etherdev() for structure allocations.
258 * o Check for and drop undersized packets.
259 * o Fixed a race in stopping/waking the queue. This should fix
260 * the timeout problems (Pavel Roskin)
261 * o Reverted to netif_wake_queue() on the ALLOC event.
262 * o Fixes for recent Symbol firmwares which lack AP density
263 * (Pavel Roskin).
264 *
265 * v0.11 -> v0.11a - 29 Apr 2002 - David Gibson
266 * o Handle different register spacing, necessary for Prism 2.5
267 * PCI adaptors (Steve Hill).
268 * o Cleaned up initialization of card structures in orinoco_cs
269 * and airport. Removed card->priv field.
270 * o Make response structure optional for hermes_docmd_wait()
271 * Pavel Roskin)
272 * o Added PCI id for Nortel emobility to orinoco_plx.c.
273 * o Cleanup to handling of Symbol's allocation bug. (Pavel Roskin)
274 * o Cleanups to firmware capability detection.
275 * o Arrange for orinoco_pci.c to override firmware detection.
276 * We should be able to support the PCI Intersil cards now.
277 * o Cleanup handling of reset_cor and hard_reset (Pavel Roskin).
278 * o Remove erroneous use of USER_BAP in the TxExc handler (Jouni
279 * Malinen).
280 * o Makefile changes for better integration into David Hinds
281 * pcmcia-cs package.
282 *
283 * v0.11a -> v0.11b - 1 May 2002 - David Gibson
284 * o Better error reporting in orinoco_plx_init_one()
285 * o Fixed multiple bad kfree() bugs introduced by the
286 * alloc_orinocodev() changes.
287 *
288 * v0.11b -> v0.12 - 19 Jun 2002 - David Gibson
289 * o Support changing the MAC address.
290 * o Correct display of Intersil firmware revision numbers.
291 * o Entirely revised locking scheme. Should be both simpler and
292 * better.
293 * o Merged some common code in orinoco_plx, orinoco_pci and
294 * airport by creating orinoco_default_{open,stop,reset}()
295 * which are used as the dev->open, dev->stop, priv->reset
296 * callbacks if none are specified when alloc_orinocodev() is
297 * called.
298 * o Removed orinoco_plx_interrupt() and orinoco_pci_interrupt().
299 * They didn't do anything.
300 *
301 * v0.12 -> v0.12a - 4 Jul 2002 - David Gibson
302 * o Some rearrangement of code.
303 * o Numerous fixups to locking and rest handling, particularly
304 * for PCMCIA.
305 * o This allows open and stop net_device methods to be in
306 * orinoco.c now, rather than in the init modules.
307 * o In orinoco_cs.c link->priv now points to the struct
308 * net_device not to the struct orinoco_private.
309 * o Added a check for undersized SNAP frames, which could cause
310 * crashes.
311 *
312 * v0.12a -> v0.12b - 11 Jul 2002 - David Gibson
313 * o Fix hw->num_init testing code, so num_init is actually
314 * incremented.
315 * o Fix very stupid bug in orinoco_cs which broke compile with
316 * CONFIG_SMP.
317 * o Squashed a warning.
318 *
319 * v0.12b -> v0.12c - 26 Jul 2002 - David Gibson
320 * o Change to C9X style designated initializers.
321 * o Add support for 3Com AirConnect PCI.
322 * o No longer ignore the hard_reset argument to
323 * alloc_orinocodev(). Oops.
324 *
325 * v0.12c -> v0.13beta1 - 13 Sep 2002 - David Gibson
326 * o Revert the broken 0.12* locking scheme and go to a new yet
327 * simpler scheme.
328 * o Do firmware resets only in orinoco_init() and when waking
329 * the card from hard sleep.
330 *
331 * v0.13beta1 -> v0.13 - 27 Sep 2002 - David Gibson
332 * o Re-introduced full resets (via schedule_task()) on Tx
333 * timeout.
334 *
335 * v0.13 -> v0.13a - 30 Sep 2002 - David Gibson
336 * o Minor cleanups to info frame handling. Add basic support
337 * for linkstatus info frames.
338 * o Include required kernel headers in orinoco.h, to avoid
339 * compile problems.
340 *
341 * v0.13a -> v0.13b - 10 Feb 2003 - David Gibson
342 * o Implemented hard reset for Airport cards
343 * o Experimental suspend/resume implementation for orinoco_pci
344 * o Abolished /proc debugging support, replaced with a debugging
345 * iwpriv. Now it's ugly and simple instead of ugly and complex.
346 * o Bugfix in hermes.c if the firmware returned a record length
347 * of 0, we could go clobbering memory.
348 * o Bugfix in orinoco_stop() - it used to fail if hw_unavailable
349 * was set, which was usually true on PCMCIA hot removes.
350 * o Track LINKSTATUS messages, silently drop Tx packets before
351 * we are connected (avoids confusing the firmware), and only
352 * give LINKSTATUS printk()s if the status has changed.
353 *
354 * v0.13b -> v0.13c - 11 Mar 2003 - David Gibson
355 * o Cleanup: use dev instead of priv in various places.
356 * o Bug fix: Don't ReleaseConfiguration on RESET_PHYSICAL event
357 * if we're in the middle of a (driver initiated) hard reset.
358 * o Bug fix: ETH_ZLEN is supposed to include the header
359 * (Dionysus Blazakis & Manish Karir)
360 * o Convert to using workqueues instead of taskqueues (and
361 * backwards compatibility macros for pre 2.5.41 kernels).
362 * o Drop redundant (I think...) MOD_{INC,DEC}_USE_COUNT in
363 * airport.c
364 * o New orinoco_tmd.c init module from Joerg Dorchain for
365 * TMD7160 based PCI to PCMCIA bridges (similar to
366 * orinoco_plx.c).
367 *
368 * v0.13c -> v0.13d - 22 Apr 2003 - David Gibson
369 * o Make hw_unavailable a counter, rather than just a flag, this
370 * is necessary to avoid some races (such as a card being
371 * removed in the middle of orinoco_reset().
372 * o Restore Release/RequestConfiguration in the PCMCIA event handler
373 * when dealing with a driver initiated hard reset. This is
374 * necessary to prevent hangs due to a spurious interrupt while
375 * the reset is in progress.
376 * o Clear the 802.11 header when transmitting, even though we
377 * don't use it. This fixes a long standing bug on some
378 * firmwares, which seem to get confused if that isn't done.
379 * o Be less eager to de-encapsulate SNAP frames, only do so if
380 * the OUI is 00:00:00 or 00:00:f8, leave others alone. The old
381 * behaviour broke CDP (Cisco Discovery Protocol).
382 * o Use dev instead of priv for free_irq() as well as
383 * request_irq() (oops).
384 * o Attempt to reset rather than giving up if we get too many
385 * IRQs.
386 * o Changed semantics of __orinoco_down() so it can be called
387 * safely with hw_unavailable set. It also now clears the
388 * linkstatus (since we're going to have to reassociate).
389 *
390 * v0.13d -> v0.13e - 12 May 2003 - David Gibson
391 * o Support for post-2.5.68 return values from irq handler.
392 * o Fixed bug where underlength packets would be double counted
393 * in the rx_dropped statistics.
394 * o Provided a module parameter to suppress linkstatus messages.
395 *
396 * v0.13e -> v0.14alpha1 - 30 Sep 2003 - David Gibson
397 * o Replaced priv->connected logic with netif_carrier_on/off()
398 * calls.
399 * o Remove has_ibss_any and never set the CREATEIBSS RID when
400 * the ESSID is empty. Too many firmwares break if we do.
401 * o 2.6 merges: Replace pdev->slot_name with pci_name(), remove
402 * __devinitdata from PCI ID tables, use free_netdev().
403 * o Enabled shared-key authentication for Agere firmware (from
404 * Robert J. Moore <Robert.J.Moore AT allanbank.com>
405 * o Move netif_wake_queue() (back) to the Tx completion from the
406 * ALLOC event. This seems to prevent/mitigate the rolling
407 * error -110 problems at least on some Intersil firmwares.
408 * Theoretically reduces performance, but I can't measure it.
409 * Patch from Andrew Tridgell <tridge AT samba.org>
410 *
411 * v0.14alpha1 -> v0.14alpha2 - 20 Oct 2003 - David Gibson
412 * o Correctly turn off shared-key authentication when requested
413 * (bugfix from Robert J. Moore).
414 * o Correct airport sleep interfaces for current 2.6 kernels.
415 * o Add code for key change without disabling/enabling the MAC
416 * port. This is supposed to allow 802.1x to work sanely, but
417 * doesn't seem to yet.
418 *
419 * TODO 49 * TODO
420 * o New wireless extensions API (patch from Moustafa
421 * Youssef, updated by Jim Carter and Pavel Roskin).
422 * o Handle de-encapsulation within network layer, provide 802.11 50 * o Handle de-encapsulation within network layer, provide 802.11
423 * headers (patch from Thomas 'Dent' Mirlacher) 51 * headers (patch from Thomas 'Dent' Mirlacher)
424 * o RF monitor mode support
425 * o Fix possible races in SPY handling. 52 * o Fix possible races in SPY handling.
426 * o Disconnect wireless extensions from fundamental configuration. 53 * o Disconnect wireless extensions from fundamental configuration.
427 * o (maybe) Software WEP support (patch from Stano Meduna). 54 * o (maybe) Software WEP support (patch from Stano Meduna).
@@ -462,7 +89,10 @@
462#include <linux/netdevice.h> 89#include <linux/netdevice.h>
463#include <linux/if_arp.h> 90#include <linux/if_arp.h>
464#include <linux/etherdevice.h> 91#include <linux/etherdevice.h>
92#include <linux/ethtool.h>
465#include <linux/wireless.h> 93#include <linux/wireless.h>
94#include <net/iw_handler.h>
95#include <net/ieee80211.h>
466 96
467#include <net/ieee80211.h> 97#include <net/ieee80211.h>
468 98
@@ -497,6 +127,10 @@ static int ignore_disconnect; /* = 0 */
497module_param(ignore_disconnect, int, 0644); 127module_param(ignore_disconnect, int, 0644);
498MODULE_PARM_DESC(ignore_disconnect, "Don't report lost link to the network layer"); 128MODULE_PARM_DESC(ignore_disconnect, "Don't report lost link to the network layer");
499 129
130static int force_monitor; /* = 0 */
131module_param(force_monitor, int, 0644);
132MODULE_PARM_DESC(force_monitor, "Allow monitor mode for all firmware versions");
133
500/********************************************************************/ 134/********************************************************************/
501/* Compile time configuration and compatibility stuff */ 135/* Compile time configuration and compatibility stuff */
502/********************************************************************/ 136/********************************************************************/
@@ -512,6 +146,10 @@ MODULE_PARM_DESC(ignore_disconnect, "Don't report lost link to the network layer
512/* Internal constants */ 146/* Internal constants */
513/********************************************************************/ 147/********************************************************************/
514 148
149/* 802.2 LLC/SNAP header used for Ethernet encapsulation over 802.11 */
150static const u8 encaps_hdr[] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
151#define ENCAPS_OVERHEAD (sizeof(encaps_hdr) + 2)
152
515#define ORINOCO_MIN_MTU 256 153#define ORINOCO_MIN_MTU 256
516#define ORINOCO_MAX_MTU (IEEE80211_DATA_LEN - ENCAPS_OVERHEAD) 154#define ORINOCO_MAX_MTU (IEEE80211_DATA_LEN - ENCAPS_OVERHEAD)
517 155
@@ -538,6 +176,11 @@ MODULE_PARM_DESC(ignore_disconnect, "Don't report lost link to the network layer
538 | HERMES_EV_WTERR | HERMES_EV_INFO \ 176 | HERMES_EV_WTERR | HERMES_EV_INFO \
539 | HERMES_EV_INFDROP ) 177 | HERMES_EV_INFDROP )
540 178
179#define MAX_RID_LEN 1024
180
181static const struct iw_handler_def orinoco_handler_def;
182static struct ethtool_ops orinoco_ethtool_ops;
183
541/********************************************************************/ 184/********************************************************************/
542/* Data tables */ 185/* Data tables */
543/********************************************************************/ 186/********************************************************************/
@@ -572,26 +215,45 @@ static struct {
572/* Data types */ 215/* Data types */
573/********************************************************************/ 216/********************************************************************/
574 217
575struct header_struct { 218/* Used in Event handling.
576 /* 802.3 */ 219 * We avoid nested structres as they break on ARM -- Moustafa */
577 u8 dest[ETH_ALEN]; 220struct hermes_tx_descriptor_802_11 {
578 u8 src[ETH_ALEN]; 221 /* hermes_tx_descriptor */
579 u16 len; 222 u16 status;
580 /* 802.2 */ 223 u16 reserved1;
224 u16 reserved2;
225 u32 sw_support;
226 u8 retry_count;
227 u8 tx_rate;
228 u16 tx_control;
229
230 /* ieee802_11_hdr */
231 u16 frame_ctl;
232 u16 duration_id;
233 u8 addr1[ETH_ALEN];
234 u8 addr2[ETH_ALEN];
235 u8 addr3[ETH_ALEN];
236 u16 seq_ctl;
237 u8 addr4[ETH_ALEN];
238 u16 data_len;
239
240 /* ethhdr */
241 unsigned char h_dest[ETH_ALEN]; /* destination eth addr */
242 unsigned char h_source[ETH_ALEN]; /* source ether addr */
243 unsigned short h_proto; /* packet type ID field */
244
245 /* p8022_hdr */
581 u8 dsap; 246 u8 dsap;
582 u8 ssap; 247 u8 ssap;
583 u8 ctrl; 248 u8 ctrl;
584 /* SNAP */
585 u8 oui[3]; 249 u8 oui[3];
250
586 u16 ethertype; 251 u16 ethertype;
587} __attribute__ ((packed)); 252} __attribute__ ((packed));
588 253
589/* 802.2 LLC/SNAP header used for Ethernet encapsulation over 802.11 */ 254/* Rx frame header except compatibility 802.3 header */
590u8 encaps_hdr[] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
591
592#define ENCAPS_OVERHEAD (sizeof(encaps_hdr) + 2)
593
594struct hermes_rx_descriptor { 255struct hermes_rx_descriptor {
256 /* Control */
595 u16 status; 257 u16 status;
596 u32 time; 258 u32 time;
597 u8 silence; 259 u8 silence;
@@ -599,13 +261,24 @@ struct hermes_rx_descriptor {
599 u8 rate; 261 u8 rate;
600 u8 rxflow; 262 u8 rxflow;
601 u32 reserved; 263 u32 reserved;
264
265 /* 802.11 header */
266 u16 frame_ctl;
267 u16 duration_id;
268 u8 addr1[ETH_ALEN];
269 u8 addr2[ETH_ALEN];
270 u8 addr3[ETH_ALEN];
271 u16 seq_ctl;
272 u8 addr4[ETH_ALEN];
273
274 /* Data length */
275 u16 data_len;
602} __attribute__ ((packed)); 276} __attribute__ ((packed));
603 277
604/********************************************************************/ 278/********************************************************************/
605/* Function prototypes */ 279/* Function prototypes */
606/********************************************************************/ 280/********************************************************************/
607 281
608static int orinoco_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
609static int __orinoco_program_rids(struct net_device *dev); 282static int __orinoco_program_rids(struct net_device *dev);
610static void __orinoco_set_multicast_list(struct net_device *dev); 283static void __orinoco_set_multicast_list(struct net_device *dev);
611 284
@@ -629,6 +302,10 @@ static inline void set_port_type(struct orinoco_private *priv)
629 priv->createibss = 1; 302 priv->createibss = 1;
630 } 303 }
631 break; 304 break;
305 case IW_MODE_MONITOR:
306 priv->port_type = 3;
307 priv->createibss = 0;
308 break;
632 default: 309 default:
633 printk(KERN_ERR "%s: Invalid priv->iw_mode in set_port_type()\n", 310 printk(KERN_ERR "%s: Invalid priv->iw_mode in set_port_type()\n",
634 priv->ndev->name); 311 priv->ndev->name);
@@ -815,7 +492,7 @@ static int orinoco_xmit(struct sk_buff *skb, struct net_device *dev)
815 return 1; 492 return 1;
816 } 493 }
817 494
818 if (! netif_carrier_ok(dev)) { 495 if (! netif_carrier_ok(dev) || (priv->iw_mode == IW_MODE_MONITOR)) {
819 /* Oops, the firmware hasn't established a connection, 496 /* Oops, the firmware hasn't established a connection,
820 silently drop the packet (this seems to be the 497 silently drop the packet (this seems to be the
821 safest approach). */ 498 safest approach). */
@@ -952,26 +629,55 @@ static void __orinoco_ev_txexc(struct net_device *dev, hermes_t *hw)
952 struct orinoco_private *priv = netdev_priv(dev); 629 struct orinoco_private *priv = netdev_priv(dev);
953 struct net_device_stats *stats = &priv->stats; 630 struct net_device_stats *stats = &priv->stats;
954 u16 fid = hermes_read_regn(hw, TXCOMPLFID); 631 u16 fid = hermes_read_regn(hw, TXCOMPLFID);
955 struct hermes_tx_descriptor desc; 632 struct hermes_tx_descriptor_802_11 hdr;
956 int err = 0; 633 int err = 0;
957 634
958 if (fid == DUMMY_FID) 635 if (fid == DUMMY_FID)
959 return; /* Nothing's really happened */ 636 return; /* Nothing's really happened */
960 637
961 err = hermes_bap_pread(hw, IRQ_BAP, &desc, sizeof(desc), fid, 0); 638 /* Read the frame header */
639 err = hermes_bap_pread(hw, IRQ_BAP, &hdr,
640 sizeof(struct hermes_tx_descriptor) +
641 sizeof(struct ieee80211_hdr),
642 fid, 0);
643
644 hermes_write_regn(hw, TXCOMPLFID, DUMMY_FID);
645 stats->tx_errors++;
646
962 if (err) { 647 if (err) {
963 printk(KERN_WARNING "%s: Unable to read descriptor on Tx error " 648 printk(KERN_WARNING "%s: Unable to read descriptor on Tx error "
964 "(FID=%04X error %d)\n", 649 "(FID=%04X error %d)\n",
965 dev->name, fid, err); 650 dev->name, fid, err);
966 } else { 651 return;
967 DEBUG(1, "%s: Tx error, status %d\n",
968 dev->name, le16_to_cpu(desc.status));
969 } 652 }
970 653
971 stats->tx_errors++; 654 DEBUG(1, "%s: Tx error, err %d (FID=%04X)\n", dev->name,
655 err, fid);
656
657 /* We produce a TXDROP event only for retry or lifetime
658 * exceeded, because that's the only status that really mean
659 * that this particular node went away.
660 * Other errors means that *we* screwed up. - Jean II */
661 hdr.status = le16_to_cpu(hdr.status);
662 if (hdr.status & (HERMES_TXSTAT_RETRYERR | HERMES_TXSTAT_AGEDERR)) {
663 union iwreq_data wrqu;
664
665 /* Copy 802.11 dest address.
666 * We use the 802.11 header because the frame may
667 * not be 802.3 or may be mangled...
668 * In Ad-Hoc mode, it will be the node address.
669 * In managed mode, it will be most likely the AP addr
670 * User space will figure out how to convert it to
671 * whatever it needs (IP address or else).
672 * - Jean II */
673 memcpy(wrqu.addr.sa_data, hdr.addr1, ETH_ALEN);
674 wrqu.addr.sa_family = ARPHRD_ETHER;
675
676 /* Send event to user space */
677 wireless_send_event(dev, IWEVTXDROP, &wrqu, NULL);
678 }
972 679
973 netif_wake_queue(dev); 680 netif_wake_queue(dev);
974 hermes_write_regn(hw, TXCOMPLFID, DUMMY_FID);
975} 681}
976 682
977static void orinoco_tx_timeout(struct net_device *dev) 683static void orinoco_tx_timeout(struct net_device *dev)
@@ -1048,18 +754,127 @@ static void orinoco_stat_gather(struct net_device *dev,
1048 } 754 }
1049} 755}
1050 756
757/*
758 * orinoco_rx_monitor - handle received monitor frames.
759 *
760 * Arguments:
761 * dev network device
762 * rxfid received FID
763 * desc rx descriptor of the frame
764 *
765 * Call context: interrupt
766 */
767static void orinoco_rx_monitor(struct net_device *dev, u16 rxfid,
768 struct hermes_rx_descriptor *desc)
769{
770 u32 hdrlen = 30; /* return full header by default */
771 u32 datalen = 0;
772 u16 fc;
773 int err;
774 int len;
775 struct sk_buff *skb;
776 struct orinoco_private *priv = netdev_priv(dev);
777 struct net_device_stats *stats = &priv->stats;
778 hermes_t *hw = &priv->hw;
779
780 len = le16_to_cpu(desc->data_len);
781
782 /* Determine the size of the header and the data */
783 fc = le16_to_cpu(desc->frame_ctl);
784 switch (fc & IEEE80211_FCTL_FTYPE) {
785 case IEEE80211_FTYPE_DATA:
786 if ((fc & IEEE80211_FCTL_TODS)
787 && (fc & IEEE80211_FCTL_FROMDS))
788 hdrlen = 30;
789 else
790 hdrlen = 24;
791 datalen = len;
792 break;
793 case IEEE80211_FTYPE_MGMT:
794 hdrlen = 24;
795 datalen = len;
796 break;
797 case IEEE80211_FTYPE_CTL:
798 switch (fc & IEEE80211_FCTL_STYPE) {
799 case IEEE80211_STYPE_PSPOLL:
800 case IEEE80211_STYPE_RTS:
801 case IEEE80211_STYPE_CFEND:
802 case IEEE80211_STYPE_CFENDACK:
803 hdrlen = 16;
804 break;
805 case IEEE80211_STYPE_CTS:
806 case IEEE80211_STYPE_ACK:
807 hdrlen = 10;
808 break;
809 }
810 break;
811 default:
812 /* Unknown frame type */
813 break;
814 }
815
816 /* sanity check the length */
817 if (datalen > IEEE80211_DATA_LEN + 12) {
818 printk(KERN_DEBUG "%s: oversized monitor frame, "
819 "data length = %d\n", dev->name, datalen);
820 err = -EIO;
821 stats->rx_length_errors++;
822 goto update_stats;
823 }
824
825 skb = dev_alloc_skb(hdrlen + datalen);
826 if (!skb) {
827 printk(KERN_WARNING "%s: Cannot allocate skb for monitor frame\n",
828 dev->name);
829 err = -ENOMEM;
830 goto drop;
831 }
832
833 /* Copy the 802.11 header to the skb */
834 memcpy(skb_put(skb, hdrlen), &(desc->frame_ctl), hdrlen);
835 skb->mac.raw = skb->data;
836
837 /* If any, copy the data from the card to the skb */
838 if (datalen > 0) {
839 err = hermes_bap_pread(hw, IRQ_BAP, skb_put(skb, datalen),
840 ALIGN(datalen, 2), rxfid,
841 HERMES_802_2_OFFSET);
842 if (err) {
843 printk(KERN_ERR "%s: error %d reading monitor frame\n",
844 dev->name, err);
845 goto drop;
846 }
847 }
848
849 skb->dev = dev;
850 skb->ip_summed = CHECKSUM_NONE;
851 skb->pkt_type = PACKET_OTHERHOST;
852 skb->protocol = __constant_htons(ETH_P_802_2);
853
854 dev->last_rx = jiffies;
855 stats->rx_packets++;
856 stats->rx_bytes += skb->len;
857
858 netif_rx(skb);
859 return;
860
861 drop:
862 dev_kfree_skb_irq(skb);
863 update_stats:
864 stats->rx_errors++;
865 stats->rx_dropped++;
866}
867
1051static void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw) 868static void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw)
1052{ 869{
1053 struct orinoco_private *priv = netdev_priv(dev); 870 struct orinoco_private *priv = netdev_priv(dev);
1054 struct net_device_stats *stats = &priv->stats; 871 struct net_device_stats *stats = &priv->stats;
1055 struct iw_statistics *wstats = &priv->wstats; 872 struct iw_statistics *wstats = &priv->wstats;
1056 struct sk_buff *skb = NULL; 873 struct sk_buff *skb = NULL;
1057 u16 rxfid, status; 874 u16 rxfid, status, fc;
1058 int length, data_len, data_off; 875 int length;
1059 char *p;
1060 struct hermes_rx_descriptor desc; 876 struct hermes_rx_descriptor desc;
1061 struct header_struct hdr; 877 struct ethhdr *hdr;
1062 struct ethhdr *eh;
1063 int err; 878 int err;
1064 879
1065 rxfid = hermes_read_regn(hw, RXFID); 880 rxfid = hermes_read_regn(hw, RXFID);
@@ -1069,53 +884,46 @@ static void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw)
1069 if (err) { 884 if (err) {
1070 printk(KERN_ERR "%s: error %d reading Rx descriptor. " 885 printk(KERN_ERR "%s: error %d reading Rx descriptor. "
1071 "Frame dropped.\n", dev->name, err); 886 "Frame dropped.\n", dev->name, err);
1072 stats->rx_errors++; 887 goto update_stats;
1073 goto drop;
1074 } 888 }
1075 889
1076 status = le16_to_cpu(desc.status); 890 status = le16_to_cpu(desc.status);
1077 891
1078 if (status & HERMES_RXSTAT_ERR) { 892 if (status & HERMES_RXSTAT_BADCRC) {
1079 if (status & HERMES_RXSTAT_UNDECRYPTABLE) { 893 DEBUG(1, "%s: Bad CRC on Rx. Frame dropped.\n",
1080 wstats->discard.code++; 894 dev->name);
1081 DEBUG(1, "%s: Undecryptable frame on Rx. Frame dropped.\n", 895 stats->rx_crc_errors++;
1082 dev->name); 896 goto update_stats;
1083 } else {
1084 stats->rx_crc_errors++;
1085 DEBUG(1, "%s: Bad CRC on Rx. Frame dropped.\n", dev->name);
1086 }
1087 stats->rx_errors++;
1088 goto drop;
1089 } 897 }
1090 898
1091 /* For now we ignore the 802.11 header completely, assuming 899 /* Handle frames in monitor mode */
1092 that the card's firmware has handled anything vital */ 900 if (priv->iw_mode == IW_MODE_MONITOR) {
901 orinoco_rx_monitor(dev, rxfid, &desc);
902 return;
903 }
1093 904
1094 err = hermes_bap_pread(hw, IRQ_BAP, &hdr, sizeof(hdr), 905 if (status & HERMES_RXSTAT_UNDECRYPTABLE) {
1095 rxfid, HERMES_802_3_OFFSET); 906 DEBUG(1, "%s: Undecryptable frame on Rx. Frame dropped.\n",
1096 if (err) { 907 dev->name);
1097 printk(KERN_ERR "%s: error %d reading frame header. " 908 wstats->discard.code++;
1098 "Frame dropped.\n", dev->name, err); 909 goto update_stats;
1099 stats->rx_errors++;
1100 goto drop;
1101 } 910 }
1102 911
1103 length = ntohs(hdr.len); 912 length = le16_to_cpu(desc.data_len);
1104 913 fc = le16_to_cpu(desc.frame_ctl);
914
1105 /* Sanity checks */ 915 /* Sanity checks */
1106 if (length < 3) { /* No for even an 802.2 LLC header */ 916 if (length < 3) { /* No for even an 802.2 LLC header */
1107 /* At least on Symbol firmware with PCF we get quite a 917 /* At least on Symbol firmware with PCF we get quite a
1108 lot of these legitimately - Poll frames with no 918 lot of these legitimately - Poll frames with no
1109 data. */ 919 data. */
1110 stats->rx_dropped++; 920 return;
1111 goto drop;
1112 } 921 }
1113 if (length > IEEE80211_DATA_LEN) { 922 if (length > IEEE80211_DATA_LEN) {
1114 printk(KERN_WARNING "%s: Oversized frame received (%d bytes)\n", 923 printk(KERN_WARNING "%s: Oversized frame received (%d bytes)\n",
1115 dev->name, length); 924 dev->name, length);
1116 stats->rx_length_errors++; 925 stats->rx_length_errors++;
1117 stats->rx_errors++; 926 goto update_stats;
1118 goto drop;
1119 } 927 }
1120 928
1121 /* We need space for the packet data itself, plus an ethernet 929 /* We need space for the packet data itself, plus an ethernet
@@ -1127,60 +935,53 @@ static void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw)
1127 if (!skb) { 935 if (!skb) {
1128 printk(KERN_WARNING "%s: Can't allocate skb for Rx\n", 936 printk(KERN_WARNING "%s: Can't allocate skb for Rx\n",
1129 dev->name); 937 dev->name);
1130 goto drop; 938 goto update_stats;
1131 } 939 }
1132 940
1133 skb_reserve(skb, 2); /* This way the IP header is aligned */ 941 /* We'll prepend the header, so reserve space for it. The worst
942 case is no decapsulation, when 802.3 header is prepended and
943 nothing is removed. 2 is for aligning the IP header. */
944 skb_reserve(skb, ETH_HLEN + 2);
945
946 err = hermes_bap_pread(hw, IRQ_BAP, skb_put(skb, length),
947 ALIGN(length, 2), rxfid,
948 HERMES_802_2_OFFSET);
949 if (err) {
950 printk(KERN_ERR "%s: error %d reading frame. "
951 "Frame dropped.\n", dev->name, err);
952 goto drop;
953 }
1134 954
1135 /* Handle decapsulation 955 /* Handle decapsulation
1136 * In most cases, the firmware tell us about SNAP frames. 956 * In most cases, the firmware tell us about SNAP frames.
1137 * For some reason, the SNAP frames sent by LinkSys APs 957 * For some reason, the SNAP frames sent by LinkSys APs
1138 * are not properly recognised by most firmwares. 958 * are not properly recognised by most firmwares.
1139 * So, check ourselves */ 959 * So, check ourselves */
1140 if (((status & HERMES_RXSTAT_MSGTYPE) == HERMES_RXSTAT_1042) || 960 if (length >= ENCAPS_OVERHEAD &&
1141 ((status & HERMES_RXSTAT_MSGTYPE) == HERMES_RXSTAT_TUNNEL) || 961 (((status & HERMES_RXSTAT_MSGTYPE) == HERMES_RXSTAT_1042) ||
1142 is_ethersnap(&hdr)) { 962 ((status & HERMES_RXSTAT_MSGTYPE) == HERMES_RXSTAT_TUNNEL) ||
963 is_ethersnap(skb->data))) {
1143 /* These indicate a SNAP within 802.2 LLC within 964 /* These indicate a SNAP within 802.2 LLC within
1144 802.11 frame which we'll need to de-encapsulate to 965 802.11 frame which we'll need to de-encapsulate to
1145 the original EthernetII frame. */ 966 the original EthernetII frame. */
1146 967 hdr = (struct ethhdr *)skb_push(skb, ETH_HLEN - ENCAPS_OVERHEAD);
1147 if (length < ENCAPS_OVERHEAD) { /* No room for full LLC+SNAP */
1148 stats->rx_length_errors++;
1149 goto drop;
1150 }
1151
1152 /* Remove SNAP header, reconstruct EthernetII frame */
1153 data_len = length - ENCAPS_OVERHEAD;
1154 data_off = HERMES_802_3_OFFSET + sizeof(hdr);
1155
1156 eh = (struct ethhdr *)skb_put(skb, ETH_HLEN);
1157
1158 memcpy(eh, &hdr, 2 * ETH_ALEN);
1159 eh->h_proto = hdr.ethertype;
1160 } else { 968 } else {
1161 /* All other cases indicate a genuine 802.3 frame. No 969 /* 802.3 frame - prepend 802.3 header as is */
1162 decapsulation needed. We just throw the whole 970 hdr = (struct ethhdr *)skb_push(skb, ETH_HLEN);
1163 thing in, and hope the protocol layer can deal with 971 hdr->h_proto = htons(length);
1164 it as 802.3 */
1165 data_len = length;
1166 data_off = HERMES_802_3_OFFSET;
1167 /* FIXME: we re-read from the card data we already read here */
1168 }
1169
1170 p = skb_put(skb, data_len);
1171 err = hermes_bap_pread(hw, IRQ_BAP, p, ALIGN(data_len, 2),
1172 rxfid, data_off);
1173 if (err) {
1174 printk(KERN_ERR "%s: error %d reading frame. "
1175 "Frame dropped.\n", dev->name, err);
1176 stats->rx_errors++;
1177 goto drop;
1178 } 972 }
973 memcpy(hdr->h_dest, desc.addr1, ETH_ALEN);
974 if (fc & IEEE80211_FCTL_FROMDS)
975 memcpy(hdr->h_source, desc.addr3, ETH_ALEN);
976 else
977 memcpy(hdr->h_source, desc.addr2, ETH_ALEN);
1179 978
1180 dev->last_rx = jiffies; 979 dev->last_rx = jiffies;
1181 skb->dev = dev; 980 skb->dev = dev;
1182 skb->protocol = eth_type_trans(skb, dev); 981 skb->protocol = eth_type_trans(skb, dev);
1183 skb->ip_summed = CHECKSUM_NONE; 982 skb->ip_summed = CHECKSUM_NONE;
983 if (fc & IEEE80211_FCTL_TODS)
984 skb->pkt_type = PACKET_OTHERHOST;
1184 985
1185 /* Process the wireless stats if needed */ 986 /* Process the wireless stats if needed */
1186 orinoco_stat_gather(dev, skb, &desc); 987 orinoco_stat_gather(dev, skb, &desc);
@@ -1193,11 +994,10 @@ static void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw)
1193 return; 994 return;
1194 995
1195 drop: 996 drop:
997 dev_kfree_skb_irq(skb);
998 update_stats:
999 stats->rx_errors++;
1196 stats->rx_dropped++; 1000 stats->rx_dropped++;
1197
1198 if (skb)
1199 dev_kfree_skb_irq(skb);
1200 return;
1201} 1001}
1202 1002
1203/********************************************************************/ 1003/********************************************************************/
@@ -1241,6 +1041,99 @@ static void print_linkstatus(struct net_device *dev, u16 status)
1241 dev->name, s, status); 1041 dev->name, s, status);
1242} 1042}
1243 1043
1044/* Search scan results for requested BSSID, join it if found */
1045static void orinoco_join_ap(struct net_device *dev)
1046{
1047 struct orinoco_private *priv = netdev_priv(dev);
1048 struct hermes *hw = &priv->hw;
1049 int err;
1050 unsigned long flags;
1051 struct join_req {
1052 u8 bssid[ETH_ALEN];
1053 u16 channel;
1054 } __attribute__ ((packed)) req;
1055 const int atom_len = offsetof(struct prism2_scan_apinfo, atim);
1056 struct prism2_scan_apinfo *atom;
1057 int offset = 4;
1058 u8 *buf;
1059 u16 len;
1060
1061 /* Allocate buffer for scan results */
1062 buf = kmalloc(MAX_SCAN_LEN, GFP_KERNEL);
1063 if (! buf)
1064 return;
1065
1066 if (orinoco_lock(priv, &flags) != 0)
1067 goto out;
1068
1069 /* Sanity checks in case user changed something in the meantime */
1070 if (! priv->bssid_fixed)
1071 goto out;
1072
1073 if (strlen(priv->desired_essid) == 0)
1074 goto out;
1075
1076 /* Read scan results from the firmware */
1077 err = hermes_read_ltv(hw, USER_BAP,
1078 HERMES_RID_SCANRESULTSTABLE,
1079 MAX_SCAN_LEN, &len, buf);
1080 if (err) {
1081 printk(KERN_ERR "%s: Cannot read scan results\n",
1082 dev->name);
1083 goto out;
1084 }
1085
1086 len = HERMES_RECLEN_TO_BYTES(len);
1087
1088 /* Go through the scan results looking for the channel of the AP
1089 * we were requested to join */
1090 for (; offset + atom_len <= len; offset += atom_len) {
1091 atom = (struct prism2_scan_apinfo *) (buf + offset);
1092 if (memcmp(&atom->bssid, priv->desired_bssid, ETH_ALEN) == 0)
1093 goto found;
1094 }
1095
1096 DEBUG(1, "%s: Requested AP not found in scan results\n",
1097 dev->name);
1098 goto out;
1099
1100 found:
1101 memcpy(req.bssid, priv->desired_bssid, ETH_ALEN);
1102 req.channel = atom->channel; /* both are little-endian */
1103 err = HERMES_WRITE_RECORD(hw, USER_BAP, HERMES_RID_CNFJOINREQUEST,
1104 &req);
1105 if (err)
1106 printk(KERN_ERR "%s: Error issuing join request\n", dev->name);
1107
1108 out:
1109 kfree(buf);
1110 orinoco_unlock(priv, &flags);
1111}
1112
1113/* Send new BSSID to userspace */
1114static void orinoco_send_wevents(struct net_device *dev)
1115{
1116 struct orinoco_private *priv = netdev_priv(dev);
1117 struct hermes *hw = &priv->hw;
1118 union iwreq_data wrqu;
1119 int err;
1120 unsigned long flags;
1121
1122 if (orinoco_lock(priv, &flags) != 0)
1123 return;
1124
1125 err = hermes_read_ltv(hw, IRQ_BAP, HERMES_RID_CURRENTBSSID,
1126 ETH_ALEN, NULL, wrqu.ap_addr.sa_data);
1127 if (err != 0)
1128 return;
1129
1130 wrqu.ap_addr.sa_family = ARPHRD_ETHER;
1131
1132 /* Send event to user space */
1133 wireless_send_event(dev, SIOCGIWAP, &wrqu, NULL);
1134 orinoco_unlock(priv, &flags);
1135}
1136
1244static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw) 1137static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1245{ 1138{
1246 struct orinoco_private *priv = netdev_priv(dev); 1139 struct orinoco_private *priv = netdev_priv(dev);
@@ -1308,6 +1201,9 @@ static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1308 u16 newstatus; 1201 u16 newstatus;
1309 int connected; 1202 int connected;
1310 1203
1204 if (priv->iw_mode == IW_MODE_MONITOR)
1205 break;
1206
1311 if (len != sizeof(linkstatus)) { 1207 if (len != sizeof(linkstatus)) {
1312 printk(KERN_WARNING "%s: Unexpected size for linkstatus frame (%d bytes)\n", 1208 printk(KERN_WARNING "%s: Unexpected size for linkstatus frame (%d bytes)\n",
1313 dev->name, len); 1209 dev->name, len);
@@ -1320,6 +1216,15 @@ static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1320 break; 1216 break;
1321 newstatus = le16_to_cpu(linkstatus.linkstatus); 1217 newstatus = le16_to_cpu(linkstatus.linkstatus);
1322 1218
1219 /* Symbol firmware uses "out of range" to signal that
1220 * the hostscan frame can be requested. */
1221 if (newstatus == HERMES_LINKSTATUS_AP_OUT_OF_RANGE &&
1222 priv->firmware_type == FIRMWARE_TYPE_SYMBOL &&
1223 priv->has_hostscan && priv->scan_inprogress) {
1224 hermes_inquire(hw, HERMES_INQ_HOSTSCAN_SYMBOL);
1225 break;
1226 }
1227
1323 connected = (newstatus == HERMES_LINKSTATUS_CONNECTED) 1228 connected = (newstatus == HERMES_LINKSTATUS_CONNECTED)
1324 || (newstatus == HERMES_LINKSTATUS_AP_CHANGE) 1229 || (newstatus == HERMES_LINKSTATUS_AP_CHANGE)
1325 || (newstatus == HERMES_LINKSTATUS_AP_IN_RANGE); 1230 || (newstatus == HERMES_LINKSTATUS_AP_IN_RANGE);
@@ -1329,12 +1234,89 @@ static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1329 else if (!ignore_disconnect) 1234 else if (!ignore_disconnect)
1330 netif_carrier_off(dev); 1235 netif_carrier_off(dev);
1331 1236
1332 if (newstatus != priv->last_linkstatus) 1237 if (newstatus != priv->last_linkstatus) {
1238 priv->last_linkstatus = newstatus;
1333 print_linkstatus(dev, newstatus); 1239 print_linkstatus(dev, newstatus);
1240 /* The info frame contains only one word which is the
1241 * status (see hermes.h). The status is pretty boring
1242 * in itself, that's why we export the new BSSID...
1243 * Jean II */
1244 schedule_work(&priv->wevent_work);
1245 }
1246 }
1247 break;
1248 case HERMES_INQ_SCAN:
1249 if (!priv->scan_inprogress && priv->bssid_fixed &&
1250 priv->firmware_type == FIRMWARE_TYPE_INTERSIL) {
1251 schedule_work(&priv->join_work);
1252 break;
1253 }
1254 /* fall through */
1255 case HERMES_INQ_HOSTSCAN:
1256 case HERMES_INQ_HOSTSCAN_SYMBOL: {
1257 /* Result of a scanning. Contains information about
1258 * cells in the vicinity - Jean II */
1259 union iwreq_data wrqu;
1260 unsigned char *buf;
1261
1262 /* Sanity check */
1263 if (len > 4096) {
1264 printk(KERN_WARNING "%s: Scan results too large (%d bytes)\n",
1265 dev->name, len);
1266 break;
1267 }
1268
1269 /* We are a strict producer. If the previous scan results
1270 * have not been consumed, we just have to drop this
1271 * frame. We can't remove the previous results ourselves,
1272 * that would be *very* racy... Jean II */
1273 if (priv->scan_result != NULL) {
1274 printk(KERN_WARNING "%s: Previous scan results not consumed, dropping info frame.\n", dev->name);
1275 break;
1276 }
1277
1278 /* Allocate buffer for results */
1279 buf = kmalloc(len, GFP_ATOMIC);
1280 if (buf == NULL)
1281 /* No memory, so can't printk()... */
1282 break;
1334 1283
1335 priv->last_linkstatus = newstatus; 1284 /* Read scan data */
1285 err = hermes_bap_pread(hw, IRQ_BAP, (void *) buf, len,
1286 infofid, sizeof(info));
1287 if (err)
1288 break;
1289
1290#ifdef ORINOCO_DEBUG
1291 {
1292 int i;
1293 printk(KERN_DEBUG "Scan result [%02X", buf[0]);
1294 for(i = 1; i < (len * 2); i++)
1295 printk(":%02X", buf[i]);
1296 printk("]\n");
1297 }
1298#endif /* ORINOCO_DEBUG */
1299
1300 /* Allow the clients to access the results */
1301 priv->scan_len = len;
1302 priv->scan_result = buf;
1303
1304 /* Send an empty event to user space.
1305 * We don't send the received data on the event because
1306 * it would require us to do complex transcoding, and
1307 * we want to minimise the work done in the irq handler
1308 * Use a request to extract the data - Jean II */
1309 wrqu.data.length = 0;
1310 wrqu.data.flags = 0;
1311 wireless_send_event(dev, SIOCGIWSCAN, &wrqu, NULL);
1336 } 1312 }
1337 break; 1313 break;
1314 case HERMES_INQ_SEC_STAT_AGERE:
1315 /* Security status (Agere specific) */
1316 /* Ignore this frame for now */
1317 if (priv->firmware_type == FIRMWARE_TYPE_AGERE)
1318 break;
1319 /* fall through */
1338 default: 1320 default:
1339 printk(KERN_DEBUG "%s: Unknown information frame received: " 1321 printk(KERN_DEBUG "%s: Unknown information frame received: "
1340 "type 0x%04x, length %d\n", dev->name, type, len); 1322 "type 0x%04x, length %d\n", dev->name, type, len);
@@ -1471,6 +1453,36 @@ static int __orinoco_hw_set_bitrate(struct orinoco_private *priv)
1471 return err; 1453 return err;
1472} 1454}
1473 1455
1456/* Set fixed AP address */
1457static int __orinoco_hw_set_wap(struct orinoco_private *priv)
1458{
1459 int roaming_flag;
1460 int err = 0;
1461 hermes_t *hw = &priv->hw;
1462
1463 switch (priv->firmware_type) {
1464 case FIRMWARE_TYPE_AGERE:
1465 /* not supported */
1466 break;
1467 case FIRMWARE_TYPE_INTERSIL:
1468 if (priv->bssid_fixed)
1469 roaming_flag = 2;
1470 else
1471 roaming_flag = 1;
1472
1473 err = hermes_write_wordrec(hw, USER_BAP,
1474 HERMES_RID_CNFROAMINGMODE,
1475 roaming_flag);
1476 break;
1477 case FIRMWARE_TYPE_SYMBOL:
1478 err = HERMES_WRITE_RECORD(hw, USER_BAP,
1479 HERMES_RID_CNFMANDATORYBSSID_SYMBOL,
1480 &priv->desired_bssid);
1481 break;
1482 }
1483 return err;
1484}
1485
1474/* Change the WEP keys and/or the current keys. Can be called 1486/* Change the WEP keys and/or the current keys. Can be called
1475 * either from __orinoco_hw_setup_wep() or directly from 1487 * either from __orinoco_hw_setup_wep() or directly from
1476 * orinoco_ioctl_setiwencode(). In the later case the association 1488 * orinoco_ioctl_setiwencode(). In the later case the association
@@ -1656,6 +1668,13 @@ static int __orinoco_program_rids(struct net_device *dev)
1656 } 1668 }
1657 } 1669 }
1658 1670
1671 /* Set the desired BSSID */
1672 err = __orinoco_hw_set_wap(priv);
1673 if (err) {
1674 printk(KERN_ERR "%s: Error %d setting AP address\n",
1675 dev->name, err);
1676 return err;
1677 }
1659 /* Set the desired ESSID */ 1678 /* Set the desired ESSID */
1660 idbuf.len = cpu_to_le16(strlen(priv->desired_essid)); 1679 idbuf.len = cpu_to_le16(strlen(priv->desired_essid));
1661 memcpy(&idbuf.val, priv->desired_essid, sizeof(idbuf.val)); 1680 memcpy(&idbuf.val, priv->desired_essid, sizeof(idbuf.val));
@@ -1794,6 +1813,20 @@ static int __orinoco_program_rids(struct net_device *dev)
1794 } 1813 }
1795 } 1814 }
1796 1815
1816 if (priv->iw_mode == IW_MODE_MONITOR) {
1817 /* Enable monitor mode */
1818 dev->type = ARPHRD_IEEE80211;
1819 err = hermes_docmd_wait(hw, HERMES_CMD_TEST |
1820 HERMES_TEST_MONITOR, 0, NULL);
1821 } else {
1822 /* Disable monitor mode */
1823 dev->type = ARPHRD_ETHER;
1824 err = hermes_docmd_wait(hw, HERMES_CMD_TEST |
1825 HERMES_TEST_STOP, 0, NULL);
1826 }
1827 if (err)
1828 return err;
1829
1797 /* Set promiscuity / multicast*/ 1830 /* Set promiscuity / multicast*/
1798 priv->promiscuous = 0; 1831 priv->promiscuous = 0;
1799 priv->mc_count = 0; 1832 priv->mc_count = 0;
@@ -1870,55 +1903,6 @@ __orinoco_set_multicast_list(struct net_device *dev)
1870 dev->flags &= ~IFF_PROMISC; 1903 dev->flags &= ~IFF_PROMISC;
1871} 1904}
1872 1905
1873static int orinoco_reconfigure(struct net_device *dev)
1874{
1875 struct orinoco_private *priv = netdev_priv(dev);
1876 struct hermes *hw = &priv->hw;
1877 unsigned long flags;
1878 int err = 0;
1879
1880 if (priv->broken_disableport) {
1881 schedule_work(&priv->reset_work);
1882 return 0;
1883 }
1884
1885 if (orinoco_lock(priv, &flags) != 0)
1886 return -EBUSY;
1887
1888 err = hermes_disable_port(hw, 0);
1889 if (err) {
1890 printk(KERN_WARNING "%s: Unable to disable port while reconfiguring card\n",
1891 dev->name);
1892 priv->broken_disableport = 1;
1893 goto out;
1894 }
1895
1896 err = __orinoco_program_rids(dev);
1897 if (err) {
1898 printk(KERN_WARNING "%s: Unable to reconfigure card\n",
1899 dev->name);
1900 goto out;
1901 }
1902
1903 err = hermes_enable_port(hw, 0);
1904 if (err) {
1905 printk(KERN_WARNING "%s: Unable to enable port while reconfiguring card\n",
1906 dev->name);
1907 goto out;
1908 }
1909
1910 out:
1911 if (err) {
1912 printk(KERN_WARNING "%s: Resetting instead...\n", dev->name);
1913 schedule_work(&priv->reset_work);
1914 err = 0;
1915 }
1916
1917 orinoco_unlock(priv, &flags);
1918 return err;
1919
1920}
1921
1922/* This must be called from user context, without locks held - use 1906/* This must be called from user context, without locks held - use
1923 * schedule_work() */ 1907 * schedule_work() */
1924static void orinoco_reset(struct net_device *dev) 1908static void orinoco_reset(struct net_device *dev)
@@ -1947,6 +1931,11 @@ static void orinoco_reset(struct net_device *dev)
1947 1931
1948 orinoco_unlock(priv, &flags); 1932 orinoco_unlock(priv, &flags);
1949 1933
1934 /* Scanning support: Cleanup of driver struct */
1935 kfree(priv->scan_result);
1936 priv->scan_result = NULL;
1937 priv->scan_inprogress = 0;
1938
1950 if (priv->hard_reset) { 1939 if (priv->hard_reset) {
1951 err = (*priv->hard_reset)(priv); 1940 err = (*priv->hard_reset)(priv);
1952 if (err) { 1941 if (err) {
@@ -2185,6 +2174,8 @@ static int determine_firmware(struct net_device *dev)
2185 priv->has_mwo = (firmver >= 0x60000); 2174 priv->has_mwo = (firmver >= 0x60000);
2186 priv->has_pm = (firmver >= 0x40020); /* Don't work in 7.52 ? */ 2175 priv->has_pm = (firmver >= 0x40020); /* Don't work in 7.52 ? */
2187 priv->ibss_port = 1; 2176 priv->ibss_port = 1;
2177 priv->has_hostscan = (firmver >= 0x8000a);
2178 priv->broken_monitor = (firmver >= 0x80000);
2188 2179
2189 /* Tested with Agere firmware : 2180 /* Tested with Agere firmware :
2190 * 1.16 ; 4.08 ; 4.52 ; 6.04 ; 6.16 ; 7.28 => Jean II 2181 * 1.16 ; 4.08 ; 4.52 ; 6.04 ; 6.16 ; 7.28 => Jean II
@@ -2230,6 +2221,8 @@ static int determine_firmware(struct net_device *dev)
2230 priv->ibss_port = 4; 2221 priv->ibss_port = 4;
2231 priv->broken_disableport = (firmver == 0x25013) || 2222 priv->broken_disableport = (firmver == 0x25013) ||
2232 (firmver >= 0x30000 && firmver <= 0x31000); 2223 (firmver >= 0x30000 && firmver <= 0x31000);
2224 priv->has_hostscan = (firmver >= 0x31001) ||
2225 (firmver >= 0x29057 && firmver < 0x30000);
2233 /* Tested with Intel firmware : 0x20015 => Jean II */ 2226 /* Tested with Intel firmware : 0x20015 => Jean II */
2234 /* Tested with 3Com firmware : 0x15012 & 0x22001 => Jean II */ 2227 /* Tested with 3Com firmware : 0x15012 & 0x22001 => Jean II */
2235 break; 2228 break;
@@ -2249,6 +2242,7 @@ static int determine_firmware(struct net_device *dev)
2249 priv->has_ibss = (firmver >= 0x000700); /* FIXME */ 2242 priv->has_ibss = (firmver >= 0x000700); /* FIXME */
2250 priv->has_big_wep = priv->has_wep = (firmver >= 0x000800); 2243 priv->has_big_wep = priv->has_wep = (firmver >= 0x000800);
2251 priv->has_pm = (firmver >= 0x000700); 2244 priv->has_pm = (firmver >= 0x000700);
2245 priv->has_hostscan = (firmver >= 0x010301);
2252 2246
2253 if (firmver >= 0x000800) 2247 if (firmver >= 0x000800)
2254 priv->ibss_port = 0; 2248 priv->ibss_port = 0;
@@ -2457,8 +2451,9 @@ struct net_device *alloc_orinocodev(int sizeof_card,
2457 dev->tx_timeout = orinoco_tx_timeout; 2451 dev->tx_timeout = orinoco_tx_timeout;
2458 dev->watchdog_timeo = HZ; /* 1 second timeout */ 2452 dev->watchdog_timeo = HZ; /* 1 second timeout */
2459 dev->get_stats = orinoco_get_stats; 2453 dev->get_stats = orinoco_get_stats;
2454 dev->ethtool_ops = &orinoco_ethtool_ops;
2460 dev->get_wireless_stats = orinoco_get_wireless_stats; 2455 dev->get_wireless_stats = orinoco_get_wireless_stats;
2461 dev->do_ioctl = orinoco_ioctl; 2456 dev->wireless_handlers = (struct iw_handler_def *)&orinoco_handler_def;
2462 dev->change_mtu = orinoco_change_mtu; 2457 dev->change_mtu = orinoco_change_mtu;
2463 dev->set_multicast_list = orinoco_set_multicast_list; 2458 dev->set_multicast_list = orinoco_set_multicast_list;
2464 /* we use the default eth_mac_addr for setting the MAC addr */ 2459 /* we use the default eth_mac_addr for setting the MAC addr */
@@ -2474,6 +2469,8 @@ struct net_device *alloc_orinocodev(int sizeof_card,
2474 * before anything else touches the 2469 * before anything else touches the
2475 * hardware */ 2470 * hardware */
2476 INIT_WORK(&priv->reset_work, (void (*)(void *))orinoco_reset, dev); 2471 INIT_WORK(&priv->reset_work, (void (*)(void *))orinoco_reset, dev);
2472 INIT_WORK(&priv->join_work, (void (*)(void *))orinoco_join_ap, dev);
2473 INIT_WORK(&priv->wevent_work, (void (*)(void *))orinoco_send_wevents, dev);
2477 2474
2478 netif_carrier_off(dev); 2475 netif_carrier_off(dev);
2479 priv->last_linkstatus = 0xffff; 2476 priv->last_linkstatus = 0xffff;
@@ -2484,6 +2481,9 @@ struct net_device *alloc_orinocodev(int sizeof_card,
2484 2481
2485void free_orinocodev(struct net_device *dev) 2482void free_orinocodev(struct net_device *dev)
2486{ 2483{
2484 struct orinoco_private *priv = netdev_priv(dev);
2485
2486 kfree(priv->scan_result);
2487 free_netdev(dev); 2487 free_netdev(dev);
2488} 2488}
2489 2489
@@ -2491,24 +2491,6 @@ void free_orinocodev(struct net_device *dev)
2491/* Wireless extensions */ 2491/* Wireless extensions */
2492/********************************************************************/ 2492/********************************************************************/
2493 2493
2494static int orinoco_hw_get_bssid(struct orinoco_private *priv,
2495 char buf[ETH_ALEN])
2496{
2497 hermes_t *hw = &priv->hw;
2498 int err = 0;
2499 unsigned long flags;
2500
2501 if (orinoco_lock(priv, &flags) != 0)
2502 return -EBUSY;
2503
2504 err = hermes_read_ltv(hw, USER_BAP, HERMES_RID_CURRENTBSSID,
2505 ETH_ALEN, NULL, buf);
2506
2507 orinoco_unlock(priv, &flags);
2508
2509 return err;
2510}
2511
2512static int orinoco_hw_get_essid(struct orinoco_private *priv, int *active, 2494static int orinoco_hw_get_essid(struct orinoco_private *priv, int *active,
2513 char buf[IW_ESSID_MAX_SIZE+1]) 2495 char buf[IW_ESSID_MAX_SIZE+1])
2514{ 2496{
@@ -2634,140 +2616,271 @@ static int orinoco_hw_get_bitratelist(struct orinoco_private *priv,
2634 return 0; 2616 return 0;
2635} 2617}
2636 2618
2637static int orinoco_ioctl_getiwrange(struct net_device *dev, struct iw_point *rrq) 2619static int orinoco_ioctl_getname(struct net_device *dev,
2620 struct iw_request_info *info,
2621 char *name,
2622 char *extra)
2638{ 2623{
2639 struct orinoco_private *priv = netdev_priv(dev); 2624 struct orinoco_private *priv = netdev_priv(dev);
2640 int err = 0;
2641 int mode;
2642 struct iw_range range;
2643 int numrates; 2625 int numrates;
2644 int i, k; 2626 int err;
2627
2628 err = orinoco_hw_get_bitratelist(priv, &numrates, NULL, 0);
2629
2630 if (!err && (numrates > 2))
2631 strcpy(name, "IEEE 802.11b");
2632 else
2633 strcpy(name, "IEEE 802.11-DS");
2634
2635 return 0;
2636}
2637
2638static int orinoco_ioctl_setwap(struct net_device *dev,
2639 struct iw_request_info *info,
2640 struct sockaddr *ap_addr,
2641 char *extra)
2642{
2643 struct orinoco_private *priv = netdev_priv(dev);
2644 int err = -EINPROGRESS; /* Call commit handler */
2645 unsigned long flags; 2645 unsigned long flags;
2646 static const u8 off_addr[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2647 static const u8 any_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2646 2648
2647 TRACE_ENTER(dev->name); 2649 if (orinoco_lock(priv, &flags) != 0)
2650 return -EBUSY;
2651
2652 /* Enable automatic roaming - no sanity checks are needed */
2653 if (memcmp(&ap_addr->sa_data, off_addr, ETH_ALEN) == 0 ||
2654 memcmp(&ap_addr->sa_data, any_addr, ETH_ALEN) == 0) {
2655 priv->bssid_fixed = 0;
2656 memset(priv->desired_bssid, 0, ETH_ALEN);
2657
2658 /* "off" means keep existing connection */
2659 if (ap_addr->sa_data[0] == 0) {
2660 __orinoco_hw_set_wap(priv);
2661 err = 0;
2662 }
2663 goto out;
2664 }
2648 2665
2649 if (!access_ok(VERIFY_WRITE, rrq->pointer, sizeof(range))) 2666 if (priv->firmware_type == FIRMWARE_TYPE_AGERE) {
2650 return -EFAULT; 2667 printk(KERN_WARNING "%s: Lucent/Agere firmware doesn't "
2668 "support manual roaming\n",
2669 dev->name);
2670 err = -EOPNOTSUPP;
2671 goto out;
2672 }
2651 2673
2652 rrq->length = sizeof(range); 2674 if (priv->iw_mode != IW_MODE_INFRA) {
2675 printk(KERN_WARNING "%s: Manual roaming supported only in "
2676 "managed mode\n", dev->name);
2677 err = -EOPNOTSUPP;
2678 goto out;
2679 }
2680
2681 /* Intersil firmware hangs without Desired ESSID */
2682 if (priv->firmware_type == FIRMWARE_TYPE_INTERSIL &&
2683 strlen(priv->desired_essid) == 0) {
2684 printk(KERN_WARNING "%s: Desired ESSID must be set for "
2685 "manual roaming\n", dev->name);
2686 err = -EOPNOTSUPP;
2687 goto out;
2688 }
2689
2690 /* Finally, enable manual roaming */
2691 priv->bssid_fixed = 1;
2692 memcpy(priv->desired_bssid, &ap_addr->sa_data, ETH_ALEN);
2693
2694 out:
2695 orinoco_unlock(priv, &flags);
2696 return err;
2697}
2698
2699static int orinoco_ioctl_getwap(struct net_device *dev,
2700 struct iw_request_info *info,
2701 struct sockaddr *ap_addr,
2702 char *extra)
2703{
2704 struct orinoco_private *priv = netdev_priv(dev);
2705
2706 hermes_t *hw = &priv->hw;
2707 int err = 0;
2708 unsigned long flags;
2653 2709
2654 if (orinoco_lock(priv, &flags) != 0) 2710 if (orinoco_lock(priv, &flags) != 0)
2655 return -EBUSY; 2711 return -EBUSY;
2656 2712
2657 mode = priv->iw_mode; 2713 ap_addr->sa_family = ARPHRD_ETHER;
2714 err = hermes_read_ltv(hw, USER_BAP, HERMES_RID_CURRENTBSSID,
2715 ETH_ALEN, NULL, ap_addr->sa_data);
2716
2658 orinoco_unlock(priv, &flags); 2717 orinoco_unlock(priv, &flags);
2659 2718
2660 memset(&range, 0, sizeof(range)); 2719 return err;
2720}
2661 2721
2662 /* Much of this shamelessly taken from wvlan_cs.c. No idea 2722static int orinoco_ioctl_setmode(struct net_device *dev,
2663 * what it all means -dgibson */ 2723 struct iw_request_info *info,
2664 range.we_version_compiled = WIRELESS_EXT; 2724 u32 *mode,
2665 range.we_version_source = 11; 2725 char *extra)
2726{
2727 struct orinoco_private *priv = netdev_priv(dev);
2728 int err = -EINPROGRESS; /* Call commit handler */
2729 unsigned long flags;
2666 2730
2667 range.min_nwid = range.max_nwid = 0; /* We don't use nwids */ 2731 if (priv->iw_mode == *mode)
2732 return 0;
2733
2734 if (orinoco_lock(priv, &flags) != 0)
2735 return -EBUSY;
2736
2737 switch (*mode) {
2738 case IW_MODE_ADHOC:
2739 if (!priv->has_ibss && !priv->has_port3)
2740 err = -EOPNOTSUPP;
2741 break;
2742
2743 case IW_MODE_INFRA:
2744 break;
2745
2746 case IW_MODE_MONITOR:
2747 if (priv->broken_monitor && !force_monitor) {
2748 printk(KERN_WARNING "%s: Monitor mode support is "
2749 "buggy in this firmware, not enabling\n",
2750 dev->name);
2751 err = -EOPNOTSUPP;
2752 }
2753 break;
2754
2755 default:
2756 err = -EOPNOTSUPP;
2757 break;
2758 }
2759
2760 if (err == -EINPROGRESS) {
2761 priv->iw_mode = *mode;
2762 set_port_type(priv);
2763 }
2764
2765 orinoco_unlock(priv, &flags);
2766
2767 return err;
2768}
2769
2770static int orinoco_ioctl_getmode(struct net_device *dev,
2771 struct iw_request_info *info,
2772 u32 *mode,
2773 char *extra)
2774{
2775 struct orinoco_private *priv = netdev_priv(dev);
2776
2777 *mode = priv->iw_mode;
2778 return 0;
2779}
2780
2781static int orinoco_ioctl_getiwrange(struct net_device *dev,
2782 struct iw_request_info *info,
2783 struct iw_point *rrq,
2784 char *extra)
2785{
2786 struct orinoco_private *priv = netdev_priv(dev);
2787 int err = 0;
2788 struct iw_range *range = (struct iw_range *) extra;
2789 int numrates;
2790 int i, k;
2791
2792 TRACE_ENTER(dev->name);
2793
2794 rrq->length = sizeof(struct iw_range);
2795 memset(range, 0, sizeof(struct iw_range));
2796
2797 range->we_version_compiled = WIRELESS_EXT;
2798 range->we_version_source = 14;
2668 2799
2669 /* Set available channels/frequencies */ 2800 /* Set available channels/frequencies */
2670 range.num_channels = NUM_CHANNELS; 2801 range->num_channels = NUM_CHANNELS;
2671 k = 0; 2802 k = 0;
2672 for (i = 0; i < NUM_CHANNELS; i++) { 2803 for (i = 0; i < NUM_CHANNELS; i++) {
2673 if (priv->channel_mask & (1 << i)) { 2804 if (priv->channel_mask & (1 << i)) {
2674 range.freq[k].i = i + 1; 2805 range->freq[k].i = i + 1;
2675 range.freq[k].m = channel_frequency[i] * 100000; 2806 range->freq[k].m = channel_frequency[i] * 100000;
2676 range.freq[k].e = 1; 2807 range->freq[k].e = 1;
2677 k++; 2808 k++;
2678 } 2809 }
2679 2810
2680 if (k >= IW_MAX_FREQUENCIES) 2811 if (k >= IW_MAX_FREQUENCIES)
2681 break; 2812 break;
2682 } 2813 }
2683 range.num_frequency = k; 2814 range->num_frequency = k;
2815 range->sensitivity = 3;
2684 2816
2685 range.sensitivity = 3; 2817 if (priv->has_wep) {
2818 range->max_encoding_tokens = ORINOCO_MAX_KEYS;
2819 range->encoding_size[0] = SMALL_KEY_SIZE;
2820 range->num_encoding_sizes = 1;
2686 2821
2687 if ((mode == IW_MODE_ADHOC) && (priv->spy_number == 0)){ 2822 if (priv->has_big_wep) {
2823 range->encoding_size[1] = LARGE_KEY_SIZE;
2824 range->num_encoding_sizes = 2;
2825 }
2826 }
2827
2828 if ((priv->iw_mode == IW_MODE_ADHOC) && (priv->spy_number == 0)){
2688 /* Quality stats meaningless in ad-hoc mode */ 2829 /* Quality stats meaningless in ad-hoc mode */
2689 range.max_qual.qual = 0;
2690 range.max_qual.level = 0;
2691 range.max_qual.noise = 0;
2692 range.avg_qual.qual = 0;
2693 range.avg_qual.level = 0;
2694 range.avg_qual.noise = 0;
2695 } else { 2830 } else {
2696 range.max_qual.qual = 0x8b - 0x2f; 2831 range->max_qual.qual = 0x8b - 0x2f;
2697 range.max_qual.level = 0x2f - 0x95 - 1; 2832 range->max_qual.level = 0x2f - 0x95 - 1;
2698 range.max_qual.noise = 0x2f - 0x95 - 1; 2833 range->max_qual.noise = 0x2f - 0x95 - 1;
2699 /* Need to get better values */ 2834 /* Need to get better values */
2700 range.avg_qual.qual = 0x24; 2835 range->avg_qual.qual = 0x24;
2701 range.avg_qual.level = 0xC2; 2836 range->avg_qual.level = 0xC2;
2702 range.avg_qual.noise = 0x9E; 2837 range->avg_qual.noise = 0x9E;
2703 } 2838 }
2704 2839
2705 err = orinoco_hw_get_bitratelist(priv, &numrates, 2840 err = orinoco_hw_get_bitratelist(priv, &numrates,
2706 range.bitrate, IW_MAX_BITRATES); 2841 range->bitrate, IW_MAX_BITRATES);
2707 if (err) 2842 if (err)
2708 return err; 2843 return err;
2709 range.num_bitrates = numrates; 2844 range->num_bitrates = numrates;
2710 2845
2711 /* Set an indication of the max TCP throughput in bit/s that we can 2846 /* Set an indication of the max TCP throughput in bit/s that we can
2712 * expect using this interface. May be use for QoS stuff... 2847 * expect using this interface. May be use for QoS stuff...
2713 * Jean II */ 2848 * Jean II */
2714 if(numrates > 2) 2849 if (numrates > 2)
2715 range.throughput = 5 * 1000 * 1000; /* ~5 Mb/s */ 2850 range->throughput = 5 * 1000 * 1000; /* ~5 Mb/s */
2716 else 2851 else
2717 range.throughput = 1.5 * 1000 * 1000; /* ~1.5 Mb/s */ 2852 range->throughput = 1.5 * 1000 * 1000; /* ~1.5 Mb/s */
2718 2853
2719 range.min_rts = 0; 2854 range->min_rts = 0;
2720 range.max_rts = 2347; 2855 range->max_rts = 2347;
2721 range.min_frag = 256; 2856 range->min_frag = 256;
2722 range.max_frag = 2346; 2857 range->max_frag = 2346;
2723 2858
2724 if (orinoco_lock(priv, &flags) != 0) 2859 range->min_pmp = 0;
2725 return -EBUSY; 2860 range->max_pmp = 65535000;
2726 if (priv->has_wep) { 2861 range->min_pmt = 0;
2727 range.max_encoding_tokens = ORINOCO_MAX_KEYS; 2862 range->max_pmt = 65535 * 1000; /* ??? */
2728 2863 range->pmp_flags = IW_POWER_PERIOD;
2729 range.encoding_size[0] = SMALL_KEY_SIZE; 2864 range->pmt_flags = IW_POWER_TIMEOUT;
2730 range.num_encoding_sizes = 1; 2865 range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_UNICAST_R;
2731 2866
2732 if (priv->has_big_wep) { 2867 range->retry_capa = IW_RETRY_LIMIT | IW_RETRY_LIFETIME;
2733 range.encoding_size[1] = LARGE_KEY_SIZE; 2868 range->retry_flags = IW_RETRY_LIMIT;
2734 range.num_encoding_sizes = 2; 2869 range->r_time_flags = IW_RETRY_LIFETIME;
2735 } 2870 range->min_retry = 0;
2736 } else { 2871 range->max_retry = 65535; /* ??? */
2737 range.num_encoding_sizes = 0; 2872 range->min_r_time = 0;
2738 range.max_encoding_tokens = 0; 2873 range->max_r_time = 65535 * 1000; /* ??? */
2739 }
2740 orinoco_unlock(priv, &flags);
2741
2742 range.min_pmp = 0;
2743 range.max_pmp = 65535000;
2744 range.min_pmt = 0;
2745 range.max_pmt = 65535 * 1000; /* ??? */
2746 range.pmp_flags = IW_POWER_PERIOD;
2747 range.pmt_flags = IW_POWER_TIMEOUT;
2748 range.pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_UNICAST_R;
2749
2750 range.num_txpower = 1;
2751 range.txpower[0] = 15; /* 15dBm */
2752 range.txpower_capa = IW_TXPOW_DBM;
2753
2754 range.retry_capa = IW_RETRY_LIMIT | IW_RETRY_LIFETIME;
2755 range.retry_flags = IW_RETRY_LIMIT;
2756 range.r_time_flags = IW_RETRY_LIFETIME;
2757 range.min_retry = 0;
2758 range.max_retry = 65535; /* ??? */
2759 range.min_r_time = 0;
2760 range.max_r_time = 65535 * 1000; /* ??? */
2761
2762 if (copy_to_user(rrq->pointer, &range, sizeof(range)))
2763 return -EFAULT;
2764 2874
2765 TRACE_EXIT(dev->name); 2875 TRACE_EXIT(dev->name);
2766 2876
2767 return 0; 2877 return 0;
2768} 2878}
2769 2879
2770static int orinoco_ioctl_setiwencode(struct net_device *dev, struct iw_point *erq) 2880static int orinoco_ioctl_setiwencode(struct net_device *dev,
2881 struct iw_request_info *info,
2882 struct iw_point *erq,
2883 char *keybuf)
2771{ 2884{
2772 struct orinoco_private *priv = netdev_priv(dev); 2885 struct orinoco_private *priv = netdev_priv(dev);
2773 int index = (erq->flags & IW_ENCODE_INDEX) - 1; 2886 int index = (erq->flags & IW_ENCODE_INDEX) - 1;
@@ -2775,8 +2888,7 @@ static int orinoco_ioctl_setiwencode(struct net_device *dev, struct iw_point *er
2775 int enable = priv->wep_on; 2888 int enable = priv->wep_on;
2776 int restricted = priv->wep_restrict; 2889 int restricted = priv->wep_restrict;
2777 u16 xlen = 0; 2890 u16 xlen = 0;
2778 int err = 0; 2891 int err = -EINPROGRESS; /* Call commit handler */
2779 char keybuf[ORINOCO_MAX_KEY_SIZE];
2780 unsigned long flags; 2892 unsigned long flags;
2781 2893
2782 if (! priv->has_wep) 2894 if (! priv->has_wep)
@@ -2789,9 +2901,6 @@ static int orinoco_ioctl_setiwencode(struct net_device *dev, struct iw_point *er
2789 2901
2790 if ( (erq->length > SMALL_KEY_SIZE) && !priv->has_big_wep ) 2902 if ( (erq->length > SMALL_KEY_SIZE) && !priv->has_big_wep )
2791 return -E2BIG; 2903 return -E2BIG;
2792
2793 if (copy_from_user(keybuf, erq->pointer, erq->length))
2794 return -EFAULT;
2795 } 2904 }
2796 2905
2797 if (orinoco_lock(priv, &flags) != 0) 2906 if (orinoco_lock(priv, &flags) != 0)
@@ -2865,12 +2974,14 @@ static int orinoco_ioctl_setiwencode(struct net_device *dev, struct iw_point *er
2865 return err; 2974 return err;
2866} 2975}
2867 2976
2868static int orinoco_ioctl_getiwencode(struct net_device *dev, struct iw_point *erq) 2977static int orinoco_ioctl_getiwencode(struct net_device *dev,
2978 struct iw_request_info *info,
2979 struct iw_point *erq,
2980 char *keybuf)
2869{ 2981{
2870 struct orinoco_private *priv = netdev_priv(dev); 2982 struct orinoco_private *priv = netdev_priv(dev);
2871 int index = (erq->flags & IW_ENCODE_INDEX) - 1; 2983 int index = (erq->flags & IW_ENCODE_INDEX) - 1;
2872 u16 xlen = 0; 2984 u16 xlen = 0;
2873 char keybuf[ORINOCO_MAX_KEY_SIZE];
2874 unsigned long flags; 2985 unsigned long flags;
2875 2986
2876 if (! priv->has_wep) 2987 if (! priv->has_wep)
@@ -2899,51 +3010,47 @@ static int orinoco_ioctl_getiwencode(struct net_device *dev, struct iw_point *er
2899 memcpy(keybuf, priv->keys[index].data, ORINOCO_MAX_KEY_SIZE); 3010 memcpy(keybuf, priv->keys[index].data, ORINOCO_MAX_KEY_SIZE);
2900 3011
2901 orinoco_unlock(priv, &flags); 3012 orinoco_unlock(priv, &flags);
2902
2903 if (erq->pointer) {
2904 if (copy_to_user(erq->pointer, keybuf, xlen))
2905 return -EFAULT;
2906 }
2907
2908 return 0; 3013 return 0;
2909} 3014}
2910 3015
2911static int orinoco_ioctl_setessid(struct net_device *dev, struct iw_point *erq) 3016static int orinoco_ioctl_setessid(struct net_device *dev,
3017 struct iw_request_info *info,
3018 struct iw_point *erq,
3019 char *essidbuf)
2912{ 3020{
2913 struct orinoco_private *priv = netdev_priv(dev); 3021 struct orinoco_private *priv = netdev_priv(dev);
2914 char essidbuf[IW_ESSID_MAX_SIZE+1];
2915 unsigned long flags; 3022 unsigned long flags;
2916 3023
2917 /* Note : ESSID is ignored in Ad-Hoc demo mode, but we can set it 3024 /* Note : ESSID is ignored in Ad-Hoc demo mode, but we can set it
2918 * anyway... - Jean II */ 3025 * anyway... - Jean II */
2919 3026
2920 memset(&essidbuf, 0, sizeof(essidbuf)); 3027 /* Hum... Should not use Wireless Extension constant (may change),
2921 3028 * should use our own... - Jean II */
2922 if (erq->flags) { 3029 if (erq->length > IW_ESSID_MAX_SIZE)
2923 /* iwconfig includes the NUL in the specified length */ 3030 return -E2BIG;
2924 if (erq->length > IW_ESSID_MAX_SIZE+1)
2925 return -E2BIG;
2926
2927 if (copy_from_user(&essidbuf, erq->pointer, erq->length))
2928 return -EFAULT;
2929
2930 essidbuf[IW_ESSID_MAX_SIZE] = '\0';
2931 }
2932 3031
2933 if (orinoco_lock(priv, &flags) != 0) 3032 if (orinoco_lock(priv, &flags) != 0)
2934 return -EBUSY; 3033 return -EBUSY;
2935 3034
2936 memcpy(priv->desired_essid, essidbuf, sizeof(priv->desired_essid)); 3035 /* NULL the string (for NULL termination & ESSID = ANY) - Jean II */
3036 memset(priv->desired_essid, 0, sizeof(priv->desired_essid));
3037
3038 /* If not ANY, get the new ESSID */
3039 if (erq->flags) {
3040 memcpy(priv->desired_essid, essidbuf, erq->length);
3041 }
2937 3042
2938 orinoco_unlock(priv, &flags); 3043 orinoco_unlock(priv, &flags);
2939 3044
2940 return 0; 3045 return -EINPROGRESS; /* Call commit handler */
2941} 3046}
2942 3047
2943static int orinoco_ioctl_getessid(struct net_device *dev, struct iw_point *erq) 3048static int orinoco_ioctl_getessid(struct net_device *dev,
3049 struct iw_request_info *info,
3050 struct iw_point *erq,
3051 char *essidbuf)
2944{ 3052{
2945 struct orinoco_private *priv = netdev_priv(dev); 3053 struct orinoco_private *priv = netdev_priv(dev);
2946 char essidbuf[IW_ESSID_MAX_SIZE+1];
2947 int active; 3054 int active;
2948 int err = 0; 3055 int err = 0;
2949 unsigned long flags; 3056 unsigned long flags;
@@ -2957,51 +3064,46 @@ static int orinoco_ioctl_getessid(struct net_device *dev, struct iw_point *erq)
2957 } else { 3064 } else {
2958 if (orinoco_lock(priv, &flags) != 0) 3065 if (orinoco_lock(priv, &flags) != 0)
2959 return -EBUSY; 3066 return -EBUSY;
2960 memcpy(essidbuf, priv->desired_essid, sizeof(essidbuf)); 3067 memcpy(essidbuf, priv->desired_essid, IW_ESSID_MAX_SIZE + 1);
2961 orinoco_unlock(priv, &flags); 3068 orinoco_unlock(priv, &flags);
2962 } 3069 }
2963 3070
2964 erq->flags = 1; 3071 erq->flags = 1;
2965 erq->length = strlen(essidbuf) + 1; 3072 erq->length = strlen(essidbuf) + 1;
2966 if (erq->pointer)
2967 if (copy_to_user(erq->pointer, essidbuf, erq->length))
2968 return -EFAULT;
2969 3073
2970 TRACE_EXIT(dev->name); 3074 TRACE_EXIT(dev->name);
2971 3075
2972 return 0; 3076 return 0;
2973} 3077}
2974 3078
2975static int orinoco_ioctl_setnick(struct net_device *dev, struct iw_point *nrq) 3079static int orinoco_ioctl_setnick(struct net_device *dev,
3080 struct iw_request_info *info,
3081 struct iw_point *nrq,
3082 char *nickbuf)
2976{ 3083{
2977 struct orinoco_private *priv = netdev_priv(dev); 3084 struct orinoco_private *priv = netdev_priv(dev);
2978 char nickbuf[IW_ESSID_MAX_SIZE+1];
2979 unsigned long flags; 3085 unsigned long flags;
2980 3086
2981 if (nrq->length > IW_ESSID_MAX_SIZE) 3087 if (nrq->length > IW_ESSID_MAX_SIZE)
2982 return -E2BIG; 3088 return -E2BIG;
2983 3089
2984 memset(nickbuf, 0, sizeof(nickbuf));
2985
2986 if (copy_from_user(nickbuf, nrq->pointer, nrq->length))
2987 return -EFAULT;
2988
2989 nickbuf[nrq->length] = '\0';
2990
2991 if (orinoco_lock(priv, &flags) != 0) 3090 if (orinoco_lock(priv, &flags) != 0)
2992 return -EBUSY; 3091 return -EBUSY;
2993 3092
2994 memcpy(priv->nick, nickbuf, sizeof(priv->nick)); 3093 memset(priv->nick, 0, sizeof(priv->nick));
3094 memcpy(priv->nick, nickbuf, nrq->length);
2995 3095
2996 orinoco_unlock(priv, &flags); 3096 orinoco_unlock(priv, &flags);
2997 3097
2998 return 0; 3098 return -EINPROGRESS; /* Call commit handler */
2999} 3099}
3000 3100
3001static int orinoco_ioctl_getnick(struct net_device *dev, struct iw_point *nrq) 3101static int orinoco_ioctl_getnick(struct net_device *dev,
3102 struct iw_request_info *info,
3103 struct iw_point *nrq,
3104 char *nickbuf)
3002{ 3105{
3003 struct orinoco_private *priv = netdev_priv(dev); 3106 struct orinoco_private *priv = netdev_priv(dev);
3004 char nickbuf[IW_ESSID_MAX_SIZE+1];
3005 unsigned long flags; 3107 unsigned long flags;
3006 3108
3007 if (orinoco_lock(priv, &flags) != 0) 3109 if (orinoco_lock(priv, &flags) != 0)
@@ -3012,23 +3114,22 @@ static int orinoco_ioctl_getnick(struct net_device *dev, struct iw_point *nrq)
3012 3114
3013 nrq->length = strlen(nickbuf)+1; 3115 nrq->length = strlen(nickbuf)+1;
3014 3116
3015 if (copy_to_user(nrq->pointer, nickbuf, sizeof(nickbuf)))
3016 return -EFAULT;
3017
3018 return 0; 3117 return 0;
3019} 3118}
3020 3119
3021static int orinoco_ioctl_setfreq(struct net_device *dev, struct iw_freq *frq) 3120static int orinoco_ioctl_setfreq(struct net_device *dev,
3121 struct iw_request_info *info,
3122 struct iw_freq *frq,
3123 char *extra)
3022{ 3124{
3023 struct orinoco_private *priv = netdev_priv(dev); 3125 struct orinoco_private *priv = netdev_priv(dev);
3024 int chan = -1; 3126 int chan = -1;
3025 unsigned long flags; 3127 unsigned long flags;
3128 int err = -EINPROGRESS; /* Call commit handler */
3026 3129
3027 /* We can only use this in Ad-Hoc demo mode to set the operating 3130 /* In infrastructure mode the AP sets the channel */
3028 * frequency, or in IBSS mode to set the frequency where the IBSS 3131 if (priv->iw_mode == IW_MODE_INFRA)
3029 * will be created - Jean II */ 3132 return -EBUSY;
3030 if (priv->iw_mode != IW_MODE_ADHOC)
3031 return -EOPNOTSUPP;
3032 3133
3033 if ( (frq->e == 0) && (frq->m <= 1000) ) { 3134 if ( (frq->e == 0) && (frq->m <= 1000) ) {
3034 /* Setting by channel number */ 3135 /* Setting by channel number */
@@ -3052,13 +3153,44 @@ static int orinoco_ioctl_setfreq(struct net_device *dev, struct iw_freq *frq)
3052 3153
3053 if (orinoco_lock(priv, &flags) != 0) 3154 if (orinoco_lock(priv, &flags) != 0)
3054 return -EBUSY; 3155 return -EBUSY;
3156
3055 priv->channel = chan; 3157 priv->channel = chan;
3158 if (priv->iw_mode == IW_MODE_MONITOR) {
3159 /* Fast channel change - no commit if successful */
3160 hermes_t *hw = &priv->hw;
3161 err = hermes_docmd_wait(hw, HERMES_CMD_TEST |
3162 HERMES_TEST_SET_CHANNEL,
3163 chan, NULL);
3164 }
3056 orinoco_unlock(priv, &flags); 3165 orinoco_unlock(priv, &flags);
3057 3166
3167 return err;
3168}
3169
3170static int orinoco_ioctl_getfreq(struct net_device *dev,
3171 struct iw_request_info *info,
3172 struct iw_freq *frq,
3173 char *extra)
3174{
3175 struct orinoco_private *priv = netdev_priv(dev);
3176 int tmp;
3177
3178 /* Locking done in there */
3179 tmp = orinoco_hw_get_freq(priv);
3180 if (tmp < 0) {
3181 return tmp;
3182 }
3183
3184 frq->m = tmp;
3185 frq->e = 1;
3186
3058 return 0; 3187 return 0;
3059} 3188}
3060 3189
3061static int orinoco_ioctl_getsens(struct net_device *dev, struct iw_param *srq) 3190static int orinoco_ioctl_getsens(struct net_device *dev,
3191 struct iw_request_info *info,
3192 struct iw_param *srq,
3193 char *extra)
3062{ 3194{
3063 struct orinoco_private *priv = netdev_priv(dev); 3195 struct orinoco_private *priv = netdev_priv(dev);
3064 hermes_t *hw = &priv->hw; 3196 hermes_t *hw = &priv->hw;
@@ -3084,7 +3216,10 @@ static int orinoco_ioctl_getsens(struct net_device *dev, struct iw_param *srq)
3084 return 0; 3216 return 0;
3085} 3217}
3086 3218
3087static int orinoco_ioctl_setsens(struct net_device *dev, struct iw_param *srq) 3219static int orinoco_ioctl_setsens(struct net_device *dev,
3220 struct iw_request_info *info,
3221 struct iw_param *srq,
3222 char *extra)
3088{ 3223{
3089 struct orinoco_private *priv = netdev_priv(dev); 3224 struct orinoco_private *priv = netdev_priv(dev);
3090 int val = srq->value; 3225 int val = srq->value;
@@ -3101,10 +3236,13 @@ static int orinoco_ioctl_setsens(struct net_device *dev, struct iw_param *srq)
3101 priv->ap_density = val; 3236 priv->ap_density = val;
3102 orinoco_unlock(priv, &flags); 3237 orinoco_unlock(priv, &flags);
3103 3238
3104 return 0; 3239 return -EINPROGRESS; /* Call commit handler */
3105} 3240}
3106 3241
3107static int orinoco_ioctl_setrts(struct net_device *dev, struct iw_param *rrq) 3242static int orinoco_ioctl_setrts(struct net_device *dev,
3243 struct iw_request_info *info,
3244 struct iw_param *rrq,
3245 char *extra)
3108{ 3246{
3109 struct orinoco_private *priv = netdev_priv(dev); 3247 struct orinoco_private *priv = netdev_priv(dev);
3110 int val = rrq->value; 3248 int val = rrq->value;
@@ -3122,13 +3260,30 @@ static int orinoco_ioctl_setrts(struct net_device *dev, struct iw_param *rrq)
3122 priv->rts_thresh = val; 3260 priv->rts_thresh = val;
3123 orinoco_unlock(priv, &flags); 3261 orinoco_unlock(priv, &flags);
3124 3262
3263 return -EINPROGRESS; /* Call commit handler */
3264}
3265
3266static int orinoco_ioctl_getrts(struct net_device *dev,
3267 struct iw_request_info *info,
3268 struct iw_param *rrq,
3269 char *extra)
3270{
3271 struct orinoco_private *priv = netdev_priv(dev);
3272
3273 rrq->value = priv->rts_thresh;
3274 rrq->disabled = (rrq->value == 2347);
3275 rrq->fixed = 1;
3276
3125 return 0; 3277 return 0;
3126} 3278}
3127 3279
3128static int orinoco_ioctl_setfrag(struct net_device *dev, struct iw_param *frq) 3280static int orinoco_ioctl_setfrag(struct net_device *dev,
3281 struct iw_request_info *info,
3282 struct iw_param *frq,
3283 char *extra)
3129{ 3284{
3130 struct orinoco_private *priv = netdev_priv(dev); 3285 struct orinoco_private *priv = netdev_priv(dev);
3131 int err = 0; 3286 int err = -EINPROGRESS; /* Call commit handler */
3132 unsigned long flags; 3287 unsigned long flags;
3133 3288
3134 if (orinoco_lock(priv, &flags) != 0) 3289 if (orinoco_lock(priv, &flags) != 0)
@@ -3160,11 +3315,14 @@ static int orinoco_ioctl_setfrag(struct net_device *dev, struct iw_param *frq)
3160 return err; 3315 return err;
3161} 3316}
3162 3317
3163static int orinoco_ioctl_getfrag(struct net_device *dev, struct iw_param *frq) 3318static int orinoco_ioctl_getfrag(struct net_device *dev,
3319 struct iw_request_info *info,
3320 struct iw_param *frq,
3321 char *extra)
3164{ 3322{
3165 struct orinoco_private *priv = netdev_priv(dev); 3323 struct orinoco_private *priv = netdev_priv(dev);
3166 hermes_t *hw = &priv->hw; 3324 hermes_t *hw = &priv->hw;
3167 int err = 0; 3325 int err;
3168 u16 val; 3326 u16 val;
3169 unsigned long flags; 3327 unsigned long flags;
3170 3328
@@ -3197,10 +3355,12 @@ static int orinoco_ioctl_getfrag(struct net_device *dev, struct iw_param *frq)
3197 return err; 3355 return err;
3198} 3356}
3199 3357
3200static int orinoco_ioctl_setrate(struct net_device *dev, struct iw_param *rrq) 3358static int orinoco_ioctl_setrate(struct net_device *dev,
3359 struct iw_request_info *info,
3360 struct iw_param *rrq,
3361 char *extra)
3201{ 3362{
3202 struct orinoco_private *priv = netdev_priv(dev); 3363 struct orinoco_private *priv = netdev_priv(dev);
3203 int err = 0;
3204 int ratemode = -1; 3364 int ratemode = -1;
3205 int bitrate; /* 100s of kilobits */ 3365 int bitrate; /* 100s of kilobits */
3206 int i; 3366 int i;
@@ -3236,10 +3396,13 @@ static int orinoco_ioctl_setrate(struct net_device *dev, struct iw_param *rrq)
3236 priv->bitratemode = ratemode; 3396 priv->bitratemode = ratemode;
3237 orinoco_unlock(priv, &flags); 3397 orinoco_unlock(priv, &flags);
3238 3398
3239 return err; 3399 return -EINPROGRESS;
3240} 3400}
3241 3401
3242static int orinoco_ioctl_getrate(struct net_device *dev, struct iw_param *rrq) 3402static int orinoco_ioctl_getrate(struct net_device *dev,
3403 struct iw_request_info *info,
3404 struct iw_param *rrq,
3405 char *extra)
3243{ 3406{
3244 struct orinoco_private *priv = netdev_priv(dev); 3407 struct orinoco_private *priv = netdev_priv(dev);
3245 hermes_t *hw = &priv->hw; 3408 hermes_t *hw = &priv->hw;
@@ -3304,10 +3467,13 @@ static int orinoco_ioctl_getrate(struct net_device *dev, struct iw_param *rrq)
3304 return err; 3467 return err;
3305} 3468}
3306 3469
3307static int orinoco_ioctl_setpower(struct net_device *dev, struct iw_param *prq) 3470static int orinoco_ioctl_setpower(struct net_device *dev,
3471 struct iw_request_info *info,
3472 struct iw_param *prq,
3473 char *extra)
3308{ 3474{
3309 struct orinoco_private *priv = netdev_priv(dev); 3475 struct orinoco_private *priv = netdev_priv(dev);
3310 int err = 0; 3476 int err = -EINPROGRESS; /* Call commit handler */
3311 unsigned long flags; 3477 unsigned long flags;
3312 3478
3313 if (orinoco_lock(priv, &flags) != 0) 3479 if (orinoco_lock(priv, &flags) != 0)
@@ -3356,7 +3522,10 @@ static int orinoco_ioctl_setpower(struct net_device *dev, struct iw_param *prq)
3356 return err; 3522 return err;
3357} 3523}
3358 3524
3359static int orinoco_ioctl_getpower(struct net_device *dev, struct iw_param *prq) 3525static int orinoco_ioctl_getpower(struct net_device *dev,
3526 struct iw_request_info *info,
3527 struct iw_param *prq,
3528 char *extra)
3360{ 3529{
3361 struct orinoco_private *priv = netdev_priv(dev); 3530 struct orinoco_private *priv = netdev_priv(dev);
3362 hermes_t *hw = &priv->hw; 3531 hermes_t *hw = &priv->hw;
@@ -3404,7 +3573,10 @@ static int orinoco_ioctl_getpower(struct net_device *dev, struct iw_param *prq)
3404 return err; 3573 return err;
3405} 3574}
3406 3575
3407static int orinoco_ioctl_getretry(struct net_device *dev, struct iw_param *rrq) 3576static int orinoco_ioctl_getretry(struct net_device *dev,
3577 struct iw_request_info *info,
3578 struct iw_param *rrq,
3579 char *extra)
3408{ 3580{
3409 struct orinoco_private *priv = netdev_priv(dev); 3581 struct orinoco_private *priv = netdev_priv(dev);
3410 hermes_t *hw = &priv->hw; 3582 hermes_t *hw = &priv->hw;
@@ -3455,10 +3627,38 @@ static int orinoco_ioctl_getretry(struct net_device *dev, struct iw_param *rrq)
3455 return err; 3627 return err;
3456} 3628}
3457 3629
3458static int orinoco_ioctl_setibssport(struct net_device *dev, struct iwreq *wrq) 3630static int orinoco_ioctl_reset(struct net_device *dev,
3631 struct iw_request_info *info,
3632 void *wrqu,
3633 char *extra)
3459{ 3634{
3460 struct orinoco_private *priv = netdev_priv(dev); 3635 struct orinoco_private *priv = netdev_priv(dev);
3461 int val = *( (int *) wrq->u.name ); 3636
3637 if (! capable(CAP_NET_ADMIN))
3638 return -EPERM;
3639
3640 if (info->cmd == (SIOCIWFIRSTPRIV + 0x1)) {
3641 printk(KERN_DEBUG "%s: Forcing reset!\n", dev->name);
3642
3643 /* Firmware reset */
3644 orinoco_reset(dev);
3645 } else {
3646 printk(KERN_DEBUG "%s: Force scheduling reset!\n", dev->name);
3647
3648 schedule_work(&priv->reset_work);
3649 }
3650
3651 return 0;
3652}
3653
3654static int orinoco_ioctl_setibssport(struct net_device *dev,
3655 struct iw_request_info *info,
3656 void *wrqu,
3657 char *extra)
3658
3659{
3660 struct orinoco_private *priv = netdev_priv(dev);
3661 int val = *( (int *) extra );
3462 unsigned long flags; 3662 unsigned long flags;
3463 3663
3464 if (orinoco_lock(priv, &flags) != 0) 3664 if (orinoco_lock(priv, &flags) != 0)
@@ -3470,28 +3670,28 @@ static int orinoco_ioctl_setibssport(struct net_device *dev, struct iwreq *wrq)
3470 set_port_type(priv); 3670 set_port_type(priv);
3471 3671
3472 orinoco_unlock(priv, &flags); 3672 orinoco_unlock(priv, &flags);
3473 return 0; 3673 return -EINPROGRESS; /* Call commit handler */
3474} 3674}
3475 3675
3476static int orinoco_ioctl_getibssport(struct net_device *dev, struct iwreq *wrq) 3676static int orinoco_ioctl_getibssport(struct net_device *dev,
3677 struct iw_request_info *info,
3678 void *wrqu,
3679 char *extra)
3477{ 3680{
3478 struct orinoco_private *priv = netdev_priv(dev); 3681 struct orinoco_private *priv = netdev_priv(dev);
3479 int *val = (int *)wrq->u.name; 3682 int *val = (int *) extra;
3480 unsigned long flags;
3481
3482 if (orinoco_lock(priv, &flags) != 0)
3483 return -EBUSY;
3484 3683
3485 *val = priv->ibss_port; 3684 *val = priv->ibss_port;
3486 orinoco_unlock(priv, &flags);
3487
3488 return 0; 3685 return 0;
3489} 3686}
3490 3687
3491static int orinoco_ioctl_setport3(struct net_device *dev, struct iwreq *wrq) 3688static int orinoco_ioctl_setport3(struct net_device *dev,
3689 struct iw_request_info *info,
3690 void *wrqu,
3691 char *extra)
3492{ 3692{
3493 struct orinoco_private *priv = netdev_priv(dev); 3693 struct orinoco_private *priv = netdev_priv(dev);
3494 int val = *( (int *) wrq->u.name ); 3694 int val = *( (int *) extra );
3495 int err = 0; 3695 int err = 0;
3496 unsigned long flags; 3696 unsigned long flags;
3497 3697
@@ -3520,51 +3720,131 @@ static int orinoco_ioctl_setport3(struct net_device *dev, struct iwreq *wrq)
3520 err = -EINVAL; 3720 err = -EINVAL;
3521 } 3721 }
3522 3722
3523 if (! err) 3723 if (! err) {
3524 /* Actually update the mode we are using */ 3724 /* Actually update the mode we are using */
3525 set_port_type(priv); 3725 set_port_type(priv);
3726 err = -EINPROGRESS;
3727 }
3526 3728
3527 orinoco_unlock(priv, &flags); 3729 orinoco_unlock(priv, &flags);
3528 3730
3529 return err; 3731 return err;
3530} 3732}
3531 3733
3532static int orinoco_ioctl_getport3(struct net_device *dev, struct iwreq *wrq) 3734static int orinoco_ioctl_getport3(struct net_device *dev,
3735 struct iw_request_info *info,
3736 void *wrqu,
3737 char *extra)
3738{
3739 struct orinoco_private *priv = netdev_priv(dev);
3740 int *val = (int *) extra;
3741
3742 *val = priv->prefer_port3;
3743 return 0;
3744}
3745
3746static int orinoco_ioctl_setpreamble(struct net_device *dev,
3747 struct iw_request_info *info,
3748 void *wrqu,
3749 char *extra)
3533{ 3750{
3534 struct orinoco_private *priv = netdev_priv(dev); 3751 struct orinoco_private *priv = netdev_priv(dev);
3535 int *val = (int *)wrq->u.name;
3536 unsigned long flags; 3752 unsigned long flags;
3753 int val;
3754
3755 if (! priv->has_preamble)
3756 return -EOPNOTSUPP;
3757
3758 /* 802.11b has recently defined some short preamble.
3759 * Basically, the Phy header has been reduced in size.
3760 * This increase performance, especially at high rates
3761 * (the preamble is transmitted at 1Mb/s), unfortunately
3762 * this give compatibility troubles... - Jean II */
3763 val = *( (int *) extra );
3537 3764
3538 if (orinoco_lock(priv, &flags) != 0) 3765 if (orinoco_lock(priv, &flags) != 0)
3539 return -EBUSY; 3766 return -EBUSY;
3540 3767
3541 *val = priv->prefer_port3; 3768 if (val)
3769 priv->preamble = 1;
3770 else
3771 priv->preamble = 0;
3772
3542 orinoco_unlock(priv, &flags); 3773 orinoco_unlock(priv, &flags);
3774
3775 return -EINPROGRESS; /* Call commit handler */
3776}
3777
3778static int orinoco_ioctl_getpreamble(struct net_device *dev,
3779 struct iw_request_info *info,
3780 void *wrqu,
3781 char *extra)
3782{
3783 struct orinoco_private *priv = netdev_priv(dev);
3784 int *val = (int *) extra;
3785
3786 if (! priv->has_preamble)
3787 return -EOPNOTSUPP;
3788
3789 *val = priv->preamble;
3543 return 0; 3790 return 0;
3544} 3791}
3545 3792
3793/* ioctl interface to hermes_read_ltv()
3794 * To use with iwpriv, pass the RID as the token argument, e.g.
3795 * iwpriv get_rid [0xfc00]
3796 * At least Wireless Tools 25 is required to use iwpriv.
3797 * For Wireless Tools 25 and 26 append "dummy" are the end. */
3798static int orinoco_ioctl_getrid(struct net_device *dev,
3799 struct iw_request_info *info,
3800 struct iw_point *data,
3801 char *extra)
3802{
3803 struct orinoco_private *priv = netdev_priv(dev);
3804 hermes_t *hw = &priv->hw;
3805 int rid = data->flags;
3806 u16 length;
3807 int err;
3808 unsigned long flags;
3809
3810 /* It's a "get" function, but we don't want users to access the
3811 * WEP key and other raw firmware data */
3812 if (! capable(CAP_NET_ADMIN))
3813 return -EPERM;
3814
3815 if (rid < 0xfc00 || rid > 0xffff)
3816 return -EINVAL;
3817
3818 if (orinoco_lock(priv, &flags) != 0)
3819 return -EBUSY;
3820
3821 err = hermes_read_ltv(hw, USER_BAP, rid, MAX_RID_LEN, &length,
3822 extra);
3823 if (err)
3824 goto out;
3825
3826 data->length = min_t(u16, HERMES_RECLEN_TO_BYTES(length),
3827 MAX_RID_LEN);
3828
3829 out:
3830 orinoco_unlock(priv, &flags);
3831 return err;
3832}
3833
3546/* Spy is used for link quality/strength measurements in Ad-Hoc mode 3834/* Spy is used for link quality/strength measurements in Ad-Hoc mode
3547 * Jean II */ 3835 * Jean II */
3548static int orinoco_ioctl_setspy(struct net_device *dev, struct iw_point *srq) 3836static int orinoco_ioctl_setspy(struct net_device *dev,
3837 struct iw_request_info *info,
3838 struct iw_point *srq,
3839 char *extra)
3840
3549{ 3841{
3550 struct orinoco_private *priv = netdev_priv(dev); 3842 struct orinoco_private *priv = netdev_priv(dev);
3551 struct sockaddr address[IW_MAX_SPY]; 3843 struct sockaddr *address = (struct sockaddr *) extra;
3552 int number = srq->length; 3844 int number = srq->length;
3553 int i; 3845 int i;
3554 int err = 0;
3555 unsigned long flags; 3846 unsigned long flags;
3556 3847
3557 /* Check the number of addresses */
3558 if (number > IW_MAX_SPY)
3559 return -E2BIG;
3560
3561 /* Get the data in the driver */
3562 if (srq->pointer) {
3563 if (copy_from_user(address, srq->pointer,
3564 sizeof(struct sockaddr) * number))
3565 return -EFAULT;
3566 }
3567
3568 /* Make sure nobody mess with the structure while we do */ 3848 /* Make sure nobody mess with the structure while we do */
3569 if (orinoco_lock(priv, &flags) != 0) 3849 if (orinoco_lock(priv, &flags) != 0)
3570 return -EBUSY; 3850 return -EBUSY;
@@ -3588,14 +3868,17 @@ static int orinoco_ioctl_setspy(struct net_device *dev, struct iw_point *srq)
3588 /* Now, let the others play */ 3868 /* Now, let the others play */
3589 orinoco_unlock(priv, &flags); 3869 orinoco_unlock(priv, &flags);
3590 3870
3591 return err; 3871 /* Do NOT call commit handler */
3872 return 0;
3592} 3873}
3593 3874
3594static int orinoco_ioctl_getspy(struct net_device *dev, struct iw_point *srq) 3875static int orinoco_ioctl_getspy(struct net_device *dev,
3876 struct iw_request_info *info,
3877 struct iw_point *srq,
3878 char *extra)
3595{ 3879{
3596 struct orinoco_private *priv = netdev_priv(dev); 3880 struct orinoco_private *priv = netdev_priv(dev);
3597 struct sockaddr address[IW_MAX_SPY]; 3881 struct sockaddr *address = (struct sockaddr *) extra;
3598 struct iw_quality spy_stat[IW_MAX_SPY];
3599 int number; 3882 int number;
3600 int i; 3883 int i;
3601 unsigned long flags; 3884 unsigned long flags;
@@ -3604,7 +3887,12 @@ static int orinoco_ioctl_getspy(struct net_device *dev, struct iw_point *srq)
3604 return -EBUSY; 3887 return -EBUSY;
3605 3888
3606 number = priv->spy_number; 3889 number = priv->spy_number;
3607 if ((number > 0) && (srq->pointer)) { 3890 /* Create address struct */
3891 for (i = 0; i < number; i++) {
3892 memcpy(address[i].sa_data, priv->spy_address[i], ETH_ALEN);
3893 address[i].sa_family = AF_UNIX;
3894 }
3895 if (number > 0) {
3608 /* Create address struct */ 3896 /* Create address struct */
3609 for (i = 0; i < number; i++) { 3897 for (i = 0; i < number; i++) {
3610 memcpy(address[i].sa_data, priv->spy_address[i], 3898 memcpy(address[i].sa_data, priv->spy_address[i],
@@ -3615,344 +3903,503 @@ static int orinoco_ioctl_getspy(struct net_device *dev, struct iw_point *srq)
3615 /* In theory, we should disable irqs while copying the stats 3903 /* In theory, we should disable irqs while copying the stats
3616 * because the rx path might update it in the middle... 3904 * because the rx path might update it in the middle...
3617 * Bah, who care ? - Jean II */ 3905 * Bah, who care ? - Jean II */
3618 memcpy(&spy_stat, priv->spy_stat, 3906 memcpy(extra + (sizeof(struct sockaddr) * number),
3619 sizeof(struct iw_quality) * IW_MAX_SPY); 3907 priv->spy_stat, sizeof(struct iw_quality) * number);
3620 for (i=0; i < number; i++)
3621 priv->spy_stat[i].updated = 0;
3622 } 3908 }
3909 /* Reset updated flags. */
3910 for (i = 0; i < number; i++)
3911 priv->spy_stat[i].updated = 0;
3623 3912
3624 orinoco_unlock(priv, &flags); 3913 orinoco_unlock(priv, &flags);
3625 3914
3626 /* Push stuff to user space */
3627 srq->length = number; 3915 srq->length = number;
3628 if(copy_to_user(srq->pointer, address,
3629 sizeof(struct sockaddr) * number))
3630 return -EFAULT;
3631 if(copy_to_user(srq->pointer + (sizeof(struct sockaddr)*number),
3632 &spy_stat, sizeof(struct iw_quality) * number))
3633 return -EFAULT;
3634 3916
3635 return 0; 3917 return 0;
3636} 3918}
3637 3919
3638static int 3920/* Trigger a scan (look for other cells in the vicinity */
3639orinoco_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3921static int orinoco_ioctl_setscan(struct net_device *dev,
3922 struct iw_request_info *info,
3923 struct iw_param *srq,
3924 char *extra)
3640{ 3925{
3641 struct orinoco_private *priv = netdev_priv(dev); 3926 struct orinoco_private *priv = netdev_priv(dev);
3642 struct iwreq *wrq = (struct iwreq *)rq; 3927 hermes_t *hw = &priv->hw;
3643 int err = 0; 3928 int err = 0;
3644 int tmp;
3645 int changed = 0;
3646 unsigned long flags; 3929 unsigned long flags;
3647 3930
3648 TRACE_ENTER(dev->name); 3931 /* Note : you may have realised that, as this is a SET operation,
3932 * this is priviledged and therefore a normal user can't
3933 * perform scanning.
3934 * This is not an error, while the device perform scanning,
3935 * traffic doesn't flow, so it's a perfect DoS...
3936 * Jean II */
3649 3937
3650 /* In theory, we could allow most of the the SET stuff to be 3938 if (orinoco_lock(priv, &flags) != 0)
3651 * done. In practice, the lapse of time at startup when the 3939 return -EBUSY;
3652 * card is not ready is very short, so why bother... Note
3653 * that netif_device_present is different from up/down
3654 * (ifconfig), when the device is not yet up, it is usually
3655 * already ready... Jean II */
3656 if (! netif_device_present(dev))
3657 return -ENODEV;
3658 3940
3659 switch (cmd) { 3941 /* Scanning with port 0 disabled would fail */
3660 case SIOCGIWNAME: 3942 if (!netif_running(dev)) {
3661 strcpy(wrq->u.name, "IEEE 802.11-DS"); 3943 err = -ENETDOWN;
3662 break; 3944 goto out;
3663 3945 }
3664 case SIOCGIWAP:
3665 wrq->u.ap_addr.sa_family = ARPHRD_ETHER;
3666 err = orinoco_hw_get_bssid(priv, wrq->u.ap_addr.sa_data);
3667 break;
3668 3946
3669 case SIOCGIWRANGE: 3947 /* In monitor mode, the scan results are always empty.
3670 err = orinoco_ioctl_getiwrange(dev, &wrq->u.data); 3948 * Probe responses are passed to the driver as received
3671 break; 3949 * frames and could be processed in software. */
3950 if (priv->iw_mode == IW_MODE_MONITOR) {
3951 err = -EOPNOTSUPP;
3952 goto out;
3953 }
3672 3954
3673 case SIOCSIWMODE: 3955 /* Note : because we don't lock out the irq handler, the way
3674 if (orinoco_lock(priv, &flags) != 0) 3956 * we access scan variables in priv is critical.
3675 return -EBUSY; 3957 * o scan_inprogress : not touched by irq handler
3676 switch (wrq->u.mode) { 3958 * o scan_mode : not touched by irq handler
3677 case IW_MODE_ADHOC: 3959 * o scan_result : irq is strict producer, non-irq is strict
3678 if (! (priv->has_ibss || priv->has_port3) ) 3960 * consumer.
3679 err = -EINVAL; 3961 * o scan_len : synchronised with scan_result
3680 else { 3962 * Before modifying anything on those variables, please think hard !
3681 priv->iw_mode = IW_MODE_ADHOC; 3963 * Jean II */
3682 changed = 1;
3683 }
3684 break;
3685 3964
3686 case IW_MODE_INFRA: 3965 /* If there is still some left-over scan results, get rid of it */
3687 priv->iw_mode = IW_MODE_INFRA; 3966 if (priv->scan_result != NULL) {
3688 changed = 1; 3967 /* What's likely is that a client did crash or was killed
3689 break; 3968 * between triggering the scan request and reading the
3969 * results, so we need to reset everything.
3970 * Some clients that are too slow may suffer from that...
3971 * Jean II */
3972 kfree(priv->scan_result);
3973 priv->scan_result = NULL;
3974 }
3690 3975
3691 default: 3976 /* Save flags */
3692 err = -EINVAL; 3977 priv->scan_mode = srq->flags;
3693 break;
3694 }
3695 set_port_type(priv);
3696 orinoco_unlock(priv, &flags);
3697 break;
3698 3978
3699 case SIOCGIWMODE: 3979 /* Always trigger scanning, even if it's in progress.
3700 if (orinoco_lock(priv, &flags) != 0) 3980 * This way, if the info frame get lost, we will recover somewhat
3701 return -EBUSY; 3981 * gracefully - Jean II */
3702 wrq->u.mode = priv->iw_mode;
3703 orinoco_unlock(priv, &flags);
3704 break;
3705 3982
3706 case SIOCSIWENCODE: 3983 if (priv->has_hostscan) {
3707 err = orinoco_ioctl_setiwencode(dev, &wrq->u.encoding); 3984 switch (priv->firmware_type) {
3708 if (! err) 3985 case FIRMWARE_TYPE_SYMBOL:
3709 changed = 1; 3986 err = hermes_write_wordrec(hw, USER_BAP,
3987 HERMES_RID_CNFHOSTSCAN_SYMBOL,
3988 HERMES_HOSTSCAN_SYMBOL_ONCE |
3989 HERMES_HOSTSCAN_SYMBOL_BCAST);
3990 break;
3991 case FIRMWARE_TYPE_INTERSIL: {
3992 u16 req[3];
3993
3994 req[0] = cpu_to_le16(0x3fff); /* All channels */
3995 req[1] = cpu_to_le16(0x0001); /* rate 1 Mbps */
3996 req[2] = 0; /* Any ESSID */
3997 err = HERMES_WRITE_RECORD(hw, USER_BAP,
3998 HERMES_RID_CNFHOSTSCAN, &req);
3999 }
3710 break; 4000 break;
4001 case FIRMWARE_TYPE_AGERE:
4002 err = hermes_write_wordrec(hw, USER_BAP,
4003 HERMES_RID_CNFSCANSSID_AGERE,
4004 0); /* Any ESSID */
4005 if (err)
4006 break;
3711 4007
3712 case SIOCGIWENCODE: 4008 err = hermes_inquire(hw, HERMES_INQ_SCAN);
3713 if (! capable(CAP_NET_ADMIN)) {
3714 err = -EPERM;
3715 break; 4009 break;
3716 } 4010 }
4011 } else
4012 err = hermes_inquire(hw, HERMES_INQ_SCAN);
3717 4013
3718 err = orinoco_ioctl_getiwencode(dev, &wrq->u.encoding); 4014 /* One more client */
3719 break; 4015 if (! err)
3720 4016 priv->scan_inprogress = 1;
3721 case SIOCSIWESSID:
3722 err = orinoco_ioctl_setessid(dev, &wrq->u.essid);
3723 if (! err)
3724 changed = 1;
3725 break;
3726 4017
3727 case SIOCGIWESSID: 4018 out:
3728 err = orinoco_ioctl_getessid(dev, &wrq->u.essid); 4019 orinoco_unlock(priv, &flags);
3729 break; 4020 return err;
4021}
3730 4022
3731 case SIOCSIWNICKN: 4023/* Translate scan data returned from the card to a card independant
3732 err = orinoco_ioctl_setnick(dev, &wrq->u.data); 4024 * format that the Wireless Tools will understand - Jean II */
3733 if (! err) 4025static inline int orinoco_translate_scan(struct net_device *dev,
3734 changed = 1; 4026 char *buffer,
3735 break; 4027 char *scan,
4028 int scan_len)
4029{
4030 struct orinoco_private *priv = netdev_priv(dev);
4031 int offset; /* In the scan data */
4032 union hermes_scan_info *atom;
4033 int atom_len;
4034 u16 capabilities;
4035 u16 channel;
4036 struct iw_event iwe; /* Temporary buffer */
4037 char * current_ev = buffer;
4038 char * end_buf = buffer + IW_SCAN_MAX_DATA;
3736 4039
3737 case SIOCGIWNICKN: 4040 switch (priv->firmware_type) {
3738 err = orinoco_ioctl_getnick(dev, &wrq->u.data); 4041 case FIRMWARE_TYPE_AGERE:
4042 atom_len = sizeof(struct agere_scan_apinfo);
4043 offset = 0;
3739 break; 4044 break;
3740 4045 case FIRMWARE_TYPE_SYMBOL:
3741 case SIOCGIWFREQ: 4046 /* Lack of documentation necessitates this hack.
3742 tmp = orinoco_hw_get_freq(priv); 4047 * Different firmwares have 68 or 76 byte long atoms.
3743 if (tmp < 0) { 4048 * We try modulo first. If the length divides by both,
3744 err = tmp; 4049 * we check what would be the channel in the second
3745 } else { 4050 * frame for a 68-byte atom. 76-byte atoms have 0 there.
3746 wrq->u.freq.m = tmp; 4051 * Valid channel cannot be 0. */
3747 wrq->u.freq.e = 1; 4052 if (scan_len % 76)
3748 } 4053 atom_len = 68;
4054 else if (scan_len % 68)
4055 atom_len = 76;
4056 else if (scan_len >= 1292 && scan[68] == 0)
4057 atom_len = 76;
4058 else
4059 atom_len = 68;
4060 offset = 0;
3749 break; 4061 break;
3750 4062 case FIRMWARE_TYPE_INTERSIL:
3751 case SIOCSIWFREQ: 4063 offset = 4;
3752 err = orinoco_ioctl_setfreq(dev, &wrq->u.freq); 4064 if (priv->has_hostscan)
3753 if (! err) 4065 atom_len = scan[0] + (scan[1] << 8);
3754 changed = 1; 4066 else
4067 atom_len = offsetof(struct prism2_scan_apinfo, atim);
3755 break; 4068 break;
4069 default:
4070 return 0;
4071 }
3756 4072
3757 case SIOCGIWSENS: 4073 /* Check that we got an whole number of atoms */
3758 err = orinoco_ioctl_getsens(dev, &wrq->u.sens); 4074 if ((scan_len - offset) % atom_len) {
3759 break; 4075 printk(KERN_ERR "%s: Unexpected scan data length %d, "
4076 "atom_len %d, offset %d\n", dev->name, scan_len,
4077 atom_len, offset);
4078 return 0;
4079 }
3760 4080
3761 case SIOCSIWSENS: 4081 /* Read the entries one by one */
3762 err = orinoco_ioctl_setsens(dev, &wrq->u.sens); 4082 for (; offset + atom_len <= scan_len; offset += atom_len) {
3763 if (! err) 4083 /* Get next atom */
3764 changed = 1; 4084 atom = (union hermes_scan_info *) (scan + offset);
3765 break; 4085
4086 /* First entry *MUST* be the AP MAC address */
4087 iwe.cmd = SIOCGIWAP;
4088 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
4089 memcpy(iwe.u.ap_addr.sa_data, atom->a.bssid, ETH_ALEN);
4090 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN);
4091
4092 /* Other entries will be displayed in the order we give them */
4093
4094 /* Add the ESSID */
4095 iwe.u.data.length = le16_to_cpu(atom->a.essid_len);
4096 if (iwe.u.data.length > 32)
4097 iwe.u.data.length = 32;
4098 iwe.cmd = SIOCGIWESSID;
4099 iwe.u.data.flags = 1;
4100 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, atom->a.essid);
4101
4102 /* Add mode */
4103 iwe.cmd = SIOCGIWMODE;
4104 capabilities = le16_to_cpu(atom->a.capabilities);
4105 if (capabilities & 0x3) {
4106 if (capabilities & 0x1)
4107 iwe.u.mode = IW_MODE_MASTER;
4108 else
4109 iwe.u.mode = IW_MODE_ADHOC;
4110 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_UINT_LEN);
4111 }
3766 4112
3767 case SIOCGIWRTS: 4113 channel = atom->s.channel;
3768 wrq->u.rts.value = priv->rts_thresh; 4114 if ( (channel >= 1) && (channel <= NUM_CHANNELS) ) {
3769 wrq->u.rts.disabled = (wrq->u.rts.value == 2347); 4115 /* Add frequency */
3770 wrq->u.rts.fixed = 1; 4116 iwe.cmd = SIOCGIWFREQ;
3771 break; 4117 iwe.u.freq.m = channel_frequency[channel-1] * 100000;
4118 iwe.u.freq.e = 1;
4119 current_ev = iwe_stream_add_event(current_ev, end_buf,
4120 &iwe, IW_EV_FREQ_LEN);
4121 }
3772 4122
3773 case SIOCSIWRTS: 4123 /* Add quality statistics */
3774 err = orinoco_ioctl_setrts(dev, &wrq->u.rts); 4124 iwe.cmd = IWEVQUAL;
3775 if (! err) 4125 iwe.u.qual.updated = 0x10; /* no link quality */
3776 changed = 1; 4126 iwe.u.qual.level = (__u8) le16_to_cpu(atom->a.level) - 0x95;
3777 break; 4127 iwe.u.qual.noise = (__u8) le16_to_cpu(atom->a.noise) - 0x95;
4128 /* Wireless tools prior to 27.pre22 will show link quality
4129 * anyway, so we provide a reasonable value. */
4130 if (iwe.u.qual.level > iwe.u.qual.noise)
4131 iwe.u.qual.qual = iwe.u.qual.level - iwe.u.qual.noise;
4132 else
4133 iwe.u.qual.qual = 0;
4134 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN);
3778 4135
3779 case SIOCSIWFRAG: 4136 /* Add encryption capability */
3780 err = orinoco_ioctl_setfrag(dev, &wrq->u.frag); 4137 iwe.cmd = SIOCGIWENCODE;
3781 if (! err) 4138 if (capabilities & 0x10)
3782 changed = 1; 4139 iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
3783 break; 4140 else
4141 iwe.u.data.flags = IW_ENCODE_DISABLED;
4142 iwe.u.data.length = 0;
4143 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, atom->a.essid);
4144
4145 /* Bit rate is not available in Lucent/Agere firmwares */
4146 if (priv->firmware_type != FIRMWARE_TYPE_AGERE) {
4147 char * current_val = current_ev + IW_EV_LCP_LEN;
4148 int i;
4149 int step;
4150
4151 if (priv->firmware_type == FIRMWARE_TYPE_SYMBOL)
4152 step = 2;
4153 else
4154 step = 1;
4155
4156 iwe.cmd = SIOCGIWRATE;
4157 /* Those two flags are ignored... */
4158 iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
4159 /* Max 10 values */
4160 for (i = 0; i < 10; i += step) {
4161 /* NULL terminated */
4162 if (atom->p.rates[i] == 0x0)
4163 break;
4164 /* Bit rate given in 500 kb/s units (+ 0x80) */
4165 iwe.u.bitrate.value = ((atom->p.rates[i] & 0x7f) * 500000);
4166 current_val = iwe_stream_add_value(current_ev, current_val,
4167 end_buf, &iwe,
4168 IW_EV_PARAM_LEN);
4169 }
4170 /* Check if we added any event */
4171 if ((current_val - current_ev) > IW_EV_LCP_LEN)
4172 current_ev = current_val;
4173 }
3784 4174
3785 case SIOCGIWFRAG: 4175 /* The other data in the scan result are not really
3786 err = orinoco_ioctl_getfrag(dev, &wrq->u.frag); 4176 * interesting, so for now drop it - Jean II */
3787 break; 4177 }
4178 return current_ev - buffer;
4179}
3788 4180
3789 case SIOCSIWRATE: 4181/* Return results of a scan */
3790 err = orinoco_ioctl_setrate(dev, &wrq->u.bitrate); 4182static int orinoco_ioctl_getscan(struct net_device *dev,
3791 if (! err) 4183 struct iw_request_info *info,
3792 changed = 1; 4184 struct iw_point *srq,
3793 break; 4185 char *extra)
4186{
4187 struct orinoco_private *priv = netdev_priv(dev);
4188 int err = 0;
4189 unsigned long flags;
3794 4190
3795 case SIOCGIWRATE: 4191 if (orinoco_lock(priv, &flags) != 0)
3796 err = orinoco_ioctl_getrate(dev, &wrq->u.bitrate); 4192 return -EBUSY;
3797 break;
3798 4193
3799 case SIOCSIWPOWER: 4194 /* If no results yet, ask to try again later */
3800 err = orinoco_ioctl_setpower(dev, &wrq->u.power); 4195 if (priv->scan_result == NULL) {
3801 if (! err) 4196 if (priv->scan_inprogress)
3802 changed = 1; 4197 /* Important note : we don't want to block the caller
3803 break; 4198 * until results are ready for various reasons.
4199 * First, managing wait queues is complex and racy.
4200 * Second, we grab some rtnetlink lock before comming
4201 * here (in dev_ioctl()).
4202 * Third, we generate an Wireless Event, so the
4203 * caller can wait itself on that - Jean II */
4204 err = -EAGAIN;
4205 else
4206 /* Client error, no scan results...
4207 * The caller need to restart the scan. */
4208 err = -ENODATA;
4209 } else {
4210 /* We have some results to push back to user space */
4211
4212 /* Translate to WE format */
4213 srq->length = orinoco_translate_scan(dev, extra,
4214 priv->scan_result,
4215 priv->scan_len);
4216
4217 /* Return flags */
4218 srq->flags = (__u16) priv->scan_mode;
4219
4220 /* Results are here, so scan no longer in progress */
4221 priv->scan_inprogress = 0;
4222
4223 /* In any case, Scan results will be cleaned up in the
4224 * reset function and when exiting the driver.
4225 * The person triggering the scanning may never come to
4226 * pick the results, so we need to do it in those places.
4227 * Jean II */
4228
4229#ifdef SCAN_SINGLE_READ
4230 /* If you enable this option, only one client (the first
4231 * one) will be able to read the result (and only one
4232 * time). If there is multiple concurent clients that
4233 * want to read scan results, this behavior is not
4234 * advisable - Jean II */
4235 kfree(priv->scan_result);
4236 priv->scan_result = NULL;
4237#endif /* SCAN_SINGLE_READ */
4238 /* Here, if too much time has elapsed since last scan,
4239 * we may want to clean up scan results... - Jean II */
4240 }
4241
4242 orinoco_unlock(priv, &flags);
4243 return err;
4244}
3804 4245
3805 case SIOCGIWPOWER: 4246/* Commit handler, called after set operations */
3806 err = orinoco_ioctl_getpower(dev, &wrq->u.power); 4247static int orinoco_ioctl_commit(struct net_device *dev,
3807 break; 4248 struct iw_request_info *info,
4249 void *wrqu,
4250 char *extra)
4251{
4252 struct orinoco_private *priv = netdev_priv(dev);
4253 struct hermes *hw = &priv->hw;
4254 unsigned long flags;
4255 int err = 0;
3808 4256
3809 case SIOCGIWTXPOW: 4257 if (!priv->open)
3810 /* The card only supports one tx power, so this is easy */ 4258 return 0;
3811 wrq->u.txpower.value = 15; /* dBm */
3812 wrq->u.txpower.fixed = 1;
3813 wrq->u.txpower.disabled = 0;
3814 wrq->u.txpower.flags = IW_TXPOW_DBM;
3815 break;
3816 4259
3817 case SIOCSIWRETRY: 4260 if (priv->broken_disableport) {
3818 err = -EOPNOTSUPP; 4261 orinoco_reset(dev);
3819 break; 4262 return 0;
4263 }
3820 4264
3821 case SIOCGIWRETRY: 4265 if (orinoco_lock(priv, &flags) != 0)
3822 err = orinoco_ioctl_getretry(dev, &wrq->u.retry); 4266 return err;
3823 break;
3824 4267
3825 case SIOCSIWSPY: 4268 err = hermes_disable_port(hw, 0);
3826 err = orinoco_ioctl_setspy(dev, &wrq->u.data); 4269 if (err) {
3827 break; 4270 printk(KERN_WARNING "%s: Unable to disable port "
4271 "while reconfiguring card\n", dev->name);
4272 priv->broken_disableport = 1;
4273 goto out;
4274 }
3828 4275
3829 case SIOCGIWSPY: 4276 err = __orinoco_program_rids(dev);
3830 err = orinoco_ioctl_getspy(dev, &wrq->u.data); 4277 if (err) {
3831 break; 4278 printk(KERN_WARNING "%s: Unable to reconfigure card\n",
4279 dev->name);
4280 goto out;
4281 }
3832 4282
3833 case SIOCGIWPRIV: 4283 err = hermes_enable_port(hw, 0);
3834 if (wrq->u.data.pointer) { 4284 if (err) {
3835 struct iw_priv_args privtab[] = { 4285 printk(KERN_WARNING "%s: Unable to enable port while reconfiguring card\n",
3836 { SIOCIWFIRSTPRIV + 0x0, 0, 0, "force_reset" }, 4286 dev->name);
3837 { SIOCIWFIRSTPRIV + 0x1, 0, 0, "card_reset" }, 4287 goto out;
3838 { SIOCIWFIRSTPRIV + 0x2, 4288 }
3839 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3840 0, "set_port3" },
3841 { SIOCIWFIRSTPRIV + 0x3, 0,
3842 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3843 "get_port3" },
3844 { SIOCIWFIRSTPRIV + 0x4,
3845 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3846 0, "set_preamble" },
3847 { SIOCIWFIRSTPRIV + 0x5, 0,
3848 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3849 "get_preamble" },
3850 { SIOCIWFIRSTPRIV + 0x6,
3851 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3852 0, "set_ibssport" },
3853 { SIOCIWFIRSTPRIV + 0x7, 0,
3854 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3855 "get_ibssport" },
3856 };
3857
3858 wrq->u.data.length = sizeof(privtab) / sizeof(privtab[0]);
3859 if (copy_to_user(wrq->u.data.pointer, privtab, sizeof(privtab)))
3860 err = -EFAULT;
3861 }
3862 break;
3863
3864 case SIOCIWFIRSTPRIV + 0x0: /* force_reset */
3865 case SIOCIWFIRSTPRIV + 0x1: /* card_reset */
3866 if (! capable(CAP_NET_ADMIN)) {
3867 err = -EPERM;
3868 break;
3869 }
3870
3871 printk(KERN_DEBUG "%s: Force scheduling reset!\n", dev->name);
3872 4289
4290 out:
4291 if (err) {
4292 printk(KERN_WARNING "%s: Resetting instead...\n", dev->name);
3873 schedule_work(&priv->reset_work); 4293 schedule_work(&priv->reset_work);
3874 break; 4294 err = 0;
3875 4295 }
3876 case SIOCIWFIRSTPRIV + 0x2: /* set_port3 */
3877 if (! capable(CAP_NET_ADMIN)) {
3878 err = -EPERM;
3879 break;
3880 }
3881
3882 err = orinoco_ioctl_setport3(dev, wrq);
3883 if (! err)
3884 changed = 1;
3885 break;
3886 4296
3887 case SIOCIWFIRSTPRIV + 0x3: /* get_port3 */ 4297 orinoco_unlock(priv, &flags);
3888 err = orinoco_ioctl_getport3(dev, wrq); 4298 return err;
3889 break; 4299}
3890 4300
3891 case SIOCIWFIRSTPRIV + 0x4: /* set_preamble */ 4301static const struct iw_priv_args orinoco_privtab[] = {
3892 if (! capable(CAP_NET_ADMIN)) { 4302 { SIOCIWFIRSTPRIV + 0x0, 0, 0, "force_reset" },
3893 err = -EPERM; 4303 { SIOCIWFIRSTPRIV + 0x1, 0, 0, "card_reset" },
3894 break; 4304 { SIOCIWFIRSTPRIV + 0x2, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3895 } 4305 0, "set_port3" },
4306 { SIOCIWFIRSTPRIV + 0x3, 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
4307 "get_port3" },
4308 { SIOCIWFIRSTPRIV + 0x4, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
4309 0, "set_preamble" },
4310 { SIOCIWFIRSTPRIV + 0x5, 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
4311 "get_preamble" },
4312 { SIOCIWFIRSTPRIV + 0x6, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
4313 0, "set_ibssport" },
4314 { SIOCIWFIRSTPRIV + 0x7, 0, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
4315 "get_ibssport" },
4316 { SIOCIWFIRSTPRIV + 0x9, 0, IW_PRIV_TYPE_BYTE | MAX_RID_LEN,
4317 "get_rid" },
4318};
3896 4319
3897 /* 802.11b has recently defined some short preamble.
3898 * Basically, the Phy header has been reduced in size.
3899 * This increase performance, especially at high rates
3900 * (the preamble is transmitted at 1Mb/s), unfortunately
3901 * this give compatibility troubles... - Jean II */
3902 if(priv->has_preamble) {
3903 int val = *( (int *) wrq->u.name );
3904
3905 if (orinoco_lock(priv, &flags) != 0)
3906 return -EBUSY;
3907 if (val)
3908 priv->preamble = 1;
3909 else
3910 priv->preamble = 0;
3911 orinoco_unlock(priv, &flags);
3912 changed = 1;
3913 } else
3914 err = -EOPNOTSUPP;
3915 break;
3916 4320
3917 case SIOCIWFIRSTPRIV + 0x5: /* get_preamble */ 4321/*
3918 if(priv->has_preamble) { 4322 * Structures to export the Wireless Handlers
3919 int *val = (int *)wrq->u.name; 4323 */
3920 4324
3921 if (orinoco_lock(priv, &flags) != 0) 4325static const iw_handler orinoco_handler[] = {
3922 return -EBUSY; 4326 [SIOCSIWCOMMIT-SIOCIWFIRST] (iw_handler) orinoco_ioctl_commit,
3923 *val = priv->preamble; 4327 [SIOCGIWNAME -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getname,
3924 orinoco_unlock(priv, &flags); 4328 [SIOCSIWFREQ -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setfreq,
3925 } else 4329 [SIOCGIWFREQ -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getfreq,
3926 err = -EOPNOTSUPP; 4330 [SIOCSIWMODE -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setmode,
3927 break; 4331 [SIOCGIWMODE -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getmode,
3928 case SIOCIWFIRSTPRIV + 0x6: /* set_ibssport */ 4332 [SIOCSIWSENS -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setsens,
3929 if (! capable(CAP_NET_ADMIN)) { 4333 [SIOCGIWSENS -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getsens,
3930 err = -EPERM; 4334 [SIOCGIWRANGE -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getiwrange,
3931 break; 4335 [SIOCSIWSPY -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setspy,
3932 } 4336 [SIOCGIWSPY -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getspy,
4337 [SIOCSIWAP -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setwap,
4338 [SIOCGIWAP -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getwap,
4339 [SIOCSIWSCAN -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setscan,
4340 [SIOCGIWSCAN -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getscan,
4341 [SIOCSIWESSID -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setessid,
4342 [SIOCGIWESSID -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getessid,
4343 [SIOCSIWNICKN -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setnick,
4344 [SIOCGIWNICKN -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getnick,
4345 [SIOCSIWRATE -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setrate,
4346 [SIOCGIWRATE -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getrate,
4347 [SIOCSIWRTS -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setrts,
4348 [SIOCGIWRTS -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getrts,
4349 [SIOCSIWFRAG -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setfrag,
4350 [SIOCGIWFRAG -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getfrag,
4351 [SIOCGIWRETRY -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getretry,
4352 [SIOCSIWENCODE-SIOCIWFIRST] (iw_handler) orinoco_ioctl_setiwencode,
4353 [SIOCGIWENCODE-SIOCIWFIRST] (iw_handler) orinoco_ioctl_getiwencode,
4354 [SIOCSIWPOWER -SIOCIWFIRST] (iw_handler) orinoco_ioctl_setpower,
4355 [SIOCGIWPOWER -SIOCIWFIRST] (iw_handler) orinoco_ioctl_getpower,
4356};
3933 4357
3934 err = orinoco_ioctl_setibssport(dev, wrq);
3935 if (! err)
3936 changed = 1;
3937 break;
3938 4358
3939 case SIOCIWFIRSTPRIV + 0x7: /* get_ibssport */ 4359/*
3940 err = orinoco_ioctl_getibssport(dev, wrq); 4360 Added typecasting since we no longer use iwreq_data -- Moustafa
3941 break; 4361 */
4362static const iw_handler orinoco_private_handler[] = {
4363 [0] (iw_handler) orinoco_ioctl_reset,
4364 [1] (iw_handler) orinoco_ioctl_reset,
4365 [2] (iw_handler) orinoco_ioctl_setport3,
4366 [3] (iw_handler) orinoco_ioctl_getport3,
4367 [4] (iw_handler) orinoco_ioctl_setpreamble,
4368 [5] (iw_handler) orinoco_ioctl_getpreamble,
4369 [6] (iw_handler) orinoco_ioctl_setibssport,
4370 [7] (iw_handler) orinoco_ioctl_getibssport,
4371 [9] (iw_handler) orinoco_ioctl_getrid,
4372};
3942 4373
3943 default: 4374static const struct iw_handler_def orinoco_handler_def = {
3944 err = -EOPNOTSUPP; 4375 .num_standard = ARRAY_SIZE(orinoco_handler),
3945 } 4376 .num_private = ARRAY_SIZE(orinoco_private_handler),
3946 4377 .num_private_args = ARRAY_SIZE(orinoco_privtab),
3947 if (! err && changed && netif_running(dev)) { 4378 .standard = orinoco_handler,
3948 err = orinoco_reconfigure(dev); 4379 .private = orinoco_private_handler,
3949 } 4380 .private_args = orinoco_privtab,
4381};
3950 4382
3951 TRACE_EXIT(dev->name); 4383static void orinoco_get_drvinfo(struct net_device *dev,
4384 struct ethtool_drvinfo *info)
4385{
4386 struct orinoco_private *priv = netdev_priv(dev);
3952 4387
3953 return err; 4388 strncpy(info->driver, DRIVER_NAME, sizeof(info->driver) - 1);
4389 strncpy(info->version, DRIVER_VERSION, sizeof(info->version) - 1);
4390 strncpy(info->fw_version, priv->fw_name, sizeof(info->fw_version) - 1);
4391 if (dev->class_dev.dev)
4392 strncpy(info->bus_info, dev->class_dev.dev->bus_id,
4393 sizeof(info->bus_info) - 1);
4394 else
4395 snprintf(info->bus_info, sizeof(info->bus_info) - 1,
4396 "PCMCIA %p", priv->hw.iobase);
3954} 4397}
3955 4398
4399static struct ethtool_ops orinoco_ethtool_ops = {
4400 .get_drvinfo = orinoco_get_drvinfo,
4401 .get_link = ethtool_op_get_link,
4402};
3956 4403
3957/********************************************************************/ 4404/********************************************************************/
3958/* Debugging */ 4405/* Debugging */
diff --git a/drivers/net/wireless/orinoco.h b/drivers/net/wireless/orinoco.h
index f749b50d1088..2f213a7103fe 100644
--- a/drivers/net/wireless/orinoco.h
+++ b/drivers/net/wireless/orinoco.h
@@ -7,7 +7,7 @@
7#ifndef _ORINOCO_H 7#ifndef _ORINOCO_H
8#define _ORINOCO_H 8#define _ORINOCO_H
9 9
10#define DRIVER_VERSION "0.14alpha2" 10#define DRIVER_VERSION "0.15rc2"
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/spinlock.h> 13#include <linux/spinlock.h>
@@ -22,6 +22,8 @@
22 22
23#define WIRELESS_SPY // enable iwspy support 23#define WIRELESS_SPY // enable iwspy support
24 24
25#define MAX_SCAN_LEN 4096
26
25#define ORINOCO_MAX_KEY_SIZE 14 27#define ORINOCO_MAX_KEY_SIZE 14
26#define ORINOCO_MAX_KEYS 4 28#define ORINOCO_MAX_KEYS 4
27 29
@@ -30,6 +32,20 @@ struct orinoco_key {
30 char data[ORINOCO_MAX_KEY_SIZE]; 32 char data[ORINOCO_MAX_KEY_SIZE];
31} __attribute__ ((packed)); 33} __attribute__ ((packed));
32 34
35struct header_struct {
36 /* 802.3 */
37 u8 dest[ETH_ALEN];
38 u8 src[ETH_ALEN];
39 u16 len;
40 /* 802.2 */
41 u8 dsap;
42 u8 ssap;
43 u8 ctrl;
44 /* SNAP */
45 u8 oui[3];
46 u16 ethertype;
47} __attribute__ ((packed));
48
33typedef enum { 49typedef enum {
34 FIRMWARE_TYPE_AGERE, 50 FIRMWARE_TYPE_AGERE,
35 FIRMWARE_TYPE_INTERSIL, 51 FIRMWARE_TYPE_INTERSIL,
@@ -48,6 +64,8 @@ struct orinoco_private {
48 /* driver state */ 64 /* driver state */
49 int open; 65 int open;
50 u16 last_linkstatus; 66 u16 last_linkstatus;
67 struct work_struct join_work;
68 struct work_struct wevent_work;
51 69
52 /* Net device stuff */ 70 /* Net device stuff */
53 struct net_device *ndev; 71 struct net_device *ndev;
@@ -74,7 +92,9 @@ struct orinoco_private {
74 unsigned int has_pm:1; 92 unsigned int has_pm:1;
75 unsigned int has_preamble:1; 93 unsigned int has_preamble:1;
76 unsigned int has_sensitivity:1; 94 unsigned int has_sensitivity:1;
95 unsigned int has_hostscan:1;
77 unsigned int broken_disableport:1; 96 unsigned int broken_disableport:1;
97 unsigned int broken_monitor:1;
78 98
79 /* Configuration paramaters */ 99 /* Configuration paramaters */
80 u32 iw_mode; 100 u32 iw_mode;
@@ -84,6 +104,8 @@ struct orinoco_private {
84 int bitratemode; 104 int bitratemode;
85 char nick[IW_ESSID_MAX_SIZE+1]; 105 char nick[IW_ESSID_MAX_SIZE+1];
86 char desired_essid[IW_ESSID_MAX_SIZE+1]; 106 char desired_essid[IW_ESSID_MAX_SIZE+1];
107 char desired_bssid[ETH_ALEN];
108 int bssid_fixed;
87 u16 frag_thresh, mwo_robust; 109 u16 frag_thresh, mwo_robust;
88 u16 channel; 110 u16 channel;
89 u16 ap_density, rts_thresh; 111 u16 ap_density, rts_thresh;
@@ -98,6 +120,12 @@ struct orinoco_private {
98 /* Configuration dependent variables */ 120 /* Configuration dependent variables */
99 int port_type, createibss; 121 int port_type, createibss;
100 int promiscuous, mc_count; 122 int promiscuous, mc_count;
123
124 /* Scanning support */
125 int scan_inprogress; /* Scan pending... */
126 u32 scan_mode; /* Type of scan done */
127 char * scan_result; /* Result of previous scan */
128 int scan_len; /* Lenght of result */
101}; 129};
102 130
103#ifdef ORINOCO_DEBUG 131#ifdef ORINOCO_DEBUG
diff --git a/drivers/net/wireless/prism54/isl_38xx.c b/drivers/net/wireless/prism54/isl_38xx.c
index 4481ec18c5a0..adc7499136dc 100644
--- a/drivers/net/wireless/prism54/isl_38xx.c
+++ b/drivers/net/wireless/prism54/isl_38xx.c
@@ -112,10 +112,10 @@ isl38xx_handle_wakeup(isl38xx_control_block *control_block,
112void 112void
113isl38xx_trigger_device(int asleep, void __iomem *device_base) 113isl38xx_trigger_device(int asleep, void __iomem *device_base)
114{ 114{
115 struct timeval current_time;
116 u32 reg, counter = 0; 115 u32 reg, counter = 0;
117 116
118#if VERBOSE > SHOW_ERROR_MESSAGES 117#if VERBOSE > SHOW_ERROR_MESSAGES
118 struct timeval current_time;
119 DEBUG(SHOW_FUNCTION_CALLS, "isl38xx trigger device\n"); 119 DEBUG(SHOW_FUNCTION_CALLS, "isl38xx trigger device\n");
120#endif 120#endif
121 121
@@ -126,11 +126,11 @@ isl38xx_trigger_device(int asleep, void __iomem *device_base)
126 do_gettimeofday(&current_time); 126 do_gettimeofday(&current_time);
127 DEBUG(SHOW_TRACING, "%08li.%08li Device wakeup triggered\n", 127 DEBUG(SHOW_TRACING, "%08li.%08li Device wakeup triggered\n",
128 current_time.tv_sec, (long)current_time.tv_usec); 128 current_time.tv_sec, (long)current_time.tv_usec);
129#endif
130 129
131 DEBUG(SHOW_TRACING, "%08li.%08li Device register read %08x\n", 130 DEBUG(SHOW_TRACING, "%08li.%08li Device register read %08x\n",
132 current_time.tv_sec, (long)current_time.tv_usec, 131 current_time.tv_sec, (long)current_time.tv_usec,
133 readl(device_base + ISL38XX_CTRL_STAT_REG)); 132 readl(device_base + ISL38XX_CTRL_STAT_REG));
133#endif
134 udelay(ISL38XX_WRITEIO_DELAY); 134 udelay(ISL38XX_WRITEIO_DELAY);
135 135
136 reg = readl(device_base + ISL38XX_INT_IDENT_REG); 136 reg = readl(device_base + ISL38XX_INT_IDENT_REG);
@@ -148,10 +148,12 @@ isl38xx_trigger_device(int asleep, void __iomem *device_base)
148 counter++; 148 counter++;
149 } 149 }
150 150
151#if VERBOSE > SHOW_ERROR_MESSAGES
151 DEBUG(SHOW_TRACING, 152 DEBUG(SHOW_TRACING,
152 "%08li.%08li Device register read %08x\n", 153 "%08li.%08li Device register read %08x\n",
153 current_time.tv_sec, (long)current_time.tv_usec, 154 current_time.tv_sec, (long)current_time.tv_usec,
154 readl(device_base + ISL38XX_CTRL_STAT_REG)); 155 readl(device_base + ISL38XX_CTRL_STAT_REG));
156#endif
155 udelay(ISL38XX_WRITEIO_DELAY); 157 udelay(ISL38XX_WRITEIO_DELAY);
156 158
157#if VERBOSE > SHOW_ERROR_MESSAGES 159#if VERBOSE > SHOW_ERROR_MESSAGES
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 22:01:07 -0500