diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/amd/au1000_eth.c | 149 | ||||
| -rw-r--r-- | drivers/net/irda/au1k_ir.c | 48 |
2 files changed, 183 insertions, 14 deletions
diff --git a/drivers/net/ethernet/amd/au1000_eth.c b/drivers/net/ethernet/amd/au1000_eth.c index a78e4c136959..31c48a7ac2b6 100644 --- a/drivers/net/ethernet/amd/au1000_eth.c +++ b/drivers/net/ethernet/amd/au1000_eth.c | |||
| @@ -89,6 +89,124 @@ MODULE_DESCRIPTION(DRV_DESC); | |||
| 89 | MODULE_LICENSE("GPL"); | 89 | MODULE_LICENSE("GPL"); |
| 90 | MODULE_VERSION(DRV_VERSION); | 90 | MODULE_VERSION(DRV_VERSION); |
| 91 | 91 | ||
| 92 | /* AU1000 MAC registers and bits */ | ||
| 93 | #define MAC_CONTROL 0x0 | ||
| 94 | # define MAC_RX_ENABLE (1 << 2) | ||
| 95 | # define MAC_TX_ENABLE (1 << 3) | ||
| 96 | # define MAC_DEF_CHECK (1 << 5) | ||
| 97 | # define MAC_SET_BL(X) (((X) & 0x3) << 6) | ||
| 98 | # define MAC_AUTO_PAD (1 << 8) | ||
| 99 | # define MAC_DISABLE_RETRY (1 << 10) | ||
| 100 | # define MAC_DISABLE_BCAST (1 << 11) | ||
| 101 | # define MAC_LATE_COL (1 << 12) | ||
| 102 | # define MAC_HASH_MODE (1 << 13) | ||
| 103 | # define MAC_HASH_ONLY (1 << 15) | ||
| 104 | # define MAC_PASS_ALL (1 << 16) | ||
| 105 | # define MAC_INVERSE_FILTER (1 << 17) | ||
| 106 | # define MAC_PROMISCUOUS (1 << 18) | ||
| 107 | # define MAC_PASS_ALL_MULTI (1 << 19) | ||
| 108 | # define MAC_FULL_DUPLEX (1 << 20) | ||
| 109 | # define MAC_NORMAL_MODE 0 | ||
| 110 | # define MAC_INT_LOOPBACK (1 << 21) | ||
| 111 | # define MAC_EXT_LOOPBACK (1 << 22) | ||
| 112 | # define MAC_DISABLE_RX_OWN (1 << 23) | ||
| 113 | # define MAC_BIG_ENDIAN (1 << 30) | ||
| 114 | # define MAC_RX_ALL (1 << 31) | ||
| 115 | #define MAC_ADDRESS_HIGH 0x4 | ||
| 116 | #define MAC_ADDRESS_LOW 0x8 | ||
| 117 | #define MAC_MCAST_HIGH 0xC | ||
| 118 | #define MAC_MCAST_LOW 0x10 | ||
| 119 | #define MAC_MII_CNTRL 0x14 | ||
| 120 | # define MAC_MII_BUSY (1 << 0) | ||
| 121 | # define MAC_MII_READ 0 | ||
| 122 | # define MAC_MII_WRITE (1 << 1) | ||
| 123 | # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) | ||
| 124 | # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) | ||
| 125 | #define MAC_MII_DATA 0x18 | ||
| 126 | #define MAC_FLOW_CNTRL 0x1C | ||
| 127 | # define MAC_FLOW_CNTRL_BUSY (1 << 0) | ||
| 128 | # define MAC_FLOW_CNTRL_ENABLE (1 << 1) | ||
| 129 | # define MAC_PASS_CONTROL (1 << 2) | ||
| 130 | # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) | ||
| 131 | #define MAC_VLAN1_TAG 0x20 | ||
| 132 | #define MAC_VLAN2_TAG 0x24 | ||
| 133 | |||
| 134 | /* Ethernet Controller Enable */ | ||
| 135 | # define MAC_EN_CLOCK_ENABLE (1 << 0) | ||
| 136 | # define MAC_EN_RESET0 (1 << 1) | ||
| 137 | # define MAC_EN_TOSS (0 << 2) | ||
| 138 | # define MAC_EN_CACHEABLE (1 << 3) | ||
| 139 | # define MAC_EN_RESET1 (1 << 4) | ||
| 140 | # define MAC_EN_RESET2 (1 << 5) | ||
| 141 | # define MAC_DMA_RESET (1 << 6) | ||
| 142 | |||
| 143 | /* Ethernet Controller DMA Channels */ | ||
| 144 | /* offsets from MAC_TX_RING_ADDR address */ | ||
| 145 | #define MAC_TX_BUFF0_STATUS 0x0 | ||
| 146 | # define TX_FRAME_ABORTED (1 << 0) | ||
| 147 | # define TX_JAB_TIMEOUT (1 << 1) | ||
| 148 | # define TX_NO_CARRIER (1 << 2) | ||
| 149 | # define TX_LOSS_CARRIER (1 << 3) | ||
| 150 | # define TX_EXC_DEF (1 << 4) | ||
| 151 | # define TX_LATE_COLL_ABORT (1 << 5) | ||
| 152 | # define TX_EXC_COLL (1 << 6) | ||
| 153 | # define TX_UNDERRUN (1 << 7) | ||
| 154 | # define TX_DEFERRED (1 << 8) | ||
| 155 | # define TX_LATE_COLL (1 << 9) | ||
| 156 | # define TX_COLL_CNT_MASK (0xF << 10) | ||
| 157 | # define TX_PKT_RETRY (1 << 31) | ||
| 158 | #define MAC_TX_BUFF0_ADDR 0x4 | ||
| 159 | # define TX_DMA_ENABLE (1 << 0) | ||
| 160 | # define TX_T_DONE (1 << 1) | ||
| 161 | # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | ||
| 162 | #define MAC_TX_BUFF0_LEN 0x8 | ||
| 163 | #define MAC_TX_BUFF1_STATUS 0x10 | ||
| 164 | #define MAC_TX_BUFF1_ADDR 0x14 | ||
| 165 | #define MAC_TX_BUFF1_LEN 0x18 | ||
| 166 | #define MAC_TX_BUFF2_STATUS 0x20 | ||
| 167 | #define MAC_TX_BUFF2_ADDR 0x24 | ||
| 168 | #define MAC_TX_BUFF2_LEN 0x28 | ||
| 169 | #define MAC_TX_BUFF3_STATUS 0x30 | ||
| 170 | #define MAC_TX_BUFF3_ADDR 0x34 | ||
| 171 | #define MAC_TX_BUFF3_LEN 0x38 | ||
| 172 | |||
| 173 | /* offsets from MAC_RX_RING_ADDR */ | ||
| 174 | #define MAC_RX_BUFF0_STATUS 0x0 | ||
| 175 | # define RX_FRAME_LEN_MASK 0x3fff | ||
| 176 | # define RX_WDOG_TIMER (1 << 14) | ||
| 177 | # define RX_RUNT (1 << 15) | ||
| 178 | # define RX_OVERLEN (1 << 16) | ||
| 179 | # define RX_COLL (1 << 17) | ||
| 180 | # define RX_ETHER (1 << 18) | ||
| 181 | # define RX_MII_ERROR (1 << 19) | ||
| 182 | # define RX_DRIBBLING (1 << 20) | ||
| 183 | # define RX_CRC_ERROR (1 << 21) | ||
| 184 | # define RX_VLAN1 (1 << 22) | ||
| 185 | # define RX_VLAN2 (1 << 23) | ||
| 186 | # define RX_LEN_ERROR (1 << 24) | ||
| 187 | # define RX_CNTRL_FRAME (1 << 25) | ||
| 188 | # define RX_U_CNTRL_FRAME (1 << 26) | ||
| 189 | # define RX_MCAST_FRAME (1 << 27) | ||
| 190 | # define RX_BCAST_FRAME (1 << 28) | ||
| 191 | # define RX_FILTER_FAIL (1 << 29) | ||
| 192 | # define RX_PACKET_FILTER (1 << 30) | ||
| 193 | # define RX_MISSED_FRAME (1 << 31) | ||
| 194 | |||
| 195 | # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | ||
| 196 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ | ||
| 197 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | ||
| 198 | #define MAC_RX_BUFF0_ADDR 0x4 | ||
| 199 | # define RX_DMA_ENABLE (1 << 0) | ||
| 200 | # define RX_T_DONE (1 << 1) | ||
| 201 | # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | ||
| 202 | # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) | ||
| 203 | #define MAC_RX_BUFF1_STATUS 0x10 | ||
| 204 | #define MAC_RX_BUFF1_ADDR 0x14 | ||
| 205 | #define MAC_RX_BUFF2_STATUS 0x20 | ||
| 206 | #define MAC_RX_BUFF2_ADDR 0x24 | ||
| 207 | #define MAC_RX_BUFF3_STATUS 0x30 | ||
| 208 | #define MAC_RX_BUFF3_ADDR 0x34 | ||
| 209 | |||
| 92 | /* | 210 | /* |
| 93 | * Theory of operation | 211 | * Theory of operation |
| 94 | * | 212 | * |
| @@ -152,10 +270,12 @@ static void au1000_enable_mac(struct net_device *dev, int force_reset) | |||
| 152 | 270 | ||
| 153 | if (force_reset || (!aup->mac_enabled)) { | 271 | if (force_reset || (!aup->mac_enabled)) { |
| 154 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); | 272 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
| 155 | au_sync_delay(2); | 273 | wmb(); /* drain writebuffer */ |
| 274 | mdelay(2); | ||
| 156 | writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 | 275 | writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
| 157 | | MAC_EN_CLOCK_ENABLE), aup->enable); | 276 | | MAC_EN_CLOCK_ENABLE), aup->enable); |
| 158 | au_sync_delay(2); | 277 | wmb(); /* drain writebuffer */ |
| 278 | mdelay(2); | ||
| 159 | 279 | ||
| 160 | aup->mac_enabled = 1; | 280 | aup->mac_enabled = 1; |
| 161 | } | 281 | } |
| @@ -273,7 +393,8 @@ static void au1000_hard_stop(struct net_device *dev) | |||
| 273 | reg = readl(&aup->mac->control); | 393 | reg = readl(&aup->mac->control); |
| 274 | reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | 394 | reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); |
| 275 | writel(reg, &aup->mac->control); | 395 | writel(reg, &aup->mac->control); |
| 276 | au_sync_delay(10); | 396 | wmb(); /* drain writebuffer */ |
| 397 | mdelay(10); | ||
| 277 | } | 398 | } |
| 278 | 399 | ||
| 279 | static void au1000_enable_rx_tx(struct net_device *dev) | 400 | static void au1000_enable_rx_tx(struct net_device *dev) |
| @@ -286,7 +407,8 @@ static void au1000_enable_rx_tx(struct net_device *dev) | |||
| 286 | reg = readl(&aup->mac->control); | 407 | reg = readl(&aup->mac->control); |
| 287 | reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | 408 | reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); |
| 288 | writel(reg, &aup->mac->control); | 409 | writel(reg, &aup->mac->control); |
| 289 | au_sync_delay(10); | 410 | wmb(); /* drain writebuffer */ |
| 411 | mdelay(10); | ||
| 290 | } | 412 | } |
| 291 | 413 | ||
| 292 | static void | 414 | static void |
| @@ -336,7 +458,8 @@ au1000_adjust_link(struct net_device *dev) | |||
| 336 | reg |= MAC_DISABLE_RX_OWN; | 458 | reg |= MAC_DISABLE_RX_OWN; |
| 337 | } | 459 | } |
| 338 | writel(reg, &aup->mac->control); | 460 | writel(reg, &aup->mac->control); |
| 339 | au_sync_delay(1); | 461 | wmb(); /* drain writebuffer */ |
| 462 | mdelay(1); | ||
| 340 | 463 | ||
| 341 | au1000_enable_rx_tx(dev); | 464 | au1000_enable_rx_tx(dev); |
| 342 | aup->old_duplex = phydev->duplex; | 465 | aup->old_duplex = phydev->duplex; |
| @@ -500,9 +623,11 @@ static void au1000_reset_mac_unlocked(struct net_device *dev) | |||
| 500 | au1000_hard_stop(dev); | 623 | au1000_hard_stop(dev); |
| 501 | 624 | ||
| 502 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); | 625 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
| 503 | au_sync_delay(2); | 626 | wmb(); /* drain writebuffer */ |
| 627 | mdelay(2); | ||
| 504 | writel(0, aup->enable); | 628 | writel(0, aup->enable); |
| 505 | au_sync_delay(2); | 629 | wmb(); /* drain writebuffer */ |
| 630 | mdelay(2); | ||
| 506 | 631 | ||
| 507 | aup->tx_full = 0; | 632 | aup->tx_full = 0; |
| 508 | for (i = 0; i < NUM_RX_DMA; i++) { | 633 | for (i = 0; i < NUM_RX_DMA; i++) { |
| @@ -652,7 +777,7 @@ static int au1000_init(struct net_device *dev) | |||
| 652 | for (i = 0; i < NUM_RX_DMA; i++) | 777 | for (i = 0; i < NUM_RX_DMA; i++) |
| 653 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; | 778 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; |
| 654 | 779 | ||
| 655 | au_sync(); | 780 | wmb(); /* drain writebuffer */ |
| 656 | 781 | ||
| 657 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; | 782 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
| 658 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | 783 | #ifndef CONFIG_CPU_LITTLE_ENDIAN |
| @@ -669,7 +794,7 @@ static int au1000_init(struct net_device *dev) | |||
| 669 | 794 | ||
| 670 | writel(control, &aup->mac->control); | 795 | writel(control, &aup->mac->control); |
| 671 | writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ | 796 | writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ |
| 672 | au_sync(); | 797 | wmb(); /* drain writebuffer */ |
| 673 | 798 | ||
| 674 | spin_unlock_irqrestore(&aup->lock, flags); | 799 | spin_unlock_irqrestore(&aup->lock, flags); |
| 675 | return 0; | 800 | return 0; |
| @@ -760,7 +885,7 @@ static int au1000_rx(struct net_device *dev) | |||
| 760 | } | 885 | } |
| 761 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | 886 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); |
| 762 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | 887 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); |
| 763 | au_sync(); | 888 | wmb(); /* drain writebuffer */ |
| 764 | 889 | ||
| 765 | /* next descriptor */ | 890 | /* next descriptor */ |
| 766 | prxd = aup->rx_dma_ring[aup->rx_head]; | 891 | prxd = aup->rx_dma_ring[aup->rx_head]; |
| @@ -808,7 +933,7 @@ static void au1000_tx_ack(struct net_device *dev) | |||
| 808 | au1000_update_tx_stats(dev, ptxd->status); | 933 | au1000_update_tx_stats(dev, ptxd->status); |
| 809 | ptxd->buff_stat &= ~TX_T_DONE; | 934 | ptxd->buff_stat &= ~TX_T_DONE; |
| 810 | ptxd->len = 0; | 935 | ptxd->len = 0; |
| 811 | au_sync(); | 936 | wmb(); /* drain writebuffer */ |
| 812 | 937 | ||
| 813 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); | 938 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
| 814 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | 939 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
| @@ -939,7 +1064,7 @@ static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) | |||
| 939 | ps->tx_bytes += ptxd->len; | 1064 | ps->tx_bytes += ptxd->len; |
| 940 | 1065 | ||
| 941 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; | 1066 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
| 942 | au_sync(); | 1067 | wmb(); /* drain writebuffer */ |
| 943 | dev_kfree_skb(skb); | 1068 | dev_kfree_skb(skb); |
| 944 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | 1069 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); |
| 945 | return NETDEV_TX_OK; | 1070 | return NETDEV_TX_OK; |
diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index 5f91e3e01c04..aab2cf72d025 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ | 19 | */ |
| 20 | 20 | ||
| 21 | #include <linux/clk.h> | ||
| 21 | #include <linux/module.h> | 22 | #include <linux/module.h> |
| 22 | #include <linux/netdevice.h> | 23 | #include <linux/netdevice.h> |
| 23 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
| @@ -175,6 +176,7 @@ struct au1k_private { | |||
| 175 | 176 | ||
| 176 | struct resource *ioarea; | 177 | struct resource *ioarea; |
| 177 | struct au1k_irda_platform_data *platdata; | 178 | struct au1k_irda_platform_data *platdata; |
| 179 | struct clk *irda_clk; | ||
| 178 | }; | 180 | }; |
| 179 | 181 | ||
| 180 | static int qos_mtt_bits = 0x07; /* 1 ms or more */ | 182 | static int qos_mtt_bits = 0x07; /* 1 ms or more */ |
| @@ -514,9 +516,39 @@ static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) | |||
| 514 | static int au1k_init(struct net_device *dev) | 516 | static int au1k_init(struct net_device *dev) |
| 515 | { | 517 | { |
| 516 | struct au1k_private *aup = netdev_priv(dev); | 518 | struct au1k_private *aup = netdev_priv(dev); |
| 517 | u32 enable, ring_address; | 519 | u32 enable, ring_address, phyck; |
| 520 | struct clk *c; | ||
| 518 | int i; | 521 | int i; |
| 519 | 522 | ||
| 523 | c = clk_get(NULL, "irda_clk"); | ||
| 524 | if (IS_ERR(c)) | ||
| 525 | return PTR_ERR(c); | ||
| 526 | i = clk_prepare_enable(c); | ||
| 527 | if (i) { | ||
| 528 | clk_put(c); | ||
| 529 | return i; | ||
| 530 | } | ||
| 531 | |||
| 532 | switch (clk_get_rate(c)) { | ||
| 533 | case 40000000: | ||
| 534 | phyck = IR_PHYCLK_40MHZ; | ||
| 535 | break; | ||
| 536 | case 48000000: | ||
| 537 | phyck = IR_PHYCLK_48MHZ; | ||
| 538 | break; | ||
| 539 | case 56000000: | ||
| 540 | phyck = IR_PHYCLK_56MHZ; | ||
| 541 | break; | ||
| 542 | case 64000000: | ||
| 543 | phyck = IR_PHYCLK_64MHZ; | ||
| 544 | break; | ||
| 545 | default: | ||
| 546 | clk_disable_unprepare(c); | ||
| 547 | clk_put(c); | ||
| 548 | return -EINVAL; | ||
| 549 | } | ||
| 550 | aup->irda_clk = c; | ||
| 551 | |||
| 520 | enable = IR_HC | IR_CE | IR_C; | 552 | enable = IR_HC | IR_CE | IR_C; |
| 521 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | 553 | #ifndef CONFIG_CPU_LITTLE_ENDIAN |
| 522 | enable |= IR_BE; | 554 | enable |= IR_BE; |
| @@ -545,7 +577,7 @@ static int au1k_init(struct net_device *dev) | |||
| 545 | irda_write(aup, IR_RING_SIZE, | 577 | irda_write(aup, IR_RING_SIZE, |
| 546 | (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12)); | 578 | (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12)); |
| 547 | 579 | ||
| 548 | irda_write(aup, IR_CONFIG_2, IR_PHYCLK_48MHZ | IR_ONE_PIN); | 580 | irda_write(aup, IR_CONFIG_2, phyck | IR_ONE_PIN); |
| 549 | irda_write(aup, IR_RING_ADDR_CMPR, 0); | 581 | irda_write(aup, IR_RING_ADDR_CMPR, 0); |
| 550 | 582 | ||
| 551 | au1k_irda_set_speed(dev, 9600); | 583 | au1k_irda_set_speed(dev, 9600); |
| @@ -619,6 +651,9 @@ static int au1k_irda_stop(struct net_device *dev) | |||
| 619 | free_irq(aup->irq_tx, dev); | 651 | free_irq(aup->irq_tx, dev); |
| 620 | free_irq(aup->irq_rx, dev); | 652 | free_irq(aup->irq_rx, dev); |
| 621 | 653 | ||
| 654 | clk_disable_unprepare(aup->irda_clk); | ||
| 655 | clk_put(aup->irda_clk); | ||
| 656 | |||
| 622 | return 0; | 657 | return 0; |
| 623 | } | 658 | } |
| 624 | 659 | ||
| @@ -853,6 +888,7 @@ static int au1k_irda_probe(struct platform_device *pdev) | |||
| 853 | struct au1k_private *aup; | 888 | struct au1k_private *aup; |
| 854 | struct net_device *dev; | 889 | struct net_device *dev; |
| 855 | struct resource *r; | 890 | struct resource *r; |
| 891 | struct clk *c; | ||
| 856 | int err; | 892 | int err; |
| 857 | 893 | ||
| 858 | dev = alloc_irdadev(sizeof(struct au1k_private)); | 894 | dev = alloc_irdadev(sizeof(struct au1k_private)); |
| @@ -886,6 +922,14 @@ static int au1k_irda_probe(struct platform_device *pdev) | |||
| 886 | if (!aup->ioarea) | 922 | if (!aup->ioarea) |
| 887 | goto out; | 923 | goto out; |
| 888 | 924 | ||
| 925 | /* bail out early if clock doesn't exist */ | ||
| 926 | c = clk_get(NULL, "irda_clk"); | ||
| 927 | if (IS_ERR(c)) { | ||
| 928 | err = PTR_ERR(c); | ||
| 929 | goto out; | ||
| 930 | } | ||
| 931 | clk_put(c); | ||
| 932 | |||
| 889 | aup->iobase = ioremap_nocache(r->start, resource_size(r)); | 933 | aup->iobase = ioremap_nocache(r->start, resource_size(r)); |
| 890 | if (!aup->iobase) | 934 | if (!aup->iobase) |
| 891 | goto out2; | 935 | goto out2; |
